diff --git a/bsp/es32f0654/drivers/drv_pm.c b/bsp/es32f0654/drivers/drv_pm.c deleted file mode 100644 index aa2f07ec68a101a94d15ecec51908d4c9ffbe2ad..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/drivers/drv_pm.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-04-01 wangyq the first version - * 2019-05-06 Zero-Free adapt to the new power management interface - */ - -#include -#include -#include "board.h" -#include "drv_pm.h" -#include - -#ifdef RT_USING_PM - -static void _drv_pm_enter(struct rt_pm *pm, uint8_t mode) -{ - switch (mode) - { - case PM_SLEEP_MODE_NONE: - break; - - case PM_SLEEP_MODE_IDLE: - __WFI(); - break; - - case PM_SLEEP_MODE_LIGHT: - break; - - case PM_SLEEP_MODE_DEEP: - pmu_stop2_enter(); - break; - - case PM_SLEEP_MODE_STANDBY: - pmu_standby_enter(PMU_STANDBY_PORT_NONE); - break; - - case PM_SLEEP_MODE_SHUTDOWN: - break; - - default: - RT_ASSERT(0); - break; - } -} - -static int drv_hw_pm_init(void) -{ - static const struct rt_pm_ops _ops = - { - _drv_pm_enter, - RT_NULL, - RT_NULL, - RT_NULL, - RT_NULL - }; - - rt_uint8_t timer_mask = 0; - - /* initialize timer mask(no need tickless) */ - timer_mask = 1UL << PM_SLEEP_MODE_DEEP; - - /* initialize system pm module */ - rt_system_pm_init(&_ops, timer_mask, RT_NULL); - - return 0; -} -INIT_BOARD_EXPORT(drv_hw_pm_init); - -#endif diff --git a/bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf deleted file mode 100644 index b374366930b2d1b5689ff5044caba49eace6aa68..0000000000000000000000000000000000000000 Binary files a/bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf and /dev/null differ diff --git a/bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf 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\fs18\loch\af1\hich\af1\dbch\af1\insrsid11754636 -\hich\af1\dbch\af1\loch\f1 NUMPAGES}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \fs18\lang1024\langfe1024\loch\af1\hich\af1\dbch\af1\noproof\insrsid9508363 \hich\af1\dbch\af1\loch\f1 4}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 -\ltrch\fcs0 \fs18\loch\af1\hich\af1\dbch\af1\insrsid11754636 \cell \cell }\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \fs18\loch\af1\hich\af1\dbch\af1\insrsid11754636 -\trowd \irow0\irowband0\lastrow \ltrrow\ts11\trgaph108\trrh240\trleft-108\trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind0\tblindtype3 \clvertalt\clbrdrt\brdrtbl \clbrdrl\brdrtbl \clbrdrb\brdrtbl \clbrdrr\brdrtbl -\cltxlrtb\clftsWidth3\clwWidth4513\clshdrawnil \cellx4405\clvertalt\clbrdrt\brdrtbl \clbrdrl\brdrtbl \clbrdrb\brdrtbl \clbrdrr\brdrtbl \cltxlrtb\clftsWidth3\clwWidth4513\clshdrawnil \cellx8918\row }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1 -\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 -\par }}{\*\pnseclvl1\pnucrm\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl2\pnucltr\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl3\pndec\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl4\pnlcltr\pnstart1\pnindent720\pnhang {\pntxta )}} -{\*\pnseclvl5\pndec\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl6\pnlcltr\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl7\pnlcrm\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl8 -\pnlcltr\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl9\pnlcrm\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}\pard\plain \ltrpar\qj \li0\ri0\sa240\widctlpar -\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 -\fs22\lang2057\langfe1033\loch\af37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 END USER LICENCE AGREEMENT FOR THE }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD (CMSIS) DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -\par THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 -SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE CMSIS }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 . ARM IS ONLY WILLING TO LICENSE THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING OR OTHERWISE USING OR COPYING THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -YOU INDICATE THAT YOU AGREE TO BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 OF }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 AND YOU MAY NOT INSTALL, USE OR COPY THE }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93 -CMSIS Deliverables\'94 means the following components: (i) CMSIS-CORE; (ii) CMSIS-DRIVER; (iii) CMSIS-DSP; (iv) CMSIS-PACK; (v) CMSIS-RTOS API; and (vi) CMSIS-SVD . -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-CORE -\'94 means the specification defining the application programming interface, naming and coding conventions for the Cortex-M processor cores. -\par \'94}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 CMSIS-DRIVER}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 -\insrsid11754636 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 means the specification defining }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\hich\af1\dbch\af37\loch\f1 a generic}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 p}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 eripheral }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 d}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 river application programming interface, naming and coding conventions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 . -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-DSP\'94 - means the digital signal process (DSP) library specification defining the application programming interface of a DSP library implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15023647 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 CMSIS-PACK}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 -\insrsid11754636\charrsid13240697 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 means the specification defining a software pack file format}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 , verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 and the associated XML schema file}{\rtlch\fcs1 -\af0 \ltrch\fcs0 \insrsid11754636\charrsid13240697 .}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-RTOS API\'94 means the - real-time operating system (RTOS) specification defining a generic application programming interface layer for a RTOS system}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15023647 .}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 -Notwithstanding the foregoing, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4730869 \hich\af1\dbch\af37\loch\f1 the CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4730869 \hich\af1\dbch\af37\loch\f1 shall not}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 include}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 (i) the implementation of other published specification -\hich\af1\dbch\af37\loch\f1 s }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 referenced }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 in th}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 -; (ii) any enabling technologies that may be necessary to make or use any product or portion thereof that }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 complies with the }{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 , but are not themselves expressly set forth in the }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 (e.\hich\af1\dbch\af37\loch\f1 -g. compiler front ends, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hardware; applications, operating system or driver software; RISC architecture; processor microarchitecture) -\hich\af1\dbch\af37\loch\f1 ;\hich\af1\dbch\af37\loch\f1 (iii) maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 -\hich\af1\dbch\af37\loch\f1 level representations of integrated circuit designs.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-SVD\'94 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid9306407 means }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 the specification defining the System View Description (SVD), verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636\charrsid9306407 and associated XML}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636 schema}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636\charrsid9306407 files. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid9306407 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93Separate Files\'94 means the components in }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid10227990 the CMSIS reference implementation identified}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 - in the Schedule that demonstrate the usage of the CMSIS-CORE, CMSIS-DRIVER, CMSIS-DSP, CMSIS-PACK and CMSIS-RTOS API, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid3618484 for microprocessors -or device specific software applications that are for use with microprocessors.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 1. LICENCE GRANTS. -\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES -\par -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable }{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 licence, to use and copy the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS D}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 for the purpose of: }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar -\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 (i) subject to clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 , developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 ; and -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 (ii) distributing and having distributed (directly or through your customers and authorised distributors) the CMSIS-D}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 unmodified, with the products}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 you have developed under }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Clause 1.1 (i) }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 provided you preserve any copyright notices which are included with the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 . -\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 1.2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 CONDITIONS ON REDISTRIBUTION}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 -\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 -If you distribute (directly or through your customers and authorised distributors) the products you have created pursuant to Clauses 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (i) you agree: (a) not to use ARM\hich\f1 \rquote \loch\f1 s name\hich\af1\dbch\af37\loch\f1 -, logo or trademarks to market any or all of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1928237 products created under Clause 1.1 (i); }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (b) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 to }{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 pr}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 serve any copyright notices included in the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 -\hich\af1\dbch\af37\loch\f1 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 -\hich\af1\dbch\af37\loch\f1 ; and (c) to ensure your customers and authorised distributors comply with this Clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 2}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 2. RESTRICTIONS ON USE OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 - CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 -\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 PERMITTED USERS: The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 shall be used only by you (either a single individual, or single legal entity) your employees, or by your }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 on-site }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -bona fide sub-contractors for whose acts and omissions you hereby agree to be responsible to ARM}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 for}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 to the same extent as }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 you are for }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 your employees, and provided always that such sub-contractors}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 :}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 (i) are contractually obligated to use the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 only for your benefit}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -;}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 and (i}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 i}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 ) agree to assign all their work product and any rights they create therein in the supply of such work to you. -\par COPYRIGHT AND RESERVATION OF RIGHTS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 : The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 - are owned by ARM or its licensors and are protected by copyright and other intellectual property laws and international treaties. The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the }{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 - or any intellectual property therein. In no event shall the licences granted herein be construed as granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 3}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . SUPPORT. -\par ARM is not obligated to support the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables but}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 may do so entirely at ARM's discretion. -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 4}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 NO }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 WARRANT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Y.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -\par YOU AGREE THAT THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES ARE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 - LICENSED "AS IS", AND THAT ARM EXPRESSLY DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARR -ANTIES OF NON-INFRINGEMENT, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 THE CMSIS DELIVERABLES MAY CONTAIN ERRORS. }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 5}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . LIMITATION OF LIABILITY. -\par THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS LICENCE SHALL NOT EXCEED }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 THE GREATER OF (I) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -THE TOTAL OF SUMS PAID BY YOU TO ARM (IF ANY) FOR THIS LICENCE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 AND (II) US$10.00}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN THIS LICEN -CE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW. -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 6 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 \hich\af1\dbch\af37\loch\f1 . THIRD PARTY RIGHTS.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13830602 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 \hich\af1\dbch\af37\loch\f1 -The Separate Files are delivered subject to and your use is governed by their own separate licence agreements. This Licence does not apply to such Separate Files and the\hich\af1\dbch\af37\loch\f1 \hich\f1 y are not included in the term \'93}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 -\loch\af1\dbch\af37\hich\f1 \'94\loch\f1 \hich\f1 under this Licence. You agree to comply with all terms and conditions imposed on you in respect of such Separate Files including those identified in the Schedule (\'93\loch\f1 \hich\f1 Third Party Terms -\'94\loch\f1 ). -\par \hich\af1\dbch\af37\loch\f1 ARM HEREBY DISCLA\hich\af1\dbch\af37\loch\f1 \hich\f1 -IMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY \'93\loch\f1 \hich\f1 -OTHER CODE\'94\loch\f1 ), AND THE USE OF\hich\af1\dbch\af37\loch\f1 \hich\af1\dbch\af37\loch\f1 -ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE. -\par \hich\af1\dbch\af37\loch\f1 NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, \hich\af1\dbch\af37\loch\f1 -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EX -\hich\af1\dbch\af37\loch\f1 E\hich\af1\dbch\af37\loch\f1 RCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENCE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 7}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . U.S. GOVERNMENT END USERS. -\par US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this commercial product and accompanying documentation is restricted in accordance with the terms of this Licence. -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . TERM AND TERMINATION. -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8.1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -This Licence shall remain in force until terminated }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 in accordance with the terms of Clause 8.2 or Clause 8.3 below}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par 8.2 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this Licence then ARM may terminate this Licence immediately upon giving written notice to you}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid7630822 . You may terminate this Licence at any time. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 -8.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you asserts any patents against ARM, ARM affiliates, third parties who have a valid licence fro\hich\af1\dbch\af37\loch\f1 -m ARM for the CMSIS Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate) patent is Necessary to implement the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 . In this Licence}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 (i) "affiliate" means any entity controlling, contr\hich\af1\dbch\af37\loch\f1 -olled by or under common control with a party (in fact or in law, via voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert" means to allege infringement in legal or administrative proceedings, o -\hich\af1\dbch\af37\loch\f1 r\hich\af1\dbch\af37\loch\f1 proceedings before any other competent trade, arbitral or international authority; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 \hich\f1 (iii) \'93\loch\f1 \hich\f1 Necessary\'94\loch\f1 - means with respect to any claims of any patent, those claims which, without the appropriate permission of the patent owner, will be infringed when imp\hich\af1\dbch\af37\loch\f1 lementing the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 -because no alternative, commercially reasonable, non-infringing way of implementing the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 is known.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid5900444 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8.4 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid7630822 Upon termination of this Licence,}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 you shall stop }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 -using the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 - and destroy all copies of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 in your possession. The provisions of clauses 5, 6, 7, 8 and 9 shall survive termination of this Licence.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 9}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . GENERAL. -\par This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by you and ARM, this is the only agreement between you and ARM relating to the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 - and it may only be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence may not be modified by purchase orders, ad -vertising or other representation by any person. If any clause or sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisions of this Licence shall not be affected thereby. The failure by ARM to enforce any o -f the provisions of this Licence, unless waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of this Licence in the future.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 This Licence may not be assigned without the prior written consent of ARM. -\par }\pard \ltrpar\qc \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \page SCHEDULE -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Separate Files -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 The }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 package }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 also }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 includes the components}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 contained in the following directories}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (a)\tab}}\pard \ltrpar -\qj \fi-360\li720\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\ls16\adjustright\rin0\lin720\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 -\hich\af1\dbch\af37\loch\f1 DSP_Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 -DSP Library sources and examples}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; -\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (b)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 -\hich\af1\dbch\af37\loch\f1 Include}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - Header files; -\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (c)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 -\hich\af1\dbch\af37\loch\f1 Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 -DSP Library build for various toolchains}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; -\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (d)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 -\hich\af1\dbch\af37\loch\f1 RTOS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 -Header file template for CMSIS-RTOS implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; and -\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (e)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 .}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /Device - T}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid14488502 \hich\af1\dbch\af37\loch\f1 emplate files and implementations for Cortex-M class processors}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 . -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par \hich\af1\dbch\af37\loch\f1 All of the above components (a\hich\f1 \endash \loch\f1 e) are licensed to you under the terms of the BSD licence, which is incorp\hich\af1\dbch\af37\loch\f1 orated within or alongside the above components. -\par }\pard \ltrpar\qj \li284\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin284\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\insrsid11754636\charrsid13975144 \hich\af1\dbch\af37\loch\f1 (f)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13975144 -\hich\af1\dbch\af37\loch\f1 ./CMSIS/Driver \hich\f1 \endash \loch\f1 CMSIS-Driver header files}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13975144 \hich\af1\dbch\af37\loch\f1 (g)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 -\hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ./CMSIS/Pack \hich\f1 \endash \loch\f1 Example Device Family Pack}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636\charrsid13975144 - -\par }\pard\plain \ltrpar\s32\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \rtlch\fcs1 \af0\afs21\alang1025 \ltrch\fcs0 \f39\fs21\lang2057\langfe1033\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par The above components (f \endash g) are licensed to you under the terms of the zlib licence, which is incorporated within or alongside the above components. -\par -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid14488502 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par -\par -\par }\pard\plain \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 -\fs22\lang2057\langfe1033\loch\af37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 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-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000105000000000000}} \ No newline at end of file diff --git a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h b/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h deleted file mode 100644 index 07ca77b338dcb29fe2f2ca80840169db4d92bfe3..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h +++ /dev/null @@ -1,6665 +0,0 @@ -/** - ********************************************************************************* - * - * @file es32f065x.h - * @brief ES32F065x Device Head File - * - * @version V1.0 - * @date 07 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ES32F0XX_H__ -#define __ES32F0XX_H__ - - -#define __I volatile const /* defines 'read only' permissions */ -#define __O volatile /* defines 'write only' permissions */ -#define __IO volatile /* defines 'read / write' permissions */ - -#define __NVIC_PRIO_BITS 2 - -typedef enum IRQn { - /* Cortex-M0 processor cxceptions index */ - Reset_IRQn = -15, - NMI_IRQn = -14, - HardFault_IRQn = -13, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - - /* es32f0xx specific interrupt index */ - WWDG_IWDG_IRQn = 0, - LVD_IRQn = 1, - RTC_TEMP_IRQn = 2, - CRYPT_TRNG_IRQn = 3, - CMU_IRQn = 4, - EXTI0_3_IRQn = 5, - EXTI4_7_IRQn = 6, - EXTI8_11_IRQn = 7, - EXTI12_15_IRQn = 8, - DMA_IRQn = 9, - CAN0_IRQn = 10, - LPTIM0_SPI2_IRQn = 11, - ADC_ACMP_IRQn = 12, - AD16C4T0_BRK_UP_TRIG_COM_IRQn = 13, - AD16C4T0_CC_IRQn = 14, - BS16T0_IRQn = 15, - GP16C2T0_IRQn = 17, - GP16C2T1_IRQn = 18, - BS16T1_UART2_IRQn = 19, - BS16T2_UART3_IRQn = 20, - GP16C4T0_LCD_IRQn = 21, - BS16T3_DAC0_IRQn = 22, - I2C0_IRQn = 23, - I2C1_IRQn = 24, - SPI0_IRQn = 25, - SPI1_IRQn = 26, - UART0_IRQn = 27, - UART1_IRQn = 28, - USART0_IRQn = 29, - USART1_IRQn = 30, - LPUART0_IRQn = 31, -} IRQn_Type; - - -#include -#include "core_cm0.h" - -#if defined (__CC_ARM) -#pragma anon_unions -#endif - -/* Peripheral register define */ - -/****************** Bit definition for SYSCFG_PROT register ************************/ - -#define SYSCFG_PROT_KEY_POSS 1U -#define SYSCFG_PROT_KEY_POSE 31U -#define SYSCFG_PROT_KEY_MSK BITS(SYSCFG_PROT_KEY_POSS,SYSCFG_PROT_KEY_POSE) - -#define SYSCFG_PROT_PROT_POS 0U -#define SYSCFG_PROT_PROT_MSK BIT(SYSCFG_PROT_PROT_POS) - -/****************** Bit definition for SYSCFG_MEMRMP register ************************/ - -#define SYSCFG_MEMRMP_VTOEN_POS 16U -#define SYSCFG_MEMRMP_VTOEN_MSK BIT(SYSCFG_MEMRMP_VTOEN_POS) - -#define SYSCFG_MEMRMP_BFRMPEN_POS 8U -#define SYSCFG_MEMRMP_BFRMPEN_MSK BIT(SYSCFG_MEMRMP_BFRMPEN_POS) - -#define SYSCFG_MEMRMP_BRRMPEN_POS 0U -#define SYSCFG_MEMRMP_BRRMPEN_MSK BIT(SYSCFG_MEMRMP_BRRMPEN_POS) - -/****************** Bit definition for SYSCFG_VTOR register ************************/ - -#define SYSCFG_VTOR_VTO_POSS 0U -#define SYSCFG_VTOR_VTO_POSE 29U -#define SYSCFG_VTOR_VTO_MSK BITS(SYSCFG_VTOR_VTO_POSS,SYSCFG_VTOR_VTO_POSE) - -typedef struct -{ - __IO uint32_t PROT; - __IO uint32_t MEMRMP; - __IO uint32_t VTOR; -} SYSCFG_TypeDef; - -/****************** Bit definition for MSC_FLASHKEY register ************************/ - -#define MSC_FLASHKEY_STATUS_POSS 0U -#define MSC_FLASHKEY_STATUS_POSE 1U -#define MSC_FLASHKEY_STATUS_MSK BITS(MSC_FLASHKEY_STATUS_POSS,MSC_FLASHKEY_STATUS_POSE) - -/****************** Bit definition for MSC_INFOKEY register ************************/ - -#define MSC_INFOKEY_STATUS_POSS 0U -#define MSC_INFOKEY_STATUS_POSE 1U -#define MSC_INFOKEY_STATUS_MSK BITS(MSC_INFOKEY_STATUS_POSS,MSC_INFOKEY_STATUS_POSE) - -/****************** Bit definition for MSC_FLASHADDR register ************************/ - -#define MSC_FLASHADDR_IFREN_POS 18U -#define MSC_FLASHADDR_IFREN_MSK BIT(MSC_FLASHADDR_IFREN_POS) - -#define MSC_FLASHADDR_ADDR_POSS 0U -#define MSC_FLASHADDR_ADDR_POSE 17U -#define MSC_FLASHADDR_ADDR_MSK BITS(MSC_FLASHADDR_ADDR_POSS,MSC_FLASHADDR_ADDR_POSE) - -/****************** Bit definition for MSC_FLASHFIFO register ************************/ - -#define MSC_FLASHFIFO_FIFO_POSS 0U -#define MSC_FLASHFIFO_FIFO_POSE 31U -#define MSC_FLASHFIFO_FIFO_MSK BITS(MSC_FLASHFIFO_FIFO_POSS,MSC_FLASHFIFO_FIFO_POSE) - -/****************** Bit definition for MSC_FLASHDL register ************************/ - -#define MSC_FLASHDL_DATAL_POSS 0U -#define MSC_FLASHDL_DATAL_POSE 31U -#define MSC_FLASHDL_DATAL_MSK BITS(MSC_FLASHDL_DATAL_POSS,MSC_FLASHDL_DATAL_POSE) - -/****************** Bit definition for MSC_FLASHDH register ************************/ - -#define MSC_FLASHDH_DATAH_POSS 0U -#define MSC_FLASHDH_DATAH_POSE 31U -#define MSC_FLASHDH_DATAH_MSK BITS(MSC_FLASHDH_DATAH_POSS,MSC_FLASHDH_DATAH_POSE) - -/****************** Bit definition for MSC_FLASHCMD register ************************/ - -#define MSC_FLASHCMD_CMD_POSS 0U -#define MSC_FLASHCMD_CMD_POSE 31U -#define MSC_FLASHCMD_CMD_MSK BITS(MSC_FLASHCMD_CMD_POSS,MSC_FLASHCMD_CMD_POSE) - -/****************** Bit definition for MSC_FLASHCR register ************************/ - -#define MSC_FLASHCR_FIFOEN_POS 5U -#define MSC_FLASHCR_FIFOEN_MSK BIT(MSC_FLASHCR_FIFOEN_POS) - -#define MSC_FLASHCR_FLASHREQ_POS 4U -#define MSC_FLASHCR_FLASHREQ_MSK BIT(MSC_FLASHCR_FLASHREQ_POS) - -#define MSC_FLASHCR_IAPRST_POS 1U -#define MSC_FLASHCR_IAPRST_MSK BIT(MSC_FLASHCR_IAPRST_POS) - -#define MSC_FLASHCR_IAPEN_POS 0U -#define MSC_FLASHCR_IAPEN_MSK BIT(MSC_FLASHCR_IAPEN_POS) - -/****************** Bit definition for MSC_FLASHSR register ************************/ - -#define MSC_FLASHSR_TIMEOUT_POS 7U -#define MSC_FLASHSR_TIMEOUT_MSK BIT(MSC_FLASHSR_TIMEOUT_POS) - -#define MSC_FLASHSR_PROG_POS 6U -#define MSC_FLASHSR_PROG_MSK BIT(MSC_FLASHSR_PROG_POS) - -#define MSC_FLASHSR_SERA_POS 5U -#define MSC_FLASHSR_SERA_MSK BIT(MSC_FLASHSR_SERA_POS) - -#define MSC_FLASHSR_MASE_POS 4U -#define MSC_FLASHSR_MASE_MSK BIT(MSC_FLASHSR_MASE_POS) - -#define MSC_FLASHSR_ADDR_OV_POS 3U -#define MSC_FLASHSR_ADDR_OV_MSK BIT(MSC_FLASHSR_ADDR_OV_POS) - -#define MSC_FLASHSR_WRP_FLAG_POS 2U -#define MSC_FLASHSR_WRP_FLAG_MSK BIT(MSC_FLASHSR_WRP_FLAG_POS) - -#define MSC_FLASHSR_BUSY_POS 1U -#define MSC_FLASHSR_BUSY_MSK BIT(MSC_FLASHSR_BUSY_POS) - -#define MSC_FLASHSR_FLASHACK_POS 0U -#define MSC_FLASHSR_FLASHACK_MSK BIT(MSC_FLASHSR_FLASHACK_POS) - -/****************** Bit definition for MSC_FLASHPL register ************************/ - -#define MSC_FLASHPL_PROG_LEN_POSS 0U -#define MSC_FLASHPL_PROG_LEN_POSE 15U -#define MSC_FLASHPL_PROG_LEN_MSK BITS(MSC_FLASHPL_PROG_LEN_POSS,MSC_FLASHPL_PROG_LEN_POSE) - -/****************** Bit definition for MSC_MEMWAIT register ************************/ - -#define MSC_MEMWAIT_SRAM_W_POSS 8U -#define MSC_MEMWAIT_SRAM_W_POSE 9U -#define MSC_MEMWAIT_SRAM_W_MSK BITS(MSC_MEMWAIT_SRAM_W_POSS,MSC_MEMWAIT_SRAM_W_POSE) - -#define MSC_MEMWAIT_FLASH_W_POSS 0U -#define MSC_MEMWAIT_FLASH_W_POSE 3U -#define MSC_MEMWAIT_FLASH_W_MSK BITS(MSC_MEMWAIT_FLASH_W_POSS,MSC_MEMWAIT_FLASH_W_POSE) - -typedef struct -{ - __IO uint32_t FLASHKEY; - __IO uint32_t INFOKEY; - __IO uint32_t FLASHADDR; - __O uint32_t FLASHFIFO; - __IO uint32_t FLASHDL; - __IO uint32_t FLASHDH; - __O uint32_t FLASHCMD; - __IO uint32_t FLASHCR; - __I uint32_t FLASHSR; - __IO uint32_t FLASHPL; - __IO uint32_t MEMWAIT; -} MSC_TypeDef; - -/****************** Bit definition for BKPC_PROT register ************************/ - -#define BKPC_PROT_KEY_POSS 1U -#define BKPC_PROT_KEY_POSE 31U -#define BKPC_PROT_KEY_MSK BITS(BKPC_PROT_KEY_POSS,BKPC_PROT_KEY_POSE) - -#define BKPC_PROT_PROT_POS 0U -#define BKPC_PROT_PROT_MSK BIT(BKPC_PROT_PROT_POS) - -/****************** Bit definition for BKPC_CR register ************************/ - -#define BKPC_CR_LDO_VSEL_POSS 24U -#define BKPC_CR_LDO_VSEL_POSE 26U -#define BKPC_CR_LDO_VSEL_MSK BITS(BKPC_CR_LDO_VSEL_POSS,BKPC_CR_LDO_VSEL_POSE) - -#define BKPC_CR_MT_STDB_POS 19U -#define BKPC_CR_MT_STDB_MSK BIT(BKPC_CR_MT_STDB_POS) - -#define BKPC_CR_VR1P5_VSEL_POSS 16U -#define BKPC_CR_VR1P5_VSEL_POSE 18U -#define BKPC_CR_VR1P5_VSEL_MSK BITS(BKPC_CR_VR1P5_VSEL_POSS,BKPC_CR_VR1P5_VSEL_POSE) - -#define BKPC_CR_TC_PWRDWN_POS 13U -#define BKPC_CR_TC_PWRDWN_MSK BIT(BKPC_CR_TC_PWRDWN_POS) - -#define BKPC_CR_WKPOL_POS 12U -#define BKPC_CR_WKPOL_MSK BIT(BKPC_CR_WKPOL_POS) - -#define BKPC_CR_WKPS_POSS 9U -#define BKPC_CR_WKPS_POSE 11U -#define BKPC_CR_WKPS_MSK BITS(BKPC_CR_WKPS_POSS,BKPC_CR_WKPS_POSE) - -#define BKPC_CR_WKPEN_POS 8U -#define BKPC_CR_WKPEN_MSK BIT(BKPC_CR_WKPEN_POS) - -#define BKPC_CR_LRCEN_POS 2U -#define BKPC_CR_LRCEN_MSK BIT(BKPC_CR_LRCEN_POS) - -#define BKPC_CR_LOSMEN_POS 1U -#define BKPC_CR_LOSMEN_MSK BIT(BKPC_CR_LOSMEN_POS) - -#define BKPC_CR_LOSCEN_POS 0U -#define BKPC_CR_LOSCEN_MSK BIT(BKPC_CR_LOSCEN_POS) - -/****************** Bit definition for BKPC_PCCR register ************************/ - -#define BKPC_PCCR_TEMPCS_POSS 4U -#define BKPC_PCCR_TEMPCS_POSE 5U -#define BKPC_PCCR_TEMPCS_MSK BITS(BKPC_PCCR_TEMPCS_POSS,BKPC_PCCR_TEMPCS_POSE) - -#define BKPC_PCCR_RTCCS_POSS 0U -#define BKPC_PCCR_RTCCS_POSE 1U -#define BKPC_PCCR_RTCCS_MSK BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE) - -/****************** Bit definition for BKPC_PCR register ************************/ - -#define BKPC_PCR_BORS_POSS 1U -#define BKPC_PCR_BORS_POSE 4U -#define BKPC_PCR_BORS_MSK BITS(BKPC_PCR_BORS_POSS,BKPC_PCR_BORS_POSE) - -#define BKPC_PCR_BOREN_POS 0U -#define BKPC_PCR_BOREN_MSK BIT(BKPC_PCR_BOREN_POS) - -typedef struct -{ - __IO uint32_t PROT; - __IO uint32_t CR; - __IO uint32_t PCCR; - __IO uint32_t PCR; -} BKPC_TypeDef; - -/****************** Bit definition for PMU_CR register ************************/ - -#define PMU_CR_MTSTOP_POS 21U -#define PMU_CR_MTSTOP_MSK BIT(PMU_CR_MTSTOP_POS) - -#define PMU_CR_LPSTOP_POS 20U -#define PMU_CR_LPSTOP_MSK BIT(PMU_CR_LPSTOP_POS) - -#define PMU_CR_LPRUN_POS 19U -#define PMU_CR_LPRUN_MSK BIT(PMU_CR_LPRUN_POS) - -#define PMU_CR_LPVS_POSS 16U -#define PMU_CR_LPVS_POSE 18U -#define PMU_CR_LPVS_MSK BITS(PMU_CR_LPVS_POSS,PMU_CR_LPVS_POSE) - -#define PMU_CR_WKPS_POSS 9U -#define PMU_CR_WKPS_POSE 11U -#define PMU_CR_WKPS_MSK BITS(PMU_CR_WKPS_POSS,PMU_CR_WKPS_POSE) - -#define PMU_CR_WKPEN_POS 8U -#define PMU_CR_WKPEN_MSK BIT(PMU_CR_WKPEN_POS) - -#define PMU_CR_CSTANDBYF_POS 3U -#define PMU_CR_CSTANDBYF_MSK BIT(PMU_CR_CSTANDBYF_POS) - -#define PMU_CR_CWUF_POS 2U -#define PMU_CR_CWUF_MSK BIT(PMU_CR_CWUF_POS) - -#define PMU_CR_LPM_POSS 0U -#define PMU_CR_LPM_POSE 1U -#define PMU_CR_LPM_MSK BITS(PMU_CR_LPM_POSS,PMU_CR_LPM_POSE) - -/****************** Bit definition for PMU_SR register ************************/ - -#define PMU_SR_STANDBYF_POS 1U -#define PMU_SR_STANDBYF_MSK BIT(PMU_SR_STANDBYF_POS) - -#define PMU_SR_WUF_POS 0U -#define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS) - -/****************** Bit definition for PMU_LVDCR register ************************/ - -#define PMU_LVDCR_LVDO_POS 15U -#define PMU_LVDCR_LVDO_MSK BIT(PMU_LVDCR_LVDO_POS) - -#define PMU_LVDCR_LVDFLT_POS 11U -#define PMU_LVDCR_LVDFLT_MSK BIT(PMU_LVDCR_LVDFLT_POS) - -#define PMU_LVDCR_LVIFS_POSS 8U -#define PMU_LVDCR_LVIFS_POSE 10U -#define PMU_LVDCR_LVIFS_MSK BITS(PMU_LVDCR_LVIFS_POSS,PMU_LVDCR_LVIFS_POSE) - -#define PMU_LVDCR_LVDS_POSS 4U -#define PMU_LVDCR_LVDS_POSE 7U -#define PMU_LVDCR_LVDS_MSK BITS(PMU_LVDCR_LVDS_POSS,PMU_LVDCR_LVDS_POSE) - -#define PMU_LVDCR_LVDCIF_POS 3U -#define PMU_LVDCR_LVDCIF_MSK BIT(PMU_LVDCR_LVDCIF_POS) - -#define PMU_LVDCR_LVDIF_POS 2U -#define PMU_LVDCR_LVDIF_MSK BIT(PMU_LVDCR_LVDIF_POS) - -#define PMU_LVDCR_LVDIE_POS 1U -#define PMU_LVDCR_LVDIE_MSK BIT(PMU_LVDCR_LVDIE_POS) - -#define PMU_LVDCR_LVDEN_POS 0U -#define PMU_LVDCR_LVDEN_MSK BIT(PMU_LVDCR_LVDEN_POS) - -/****************** Bit definition for PMU_PWRCR register ************************/ - -#define PMU_PWRCR_BXCAN_POS 4U -#define PMU_PWRCR_BXCAN_MSK BIT(PMU_PWRCR_BXCAN_POS) - -#define PMU_PWRCR_SRAM_POSS 0U -#define PMU_PWRCR_SRAM_POSE 1U -#define PMU_PWRCR_SRAM_MSK BITS(PMU_PWRCR_SRAM_POSS,PMU_PWRCR_SRAM_POSE) - -/****************** Bit definition for PMU_TWUR register ************************/ - -#define PMU_TWUR_TWU_POSS 0U -#define PMU_TWUR_TWU_POSE 11U -#define PMU_TWUR_TWU_MSK BITS(PMU_TWUR_TWU_POSS,PMU_TWUR_TWU_POSE) - -/****************** Bit definition for PMU_VREFCR register ************************/ - -#define PMU_VREFCR_FLTS_POSS 13U -#define PMU_VREFCR_FLTS_POSE 14U -#define PMU_VREFCR_FLTS_MSK BITS(PMU_VREFCR_FLTS_POSS,PMU_VREFCR_FLTS_POSE) - -#define PMU_VREFCR_CHOPCS_POSS 10U -#define PMU_VREFCR_CHOPCS_POSE 12U -#define PMU_VREFCR_CHOPCS_MSK BITS(PMU_VREFCR_CHOPCS_POSS,PMU_VREFCR_CHOPCS_POSE) - -#define PMU_VREFCR_CHOP1EN_POS 9U -#define PMU_VREFCR_CHOP1EN_MSK BIT(PMU_VREFCR_CHOP1EN_POS) - -#define PMU_VREFCR_CHOPEN_POS 8U -#define PMU_VREFCR_CHOPEN_MSK BIT(PMU_VREFCR_CHOPEN_POS) - -#define PMU_VREFCR_VREFEN_POS 0U -#define PMU_VREFCR_VREFEN_MSK BIT(PMU_VREFCR_VREFEN_POS) - -typedef struct -{ - __IO uint32_t CR; - __I uint32_t SR; - __IO uint32_t LVDCR; - __IO uint32_t PWRCR; - __IO uint32_t TWUR; - __IO uint32_t VREFCR; -} PMU_TypeDef; - -/****************** Bit definition for RMU_CR register ************************/ - -#define RMU_CR_BORVS_POSS 4U -#define RMU_CR_BORVS_POSE 7U -#define RMU_CR_BORVS_MSK BITS(RMU_CR_BORVS_POSS,RMU_CR_BORVS_POSE) - -#define RMU_CR_BORFLT_POSS 1U -#define RMU_CR_BORFLT_POSE 3U -#define RMU_CR_BORFLT_MSK BITS(RMU_CR_BORFLT_POSS,RMU_CR_BORFLT_POSE) - -#define RMU_CR_BOREN_POS 0U -#define RMU_CR_BOREN_MSK BIT(RMU_CR_BOREN_POS) - -/****************** Bit definition for RMU_RSTSR register ************************/ - -#define RMU_RSTSR_CFGERR_POS 16U -#define RMU_RSTSR_CFGERR_MSK BIT(RMU_RSTSR_CFGERR_POS) - -#define RMU_RSTSR_CFG_POS 10U -#define RMU_RSTSR_CFG_MSK BIT(RMU_RSTSR_CFG_POS) - -#define RMU_RSTSR_CPU_POS 9U -#define RMU_RSTSR_CPU_MSK BIT(RMU_RSTSR_CPU_POS) - -#define RMU_RSTSR_MCU_POS 8U -#define RMU_RSTSR_MCU_MSK BIT(RMU_RSTSR_MCU_POS) - -#define RMU_RSTSR_CHIP_POS 7U -#define RMU_RSTSR_CHIP_MSK BIT(RMU_RSTSR_CHIP_POS) - -#define RMU_RSTSR_LOCKUP_POS 6U -#define RMU_RSTSR_LOCKUP_MSK BIT(RMU_RSTSR_LOCKUP_POS) - -#define RMU_RSTSR_WWDT_POS 5U -#define RMU_RSTSR_WWDT_MSK BIT(RMU_RSTSR_WWDT_POS) - -#define RMU_RSTSR_IWDT_POS 4U -#define RMU_RSTSR_IWDT_MSK BIT(RMU_RSTSR_IWDT_POS) - -#define RMU_RSTSR_NMRST_POS 3U -#define RMU_RSTSR_NMRST_MSK BIT(RMU_RSTSR_NMRST_POS) - -#define RMU_RSTSR_BOR_POS 2U -#define RMU_RSTSR_BOR_MSK BIT(RMU_RSTSR_BOR_POS) - -#define RMU_RSTSR_WAKEUP_POS 1U -#define RMU_RSTSR_WAKEUP_MSK BIT(RMU_RSTSR_WAKEUP_POS) - -#define RMU_RSTSR_POR_POS 0U -#define RMU_RSTSR_POR_MSK BIT(RMU_RSTSR_POR_POS) - -/****************** Bit definition for RMU_CRSTSR register ************************/ - -#define RMU_CRSTSR_CFG_POS 10U -#define RMU_CRSTSR_CFG_MSK BIT(RMU_CRSTSR_CFG_POS) - -#define RMU_CRSTSR_CPU_POS 9U -#define RMU_CRSTSR_CPU_MSK BIT(RMU_CRSTSR_CPU_POS) - -#define RMU_CRSTSR_MCU_POS 8U -#define RMU_CRSTSR_MCU_MSK BIT(RMU_CRSTSR_MCU_POS) - -#define RMU_CRSTSR_CHIP_POS 7U -#define RMU_CRSTSR_CHIP_MSK BIT(RMU_CRSTSR_CHIP_POS) - -#define RMU_CRSTSR_LOCKUP_POS 6U -#define RMU_CRSTSR_LOCKUP_MSK BIT(RMU_CRSTSR_LOCKUP_POS) - -#define RMU_CRSTSR_WWDT_POS 5U -#define RMU_CRSTSR_WWDT_MSK BIT(RMU_CRSTSR_WWDT_POS) - -#define RMU_CRSTSR_IWDT_POS 4U -#define RMU_CRSTSR_IWDT_MSK BIT(RMU_CRSTSR_IWDT_POS) - -#define RMU_CRSTSR_NMRST_POS 3U -#define RMU_CRSTSR_NMRST_MSK BIT(RMU_CRSTSR_NMRST_POS) - -#define RMU_CRSTSR_BOR_POS 2U -#define RMU_CRSTSR_BOR_MSK BIT(RMU_CRSTSR_BOR_POS) - -#define RMU_CRSTSR_WAKEUP_POS 1U -#define RMU_CRSTSR_WAKEUP_MSK BIT(RMU_CRSTSR_WAKEUP_POS) - -#define RMU_CRSTSR_POR_POS 0U -#define RMU_CRSTSR_POR_MSK BIT(RMU_CRSTSR_POR_POS) - -/****************** Bit definition for RMU_AHB1RSTR register ************************/ - -#define RMU_AHB1RSTR_PISRST_POS 5U -#define RMU_AHB1RSTR_PISRST_MSK BIT(RMU_AHB1RSTR_PISRST_POS) - -#define RMU_AHB1RSTR_TRNGRST_POS 4U -#define RMU_AHB1RSTR_TRNGRST_MSK BIT(RMU_AHB1RSTR_TRNGRST_POS) - -#define RMU_AHB1RSTR_CRYPTRST_POS 3U -#define RMU_AHB1RSTR_CRYPTRST_MSK BIT(RMU_AHB1RSTR_CRYPTRST_POS) - -#define RMU_AHB1RSTR_CALCRST_POS 2U -#define RMU_AHB1RSTR_CALCRST_MSK BIT(RMU_AHB1RSTR_CALCRST_POS) - -#define RMU_AHB1RSTR_CRCRST_POS 1U -#define RMU_AHB1RSTR_CRCRST_MSK BIT(RMU_AHB1RSTR_CRCRST_POS) - -#define RMU_AHB1RSTR_GPIORST_POS 0U -#define RMU_AHB1RSTR_GPIORST_MSK BIT(RMU_AHB1RSTR_GPIORST_POS) - -/****************** Bit definition for RMU_AHB2RSTR register ************************/ - -#define RMU_AHB2RSTR_CPURST_POS 1U -#define RMU_AHB2RSTR_CPURST_MSK BIT(RMU_AHB2RSTR_CPURST_POS) - -#define RMU_AHB2RSTR_CHIPRST_POS 0U -#define RMU_AHB2RSTR_CHIPRST_MSK BIT(RMU_AHB2RSTR_CHIPRST_POS) - -/****************** Bit definition for RMU_APB1RSTR register ************************/ - -#define RMU_APB1RSTR_CAN0RST_POS 24U -#define RMU_APB1RSTR_CAN0RST_MSK BIT(RMU_APB1RSTR_CAN0RST_POS) - -#define RMU_APB1RSTR_I2C1RST_POS 21U -#define RMU_APB1RSTR_I2C1RST_MSK BIT(RMU_APB1RSTR_I2C1RST_POS) - -#define RMU_APB1RSTR_I2C0RST_POS 20U -#define RMU_APB1RSTR_I2C0RST_MSK BIT(RMU_APB1RSTR_I2C0RST_POS) - -#define RMU_APB1RSTR_SPI2RST_POS 18U -#define RMU_APB1RSTR_SPI2RST_MSK BIT(RMU_APB1RSTR_SPI2RST_POS) - -#define RMU_APB1RSTR_SPI1RST_POS 17U -#define RMU_APB1RSTR_SPI1RST_MSK BIT(RMU_APB1RSTR_SPI1RST_POS) - -#define RMU_APB1RSTR_SPI0RST_POS 16U -#define RMU_APB1RSTR_SPI0RST_MSK BIT(RMU_APB1RSTR_SPI0RST_POS) - -#define RMU_APB1RSTR_USART1RST_POS 13U -#define RMU_APB1RSTR_USART1RST_MSK BIT(RMU_APB1RSTR_USART1RST_POS) - -#define RMU_APB1RSTR_USART0RST_POS 12U -#define RMU_APB1RSTR_USART0RST_MSK BIT(RMU_APB1RSTR_USART0RST_POS) - -#define RMU_APB1RSTR_UART3RST_POS 11U -#define RMU_APB1RSTR_UART3RST_MSK BIT(RMU_APB1RSTR_UART3RST_POS) - -#define RMU_APB1RSTR_UART2RST_POS 10U -#define RMU_APB1RSTR_UART2RST_MSK BIT(RMU_APB1RSTR_UART2RST_POS) - -#define RMU_APB1RSTR_UART1RST_POS 9U -#define RMU_APB1RSTR_UART1RST_MSK BIT(RMU_APB1RSTR_UART1RST_POS) - -#define RMU_APB1RSTR_UART0RST_POS 8U -#define RMU_APB1RSTR_UART0RST_MSK BIT(RMU_APB1RSTR_UART0RST_POS) - -#define RMU_APB1RSTR_TIM7RST_POS 7U -#define RMU_APB1RSTR_TIM7RST_MSK BIT(RMU_APB1RSTR_TIM7RST_POS) - -#define RMU_APB1RSTR_TIM6RST_POS 6U -#define RMU_APB1RSTR_TIM6RST_MSK BIT(RMU_APB1RSTR_TIM6RST_POS) - -#define RMU_APB1RSTR_TIM5RST_POS 5U -#define RMU_APB1RSTR_TIM5RST_MSK BIT(RMU_APB1RSTR_TIM5RST_POS) - -#define RMU_APB1RSTR_TIM4RST_POS 4U -#define RMU_APB1RSTR_TIM4RST_MSK BIT(RMU_APB1RSTR_TIM4RST_POS) - -#define RMU_APB1RSTR_TIM3RST_POS 3U -#define RMU_APB1RSTR_TIM3RST_MSK BIT(RMU_APB1RSTR_TIM3RST_POS) - -#define RMU_APB1RSTR_TIM2RST_POS 2U -#define RMU_APB1RSTR_TIM2RST_MSK BIT(RMU_APB1RSTR_TIM2RST_POS) - -#define RMU_APB1RSTR_TIM1RST_POS 1U -#define RMU_APB1RSTR_TIM1RST_MSK BIT(RMU_APB1RSTR_TIM1RST_POS) - -#define RMU_APB1RSTR_TIM0RST_POS 0U -#define RMU_APB1RSTR_TIM0RST_MSK BIT(RMU_APB1RSTR_TIM0RST_POS) - -/****************** Bit definition for RMU_APB2RSTR register ************************/ - -#define RMU_APB2RSTR_BKPRAMRST_POS 18U -#define RMU_APB2RSTR_BKPRAMRST_MSK BIT(RMU_APB2RSTR_BKPRAMRST_POS) - -#define RMU_APB2RSTR_BKPCRST_POS 17U -#define RMU_APB2RSTR_BKPCRST_MSK BIT(RMU_APB2RSTR_BKPCRST_POS) - -#define RMU_APB2RSTR_TEMPRST_POS 16U -#define RMU_APB2RSTR_TEMPRST_MSK BIT(RMU_APB2RSTR_TEMPRST_POS) - -#define RMU_APB2RSTR_RTCRST_POS 15U -#define RMU_APB2RSTR_RTCRST_MSK BIT(RMU_APB2RSTR_RTCRST_POS) - -#define RMU_APB2RSTR_IWDTRST_POS 14U -#define RMU_APB2RSTR_IWDTRST_MSK BIT(RMU_APB2RSTR_IWDTRST_POS) - -#define RMU_APB2RSTR_LCDRST_POS 13U -#define RMU_APB2RSTR_LCDRST_MSK BIT(RMU_APB2RSTR_LCDRST_POS) - -#define RMU_APB2RSTR_WWDTRST_POS 12U -#define RMU_APB2RSTR_WWDTRST_MSK BIT(RMU_APB2RSTR_WWDTRST_POS) - -#define RMU_APB2RSTR_OPAMPRST_POS 8U -#define RMU_APB2RSTR_OPAMPRST_MSK BIT(RMU_APB2RSTR_OPAMPRST_POS) - -#define RMU_APB2RSTR_ACMP1RST_POS 7U -#define RMU_APB2RSTR_ACMP1RST_MSK BIT(RMU_APB2RSTR_ACMP1RST_POS) - -#define RMU_APB2RSTR_ACMP0RST_POS 6U -#define RMU_APB2RSTR_ACMP0RST_MSK BIT(RMU_APB2RSTR_ACMP0RST_POS) - -#define RMU_APB2RSTR_ADC0RST_POS 4U -#define RMU_APB2RSTR_ADC0RST_MSK BIT(RMU_APB2RSTR_ADC0RST_POS) - -#define RMU_APB2RSTR_LPUART0RST_POS 2U -#define RMU_APB2RSTR_LPUART0RST_MSK BIT(RMU_APB2RSTR_LPUART0RST_POS) - -#define RMU_APB2RSTR_LPTIM0RST_POS 0U -#define RMU_APB2RSTR_LPTIM0RST_MSK BIT(RMU_APB2RSTR_LPTIM0RST_POS) - -typedef struct -{ - __IO uint32_t CR; - uint32_t RESERVED0[3] ; - __I uint32_t RSTSR; - __O uint32_t CRSTSR; - uint32_t RESERVED1[2] ; - __O uint32_t AHB1RSTR; - __O uint32_t AHB2RSTR; - uint32_t RESERVED2[2] ; - __O uint32_t APB1RSTR; - __O uint32_t APB2RSTR; -} RMU_TypeDef; - -/****************** Bit definition for CMU_CSR register ************************/ - -#define CMU_CSR_CFT_RDYN_POS 25U -#define CMU_CSR_CFT_RDYN_MSK BIT(CMU_CSR_CFT_RDYN_POS) - -#define CMU_CSR_CFT_STU_POS 24U -#define CMU_CSR_CFT_STU_MSK BIT(CMU_CSR_CFT_STU_POS) - -#define CMU_CSR_CFT_CMD_POSS 16U -#define CMU_CSR_CFT_CMD_POSE 23U -#define CMU_CSR_CFT_CMD_MSK BITS(CMU_CSR_CFT_CMD_POSS,CMU_CSR_CFT_CMD_POSE) - -#define CMU_CSR_SYS_RDYN_POS 12U -#define CMU_CSR_SYS_RDYN_MSK BIT(CMU_CSR_SYS_RDYN_POS) - -#define CMU_CSR_SYS_STU_POSS 8U -#define CMU_CSR_SYS_STU_POSE 10U -#define CMU_CSR_SYS_STU_MSK BITS(CMU_CSR_SYS_STU_POSS,CMU_CSR_SYS_STU_POSE) - -#define CMU_CSR_SYS_CMD_POSS 0U -#define CMU_CSR_SYS_CMD_POSE 2U -#define CMU_CSR_SYS_CMD_MSK BITS(CMU_CSR_SYS_CMD_POSS,CMU_CSR_SYS_CMD_POSE) - -/****************** Bit definition for CMU_CFGR register ************************/ - -#define CMU_CFGR_HRCFST_POS 25U -#define CMU_CFGR_HRCFST_MSK BIT(CMU_CFGR_HRCFST_POS) - -#define CMU_CFGR_HRCFSW_POS 24U -#define CMU_CFGR_HRCFSW_MSK BIT(CMU_CFGR_HRCFSW_POS) - -#define CMU_CFGR_PCLK2DIV_POSS 20U -#define CMU_CFGR_PCLK2DIV_POSE 23U -#define CMU_CFGR_PCLK2DIV_MSK BITS(CMU_CFGR_PCLK2DIV_POSS,CMU_CFGR_PCLK2DIV_POSE) - -#define CMU_CFGR_PCLK1DIV_POSS 16U -#define CMU_CFGR_PCLK1DIV_POSE 19U -#define CMU_CFGR_PCLK1DIV_MSK BITS(CMU_CFGR_PCLK1DIV_POSS,CMU_CFGR_PCLK1DIV_POSE) - -#define CMU_CFGR_SYSDIV_POSS 12U -#define CMU_CFGR_SYSDIV_POSE 15U -#define CMU_CFGR_SYSDIV_MSK BITS(CMU_CFGR_SYSDIV_POSS,CMU_CFGR_SYSDIV_POSE) - -#define CMU_CFGR_HCLK1DIV_POSS 0U -#define CMU_CFGR_HCLK1DIV_POSE 3U -#define CMU_CFGR_HCLK1DIV_MSK BITS(CMU_CFGR_HCLK1DIV_POSS,CMU_CFGR_HCLK1DIV_POSE) - -/****************** Bit definition for CMU_CLKENR register ************************/ - -#define CMU_CLKENR_PLL2EN_POS 9U -#define CMU_CLKENR_PLL2EN_MSK BIT(CMU_CLKENR_PLL2EN_POS) - -#define CMU_CLKENR_PLL1EN_POS 8U -#define CMU_CLKENR_PLL1EN_MSK BIT(CMU_CLKENR_PLL1EN_POS) - -#define CMU_CLKENR_ULRCEN_POS 4U -#define CMU_CLKENR_ULRCEN_MSK BIT(CMU_CLKENR_ULRCEN_POS) - -#define CMU_CLKENR_LRCEN_POS 3U -#define CMU_CLKENR_LRCEN_MSK BIT(CMU_CLKENR_LRCEN_POS) - -#define CMU_CLKENR_HRCEN_POS 2U -#define CMU_CLKENR_HRCEN_MSK BIT(CMU_CLKENR_HRCEN_POS) - -#define CMU_CLKENR_LOSCEN_POS 1U -#define CMU_CLKENR_LOSCEN_MSK BIT(CMU_CLKENR_LOSCEN_POS) - -#define CMU_CLKENR_HOSCEN_POS 0U -#define CMU_CLKENR_HOSCEN_MSK BIT(CMU_CLKENR_HOSCEN_POS) - -/****************** Bit definition for CMU_CLKSR register ************************/ - -#define CMU_CLKSR_PLL2RDY_POS 25U -#define CMU_CLKSR_PLL2RDY_MSK BIT(CMU_CLKSR_PLL2RDY_POS) - -#define CMU_CLKSR_PLL1RDY_POS 24U -#define CMU_CLKSR_PLL1RDY_MSK BIT(CMU_CLKSR_PLL1RDY_POS) - -#define CMU_CLKSR_LRCRDY_POS 19U -#define CMU_CLKSR_LRCRDY_MSK BIT(CMU_CLKSR_LRCRDY_POS) - -#define CMU_CLKSR_HRCRDY_POS 18U -#define CMU_CLKSR_HRCRDY_MSK BIT(CMU_CLKSR_HRCRDY_POS) - -#define CMU_CLKSR_LOSCRDY_POS 17U -#define CMU_CLKSR_LOSCRDY_MSK BIT(CMU_CLKSR_LOSCRDY_POS) - -#define CMU_CLKSR_HOSCRDY_POS 16U -#define CMU_CLKSR_HOSCRDY_MSK BIT(CMU_CLKSR_HOSCRDY_POS) - -#define CMU_CLKSR_PLL2ACT_POS 9U -#define CMU_CLKSR_PLL2ACT_MSK BIT(CMU_CLKSR_PLL2ACT_POS) - -#define CMU_CLKSR_PLL1ACT_POS 8U -#define CMU_CLKSR_PLL1ACT_MSK BIT(CMU_CLKSR_PLL1ACT_POS) - -#define CMU_CLKSR_ULRCACT_POS 4U -#define CMU_CLKSR_ULRCACT_MSK BIT(CMU_CLKSR_ULRCACT_POS) - -#define CMU_CLKSR_LRCACT_POS 3U -#define CMU_CLKSR_LRCACT_MSK BIT(CMU_CLKSR_LRCACT_POS) - -#define CMU_CLKSR_HRCACT_POS 2U -#define CMU_CLKSR_HRCACT_MSK BIT(CMU_CLKSR_HRCACT_POS) - -#define CMU_CLKSR_LOSCACT_POS 1U -#define CMU_CLKSR_LOSCACT_MSK BIT(CMU_CLKSR_LOSCACT_POS) - -#define CMU_CLKSR_HOSCACT_POS 0U -#define CMU_CLKSR_HOSCACT_MSK BIT(CMU_CLKSR_HOSCACT_POS) - -/****************** Bit definition for CMU_PLLCFG register ************************/ - -#define CMU_PLLCFG_PLL2LCKN_POS 17U -#define CMU_PLLCFG_PLL2LCKN_MSK BIT(CMU_PLLCFG_PLL2LCKN_POS) - -#define CMU_PLLCFG_PLL1LCKN_POS 16U -#define CMU_PLLCFG_PLL1LCKN_MSK BIT(CMU_PLLCFG_PLL1LCKN_POS) - -#define CMU_PLLCFG_PLL2RFS_POSS 8U -#define CMU_PLLCFG_PLL2RFS_POSE 9U -#define CMU_PLLCFG_PLL2RFS_MSK BITS(CMU_PLLCFG_PLL2RFS_POSS,CMU_PLLCFG_PLL2RFS_POSE) - -#define CMU_PLLCFG_PLL1OS_POS 4U -#define CMU_PLLCFG_PLL1OS_MSK BIT(CMU_PLLCFG_PLL1OS_POS) - -#define CMU_PLLCFG_PLL1RFS_POSS 0U -#define CMU_PLLCFG_PLL1RFS_POSE 2U -#define CMU_PLLCFG_PLL1RFS_MSK BITS(CMU_PLLCFG_PLL1RFS_POSS,CMU_PLLCFG_PLL1RFS_POSE) - -/****************** Bit definition for CMU_HOSCCFG register ************************/ - -#define CMU_HOSCCFG_FREQ_POSS 0U -#define CMU_HOSCCFG_FREQ_POSE 4U -#define CMU_HOSCCFG_FREQ_MSK BITS(CMU_HOSCCFG_FREQ_POSS,CMU_HOSCCFG_FREQ_POSE) - -/****************** Bit definition for CMU_HOSMCR register ************************/ - -#define CMU_HOSMCR_NMIE_POS 20U -#define CMU_HOSMCR_NMIE_MSK BIT(CMU_HOSMCR_NMIE_POS) - -#define CMU_HOSMCR_STPIF_POS 19U -#define CMU_HOSMCR_STPIF_MSK BIT(CMU_HOSMCR_STPIF_POS) - -#define CMU_HOSMCR_STRIF_POS 18U -#define CMU_HOSMCR_STRIF_MSK BIT(CMU_HOSMCR_STRIF_POS) - -#define CMU_HOSMCR_STPIE_POS 17U -#define CMU_HOSMCR_STPIE_MSK BIT(CMU_HOSMCR_STPIE_POS) - -#define CMU_HOSMCR_STRIE_POS 16U -#define CMU_HOSMCR_STRIE_MSK BIT(CMU_HOSMCR_STRIE_POS) - -#define CMU_HOSMCR_FRQS_POSS 8U -#define CMU_HOSMCR_FRQS_POSE 10U -#define CMU_HOSMCR_FRQS_MSK BITS(CMU_HOSMCR_FRQS_POSS,CMU_HOSMCR_FRQS_POSE) - -#define CMU_HOSMCR_CLKS_POS 1U -#define CMU_HOSMCR_CLKS_MSK BIT(CMU_HOSMCR_CLKS_POS) - -#define CMU_HOSMCR_EN_POS 0U -#define CMU_HOSMCR_EN_MSK BIT(CMU_HOSMCR_EN_POS) - -/****************** Bit definition for CMU_LOSMCR register ************************/ - -#define CMU_LOSMCR_NMIE_POS 20U -#define CMU_LOSMCR_NMIE_MSK BIT(CMU_LOSMCR_NMIE_POS) - -#define CMU_LOSMCR_STPIF_POS 19U -#define CMU_LOSMCR_STPIF_MSK BIT(CMU_LOSMCR_STPIF_POS) - -#define CMU_LOSMCR_STRIF_POS 18U -#define CMU_LOSMCR_STRIF_MSK BIT(CMU_LOSMCR_STRIF_POS) - -#define CMU_LOSMCR_STPIE_POS 17U -#define CMU_LOSMCR_STPIE_MSK BIT(CMU_LOSMCR_STPIE_POS) - -#define CMU_LOSMCR_STRIE_POS 16U -#define CMU_LOSMCR_STRIE_MSK BIT(CMU_LOSMCR_STRIE_POS) - -#define CMU_LOSMCR_CLKS_POS 1U -#define CMU_LOSMCR_CLKS_MSK BIT(CMU_LOSMCR_CLKS_POS) - -#define CMU_LOSMCR_EN_POS 0U -#define CMU_LOSMCR_EN_MSK BIT(CMU_LOSMCR_EN_POS) - -/****************** Bit definition for CMU_PULMCR register ************************/ - -#define CMU_PULMCR_NMIE_POS 20U -#define CMU_PULMCR_NMIE_MSK BIT(CMU_PULMCR_NMIE_POS) - -#define CMU_PULMCR_ULKIF_POS 19U -#define CMU_PULMCR_ULKIF_MSK BIT(CMU_PULMCR_ULKIF_POS) - -#define CMU_PULMCR_LCKIF_POS 18U -#define CMU_PULMCR_LCKIF_MSK BIT(CMU_PULMCR_LCKIF_POS) - -#define CMU_PULMCR_ULKIE_POS 17U -#define CMU_PULMCR_ULKIE_MSK BIT(CMU_PULMCR_ULKIE_POS) - -#define CMU_PULMCR_LCKIE_POS 16U -#define CMU_PULMCR_LCKIE_MSK BIT(CMU_PULMCR_LCKIE_POS) - -#define CMU_PULMCR_MODE_POSS 8U -#define CMU_PULMCR_MODE_POSE 9U -#define CMU_PULMCR_MODE_MSK BITS(CMU_PULMCR_MODE_POSS,CMU_PULMCR_MODE_POSE) - -#define CMU_PULMCR_CLKS_POS 1U -#define CMU_PULMCR_CLKS_MSK BIT(CMU_PULMCR_CLKS_POS) - -#define CMU_PULMCR_EN_POS 0U -#define CMU_PULMCR_EN_MSK BIT(CMU_PULMCR_EN_POS) - -/****************** Bit definition for CMU_CLKOCR register ************************/ - -#define CMU_CLKOCR_LSCOS_POSS 24U -#define CMU_CLKOCR_LSCOS_POSE 26U -#define CMU_CLKOCR_LSCOS_MSK BITS(CMU_CLKOCR_LSCOS_POSS,CMU_CLKOCR_LSCOS_POSE) - -#define CMU_CLKOCR_LSCOEN_POS 16U -#define CMU_CLKOCR_LSCOEN_MSK BIT(CMU_CLKOCR_LSCOEN_POS) - -#define CMU_CLKOCR_HSCODIV_POSS 12U -#define CMU_CLKOCR_HSCODIV_POSE 14U -#define CMU_CLKOCR_HSCODIV_MSK BITS(CMU_CLKOCR_HSCODIV_POSS,CMU_CLKOCR_HSCODIV_POSE) - -#define CMU_CLKOCR_HSCOS_POSS 8U -#define CMU_CLKOCR_HSCOS_POSE 10U -#define CMU_CLKOCR_HSCOS_MSK BITS(CMU_CLKOCR_HSCOS_POSS,CMU_CLKOCR_HSCOS_POSE) - -#define CMU_CLKOCR_HSCOEN_POS 0U -#define CMU_CLKOCR_HSCOEN_MSK BIT(CMU_CLKOCR_HSCOEN_POS) - -/****************** Bit definition for CMU_BUZZCR register ************************/ - -#define CMU_BUZZCR_DAT_POSS 16U -#define CMU_BUZZCR_DAT_POSE 31U -#define CMU_BUZZCR_DAT_MSK BITS(CMU_BUZZCR_DAT_POSS,CMU_BUZZCR_DAT_POSE) - -#define CMU_BUZZCR_DIV_POSS 8U -#define CMU_BUZZCR_DIV_POSE 10U -#define CMU_BUZZCR_DIV_MSK BITS(CMU_BUZZCR_DIV_POSS,CMU_BUZZCR_DIV_POSE) - -#define CMU_BUZZCR_EN_POS 0U -#define CMU_BUZZCR_EN_MSK BIT(CMU_BUZZCR_EN_POS) - -/****************** Bit definition for CMU_AHB1ENR register ************************/ - -#define CMU_AHB1ENR_PISEN_POS 5U -#define CMU_AHB1ENR_PISEN_MSK BIT(CMU_AHB1ENR_PISEN_POS) - -#define CMU_AHB1ENR_TRNGEN_POS 4U -#define CMU_AHB1ENR_TRNGEN_MSK BIT(CMU_AHB1ENR_TRNGEN_POS) - -#define CMU_AHB1ENR_CRYPTEN_POS 3U -#define CMU_AHB1ENR_CRYPTEN_MSK BIT(CMU_AHB1ENR_CRYPTEN_POS) - -#define CMU_AHB1ENR_CALCEN_POS 2U -#define CMU_AHB1ENR_CALCEN_MSK BIT(CMU_AHB1ENR_CALCEN_POS) - -#define CMU_AHB1ENR_CRCEN_POS 1U -#define CMU_AHB1ENR_CRCEN_MSK BIT(CMU_AHB1ENR_CRCEN_POS) - -#define CMU_AHB1ENR_GPIOEN_POS 0U -#define CMU_AHB1ENR_GPIOEN_MSK BIT(CMU_AHB1ENR_GPIOEN_POS) - -/****************** Bit definition for CMU_APB1ENR register ************************/ - -#define CMU_APB1ENR_CAN0EN_POS 24U -#define CMU_APB1ENR_CAN0EN_MSK BIT(CMU_APB1ENR_CAN0EN_POS) - -#define CMU_APB1ENR_I2C1EN_POS 21U -#define CMU_APB1ENR_I2C1EN_MSK BIT(CMU_APB1ENR_I2C1EN_POS) - -#define CMU_APB1ENR_I2C0EN_POS 20U -#define CMU_APB1ENR_I2C0EN_MSK BIT(CMU_APB1ENR_I2C0EN_POS) - -#define CMU_APB1ENR_SPI2EN_POS 18U -#define CMU_APB1ENR_SPI2EN_MSK BIT(CMU_APB1ENR_SPI2EN_POS) - -#define CMU_APB1ENR_SPI1EN_POS 17U -#define CMU_APB1ENR_SPI1EN_MSK BIT(CMU_APB1ENR_SPI1EN_POS) - -#define CMU_APB1ENR_SPI0EN_POS 16U -#define CMU_APB1ENR_SPI0EN_MSK BIT(CMU_APB1ENR_SPI0EN_POS) - -#define CMU_APB1ENR_USART1EN_POS 13U -#define CMU_APB1ENR_USART1EN_MSK BIT(CMU_APB1ENR_USART1EN_POS) - -#define CMU_APB1ENR_USART0EN_POS 12U -#define CMU_APB1ENR_USART0EN_MSK BIT(CMU_APB1ENR_USART0EN_POS) - -#define CMU_APB1ENR_UART3EN_POS 11U -#define CMU_APB1ENR_UART3EN_MSK BIT(CMU_APB1ENR_UART3EN_POS) - -#define CMU_APB1ENR_UART2EN_POS 10U -#define CMU_APB1ENR_UART2EN_MSK BIT(CMU_APB1ENR_UART2EN_POS) - -#define CMU_APB1ENR_UART1EN_POS 9U -#define CMU_APB1ENR_UART1EN_MSK BIT(CMU_APB1ENR_UART1EN_POS) - -#define CMU_APB1ENR_UART0EN_POS 8U -#define CMU_APB1ENR_UART0EN_MSK BIT(CMU_APB1ENR_UART0EN_POS) - -#define CMU_APB1ENR_TIM7EN_POS 7U -#define CMU_APB1ENR_TIM7EN_MSK BIT(CMU_APB1ENR_TIM7EN_POS) - -#define CMU_APB1ENR_TIM6EN_POS 6U -#define CMU_APB1ENR_TIM6EN_MSK BIT(CMU_APB1ENR_TIM6EN_POS) - -#define CMU_APB1ENR_TIM5EN_POS 5U -#define CMU_APB1ENR_TIM5EN_MSK BIT(CMU_APB1ENR_TIM5EN_POS) - -#define CMU_APB1ENR_TIM4EN_POS 4U -#define CMU_APB1ENR_TIM4EN_MSK BIT(CMU_APB1ENR_TIM4EN_POS) - -#define CMU_APB1ENR_TIM3EN_POS 3U -#define CMU_APB1ENR_TIM3EN_MSK BIT(CMU_APB1ENR_TIM3EN_POS) - -#define CMU_APB1ENR_TIM2EN_POS 2U -#define CMU_APB1ENR_TIM2EN_MSK BIT(CMU_APB1ENR_TIM2EN_POS) - -#define CMU_APB1ENR_TIM1EN_POS 1U -#define CMU_APB1ENR_TIM1EN_MSK BIT(CMU_APB1ENR_TIM1EN_POS) - -#define CMU_APB1ENR_TIM0EN_POS 0U -#define CMU_APB1ENR_TIM0EN_MSK BIT(CMU_APB1ENR_TIM0EN_POS) - -/****************** Bit definition for CMU_APB2ENR register ************************/ - -#define CMU_APB2ENR_DBGCEN_POS 19U -#define CMU_APB2ENR_DBGCEN_MSK BIT(CMU_APB2ENR_DBGCEN_POS) - -#define CMU_APB2ENR_BKPCEN_POS 17U -#define CMU_APB2ENR_BKPCEN_MSK BIT(CMU_APB2ENR_BKPCEN_POS) - -#define CMU_APB2ENR_TEMPEN_POS 16U -#define CMU_APB2ENR_TEMPEN_MSK BIT(CMU_APB2ENR_TEMPEN_POS) - -#define CMU_APB2ENR_RTCEN_POS 15U -#define CMU_APB2ENR_RTCEN_MSK BIT(CMU_APB2ENR_RTCEN_POS) - -#define CMU_APB2ENR_IWDTEN_POS 14U -#define CMU_APB2ENR_IWDTEN_MSK BIT(CMU_APB2ENR_IWDTEN_POS) - -#define CMU_APB2ENR_LCDEN_POS 13U -#define CMU_APB2ENR_LCDEN_MSK BIT(CMU_APB2ENR_LCDEN_POS) - -#define CMU_APB2ENR_WWDTEN_POS 12U -#define CMU_APB2ENR_WWDTEN_MSK BIT(CMU_APB2ENR_WWDTEN_POS) - -#define CMU_APB2ENR_OPAMPEN_POS 8U -#define CMU_APB2ENR_OPAMPEN_MSK BIT(CMU_APB2ENR_OPAMPEN_POS) - -#define CMU_APB2ENR_ACMP1EN_POS 7U -#define CMU_APB2ENR_ACMP1EN_MSK BIT(CMU_APB2ENR_ACMP1EN_POS) - -#define CMU_APB2ENR_ACMP0EN_POS 6U -#define CMU_APB2ENR_ACMP0EN_MSK BIT(CMU_APB2ENR_ACMP0EN_POS) - -#define CMU_APB2ENR_ADC0EN_POS 4U -#define CMU_APB2ENR_ADC0EN_MSK BIT(CMU_APB2ENR_ADC0EN_POS) - -#define CMU_APB2ENR_LPUART0EN_POS 2U -#define CMU_APB2ENR_LPUART0EN_MSK BIT(CMU_APB2ENR_LPUART0EN_POS) - -#define CMU_APB2ENR_LPTIM0EN_POS 0U -#define CMU_APB2ENR_LPTIM0EN_MSK BIT(CMU_APB2ENR_LPTIM0EN_POS) - -/****************** Bit definition for CMU_LPENR register ************************/ - -#define CMU_LPENR_HOSCEN_POS 3U -#define CMU_LPENR_HOSCEN_MSK BIT(CMU_LPENR_HOSCEN_POS) - -#define CMU_LPENR_HRCEN_POS 2U -#define CMU_LPENR_HRCEN_MSK BIT(CMU_LPENR_HRCEN_POS) - -#define CMU_LPENR_LOSCEN_POS 1U -#define CMU_LPENR_LOSCEN_MSK BIT(CMU_LPENR_LOSCEN_POS) - -#define CMU_LPENR_LRCEN_POS 0U -#define CMU_LPENR_LRCEN_MSK BIT(CMU_LPENR_LRCEN_POS) - -/****************** Bit definition for CMU_PERICR register ************************/ - -#define CMU_PERICR_LCD_POSS 16U -#define CMU_PERICR_LCD_POSE 18U -#define CMU_PERICR_LCD_MSK BITS(CMU_PERICR_LCD_POSS,CMU_PERICR_LCD_POSE) - -#define CMU_PERICR_LPUART0_POSS 8U -#define CMU_PERICR_LPUART0_POSE 11U -#define CMU_PERICR_LPUART0_MSK BITS(CMU_PERICR_LPUART0_POSS,CMU_PERICR_LPUART0_POSE) - -#define CMU_PERICR_LPTIM0_POSS 0U -#define CMU_PERICR_LPTIM0_POSE 3U -#define CMU_PERICR_LPTIM0_MSK BITS(CMU_PERICR_LPTIM0_POSS,CMU_PERICR_LPTIM0_POSE) - -/****************** Bit definition for CMU_HRCACR register ************************/ - -#define CMU_HRCACR_IB_POSS 28U -#define CMU_HRCACR_IB_POSE 29U -#define CMU_HRCACR_IB_MSK BITS(CMU_HRCACR_IB_POSS,CMU_HRCACR_IB_POSE) - -#define CMU_HRCACR_CAP_POSS 26U -#define CMU_HRCACR_CAP_POSE 27U -#define CMU_HRCACR_CAP_MSK BITS(CMU_HRCACR_CAP_POSS,CMU_HRCACR_CAP_POSE) - -#define CMU_HRCACR_CAL_POSS 16U -#define CMU_HRCACR_CAL_POSE 25U -#define CMU_HRCACR_CAL_MSK BITS(CMU_HRCACR_CAL_POSS,CMU_HRCACR_CAL_POSE) - -#define CMU_HRCACR_IBSET_POSS 14U -#define CMU_HRCACR_IBSET_POSE 15U -#define CMU_HRCACR_IBSET_MSK BITS(CMU_HRCACR_IBSET_POSS,CMU_HRCACR_IBSET_POSE) - -#define CMU_HRCACR_CAPSET_POSS 12U -#define CMU_HRCACR_CAPSET_POSE 13U -#define CMU_HRCACR_CAPSET_MSK BITS(CMU_HRCACR_CAPSET_POSS,CMU_HRCACR_CAPSET_POSE) - -#define CMU_HRCACR_STA_POSS 9U -#define CMU_HRCACR_STA_POSE 10U -#define CMU_HRCACR_STA_MSK BITS(CMU_HRCACR_STA_POSS,CMU_HRCACR_STA_POSE) - -#define CMU_HRCACR_BUSY_POS 8U -#define CMU_HRCACR_BUSY_MSK BIT(CMU_HRCACR_BUSY_POS) - -#define CMU_HRCACR_WRTRG_POS 7U -#define CMU_HRCACR_WRTRG_MSK BIT(CMU_HRCACR_WRTRG_POS) - -#define CMU_HRCACR_AC_POSS 4U -#define CMU_HRCACR_AC_POSE 6U -#define CMU_HRCACR_AC_MSK BITS(CMU_HRCACR_AC_POSS,CMU_HRCACR_AC_POSE) - -#define CMU_HRCACR_IBS_POS 3U -#define CMU_HRCACR_IBS_MSK BIT(CMU_HRCACR_IBS_POS) - -#define CMU_HRCACR_RFSEL_POS 2U -#define CMU_HRCACR_RFSEL_MSK BIT(CMU_HRCACR_RFSEL_POS) - -#define CMU_HRCACR_FREQ_POS 1U -#define CMU_HRCACR_FREQ_MSK BIT(CMU_HRCACR_FREQ_POS) - -#define CMU_HRCACR_EN_POS 0U -#define CMU_HRCACR_EN_MSK BIT(CMU_HRCACR_EN_POS) - -typedef struct -{ - __O uint32_t CSR; - __IO uint32_t CFGR; - uint32_t RESERVED0[2] ; - __IO uint32_t CLKENR; - __I uint32_t CLKSR; - __IO uint32_t PLLCFG; - __IO uint32_t HOSCCFG; - __IO uint32_t HOSMCR; - __IO uint32_t LOSMCR; - __IO uint32_t PULMCR; - uint32_t RESERVED1 ; - __IO uint32_t CLKOCR; - __IO uint32_t BUZZCR; - uint32_t RESERVED2[2] ; - __IO uint32_t AHB1ENR; - uint32_t RESERVED3[3] ; - __IO uint32_t APB1ENR; - __IO uint32_t APB2ENR; - uint32_t RESERVED4[2] ; - __IO uint32_t LPENR; - uint32_t RESERVED5[7] ; - __IO uint32_t PERICR; - uint32_t RESERVED6[3] ; - __IO uint32_t HRCACR; -} CMU_TypeDef; - -/****************** Bit definition for DMA_STATUS register ************************/ - -#define DMA_STATUS_STATUS_POSS 4U -#define DMA_STATUS_STATUS_POSE 7U -#define DMA_STATUS_STATUS_MSK BITS(DMA_STATUS_STATUS_POSS,DMA_STATUS_STATUS_POSE) - -#define DMA_STATUS_MASTER_ENABLE_POS 0U -#define DMA_STATUS_MASTER_ENABLE_MSK BIT(DMA_STATUS_MASTER_ENABLE_POS) - -/****************** Bit definition for DMA_CFG register ************************/ - -#define DMA_CFG_CHNL_PROT_CTRL_POSS 5U -#define DMA_CFG_CHNL_PROT_CTRL_POSE 7U -#define DMA_CFG_CHNL_PROT_CTRL_MSK BITS(DMA_CFG_CHNL_PROT_CTRL_POSS,DMA_CFG_CHNL_PROT_CTRL_POSE) - -#define DMA_CFG_MASTER_ENABLE_POS 0U -#define DMA_CFG_MASTER_ENABLE_MSK BIT(DMA_CFG_MASTER_ENABLE_POS) - -/****************** Bit definition for DMA_CTRLBASE register ************************/ - -#define DMA_CTRLBASE_CTRL_BASE_PTR_POSS 9U -#define DMA_CTRLBASE_CTRL_BASE_PTR_POSE 31U -#define DMA_CTRLBASE_CTRL_BASE_PTR_MSK BITS(DMA_CTRLBASE_CTRL_BASE_PTR_POSS,DMA_CTRLBASE_CTRL_BASE_PTR_POSE) - -/****************** Bit definition for DMA_ALTCTRLBASE register ************************/ - -#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS 0U -#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE 31U -#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_MSK BITS(DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS,DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE) - -/****************** Bit definition for DMA_CHWAITSTATUS register ************************/ - -#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS 0U -#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE 31U -#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_MSK BITS(DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS,DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE) - -/****************** Bit definition for DMA_CHSWREQ register ************************/ - -#define DMA_CHSWREQ_CHSWREQ_POSS 0U -#define DMA_CHSWREQ_CHSWREQ_POSE 31U -#define DMA_CHSWREQ_CHSWREQ_MSK BITS(DMA_CHSWREQ_CHSWREQ_POSS,DMA_CHSWREQ_CHSWREQ_POSE) - -/****************** Bit definition for DMA_CHUSEBURSTSET register ************************/ - -#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS 0U -#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE 31U -#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_MSK BITS(DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS,DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE) - -/****************** Bit definition for DMA_CHUSEBURSTCLR register ************************/ - -#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS 0U -#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE 31U -#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_MSK BITS(DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS,DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE) - -/****************** Bit definition for DMA_CHREQMASKSET register ************************/ - -#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS 0U -#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE 31U -#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_MSK BITS(DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS,DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE) - -/****************** Bit definition for DMA_CHREQMASKCLR register ************************/ - -#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS 0U -#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE 31U -#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_MSK BITS(DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS,DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE) - -/****************** Bit definition for DMA_CHENSET register ************************/ - -#define DMA_CHENSET_CHNL_ENABLE_SET_POSS 0U -#define DMA_CHENSET_CHNL_ENABLE_SET_POSE 31U -#define DMA_CHENSET_CHNL_ENABLE_SET_MSK BITS(DMA_CHENSET_CHNL_ENABLE_SET_POSS,DMA_CHENSET_CHNL_ENABLE_SET_POSE) - -/****************** Bit definition for DMA_CHENCLR register ************************/ - -#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSS 0U -#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSE 31U -#define DMA_CHENCLR_CHNL_ENABLE_CLR_MSK BITS(DMA_CHENCLR_CHNL_ENABLE_CLR_POSS,DMA_CHENCLR_CHNL_ENABLE_CLR_POSE) - -/****************** Bit definition for DMA_CHPRIALTSET register ************************/ - -#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS 0U -#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE 31U -#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_MSK BITS(DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS,DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE) - -/****************** Bit definition for DMA_CHPRIALTCLR register ************************/ - -#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS 0U -#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE 31U -#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_MSK BITS(DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS,DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE) - -/****************** Bit definition for DMA_CHPRSET register ************************/ - -#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSS 0U -#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSE 31U -#define DMA_CHPRSET_CHNL_PRIORITY_SET_MSK BITS(DMA_CHPRSET_CHNL_PRIORITY_SET_POSS,DMA_CHPRSET_CHNL_PRIORITY_SET_POSE) - -/****************** Bit definition for DMA_CHPRCLR register ************************/ - -#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS 0U -#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE 31U -#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_MSK BITS(DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS,DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE) - -/****************** Bit definition for DMA_ERRCLR register ************************/ - -#define DMA_ERRCLR_ERR_CLR_POS 0U -#define DMA_ERRCLR_ERR_CLR_MSK BIT(DMA_ERRCLR_ERR_CLR_POS) - -/****************** Bit definition for DMA_IFLAG register ************************/ - -#define DMA_IFLAG_DMAERRIF_POS 31U -#define DMA_IFLAG_DMAERRIF_MSK BIT(DMA_IFLAG_DMAERRIF_POS) - -#define DMA_IFLAG_CH5DONEIF_POS 5U -#define DMA_IFLAG_CH5DONEIF_MSK BIT(DMA_IFLAG_CH5DONEIF_POS) - -#define DMA_IFLAG_CH4DONEIF_POS 4U -#define DMA_IFLAG_CH4DONEIF_MSK BIT(DMA_IFLAG_CH4DONEIF_POS) - -#define DMA_IFLAG_CH3DONEIF_POS 3U -#define DMA_IFLAG_CH3DONEIF_MSK BIT(DMA_IFLAG_CH3DONEIF_POS) - -#define DMA_IFLAG_CH2DONEIF_POS 2U -#define DMA_IFLAG_CH2DONEIF_MSK BIT(DMA_IFLAG_CH2DONEIF_POS) - -#define DMA_IFLAG_CH1DONEIF_POS 1U -#define DMA_IFLAG_CH1DONEIF_MSK BIT(DMA_IFLAG_CH1DONEIF_POS) - -#define DMA_IFLAG_CH0DONEIF_POS 0U -#define DMA_IFLAG_CH0DONEIF_MSK BIT(DMA_IFLAG_CH0DONEIF_POS) - -/****************** Bit definition for DMA_ICFR register ************************/ - -#define DMA_ICFR_DMAERRC_POS 31U -#define DMA_ICFR_DMAERRC_MSK BIT(DMA_ICFR_DMAERRC_POS) - -#define DMA_ICFR_CH5DONEC_POS 5U -#define DMA_ICFR_CH5DONEC_MSK BIT(DMA_ICFR_CH5DONEC_POS) - -#define DMA_ICFR_CH4DONEC_POS 4U -#define DMA_ICFR_CH4DONEC_MSK BIT(DMA_ICFR_CH4DONEC_POS) - -#define DMA_ICFR_CH3DONEC_POS 3U -#define DMA_ICFR_CH3DONEC_MSK BIT(DMA_ICFR_CH3DONEC_POS) - -#define DMA_ICFR_CH2DONEC_POS 2U -#define DMA_ICFR_CH2DONEC_MSK BIT(DMA_ICFR_CH2DONEC_POS) - -#define DMA_ICFR_CH1DONEC_POS 1U -#define DMA_ICFR_CH1DONEC_MSK BIT(DMA_ICFR_CH1DONEC_POS) - -#define DMA_ICFR_CH0DONEC_POS 0U -#define DMA_ICFR_CH0DONEC_MSK BIT(DMA_ICFR_CH0DONEC_POS) - -/****************** Bit definition for DMA_IER register ************************/ - -#define DMA_IER_DMAERRIE_POS 31U -#define DMA_IER_DMAERRIE_MSK BIT(DMA_IER_DMAERRIE_POS) - -#define DMA_IER_CH5DONEIE_POS 5U -#define DMA_IER_CH5DONEIE_MSK BIT(DMA_IER_CH5DONEIE_POS) - -#define DMA_IER_CH4DONEIE_POS 4U -#define DMA_IER_CH4DONEIE_MSK BIT(DMA_IER_CH4DONEIE_POS) - -#define DMA_IER_CH3DONEIE_POS 3U -#define DMA_IER_CH3DONEIE_MSK BIT(DMA_IER_CH3DONEIE_POS) - -#define DMA_IER_CH2DONEIE_POS 2U -#define DMA_IER_CH2DONEIE_MSK BIT(DMA_IER_CH2DONEIE_POS) - -#define DMA_IER_CH1DONEIE_POS 1U -#define DMA_IER_CH1DONEIE_MSK BIT(DMA_IER_CH1DONEIE_POS) - -#define DMA_IER_CH0DONEIE_POS 0U -#define DMA_IER_CH0DONEIE_MSK BIT(DMA_IER_CH0DONEIE_POS) - -/****************** Bit definition for DMA_CH0_SELCON register ************************/ - -#define DMA_CH0_SELCON_MSEL_POSS 8U -#define DMA_CH0_SELCON_MSEL_POSE 13U -#define DMA_CH0_SELCON_MSEL_MSK BITS(DMA_CH0_SELCON_MSEL_POSS,DMA_CH0_SELCON_MSEL_POSE) - -#define DMA_CH0_SELCON_MSIGSEL_POSS 0U -#define DMA_CH0_SELCON_MSIGSEL_POSE 3U -#define DMA_CH0_SELCON_MSIGSEL_MSK BITS(DMA_CH0_SELCON_MSIGSEL_POSS,DMA_CH0_SELCON_MSIGSEL_POSE) - -typedef struct -{ - __I uint32_t STATUS; - __IO uint32_t CFG; - __IO uint32_t CTRLBASE; - __I uint32_t ALTCTRLBASE; - __I uint32_t CHWAITSTATUS; - __IO uint32_t CHSWREQ; - __IO uint32_t CHUSEBURSTSET; - __O uint32_t CHUSEBURSTCLR; - __IO uint32_t CHREQMASKSET; - __O uint32_t CHREQMASKCLR; - __IO uint32_t CHENSET; - __O uint32_t CHENCLR; - __IO uint32_t CHPRIALTSET; - __O uint32_t CHPRIALTCLR; - __IO uint32_t CHPRSET; - __O uint32_t CHPRCLR; - uint32_t RESERVED0[3] ; - __IO uint32_t ERRCLR; - uint32_t RESERVED1[1004] ; - __I uint32_t IFLAG; - uint32_t RESERVED2 ; - __O uint32_t ICFR; - __IO uint32_t IER; - uint32_t RESERVED3[60] ; - __IO uint32_t CH_SELCON[6]; -} DMA_TypeDef; - -/****************** Bit definition for PIS_CH0_CON register ************************/ - -#define PIS_CH0_CON_SYNCSEL_POSS 24U -#define PIS_CH0_CON_SYNCSEL_POSE 26U -#define PIS_CH0_CON_SYNCSEL_MSK BITS(PIS_CH0_CON_SYNCSEL_POSS,PIS_CH0_CON_SYNCSEL_POSE) - -#define PIS_CH0_CON_PULCK_POSS 18U -#define PIS_CH0_CON_PULCK_POSE 19U -#define PIS_CH0_CON_PULCK_MSK BITS(PIS_CH0_CON_PULCK_POSS,PIS_CH0_CON_PULCK_POSE) - -#define PIS_CH0_CON_EDGS_POSS 16U -#define PIS_CH0_CON_EDGS_POSE 17U -#define PIS_CH0_CON_EDGS_MSK BITS(PIS_CH0_CON_EDGS_POSS,PIS_CH0_CON_EDGS_POSE) - -#define PIS_CH0_CON_SRCS_POSS 8U -#define PIS_CH0_CON_SRCS_POSE 13U -#define PIS_CH0_CON_SRCS_MSK BITS(PIS_CH0_CON_SRCS_POSS,PIS_CH0_CON_SRCS_POSE) - -#define PIS_CH0_CON_MSIGS_POSS 0U -#define PIS_CH0_CON_MSIGS_POSE 3U -#define PIS_CH0_CON_MSIGS_MSK BITS(PIS_CH0_CON_MSIGS_POSS,PIS_CH0_CON_MSIGS_POSE) - -/****************** Bit definition for PIS_CH_OER register ************************/ - -#define PIS_CH_OER_CH3OE_POS 3U -#define PIS_CH_OER_CH3OE_MSK BIT(PIS_CH_OER_CH3OE_POS) - -#define PIS_CH_OER_CH2OE_POS 2U -#define PIS_CH_OER_CH2OE_MSK BIT(PIS_CH_OER_CH2OE_POS) - -#define PIS_CH_OER_CH1OE_POS 1U -#define PIS_CH_OER_CH1OE_MSK BIT(PIS_CH_OER_CH1OE_POS) - -#define PIS_CH_OER_CH0OE_POS 0U -#define PIS_CH_OER_CH0OE_MSK BIT(PIS_CH_OER_CH0OE_POS) - -/****************** Bit definition for PIS_TAR_CON0 register ************************/ - -#define PIS_TAR_CON0_TIM3_CH2IN_SEL_POS 25U -#define PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH2IN_SEL_POS) - -#define PIS_TAR_CON0_TIM3_CH1IN_SEL_POS 24U -#define PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH1IN_SEL_POS) - -#define PIS_TAR_CON0_TIM2_CH2IN_SEL_POS 17U -#define PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH2IN_SEL_POS) - -#define PIS_TAR_CON0_TIM2_CH1IN_SEL_POS 16U -#define PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH1IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_BRKIN_SEL_POS 4U -#define PIS_TAR_CON0_TIM0_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_BRKIN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH4IN_SEL_POS 3U -#define PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH4IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH3IN_SEL_POS 2U -#define PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH3IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH2IN_SEL_POS 1U -#define PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH2IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH1IN_SEL_POS 0U -#define PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH1IN_SEL_POS) - -/****************** Bit definition for PIS_TAR_CON1 register ************************/ - -#define PIS_TAR_CON1_SPI1_CLK_SEL_POS 15U -#define PIS_TAR_CON1_SPI1_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI1_CLK_SEL_POS) - -#define PIS_TAR_CON1_SPI1_RX_SEL_POS 14U -#define PIS_TAR_CON1_SPI1_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI1_RX_SEL_POS) - -#define PIS_TAR_CON1_SPI0_CLK_SEL_POS 13U -#define PIS_TAR_CON1_SPI0_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI0_CLK_SEL_POS) - -#define PIS_TAR_CON1_SPI0_RX_SEL_POS 12U -#define PIS_TAR_CON1_SPI0_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI0_RX_SEL_POS) - -#define PIS_TAR_CON1_LPUART0_RXD_SEL_POS 8U -#define PIS_TAR_CON1_LPUART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_LPUART0_RXD_SEL_POS) - -#define PIS_TAR_CON1_USART1_RXD_SEL_POS 7U -#define PIS_TAR_CON1_USART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART1_RXD_SEL_POS) - -#define PIS_TAR_CON1_USART0_RXD_SEL_POS 6U -#define PIS_TAR_CON1_USART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART0_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART3_RXD_SEL_POS 3U -#define PIS_TAR_CON1_UART3_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART3_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART2_RXD_SEL_POS 2U -#define PIS_TAR_CON1_UART2_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART2_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART1_RXD_SEL_POS 1U -#define PIS_TAR_CON1_UART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART1_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART0_RXD_SEL_POS 0U -#define PIS_TAR_CON1_UART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART0_RXD_SEL_POS) - -/****************** Bit definition for PIS_TXMCR register ************************/ - -#define PIS_TXMCR_TXMLVLS_POS 8U -#define PIS_TXMCR_TXMLVLS_MSK BIT(PIS_TXMCR_TXMLVLS_POS) - -#define PIS_TXMCR_TXMSS_POSS 4U -#define PIS_TXMCR_TXMSS_POSE 7U -#define PIS_TXMCR_TXMSS_MSK BITS(PIS_TXMCR_TXMSS_POSS,PIS_TXMCR_TXMSS_POSE) - -#define PIS_TXMCR_TXSIGS_POSS 0U -#define PIS_TXMCR_TXSIGS_POSE 3U -#define PIS_TXMCR_TXSIGS_MSK BITS(PIS_TXMCR_TXSIGS_POSS,PIS_TXMCR_TXSIGS_POSE) - -typedef struct -{ - __IO uint32_t CH_CON[8]; - uint32_t RESERVED0[8] ; - __IO uint32_t CH_OER; - __IO uint32_t TAR_CON0; - __IO uint32_t TAR_CON1; - uint32_t RESERVED1[5] ; - __IO uint32_t UART0_TXMCR; - __IO uint32_t UART1_TXMCR; - __IO uint32_t UART2_TXMCR; - __IO uint32_t UART3_TXMCR; - __IO uint32_t LPUART0_TXMCR; -} PIS_TypeDef; - -/****************** Bit definition for GPIO_DIN register ************************/ - -#define GPIO_DIN_DIN_POSS 0U -#define GPIO_DIN_DIN_POSE 15U -#define GPIO_DIN_DIN_MSK BITS(GPIO_DIN_DIN_POSS,GPIO_DIN_DIN_POSE) - -/****************** Bit definition for GPIO_DOUT register ************************/ - -#define GPIO_DOUT_DOUT_POSS 0U -#define GPIO_DOUT_DOUT_POSE 15U -#define GPIO_DOUT_DOUT_MSK BITS(GPIO_DOUT_DOUT_POSS,GPIO_DOUT_DOUT_POSE) - -/****************** Bit definition for GPIO_BSRR register ************************/ - -#define GPIO_BSRR_BRR_POSS 16U -#define GPIO_BSRR_BRR_POSE 31U -#define GPIO_BSRR_BRR_MSK BITS(GPIO_BSRR_BRR_POSS,GPIO_BSRR_BRR_POSE) - -#define GPIO_BSRR_BSR_POSS 0U -#define GPIO_BSRR_BSR_POSE 15U -#define GPIO_BSRR_BSR_MSK BITS(GPIO_BSRR_BSR_POSS,GPIO_BSRR_BSR_POSE) - -/****************** Bit definition for GPIO_BIR register ************************/ - -#define GPIO_BIR_BIR_POSS 0U -#define GPIO_BIR_BIR_POSE 15U -#define GPIO_BIR_BIR_MSK BITS(GPIO_BIR_BIR_POSS,GPIO_BIR_BIR_POSE) - -/****************** Bit definition for GPIO_MODE register ************************/ - -#define GPIO_MODE_MODE_POSS 0U -#define GPIO_MODE_MODE_POSE 31U -#define GPIO_MODE_MODE_MSK BITS(GPIO_MODE_MODE_POSS,GPIO_MODE_MODE_POSE) - -/****************** Bit definition for GPIO_ODOS register ************************/ - -#define GPIO_ODOS_ODOS_POSS 0U -#define GPIO_ODOS_ODOS_POSE 31U -#define GPIO_ODOS_ODOS_MSK BITS(GPIO_ODOS_ODOS_POSS,GPIO_ODOS_ODOS_POSE) - -/****************** Bit definition for GPIO_PUPD register ************************/ - -#define GPIO_PUPD_PUPD_POSS 0U -#define GPIO_PUPD_PUPD_POSE 31U -#define GPIO_PUPD_PUPD_MSK BITS(GPIO_PUPD_PUPD_POSS,GPIO_PUPD_PUPD_POSE) - -/****************** Bit definition for GPIO_ODRV register ************************/ - -#define GPIO_ODRV_ODRV_POSS 0U -#define GPIO_ODRV_ODRV_POSE 31U -#define GPIO_ODRV_ODRV_MSK BITS(GPIO_ODRV_ODRV_POSS,GPIO_ODRV_ODRV_POSE) - -/****************** Bit definition for GPIO_FLT register ************************/ - -#define GPIO_FLT_FLT_POSS 0U -#define GPIO_FLT_FLT_POSE 15U -#define GPIO_FLT_FLT_MSK BITS(GPIO_FLT_FLT_POSS,GPIO_FLT_FLT_POSE) - -/****************** Bit definition for GPIO_TYPE register ************************/ - -#define GPIO_TYPE_TYPE_POSS 0U -#define GPIO_TYPE_TYPE_POSE 15U -#define GPIO_TYPE_TYPE_MSK BITS(GPIO_TYPE_TYPE_POSS,GPIO_TYPE_TYPE_POSE) - -/****************** Bit definition for GPIO_FUNC0 register ************************/ - -#define GPIO_FUNC0_FSEL_IO7_POSS 28U -#define GPIO_FUNC0_FSEL_IO7_POSE 31U -#define GPIO_FUNC0_FSEL_IO7_MSK BITS(GPIO_FUNC0_FSEL_IO7_POSS,GPIO_FUNC0_FSEL_IO7_POSE) - -#define GPIO_FUNC0_FSEL_IO6_POSS 24U -#define GPIO_FUNC0_FSEL_IO6_POSE 27U -#define GPIO_FUNC0_FSEL_IO6_MSK BITS(GPIO_FUNC0_FSEL_IO6_POSS,GPIO_FUNC0_FSEL_IO6_POSE) - -#define GPIO_FUNC0_FSEL_IO5_POSS 20U -#define GPIO_FUNC0_FSEL_IO5_POSE 23U -#define GPIO_FUNC0_FSEL_IO5_MSK BITS(GPIO_FUNC0_FSEL_IO5_POSS,GPIO_FUNC0_FSEL_IO5_POSE) - -#define GPIO_FUNC0_FSEL_IO4_POSS 16U -#define GPIO_FUNC0_FSEL_IO4_POSE 19U -#define GPIO_FUNC0_FSEL_IO4_MSK BITS(GPIO_FUNC0_FSEL_IO4_POSS,GPIO_FUNC0_FSEL_IO4_POSE) - -#define GPIO_FUNC0_FSEL_IO3_POSS 12U -#define GPIO_FUNC0_FSEL_IO3_POSE 15U -#define GPIO_FUNC0_FSEL_IO3_MSK BITS(GPIO_FUNC0_FSEL_IO3_POSS,GPIO_FUNC0_FSEL_IO3_POSE) - -#define GPIO_FUNC0_FSEL_IO2_POSS 8U -#define GPIO_FUNC0_FSEL_IO2_POSE 11U -#define GPIO_FUNC0_FSEL_IO2_MSK BITS(GPIO_FUNC0_FSEL_IO2_POSS,GPIO_FUNC0_FSEL_IO2_POSE) - -#define GPIO_FUNC0_FSEL_IO1_POSS 4U -#define GPIO_FUNC0_FSEL_IO1_POSE 7U -#define GPIO_FUNC0_FSEL_IO1_MSK BITS(GPIO_FUNC0_FSEL_IO1_POSS,GPIO_FUNC0_FSEL_IO1_POSE) - -#define GPIO_FUNC0_FSEL_IO0_POSS 0U -#define GPIO_FUNC0_FSEL_IO0_POSE 3U -#define GPIO_FUNC0_FSEL_IO0_MSK BITS(GPIO_FUNC0_FSEL_IO0_POSS,GPIO_FUNC0_FSEL_IO0_POSE) - -/****************** Bit definition for GPIO_FUNC1 register ************************/ - -#define GPIO_FUNC1_FSEL_IO15_POSS 28U -#define GPIO_FUNC1_FSEL_IO15_POSE 31U -#define GPIO_FUNC1_FSEL_IO15_MSK BITS(GPIO_FUNC1_FSEL_IO15_POSS,GPIO_FUNC1_FSEL_IO15_POSE) - -#define GPIO_FUNC1_FSEL_IO14_POSS 24U -#define GPIO_FUNC1_FSEL_IO14_POSE 27U -#define GPIO_FUNC1_FSEL_IO14_MSK BITS(GPIO_FUNC1_FSEL_IO14_POSS,GPIO_FUNC1_FSEL_IO14_POSE) - -#define GPIO_FUNC1_FSEL_IO13_POSS 20U -#define GPIO_FUNC1_FSEL_IO13_POSE 23U -#define GPIO_FUNC1_FSEL_IO13_MSK BITS(GPIO_FUNC1_FSEL_IO13_POSS,GPIO_FUNC1_FSEL_IO13_POSE) - -#define GPIO_FUNC1_FSEL_IO12_POSS 16U -#define GPIO_FUNC1_FSEL_IO12_POSE 19U -#define GPIO_FUNC1_FSEL_IO12_MSK BITS(GPIO_FUNC1_FSEL_IO12_POSS,GPIO_FUNC1_FSEL_IO12_POSE) - -#define GPIO_FUNC1_FSEL_IO11_POSS 12U -#define GPIO_FUNC1_FSEL_IO11_POSE 15U -#define GPIO_FUNC1_FSEL_IO11_MSK BITS(GPIO_FUNC1_FSEL_IO11_POSS,GPIO_FUNC1_FSEL_IO11_POSE) - -#define GPIO_FUNC1_FSEL_IO10_POSS 8U -#define GPIO_FUNC1_FSEL_IO10_POSE 11U -#define GPIO_FUNC1_FSEL_IO10_MSK BITS(GPIO_FUNC1_FSEL_IO10_POSS,GPIO_FUNC1_FSEL_IO10_POSE) - -#define GPIO_FUNC1_FSEL_IO9_POSS 4U -#define GPIO_FUNC1_FSEL_IO9_POSE 7U -#define GPIO_FUNC1_FSEL_IO9_MSK BITS(GPIO_FUNC1_FSEL_IO9_POSS,GPIO_FUNC1_FSEL_IO9_POSE) - -#define GPIO_FUNC1_FSEL_IO8_POSS 0U -#define GPIO_FUNC1_FSEL_IO8_POSE 3U -#define GPIO_FUNC1_FSEL_IO8_MSK BITS(GPIO_FUNC1_FSEL_IO8_POSS,GPIO_FUNC1_FSEL_IO8_POSE) - -/****************** Bit definition for GPIO_LOCK register ************************/ - -#define GPIO_LOCK_KEY_POSS 16U -#define GPIO_LOCK_KEY_POSE 31U -#define GPIO_LOCK_KEY_MSK BITS(GPIO_LOCK_KEY_POSS,GPIO_LOCK_KEY_POSE) - -#define GPIO_LOCK_LOCK_POSS 0U -#define GPIO_LOCK_LOCK_POSE 15U -#define GPIO_LOCK_LOCK_MSK BITS(GPIO_LOCK_LOCK_POSS,GPIO_LOCK_LOCK_POSE) - -typedef struct -{ - __I uint32_t DIN; - __IO uint32_t DOUT; - __O uint32_t BSRR; - __O uint32_t BIR; - __IO uint32_t MODE; - __IO uint32_t ODOS; - __IO uint32_t PUPD; - __IO uint32_t ODRV; - __IO uint32_t FLT; - __IO uint32_t TYPE; - __IO uint32_t FUNC0; - __IO uint32_t FUNC1; - __IO uint32_t LOCK; -} GPIO_TypeDef; - -/****************** Bit definition for GPIO_EXTIRER register ************************/ - -#define GPIO_EXTIRER_EXTIRER_POSS 0U -#define GPIO_EXTIRER_EXTIRER_POSE 15U -#define GPIO_EXTIRER_EXTIRER_MSK BITS(GPIO_EXTIRER_EXTIRER_POSS,GPIO_EXTIRER_EXTIRER_POSE) - -/****************** Bit definition for GPIO_EXTIFER register ************************/ - -#define GPIO_EXTIFER_EXTIFER_POSS 0U -#define GPIO_EXTIFER_EXTIFER_POSE 15U -#define GPIO_EXTIFER_EXTIFER_MSK BITS(GPIO_EXTIFER_EXTIFER_POSS,GPIO_EXTIFER_EXTIFER_POSE) - -/****************** Bit definition for GPIO_EXTIEN register ************************/ - -#define GPIO_EXTIEN_EXTIEN_POSS 0U -#define GPIO_EXTIEN_EXTIEN_POSE 15U -#define GPIO_EXTIEN_EXTIEN_MSK BITS(GPIO_EXTIEN_EXTIEN_POSS,GPIO_EXTIEN_EXTIEN_POSE) - -/****************** Bit definition for GPIO_EXTIFLAG register ************************/ - -#define GPIO_EXTIFLAG_EXTIFLAG_POSS 0U -#define GPIO_EXTIFLAG_EXTIFLAG_POSE 15U -#define GPIO_EXTIFLAG_EXTIFLAG_MSK BITS(GPIO_EXTIFLAG_EXTIFLAG_POSS,GPIO_EXTIFLAG_EXTIFLAG_POSE) - -/****************** Bit definition for GPIO_EXTISFR register ************************/ - -#define GPIO_EXTISFR_EXTISFR_POSS 0U -#define GPIO_EXTISFR_EXTISFR_POSE 15U -#define GPIO_EXTISFR_EXTISFR_MSK BITS(GPIO_EXTISFR_EXTISFR_POSS,GPIO_EXTISFR_EXTISFR_POSE) - -/****************** Bit definition for GPIO_EXTICFR register ************************/ - -#define GPIO_EXTICFR_EXTICFR_POSS 0U -#define GPIO_EXTICFR_EXTICFR_POSE 15U -#define GPIO_EXTICFR_EXTICFR_MSK BITS(GPIO_EXTICFR_EXTICFR_POSS,GPIO_EXTICFR_EXTICFR_POSE) - -/****************** Bit definition for GPIO_EXTIPSR0 register ************************/ - -#define GPIO_EXTIPSR0_EXTIS7_POSS 28U -#define GPIO_EXTIPSR0_EXTIS7_POSE 30U -#define GPIO_EXTIPSR0_EXTIS7_MSK BITS(GPIO_EXTIPSR0_EXTIS7_POSS,GPIO_EXTIPSR0_EXTIS7_POSE) - -#define GPIO_EXTIPSR0_EXTIS6_POSS 24U -#define GPIO_EXTIPSR0_EXTIS6_POSE 26U -#define GPIO_EXTIPSR0_EXTIS6_MSK BITS(GPIO_EXTIPSR0_EXTIS6_POSS,GPIO_EXTIPSR0_EXTIS6_POSE) - -#define GPIO_EXTIPSR0_EXTIS5_POSS 20U -#define GPIO_EXTIPSR0_EXTIS5_POSE 22U -#define GPIO_EXTIPSR0_EXTIS5_MSK BITS(GPIO_EXTIPSR0_EXTIS5_POSS,GPIO_EXTIPSR0_EXTIS5_POSE) - -#define GPIO_EXTIPSR0_EXTIS4_POSS 16U -#define GPIO_EXTIPSR0_EXTIS4_POSE 18U -#define GPIO_EXTIPSR0_EXTIS4_MSK BITS(GPIO_EXTIPSR0_EXTIS4_POSS,GPIO_EXTIPSR0_EXTIS4_POSE) - -#define GPIO_EXTIPSR0_EXTIS3_POSS 12U -#define GPIO_EXTIPSR0_EXTIS3_POSE 14U -#define GPIO_EXTIPSR0_EXTIS3_MSK BITS(GPIO_EXTIPSR0_EXTIS3_POSS,GPIO_EXTIPSR0_EXTIS3_POSE) - -#define GPIO_EXTIPSR0_EXTIS2_POSS 8U -#define GPIO_EXTIPSR0_EXTIS2_POSE 10U -#define GPIO_EXTIPSR0_EXTIS2_MSK BITS(GPIO_EXTIPSR0_EXTIS2_POSS,GPIO_EXTIPSR0_EXTIS2_POSE) - -#define GPIO_EXTIPSR0_EXTIS1_POSS 4U -#define GPIO_EXTIPSR0_EXTIS1_POSE 6U -#define GPIO_EXTIPSR0_EXTIS1_MSK BITS(GPIO_EXTIPSR0_EXTIS1_POSS,GPIO_EXTIPSR0_EXTIS1_POSE) - -#define GPIO_EXTIPSR0_EXTIS0_POSS 0U -#define GPIO_EXTIPSR0_EXTIS0_POSE 2U -#define GPIO_EXTIPSR0_EXTIS0_MSK BITS(GPIO_EXTIPSR0_EXTIS0_POSS,GPIO_EXTIPSR0_EXTIS0_POSE) - -/****************** Bit definition for GPIO_EXTIPSR1 register ************************/ - -#define GPIO_EXTIPSR1_EXTIS15_POSS 28U -#define GPIO_EXTIPSR1_EXTIS15_POSE 30U -#define GPIO_EXTIPSR1_EXTIS15_MSK BITS(GPIO_EXTIPSR1_EXTIS15_POSS,GPIO_EXTIPSR1_EXTIS15_POSE) - -#define GPIO_EXTIPSR1_EXTIS14_POSS 24U -#define GPIO_EXTIPSR1_EXTIS14_POSE 26U -#define GPIO_EXTIPSR1_EXTIS14_MSK BITS(GPIO_EXTIPSR1_EXTIS14_POSS,GPIO_EXTIPSR1_EXTIS14_POSE) - -#define GPIO_EXTIPSR1_EXTIS13_POSS 20U -#define GPIO_EXTIPSR1_EXTIS13_POSE 22U -#define GPIO_EXTIPSR1_EXTIS13_MSK BITS(GPIO_EXTIPSR1_EXTIS13_POSS,GPIO_EXTIPSR1_EXTIS13_POSE) - -#define GPIO_EXTIPSR1_EXTIS12_POSS 16U -#define GPIO_EXTIPSR1_EXTIS12_POSE 18U -#define GPIO_EXTIPSR1_EXTIS12_MSK BITS(GPIO_EXTIPSR1_EXTIS12_POSS,GPIO_EXTIPSR1_EXTIS12_POSE) - -#define GPIO_EXTIPSR1_EXTIS11_POSS 12U -#define GPIO_EXTIPSR1_EXTIS11_POSE 14U -#define GPIO_EXTIPSR1_EXTIS11_MSK BITS(GPIO_EXTIPSR1_EXTIS11_POSS,GPIO_EXTIPSR1_EXTIS11_POSE) - -#define GPIO_EXTIPSR1_EXTIS10_POSS 8U -#define GPIO_EXTIPSR1_EXTIS10_POSE 10U -#define GPIO_EXTIPSR1_EXTIS10_MSK BITS(GPIO_EXTIPSR1_EXTIS10_POSS,GPIO_EXTIPSR1_EXTIS10_POSE) - -#define GPIO_EXTIPSR1_EXTIS9_POSS 4U -#define GPIO_EXTIPSR1_EXTIS9_POSE 6U -#define GPIO_EXTIPSR1_EXTIS9_MSK BITS(GPIO_EXTIPSR1_EXTIS9_POSS,GPIO_EXTIPSR1_EXTIS9_POSE) - -#define GPIO_EXTIPSR1_EXTIS8_POSS 0U -#define GPIO_EXTIPSR1_EXTIS8_POSE 2U -#define GPIO_EXTIPSR1_EXTIS8_MSK BITS(GPIO_EXTIPSR1_EXTIS8_POSS,GPIO_EXTIPSR1_EXTIS8_POSE) - -/****************** Bit definition for GPIO_EXTIFLTCR register ************************/ - -#define GPIO_EXTIFLTCR_FLTCKS_POSS 24U -#define GPIO_EXTIFLTCR_FLTCKS_POSE 25U -#define GPIO_EXTIFLTCR_FLTCKS_MSK BITS(GPIO_EXTIFLTCR_FLTCKS_POSS,GPIO_EXTIFLTCR_FLTCKS_POSE) - -#define GPIO_EXTIFLTCR_FLTSEL_POSS 16U -#define GPIO_EXTIFLTCR_FLTSEL_POSE 23U -#define GPIO_EXTIFLTCR_FLTSEL_MSK BITS(GPIO_EXTIFLTCR_FLTSEL_POSS,GPIO_EXTIFLTCR_FLTSEL_POSE) - -#define GPIO_EXTIFLTCR_FLTEN_POSS 0U -#define GPIO_EXTIFLTCR_FLTEN_POSE 15U -#define GPIO_EXTIFLTCR_FLTEN_MSK BITS(GPIO_EXTIFLTCR_FLTEN_POSS,GPIO_EXTIFLTCR_FLTEN_POSE) - -typedef struct -{ - __IO uint32_t EXTIRER; - uint32_t RESERVED0 ; - __IO uint32_t EXTIFER; - uint32_t RESERVED1 ; - __IO uint32_t EXTIEN; - uint32_t RESERVED2 ; - __I uint32_t EXTIFLAG; - uint32_t RESERVED3 ; - __O uint32_t EXTISFR; - uint32_t RESERVED4 ; - __O uint32_t EXTICFR; - uint32_t RESERVED5 ; - __IO uint32_t EXTIPSR0; - __IO uint32_t EXTIPSR1; - uint32_t RESERVED6[2] ; - __IO uint32_t EXTIFLTCR; -} EXTI_TypeDef; - -/****************** Bit definition for RTC_WPR register ************************/ - -#define RTC_WPR_WP_POS 0U -#define RTC_WPR_WP_MSK BIT(RTC_WPR_WP_POS) - -/****************** Bit definition for RTC_CON register ************************/ - -#define RTC_CON_SSEC_POS 25U -#define RTC_CON_SSEC_MSK BIT(RTC_CON_SSEC_POS) - -#define RTC_CON_BUSY_POS 24U -#define RTC_CON_BUSY_MSK BIT(RTC_CON_BUSY_POS) - -#define RTC_CON_POL_POS 22U -#define RTC_CON_POL_MSK BIT(RTC_CON_POL_POS) - -#define RTC_CON_EOS_POSS 20U -#define RTC_CON_EOS_POSE 21U -#define RTC_CON_EOS_MSK BITS(RTC_CON_EOS_POSS,RTC_CON_EOS_POSE) - -#define RTC_CON_CKOS_POSS 17U -#define RTC_CON_CKOS_POSE 19U -#define RTC_CON_CKOS_MSK BITS(RTC_CON_CKOS_POSS,RTC_CON_CKOS_POSE) - -#define RTC_CON_CKOE_POS 16U -#define RTC_CON_CKOE_MSK BIT(RTC_CON_CKOE_POS) - -#define RTC_CON_WUCKS_POSS 13U -#define RTC_CON_WUCKS_POSE 15U -#define RTC_CON_WUCKS_MSK BITS(RTC_CON_WUCKS_POSS,RTC_CON_WUCKS_POSE) - -#define RTC_CON_WUTE_POS 12U -#define RTC_CON_WUTE_MSK BIT(RTC_CON_WUTE_POS) - -#define RTC_CON_DSTS_POS 10U -#define RTC_CON_DSTS_MSK BIT(RTC_CON_DSTS_POS) - -#define RTC_CON_SUB1H_POS 9U -#define RTC_CON_SUB1H_MSK BIT(RTC_CON_SUB1H_POS) - -#define RTC_CON_ADD1H_POS 8U -#define RTC_CON_ADD1H_MSK BIT(RTC_CON_ADD1H_POS) - -#define RTC_CON_TSPIN_POS 7U -#define RTC_CON_TSPIN_MSK BIT(RTC_CON_TSPIN_POS) - -#define RTC_CON_TSSEL_POS 6U -#define RTC_CON_TSSEL_MSK BIT(RTC_CON_TSSEL_POS) - -#define RTC_CON_TSEN_POS 5U -#define RTC_CON_TSEN_MSK BIT(RTC_CON_TSEN_POS) - -#define RTC_CON_SHDBP_POS 4U -#define RTC_CON_SHDBP_MSK BIT(RTC_CON_SHDBP_POS) - -#define RTC_CON_HFM_POS 3U -#define RTC_CON_HFM_MSK BIT(RTC_CON_HFM_POS) - -#define RTC_CON_ALMBEN_POS 2U -#define RTC_CON_ALMBEN_MSK BIT(RTC_CON_ALMBEN_POS) - -#define RTC_CON_ALMAEN_POS 1U -#define RTC_CON_ALMAEN_MSK BIT(RTC_CON_ALMAEN_POS) - -#define RTC_CON_GO_POS 0U -#define RTC_CON_GO_MSK BIT(RTC_CON_GO_POS) - -/****************** Bit definition for RTC_PSR register ************************/ - -#define RTC_PSR_APRS_POSS 16U -#define RTC_PSR_APRS_POSE 22U -#define RTC_PSR_APRS_MSK BITS(RTC_PSR_APRS_POSS,RTC_PSR_APRS_POSE) - -#define RTC_PSR_SPRS_POSS 0U -#define RTC_PSR_SPRS_POSE 14U -#define RTC_PSR_SPRS_MSK BITS(RTC_PSR_SPRS_POSS,RTC_PSR_SPRS_POSE) - -/****************** Bit definition for RTC_TAMPCON register ************************/ - -#define RTC_TAMPCON_TAMPFLT_POSS 20U -#define RTC_TAMPCON_TAMPFLT_POSE 21U -#define RTC_TAMPCON_TAMPFLT_MSK BITS(RTC_TAMPCON_TAMPFLT_POSS,RTC_TAMPCON_TAMPFLT_POSE) - -#define RTC_TAMPCON_TAMPCKS_POSS 17U -#define RTC_TAMPCON_TAMPCKS_POSE 19U -#define RTC_TAMPCON_TAMPCKS_MSK BITS(RTC_TAMPCON_TAMPCKS_POSS,RTC_TAMPCON_TAMPCKS_POSE) - -#define RTC_TAMPCON_TAMPTS_POS 16U -#define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS) - -#define RTC_TAMPCON_TAMP2LV_POS 9U -#define RTC_TAMPCON_TAMP2LV_MSK BIT(RTC_TAMPCON_TAMP2LV_POS) - -#define RTC_TAMPCON_TAMP2EN_POS 8U -#define RTC_TAMPCON_TAMP2EN_MSK BIT(RTC_TAMPCON_TAMP2EN_POS) - -#define RTC_TAMPCON_TAMP1LV_POS 1U -#define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS) - -#define RTC_TAMPCON_TAMP1EN_POS 0U -#define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS) - -/****************** Bit definition for RTC_TIME register ************************/ - -#define RTC_TIME_PM_POS 22U -#define RTC_TIME_PM_MSK BIT(RTC_TIME_PM_POS) - -#define RTC_TIME_HRT_POSS 20U -#define RTC_TIME_HRT_POSE 21U -#define RTC_TIME_HRT_MSK BITS(RTC_TIME_HRT_POSS,RTC_TIME_HRT_POSE) - -#define RTC_TIME_HRU_POSS 16U -#define RTC_TIME_HRU_POSE 19U -#define RTC_TIME_HRU_MSK BITS(RTC_TIME_HRU_POSS,RTC_TIME_HRU_POSE) - -#define RTC_TIME_MINT_POSS 12U -#define RTC_TIME_MINT_POSE 14U -#define RTC_TIME_MINT_MSK BITS(RTC_TIME_MINT_POSS,RTC_TIME_MINT_POSE) - -#define RTC_TIME_MINU_POSS 8U -#define RTC_TIME_MINU_POSE 11U -#define RTC_TIME_MINU_MSK BITS(RTC_TIME_MINU_POSS,RTC_TIME_MINU_POSE) - -#define RTC_TIME_SECT_POSS 4U -#define RTC_TIME_SECT_POSE 6U -#define RTC_TIME_SECT_MSK BITS(RTC_TIME_SECT_POSS,RTC_TIME_SECT_POSE) - -#define RTC_TIME_SECU_POSS 0U -#define RTC_TIME_SECU_POSE 3U -#define RTC_TIME_SECU_MSK BITS(RTC_TIME_SECU_POSS,RTC_TIME_SECU_POSE) - -/****************** Bit definition for RTC_DATE register ************************/ - -#define RTC_DATE_WD_POSS 24U -#define RTC_DATE_WD_POSE 26U -#define RTC_DATE_WD_MSK BITS(RTC_DATE_WD_POSS,RTC_DATE_WD_POSE) - -#define RTC_DATE_YRT_POSS 20U -#define RTC_DATE_YRT_POSE 23U -#define RTC_DATE_YRT_MSK BITS(RTC_DATE_YRT_POSS,RTC_DATE_YRT_POSE) - -#define RTC_DATE_YRU_POSS 16U -#define RTC_DATE_YRU_POSE 19U -#define RTC_DATE_YRU_MSK BITS(RTC_DATE_YRU_POSS,RTC_DATE_YRU_POSE) - -#define RTC_DATE_MONT_POS 12U -#define RTC_DATE_MONT_MSK BIT(RTC_DATE_MONT_POS) - -#define RTC_DATE_MONU_POSS 8U -#define RTC_DATE_MONU_POSE 11U -#define RTC_DATE_MONU_MSK BITS(RTC_DATE_MONU_POSS,RTC_DATE_MONU_POSE) - -#define RTC_DATE_DAYT_POSS 4U -#define RTC_DATE_DAYT_POSE 5U -#define RTC_DATE_DAYT_MSK BITS(RTC_DATE_DAYT_POSS,RTC_DATE_DAYT_POSE) - -#define RTC_DATE_DAYU_POSS 0U -#define RTC_DATE_DAYU_POSE 3U -#define RTC_DATE_DAYU_MSK BITS(RTC_DATE_DAYU_POSS,RTC_DATE_DAYU_POSE) - -/****************** Bit definition for RTC_SSEC register ************************/ - -#define RTC_SSEC_VAL_POSS 0U -#define RTC_SSEC_VAL_POSE 15U -#define RTC_SSEC_VAL_MSK BITS(RTC_SSEC_VAL_POSS,RTC_SSEC_VAL_POSE) - -/****************** Bit definition for RTC_WUMAT register ************************/ - -#define RTC_WUMAT_VAL_POSS 0U -#define RTC_WUMAT_VAL_POSE 15U -#define RTC_WUMAT_VAL_MSK BITS(RTC_WUMAT_VAL_POSS,RTC_WUMAT_VAL_POSE) - -/****************** Bit definition for RTC_ALMA register ************************/ - -#define RTC_ALMA_WDS_POS 31U -#define RTC_ALMA_WDS_MSK BIT(RTC_ALMA_WDS_POS) - -#define RTC_ALMA_DAWD_POSS 24U -#define RTC_ALMA_DAWD_POSE 30U -#define RTC_ALMA_DAWD_MSK BITS(RTC_ALMA_DAWD_POSS,RTC_ALMA_DAWD_POSE) - -#define RTC_ALMA_DAYMSK_POS 30U -#define RTC_ALMA_DAYMSK_MSK BIT(RTC_ALMA_DAYMSK_POS) - -#define RTC_ALMA_DAWD_DAYT_POSS 28U -#define RTC_ALMA_DAWD_DAYT_POSE 29U -#define RTC_ALMA_DAWD_DAYT_MSK BITS(RTC_ALMA_DAWD_DAYT_POSS, RTC_ALMA_DAWD_DAYT_POSE) - -#define RTC_ALMA_DAWD_DAYU_POSS 24U -#define RTC_ALMA_DAWD_DAYU_POSE 27U -#define RTC_ALMA_DAWD_DAYU_MSK BITS(RTC_ALMA_DAWD_DAYU_POSS, RTC_ALMA_DAWD_DAYU_POSE) - -#define RTC_ALMA_HRMSK_POS 23U -#define RTC_ALMA_HRMSK_MSK BIT(RTC_ALMA_HRMSK_POS) - -#define RTC_ALMA_PM_POS 22U -#define RTC_ALMA_PM_MSK BIT(RTC_ALMA_PM_POS) - -#define RTC_ALMA_HRT_POSS 20U -#define RTC_ALMA_HRT_POSE 21U -#define RTC_ALMA_HRT_MSK BITS(RTC_ALMA_HRT_POSS,RTC_ALMA_HRT_POSE) - -#define RTC_ALMA_HRU_POSS 16U -#define RTC_ALMA_HRU_POSE 19U -#define RTC_ALMA_HRU_MSK BITS(RTC_ALMA_HRU_POSS,RTC_ALMA_HRU_POSE) - -#define RTC_ALMA_MINMSK_POS 15U -#define RTC_ALMA_MINMSK_MSK BIT(RTC_ALMA_MINMSK_POS) - -#define RTC_ALMA_MINT_POSS 12U -#define RTC_ALMA_MINT_POSE 14U -#define RTC_ALMA_MINT_MSK BITS(RTC_ALMA_MINT_POSS,RTC_ALMA_MINT_POSE) - -#define RTC_ALMA_MINU_POSS 8U -#define RTC_ALMA_MINU_POSE 11U -#define RTC_ALMA_MINU_MSK BITS(RTC_ALMA_MINU_POSS,RTC_ALMA_MINU_POSE) - -#define RTC_ALMA_SECMSK_POS 7U -#define RTC_ALMA_SECMSK_MSK BIT(RTC_ALMA_SECMSK_POS) - -#define RTC_ALMA_SECT_POSS 4U -#define RTC_ALMA_SECT_POSE 6U -#define RTC_ALMA_SECT_MSK BITS(RTC_ALMA_SECT_POSS,RTC_ALMA_SECT_POSE) - -#define RTC_ALMA_SECU_POSS 0U -#define RTC_ALMA_SECU_POSE 3U -#define RTC_ALMA_SECU_MSK BITS(RTC_ALMA_SECU_POSS,RTC_ALMA_SECU_POSE) - -/****************** Bit definition for RTC_ALMB register ************************/ - -#define RTC_ALMB_WDS_POS 31U -#define RTC_ALMB_WDS_MSK BIT(RTC_ALMB_WDS_POS) - -#define RTC_ALMB_DAWD_POSS 24U -#define RTC_ALMB_DAWD_POSE 30U -#define RTC_ALMB_DAWD_MSK BITS(RTC_ALMB_DAWD_POSS,RTC_ALMB_DAWD_POSE) - -#define RTC_ALMB_DAYMSK_POS 30U -#define RTC_ALMB_DAYMSK_MSK BIT(RTC_ALMB_DAYMSK_POS) - -#define RTC_ALMB_DAWD_DAYT_POSS 28U -#define RTC_ALMB_DAWD_DAYT_POSE 29U -#define RTC_ALMB_DAWD_DAYT_MSK BITS(RTC_ALMB_DAWD_DAYT_POSS, RTC_ALMB_DAWD_DAYT_POSE) - -#define RTC_ALMB_DAWD_DAYU_POSS 24U -#define RTC_ALMB_DAWD_DAYU_POSE 27U -#define RTC_ALMB_DAWD_DAYU_MSK BITS(RTC_ALMB_DAWD_DAYU_POSS, RTC_ALMB_DAWD_DAYU_POSE) - -#define RTC_ALMB_HRMSK_POS 23U -#define RTC_ALMB_HRMSK_MSK BIT(RTC_ALMB_HRMSK_POS) - -#define RTC_ALMB_PM_POS 22U -#define RTC_ALMB_PM_MSK BIT(RTC_ALMB_PM_POS) - -#define RTC_ALMB_HRT_POSS 20U -#define RTC_ALMB_HRT_POSE 21U -#define RTC_ALMB_HRT_MSK BITS(RTC_ALMB_HRT_POSS,RTC_ALMB_HRT_POSE) - -#define RTC_ALMB_HRU_POSS 16U -#define RTC_ALMB_HRU_POSE 19U -#define RTC_ALMB_HRU_MSK BITS(RTC_ALMB_HRU_POSS,RTC_ALMB_HRU_POSE) - -#define RTC_ALMB_MINMSK_POS 15U -#define RTC_ALMB_MINMSK_MSK BIT(RTC_ALMB_MINMSK_POS) - -#define RTC_ALMB_MINT_POSS 12U -#define RTC_ALMB_MINT_POSE 14U -#define RTC_ALMB_MINT_MSK BITS(RTC_ALMB_MINT_POSS,RTC_ALMB_MINT_POSE) - -#define RTC_ALMB_MINU_POSS 8U -#define RTC_ALMB_MINU_POSE 11U -#define RTC_ALMB_MINU_MSK BITS(RTC_ALMB_MINU_POSS,RTC_ALMB_MINU_POSE) - -#define RTC_ALMB_SECMSK_POS 7U -#define RTC_ALMB_SECMSK_MSK BIT(RTC_ALMB_SECMSK_POS) - -#define RTC_ALMB_SECT_POSS 4U -#define RTC_ALMB_SECT_POSE 6U -#define RTC_ALMB_SECT_MSK BITS(RTC_ALMB_SECT_POSS,RTC_ALMB_SECT_POSE) - -#define RTC_ALMB_SECU_POSS 0U -#define RTC_ALMB_SECU_POSE 3U -#define RTC_ALMB_SECU_MSK BITS(RTC_ALMB_SECU_POSS,RTC_ALMB_SECU_POSE) - -/****************** Bit definition for RTC_ALMASSEC register ************************/ - -#define RTC_ALMASSEC_SSECM_POSS 24U -#define RTC_ALMASSEC_SSECM_POSE 27U -#define RTC_ALMASSEC_SSECM_MSK BITS(RTC_ALMASSEC_SSECM_POSS,RTC_ALMASSEC_SSECM_POSE) - -#define RTC_ALMASSEC_SSEC_POSS 0U -#define RTC_ALMASSEC_SSEC_POSE 14U -#define RTC_ALMASSEC_SSEC_MSK BITS(RTC_ALMASSEC_SSEC_POSS,RTC_ALMASSEC_SSEC_POSE) - -/****************** Bit definition for RTC_ALMBSSEC register ************************/ - -#define RTC_ALMBSSEC_SSECM_POSS 24U -#define RTC_ALMBSSEC_SSECM_POSE 27U -#define RTC_ALMBSSEC_SSECM_MSK BITS(RTC_ALMBSSEC_SSECM_POSS,RTC_ALMBSSEC_SSECM_POSE) - -#define RTC_ALMBSSEC_SSEC_POSS 0U -#define RTC_ALMBSSEC_SSEC_POSE 14U -#define RTC_ALMBSSEC_SSEC_MSK BITS(RTC_ALMBSSEC_SSEC_POSS,RTC_ALMBSSEC_SSEC_POSE) - -/****************** Bit definition for RTC_TSTIME register ************************/ - -#define RTC_TSTIME_PM_POS 22U -#define RTC_TSTIME_PM_MSK BIT(RTC_TSTIME_PM_POS) - -#define RTC_TSTIME_HRT_POSS 20U -#define RTC_TSTIME_HRT_POSE 21U -#define RTC_TSTIME_HRT_MSK BITS(RTC_TSTIME_HRT_POSS,RTC_TSTIME_HRT_POSE) - -#define RTC_TSTIME_HRU_POSS 16U -#define RTC_TSTIME_HRU_POSE 19U -#define RTC_TSTIME_HRU_MSK BITS(RTC_TSTIME_HRU_POSS,RTC_TSTIME_HRU_POSE) - -#define RTC_TSTIME_MINT_POSS 12U -#define RTC_TSTIME_MINT_POSE 14U -#define RTC_TSTIME_MINT_MSK BITS(RTC_TSTIME_MINT_POSS,RTC_TSTIME_MINT_POSE) - -#define RTC_TSTIME_MINU_POSS 8U -#define RTC_TSTIME_MINU_POSE 11U -#define RTC_TSTIME_MINU_MSK BITS(RTC_TSTIME_MINU_POSS,RTC_TSTIME_MINU_POSE) - -#define RTC_TSTIME_SECT_POSS 4U -#define RTC_TSTIME_SECT_POSE 6U -#define RTC_TSTIME_SECT_MSK BITS(RTC_TSTIME_SECT_POSS,RTC_TSTIME_SECT_POSE) - -#define RTC_TSTIME_SECU_POSS 0U -#define RTC_TSTIME_SECU_POSE 3U -#define RTC_TSTIME_SECU_MSK BITS(RTC_TSTIME_SECU_POSS,RTC_TSTIME_SECU_POSE) - -/****************** Bit definition for RTC_TSDATE register ************************/ - -#define RTC_TSDATE_WD_POSS 24U -#define RTC_TSDATE_WD_POSE 26U -#define RTC_TSDATE_WD_MSK BITS(RTC_TSDATE_WD_POSS,RTC_TSDATE_WD_POSE) - -#define RTC_TSDATE_YRT_POSS 20U -#define RTC_TSDATE_YRT_POSE 23U -#define RTC_TSDATE_YRT_MSK BITS(RTC_TSDATE_YRT_POSS,RTC_TSDATE_YRT_POSE) - -#define RTC_TSDATE_YRU_POSS 16U -#define RTC_TSDATE_YRU_POSE 19U -#define RTC_TSDATE_YRU_MSK BITS(RTC_TSDATE_YRU_POSS,RTC_TSDATE_YRU_POSE) - -#define RTC_TSDATE_MONT_POS 12U -#define RTC_TSDATE_MONT_MSK BIT(RTC_TSDATE_MONT_POS) - -#define RTC_TSDATE_MONU_POSS 8U -#define RTC_TSDATE_MONU_POSE 11U -#define RTC_TSDATE_MONU_MSK BITS(RTC_TSDATE_MONU_POSS,RTC_TSDATE_MONU_POSE) - -#define RTC_TSDATE_DAYT_POSS 4U -#define RTC_TSDATE_DAYT_POSE 5U -#define RTC_TSDATE_DAYT_MSK BITS(RTC_TSDATE_DAYT_POSS,RTC_TSDATE_DAYT_POSE) - -#define RTC_TSDATE_DAYU_POSS 0U -#define RTC_TSDATE_DAYU_POSE 3U -#define RTC_TSDATE_DAYU_MSK BITS(RTC_TSDATE_DAYU_POSS,RTC_TSDATE_DAYU_POSE) - -/****************** Bit definition for RTC_TSSSEC register ************************/ - -#define RTC_TSSSEC_SSEC_POSS 0U -#define RTC_TSSSEC_SSEC_POSE 15U -#define RTC_TSSSEC_SSEC_MSK BITS(RTC_TSSSEC_SSEC_POSS,RTC_TSSSEC_SSEC_POSE) - -/****************** Bit definition for RTC_SSECTR register ************************/ - -#define RTC_SSECTR_INC_POS 31U -#define RTC_SSECTR_INC_MSK BIT(RTC_SSECTR_INC_POS) - -#define RTC_SSECTR_TRIM_POSS 0U -#define RTC_SSECTR_TRIM_POSE 14U -#define RTC_SSECTR_TRIM_MSK BITS(RTC_SSECTR_TRIM_POSS,RTC_SSECTR_TRIM_POSE) - -/****************** Bit definition for RTC_IER register ************************/ - -#define RTC_IER_TCE_POS 25U -#define RTC_IER_TCE_MSK BIT(RTC_IER_TCE_POS) - -#define RTC_IER_TCC_POS 24U -#define RTC_IER_TCC_MSK BIT(RTC_IER_TCC_POS) - -#define RTC_IER_WU_POS 18U -#define RTC_IER_WU_MSK BIT(RTC_IER_WU_POS) - -#define RTC_IER_SSTC_POS 17U -#define RTC_IER_SSTC_MSK BIT(RTC_IER_SSTC_POS) - -#define RTC_IER_RSC_POS 16U -#define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS) - -#define RTC_IER_TAMP2_POS 13U -#define RTC_IER_TAMP2_MSK BIT(RTC_IER_TAMP2_POS) - -#define RTC_IER_TAMP1_POS 12U -#define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS) - -#define RTC_IER_TSOV_POS 11U -#define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS) - -#define RTC_IER_TS_POS 10U -#define RTC_IER_TS_MSK BIT(RTC_IER_TS_POS) - -#define RTC_IER_ALMB_POS 9U -#define RTC_IER_ALMB_MSK BIT(RTC_IER_ALMB_POS) - -#define RTC_IER_ALMA_POS 8U -#define RTC_IER_ALMA_MSK BIT(RTC_IER_ALMA_POS) - -#define RTC_IER_YR_POS 5U -#define RTC_IER_YR_MSK BIT(RTC_IER_YR_POS) - -#define RTC_IER_MON_POS 4U -#define RTC_IER_MON_MSK BIT(RTC_IER_MON_POS) - -#define RTC_IER_DAY_POS 3U -#define RTC_IER_DAY_MSK BIT(RTC_IER_DAY_POS) - -#define RTC_IER_HR_POS 2U -#define RTC_IER_HR_MSK BIT(RTC_IER_HR_POS) - -#define RTC_IER_MIN_POS 1U -#define RTC_IER_MIN_MSK BIT(RTC_IER_MIN_POS) - -#define RTC_IER_SEC_POS 0U -#define RTC_IER_SEC_MSK BIT(RTC_IER_SEC_POS) - -/****************** Bit definition for RTC_IFR register ************************/ - -#define RTC_IFR_TCEF_POS 25U -#define RTC_IFR_TCEF_MSK BIT(RTC_IFR_TCEF_POS) - -#define RTC_IFR_TCCF_POS 24U -#define RTC_IFR_TCCF_MSK BIT(RTC_IFR_TCCF_POS) - -#define RTC_IFR_WUF_POS 18U -#define RTC_IFR_WUF_MSK BIT(RTC_IFR_WUF_POS) - -#define RTC_IFR_SSTCF_POS 17U -#define RTC_IFR_SSTCF_MSK BIT(RTC_IFR_SSTCF_POS) - -#define RTC_IFR_RSCF_POS 16U -#define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS) - -#define RTC_IFR_TAMP2F_POS 13U -#define RTC_IFR_TAMP2F_MSK BIT(RTC_IFR_TAMP2F_POS) - -#define RTC_IFR_TAMP1F_POS 12U -#define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS) - -#define RTC_IFR_TSOVF_POS 11U -#define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS) - -#define RTC_IFR_TSF_POS 10U -#define RTC_IFR_TSF_MSK BIT(RTC_IFR_TSF_POS) - -#define RTC_IFR_ALMBF_POS 9U -#define RTC_IFR_ALMBF_MSK BIT(RTC_IFR_ALMBF_POS) - -#define RTC_IFR_ALMAF_POS 8U -#define RTC_IFR_ALMAF_MSK BIT(RTC_IFR_ALMAF_POS) - -#define RTC_IFR_YRF_POS 5U -#define RTC_IFR_YRF_MSK BIT(RTC_IFR_YRF_POS) - -#define RTC_IFR_MONF_POS 4U -#define RTC_IFR_MONF_MSK BIT(RTC_IFR_MONF_POS) - -#define RTC_IFR_DAYF_POS 3U -#define RTC_IFR_DAYF_MSK BIT(RTC_IFR_DAYF_POS) - -#define RTC_IFR_HRF_POS 2U -#define RTC_IFR_HRF_MSK BIT(RTC_IFR_HRF_POS) - -#define RTC_IFR_MINF_POS 1U -#define RTC_IFR_MINF_MSK BIT(RTC_IFR_MINF_POS) - -#define RTC_IFR_SECF_POS 0U -#define RTC_IFR_SECF_MSK BIT(RTC_IFR_SECF_POS) - -/****************** Bit definition for RTC_IFCR register ************************/ - -#define RTC_IFCR_TCEFC_POS 25U -#define RTC_IFCR_TCEFC_MSK BIT(RTC_IFCR_TCEFC_POS) - -#define RTC_IFCR_TCCFC_POS 24U -#define RTC_IFCR_TCCFC_MSK BIT(RTC_IFCR_TCCFC_POS) - -#define RTC_IFCR_WUFC_POS 18U -#define RTC_IFCR_WUFC_MSK BIT(RTC_IFCR_WUFC_POS) - -#define RTC_IFCR_SSTCFC_POS 17U -#define RTC_IFCR_SSTCFC_MSK BIT(RTC_IFCR_SSTCFC_POS) - -#define RTC_IFCR_RSCFC_POS 16U -#define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS) - -#define RTC_IFCR_TAMP2FC_POS 13U -#define RTC_IFCR_TAMP2FC_MSK BIT(RTC_IFCR_TAMP2FC_POS) - -#define RTC_IFCR_TAMP1FC_POS 12U -#define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS) - -#define RTC_IFCR_TSOVFC_POS 11U -#define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS) - -#define RTC_IFCR_TSSTC_POS 10U -#define RTC_IFCR_TSSTC_MSK BIT(RTC_IFCR_TSSTC_POS) - -#define RTC_IFCR_ALMBFC_POS 9U -#define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS) - -#define RTC_IFCR_ALMAFC_POS 8U -#define RTC_IFCR_ALMAFC_MSK BIT(RTC_IFCR_ALMAFC_POS) - -#define RTC_IFCR_YRFC_POS 5U -#define RTC_IFCR_YRFC_MSK BIT(RTC_IFCR_YRFC_POS) - -#define RTC_IFCR_MONFC_POS 4U -#define RTC_IFCR_MONFC_MSK BIT(RTC_IFCR_MONFC_POS) - -#define RTC_IFCR_DAYFC_POS 3U -#define RTC_IFCR_DAYFC_MSK BIT(RTC_IFCR_DAYFC_POS) - -#define RTC_IFCR_HRFC_POS 2U -#define RTC_IFCR_HRFC_MSK BIT(RTC_IFCR_HRFC_POS) - -#define RTC_IFCR_MINFC_POS 1U -#define RTC_IFCR_MINFC_MSK BIT(RTC_IFCR_MINFC_POS) - -#define RTC_IFCR_SECFC_POS 0U -#define RTC_IFCR_SECFC_MSK BIT(RTC_IFCR_SECFC_POS) - -/****************** Bit definition for RTC_ISR register ************************/ - -#define RTC_ISR_TCEF_POS 25U -#define RTC_ISR_TCEF_MSK BIT(RTC_ISR_TCEF_POS) - -#define RTC_ISR_TCCF_POS 24U -#define RTC_ISR_TCCF_MSK BIT(RTC_ISR_TCCF_POS) - -#define RTC_ISR_WUF_POS 18U -#define RTC_ISR_WUF_MSK BIT(RTC_ISR_WUF_POS) - -#define RTC_ISR_SSTCF_POS 17U -#define RTC_ISR_SSTCF_MSK BIT(RTC_ISR_SSTCF_POS) - -#define RTC_ISR_RSCF_POS 16U -#define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS) - -#define RTC_ISR_TAMP2F_POS 13U -#define RTC_ISR_TAMP2F_MSK BIT(RTC_ISR_TAMP2F_POS) - -#define RTC_ISR_TAMP1F_POS 12U -#define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS) - -#define RTC_ISR_TSOVF_POS 11U -#define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS) - -#define RTC_ISR_TSF_POS 10U -#define RTC_ISR_TSF_MSK BIT(RTC_ISR_TSF_POS) - -#define RTC_ISR_ALMBF_POS 9U -#define RTC_ISR_ALMBF_MSK BIT(RTC_ISR_ALMBF_POS) - -#define RTC_ISR_ALMAF_POS 8U -#define RTC_ISR_ALMAF_MSK BIT(RTC_ISR_ALMAF_POS) - -#define RTC_ISR_YRF_POS 5U -#define RTC_ISR_YRF_MSK BIT(RTC_ISR_YRF_POS) - -#define RTC_ISR_MONF_POS 4U -#define RTC_ISR_MONF_MSK BIT(RTC_ISR_MONF_POS) - -#define RTC_ISR_DAYF_POS 3U -#define RTC_ISR_DAYF_MSK BIT(RTC_ISR_DAYF_POS) - -#define RTC_ISR_HRF_POS 2U -#define RTC_ISR_HRF_MSK BIT(RTC_ISR_HRF_POS) - -#define RTC_ISR_MINF_POS 1U -#define RTC_ISR_MINF_MSK BIT(RTC_ISR_MINF_POS) - -#define RTC_ISR_SECF_POS 0U -#define RTC_ISR_SECF_MSK BIT(RTC_ISR_SECF_POS) - -/****************** Bit definition for RTC_CALWPR register ************************/ - -#define RTC_CALWPR_WP_POS 0U -#define RTC_CALWPR_WP_MSK BIT(RTC_CALWPR_WP_POS) - -/****************** Bit definition for RTC_CALCON register ************************/ - -#define RTC_CALCON_DCMACC_POS 24U -#define RTC_CALCON_DCMACC_MSK BIT(RTC_CALCON_DCMACC_POS) - -#define RTC_CALCON_ALG_POS 23U -#define RTC_CALCON_ALG_MSK BIT(RTC_CALCON_ALG_POS) - -#define RTC_CALCON_TCP_POSS 20U -#define RTC_CALCON_TCP_POSE 22U -#define RTC_CALCON_TCP_MSK BITS(RTC_CALCON_TCP_POSS,RTC_CALCON_TCP_POSE) - -#define RTC_CALCON_ERR_POS 19U -#define RTC_CALCON_ERR_MSK BIT(RTC_CALCON_ERR_POS) - -#define RTC_CALCON_BUSY_POS 18U -#define RTC_CALCON_BUSY_MSK BIT(RTC_CALCON_BUSY_POS) - -#define RTC_CALCON_TCM_POSS 16U -#define RTC_CALCON_TCM_POSE 17U -#define RTC_CALCON_TCM_MSK BITS(RTC_CALCON_TCM_POSS,RTC_CALCON_TCM_POSE) - -#define RTC_CALCON_CALP_POSS 1U -#define RTC_CALCON_CALP_POSE 3U -#define RTC_CALCON_CALP_MSK BITS(RTC_CALCON_CALP_POSS,RTC_CALCON_CALP_POSE) - -#define RTC_CALCON_CALEN_POS 0U -#define RTC_CALCON_CALEN_MSK BIT(RTC_CALCON_CALEN_POS) - -/****************** Bit definition for RTC_CALDR register ************************/ - -#define RTC_CALDR_DATA_POSS 16U -#define RTC_CALDR_DATA_POSE 31U -#define RTC_CALDR_DATA_MSK BITS(RTC_CALDR_DATA_POSS,RTC_CALDR_DATA_POSE) - -#define RTC_CALDR_VAL_POSS 0U -#define RTC_CALDR_VAL_POSE 15U -#define RTC_CALDR_VAL_MSK BITS(RTC_CALDR_VAL_POSS,RTC_CALDR_VAL_POSE) - -/****************** Bit definition for RTC_TEMPR register ************************/ - -#define RTC_TEMPR_DATA_POSS 16U -#define RTC_TEMPR_DATA_POSE 31U -#define RTC_TEMPR_DATA_MSK BITS(RTC_TEMPR_DATA_POSS,RTC_TEMPR_DATA_POSE) - -#define RTC_TEMPR_VAL_POSS 0U -#define RTC_TEMPR_VAL_POSE 15U -#define RTC_TEMPR_VAL_MSK BITS(RTC_TEMPR_VAL_POSS,RTC_TEMPR_VAL_POSE) - -/****************** Bit definition for RTC_TEMPBDR register ************************/ - -#define RTC_TEMPBDR_VAL_POSS 0U -#define RTC_TEMPBDR_VAL_POSE 15U -#define RTC_TEMPBDR_VAL_MSK BITS(RTC_TEMPBDR_VAL_POSS,RTC_TEMPBDR_VAL_POSE) - -/****************** Bit definition for RTC_BKP register ************************/ - -#define RTC_BKP_BKP_POSS 0U -#define RTC_BKP_BKP_POSE 31U -#define RTC_BKP_BKP_MSK BITS(RTC_BKP_BKP_POSS,RTC_BKP_BKP_POSE) - -typedef struct -{ - __IO uint32_t WPR; - __IO uint32_t CON; - __IO uint32_t PSR; - __IO uint32_t TAMPCON; - __IO uint32_t TIME; - __IO uint32_t DATE; - __IO uint32_t SSEC; - __IO uint32_t WUMAT; - __IO uint32_t ALMA; - __IO uint32_t ALMB; - __IO uint32_t ALMASSEC; - __IO uint32_t ALMBSSEC; - __I uint32_t TSTIME; - __I uint32_t TSDATE; - __I uint32_t TSSSEC; - __O uint32_t SSECTR; - __IO uint32_t IER; - __I uint32_t IFR; - __O uint32_t IFCR; - __I uint32_t ISR; - __IO uint32_t CALWPR; - __IO uint32_t CALCON; - __IO uint32_t CALDR; - __IO uint32_t TEMPR; - __IO uint32_t LTCAR; - __IO uint32_t LTCBR; - __IO uint32_t LTCCR; - __IO uint32_t LTCDR; - __IO uint32_t LTCER; - __IO uint32_t HTCAR; - __IO uint32_t HTCBR; - __IO uint32_t HTCCR; - __IO uint32_t HTCDR; - __IO uint32_t HTCER; - __IO uint32_t TEMPBDR; - uint32_t RESERVED0[29] ; - __IO uint32_t BKPR[32]; -} RTC_TypeDef; - -/****************** Bit definition for TIMER_CON1 register ************************/ - -#define TIMER_CON1_DFCKSEL_POSS 8U -#define TIMER_CON1_DFCKSEL_POSE 9U -#define TIMER_CON1_DFCKSEL_MSK BITS(TIMER_CON1_DFCKSEL_POSS,TIMER_CON1_DFCKSEL_POSE) - -#define TIMER_CON1_ARPEN_POS 7U -#define TIMER_CON1_ARPEN_MSK BIT(TIMER_CON1_ARPEN_POS) - -#define TIMER_CON1_CMSEL_POSS 5U -#define TIMER_CON1_CMSEL_POSE 6U -#define TIMER_CON1_CMSEL_MSK BITS(TIMER_CON1_CMSEL_POSS,TIMER_CON1_CMSEL_POSE) - -#define TIMER_CON1_DIRSEL_POS 4U -#define TIMER_CON1_DIRSEL_MSK BIT(TIMER_CON1_DIRSEL_POS) - -#define TIMER_CON1_SPMEN_POS 3U -#define TIMER_CON1_SPMEN_MSK BIT(TIMER_CON1_SPMEN_POS) - -#define TIMER_CON1_UERSEL_POS 2U -#define TIMER_CON1_UERSEL_MSK BIT(TIMER_CON1_UERSEL_POS) - -#define TIMER_CON1_DISUE_POS 1U -#define TIMER_CON1_DISUE_MSK BIT(TIMER_CON1_DISUE_POS) - -#define TIMER_CON1_CNTEN_POS 0U -#define TIMER_CON1_CNTEN_MSK BIT(TIMER_CON1_CNTEN_POS) - -/****************** Bit definition for TIMER_CON2 register ************************/ - -#define TIMER_CON2_OISS4_POS 14U -#define TIMER_CON2_OISS4_MSK BIT(TIMER_CON2_OISS4_POS) - -#define TIMER_CON2_OISS3N_POS 13U -#define TIMER_CON2_OISS3N_MSK BIT(TIMER_CON2_OISS3N_POS) - -#define TIMER_CON2_OISS3_POS 12U -#define TIMER_CON2_OISS3_MSK BIT(TIMER_CON2_OISS3_POS) - -#define TIMER_CON2_OISS2N_POS 11U -#define TIMER_CON2_OISS2N_MSK BIT(TIMER_CON2_OISS2N_POS) - -#define TIMER_CON2_OISS2_POS 10U -#define TIMER_CON2_OISS2_MSK BIT(TIMER_CON2_OISS2_POS) - -#define TIMER_CON2_OISS1N_POS 9U -#define TIMER_CON2_OISS1N_MSK BIT(TIMER_CON2_OISS1N_POS) - -#define TIMER_CON2_OISS1_POS 8U -#define TIMER_CON2_OISS1_MSK BIT(TIMER_CON2_OISS1_POS) - -#define TIMER_CON2_I1FSEL_POS 7U -#define TIMER_CON2_I1FSEL_MSK BIT(TIMER_CON2_I1FSEL_POS) - -#define TIMER_CON2_TRGOSEL_POSS 4U -#define TIMER_CON2_TRGOSEL_POSE 6U -#define TIMER_CON2_TRGOSEL_MSK BITS(TIMER_CON2_TRGOSEL_POSS,TIMER_CON2_TRGOSEL_POSE) - -#define TIMER_CON2_CCDMASEL_POS 3U -#define TIMER_CON2_CCDMASEL_MSK BIT(TIMER_CON2_CCDMASEL_POS) - -#define TIMER_CON2_CCUSEL_POS 2U -#define TIMER_CON2_CCUSEL_MSK BIT(TIMER_CON2_CCUSEL_POS) - -#define TIMER_CON2_CCPCEN_POS 0U -#define TIMER_CON2_CCPCEN_MSK BIT(TIMER_CON2_CCPCEN_POS) - -/****************** Bit definition for TIMER_SMCON register ************************/ - -#define TIMER_SMCON_ETPOL_POS 15U -#define TIMER_SMCON_ETPOL_MSK BIT(TIMER_SMCON_ETPOL_POS) - -#define TIMER_SMCON_ECM2EN_POS 14U -#define TIMER_SMCON_ECM2EN_MSK BIT(TIMER_SMCON_ECM2EN_POS) - -#define TIMER_SMCON_ETPSEL_POSS 12U -#define TIMER_SMCON_ETPSEL_POSE 13U -#define TIMER_SMCON_ETPSEL_MSK BITS(TIMER_SMCON_ETPSEL_POSS,TIMER_SMCON_ETPSEL_POSE) - -#define TIMER_SMCON_ETFLT_POSS 8U -#define TIMER_SMCON_ETFLT_POSE 11U -#define TIMER_SMCON_ETFLT_MSK BITS(TIMER_SMCON_ETFLT_POSS,TIMER_SMCON_ETFLT_POSE) - -#define TIMER_SMCON_MSCFG_POS 7U -#define TIMER_SMCON_MSCFG_MSK BIT(TIMER_SMCON_MSCFG_POS) - -#define TIMER_SMCON_TSSEL_POSS 4U -#define TIMER_SMCON_TSSEL_POSE 6U -#define TIMER_SMCON_TSSEL_MSK BITS(TIMER_SMCON_TSSEL_POSS,TIMER_SMCON_TSSEL_POSE) - -#define TIMER_SMCON_SMODS_POSS 0U -#define TIMER_SMCON_SMODS_POSE 2U -#define TIMER_SMCON_SMODS_MSK BITS(TIMER_SMCON_SMODS_POSS,TIMER_SMCON_SMODS_POSE) - -/****************** Bit definition for TIMER_DIER register ************************/ - -#define TIMER_DIER_TRGDMA_POS 14U -#define TIMER_DIER_TRGDMA_MSK BIT(TIMER_DIER_TRGDMA_POS) - -#define TIMER_DIER_COMDMA_POS 13U -#define TIMER_DIER_COMDMA_MSK BIT(TIMER_DIER_COMDMA_POS) - -#define TIMER_DIER_CC4DMA_POS 12U -#define TIMER_DIER_CC4DMA_MSK BIT(TIMER_DIER_CC4DMA_POS) - -#define TIMER_DIER_CC3DMA_POS 11U -#define TIMER_DIER_CC3DMA_MSK BIT(TIMER_DIER_CC3DMA_POS) - -#define TIMER_DIER_CC2DMA_POS 10U -#define TIMER_DIER_CC2DMA_MSK BIT(TIMER_DIER_CC2DMA_POS) - -#define TIMER_DIER_CC1DMA_POS 9U -#define TIMER_DIER_CC1DMA_MSK BIT(TIMER_DIER_CC1DMA_POS) - -#define TIMER_DIER_UDMA_POS 8U -#define TIMER_DIER_UDMA_MSK BIT(TIMER_DIER_UDMA_POS) - -#define TIMER_DIER_BRKIT_POS 7U -#define TIMER_DIER_BRKIT_MSK BIT(TIMER_DIER_BRKIT_POS) - -#define TIMER_DIER_TRGIT_POS 6U -#define TIMER_DIER_TRGIT_MSK BIT(TIMER_DIER_TRGIT_POS) - -#define TIMER_DIER_COMIT_POS 5U -#define TIMER_DIER_COMIT_MSK BIT(TIMER_DIER_COMIT_POS) - -#define TIMER_DIER_CC4IT_POS 4U -#define TIMER_DIER_CC4IT_MSK BIT(TIMER_DIER_CC4IT_POS) - -#define TIMER_DIER_CC3IT_POS 3U -#define TIMER_DIER_CC3IT_MSK BIT(TIMER_DIER_CC3IT_POS) - -#define TIMER_DIER_CC2IT_POS 2U -#define TIMER_DIER_CC2IT_MSK BIT(TIMER_DIER_CC2IT_POS) - -#define TIMER_DIER_CC1IT_POS 1U -#define TIMER_DIER_CC1IT_MSK BIT(TIMER_DIER_CC1IT_POS) - -#define TIMER_DIER_UIT_POS 0U -#define TIMER_DIER_UIT_MSK BIT(TIMER_DIER_UIT_POS) - -/****************** Bit definition for TIMER_DIDR register ************************/ - -#define TIMER_DIDR_TRGDMA_POS 14U -#define TIMER_DIDR_TRGDMA_MSK BIT(TIMER_DIDR_TRGDMA_POS) - -#define TIMER_DIDR_COMD_POS 13U -#define TIMER_DIDR_COMD_MSK BIT(TIMER_DIDR_COMD_POS) - -#define TIMER_DIDR_CC4D_POS 12U -#define TIMER_DIDR_CC4D_MSK BIT(TIMER_DIDR_CC4D_POS) - -#define TIMER_DIDR_CC3D_POS 11U -#define TIMER_DIDR_CC3D_MSK BIT(TIMER_DIDR_CC3D_POS) - -#define TIMER_DIDR_CC2D_POS 10U -#define TIMER_DIDR_CC2D_MSK BIT(TIMER_DIDR_CC2D_POS) - -#define TIMER_DIDR_CC1D_POS 9U -#define TIMER_DIDR_CC1D_MSK BIT(TIMER_DIDR_CC1D_POS) - -#define TIMER_DIDR_UD_POS 8U -#define TIMER_DIDR_UD_MSK BIT(TIMER_DIDR_UD_POS) - -#define TIMER_DIDR_BRKI_POS 7U -#define TIMER_DIDR_BRKI_MSK BIT(TIMER_DIDR_BRKI_POS) - -#define TIMER_DIDR_TRGI_POS 6U -#define TIMER_DIDR_TRGI_MSK BIT(TIMER_DIDR_TRGI_POS) - -#define TIMER_DIDR_COMI_POS 5U -#define TIMER_DIDR_COMI_MSK BIT(TIMER_DIDR_COMI_POS) - -#define TIMER_DIDR_CC4I_POS 4U -#define TIMER_DIDR_CC4I_MSK BIT(TIMER_DIDR_CC4I_POS) - -#define TIMER_DIDR_CC3I_POS 3U -#define TIMER_DIDR_CC3I_MSK BIT(TIMER_DIDR_CC3I_POS) - -#define TIMER_DIDR_CC2I_POS 2U -#define TIMER_DIDR_CC2I_MSK BIT(TIMER_DIDR_CC2I_POS) - -#define TIMER_DIDR_CC1I_POS 1U -#define TIMER_DIDR_CC1I_MSK BIT(TIMER_DIDR_CC1I_POS) - -#define TIMER_DIDR_UI_POS 0U -#define TIMER_DIDR_UI_MSK BIT(TIMER_DIDR_UI_POS) - -/****************** Bit definition for TIMER_DIVS register ************************/ - -#define TIMER_DIVS_TRGDMA_POS 14U -#define TIMER_DIVS_TRGDMA_MSK BIT(TIMER_DIVS_TRGDMA_POS) - -#define TIMER_DIVS_COMDMA_POS 13U -#define TIMER_DIVS_COMDMA_MSK BIT(TIMER_DIVS_COMDMA_POS) - -#define TIMER_DIVS_CC4DMA_POS 12U -#define TIMER_DIVS_CC4DMA_MSK BIT(TIMER_DIVS_CC4DMA_POS) - -#define TIMER_DIVS_CC3DMA_POS 11U -#define TIMER_DIVS_CC3DMA_MSK BIT(TIMER_DIVS_CC3DMA_POS) - -#define TIMER_DIVS_CC2DMA_POS 10U -#define TIMER_DIVS_CC2DMA_MSK BIT(TIMER_DIVS_CC2DMA_POS) - -#define TIMER_DIVS_CC1DMA_POS 9U -#define TIMER_DIVS_CC1DMA_MSK BIT(TIMER_DIVS_CC1DMA_POS) - -#define TIMER_DIVS_UEDTR_POS 8U -#define TIMER_DIVS_UEDTR_MSK BIT(TIMER_DIVS_UEDTR_POS) - -#define TIMER_DIVS_BKI_POS 7U -#define TIMER_DIVS_BKI_MSK BIT(TIMER_DIVS_BKI_POS) - -#define TIMER_DIVS_TRGI_POS 6U -#define TIMER_DIVS_TRGI_MSK BIT(TIMER_DIVS_TRGI_POS) - -#define TIMER_DIVS_COMI_POS 5U -#define TIMER_DIVS_COMI_MSK BIT(TIMER_DIVS_COMI_POS) - -#define TIMER_DIVS_CC4I_POS 4U -#define TIMER_DIVS_CC4I_MSK BIT(TIMER_DIVS_CC4I_POS) - -#define TIMER_DIVS_CC3I_POS 3U -#define TIMER_DIVS_CC3I_MSK BIT(TIMER_DIVS_CC3I_POS) - -#define TIMER_DIVS_CC2I_POS 2U -#define TIMER_DIVS_CC2I_MSK BIT(TIMER_DIVS_CC2I_POS) - -#define TIMER_DIVS_CC1I_POS 1U -#define TIMER_DIVS_CC1I_MSK BIT(TIMER_DIVS_CC1I_POS) - -#define TIMER_DIVS_UEI_POS 0U -#define TIMER_DIVS_UEI_MSK BIT(TIMER_DIVS_UEI_POS) - -/****************** Bit definition for TIMER_RIF register ************************/ - -#define TIMER_RIF_CH4OVIF_POS 12U -#define TIMER_RIF_CH4OVIF_MSK BIT(TIMER_RIF_CH4OVIF_POS) - -#define TIMER_RIF_CH3OVIF_POS 11U -#define TIMER_RIF_CH3OVIF_MSK BIT(TIMER_RIF_CH3OVIF_POS) - -#define TIMER_RIF_CH2OVIF_POS 10U -#define TIMER_RIF_CH2OVIF_MSK BIT(TIMER_RIF_CH2OVIF_POS) - -#define TIMER_RIF_CH1OVIF_POS 9U -#define TIMER_RIF_CH1OVIF_MSK BIT(TIMER_RIF_CH1OVIF_POS) - -#define TIMER_RIF_BRKIF_POS 7U -#define TIMER_RIF_BRKIF_MSK BIT(TIMER_RIF_BRKIF_POS) - -#define TIMER_RIF_TRGIF_POS 6U -#define TIMER_RIF_TRGIF_MSK BIT(TIMER_RIF_TRGIF_POS) - -#define TIMER_RIF_COMIF_POS 5U -#define TIMER_RIF_COMIF_MSK BIT(TIMER_RIF_COMIF_POS) - -#define TIMER_RIF_CH4IF_POS 4U -#define TIMER_RIF_CH4IF_MSK BIT(TIMER_RIF_CH4IF_POS) - -#define TIMER_RIF_CH3IF_POS 3U -#define TIMER_RIF_CH3IF_MSK BIT(TIMER_RIF_CH3IF_POS) - -#define TIMER_RIF_CH2IF_POS 2U -#define TIMER_RIF_CH2IF_MSK BIT(TIMER_RIF_CH2IF_POS) - -#define TIMER_RIF_CH1IF_POS 1U -#define TIMER_RIF_CH1IF_MSK BIT(TIMER_RIF_CH1IF_POS) - -#define TIMER_RIF_UEVTIF_POS 0U -#define TIMER_RIF_UEVTIF_MSK BIT(TIMER_RIF_UEVTIF_POS) - -/****************** Bit definition for TIMER_IFM register ************************/ - -#define TIMER_IFM_BRKIM_POS 7U -#define TIMER_IFM_BRKIM_MSK BIT(TIMER_IFM_BRKIM_POS) - -#define TIMER_IFM_TRGI_POS 6U -#define TIMER_IFM_TRGI_MSK BIT(TIMER_IFM_TRGI_POS) - -#define TIMER_IFM_COMI_POS 5U -#define TIMER_IFM_COMI_MSK BIT(TIMER_IFM_COMI_POS) - -#define TIMER_IFM_CH4CCI_POS 4U -#define TIMER_IFM_CH4CCI_MSK BIT(TIMER_IFM_CH4CCI_POS) - -#define TIMER_IFM_CH3CCI_POS 3U -#define TIMER_IFM_CH3CCI_MSK BIT(TIMER_IFM_CH3CCI_POS) - -#define TIMER_IFM_CH2CCI_POS 2U -#define TIMER_IFM_CH2CCI_MSK BIT(TIMER_IFM_CH2CCI_POS) - -#define TIMER_IFM_CH1CCI_POS 1U -#define TIMER_IFM_CH1CCI_MSK BIT(TIMER_IFM_CH1CCI_POS) - -#define TIMER_IFM_UEI_POS 0U -#define TIMER_IFM_UEI_MSK BIT(TIMER_IFM_UEI_POS) - -/****************** Bit definition for TIMER_ICR register ************************/ - -#define TIMER_ICR_BRKIC_POS 7U -#define TIMER_ICR_BRKIC_MSK BIT(TIMER_ICR_BRKIC_POS) - -#define TIMER_ICR_TRGIC_POS 6U -#define TIMER_ICR_TRGIC_MSK BIT(TIMER_ICR_TRGIC_POS) - -#define TIMER_ICR_COMIC_POS 5U -#define TIMER_ICR_COMIC_MSK BIT(TIMER_ICR_COMIC_POS) - -#define TIMER_ICR_CH4CCIC_POS 4U -#define TIMER_ICR_CH4CCIC_MSK BIT(TIMER_ICR_CH4CCIC_POS) - -#define TIMER_ICR_CH3CCIC_POS 3U -#define TIMER_ICR_CH3CCIC_MSK BIT(TIMER_ICR_CH3CCIC_POS) - -#define TIMER_ICR_CH2CCIC_POS 2U -#define TIMER_ICR_CH2CCIC_MSK BIT(TIMER_ICR_CH2CCIC_POS) - -#define TIMER_ICR_CH1CCIC_POS 1U -#define TIMER_ICR_CH1CCIC_MSK BIT(TIMER_ICR_CH1CCIC_POS) - -#define TIMER_ICR_UEIC_POS 0U -#define TIMER_ICR_UEIC_MSK BIT(TIMER_ICR_UEIC_POS) - -/****************** Bit definition for TIMER_SGE register ************************/ - -#define TIMER_SGE_SGBRK_POS 7U -#define TIMER_SGE_SGBRK_MSK BIT(TIMER_SGE_SGBRK_POS) - -#define TIMER_SGE_SGTRG_POS 6U -#define TIMER_SGE_SGTRG_MSK BIT(TIMER_SGE_SGTRG_POS) - -#define TIMER_SGE_SGCOM_POS 5U -#define TIMER_SGE_SGCOM_MSK BIT(TIMER_SGE_SGCOM_POS) - -#define TIMER_SGE_SGCC4E_POS 4U -#define TIMER_SGE_SGCC4E_MSK BIT(TIMER_SGE_SGCC4E_POS) - -#define TIMER_SGE_SGCC3E_POS 3U -#define TIMER_SGE_SGCC3E_MSK BIT(TIMER_SGE_SGCC3E_POS) - -#define TIMER_SGE_SGCC2E_POS 2U -#define TIMER_SGE_SGCC2E_MSK BIT(TIMER_SGE_SGCC2E_POS) - -#define TIMER_SGE_SGCC1E_POS 1U -#define TIMER_SGE_SGCC1E_MSK BIT(TIMER_SGE_SGCC1E_POS) - -#define TIMER_SGE_SGU_POS 0U -#define TIMER_SGE_SGU_MSK BIT(TIMER_SGE_SGU_POS) - -/****************** Bit definition for TIMER_CHMR1 register ************************/ -/* Output */ -#define TIMER_CHMR1_CH2OCLREN_POS 15U -#define TIMER_CHMR1_CH2OCLREN_MSK BIT(TIMER_CHMR1_CH2OCLREN_POS) - -#define TIMER_CHMR1_CH2OMOD_POSS 12U -#define TIMER_CHMR1_CH2OMOD_POSE 14U -#define TIMER_CHMR1_CH2OMOD_MSK BITS(TIMER_CHMR1_CH2OMOD_POSS,TIMER_CHMR1_CH2OMOD_POSE) - -#define TIMER_CHMR1_CH2OPEN_POS 11U -#define TIMER_CHMR1_CH2OPEN_MSK BIT(TIMER_CHMR1_CH2OPEN_POS) - -#define TIMER_CHMR1_CH2OFEN_POS 10U -#define TIMER_CHMR1_CH2OFEN_MSK BIT(TIMER_CHMR1_CH2OFEN_POS) - -#define TIMER_CHMR1_CC2SSEL_POSS 8U -#define TIMER_CHMR1_CC2SSEL_POSE 9U -#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) - -#define TIMER_CHMR1_CH1OCLREN_POS 7U -#define TIMER_CHMR1_CH1OCLREN_MSK BIT(TIMER_CHMR1_CH1OCLREN_POS) - -#define TIMER_CHMR1_CH1OMOD_POSS 4U -#define TIMER_CHMR1_CH1OMOD_POSE 6U -#define TIMER_CHMR1_CH1OMOD_MSK BITS(TIMER_CHMR1_CH1OMOD_POSS,TIMER_CHMR1_CH1OMOD_POSE) - -#define TIMER_CHMR1_CH1OPREN_POS 3U -#define TIMER_CHMR1_CH1OPREN_MSK BIT(TIMER_CHMR1_CH1OPREN_POS) - -#define TIMER_CHMR1_CH1OHSEN_POS 2U -#define TIMER_CHMR1_CH1OHSEN_MSK BIT(TIMER_CHMR1_CH1OHSEN_POS) - -#define TIMER_CHMR1_CC1SSEL_POSS 0U -#define TIMER_CHMR1_CC1SSEL_POSE 1U -#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) - -/* Input */ -#define TIMER_CHMR1_I2FLT_POSS 12U -#define TIMER_CHMR1_I2FLT_POSE 15U -#define TIMER_CHMR1_I2FLT_MSK BITS(TIMER_CHMR1_I2FLT_POSS,TIMER_CHMR1_I2FLT_POSE) - -#define TIMER_CHMR1_IC2PRES_POSS 10U -#define TIMER_CHMR1_IC2PRES_POSE 11U -#define TIMER_CHMR1_IC2PRES_MSK BITS(TIMER_CHMR1_IC2PRES_POSS,TIMER_CHMR1_IC2PRES_POSE) - -#define TIMER_CHMR1_CC2SSEL_POSS 8U -#define TIMER_CHMR1_CC2SSEL_POSE 9U -#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) - -#define TIMER_CHMR1_I1FLT_POSS 4U -#define TIMER_CHMR1_I1FLT_POSE 7U -#define TIMER_CHMR1_I1FLT_MSK BITS(TIMER_CHMR1_I1FLT_POSS,TIMER_CHMR1_I1FLT_POSE) - -#define TIMER_CHMR1_IC1PRES_POSS 2U -#define TIMER_CHMR1_IC1PRES_POSE 3U -#define TIMER_CHMR1_IC1PRES_MSK BITS(TIMER_CHMR1_IC1PRES_POSS,TIMER_CHMR1_IC1PRES_POSE) - -#define TIMER_CHMR1_CC1SSEL_POSS 0U -#define TIMER_CHMR1_CC1SSEL_POSE 1U -#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) - -/****************** Bit definition for TIMER_CHMR2 register ************************/ -/* Output */ -#define TIMER_CHMR2_CH4OCLREN_POS 15U -#define TIMER_CHMR2_CH4OCLREN_MSK BIT(TIMER_CHMR2_CH4OCLREN_POS) - -#define TIMER_CHMR2_CH4OMOD_POSS 12U -#define TIMER_CHMR2_CH4OMOD_POSE 14U -#define TIMER_CHMR2_CH4OMOD_MSK BITS(TIMER_CHMR2_CH4OMOD_POSS,TIMER_CHMR2_CH4OMOD_POSE) - -#define TIMER_CHMR2_CH4OPEN_POS 11U -#define TIMER_CHMR2_CH4OPEN_MSK BIT(TIMER_CHMR2_CH4OPEN_POS) - -#define TIMER_CHMR2_CH4OHSEN_POS 10U -#define TIMER_CHMR2_CH4OHSEN_MSK BIT(TIMER_CHMR2_CH4OHSEN_POS) - -#define TIMER_CHMR2_CC4SSEL_POSS 8U -#define TIMER_CHMR2_CC4SSEL_POSE 9U -#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) - -#define TIMER_CHMR2_CH3OCLREN_POS 7U -#define TIMER_CHMR2_CH3OCLREN_MSK BIT(TIMER_CHMR2_CH3OCLREN_POS) - -#define TIMER_CHMR2_CH3OMOD_POSS 4U -#define TIMER_CHMR2_CH3OMOD_POSE 6U -#define TIMER_CHMR2_CH3OMOD_MSK BITS(TIMER_CHMR2_CH3OMOD_POSS,TIMER_CHMR2_CH3OMOD_POSE) - -#define TIMER_CHMR2_CH3OPEN_POS 3U -#define TIMER_CHMR2_CH3OPEN_MSK BIT(TIMER_CHMR2_CH3OPEN_POS) - -#define TIMER_CHMR2_CH3OFEN_POS 2U -#define TIMER_CHMR2_CH3OFEN_MSK BIT(TIMER_CHMR2_CH3OFEN_POS) - -#define TIMER_CHMR2_CC3SSEL_POSS 0U -#define TIMER_CHMR2_CC3SSEL_POSE 1U -#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) - -/* Input */ -#define TIMER_CHMR2_I4FLT_POSS 12U -#define TIMER_CHMR2_I4FLT_POSE 15U -#define TIMER_CHMR2_I4FLT_MSK BITS(TIMER_CHMR2_I4FLT_POSS,TIMER_CHMR2_I4FLT_POSE) - -#define TIMER_CHMR2_IC4PRES_POSS 10U -#define TIMER_CHMR2_IC4PRES_POSE 11U -#define TIMER_CHMR2_IC4PRES_MSK BITS(TIMER_CHMR2_IC4PRES_POSS,TIMER_CHMR2_IC4PRES_POSE) - -#define TIMER_CHMR2_CC4SSEL_POSS 8U -#define TIMER_CHMR2_CC4SSEL_POSE 9U -#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) - -#define TIMER_CHMR2_I3FLT_POSS 4U -#define TIMER_CHMR2_I3FLT_POSE 7U -#define TIMER_CHMR2_I3FLT_MSK BITS(TIMER_CHMR2_I3FLT_POSS,TIMER_CHMR2_I3FLT_POSE) - -#define TIMER_CHMR2_IC3PRES_POSS 2U -#define TIMER_CHMR2_IC3PRES_POSE 3U -#define TIMER_CHMR2_IC3PRES_MSK BITS(TIMER_CHMR2_IC3PRES_POSS,TIMER_CHMR2_IC3PRES_POSE) - -#define TIMER_CHMR2_CC3SSEL_POSS 0U -#define TIMER_CHMR2_CC3SSEL_POSE 1U -#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) - -/****************** Bit definition for TIMER_CCEP register ************************/ - -#define TIMER_CCEP_CC4POL_POS 13U -#define TIMER_CCEP_CC4POL_MSK BIT(TIMER_CCEP_CC4POL_POS) - -#define TIMER_CCEP_CC4EN_POS 12U -#define TIMER_CCEP_CC4EN_MSK BIT(TIMER_CCEP_CC4EN_POS) - -#define TIMER_CCEP_CC3NPOL_POS 11U -#define TIMER_CCEP_CC3NPOL_MSK BIT(TIMER_CCEP_CC3NPOL_POS) - -#define TIMER_CCEP_CC3NEN_POS 10U -#define TIMER_CCEP_CC3NEN_MSK BIT(TIMER_CCEP_CC3NEN_POS) - -#define TIMER_CCEP_CC3POL_POS 9U -#define TIMER_CCEP_CC3POL_MSK BIT(TIMER_CCEP_CC3POL_POS) - -#define TIMER_CCEP_CC3EN_POS 8U -#define TIMER_CCEP_CC3EN_MSK BIT(TIMER_CCEP_CC3EN_POS) - -#define TIMER_CCEP_CC2NPOL_POS 7U -#define TIMER_CCEP_CC2NPOL_MSK BIT(TIMER_CCEP_CC2NPOL_POS) - -#define TIMER_CCEP_CC2NEN_POS 6U -#define TIMER_CCEP_CC2NEN_MSK BIT(TIMER_CCEP_CC2NEN_POS) - -#define TIMER_CCEP_CC2POL_POS 5U -#define TIMER_CCEP_CC2POL_MSK BIT(TIMER_CCEP_CC2POL_POS) - -#define TIMER_CCEP_CC2EN_POS 4U -#define TIMER_CCEP_CC2EN_MSK BIT(TIMER_CCEP_CC2EN_POS) - -#define TIMER_CCEP_CC1NPOL_POS 3U -#define TIMER_CCEP_CC1NPOL_MSK BIT(TIMER_CCEP_CC1NPOL_POS) - -#define TIMER_CCEP_CC1NEN_POS 2U -#define TIMER_CCEP_CC1NEN_MSK BIT(TIMER_CCEP_CC1NEN_POS) - -#define TIMER_CCEP_CC1POL_POS 1U -#define TIMER_CCEP_CC1POL_MSK BIT(TIMER_CCEP_CC1POL_POS) - -#define TIMER_CCEP_CC1EN_POS 0U -#define TIMER_CCEP_CC1EN_MSK BIT(TIMER_CCEP_CC1EN_POS) - -/****************** Bit definition for TIMER_COUNT register ************************/ - -#define TIMER_COUNT_CNTV_POSS 0U -#define TIMER_COUNT_CNTV_POSE 15U -#define TIMER_COUNT_CNTV_MSK BITS(TIMER_COUNT_CNTV_POSS,TIMER_COUNT_CNTV_POSE) - -/****************** Bit definition for TIMER_PRES register ************************/ - -#define TIMER_PRES_PSCV_POSS 0U -#define TIMER_PRES_PSCV_POSE 15U -#define TIMER_PRES_PSCV_MSK BITS(TIMER_PRES_PSCV_POSS,TIMER_PRES_PSCV_POSE) - -/****************** Bit definition for TIMER_AR register ************************/ - -#define TIMER_AR_ARRV_POSS 0U -#define TIMER_AR_ARRV_POSE 15U -#define TIMER_AR_ARRV_MSK BITS(TIMER_AR_ARRV_POSS,TIMER_AR_ARRV_POSE) - -/****************** Bit definition for TIMER_REPAR register ************************/ - -#define TIMER_REPAR_REPV_POSS 0U -#define TIMER_REPAR_REPV_POSE 7U -#define TIMER_REPAR_REPV_MSK BITS(TIMER_REPAR_REPV_POSS,TIMER_REPAR_REPV_POSE) - -/****************** Bit definition for TIMER_CCVAL1 register ************************/ - -#define TIMER_CCVAL1_CCRV1_POSS 0U -#define TIMER_CCVAL1_CCRV1_POSE 15U -#define TIMER_CCVAL1_CCRV1_MSK BITS(TIMER_CCVAL1_CCRV1_POSS,TIMER_CCVAL1_CCRV1_POSE) - -/****************** Bit definition for TIMER_CCVAL2 register ************************/ - -#define TIMER_CCVAL2_CCRV2_POSS 0U -#define TIMER_CCVAL2_CCRV2_POSE 15U -#define TIMER_CCVAL2_CCRV2_MSK BITS(TIMER_CCVAL2_CCRV2_POSS,TIMER_CCVAL2_CCRV2_POSE) - -/****************** Bit definition for TIMER_CCVAL3 register ************************/ - -#define TIMER_CCVAL3_CCRV3_POSS 0U -#define TIMER_CCVAL3_CCRV3_POSE 15U -#define TIMER_CCVAL3_CCRV3_MSK BITS(TIMER_CCVAL3_CCRV3_POSS,TIMER_CCVAL3_CCRV3_POSE) - -/****************** Bit definition for TIMER_CCVAL4 register ************************/ - -#define TIMER_CCVAL4_CCRV4_POSS 0U -#define TIMER_CCVAL4_CCRV4_POSE 15U -#define TIMER_CCVAL4_CCRV4_MSK BITS(TIMER_CCVAL4_CCRV4_POSS,TIMER_CCVAL4_CCRV4_POSE) - -/****************** Bit definition for TIMER_BDCFG register ************************/ - -#define TIMER_BDCFG_GOEN_POS 15U -#define TIMER_BDCFG_GOEN_MSK BIT(TIMER_BDCFG_GOEN_POS) - -#define TIMER_BDCFG_AOEN_POS 14U -#define TIMER_BDCFG_AOEN_MSK BIT(TIMER_BDCFG_AOEN_POS) - -#define TIMER_BDCFG_BRKP_POS 13U -#define TIMER_BDCFG_BRKP_MSK BIT(TIMER_BDCFG_BRKP_POS) - -#define TIMER_BDCFG_BRKEN_POS 12U -#define TIMER_BDCFG_BRKEN_MSK BIT(TIMER_BDCFG_BRKEN_POS) - -#define TIMER_BDCFG_OFFSSR_POS 11U -#define TIMER_BDCFG_OFFSSR_MSK BIT(TIMER_BDCFG_OFFSSR_POS) - -#define TIMER_BDCFG_OFFSSI_POS 10U -#define TIMER_BDCFG_OFFSSI_MSK BIT(TIMER_BDCFG_OFFSSI_POS) - -#define TIMER_BDCFG_LOCKLVL_POSS 8U -#define TIMER_BDCFG_LOCKLVL_POSE 9U -#define TIMER_BDCFG_LOCKLVL_MSK BITS(TIMER_BDCFG_LOCKLVL_POSS,TIMER_BDCFG_LOCKLVL_POSE) - -#define TIMER_BDCFG_DT_POSS 0U -#define TIMER_BDCFG_DT_POSE 7U -#define TIMER_BDCFG_DT_MSK BITS(TIMER_BDCFG_DT_POSS,TIMER_BDCFG_DT_POSE) - -typedef struct -{ - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t SMCON; - __O uint32_t DIER; - __O uint32_t DIDR; - __I uint32_t DIVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; - __O uint32_t SGE; - __IO uint32_t CHMR1; - __IO uint32_t CHMR2; - __IO uint32_t CCEP; - __IO uint32_t COUNT; - __IO uint32_t PRES; - __IO uint32_t AR; - __IO uint32_t REPAR; - __IO uint32_t CCVAL1; - __IO uint32_t CCVAL2; - __IO uint32_t CCVAL3; - __IO uint32_t CCVAL4; - __IO uint32_t BDCFG; -} TIMER_TypeDef; - -/****************** Bit definition for USART_STAT register ************************/ - -#define USART_STAT_CTSIF_POS 9U -#define USART_STAT_CTSIF_MSK BIT(USART_STAT_CTSIF_POS) - -#define USART_STAT_TXEMPIF_POS 7U -#define USART_STAT_TXEMPIF_MSK BIT(USART_STAT_TXEMPIF_POS) - -#define USART_STAT_TXCIF_POS 6U -#define USART_STAT_TXCIF_MSK BIT(USART_STAT_TXCIF_POS) - -#define USART_STAT_RXNEIF_POS 5U -#define USART_STAT_RXNEIF_MSK BIT(USART_STAT_RXNEIF_POS) - -#define USART_STAT_IDLEIF_POS 4U -#define USART_STAT_IDLEIF_MSK BIT(USART_STAT_IDLEIF_POS) - -#define USART_STAT_OVRIF_POS 3U -#define USART_STAT_OVRIF_MSK BIT(USART_STAT_OVRIF_POS) - -#define USART_STAT_NDETIF_POS 2U -#define USART_STAT_NDETIF_MSK BIT(USART_STAT_NDETIF_POS) - -#define USART_STAT_FERRIF_POS 1U -#define USART_STAT_FERRIF_MSK BIT(USART_STAT_FERRIF_POS) - -#define USART_STAT_PERRIF_POS 0U -#define USART_STAT_PERRIF_MSK BIT(USART_STAT_PERRIF_POS) - -/****************** Bit definition for USART_DATA register ************************/ - -#define USART_DATA_VAL_POSS 0U -#define USART_DATA_VAL_POSE 8U -#define USART_DATA_VAL_MSK BITS(USART_DATA_VAL_POSS,USART_DATA_VAL_POSE) - -/****************** Bit definition for USART_BAUDCON register ************************/ - -#define USART_BAUDCON_DIV_M_POSS 4U -#define USART_BAUDCON_DIV_M_POSE 15U -#define USART_BAUDCON_DIV_M_MSK BITS(USART_BAUDCON_DIV_M_POSS,USART_BAUDCON_DIV_M_POSE) - -#define USART_BAUDCON_DIV_F_POSS 0U -#define USART_BAUDCON_DIV_F_POSE 3U -#define USART_BAUDCON_DIV_F_MSK BITS(USART_BAUDCON_DIV_F_POSS,USART_BAUDCON_DIV_F_POSE) - -/****************** Bit definition for USART_CON0 register ************************/ - -#define USART_CON0_EN_POS 13U -#define USART_CON0_EN_MSK BIT(USART_CON0_EN_POS) - -#define USART_CON0_DLEN_POS 12U -#define USART_CON0_DLEN_MSK BIT(USART_CON0_DLEN_POS) - -#define USART_CON0_WKMOD_POS 11U -#define USART_CON0_WKMOD_MSK BIT(USART_CON0_WKMOD_POS) - -#define USART_CON0_PEN_POS 10U -#define USART_CON0_PEN_MSK BIT(USART_CON0_PEN_POS) - -#define USART_CON0_PSEL_POS 9U -#define USART_CON0_PSEL_MSK BIT(USART_CON0_PSEL_POS) - -#define USART_CON0_PERRIE_POS 8U -#define USART_CON0_PERRIE_MSK BIT(USART_CON0_PERRIE_POS) - -#define USART_CON0_TXEMPIE_POS 7U -#define USART_CON0_TXEMPIE_MSK BIT(USART_CON0_TXEMPIE_POS) - -#define USART_CON0_TXCIE_POS 6U -#define USART_CON0_TXCIE_MSK BIT(USART_CON0_TXCIE_POS) - -#define USART_CON0_RXNEIE_POS 5U -#define USART_CON0_RXNEIE_MSK BIT(USART_CON0_RXNEIE_POS) - -#define USART_CON0_IDLEIE_POS 4U -#define USART_CON0_IDLEIE_MSK BIT(USART_CON0_IDLEIE_POS) - -#define USART_CON0_TXEN_POS 3U -#define USART_CON0_TXEN_MSK BIT(USART_CON0_TXEN_POS) - -#define USART_CON0_RXEN_POS 2U -#define USART_CON0_RXEN_MSK BIT(USART_CON0_RXEN_POS) - -#define USART_CON0_RXWK_POS 1U -#define USART_CON0_RXWK_MSK BIT(USART_CON0_RXWK_POS) - -/****************** Bit definition for USART_CON1 register ************************/ - -#define USART_CON1_STPLEN_POSS 12U -#define USART_CON1_STPLEN_POSE 13U -#define USART_CON1_STPLEN_MSK BITS(USART_CON1_STPLEN_POSS,USART_CON1_STPLEN_POSE) - -#define USART_CON1_SCKEN_POS 11U -#define USART_CON1_SCKEN_MSK BIT(USART_CON1_SCKEN_POS) - -#define USART_CON1_SCKPOL_POS 10U -#define USART_CON1_SCKPOL_MSK BIT(USART_CON1_SCKPOL_POS) - -#define USART_CON1_SCKPHA_POS 9U -#define USART_CON1_SCKPHA_MSK BIT(USART_CON1_SCKPHA_POS) - -#define USART_CON1_LBCP_POS 8U -#define USART_CON1_LBCP_MSK BIT(USART_CON1_LBCP_POS) - -#define USART_CON1_ADDR_POSS 0U -#define USART_CON1_ADDR_POSE 3U -#define USART_CON1_ADDR_MSK BITS(USART_CON1_ADDR_POSS,USART_CON1_ADDR_POSE) - -/****************** Bit definition for USART_CON2 register ************************/ - -#define USART_CON2_CTSIE_POS 10U -#define USART_CON2_CTSIE_MSK BIT(USART_CON2_CTSIE_POS) - -#define USART_CON2_CTSEN_POS 9U -#define USART_CON2_CTSEN_MSK BIT(USART_CON2_CTSEN_POS) - -#define USART_CON2_RTSEN_POS 8U -#define USART_CON2_RTSEN_MSK BIT(USART_CON2_RTSEN_POS) - -#define USART_CON2_TXDMAEN_POS 7U -#define USART_CON2_TXDMAEN_MSK BIT(USART_CON2_TXDMAEN_POS) - -#define USART_CON2_RXDMAEN_POS 6U -#define USART_CON2_RXDMAEN_MSK BIT(USART_CON2_RXDMAEN_POS) - -#define USART_CON2_SMARTEN_POS 5U -#define USART_CON2_SMARTEN_MSK BIT(USART_CON2_SMARTEN_POS) - -#define USART_CON2_NACK_POS 4U -#define USART_CON2_NACK_MSK BIT(USART_CON2_NACK_POS) - -#define USART_CON2_HDPSEL_POS 3U -#define USART_CON2_HDPSEL_MSK BIT(USART_CON2_HDPSEL_POS) - -#define USART_CON2_IREN_POS 1U -#define USART_CON2_IREN_MSK BIT(USART_CON2_IREN_POS) - -#define USART_CON2_ERRIE_POS 0U -#define USART_CON2_ERRIE_MSK BIT(USART_CON2_ERRIE_POS) - -/****************** Bit definition for USART_GP register ************************/ - -#define USART_GP_GTVAL_POSS 8U -#define USART_GP_GTVAL_POSE 15U -#define USART_GP_GTVAL_MSK BITS(USART_GP_GTVAL_POSS,USART_GP_GTVAL_POSE) - -#define USART_GP_PSC_POSS 0U -#define USART_GP_PSC_POSE 7U -#define USART_GP_PSC_MSK BITS(USART_GP_PSC_POSS,USART_GP_PSC_POSE) - -typedef struct -{ - __IO uint32_t STAT; - __IO uint32_t DATA; - __IO uint32_t BAUDCON; - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t GP; -} USART_TypeDef; - -/****************** Bit definition for UART_RBR register ************************/ - -#define UART_RBR_RBR_POSS 0U -#define UART_RBR_RBR_POSE 8U -#define UART_RBR_RBR_MSK BITS(UART_RBR_RBR_POSS,UART_RBR_RBR_POSE) - -/****************** Bit definition for UART_TBR register ************************/ - -#define UART_TBR_TBR_POSS 0U -#define UART_TBR_TBR_POSE 8U -#define UART_TBR_TBR_MSK BITS(UART_TBR_TBR_POSS,UART_TBR_TBR_POSE) - -/****************** Bit definition for UART_BRR register ************************/ - -#define UART_BRR_BRR_POSS 0U -#define UART_BRR_BRR_POSE 15U -#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) - -/****************** Bit definition for UART_LCR register ************************/ - -#define UART_LCR_SWAP_POS 13U -#define UART_LCR_SWAP_MSK BIT(UART_LCR_SWAP_POS) - -#define UART_LCR_TXINV_POS 12U -#define UART_LCR_TXINV_MSK BIT(UART_LCR_TXINV_POS) - -#define UART_LCR_RXINV_POS 11U -#define UART_LCR_RXINV_MSK BIT(UART_LCR_RXINV_POS) - -#define UART_LCR_DATAINV_POS 10U -#define UART_LCR_DATAINV_MSK BIT(UART_LCR_DATAINV_POS) - -#define UART_LCR_MSBFIRST_POS 9U -#define UART_LCR_MSBFIRST_MSK BIT(UART_LCR_MSBFIRST_POS) - -#define UART_LCR_RTOEN_POS 8U -#define UART_LCR_RTOEN_MSK BIT(UART_LCR_RTOEN_POS) - -#define UART_LCR_BRWEN_POS 7U -#define UART_LCR_BRWEN_MSK BIT(UART_LCR_BRWEN_POS) - -#define UART_LCR_BC_POS 6U -#define UART_LCR_BC_MSK BIT(UART_LCR_BC_POS) - -#define UART_LCR_RXEN_POS 5U -#define UART_LCR_RXEN_MSK BIT(UART_LCR_RXEN_POS) - -#define UART_LCR_PS_POS 4U -#define UART_LCR_PS_MSK BIT(UART_LCR_PS_POS) - -#define UART_LCR_PEN_POS 3U -#define UART_LCR_PEN_MSK BIT(UART_LCR_PEN_POS) - -#define UART_LCR_STOP_POS 2U -#define UART_LCR_STOP_MSK BIT(UART_LCR_STOP_POS) - -#define UART_LCR_DLS_POSS 0U -#define UART_LCR_DLS_POSE 1U -#define UART_LCR_DLS_MSK BITS(UART_LCR_DLS_POSS,UART_LCR_DLS_POSE) - -/****************** Bit definition for UART_MCR register ************************/ - -#define UART_MCR_HDSEL_POS 22U -#define UART_MCR_HDSEL_MSK BIT(UART_MCR_HDSEL_POS) - -#define UART_MCR_ABRRS_POS 15U -#define UART_MCR_ABRRS_MSK BIT(UART_MCR_ABRRS_POS) - -#define UART_MCR_ABRMOD_POSS 13U -#define UART_MCR_ABRMOD_POSE 14U -#define UART_MCR_ABRMOD_MSK BITS(UART_MCR_ABRMOD_POSS,UART_MCR_ABRMOD_POSE) - -#define UART_MCR_ABREN_POS 12U -#define UART_MCR_ABREN_MSK BIT(UART_MCR_ABREN_POS) - -#define UART_MCR_DMAEN_POS 11U -#define UART_MCR_DMAEN_MSK BIT(UART_MCR_DMAEN_POS) - -#define UART_MCR_LINBDL_POS 10U -#define UART_MCR_LINBDL_MSK BIT(UART_MCR_LINBDL_POS) - -#define UART_MCR_BKREQ_POS 9U -#define UART_MCR_BKREQ_MSK BIT(UART_MCR_BKREQ_POS) - -#define UART_MCR_LINEN_POS 8U -#define UART_MCR_LINEN_MSK BIT(UART_MCR_LINEN_POS) - -#define UART_MCR_AADINV_POS 7U -#define UART_MCR_AADINV_MSK BIT(UART_MCR_AADINV_POS) - -#define UART_MCR_AADDIR_POS 6U -#define UART_MCR_AADDIR_MSK BIT(UART_MCR_AADDIR_POS) - -#define UART_MCR_AADNOR_POS 5U -#define UART_MCR_AADNOR_MSK BIT(UART_MCR_AADNOR_POS) - -#define UART_MCR_AADEN_POS 4U -#define UART_MCR_AADEN_MSK BIT(UART_MCR_AADEN_POS) - -#define UART_MCR_RTSCTRL_POS 3U -#define UART_MCR_RTSCTRL_MSK BIT(UART_MCR_RTSCTRL_POS) - -#define UART_MCR_AFCEN_POS 2U -#define UART_MCR_AFCEN_MSK BIT(UART_MCR_AFCEN_POS) - -#define UART_MCR_LBEN_POS 1U -#define UART_MCR_LBEN_MSK BIT(UART_MCR_LBEN_POS) - -#define UART_MCR_IREN_POS 0U -#define UART_MCR_IREN_MSK BIT(UART_MCR_IREN_POS) - -/****************** Bit definition for UART_CR register ************************/ - -#define UART_CR_PSC_POSS 16U -#define UART_CR_PSC_POSE 23U -#define UART_CR_PSC_MSK BITS(UART_CR_PSC_POSS,UART_CR_PSC_POSE) - -#define UART_CR_DLY_POSS 8U -#define UART_CR_DLY_POSE 15U -#define UART_CR_DLY_MSK BITS(UART_CR_DLY_POSS,UART_CR_DLY_POSE) - -#define UART_CR_ADDR_POSS 0U -#define UART_CR_ADDR_POSE 7U -#define UART_CR_ADDR_MSK BITS(UART_CR_ADDR_POSS,UART_CR_ADDR_POSE) - -/****************** Bit definition for UART_RTOR register ************************/ - -#define UART_RTOR_BLEN_POSS 24U -#define UART_RTOR_BLEN_POSE 31U -#define UART_RTOR_BLEN_MSK BITS(UART_RTOR_BLEN_POSS,UART_RTOR_BLEN_POSE) - -#define UART_RTOR_RTO_POSS 0U -#define UART_RTOR_RTO_POSE 23U -#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) - -/****************** Bit definition for UART_FCR register ************************/ - -#define UART_FCR_TXFL_POSS 12U -#define UART_FCR_TXFL_POSE 15U -#define UART_FCR_TXFL_MSK BITS(UART_FCR_TXFL_POSS,UART_FCR_TXFL_POSE) - -#define UART_FCR_RXFL_POSS 8U -#define UART_FCR_RXFL_POSE 11U -#define UART_FCR_RXFL_MSK BITS(UART_FCR_RXFL_POSS,UART_FCR_RXFL_POSE) - -#define UART_FCR_TXTL_POSS 6U -#define UART_FCR_TXTL_POSE 7U -#define UART_FCR_TXTL_MSK BITS(UART_FCR_TXTL_POSS,UART_FCR_TXTL_POSE) - -#define UART_FCR_RXTL_POSS 4U -#define UART_FCR_RXTL_POSE 5U -#define UART_FCR_RXTL_MSK BITS(UART_FCR_RXTL_POSS,UART_FCR_RXTL_POSE) - -#define UART_FCR_TFRST_POS 2U -#define UART_FCR_TFRST_MSK BIT(UART_FCR_TFRST_POS) - -#define UART_FCR_RFRST_POS 1U -#define UART_FCR_RFRST_MSK BIT(UART_FCR_RFRST_POS) - -#define UART_FCR_FIFOEN_POS 0U -#define UART_FCR_FIFOEN_MSK BIT(UART_FCR_FIFOEN_POS) - -/****************** Bit definition for UART_SR register ************************/ - -#define UART_SR_CTS_POS 14U -#define UART_SR_CTS_MSK BIT(UART_SR_CTS_POS) - -#define UART_SR_DCTS_POS 13U -#define UART_SR_DCTS_MSK BIT(UART_SR_DCTS_POS) - -#define UART_SR_RFF_POS 12U -#define UART_SR_RFF_MSK BIT(UART_SR_RFF_POS) - -#define UART_SR_RFNE_POS 11U -#define UART_SR_RFNE_MSK BIT(UART_SR_RFNE_POS) - -#define UART_SR_TFEM_POS 10U -#define UART_SR_TFEM_MSK BIT(UART_SR_TFEM_POS) - -#define UART_SR_TFNF_POS 9U -#define UART_SR_TFNF_MSK BIT(UART_SR_TFNF_POS) - -#define UART_SR_BUSY_POS 8U -#define UART_SR_BUSY_MSK BIT(UART_SR_BUSY_POS) - -#define UART_SR_RFE_POS 7U -#define UART_SR_RFE_MSK BIT(UART_SR_RFE_POS) - -#define UART_SR_TEM_POS 6U -#define UART_SR_TEM_MSK BIT(UART_SR_TEM_POS) - -#define UART_SR_TBEM_POS 5U -#define UART_SR_TBEM_MSK BIT(UART_SR_TBEM_POS) - -#define UART_SR_BF_POS 4U -#define UART_SR_BF_MSK BIT(UART_SR_BF_POS) - -#define UART_SR_FE_POS 3U -#define UART_SR_FE_MSK BIT(UART_SR_FE_POS) - -#define UART_SR_PE_POS 2U -#define UART_SR_PE_MSK BIT(UART_SR_PE_POS) - -#define UART_SR_OE_POS 1U -#define UART_SR_OE_MSK BIT(UART_SR_OE_POS) - -#define UART_SR_DR_POS 0U -#define UART_SR_DR_MSK BIT(UART_SR_DR_POS) - -/****************** Bit definition for UART_IER register ************************/ - -#define UART_IER_CMIE_POS 11U -#define UART_IER_CMIE_MSK BIT(UART_IER_CMIE_POS) - -#define UART_IER_EOBIE_POS 10U -#define UART_IER_EOBIE_MSK BIT(UART_IER_EOBIE_POS) - -#define UART_IER_TCIE_POS 9U -#define UART_IER_TCIE_MSK BIT(UART_IER_TCIE_POS) - -#define UART_IER_LINBKIE_POS 8U -#define UART_IER_LINBKIE_MSK BIT(UART_IER_LINBKIE_POS) - -#define UART_IER_ABTOIE_POS 7U -#define UART_IER_ABTOIE_MSK BIT(UART_IER_ABTOIE_POS) - -#define UART_IER_ABEIE_POS 6U -#define UART_IER_ABEIE_MSK BIT(UART_IER_ABEIE_POS) - -#define UART_IER_BZIE_POS 5U -#define UART_IER_BZIE_MSK BIT(UART_IER_BZIE_POS) - -#define UART_IER_RTOIE_POS 4U -#define UART_IER_RTOIE_MSK BIT(UART_IER_RTOIE_POS) - -#define UART_IER_MDSIE_POS 3U -#define UART_IER_MDSIE_MSK BIT(UART_IER_MDSIE_POS) - -#define UART_IER_RXSIE_POS 2U -#define UART_IER_RXSIE_MSK BIT(UART_IER_RXSIE_POS) - -#define UART_IER_TXSIE_POS 1U -#define UART_IER_TXSIE_MSK BIT(UART_IER_TXSIE_POS) - -#define UART_IER_RXRDIE_POS 0U -#define UART_IER_RXRDIE_MSK BIT(UART_IER_RXRDIE_POS) - -/****************** Bit definition for UART_IDR register ************************/ - -#define UART_IDR_CMID_POS 11U -#define UART_IDR_CMID_MSK BIT(UART_IDR_CMID_POS) - -#define UART_IDR_EOBID_POS 10U -#define UART_IDR_EOBID_MSK BIT(UART_IDR_EOBID_POS) - -#define UART_IDR_TCID_POS 9U -#define UART_IDR_TCID_MSK BIT(UART_IDR_TCID_POS) - -#define UART_IDR_LINBKID_POS 8U -#define UART_IDR_LINBKID_MSK BIT(UART_IDR_LINBKID_POS) - -#define UART_IDR_ABTOID_POS 7U -#define UART_IDR_ABTOID_MSK BIT(UART_IDR_ABTOID_POS) - -#define UART_IDR_ABEID_POS 6U -#define UART_IDR_ABEID_MSK BIT(UART_IDR_ABEID_POS) - -#define UART_IDR_BZID_POS 5U -#define UART_IDR_BZID_MSK BIT(UART_IDR_BZID_POS) - -#define UART_IDR_RTOID_POS 4U -#define UART_IDR_RTOID_MSK BIT(UART_IDR_RTOID_POS) - -#define UART_IDR_MDSID_POS 3U -#define UART_IDR_MDSID_MSK BIT(UART_IDR_MDSID_POS) - -#define UART_IDR_RXSID_POS 2U -#define UART_IDR_RXSID_MSK BIT(UART_IDR_RXSID_POS) - -#define UART_IDR_TXSID_POS 1U -#define UART_IDR_TXSID_MSK BIT(UART_IDR_TXSID_POS) - -#define UART_IDR_RXRDID_POS 0U -#define UART_IDR_RXRDID_MSK BIT(UART_IDR_RXRDID_POS) - -/****************** Bit definition for UART_IVS register ************************/ - -#define UART_IVS_CMIS_POS 11U -#define UART_IVS_CMIS_MSK BIT(UART_IVS_CMIS_POS) - -#define UART_IVS_EOBIS_POS 10U -#define UART_IVS_EOBIS_MSK BIT(UART_IVS_EOBIS_POS) - -#define UART_IVS_TCIS_POS 9U -#define UART_IVS_TCIS_MSK BIT(UART_IVS_TCIS_POS) - -#define UART_IVS_LINBKIS_POS 8U -#define UART_IVS_LINBKIS_MSK BIT(UART_IVS_LINBKIS_POS) - -#define UART_IVS_ABTOIS_POS 7U -#define UART_IVS_ABTOIS_MSK BIT(UART_IVS_ABTOIS_POS) - -#define UART_IVS_ABEIS_POS 6U -#define UART_IVS_ABEIS_MSK BIT(UART_IVS_ABEIS_POS) - -#define UART_IVS_BZIS_POS 5U -#define UART_IVS_BZIS_MSK BIT(UART_IVS_BZIS_POS) - -#define UART_IVS_RTOIS_POS 4U -#define UART_IVS_RTOIS_MSK BIT(UART_IVS_RTOIS_POS) - -#define UART_IVS_MDSIS_POS 3U -#define UART_IVS_MDSIS_MSK BIT(UART_IVS_MDSIS_POS) - -#define UART_IVS_RXSIS_POS 2U -#define UART_IVS_RXSIS_MSK BIT(UART_IVS_RXSIS_POS) - -#define UART_IVS_TXSIS_POS 1U -#define UART_IVS_TXSIS_MSK BIT(UART_IVS_TXSIS_POS) - -#define UART_IVS_RXRDIS_POS 0U -#define UART_IVS_RXRDIS_MSK BIT(UART_IVS_RXRDIS_POS) - -/****************** Bit definition for UART_RIF register ************************/ - -#define UART_RIF_CMIF_POS 11U -#define UART_RIF_CMIF_MSK BIT(UART_RIF_CMIF_POS) - -#define UART_RIF_EOBIF_POS 10U -#define UART_RIF_EOBIF_MSK BIT(UART_RIF_EOBIF_POS) - -#define UART_RIF_TCIF_POS 9U -#define UART_RIF_TCIF_MSK BIT(UART_RIF_TCIF_POS) - -#define UART_RIF_LINBKIF_POS 8U -#define UART_RIF_LINBKIF_MSK BIT(UART_RIF_LINBKIF_POS) - -#define UART_RIF_ABTOIF_POS 7U -#define UART_RIF_ABTOIF_MSK BIT(UART_RIF_ABTOIF_POS) - -#define UART_RIF_ABEIF_POS 6U -#define UART_RIF_ABEIF_MSK BIT(UART_RIF_ABEIF_POS) - -#define UART_RIF_BZIF_POS 5U -#define UART_RIF_BZIF_MSK BIT(UART_RIF_BZIF_POS) - -#define UART_RIF_RTOIF_POS 4U -#define UART_RIF_RTOIF_MSK BIT(UART_RIF_RTOIF_POS) - -#define UART_RIF_MDSIF_POS 3U -#define UART_RIF_MDSIF_MSK BIT(UART_RIF_MDSIF_POS) - -#define UART_RIF_RXSIF_POS 2U -#define UART_RIF_RXSIF_MSK BIT(UART_RIF_RXSIF_POS) - -#define UART_RIF_TXSIF_POS 1U -#define UART_RIF_TXSIF_MSK BIT(UART_RIF_TXSIF_POS) - -#define UART_RIF_RXRDIF_POS 0U -#define UART_RIF_RXRDIF_MSK BIT(UART_RIF_RXRDIF_POS) - -/****************** Bit definition for UART_IFM register ************************/ - -#define UART_IFM_CMIM_POS 11U -#define UART_IFM_CMIM_MSK BIT(UART_IFM_CMIM_POS) - -#define UART_IFM_EOBIM_POS 10U -#define UART_IFM_EOBIM_MSK BIT(UART_IFM_EOBIM_POS) - -#define UART_IFM_TCIM_POS 9U -#define UART_IFM_TCIM_MSK BIT(UART_IFM_TCIM_POS) - -#define UART_IFM_LINBKIM_POS 8U -#define UART_IFM_LINBKIM_MSK BIT(UART_IFM_LINBKIM_POS) - -#define UART_IFM_ABTOIM_POS 7U -#define UART_IFM_ABTOIM_MSK BIT(UART_IFM_ABTOIM_POS) - -#define UART_IFM_ABEIM_POS 6U -#define UART_IFM_ABEIM_MSK BIT(UART_IFM_ABEIM_POS) - -#define UART_IFM_BZIM_POS 5U -#define UART_IFM_BZIM_MSK BIT(UART_IFM_BZIM_POS) - -#define UART_IFM_RTOIM_POS 4U -#define UART_IFM_RTOIM_MSK BIT(UART_IFM_RTOIM_POS) - -#define UART_IFM_MDSIM_POS 3U -#define UART_IFM_MDSIM_MSK BIT(UART_IFM_MDSIM_POS) - -#define UART_IFM_RXSIM_POS 2U -#define UART_IFM_RXSIM_MSK BIT(UART_IFM_RXSIM_POS) - -#define UART_IFM_TXSIM_POS 1U -#define UART_IFM_TXSIM_MSK BIT(UART_IFM_TXSIM_POS) - -#define UART_IFM_RXRDIM_POS 0U -#define UART_IFM_RXRDIM_MSK BIT(UART_IFM_RXRDIM_POS) - -/****************** Bit definition for UART_ICR register ************************/ - -#define UART_ICR_CMIC_POS 11U -#define UART_ICR_CMIC_MSK BIT(UART_ICR_CMIC_POS) - -#define UART_ICR_EOBIC_POS 10U -#define UART_ICR_EOBIC_MSK BIT(UART_ICR_EOBIC_POS) - -#define UART_ICR_TCIC_POS 9U -#define UART_ICR_TCIC_MSK BIT(UART_ICR_TCIC_POS) - -#define UART_ICR_LINBKIC_POS 8U -#define UART_ICR_LINBKIC_MSK BIT(UART_ICR_LINBKIC_POS) - -#define UART_ICR_ABTOIC_POS 7U -#define UART_ICR_ABTOIC_MSK BIT(UART_ICR_ABTOIC_POS) - -#define UART_ICR_ABEIC_POS 6U -#define UART_ICR_ABEIC_MSK BIT(UART_ICR_ABEIC_POS) - -#define UART_ICR_BZIC_POS 5U -#define UART_ICR_BZIC_MSK BIT(UART_ICR_BZIC_POS) - -#define UART_ICR_CHTOIC_POS 4U -#define UART_ICR_CHTOIC_MSK BIT(UART_ICR_CHTOIC_POS) - -#define UART_ICR_MDSIC_POS 3U -#define UART_ICR_MDSIC_MSK BIT(UART_ICR_MDSIC_POS) - -#define UART_ICR_RXSIC_POS 2U -#define UART_ICR_RXSIC_MSK BIT(UART_ICR_RXSIC_POS) - -#define UART_ICR_TXSIC_POS 1U -#define UART_ICR_TXSIC_MSK BIT(UART_ICR_TXSIC_POS) - -#define UART_ICR_RXRDIC_POS 0U -#define UART_ICR_RXRDIC_MSK BIT(UART_ICR_RXRDIC_POS) - -typedef struct -{ - __I uint32_t RBR; - __IO uint32_t TBR; - __IO uint32_t BRR; - __IO uint32_t LCR; - __IO uint32_t MCR; - __IO uint32_t CR; - __IO uint32_t RTOR; - __IO uint32_t FCR; - __I uint32_t SR; - __O uint32_t IER; - __O uint32_t IDR; - __I uint32_t IVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; -} UART_TypeDef; - -/****************** Bit definition for LPUART_CON0 register ************************/ - -#define LPUART_CON0_MODESEL_POSS 30U -#define LPUART_CON0_MODESEL_POSE 31U -#define LPUART_CON0_MODESEL_MSK BITS(LPUART_CON0_MODESEL_POSS,LPUART_CON0_MODESEL_POSE) - -#define LPUART_CON0_TXDMAE_POS 29U -#define LPUART_CON0_TXDMAE_MSK BIT(LPUART_CON0_TXDMAE_POS) - -#define LPUART_CON0_RXDMAE_POS 28U -#define LPUART_CON0_RXDMAE_MSK BIT(LPUART_CON0_RXDMAE_POS) - -#define LPUART_CON0_INTERVAL_POSS 16U -#define LPUART_CON0_INTERVAL_POSE 23U -#define LPUART_CON0_INTERVAL_MSK BITS(LPUART_CON0_INTERVAL_POSS,LPUART_CON0_INTERVAL_POSE) - -#define LPUART_CON0_SYNCBP_POS 15U -#define LPUART_CON0_SYNCBP_MSK BIT(LPUART_CON0_SYNCBP_POS) - -#define LPUART_CON0_CTSPOL_POS 13U -#define LPUART_CON0_CTSPOL_MSK BIT(LPUART_CON0_CTSPOL_POS) - -#define LPUART_CON0_RTSPOL_POS 12U -#define LPUART_CON0_RTSPOL_MSK BIT(LPUART_CON0_RTSPOL_POS) - -#define LPUART_CON0_ATCTSE_POS 11U -#define LPUART_CON0_ATCTSE_MSK BIT(LPUART_CON0_ATCTSE_POS) - -#define LPUART_CON0_ATRTSE_POS 10U -#define LPUART_CON0_ATRTSE_MSK BIT(LPUART_CON0_ATRTSE_POS) - -#define LPUART_CON0_BRKCE_POS 8U -#define LPUART_CON0_BRKCE_MSK BIT(LPUART_CON0_BRKCE_POS) - -#define LPUART_CON0_LPBMOD_POS 7U -#define LPUART_CON0_LPBMOD_MSK BIT(LPUART_CON0_LPBMOD_POS) - -#define LPUART_CON0_STICKPARSEL_POS 6U -#define LPUART_CON0_STICKPARSEL_MSK BIT(LPUART_CON0_STICKPARSEL_POS) - -#define LPUART_CON0_EVENPARSEL_POS 5U -#define LPUART_CON0_EVENPARSEL_MSK BIT(LPUART_CON0_EVENPARSEL_POS) - -#define LPUART_CON0_PARCHKE_POS 4U -#define LPUART_CON0_PARCHKE_MSK BIT(LPUART_CON0_PARCHKE_POS) - -#define LPUART_CON0_STPLENTH_POS 3U -#define LPUART_CON0_STPLENTH_MSK BIT(LPUART_CON0_STPLENTH_POS) - -#define LPUART_CON0_DATLENTH_POSS 0U -#define LPUART_CON0_DATLENTH_POSE 2U -#define LPUART_CON0_DATLENTH_MSK BITS(LPUART_CON0_DATLENTH_POSS,LPUART_CON0_DATLENTH_POSE) - -/****************** Bit definition for LPUART_CON1 register ************************/ - -#define LPUART_CON1_ADDCMP_POSS 24U -#define LPUART_CON1_ADDCMP_POSE 31U -#define LPUART_CON1_ADDCMP_MSK BITS(LPUART_CON1_ADDCMP_POSS,LPUART_CON1_ADDCMP_POSE) - -#define LPUART_CON1_ADETE_POS 23U -#define LPUART_CON1_ADETE_MSK BIT(LPUART_CON1_ADETE_POS) - -#define LPUART_CON1_ATDIRM_POS 22U -#define LPUART_CON1_ATDIRM_MSK BIT(LPUART_CON1_ATDIRM_POS) - -#define LPUART_CON1_ATADETE_POS 21U -#define LPUART_CON1_ATADETE_MSK BIT(LPUART_CON1_ATADETE_POS) - -#define LPUART_CON1_NMPMOD_POS 20U -#define LPUART_CON1_NMPMOD_MSK BIT(LPUART_CON1_NMPMOD_POS) - -#define LPUART_CON1_IRWIDTH_POS 16U -#define LPUART_CON1_IRWIDTH_MSK BIT(LPUART_CON1_IRWIDTH_POS) - -#define LPUART_CON1_TOICMP_POSS 8U -#define LPUART_CON1_TOICMP_POSE 15U -#define LPUART_CON1_TOICMP_MSK BITS(LPUART_CON1_TOICMP_POSS,LPUART_CON1_TOICMP_POSE) - -#define LPUART_CON1_TOCNTE_POS 7U -#define LPUART_CON1_TOCNTE_MSK BIT(LPUART_CON1_TOCNTE_POS) - -#define LPUART_CON1_IRTXINV_POS 3U -#define LPUART_CON1_IRTXINV_MSK BIT(LPUART_CON1_IRTXINV_POS) - -#define LPUART_CON1_IRRXINV_POS 2U -#define LPUART_CON1_IRRXINV_MSK BIT(LPUART_CON1_IRRXINV_POS) - -#define LPUART_CON1_IRTXE_POS 1U -#define LPUART_CON1_IRTXE_MSK BIT(LPUART_CON1_IRTXE_POS) - -#define LPUART_CON1_RTS_POS 0U -#define LPUART_CON1_RTS_MSK BIT(LPUART_CON1_RTS_POS) - -/****************** Bit definition for LPUART_CLKDIV register ************************/ - -#define LPUART_CLKDIV_CLKDIV_POSS 0U -#define LPUART_CLKDIV_CLKDIV_POSE 19U -#define LPUART_CLKDIV_CLKDIV_MSK BITS(LPUART_CLKDIV_CLKDIV_POSS,LPUART_CLKDIV_CLKDIV_POSE) - -/****************** Bit definition for LPUART_FIFOCON register ************************/ - -#define LPUART_FIFOCON_RTSTRGLVL_POSS 12U -#define LPUART_FIFOCON_RTSTRGLVL_POSE 15U -#define LPUART_FIFOCON_RTSTRGLVL_MSK BITS(LPUART_FIFOCON_RTSTRGLVL_POSS,LPUART_FIFOCON_RTSTRGLVL_POSE) - -#define LPUART_FIFOCON_RXTRGLVL_POSS 8U -#define LPUART_FIFOCON_RXTRGLVL_POSE 11U -#define LPUART_FIFOCON_RXTRGLVL_MSK BITS(LPUART_FIFOCON_RXTRGLVL_POSS,LPUART_FIFOCON_RXTRGLVL_POSE) - -#define LPUART_FIFOCON_NMPMRXDIS_POS 2U -#define LPUART_FIFOCON_NMPMRXDIS_MSK BIT(LPUART_FIFOCON_NMPMRXDIS_POS) - -#define LPUART_FIFOCON_TXRESET_POS 1U -#define LPUART_FIFOCON_TXRESET_MSK BIT(LPUART_FIFOCON_TXRESET_POS) - -#define LPUART_FIFOCON_RXRESET_POS 0U -#define LPUART_FIFOCON_RXRESET_MSK BIT(LPUART_FIFOCON_RXRESET_POS) - -/****************** Bit definition for LPUART_RXDR register ************************/ - -#define LPUART_RXDR_FERR_POS 15U -#define LPUART_RXDR_FERR_MSK BIT(LPUART_RXDR_FERR_POS) - -#define LPUART_RXDR_PERR_POS 14U -#define LPUART_RXDR_PERR_MSK BIT(LPUART_RXDR_PERR_POS) - -#define LPUART_RXDR_RXDR_POSS 0U -#define LPUART_RXDR_RXDR_POSE 8U -#define LPUART_RXDR_RXDR_MSK BITS(LPUART_RXDR_RXDR_POSS,LPUART_RXDR_RXDR_POSE) - -/****************** Bit definition for LPUART_TXDR register ************************/ - -#define LPUART_TXDR_TXDR_POSS 0U -#define LPUART_TXDR_TXDR_POSE 8U -#define LPUART_TXDR_TXDR_MSK BITS(LPUART_TXDR_TXDR_POSS,LPUART_TXDR_TXDR_POSE) - -/****************** Bit definition for LPUART_STAT register ************************/ - -#define LPUART_STAT_RTSSTAT_POS 18U -#define LPUART_STAT_RTSSTAT_MSK BIT(LPUART_STAT_RTSSTAT_POS) - -#define LPUART_STAT_CTSSTAT_POS 17U -#define LPUART_STAT_CTSSTAT_MSK BIT(LPUART_STAT_CTSSTAT_POS) - -#define LPUART_STAT_TXIDLE_POS 16U -#define LPUART_STAT_TXIDLE_MSK BIT(LPUART_STAT_TXIDLE_POS) - -#define LPUART_STAT_TXFULL_POS 15U -#define LPUART_STAT_TXFULL_MSK BIT(LPUART_STAT_TXFULL_POS) - -#define LPUART_STAT_TXEMP_POS 14U -#define LPUART_STAT_TXEMP_MSK BIT(LPUART_STAT_TXEMP_POS) - -#define LPUART_STAT_TXPTR_POSS 8U -#define LPUART_STAT_TXPTR_POSE 13U -#define LPUART_STAT_TXPTR_MSK BITS(LPUART_STAT_TXPTR_POSS,LPUART_STAT_TXPTR_POSE) - -#define LPUART_STAT_RXFULL_POS 7U -#define LPUART_STAT_RXFULL_MSK BIT(LPUART_STAT_RXFULL_POS) - -#define LPUART_STAT_RXEMP_POS 6U -#define LPUART_STAT_RXEMP_MSK BIT(LPUART_STAT_RXEMP_POS) - -#define LPUART_STAT_RXPTR_POSS 0U -#define LPUART_STAT_RXPTR_POSE 5U -#define LPUART_STAT_RXPTR_MSK BITS(LPUART_STAT_RXPTR_POSS,LPUART_STAT_RXPTR_POSE) - -/****************** Bit definition for LPUART_IER register ************************/ - -#define LPUART_IER_TCIE_POS 15U -#define LPUART_IER_TCIE_MSK BIT(LPUART_IER_TCIE_POS) - -#define LPUART_IER_ADETIE_POS 12U -#define LPUART_IER_ADETIE_MSK BIT(LPUART_IER_ADETIE_POS) - -#define LPUART_IER_BRKERRIE_POS 11U -#define LPUART_IER_BRKERRIE_MSK BIT(LPUART_IER_BRKERRIE_POS) - -#define LPUART_IER_FERRIE_POS 10U -#define LPUART_IER_FERRIE_MSK BIT(LPUART_IER_FERRIE_POS) - -#define LPUART_IER_PERRIE_POS 9U -#define LPUART_IER_PERRIE_MSK BIT(LPUART_IER_PERRIE_POS) - -#define LPUART_IER_DATWKIE_POS 8U -#define LPUART_IER_DATWKIE_MSK BIT(LPUART_IER_DATWKIE_POS) - -#define LPUART_IER_CTSWKIE_POS 7U -#define LPUART_IER_CTSWKIE_MSK BIT(LPUART_IER_CTSWKIE_POS) - -#define LPUART_IER_TXOVIE_POS 5U -#define LPUART_IER_TXOVIE_MSK BIT(LPUART_IER_TXOVIE_POS) - -#define LPUART_IER_RXOVIE_POS 4U -#define LPUART_IER_RXOVIE_MSK BIT(LPUART_IER_RXOVIE_POS) - -#define LPUART_IER_RXTOIE_POS 3U -#define LPUART_IER_RXTOIE_MSK BIT(LPUART_IER_RXTOIE_POS) - -#define LPUART_IER_CTSDETIE_POS 2U -#define LPUART_IER_CTSDETIE_MSK BIT(LPUART_IER_CTSDETIE_POS) - -#define LPUART_IER_TBEMPIE_POS 1U -#define LPUART_IER_TBEMPIE_MSK BIT(LPUART_IER_TBEMPIE_POS) - -#define LPUART_IER_RBRIE_POS 0U -#define LPUART_IER_RBRIE_MSK BIT(LPUART_IER_RBRIE_POS) - -/****************** Bit definition for LPUART_IFLAG register ************************/ - -#define LPUART_IFLAG_TCIF_POS 15U -#define LPUART_IFLAG_TCIF_MSK BIT(LPUART_IFLAG_TCIF_POS) - -#define LPUART_IFLAG_ADETIF_POS 12U -#define LPUART_IFLAG_ADETIF_MSK BIT(LPUART_IFLAG_ADETIF_POS) - -#define LPUART_IFLAG_BRKERRIF_POS 11U -#define LPUART_IFLAG_BRKERRIF_MSK BIT(LPUART_IFLAG_BRKERRIF_POS) - -#define LPUART_IFLAG_FERRIF_POS 10U -#define LPUART_IFLAG_FERRIF_MSK BIT(LPUART_IFLAG_FERRIF_POS) - -#define LPUART_IFLAG_PERRIF_POS 9U -#define LPUART_IFLAG_PERRIF_MSK BIT(LPUART_IFLAG_PERRIF_POS) - -#define LPUART_IFLAG_DATWKIF_POS 8U -#define LPUART_IFLAG_DATWKIF_MSK BIT(LPUART_IFLAG_DATWKIF_POS) - -#define LPUART_IFLAG_CTSWKIF_POS 7U -#define LPUART_IFLAG_CTSWKIF_MSK BIT(LPUART_IFLAG_CTSWKIF_POS) - -#define LPUART_IFLAG_TXOVIF_POS 5U -#define LPUART_IFLAG_TXOVIF_MSK BIT(LPUART_IFLAG_TXOVIF_POS) - -#define LPUART_IFLAG_RXOVIF_POS 4U -#define LPUART_IFLAG_RXOVIF_MSK BIT(LPUART_IFLAG_RXOVIF_POS) - -#define LPUART_IFLAG_RXTOIF_POS 3U -#define LPUART_IFLAG_RXTOIF_MSK BIT(LPUART_IFLAG_RXTOIF_POS) - -#define LPUART_IFLAG_CTSDETIF_POS 2U -#define LPUART_IFLAG_CTSDETIF_MSK BIT(LPUART_IFLAG_CTSDETIF_POS) - -#define LPUART_IFLAG_TBEMPIF_POS 1U -#define LPUART_IFLAG_TBEMPIF_MSK BIT(LPUART_IFLAG_TBEMPIF_POS) - -#define LPUART_IFLAG_RBRIF_POS 0U -#define LPUART_IFLAG_RBRIF_MSK BIT(LPUART_IFLAG_RBRIF_POS) - -/****************** Bit definition for LPUART_IFC register ************************/ - -#define LPUART_IFC_TCIFC_POS 15U -#define LPUART_IFC_TCIFC_MSK BIT(LPUART_IFC_TCIFC_POS) - -#define LPUART_IFC_ADETIFC_POS 12U -#define LPUART_IFC_ADETIFC_MSK BIT(LPUART_IFC_ADETIFC_POS) - -#define LPUART_IFC_BRKERRIFC_POS 11U -#define LPUART_IFC_BRKERRIFC_MSK BIT(LPUART_IFC_BRKERRIFC_POS) - -#define LPUART_IFC_FERRIFC_POS 10U -#define LPUART_IFC_FERRIFC_MSK BIT(LPUART_IFC_FERRIFC_POS) - -#define LPUART_IFC_PERRIFC_POS 9U -#define LPUART_IFC_PERRIFC_MSK BIT(LPUART_IFC_PERRIFC_POS) - -#define LPUART_IFC_DATWKIFC_POS 8U -#define LPUART_IFC_DATWKIFC_MSK BIT(LPUART_IFC_DATWKIFC_POS) - -#define LPUART_IFC_CTSWKIFC_POS 7U -#define LPUART_IFC_CTSWKIFC_MSK BIT(LPUART_IFC_CTSWKIFC_POS) - -#define LPUART_IFC_TXOVIFC_POS 5U -#define LPUART_IFC_TXOVIFC_MSK BIT(LPUART_IFC_TXOVIFC_POS) - -#define LPUART_IFC_RXOVIFC_POS 4U -#define LPUART_IFC_RXOVIFC_MSK BIT(LPUART_IFC_RXOVIFC_POS) - -#define LPUART_IFC_CTSDETIFC_POS 2U -#define LPUART_IFC_CTSDETIFC_MSK BIT(LPUART_IFC_CTSDETIFC_POS) - -#define LPUART_IFC_TBEMPIFC_POS 1U -#define LPUART_IFC_TBEMPIFC_MSK BIT(LPUART_IFC_TBEMPIFC_POS) - -#define LPUART_IFC_RBRIFC_POS 0U -#define LPUART_IFC_RBRIFC_MSK BIT(LPUART_IFC_RBRIFC_POS) - -/****************** Bit definition for LPUART_ISTAT register ************************/ - -#define LPUART_ISTAT_TCINT_POS 15U -#define LPUART_ISTAT_TCINT_MSK BIT(LPUART_ISTAT_TCINT_POS) - -#define LPUART_ISTAT_RXSTATINT_POS 9U -#define LPUART_ISTAT_RXSTATINT_MSK BIT(LPUART_ISTAT_RXSTATINT_POS) - -#define LPUART_ISTAT_DATWKINT_POS 8U -#define LPUART_ISTAT_DATWKINT_MSK BIT(LPUART_ISTAT_DATWKINT_POS) - -#define LPUART_ISTAT_CTSWKINT_POS 7U -#define LPUART_ISTAT_CTSWKINT_MSK BIT(LPUART_ISTAT_CTSWKINT_POS) - -#define LPUART_ISTAT_BUFERRINT_POS 4U -#define LPUART_ISTAT_BUFERRINT_MSK BIT(LPUART_ISTAT_BUFERRINT_POS) - -#define LPUART_ISTAT_RXTOINT_POS 3U -#define LPUART_ISTAT_RXTOINT_MSK BIT(LPUART_ISTAT_RXTOINT_POS) - -#define LPUART_ISTAT_CTSDETINT_POS 2U -#define LPUART_ISTAT_CTSDETINT_MSK BIT(LPUART_ISTAT_CTSDETINT_POS) - -#define LPUART_ISTAT_TBEMPINT_POS 1U -#define LPUART_ISTAT_TBEMPINT_MSK BIT(LPUART_ISTAT_TBEMPINT_POS) - -#define LPUART_ISTAT_RBRINT_POS 0U -#define LPUART_ISTAT_RBRINT_MSK BIT(LPUART_ISTAT_RBRINT_POS) - -/****************** Bit definition for LPUART_UPDATE register ************************/ - -#define LPUART_UPDATE_UDIS_POS 0U -#define LPUART_UPDATE_UDIS_MSK BIT(LPUART_UPDATE_UDIS_POS) - -/****************** Bit definition for LPUART_SYNCSTAT register ************************/ - -#define LPUART_SYNCSTAT_FIFOCONWBSY_POS 3U -#define LPUART_SYNCSTAT_FIFOCONWBSY_MSK BIT(LPUART_SYNCSTAT_FIFOCONWBSY_POS) - -#define LPUART_SYNCSTAT_CLKDIVWBSY_POS 2U -#define LPUART_SYNCSTAT_CLKDIVWBSY_MSK BIT(LPUART_SYNCSTAT_CLKDIVWBSY_POS) - -#define LPUART_SYNCSTAT_CON1WBSY_POS 1U -#define LPUART_SYNCSTAT_CON1WBSY_MSK BIT(LPUART_SYNCSTAT_CON1WBSY_POS) - -#define LPUART_SYNCSTAT_CON0WBSY_POS 0U -#define LPUART_SYNCSTAT_CON0WBSY_MSK BIT(LPUART_SYNCSTAT_CON0WBSY_POS) - -typedef struct -{ - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t CLKDIV; - __IO uint32_t FIFOCON; - uint32_t RESERVED0 ; - __I uint32_t RXDR; - __O uint32_t TXDR; - __I uint32_t STAT; - __IO uint32_t IER; - __I uint32_t IFLAG; - __O uint32_t IFC; - __I uint32_t ISTAT; - uint32_t RESERVED1[2] ; - __IO uint32_t UPDATE; - __I uint32_t SYNCSTAT; -} LPUART_TypeDef; - -/****************** Bit definition for SPI_CON1 register ************************/ - -#define SPI_CON1_BIDEN_POS 15U -#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) - -#define SPI_CON1_BIDOEN_POS 14U -#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) - -#define SPI_CON1_CRCEN_POS 13U -#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) - -#define SPI_CON1_NXTCRC_POS 12U -#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) - -#define SPI_CON1_FLEN_POS 11U -#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) - -#define SPI_CON1_RXO_POS 10U -#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) - -#define SPI_CON1_SSEN_POS 9U -#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) - -#define SPI_CON1_SSOUT_POS 8U -#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) - -#define SPI_CON1_LSBFST_POS 7U -#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) - -#define SPI_CON1_SPIEN_POS 6U -#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) - -#define SPI_CON1_BAUD_POSS 3U -#define SPI_CON1_BAUD_POSE 5U -#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) - -#define SPI_CON1_MSTREN_POS 2U -#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) - -#define SPI_CON1_CPOL_POS 1U -#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) - -#define SPI_CON1_CPHA_POS 0U -#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) - -/****************** Bit definition for SPI_CON2 register ************************/ - -#define SPI_CON2_TXBEIE_POS 7U -#define SPI_CON2_TXBEIE_MSK BIT(SPI_CON2_TXBEIE_POS) - -#define SPI_CON2_RXBNEIE_POS 6U -#define SPI_CON2_RXBNEIE_MSK BIT(SPI_CON2_RXBNEIE_POS) - -#define SPI_CON2_ERRIE_POS 5U -#define SPI_CON2_ERRIE_MSK BIT(SPI_CON2_ERRIE_POS) - -#define SPI_CON2_NSSOE_POS 2U -#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) - -#define SPI_CON2_TXDMA_POS 1U -#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) - -#define SPI_CON2_RXDMA_POS 0U -#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) - -/****************** Bit definition for SPI_STAT register ************************/ - -#define SPI_STAT_BUSY_POS 7U -#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) - -#define SPI_STAT_OVERR_POS 6U -#define SPI_STAT_OVERR_MSK BIT(SPI_STAT_OVERR_POS) - -#define SPI_STAT_MODERR_POS 5U -#define SPI_STAT_MODERR_MSK BIT(SPI_STAT_MODERR_POS) - -#define SPI_STAT_CRCERR_POS 4U -#define SPI_STAT_CRCERR_MSK BIT(SPI_STAT_CRCERR_POS) - -#define SPI_STAT_TXBE_POS 1U -#define SPI_STAT_TXBE_MSK BIT(SPI_STAT_TXBE_POS) - -#define SPI_STAT_RXBNE_POS 0U -#define SPI_STAT_RXBNE_MSK BIT(SPI_STAT_RXBNE_POS) - -/****************** Bit definition for SPI_DATA register ************************/ - -#define SPI_DATA_VALUE_POSS 0U -#define SPI_DATA_VALUE_POSE 15U -#define SPI_DATA_VALUE_MSK BITS(SPI_DATA_VALUE_POSS,SPI_DATA_VALUE_POSE) - -/****************** Bit definition for SPI_CRCPOLY register ************************/ - -#define SPI_CRCPOLY_VALUE_POSS 0U -#define SPI_CRCPOLY_VALUE_POSE 15U -#define SPI_CRCPOLY_VALUE_MSK BITS(SPI_CRCPOLY_VALUE_POSS,SPI_CRCPOLY_VALUE_POSE) - -/****************** Bit definition for SPI_RXCRC register ************************/ - -#define SPI_RXCRC_CRCVAL_POSS 0U -#define SPI_RXCRC_CRCVAL_POSE 15U -#define SPI_RXCRC_CRCVAL_MSK BITS(SPI_RXCRC_CRCVAL_POSS,SPI_RXCRC_CRCVAL_POSE) - -/****************** Bit definition for SPI_TXCRC register ************************/ - -#define SPI_TXCRC_CRCVAL_POSS 0U -#define SPI_TXCRC_CRCVAL_POSE 15U -#define SPI_TXCRC_CRCVAL_MSK BITS(SPI_TXCRC_CRCVAL_POSS,SPI_TXCRC_CRCVAL_POSE) - -typedef struct -{ - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t STAT; - __IO uint32_t DATA; - __IO uint32_t CRCPOLY; - __I uint32_t RXCRC; - __I uint32_t TXCRC; -} SPI_TypeDef; - -/****************** Bit definition for I2C_CON1 register ************************/ - -#define I2C_CON1_SRST_POS 15U -#define I2C_CON1_SRST_MSK BIT(I2C_CON1_SRST_POS) - -#define I2C_CON1_ALARM_POS 13U -#define I2C_CON1_ALARM_MSK BIT(I2C_CON1_ALARM_POS) - -#define I2C_CON1_TRPEC_POS 12U -#define I2C_CON1_TRPEC_MSK BIT(I2C_CON1_TRPEC_POS) - -#define I2C_CON1_POSAP_POS 11U -#define I2C_CON1_POSAP_MSK BIT(I2C_CON1_POSAP_POS) - -#define I2C_CON1_ACKEN_POS 10U -#define I2C_CON1_ACKEN_MSK BIT(I2C_CON1_ACKEN_POS) - -#define I2C_CON1_STOP_POS 9U -#define I2C_CON1_STOP_MSK BIT(I2C_CON1_STOP_POS) - -#define I2C_CON1_START_POS 8U -#define I2C_CON1_START_MSK BIT(I2C_CON1_START_POS) - -#define I2C_CON1_DISCS_POS 7U -#define I2C_CON1_DISCS_MSK BIT(I2C_CON1_DISCS_POS) - -#define I2C_CON1_GCEN_POS 6U -#define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) - -#define I2C_CON1_PECEN_POS 5U -#define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) - -#define I2C_CON1_ARPEN_POS 4U -#define I2C_CON1_ARPEN_MSK BIT(I2C_CON1_ARPEN_POS) - -#define I2C_CON1_SMBMOD_POS 3U -#define I2C_CON1_SMBMOD_MSK BIT(I2C_CON1_SMBMOD_POS) - -#define I2C_CON1_PMOD_POS 1U -#define I2C_CON1_PMOD_MSK BIT(I2C_CON1_PMOD_POS) - -#define I2C_CON1_PEN_POS 0U -#define I2C_CON1_PEN_MSK BIT(I2C_CON1_PEN_POS) - -/****************** Bit definition for I2C_CON2 register ************************/ - -#define I2C_CON2_LDMA_POS 12U -#define I2C_CON2_LDMA_MSK BIT(I2C_CON2_LDMA_POS) - -#define I2C_CON2_DMAEN_POS 11U -#define I2C_CON2_DMAEN_MSK BIT(I2C_CON2_DMAEN_POS) - -#define I2C_CON2_BUFIE_POS 10U -#define I2C_CON2_BUFIE_MSK BIT(I2C_CON2_BUFIE_POS) - -#define I2C_CON2_EVTIE_POS 9U -#define I2C_CON2_EVTIE_MSK BIT(I2C_CON2_EVTIE_POS) - -#define I2C_CON2_ERRIE_POS 8U -#define I2C_CON2_ERRIE_MSK BIT(I2C_CON2_ERRIE_POS) - -#define I2C_CON2_CLKF_POSS 0U -#define I2C_CON2_CLKF_POSE 5U -#define I2C_CON2_CLKF_MSK BITS(I2C_CON2_CLKF_POSS,I2C_CON2_CLKF_POSE) - -/****************** Bit definition for I2C_ADDR1 register ************************/ - -#define I2C_ADDR1_ADDTYPE_POS 15U -#define I2C_ADDR1_ADDTYPE_MSK BIT(I2C_ADDR1_ADDTYPE_POS) - -#define I2C_ADDR1_ADDH_POSS 8U -#define I2C_ADDR1_ADDH_POSE 9U -#define I2C_ADDR1_ADDH_MSK BITS(I2C_ADDR1_ADDH_POSS,I2C_ADDR1_ADDH_POSE) - -#define I2C_ADDR1_ADD_POSS 1U -#define I2C_ADDR1_ADD_POSE 7U -#define I2C_ADDR1_ADD_MSK BITS(I2C_ADDR1_ADD_POSS,I2C_ADDR1_ADD_POSE) - -#define I2C_ADDR1_ADDLSB_POS 0U -#define I2C_ADDR1_ADDLSB_MSK BIT(I2C_ADDR1_ADDLSB_POS) - -/****************** Bit definition for I2C_ADDR2 register ************************/ - -#define I2C_ADDR2_ADD_POSS 1U -#define I2C_ADDR2_ADD_POSE 7U -#define I2C_ADDR2_ADD_MSK BITS(I2C_ADDR2_ADD_POSS,I2C_ADDR2_ADD_POSE) - -#define I2C_ADDR2_DUALEN_POS 0U -#define I2C_ADDR2_DUALEN_MSK BIT(I2C_ADDR2_DUALEN_POS) - -/****************** Bit definition for I2C_DATA register ************************/ - -#define I2C_DATA_TRBUF_POSS 0U -#define I2C_DATA_TRBUF_POSE 7U -#define I2C_DATA_TRBUF_MSK BITS(I2C_DATA_TRBUF_POSS,I2C_DATA_TRBUF_POSE) - -/****************** Bit definition for I2C_STAT1 register ************************/ - -#define I2C_STAT1_SMBALARM_POS 15U -#define I2C_STAT1_SMBALARM_MSK BIT(I2C_STAT1_SMBALARM_POS) - -#define I2C_STAT1_SMBTO_POS 14U -#define I2C_STAT1_SMBTO_MSK BIT(I2C_STAT1_SMBTO_POS) - -#define I2C_STAT1_PECERR_POS 12U -#define I2C_STAT1_PECERR_MSK BIT(I2C_STAT1_PECERR_POS) - -#define I2C_STAT1_ROUERR_POS 11U -#define I2C_STAT1_ROUERR_MSK BIT(I2C_STAT1_ROUERR_POS) - -#define I2C_STAT1_ACKERR_POS 10U -#define I2C_STAT1_ACKERR_MSK BIT(I2C_STAT1_ACKERR_POS) - -#define I2C_STAT1_LARB_POS 9U -#define I2C_STAT1_LARB_MSK BIT(I2C_STAT1_LARB_POS) - -#define I2C_STAT1_BUSERR_POS 8U -#define I2C_STAT1_BUSERR_MSK BIT(I2C_STAT1_BUSERR_POS) - -#define I2C_STAT1_TXBE_POS 7U -#define I2C_STAT1_TXBE_MSK BIT(I2C_STAT1_TXBE_POS) - -#define I2C_STAT1_RXBNE_POS 6U -#define I2C_STAT1_RXBNE_MSK BIT(I2C_STAT1_RXBNE_POS) - -#define I2C_STAT1_DETSTP_POS 4U -#define I2C_STAT1_DETSTP_MSK BIT(I2C_STAT1_DETSTP_POS) - -#define I2C_STAT1_SENDADD10_POS 3U -#define I2C_STAT1_SENDADD10_MSK BIT(I2C_STAT1_SENDADD10_POS) - -#define I2C_STAT1_BTC_POS 2U -#define I2C_STAT1_BTC_MSK BIT(I2C_STAT1_BTC_POS) - -#define I2C_STAT1_ADDR_POS 1U -#define I2C_STAT1_ADDR_MSK BIT(I2C_STAT1_ADDR_POS) - -#define I2C_STAT1_SENDSTR_POS 0U -#define I2C_STAT1_SENDSTR_MSK BIT(I2C_STAT1_SENDSTR_POS) - -/****************** Bit definition for I2C_STAT2 register ************************/ - -#define I2C_STAT2_PECV_POSS 8U -#define I2C_STAT2_PECV_POSE 15U -#define I2C_STAT2_PECV_MSK BITS(I2C_STAT2_PECV_POSS,I2C_STAT2_PECV_POSE) - -#define I2C_STAT2_DMF_POS 7U -#define I2C_STAT2_DMF_MSK BIT(I2C_STAT2_DMF_POS) - -#define I2C_STAT2_SMBHH_POS 6U -#define I2C_STAT2_SMBHH_MSK BIT(I2C_STAT2_SMBHH_POS) - -#define I2C_STAT2_SMBDEF_POS 5U -#define I2C_STAT2_SMBDEF_MSK BIT(I2C_STAT2_SMBDEF_POS) - -#define I2C_STAT2_RXGCF_POS 4U -#define I2C_STAT2_RXGCF_MSK BIT(I2C_STAT2_RXGCF_POS) - -#define I2C_STAT2_TRF_POS 2U -#define I2C_STAT2_TRF_MSK BIT(I2C_STAT2_TRF_POS) - -#define I2C_STAT2_BSYF_POS 1U -#define I2C_STAT2_BSYF_MSK BIT(I2C_STAT2_BSYF_POS) - -#define I2C_STAT2_MASTER_POS 0U -#define I2C_STAT2_MASTER_MSK BIT(I2C_STAT2_MASTER_POS) - -/****************** Bit definition for I2C_CKCFG register ************************/ - -#define I2C_CKCFG_CLKMOD_POS 15U -#define I2C_CKCFG_CLKMOD_MSK BIT(I2C_CKCFG_CLKMOD_POS) - -#define I2C_CKCFG_DUTY_POS 14U -#define I2C_CKCFG_DUTY_MSK BIT(I2C_CKCFG_DUTY_POS) - -#define I2C_CKCFG_CLKSET_POSS 0U -#define I2C_CKCFG_CLKSET_POSE 11U -#define I2C_CKCFG_CLKSET_MSK BITS(I2C_CKCFG_CLKSET_POSS,I2C_CKCFG_CLKSET_POSE) - -/****************** Bit definition for I2C_RT register ************************/ - -#define I2C_RT_RISET_POSS 0U -#define I2C_RT_RISET_POSE 5U -#define I2C_RT_RISET_MSK BITS(I2C_RT_RISET_POSS,I2C_RT_RISET_POSE) - -typedef struct -{ - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t ADDR1; - __IO uint32_t ADDR2; - __IO uint32_t DATA; - __IO uint32_t STAT1; - __I uint32_t STAT2; - __IO uint32_t CKCFG; - __IO uint32_t RT; -} I2C_TypeDef; - -/****************** Bit definition for CAN_CON register ************************/ - -#define CAN_CON_DBGSTP_POS 16U -#define CAN_CON_DBGSTP_MSK BIT(CAN_CON_DBGSTP_POS) - -#define CAN_CON_RST_POS 15U -#define CAN_CON_RST_MSK BIT(CAN_CON_RST_POS) - -#define CAN_CON_TTCEN_POS 7U -#define CAN_CON_TTCEN_MSK BIT(CAN_CON_TTCEN_POS) - -#define CAN_CON_ABOFFEN_POS 6U -#define CAN_CON_ABOFFEN_MSK BIT(CAN_CON_ABOFFEN_POS) - -#define CAN_CON_AWKEN_POS 5U -#define CAN_CON_AWKEN_MSK BIT(CAN_CON_AWKEN_POS) - -#define CAN_CON_ARTXDIS_POS 4U -#define CAN_CON_ARTXDIS_MSK BIT(CAN_CON_ARTXDIS_POS) - -#define CAN_CON_RXFOPM_POS 3U -#define CAN_CON_RXFOPM_MSK BIT(CAN_CON_RXFOPM_POS) - -#define CAN_CON_TXMP_POS 2U -#define CAN_CON_TXMP_MSK BIT(CAN_CON_TXMP_POS) - -#define CAN_CON_SLPREQ_POS 1U -#define CAN_CON_SLPREQ_MSK BIT(CAN_CON_SLPREQ_POS) - -#define CAN_CON_INIREQ_POS 0U -#define CAN_CON_INIREQ_MSK BIT(CAN_CON_INIREQ_POS) - -/****************** Bit definition for CAN_STAT register ************************/ - -#define CAN_STAT_RX_POS 11U -#define CAN_STAT_RX_MSK BIT(CAN_STAT_RX_POS) - -#define CAN_STAT_PRESMP_POS 10U -#define CAN_STAT_PRESMP_MSK BIT(CAN_STAT_PRESMP_POS) - -#define CAN_STAT_RXSTAT_POS 9U -#define CAN_STAT_RXSTAT_MSK BIT(CAN_STAT_RXSTAT_POS) - -#define CAN_STAT_TXSTAT_POS 8U -#define CAN_STAT_TXSTAT_MSK BIT(CAN_STAT_TXSTAT_POS) - -#define CAN_STAT_SLPIF_POS 4U -#define CAN_STAT_SLPIF_MSK BIT(CAN_STAT_SLPIF_POS) - -#define CAN_STAT_WKIF_POS 3U -#define CAN_STAT_WKIF_MSK BIT(CAN_STAT_WKIF_POS) - -#define CAN_STAT_ERRIF_POS 2U -#define CAN_STAT_ERRIF_MSK BIT(CAN_STAT_ERRIF_POS) - -#define CAN_STAT_SLPSTAT_POS 1U -#define CAN_STAT_SLPSTAT_MSK BIT(CAN_STAT_SLPSTAT_POS) - -#define CAN_STAT_INISTAT_POS 0U -#define CAN_STAT_INISTAT_MSK BIT(CAN_STAT_INISTAT_POS) - -/****************** Bit definition for CAN_IFC register ************************/ - -#define CAN_IFC_SLPIFC_POS 4U -#define CAN_IFC_SLPIFC_MSK BIT(CAN_IFC_SLPIFC_POS) - -#define CAN_IFC_WKIFC_POS 3U -#define CAN_IFC_WKIFC_MSK BIT(CAN_IFC_WKIFC_POS) - -#define CAN_IFC_ERRIFC_POS 2U -#define CAN_IFC_ERRIFC_MSK BIT(CAN_IFC_ERRIFC_POS) - -/****************** Bit definition for CAN_TXSTAT register ************************/ - -#define CAN_TXSTAT_TXM2LPF_POS 31U -#define CAN_TXSTAT_TXM2LPF_MSK BIT(CAN_TXSTAT_TXM2LPF_POS) - -#define CAN_TXSTAT_TXM1LPF_POS 30U -#define CAN_TXSTAT_TXM1LPF_MSK BIT(CAN_TXSTAT_TXM1LPF_POS) - -#define CAN_TXSTAT_TXM0LPF_POS 29U -#define CAN_TXSTAT_TXM0LPF_MSK BIT(CAN_TXSTAT_TXM0LPF_POS) - -#define CAN_TXSTAT_TXM2EF_POS 28U -#define CAN_TXSTAT_TXM2EF_MSK BIT(CAN_TXSTAT_TXM2EF_POS) - -#define CAN_TXSTAT_TXM1EF_POS 27U -#define CAN_TXSTAT_TXM1EF_MSK BIT(CAN_TXSTAT_TXM1EF_POS) - -#define CAN_TXSTAT_TXM0EF_POS 26U -#define CAN_TXSTAT_TXM0EF_MSK BIT(CAN_TXSTAT_TXM0EF_POS) - -#define CAN_TXSTAT_CODE_POSS 24U -#define CAN_TXSTAT_CODE_POSE 25U -#define CAN_TXSTAT_CODE_MSK BITS(CAN_TXSTAT_CODE_POSS,CAN_TXSTAT_CODE_POSE) - -#define CAN_TXSTAT_M2STPREQ_POS 23U -#define CAN_TXSTAT_M2STPREQ_MSK BIT(CAN_TXSTAT_M2STPREQ_POS) - -#define CAN_TXSTAT_M2TXERR_POS 19U -#define CAN_TXSTAT_M2TXERR_MSK BIT(CAN_TXSTAT_M2TXERR_POS) - -#define CAN_TXSTAT_M2ARBLST_POS 18U -#define CAN_TXSTAT_M2ARBLST_MSK BIT(CAN_TXSTAT_M2ARBLST_POS) - -#define CAN_TXSTAT_M2TXC_POS 17U -#define CAN_TXSTAT_M2TXC_MSK BIT(CAN_TXSTAT_M2TXC_POS) - -#define CAN_TXSTAT_M2REQC_POS 16U -#define CAN_TXSTAT_M2REQC_MSK BIT(CAN_TXSTAT_M2REQC_POS) - -#define CAN_TXSTAT_M1STPREQ_POS 15U -#define CAN_TXSTAT_M1STPREQ_MSK BIT(CAN_TXSTAT_M1STPREQ_POS) - -#define CAN_TXSTAT_M1TXERR_POS 11U -#define CAN_TXSTAT_M1TXERR_MSK BIT(CAN_TXSTAT_M1TXERR_POS) - -#define CAN_TXSTAT_M1ARBLST_POS 10U -#define CAN_TXSTAT_M1ARBLST_MSK BIT(CAN_TXSTAT_M1ARBLST_POS) - -#define CAN_TXSTAT_M1TXC_POS 9U -#define CAN_TXSTAT_M1TXC_MSK BIT(CAN_TXSTAT_M1TXC_POS) - -#define CAN_TXSTAT_M1REQC_POS 8U -#define CAN_TXSTAT_M1REQC_MSK BIT(CAN_TXSTAT_M1REQC_POS) - -#define CAN_TXSTAT_M0STPREQ_POS 7U -#define CAN_TXSTAT_M0STPREQ_MSK BIT(CAN_TXSTAT_M0STPREQ_POS) - -#define CAN_TXSTAT_M0TXERR_POS 3U -#define CAN_TXSTAT_M0TXERR_MSK BIT(CAN_TXSTAT_M0TXERR_POS) - -#define CAN_TXSTAT_M0ARBLST_POS 2U -#define CAN_TXSTAT_M0ARBLST_MSK BIT(CAN_TXSTAT_M0ARBLST_POS) - -#define CAN_TXSTAT_M0TXC_POS 1U -#define CAN_TXSTAT_M0TXC_MSK BIT(CAN_TXSTAT_M0TXC_POS) - -#define CAN_TXSTAT_M0REQC_POS 0U -#define CAN_TXSTAT_M0REQC_MSK BIT(CAN_TXSTAT_M0REQC_POS) - -/****************** Bit definition for CAN_TXSTATC register ************************/ - -#define CAN_TXSTATC_M2TXERR_POS 19U -#define CAN_TXSTATC_M2TXERR_MSK BIT(CAN_TXSTATC_M2TXERR_POS) - -#define CAN_TXSTATC_M2ARBLST_POS 18U -#define CAN_TXSTATC_M2ARBLST_MSK BIT(CAN_TXSTATC_M2ARBLST_POS) - -#define CAN_TXSTATC_M2TXC_POS 17U -#define CAN_TXSTATC_M2TXC_MSK BIT(CAN_TXSTATC_M2TXC_POS) - -#define CAN_TXSTATC_M2REQC_POS 16U -#define CAN_TXSTATC_M2REQC_MSK BIT(CAN_TXSTATC_M2REQC_POS) - -#define CAN_TXSTATC_M1TXERR_POS 11U -#define CAN_TXSTATC_M1TXERR_MSK BIT(CAN_TXSTATC_M1TXERR_POS) - -#define CAN_TXSTATC_M1ARBLST_POS 10U -#define CAN_TXSTATC_M1ARBLST_MSK BIT(CAN_TXSTATC_M1ARBLST_POS) - -#define CAN_TXSTATC_M1TXC_POS 9U -#define CAN_TXSTATC_M1TXC_MSK BIT(CAN_TXSTATC_M1TXC_POS) - -#define CAN_TXSTATC_M1REQC_POS 8U -#define CAN_TXSTATC_M1REQC_MSK BIT(CAN_TXSTATC_M1REQC_POS) - -#define CAN_TXSTATC_M0TXERR_POS 3U -#define CAN_TXSTATC_M0TXERR_MSK BIT(CAN_TXSTATC_M0TXERR_POS) - -#define CAN_TXSTATC_M0ARBLST_POS 2U -#define CAN_TXSTATC_M0ARBLST_MSK BIT(CAN_TXSTATC_M0ARBLST_POS) - -#define CAN_TXSTATC_M0TXC_POS 1U -#define CAN_TXSTATC_M0TXC_MSK BIT(CAN_TXSTATC_M0TXC_POS) - -#define CAN_TXSTATC_M0REQC_POS 0U -#define CAN_TXSTATC_M0REQC_MSK BIT(CAN_TXSTATC_M0REQC_POS) - -/****************** Bit definition for CAN_RXF0 register ************************/ - -#define CAN_RXF0_FREE_POS 5U -#define CAN_RXF0_FREE_MSK BIT(CAN_RXF0_FREE_POS) - -#define CAN_RXF0_OVR_POS 4U -#define CAN_RXF0_OVR_MSK BIT(CAN_RXF0_OVR_POS) - -#define CAN_RXF0_FULL_POS 3U -#define CAN_RXF0_FULL_MSK BIT(CAN_RXF0_FULL_POS) - -#define CAN_RXF0_PEND_POSS 0U -#define CAN_RXF0_PEND_POSE 1U -#define CAN_RXF0_PEND_MSK BITS(CAN_RXF0_PEND_POSS,CAN_RXF0_PEND_POSE) - -/****************** Bit definition for CAN_RXF0C register ************************/ - -#define CAN_RXF0C_OVRC_POS 4U -#define CAN_RXF0C_OVRC_MSK BIT(CAN_RXF0C_OVRC_POS) - -#define CAN_RXF0C_FULLC_POS 3U -#define CAN_RXF0C_FULLC_MSK BIT(CAN_RXF0C_FULLC_POS) - -/****************** Bit definition for CAN_RXF1 register ************************/ - -#define CAN_RXF1_FREE_POS 5U -#define CAN_RXF1_FREE_MSK BIT(CAN_RXF1_FREE_POS) - -#define CAN_RXF1_OVR_POS 4U -#define CAN_RXF1_OVR_MSK BIT(CAN_RXF1_OVR_POS) - -#define CAN_RXF1_FULL_POS 3U -#define CAN_RXF1_FULL_MSK BIT(CAN_RXF1_FULL_POS) - -#define CAN_RXF1_PEND_POSS 0U -#define CAN_RXF1_PEND_POSE 1U -#define CAN_RXF1_PEND_MSK BITS(CAN_RXF1_PEND_POSS,CAN_RXF1_PEND_POSE) - -/****************** Bit definition for CAN_RXF1C register ************************/ - -#define CAN_RXF1C_OVRC_POS 4U -#define CAN_RXF1C_OVRC_MSK BIT(CAN_RXF1C_OVRC_POS) - -#define CAN_RXF1C_FULLC_POS 3U -#define CAN_RXF1C_FULLC_MSK BIT(CAN_RXF1C_FULLC_POS) - -/****************** Bit definition for CAN_IE register ************************/ - -#define CAN_IE_SLPIE_POS 17U -#define CAN_IE_SLPIE_MSK BIT(CAN_IE_SLPIE_POS) - -#define CAN_IE_WKIE_POS 16U -#define CAN_IE_WKIE_MSK BIT(CAN_IE_WKIE_POS) - -#define CAN_IE_ERRIE_POS 15U -#define CAN_IE_ERRIE_MSK BIT(CAN_IE_ERRIE_POS) - -#define CAN_IE_PRERRIE_POS 11U -#define CAN_IE_PRERRIE_MSK BIT(CAN_IE_PRERRIE_POS) - -#define CAN_IE_BOFFIE_POS 10U -#define CAN_IE_BOFFIE_MSK BIT(CAN_IE_BOFFIE_POS) - -#define CAN_IE_PERRIE_POS 9U -#define CAN_IE_PERRIE_MSK BIT(CAN_IE_PERRIE_POS) - -#define CAN_IE_WARNIE_POS 8U -#define CAN_IE_WARNIE_MSK BIT(CAN_IE_WARNIE_POS) - -#define CAN_IE_F1OVRIE_POS 6U -#define CAN_IE_F1OVRIE_MSK BIT(CAN_IE_F1OVRIE_POS) - -#define CAN_IE_F1FULIE_POS 5U -#define CAN_IE_F1FULIE_MSK BIT(CAN_IE_F1FULIE_POS) - -#define CAN_IE_F1PIE_POS 4U -#define CAN_IE_F1PIE_MSK BIT(CAN_IE_F1PIE_POS) - -#define CAN_IE_F0OVRIE_POS 3U -#define CAN_IE_F0OVRIE_MSK BIT(CAN_IE_F0OVRIE_POS) - -#define CAN_IE_F0FULIE_POS 2U -#define CAN_IE_F0FULIE_MSK BIT(CAN_IE_F0FULIE_POS) - -#define CAN_IE_F0PIE_POS 1U -#define CAN_IE_F0PIE_MSK BIT(CAN_IE_F0PIE_POS) - -#define CAN_IE_TXMEIE_POS 0U -#define CAN_IE_TXMEIE_MSK BIT(CAN_IE_TXMEIE_POS) - -/****************** Bit definition for CAN_ERRSTAT register ************************/ - -#define CAN_ERRSTAT_RXERRC_POSS 24U -#define CAN_ERRSTAT_RXERRC_POSE 31U -#define CAN_ERRSTAT_RXERRC_MSK BITS(CAN_ERRSTAT_RXERRC_POSS,CAN_ERRSTAT_RXERRC_POSE) - -#define CAN_ERRSTAT_TXERRC_POSS 16U -#define CAN_ERRSTAT_TXERRC_POSE 23U -#define CAN_ERRSTAT_TXERRC_MSK BITS(CAN_ERRSTAT_TXERRC_POSS,CAN_ERRSTAT_TXERRC_POSE) - -#define CAN_ERRSTAT_PRERRF_POSS 4U -#define CAN_ERRSTAT_PRERRF_POSE 6U -#define CAN_ERRSTAT_PRERRF_MSK BITS(CAN_ERRSTAT_PRERRF_POSS,CAN_ERRSTAT_PRERRF_POSE) - -#define CAN_ERRSTAT_BOFF_POS 2U -#define CAN_ERRSTAT_BOFF_MSK BIT(CAN_ERRSTAT_BOFF_POS) - -#define CAN_ERRSTAT_PERRF_POS 1U -#define CAN_ERRSTAT_PERRF_MSK BIT(CAN_ERRSTAT_PERRF_POS) - -#define CAN_ERRSTAT_WARNF_POS 0U -#define CAN_ERRSTAT_WARNF_MSK BIT(CAN_ERRSTAT_WARNF_POS) - -/****************** Bit definition for CAN_BTIME register ************************/ - -#define CAN_BTIME_SILENT_POS 31U -#define CAN_BTIME_SILENT_MSK BIT(CAN_BTIME_SILENT_POS) - -#define CAN_BTIME_LOOP_POS 30U -#define CAN_BTIME_LOOP_MSK BIT(CAN_BTIME_LOOP_POS) - -#define CAN_BTIME_RESJW_POSS 24U -#define CAN_BTIME_RESJW_POSE 25U -#define CAN_BTIME_RESJW_MSK BITS(CAN_BTIME_RESJW_POSS,CAN_BTIME_RESJW_POSE) - -#define CAN_BTIME_SEG2_POSS 20U -#define CAN_BTIME_SEG2_POSE 22U -#define CAN_BTIME_SEG2_MSK BITS(CAN_BTIME_SEG2_POSS,CAN_BTIME_SEG2_POSE) - -#define CAN_BTIME_SEG1_POSS 16U -#define CAN_BTIME_SEG1_POSE 19U -#define CAN_BTIME_SEG1_MSK BITS(CAN_BTIME_SEG1_POSS,CAN_BTIME_SEG1_POSE) - -#define CAN_BTIME_BPSC_POSS 0U -#define CAN_BTIME_BPSC_POSE 9U -#define CAN_BTIME_BPSC_MSK BITS(CAN_BTIME_BPSC_POSS,CAN_BTIME_BPSC_POSE) - -/****************** Bit definition for CAN_TXID0 register ************************/ - -#define CAN_TXID0_STDID_POSS 21U -#define CAN_TXID0_STDID_POSE 31U -#define CAN_TXID0_STDID_MSK BITS(CAN_TXID0_STDID_POSS,CAN_TXID0_STDID_POSE) - -#define CAN_TXID0_EXID_POSS 3U -#define CAN_TXID0_EXID_POSE 20U -#define CAN_TXID0_EXID_MSK BITS(CAN_TXID0_EXID_POSS,CAN_TXID0_EXID_POSE) - -#define CAN_TXID0_IDE_POS 2U -#define CAN_TXID0_IDE_MSK BIT(CAN_TXID0_IDE_POS) - -#define CAN_TXID0_RTR_POS 1U -#define CAN_TXID0_RTR_MSK BIT(CAN_TXID0_RTR_POS) - -#define CAN_TXID0_TXMREQ_POS 0U -#define CAN_TXID0_TXMREQ_MSK BIT(CAN_TXID0_TXMREQ_POS) - -/****************** Bit definition for CAN_TXFCON0 register ************************/ - -#define CAN_TXFCON0_STAMP_POSS 16U -#define CAN_TXFCON0_STAMP_POSE 31U -#define CAN_TXFCON0_STAMP_MSK BITS(CAN_TXFCON0_STAMP_POSS,CAN_TXFCON0_STAMP_POSE) - -#define CAN_TXFCON0_TXGT_POS 8U -#define CAN_TXFCON0_TXGT_MSK BIT(CAN_TXFCON0_TXGT_POS) - -#define CAN_TXFCON0_DLEN_POSS 0U -#define CAN_TXFCON0_DLEN_POSE 3U -#define CAN_TXFCON0_DLEN_MSK BITS(CAN_TXFCON0_DLEN_POSS,CAN_TXFCON0_DLEN_POSE) - -/****************** Bit definition for CAN_TXDL0 register ************************/ - -#define CAN_TXDL0_BYTE3_POSS 24U -#define CAN_TXDL0_BYTE3_POSE 31U -#define CAN_TXDL0_BYTE3_MSK BITS(CAN_TXDL0_BYTE3_POSS,CAN_TXDL0_BYTE3_POSE) - -#define CAN_TXDL0_BYTE2_POSS 16U -#define CAN_TXDL0_BYTE2_POSE 23U -#define CAN_TXDL0_BYTE2_MSK BITS(CAN_TXDL0_BYTE2_POSS,CAN_TXDL0_BYTE2_POSE) - -#define CAN_TXDL0_BYTE1_POSS 8U -#define CAN_TXDL0_BYTE1_POSE 15U -#define CAN_TXDL0_BYTE1_MSK BITS(CAN_TXDL0_BYTE1_POSS,CAN_TXDL0_BYTE1_POSE) - -#define CAN_TXDL0_BYTE0_POSS 0U -#define CAN_TXDL0_BYTE0_POSE 7U -#define CAN_TXDL0_BYTE0_MSK BITS(CAN_TXDL0_BYTE0_POSS,CAN_TXDL0_BYTE0_POSE) - -/****************** Bit definition for CAN_TXDH0 register ************************/ - -#define CAN_TXDH0_BYTE7_POSS 24U -#define CAN_TXDH0_BYTE7_POSE 31U -#define CAN_TXDH0_BYTE7_MSK BITS(CAN_TXDH0_BYTE7_POSS,CAN_TXDH0_BYTE7_POSE) - -#define CAN_TXDH0_BYTE6_POSS 16U -#define CAN_TXDH0_BYTE6_POSE 23U -#define CAN_TXDH0_BYTE6_MSK BITS(CAN_TXDH0_BYTE6_POSS,CAN_TXDH0_BYTE6_POSE) - -#define CAN_TXDH0_BYTE5_POSS 8U -#define CAN_TXDH0_BYTE5_POSE 15U -#define CAN_TXDH0_BYTE5_MSK BITS(CAN_TXDH0_BYTE5_POSS,CAN_TXDH0_BYTE5_POSE) - -#define CAN_TXDH0_BYTE4_POSS 0U -#define CAN_TXDH0_BYTE4_POSE 7U -#define CAN_TXDH0_BYTE4_MSK BITS(CAN_TXDH0_BYTE4_POSS,CAN_TXDH0_BYTE4_POSE) - -/****************** Bit definition for CAN_TXID1 register ************************/ - -#define CAN_TXID1_STDID_POSS 21U -#define CAN_TXID1_STDID_POSE 31U -#define CAN_TXID1_STDID_MSK BITS(CAN_TXID1_STDID_POSS,CAN_TXID1_STDID_POSE) - -#define CAN_TXID1_EXID_POSS 3U -#define CAN_TXID1_EXID_POSE 20U -#define CAN_TXID1_EXID_MSK BITS(CAN_TXID1_EXID_POSS,CAN_TXID1_EXID_POSE) - -#define CAN_TXID1_IDE_POS 2U -#define CAN_TXID1_IDE_MSK BIT(CAN_TXID1_IDE_POS) - -#define CAN_TXID1_RTR_POS 1U -#define CAN_TXID1_RTR_MSK BIT(CAN_TXID1_RTR_POS) - -#define CAN_TXID1_TXMREQ_POS 0U -#define CAN_TXID1_TXMREQ_MSK BIT(CAN_TXID1_TXMREQ_POS) - -/****************** Bit definition for CAN_TXFCON1 register ************************/ - -#define CAN_TXFCON1_STAMP_POSS 16U -#define CAN_TXFCON1_STAMP_POSE 31U -#define CAN_TXFCON1_STAMP_MSK BITS(CAN_TXFCON1_STAMP_POSS,CAN_TXFCON1_STAMP_POSE) - -#define CAN_TXFCON1_TXGT_POS 8U -#define CAN_TXFCON1_TXGT_MSK BIT(CAN_TXFCON1_TXGT_POS) - -#define CAN_TXFCON1_DLEN_POSS 0U -#define CAN_TXFCON1_DLEN_POSE 3U -#define CAN_TXFCON1_DLEN_MSK BITS(CAN_TXFCON1_DLEN_POSS,CAN_TXFCON1_DLEN_POSE) - -/****************** Bit definition for CAN_TXDL1 register ************************/ - -#define CAN_TXDL1_BYTE3_POSS 24U -#define CAN_TXDL1_BYTE3_POSE 31U -#define CAN_TXDL1_BYTE3_MSK BITS(CAN_TXDL1_BYTE3_POSS,CAN_TXDL1_BYTE3_POSE) - -#define CAN_TXDL1_BYTE2_POSS 16U -#define CAN_TXDL1_BYTE2_POSE 23U -#define CAN_TXDL1_BYTE2_MSK BITS(CAN_TXDL1_BYTE2_POSS,CAN_TXDL1_BYTE2_POSE) - -#define CAN_TXDL1_BYTE1_POSS 8U -#define CAN_TXDL1_BYTE1_POSE 15U -#define CAN_TXDL1_BYTE1_MSK BITS(CAN_TXDL1_BYTE1_POSS,CAN_TXDL1_BYTE1_POSE) - -#define CAN_TXDL1_BYTE0_POSS 0U -#define CAN_TXDL1_BYTE0_POSE 7U -#define CAN_TXDL1_BYTE0_MSK BITS(CAN_TXDL1_BYTE0_POSS,CAN_TXDL1_BYTE0_POSE) - -/****************** Bit definition for CAN_TXDH1 register ************************/ - -#define CAN_TXDH1_BYTE7_POSS 24U -#define CAN_TXDH1_BYTE7_POSE 31U -#define CAN_TXDH1_BYTE7_MSK BITS(CAN_TXDH1_BYTE7_POSS,CAN_TXDH1_BYTE7_POSE) - -#define CAN_TXDH1_BYTE6_POSS 16U -#define CAN_TXDH1_BYTE6_POSE 23U -#define CAN_TXDH1_BYTE6_MSK BITS(CAN_TXDH1_BYTE6_POSS,CAN_TXDH1_BYTE6_POSE) - -#define CAN_TXDH1_BYTE5_POSS 8U -#define CAN_TXDH1_BYTE5_POSE 15U -#define CAN_TXDH1_BYTE5_MSK BITS(CAN_TXDH1_BYTE5_POSS,CAN_TXDH1_BYTE5_POSE) - -#define CAN_TXDH1_BYTE4_POSS 0U -#define CAN_TXDH1_BYTE4_POSE 7U -#define CAN_TXDH1_BYTE4_MSK BITS(CAN_TXDH1_BYTE4_POSS,CAN_TXDH1_BYTE4_POSE) - -/****************** Bit definition for CAN_TXID2 register ************************/ - -#define CAN_TXID2_STDID_POSS 21U -#define CAN_TXID2_STDID_POSE 31U -#define CAN_TXID2_STDID_MSK BITS(CAN_TXID2_STDID_POSS,CAN_TXID2_STDID_POSE) - -#define CAN_TXID2_EXID_POSS 3U -#define CAN_TXID2_EXID_POSE 20U -#define CAN_TXID2_EXID_MSK BITS(CAN_TXID2_EXID_POSS,CAN_TXID2_EXID_POSE) - -#define CAN_TXID2_IDE_POS 2U -#define CAN_TXID2_IDE_MSK BIT(CAN_TXID2_IDE_POS) - -#define CAN_TXID2_RTR_POS 1U -#define CAN_TXID2_RTR_MSK BIT(CAN_TXID2_RTR_POS) - -#define CAN_TXID2_TXMREQ_POS 0U -#define CAN_TXID2_TXMREQ_MSK BIT(CAN_TXID2_TXMREQ_POS) - -/****************** Bit definition for CAN_TXFCON2 register ************************/ - -#define CAN_TXFCON2_STAMP_POSS 16U -#define CAN_TXFCON2_STAMP_POSE 31U -#define CAN_TXFCON2_STAMP_MSK BITS(CAN_TXFCON2_STAMP_POSS,CAN_TXFCON2_STAMP_POSE) - -#define CAN_TXFCON2_TXGT_POS 8U -#define CAN_TXFCON2_TXGT_MSK BIT(CAN_TXFCON2_TXGT_POS) - -#define CAN_TXFCON2_DLEN_POSS 0U -#define CAN_TXFCON2_DLEN_POSE 3U -#define CAN_TXFCON2_DLEN_MSK BITS(CAN_TXFCON2_DLEN_POSS,CAN_TXFCON2_DLEN_POSE) - -/****************** Bit definition for CAN_TXDL2 register ************************/ - -#define CAN_TXDL2_BYTE3_POSS 24U -#define CAN_TXDL2_BYTE3_POSE 31U -#define CAN_TXDL2_BYTE3_MSK BITS(CAN_TXDL2_BYTE3_POSS,CAN_TXDL2_BYTE3_POSE) - -#define CAN_TXDL2_BYTE2_POSS 16U -#define CAN_TXDL2_BYTE2_POSE 23U -#define CAN_TXDL2_BYTE2_MSK BITS(CAN_TXDL2_BYTE2_POSS,CAN_TXDL2_BYTE2_POSE) - -#define CAN_TXDL2_BYTE1_POSS 8U -#define CAN_TXDL2_BYTE1_POSE 15U -#define CAN_TXDL2_BYTE1_MSK BITS(CAN_TXDL2_BYTE1_POSS,CAN_TXDL2_BYTE1_POSE) - -#define CAN_TXDL2_BYTE0_POSS 0U -#define CAN_TXDL2_BYTE0_POSE 7U -#define CAN_TXDL2_BYTE0_MSK BITS(CAN_TXDL2_BYTE0_POSS,CAN_TXDL2_BYTE0_POSE) - -/****************** Bit definition for CAN_TXDH2 register ************************/ - -#define CAN_TXDH2_BYTE7_POSS 24U -#define CAN_TXDH2_BYTE7_POSE 31U -#define CAN_TXDH2_BYTE7_MSK BITS(CAN_TXDH2_BYTE7_POSS,CAN_TXDH2_BYTE7_POSE) - -#define CAN_TXDH2_BYTE6_POSS 16U -#define CAN_TXDH2_BYTE6_POSE 23U -#define CAN_TXDH2_BYTE6_MSK BITS(CAN_TXDH2_BYTE6_POSS,CAN_TXDH2_BYTE6_POSE) - -#define CAN_TXDH2_BYTE5_POSS 8U -#define CAN_TXDH2_BYTE5_POSE 15U -#define CAN_TXDH2_BYTE5_MSK BITS(CAN_TXDH2_BYTE5_POSS,CAN_TXDH2_BYTE5_POSE) - -#define CAN_TXDH2_BYTE4_POSS 0U -#define CAN_TXDH2_BYTE4_POSE 7U -#define CAN_TXDH2_BYTE4_MSK BITS(CAN_TXDH2_BYTE4_POSS,CAN_TXDH2_BYTE4_POSE) - -/****************** Bit definition for CAN_RXF0ID register ************************/ - -#define CAN_RXF0ID_STDID_POSS 21U -#define CAN_RXF0ID_STDID_POSE 31U -#define CAN_RXF0ID_STDID_MSK BITS(CAN_RXF0ID_STDID_POSS,CAN_RXF0ID_STDID_POSE) - -#define CAN_RXF0ID_EXID_POSS 3U -#define CAN_RXF0ID_EXID_POSE 20U -#define CAN_RXF0ID_EXID_MSK BITS(CAN_RXF0ID_EXID_POSS,CAN_RXF0ID_EXID_POSE) - -#define CAN_RXF0ID_IDE_POS 2U -#define CAN_RXF0ID_IDE_MSK BIT(CAN_RXF0ID_IDE_POS) - -#define CAN_RXF0ID_RTR_POS 1U -#define CAN_RXF0ID_RTR_MSK BIT(CAN_RXF0ID_RTR_POS) - -/****************** Bit definition for CAN_RXF0INF register ************************/ - -#define CAN_RXF0INF_STAMP_POSS 16U -#define CAN_RXF0INF_STAMP_POSE 31U -#define CAN_RXF0INF_STAMP_MSK BITS(CAN_RXF0INF_STAMP_POSS,CAN_RXF0INF_STAMP_POSE) - -#define CAN_RXF0INF_FLTIDX_POSS 8U -#define CAN_RXF0INF_FLTIDX_POSE 15U -#define CAN_RXF0INF_FLTIDX_MSK BITS(CAN_RXF0INF_FLTIDX_POSS,CAN_RXF0INF_FLTIDX_POSE) - -#define CAN_RXF0INF_DLEN_POSS 0U -#define CAN_RXF0INF_DLEN_POSE 3U -#define CAN_RXF0INF_DLEN_MSK BITS(CAN_RXF0INF_DLEN_POSS,CAN_RXF0INF_DLEN_POSE) - -/****************** Bit definition for CAN_RXF0DL register ************************/ - -#define CAN_RXF0DL_BYTE3_POSS 24U -#define CAN_RXF0DL_BYTE3_POSE 31U -#define CAN_RXF0DL_BYTE3_MSK BITS(CAN_RXF0DL_BYTE3_POSS,CAN_RXF0DL_BYTE3_POSE) - -#define CAN_RXF0DL_BYTE2_POSS 16U -#define CAN_RXF0DL_BYTE2_POSE 23U -#define CAN_RXF0DL_BYTE2_MSK BITS(CAN_RXF0DL_BYTE2_POSS,CAN_RXF0DL_BYTE2_POSE) - -#define CAN_RXF0DL_BYTE1_POSS 8U -#define CAN_RXF0DL_BYTE1_POSE 15U -#define CAN_RXF0DL_BYTE1_MSK BITS(CAN_RXF0DL_BYTE1_POSS,CAN_RXF0DL_BYTE1_POSE) - -#define CAN_RXF0DL_BYTE0_POSS 0U -#define CAN_RXF0DL_BYTE0_POSE 7U -#define CAN_RXF0DL_BYTE0_MSK BITS(CAN_RXF0DL_BYTE0_POSS,CAN_RXF0DL_BYTE0_POSE) - -/****************** Bit definition for CAN_RXF0DH register ************************/ - -#define CAN_RXF0DH_BYTE7_POSS 24U -#define CAN_RXF0DH_BYTE7_POSE 31U -#define CAN_RXF0DH_BYTE7_MSK BITS(CAN_RXF0DH_BYTE7_POSS,CAN_RXF0DH_BYTE7_POSE) - -#define CAN_RXF0DH_BYTE6_POSS 16U -#define CAN_RXF0DH_BYTE6_POSE 23U -#define CAN_RXF0DH_BYTE6_MSK BITS(CAN_RXF0DH_BYTE6_POSS,CAN_RXF0DH_BYTE6_POSE) - -#define CAN_RXF0DH_BYTE5_POSS 8U -#define CAN_RXF0DH_BYTE5_POSE 15U -#define CAN_RXF0DH_BYTE5_MSK BITS(CAN_RXF0DH_BYTE5_POSS,CAN_RXF0DH_BYTE5_POSE) - -#define CAN_RXF0DH_BYTE4_POSS 0U -#define CAN_RXF0DH_BYTE4_POSE 7U -#define CAN_RXF0DH_BYTE4_MSK BITS(CAN_RXF0DH_BYTE4_POSS,CAN_RXF0DH_BYTE4_POSE) - -/****************** Bit definition for CAN_RXF1ID register ************************/ - -#define CAN_RXF1ID_STDID_POSS 21U -#define CAN_RXF1ID_STDID_POSE 31U -#define CAN_RXF1ID_STDID_MSK BITS(CAN_RXF1ID_STDID_POSS,CAN_RXF1ID_STDID_POSE) - -#define CAN_RXF1ID_EXID_POSS 3U -#define CAN_RXF1ID_EXID_POSE 20U -#define CAN_RXF1ID_EXID_MSK BITS(CAN_RXF1ID_EXID_POSS,CAN_RXF1ID_EXID_POSE) - -#define CAN_RXF1ID_IDE_POS 2U -#define CAN_RXF1ID_IDE_MSK BIT(CAN_RXF1ID_IDE_POS) - -#define CAN_RXF1ID_RTR_POS 1U -#define CAN_RXF1ID_RTR_MSK BIT(CAN_RXF1ID_RTR_POS) - -/****************** Bit definition for CAN_RXF1INF register ************************/ - -#define CAN_RXF1INF_STAMP_POSS 16U -#define CAN_RXF1INF_STAMP_POSE 31U -#define CAN_RXF1INF_STAMP_MSK BITS(CAN_RXF1INF_STAMP_POSS,CAN_RXF1INF_STAMP_POSE) - -#define CAN_RXF1INF_FLTIDX_POSS 8U -#define CAN_RXF1INF_FLTIDX_POSE 15U -#define CAN_RXF1INF_FLTIDX_MSK BITS(CAN_RXF1INF_FLTIDX_POSS,CAN_RXF1INF_FLTIDX_POSE) - -#define CAN_RXF1INF_DLEN_POSS 0U -#define CAN_RXF1INF_DLEN_POSE 3U -#define CAN_RXF1INF_DLEN_MSK BITS(CAN_RXF1INF_DLEN_POSS,CAN_RXF1INF_DLEN_POSE) - -/****************** Bit definition for CAN_RXF1DL register ************************/ - -#define CAN_RXF1DL_BYTE3_POSS 24U -#define CAN_RXF1DL_BYTE3_POSE 31U -#define CAN_RXF1DL_BYTE3_MSK BITS(CAN_RXF1DL_BYTE3_POSS,CAN_RXF1DL_BYTE3_POSE) - -#define CAN_RXF1DL_BYTE2_POSS 16U -#define CAN_RXF1DL_BYTE2_POSE 23U -#define CAN_RXF1DL_BYTE2_MSK BITS(CAN_RXF1DL_BYTE2_POSS,CAN_RXF1DL_BYTE2_POSE) - -#define CAN_RXF1DL_BYTE1_POSS 8U -#define CAN_RXF1DL_BYTE1_POSE 15U -#define CAN_RXF1DL_BYTE1_MSK BITS(CAN_RXF1DL_BYTE1_POSS,CAN_RXF1DL_BYTE1_POSE) - -#define CAN_RXF1DL_BYTE0_POSS 0U -#define CAN_RXF1DL_BYTE0_POSE 7U -#define CAN_RXF1DL_BYTE0_MSK BITS(CAN_RXF1DL_BYTE0_POSS,CAN_RXF1DL_BYTE0_POSE) - -/****************** Bit definition for CAN_RXF1DH register ************************/ - -#define CAN_RXF1DH_BYTE7_POSS 24U -#define CAN_RXF1DH_BYTE7_POSE 31U -#define CAN_RXF1DH_BYTE7_MSK BITS(CAN_RXF1DH_BYTE7_POSS,CAN_RXF1DH_BYTE7_POSE) - -#define CAN_RXF1DH_BYTE6_POSS 16U -#define CAN_RXF1DH_BYTE6_POSE 23U -#define CAN_RXF1DH_BYTE6_MSK BITS(CAN_RXF1DH_BYTE6_POSS,CAN_RXF1DH_BYTE6_POSE) - -#define CAN_RXF1DH_BYTE5_POSS 8U -#define CAN_RXF1DH_BYTE5_POSE 15U -#define CAN_RXF1DH_BYTE5_MSK BITS(CAN_RXF1DH_BYTE5_POSS,CAN_RXF1DH_BYTE5_POSE) - -#define CAN_RXF1DH_BYTE4_POSS 0U -#define CAN_RXF1DH_BYTE4_POSE 7U -#define CAN_RXF1DH_BYTE4_MSK BITS(CAN_RXF1DH_BYTE4_POSS,CAN_RXF1DH_BYTE4_POSE) - -/****************** Bit definition for CAN_FLTCON register ************************/ - -#define CAN_FLTCON_FLTINI_POS 0U -#define CAN_FLTCON_FLTINI_MSK BIT(CAN_FLTCON_FLTINI_POS) - -/****************** Bit definition for CAN_FLTM register ************************/ - -#define CAN_FLTM_MOD_POSS 0U -#define CAN_FLTM_MOD_POSE 13U -#define CAN_FLTM_MOD_MSK BITS(CAN_FLTM_MOD_POSS,CAN_FLTM_MOD_POSE) - -/****************** Bit definition for CAN_FLTWS register ************************/ - -#define CAN_FLTWS_SEL_POSS 0U -#define CAN_FLTWS_SEL_POSE 13U -#define CAN_FLTWS_SEL_MSK BITS(CAN_FLTWS_SEL_POSS,CAN_FLTWS_SEL_POSE) - -/****************** Bit definition for CAN_FLTAS register ************************/ - -#define CAN_FLTAS_ASSIGN_POSS 0U -#define CAN_FLTAS_ASSIGN_POSE 13U -#define CAN_FLTAS_ASSIGN_MSK BITS(CAN_FLTAS_ASSIGN_POSS,CAN_FLTAS_ASSIGN_POSE) - -/****************** Bit definition for CAN_FLTGO register ************************/ - -#define CAN_FLTGO_GO_POSS 0U -#define CAN_FLTGO_GO_POSE 13U -#define CAN_FLTGO_GO_MSK BITS(CAN_FLTGO_GO_POSS,CAN_FLTGO_GO_POSE) - -typedef struct { - __IO uint32_t TXID; - __IO uint32_t TXFCON; - __IO uint32_t TXDL; - __IO uint32_t TXDH; -} CAN_TxMailBox_Typedef; - -typedef struct { - __IO uint32_t RXFID; - __IO uint32_t RXFINF; - __IO uint32_t RXFDL; - __IO uint32_t RXFDH; -} CAN_RxFIFO_Typedef; - -typedef struct { - __IO uint32_t FLT1; - __IO uint32_t FLT2; -} CAN_Filter_Typedef; - -typedef struct -{ - __IO uint32_t CON; - __I uint32_t STAT; - __O uint32_t IFC; - __IO uint32_t TXSTAT; - __O uint32_t TXSTATC; - __IO uint32_t RXF0; - __O uint32_t RXF0C; - __IO uint32_t RXF1; - __O uint32_t RXF1C; - __IO uint32_t IE; - __IO uint32_t ERRSTAT; - __IO uint32_t BTIME; - uint32_t RESERVED0[84] ; - CAN_TxMailBox_Typedef TxMailBox[3]; - CAN_RxFIFO_Typedef RxFIFO[2]; - uint32_t RESERVED1[12] ; - __IO uint32_t FLTCON; - __IO uint32_t FLTM; - uint32_t RESERVED2 ; - __IO uint32_t FLTWS; - uint32_t RESERVED3 ; - __IO uint32_t FLTAS; - uint32_t RESERVED4 ; - __IO uint32_t FLTGO; - uint32_t RESERVED5[8] ; - CAN_Filter_Typedef Filter[14]; -} CAN_TypeDef; - -/****************** Bit definition for CRC_CR register ************************/ -#define CRC_CR_BYTORD_POS 24U -#define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS) - -#define CRC_CR_DATLEN_POSS 22U -#define CRC_CR_DATLEN_POSE 23U -#define CRC_CR_DATLEN_MSK BITS(CRC_CR_DATLEN_POSS,CRC_CR_DATLEN_POSE) - -#define CRC_CR_MODE_POSS 20U -#define CRC_CR_MODE_POSE 21U -#define CRC_CR_MODE_MSK BITS(CRC_CR_MODE_POSS,CRC_CR_MODE_POSE) - -#define CRC_CR_CHSINV_POS 19U -#define CRC_CR_CHSINV_MSK BIT(CRC_CR_CHSINV_POS) - -#define CRC_CR_DATINV_POS 18U -#define CRC_CR_DATINV_MSK BIT(CRC_CR_DATINV_POS) - -#define CRC_CR_CHSREV_POS 17U -#define CRC_CR_CHSREV_MSK BIT(CRC_CR_CHSREV_POS) - -#define CRC_CR_DATREV_POS 16U -#define CRC_CR_DATREV_MSK BIT(CRC_CR_DATREV_POS) - -#define CRC_CR_DMAEN_POS 4U -#define CRC_CR_DMAEN_MSK BIT(CRC_CR_DMAEN_POS) - -#define CRC_CR_CWERR_POS 3U -#define CRC_CR_CWERR_MSK BIT(CRC_CR_CWERR_POS) - -#define CRC_CR_WERR_POS 2U -#define CRC_CR_WERR_MSK BIT(CRC_CR_WERR_POS) - -#define CRC_CR_RST_POS 1U -#define CRC_CR_RST_MSK BIT(CRC_CR_RST_POS) - -#define CRC_CR_EN_POS 0U -#define CRC_CR_EN_MSK BIT(CRC_CR_EN_POS) - -/****************** Bit definition for CRC_DATA register ************************/ - -#define CRC_DATA_DATA_POSS 0U -#define CRC_DATA_DATA_POSE 31U -#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) - -/****************** Bit definition for CRC_SEED register ************************/ - -#define CRC_SEED_SEED_POSS 0U -#define CRC_SEED_SEED_POSE 31U -#define CRC_SEED_SEED_MSK BITS(CRC_SEED_SEED_POSS,CRC_SEED_SEED_POSE) - -/****************** Bit definition for CRC_CHECKSUM register ************************/ - -#define CRC_CHECKSUM_CHECKSUM_POSS 0U -#define CRC_CHECKSUM_CHECKSUM_POSE 31U -#define CRC_CHECKSUM_CHECKSUM_MSK BITS(CRC_CHECKSUM_CHECKSUM_POSS,CRC_CHECKSUM_CHECKSUM_POSE) - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t DATA; - __IO uint32_t SEED; - __I uint32_t CHECKSUM; -} CRC_TypeDef; - -/****************** Bit definition for CRYPT_CON register ************************/ - -#define CRYPT_CON_CRYSEL_POS 31U -#define CRYPT_CON_CRYSEL_MSK BIT(CRYPT_CON_CRYSEL_POS) - -#define CRYPT_CON_RESCLR_POS 15U -#define CRYPT_CON_RESCLR_MSK BIT(CRYPT_CON_RESCLR_POS) - -#define CRYPT_CON_DMAEN_POS 14U -#define CRYPT_CON_DMAEN_MSK BIT(CRYPT_CON_DMAEN_POS) - -#define CRYPT_CON_FIFOODR_POS 13U -#define CRYPT_CON_FIFOODR_MSK BIT(CRYPT_CON_FIFOODR_POS) - -#define CRYPT_CON_FIFOEN_POS 12U -#define CRYPT_CON_FIFOEN_MSK BIT(CRYPT_CON_FIFOEN_POS) - -#define CRYPT_CON_DESKS_POS 11U -#define CRYPT_CON_DESKS_MSK BIT(CRYPT_CON_DESKS_POS) - -#define CRYPT_CON_TDES_POS 10U -#define CRYPT_CON_TDES_MSK BIT(CRYPT_CON_TDES_POS) - -#define CRYPT_CON_TYPE_POSS 8U -#define CRYPT_CON_TYPE_POSE 9U -#define CRYPT_CON_TYPE_MSK BITS(CRYPT_CON_TYPE_POSS,CRYPT_CON_TYPE_POSE) - -#define CRYPT_CON_IE_POS 7U -#define CRYPT_CON_IE_MSK BIT(CRYPT_CON_IE_POS) - -#define CRYPT_CON_IVEN_POS 6U -#define CRYPT_CON_IVEN_MSK BIT(CRYPT_CON_IVEN_POS) - -#define CRYPT_CON_MODE_POSS 4U -#define CRYPT_CON_MODE_POSE 5U -#define CRYPT_CON_MODE_MSK BITS(CRYPT_CON_MODE_POSS,CRYPT_CON_MODE_POSE) - -#define CRYPT_CON_AESKS_POSS 2U -#define CRYPT_CON_AESKS_POSE 3U -#define CRYPT_CON_AESKS_MSK BITS(CRYPT_CON_AESKS_POSS,CRYPT_CON_AESKS_POSE) - -#define CRYPT_CON_ENCS_POS 1U -#define CRYPT_CON_ENCS_MSK BIT(CRYPT_CON_ENCS_POS) - -#define CRYPT_CON_GO_POS 0U -#define CRYPT_CON_GO_MSK BIT(CRYPT_CON_GO_POS) - -/****************** Bit definition for CRYPT_IF register ************************/ - -#define CRYPT_IF_DONE_POS 8U -#define CRYPT_IF_DONE_MSK BIT(CRYPT_IF_DONE_POS) - -#define CRYPT_IF_MULTHIF_POS 2U -#define CRYPT_IF_MULTHIF_MSK BIT(CRYPT_IF_MULTHIF_POS) - -#define CRYPT_IF_DESIF_POS 1U -#define CRYPT_IF_DESIF_MSK BIT(CRYPT_IF_DESIF_POS) - -#define CRYPT_IF_AESIF_POS 0U -#define CRYPT_IF_AESIF_MSK BIT(CRYPT_IF_AESIF_POS) - -/****************** Bit definition for CRYPT_IFC register ************************/ - -#define CRYPT_IFC_MULTHIFC_POS 2U -#define CRYPT_IFC_MULTHIFC_MSK BIT(CRYPT_IFC_MULTHIFC_POS) - -#define CRYPT_IFC_DESIFC_POS 1U -#define CRYPT_IFC_DESIFC_MSK BIT(CRYPT_IFC_DESIFC_POS) - -#define CRYPT_IFC_AESIFC_POS 0U -#define CRYPT_IFC_AESIFC_MSK BIT(CRYPT_IFC_AESIFC_POS) - -/****************** Bit definition for CRYPT_FIFO register ************************/ - -#define CRYPT_FIFO_FIFO_POSS 0U -#define CRYPT_FIFO_FIFO_POSE 31U -#define CRYPT_FIFO_FIFO_MSK BITS(CRYPT_FIFO_FIFO_POSS,CRYPT_FIFO_FIFO_POSE) - -typedef struct -{ - __IO uint32_t DATA[4]; - __IO uint32_t KEY[8]; - __IO uint32_t IV[4]; - __I uint32_t RES[4]; - __IO uint32_t CON; - __I uint32_t IF; - __O uint32_t IFC; - __IO uint32_t FIFO; -} CRYPT_TypeDef; - -/****************** Bit definition for LCD_CR register ************************/ - -#define LCD_CR_VCHPS_POSS 24U -#define LCD_CR_VCHPS_POSE 25U -#define LCD_CR_VCHPS_MSK BITS(LCD_CR_VCHPS_POSS,LCD_CR_VCHPS_POSE) - -#define LCD_CR_DSLD_POSS 20U -#define LCD_CR_DSLD_POSE 23U -#define LCD_CR_DSLD_MSK BITS(LCD_CR_DSLD_POSS,LCD_CR_DSLD_POSE) - -#define LCD_CR_DSHD_POSS 16U -#define LCD_CR_DSHD_POSE 19U -#define LCD_CR_DSHD_MSK BITS(LCD_CR_DSHD_POSS,LCD_CR_DSHD_POSE) - -#define LCD_CR_VBUFLD_POS 15U -#define LCD_CR_VBUFLD_MSK BIT(LCD_CR_VBUFLD_POS) - -#define LCD_CR_VBUFHD_POS 14U -#define LCD_CR_VBUFHD_MSK BIT(LCD_CR_VBUFHD_POS) - -#define LCD_CR_RESLD_POSS 12U -#define LCD_CR_RESLD_POSE 13U -#define LCD_CR_RESLD_MSK BITS(LCD_CR_RESLD_POSS,LCD_CR_RESLD_POSE) - -#define LCD_CR_RESHD_POSS 10U -#define LCD_CR_RESHD_POSE 11U -#define LCD_CR_RESHD_MSK BITS(LCD_CR_RESHD_POSS,LCD_CR_RESHD_POSE) - -#define LCD_CR_BIAS_POSS 8U -#define LCD_CR_BIAS_POSE 9U -#define LCD_CR_BIAS_MSK BITS(LCD_CR_BIAS_POSS,LCD_CR_BIAS_POSE) - -#define LCD_CR_DUTY_POSS 4U -#define LCD_CR_DUTY_POSE 6U -#define LCD_CR_DUTY_MSK BITS(LCD_CR_DUTY_POSS,LCD_CR_DUTY_POSE) - -#define LCD_CR_OE_POS 3U -#define LCD_CR_OE_MSK BIT(LCD_CR_OE_POS) - -#define LCD_CR_VSEL_POSS 1U -#define LCD_CR_VSEL_POSE 2U -#define LCD_CR_VSEL_MSK BITS(LCD_CR_VSEL_POSS,LCD_CR_VSEL_POSE) - -#define LCD_CR_EN_POS 0U -#define LCD_CR_EN_MSK BIT(LCD_CR_EN_POS) - -/****************** Bit definition for LCD_FCR register ************************/ - -#define LCD_FCR_WFS_POS 31U -#define LCD_FCR_WFS_MSK BIT(LCD_FCR_WFS_POS) - -#define LCD_FCR_PRS_POSS 24U -#define LCD_FCR_PRS_POSE 27U -#define LCD_FCR_PRS_MSK BITS(LCD_FCR_PRS_POSS,LCD_FCR_PRS_POSE) - -#define LCD_FCR_DIV_POSS 20U -#define LCD_FCR_DIV_POSE 23U -#define LCD_FCR_DIV_MSK BITS(LCD_FCR_DIV_POSS,LCD_FCR_DIV_POSE) - -#define LCD_FCR_BLMOD_POSS 16U -#define LCD_FCR_BLMOD_POSE 17U -#define LCD_FCR_BLMOD_MSK BITS(LCD_FCR_BLMOD_POSS,LCD_FCR_BLMOD_POSE) - -#define LCD_FCR_BLFRQ_POSS 12U -#define LCD_FCR_BLFRQ_POSE 14U -#define LCD_FCR_BLFRQ_MSK BITS(LCD_FCR_BLFRQ_POSS,LCD_FCR_BLFRQ_POSE) - -#define LCD_FCR_DEAD_POSS 8U -#define LCD_FCR_DEAD_POSE 10U -#define LCD_FCR_DEAD_MSK BITS(LCD_FCR_DEAD_POSS,LCD_FCR_DEAD_POSE) - -#define LCD_FCR_HD_POS 7U -#define LCD_FCR_HD_MSK BIT(LCD_FCR_HD_POS) - -#define LCD_FCR_PON_POSS 4U -#define LCD_FCR_PON_POSE 6U -#define LCD_FCR_PON_MSK BITS(LCD_FCR_PON_POSS,LCD_FCR_PON_POSE) - -#define LCD_FCR_VGS_POSS 0U -#define LCD_FCR_VGS_POSE 3U -#define LCD_FCR_VGS_MSK BITS(LCD_FCR_VGS_POSS,LCD_FCR_VGS_POSE) - -/****************** Bit definition for LCD_SEGCR0 register ************************/ - -#define LCD_SEGCR0_SEG_OE_POSS 0U -#define LCD_SEGCR0_SEG_OE_POSE 31U -#define LCD_SEGCR0_SEG_OE_MSK BITS(LCD_SEGCR0_SEG_OE_POSS,LCD_SEGCR0_SEG_OE_POSE) - -/****************** Bit definition for LCD_SEGCR1 register ************************/ - -#define LCD_SEGCR1_SEG_OE_POSS 0U -#define LCD_SEGCR1_SEG_OE_POSE 11U -#define LCD_SEGCR1_SEG_OE_MSK BITS(LCD_SEGCR1_SEG_OE_POSS,LCD_SEGCR1_SEG_OE_POSE) - -/****************** Bit definition for LCD_IE register ************************/ - -#define LCD_IE_UDDIE_POS 1U -#define LCD_IE_UDDIE_MSK BIT(LCD_IE_UDDIE_POS) - -#define LCD_IE_SOFIE_POS 0U -#define LCD_IE_SOFIE_MSK BIT(LCD_IE_SOFIE_POS) - -/****************** Bit definition for LCD_IF register ************************/ - -#define LCD_IF_UDDIF_POS 1U -#define LCD_IF_UDDIF_MSK BIT(LCD_IF_UDDIF_POS) - -#define LCD_IF_SOFIF_POS 0U -#define LCD_IF_SOFIF_MSK BIT(LCD_IF_SOFIF_POS) - -/****************** Bit definition for LCD_IFCR register ************************/ - -#define LCD_IFCR_UDDIFC_POS 1U -#define LCD_IFCR_UDDIFC_MSK BIT(LCD_IFCR_UDDIFC_POS) - -#define LCD_IFCR_SOFIFC_POS 0U -#define LCD_IFCR_SOFIFC_MSK BIT(LCD_IFCR_SOFIFC_POS) - -/****************** Bit definition for LCD_SR register ************************/ - -#define LCD_SR_FCRSF_POS 3U -#define LCD_SR_FCRSF_MSK BIT(LCD_SR_FCRSF_POS) - -#define LCD_SR_UDR_POS 2U -#define LCD_SR_UDR_MSK BIT(LCD_SR_UDR_POS) - -#define LCD_SR_ENS_POS 1U -#define LCD_SR_ENS_MSK BIT(LCD_SR_ENS_POS) - -#define LCD_SR_RDY_POS 0U -#define LCD_SR_RDY_MSK BIT(LCD_SR_RDY_POS) - -/****************** Bit definition for LCD_BUF register ************************/ - -#define LCD_BUF_SEG_DATA_POSS 0U -#define LCD_BUF_SEG_DATA_POSE 31U -#define LCD_BUF_SEG_DATA_MSK BITS(LCD_BUF_SEG_DATA_POSS,LCD_BUF_SEG_DATA_POSE) - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t FCR; - __IO uint32_t SEGCR0; - __IO uint32_t SEGCR1; - __IO uint32_t IE; - __I uint32_t IF; - __O uint32_t IFCR; - __I uint32_t SR; - uint32_t RESERVED0[8] ; - __IO uint32_t BUF[16]; -} LCD_TypeDef; - -/****************** Bit definition for ADC_STAT register ************************/ - -#define ADC_STAT_ICHS_POS 9U -#define ADC_STAT_ICHS_MSK BIT(ADC_STAT_ICHS_POS) - -#define ADC_STAT_NCHS_POS 8U -#define ADC_STAT_NCHS_MSK BIT(ADC_STAT_NCHS_POS) - -#define ADC_STAT_OVR_POS 3U -#define ADC_STAT_OVR_MSK BIT(ADC_STAT_OVR_POS) - -#define ADC_STAT_ICHE_POS 2U -#define ADC_STAT_ICHE_MSK BIT(ADC_STAT_ICHE_POS) - -#define ADC_STAT_NCHE_POS 1U -#define ADC_STAT_NCHE_MSK BIT(ADC_STAT_NCHE_POS) - -#define ADC_STAT_AWDF_POS 0U -#define ADC_STAT_AWDF_MSK BIT(ADC_STAT_AWDF_POS) - -/****************** Bit definition for ADC_CLR register ************************/ - -#define ADC_CLR_ICHS_POS 9U -#define ADC_CLR_ICHS_MSK BIT(ADC_CLR_ICHS_POS) - -#define ADC_CLR_NCHS_POS 8U -#define ADC_CLR_NCHS_MSK BIT(ADC_CLR_NCHS_POS) - -#define ADC_CLR_OVR_POS 3U -#define ADC_CLR_OVR_MSK BIT(ADC_CLR_OVR_POS) - -#define ADC_CLR_ICHE_POS 2U -#define ADC_CLR_ICHE_MSK BIT(ADC_CLR_ICHE_POS) - -#define ADC_CLR_NCHE_POS 1U -#define ADC_CLR_NCHE_MSK BIT(ADC_CLR_NCHE_POS) - -#define ADC_CLR_AWDF_POS 0U -#define ADC_CLR_AWDF_MSK BIT(ADC_CLR_AWDF_POS) - -/****************** Bit definition for ADC_CON0 register ************************/ - -#define ADC_CON0_OVRIE_POS 26U -#define ADC_CON0_OVRIE_MSK BIT(ADC_CON0_OVRIE_POS) - -#define ADC_CON0_RSEL_POSS 24U -#define ADC_CON0_RSEL_POSE 25U -#define ADC_CON0_RSEL_MSK BITS(ADC_CON0_RSEL_POSS,ADC_CON0_RSEL_POSE) - -#define ADC_CON0_NCHWDEN_POS 23U -#define ADC_CON0_NCHWDEN_MSK BIT(ADC_CON0_NCHWDEN_POS) - -#define ADC_CON0_ICHWDTEN_POS 22U -#define ADC_CON0_ICHWDTEN_MSK BIT(ADC_CON0_ICHWDTEN_POS) - -#define ADC_CON0_ETRGN_POSS 13U -#define ADC_CON0_ETRGN_POSE 15U -#define ADC_CON0_ETRGN_MSK BITS(ADC_CON0_ETRGN_POSS,ADC_CON0_ETRGN_POSE) - -#define ADC_CON0_ICHDCEN_POS 12U -#define ADC_CON0_ICHDCEN_MSK BIT(ADC_CON0_ICHDCEN_POS) - -#define ADC_CON0_NCHDCEN_POS 11U -#define ADC_CON0_NCHDCEN_MSK BIT(ADC_CON0_NCHDCEN_POS) - -#define ADC_CON0_IAUTO_POS 10U -#define ADC_CON0_IAUTO_MSK BIT(ADC_CON0_IAUTO_POS) - -#define ADC_CON0_AWDSGL_POS 9U -#define ADC_CON0_AWDSGL_MSK BIT(ADC_CON0_AWDSGL_POS) - -#define ADC_CON0_SCANEN_POS 8U -#define ADC_CON0_SCANEN_MSK BIT(ADC_CON0_SCANEN_POS) - -#define ADC_CON0_ICHEIE_POS 7U -#define ADC_CON0_ICHEIE_MSK BIT(ADC_CON0_ICHEIE_POS) - -#define ADC_CON0_AWDIE_POS 6U -#define ADC_CON0_AWDIE_MSK BIT(ADC_CON0_AWDIE_POS) - -#define ADC_CON0_NCHEIE_POS 5U -#define ADC_CON0_NCHEIE_MSK BIT(ADC_CON0_NCHEIE_POS) - -#define ADC_CON0_AWDCH_POSS 0U -#define ADC_CON0_AWDCH_POSE 4U -#define ADC_CON0_AWDCH_MSK BITS(ADC_CON0_AWDCH_POSS,ADC_CON0_AWDCH_POSE) - -/****************** Bit definition for ADC_CON1 register ************************/ - -#define ADC_CON1_NCHTRG_POS 30U -#define ADC_CON1_NCHTRG_MSK BIT(ADC_CON1_NCHTRG_POS) - -#define ADC_CON1_ICHTRG_POS 22U -#define ADC_CON1_ICHTRG_MSK BIT(ADC_CON1_ICHTRG_POS) - -#define ADC_CON1_ALIGN_POS 11U -#define ADC_CON1_ALIGN_MSK BIT(ADC_CON1_ALIGN_POS) - -#define ADC_CON1_NCHESEL_POS 10U -#define ADC_CON1_NCHESEL_MSK BIT(ADC_CON1_NCHESEL_POS) - -#define ADC_CON1_OVRDIS_POS 8U -#define ADC_CON1_OVRDIS_MSK BIT(ADC_CON1_OVRDIS_POS) - -#define ADC_CON1_CM_POS 1U -#define ADC_CON1_CM_MSK BIT(ADC_CON1_CM_POS) - -#define ADC_CON1_ADCEN_POS 0U -#define ADC_CON1_ADCEN_MSK BIT(ADC_CON1_ADCEN_POS) - -/****************** Bit definition for ADC_SMPT1 register ************************/ - -#define ADC_SMPT1_CHT_POSS 0U -#define ADC_SMPT1_CHT_POSE 31U -#define ADC_SMPT1_CHT_MSK BITS(ADC_SMPT1_CHT_POSS,ADC_SMPT1_CHT_POSE) - -/****************** Bit definition for ADC_SMPT2 register ************************/ - -#define ADC_SMPT2_CHT_POSS 0U -#define ADC_SMPT2_CHT_POSE 7U -#define ADC_SMPT2_CHT_MSK BITS(ADC_SMPT2_CHT_POSS,ADC_SMPT2_CHT_POSE) - -/****************** Bit definition for ADC_ICHOFF1 register ************************/ - -#define ADC_ICHOFF1_IOFF_POSS 0U -#define ADC_ICHOFF1_IOFF_POSE 11U -#define ADC_ICHOFF1_IOFF_MSK BITS(ADC_ICHOFF1_IOFF_POSS,ADC_ICHOFF1_IOFF_POSE) - -/****************** Bit definition for ADC_ICHOFF2 register ************************/ - -#define ADC_ICHOFF2_IOFF_POSS 0U -#define ADC_ICHOFF2_IOFF_POSE 11U -#define ADC_ICHOFF2_IOFF_MSK BITS(ADC_ICHOFF2_IOFF_POSS,ADC_ICHOFF2_IOFF_POSE) - -/****************** Bit definition for ADC_ICHOFF3 register ************************/ - -#define ADC_ICHOFF3_IOFF_POSS 0U -#define ADC_ICHOFF3_IOFF_POSE 11U -#define ADC_ICHOFF3_IOFF_MSK BITS(ADC_ICHOFF3_IOFF_POSS,ADC_ICHOFF3_IOFF_POSE) - -/****************** Bit definition for ADC_ICHOFF4 register ************************/ - -#define ADC_ICHOFF4_IOFF_POSS 0U -#define ADC_ICHOFF4_IOFF_POSE 11U -#define ADC_ICHOFF4_IOFF_MSK BITS(ADC_ICHOFF4_IOFF_POSS,ADC_ICHOFF4_IOFF_POSE) - -/****************** Bit definition for ADC_WDTH register ************************/ - -#define ADC_WDTH_HT_POSS 0U -#define ADC_WDTH_HT_POSE 11U -#define ADC_WDTH_HT_MSK BITS(ADC_WDTH_HT_POSS,ADC_WDTH_HT_POSE) - -/****************** Bit definition for ADC_WDTL register ************************/ - -#define ADC_WDTL_LT_POSS 0U -#define ADC_WDTL_LT_POSE 11U -#define ADC_WDTL_LT_MSK BITS(ADC_WDTL_LT_POSS,ADC_WDTL_LT_POSE) - -/****************** Bit definition for ADC_NCHS1 register ************************/ - -#define ADC_NCHS1_NS4_POSS 24U -#define ADC_NCHS1_NS4_POSE 28U -#define ADC_NCHS1_NS4_MSK BITS(ADC_NCHS1_NS4_POSS,ADC_NCHS1_NS4_POSE) - -#define ADC_NCHS1_NS3_POSS 16U -#define ADC_NCHS1_NS3_POSE 20U -#define ADC_NCHS1_NS3_MSK BITS(ADC_NCHS1_NS3_POSS,ADC_NCHS1_NS3_POSE) - -#define ADC_NCHS1_NS2_POSS 8U -#define ADC_NCHS1_NS2_POSE 12U -#define ADC_NCHS1_NS2_MSK BITS(ADC_NCHS1_NS2_POSS,ADC_NCHS1_NS2_POSE) - -#define ADC_NCHS1_NS1_POSS 0U -#define ADC_NCHS1_NS1_POSE 4U -#define ADC_NCHS1_NS1_MSK BITS(ADC_NCHS1_NS1_POSS,ADC_NCHS1_NS1_POSE) - -/****************** Bit definition for ADC_NCHS2 register ************************/ - -#define ADC_NCHS2_NS8_POSS 24U -#define ADC_NCHS2_NS8_POSE 28U -#define ADC_NCHS2_NS8_MSK BITS(ADC_NCHS2_NS8_POSS,ADC_NCHS2_NS8_POSE) - -#define ADC_NCHS2_NS7_POSS 16U -#define ADC_NCHS2_NS7_POSE 20U -#define ADC_NCHS2_NS7_MSK BITS(ADC_NCHS2_NS7_POSS,ADC_NCHS2_NS7_POSE) - -#define ADC_NCHS2_NS6_POSS 8U -#define ADC_NCHS2_NS6_POSE 12U -#define ADC_NCHS2_NS6_MSK BITS(ADC_NCHS2_NS6_POSS,ADC_NCHS2_NS6_POSE) - -#define ADC_NCHS2_NS5_POSS 0U -#define ADC_NCHS2_NS5_POSE 4U -#define ADC_NCHS2_NS5_MSK BITS(ADC_NCHS2_NS5_POSS,ADC_NCHS2_NS5_POSE) - -/****************** Bit definition for ADC_NCHS3 register ************************/ - -#define ADC_NCHS3_NS12_POSS 24U -#define ADC_NCHS3_NS12_POSE 28U -#define ADC_NCHS3_NS12_MSK BITS(ADC_NCHS3_NS12_POSS,ADC_NCHS3_NS12_POSE) - -#define ADC_NCHS3_NS11_POSS 16U -#define ADC_NCHS3_NS11_POSE 20U -#define ADC_NCHS3_NS11_MSK BITS(ADC_NCHS3_NS11_POSS,ADC_NCHS3_NS11_POSE) - -#define ADC_NCHS3_NS10_POSS 8U -#define ADC_NCHS3_NS10_POSE 12U -#define ADC_NCHS3_NS10_MSK BITS(ADC_NCHS3_NS10_POSS,ADC_NCHS3_NS10_POSE) - -#define ADC_NCHS3_NS9_POSS 0U -#define ADC_NCHS3_NS9_POSE 4U -#define ADC_NCHS3_NS9_MSK BITS(ADC_NCHS3_NS9_POSS,ADC_NCHS3_NS9_POSE) - -/****************** Bit definition for ADC_NCHS4 register ************************/ - -#define ADC_NCHS4_NS16_POSS 24U -#define ADC_NCHS4_NS16_POSE 28U -#define ADC_NCHS4_NS16_MSK BITS(ADC_NCHS4_NS16_POSS,ADC_NCHS4_NS16_POSE) - -#define ADC_NCHS4_NS15_POSS 16U -#define ADC_NCHS4_NS15_POSE 20U -#define ADC_NCHS4_NS15_MSK BITS(ADC_NCHS4_NS15_POSS,ADC_NCHS4_NS15_POSE) - -#define ADC_NCHS4_NS14_POSS 8U -#define ADC_NCHS4_NS14_POSE 12U -#define ADC_NCHS4_NS14_MSK BITS(ADC_NCHS4_NS14_POSS,ADC_NCHS4_NS14_POSE) - -#define ADC_NCHS4_NS13_POSS 0U -#define ADC_NCHS4_NS13_POSE 4U -#define ADC_NCHS4_NS13_MSK BITS(ADC_NCHS4_NS13_POSS,ADC_NCHS4_NS13_POSE) - -/****************** Bit definition for ADC_ICHS register ************************/ - -#define ADC_ICHS_IS4_POSS 24U -#define ADC_ICHS_IS4_POSE 28U -#define ADC_ICHS_IS4_MSK BITS(ADC_ICHS_IS4_POSS,ADC_ICHS_IS4_POSE) - -#define ADC_ICHS_IS3_POSS 16U -#define ADC_ICHS_IS3_POSE 20U -#define ADC_ICHS_IS3_MSK BITS(ADC_ICHS_IS3_POSS,ADC_ICHS_IS3_POSE) - -#define ADC_ICHS_IS2_POSS 8U -#define ADC_ICHS_IS2_POSE 12U -#define ADC_ICHS_IS2_MSK BITS(ADC_ICHS_IS2_POSS,ADC_ICHS_IS2_POSE) - -#define ADC_ICHS_IS1_POSS 0U -#define ADC_ICHS_IS1_POSE 4U -#define ADC_ICHS_IS1_MSK BITS(ADC_ICHS_IS1_POSS,ADC_ICHS_IS1_POSE) - -/****************** Bit definition for ADC_CHSL register ************************/ - -#define ADC_CHSL_ISL_POSS 8U -#define ADC_CHSL_ISL_POSE 9U -#define ADC_CHSL_ISL_MSK BITS(ADC_CHSL_ISL_POSS,ADC_CHSL_ISL_POSE) - -#define ADC_CHSL_NSL_POSS 0U -#define ADC_CHSL_NSL_POSE 3U -#define ADC_CHSL_NSL_MSK BITS(ADC_CHSL_NSL_POSS,ADC_CHSL_NSL_POSE) - -/****************** Bit definition for ADC_ICHDR1 register ************************/ - -#define ADC_ICHDR1_VAL_POSS 0U -#define ADC_ICHDR1_VAL_POSE 15U -#define ADC_ICHDR1_VAL_MSK BITS(ADC_ICHDR1_VAL_POSS,ADC_ICHDR1_VAL_POSE) - -/****************** Bit definition for ADC_ICHDR2 register ************************/ - -#define ADC_ICHDR2_VAL_POSS 0U -#define ADC_ICHDR2_VAL_POSE 15U -#define ADC_ICHDR2_VAL_MSK BITS(ADC_ICHDR2_VAL_POSS,ADC_ICHDR2_VAL_POSE) - -/****************** Bit definition for ADC_ICHDR3 register ************************/ - -#define ADC_ICHDR3_VAL_POSS 0U -#define ADC_ICHDR3_VAL_POSE 15U -#define ADC_ICHDR3_VAL_MSK BITS(ADC_ICHDR3_VAL_POSS,ADC_ICHDR3_VAL_POSE) - -/****************** Bit definition for ADC_ICHDR4 register ************************/ - -#define ADC_ICHDR4_VAL_POSS 0U -#define ADC_ICHDR4_VAL_POSE 15U -#define ADC_ICHDR4_VAL_MSK BITS(ADC_ICHDR4_VAL_POSS,ADC_ICHDR4_VAL_POSE) - -/****************** Bit definition for ADC_NCHDR register ************************/ - -#define ADC_NCHDR_VAL_POSS 0U -#define ADC_NCHDR_VAL_POSE 15U -#define ADC_NCHDR_VAL_MSK BITS(ADC_NCHDR_VAL_POSS,ADC_NCHDR_VAL_POSE) - -/****************** Bit definition for ADC_CCR register ************************/ - -#define ADC_CCR_TRMEN_POS 28U -#define ADC_CCR_TRMEN_MSK BIT(ADC_CCR_TRMEN_POS) - -#define ADC_CCR_GAINCALEN_POS 25U -#define ADC_CCR_GAINCALEN_MSK BIT(ADC_CCR_GAINCALEN_POS) - -#define ADC_CCR_OFFCALEN_POS 24U -#define ADC_CCR_OFFCALEN_MSK BIT(ADC_CCR_OFFCALEN_POS) - -#define ADC_CCR_VREFOEN_POS 19U -#define ADC_CCR_VREFOEN_MSK BIT(ADC_CCR_VREFOEN_POS) - -#define ADC_CCR_VRNSEL_POS 18U -#define ADC_CCR_VRNSEL_MSK BIT(ADC_CCR_VRNSEL_POS) - -#define ADC_CCR_VRPSEL_POSS 16U -#define ADC_CCR_VRPSEL_POSE 17U -#define ADC_CCR_VRPSEL_MSK BITS(ADC_CCR_VRPSEL_POSS,ADC_CCR_VRPSEL_POSE) - -#define ADC_CCR_PWRMODSEL_POS 15U -#define ADC_CCR_PWRMODSEL_MSK BIT(ADC_CCR_PWRMODSEL_POS) - -#define ADC_CCR_DIFFEN_POS 12U -#define ADC_CCR_DIFFEN_MSK BIT(ADC_CCR_DIFFEN_POS) - -#define ADC_CCR_IREFEN_POS 11U -#define ADC_CCR_IREFEN_MSK BIT(ADC_CCR_IREFEN_POS) - -#define ADC_CCR_VRBUFEN_POS 10U -#define ADC_CCR_VRBUFEN_MSK BIT(ADC_CCR_VRBUFEN_POS) - -#define ADC_CCR_VCMBUFEN_POS 9U -#define ADC_CCR_VCMBUFEN_MSK BIT(ADC_CCR_VCMBUFEN_POS) - -#define ADC_CCR_VREFEN_POS 8U -#define ADC_CCR_VREFEN_MSK BIT(ADC_CCR_VREFEN_POS) - -#define ADC_CCR_CKDIV_POSS 0U -#define ADC_CCR_CKDIV_POSE 2U -#define ADC_CCR_CKDIV_MSK BITS(ADC_CCR_CKDIV_POSS,ADC_CCR_CKDIV_POSE) - -typedef struct -{ - __I uint32_t STAT; - __O uint32_t CLR; - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t SMPT1; - __IO uint32_t SMPT2; - __IO uint32_t ICHOFF[4]; - __IO uint32_t WDTH; - __IO uint32_t WDTL; - __IO uint32_t NCHS1; - __IO uint32_t NCHS2; - __IO uint32_t NCHS3; - __IO uint32_t NCHS4; - __IO uint32_t ICHS; - __IO uint32_t CHSL; - __I uint32_t ICHDR[4]; - __I uint32_t NCHDR; - __IO uint32_t CCR; -} ADC_TypeDef; - -/****************** Bit definition for ACMP_CON register ************************/ - -#define ACMP_CON_FALLEN_POS 17U -#define ACMP_CON_FALLEN_MSK BIT(ACMP_CON_FALLEN_POS) - -#define ACMP_CON_RISEEN_POS 16U -#define ACMP_CON_RISEEN_MSK BIT(ACMP_CON_RISEEN_POS) - -#define ACMP_CON_MODSEL_POSS 14U -#define ACMP_CON_MODSEL_POSE 15U -#define ACMP_CON_MODSEL_MSK BITS(ACMP_CON_MODSEL_POSS,ACMP_CON_MODSEL_POSE) - -#define ACMP_CON_WARMUPT_POSS 8U -#define ACMP_CON_WARMUPT_POSE 10U -#define ACMP_CON_WARMUPT_MSK BITS(ACMP_CON_WARMUPT_POSS,ACMP_CON_WARMUPT_POSE) - -#define ACMP_CON_HYSTSEL_POSS 4U -#define ACMP_CON_HYSTSEL_POSE 6U -#define ACMP_CON_HYSTSEL_MSK BITS(ACMP_CON_HYSTSEL_POSS,ACMP_CON_HYSTSEL_POSE) - -#define ACMP_CON_OUTINV_POS 3U -#define ACMP_CON_OUTINV_MSK BIT(ACMP_CON_OUTINV_POS) - -#define ACMP_CON_INACTV_POS 2U -#define ACMP_CON_INACTV_MSK BIT(ACMP_CON_INACTV_POS) - -#define ACMP_CON_EN_POS 0U -#define ACMP_CON_EN_MSK BIT(ACMP_CON_EN_POS) - -/****************** Bit definition for ACMP_INPUTSEL register ************************/ - -#define ACMP_INPUTSEL_VDDLVL_POSS 8U -#define ACMP_INPUTSEL_VDDLVL_POSE 13U -#define ACMP_INPUTSEL_VDDLVL_MSK BITS(ACMP_INPUTSEL_VDDLVL_POSS,ACMP_INPUTSEL_VDDLVL_POSE) - -#define ACMP_INPUTSEL_NSEL_POSS 4U -#define ACMP_INPUTSEL_NSEL_POSE 7U -#define ACMP_INPUTSEL_NSEL_MSK BITS(ACMP_INPUTSEL_NSEL_POSS,ACMP_INPUTSEL_NSEL_POSE) - -#define ACMP_INPUTSEL_PSEL_POSS 0U -#define ACMP_INPUTSEL_PSEL_POSE 2U -#define ACMP_INPUTSEL_PSEL_MSK BITS(ACMP_INPUTSEL_PSEL_POSS,ACMP_INPUTSEL_PSEL_POSE) - -/****************** Bit definition for ACMP_STAT register ************************/ - -#define ACMP_STAT_OUT_POS 1U -#define ACMP_STAT_OUT_MSK BIT(ACMP_STAT_OUT_POS) - -#define ACMP_STAT_ACT_POS 0U -#define ACMP_STAT_ACT_MSK BIT(ACMP_STAT_ACT_POS) - -/****************** Bit definition for ACMP_IES register ************************/ - -#define ACMP_IES_WARMUP_POS 1U -#define ACMP_IES_WARMUP_MSK BIT(ACMP_IES_WARMUP_POS) - -#define ACMP_IES_EDGE_POS 0U -#define ACMP_IES_EDGE_MSK BIT(ACMP_IES_EDGE_POS) - -/****************** Bit definition for ACMP_IEV register ************************/ - -#define ACMP_IEV_WARMUP_POS 1U -#define ACMP_IEV_WARMUP_MSK BIT(ACMP_IEV_WARMUP_POS) - -#define ACMP_IEV_EDGE_POS 0U -#define ACMP_IEV_EDGE_MSK BIT(ACMP_IEV_EDGE_POS) - -/****************** Bit definition for ACMP_IEC register ************************/ - -#define ACMP_IEC_WARMUP_POS 1U -#define ACMP_IEC_WARMUP_MSK BIT(ACMP_IEC_WARMUP_POS) - -#define ACMP_IEC_EDGE_POS 0U -#define ACMP_IEC_EDGE_MSK BIT(ACMP_IEC_EDGE_POS) - -/****************** Bit definition for ACMP_RIF register ************************/ - -#define ACMP_RIF_WARMUP_POS 1U -#define ACMP_RIF_WARMUP_MSK BIT(ACMP_RIF_WARMUP_POS) - -#define ACMP_RIF_EDGE_POS 0U -#define ACMP_RIF_EDGE_MSK BIT(ACMP_RIF_EDGE_POS) - -/****************** Bit definition for ACMP_IFM register ************************/ - -#define ACMP_IFM_WARMUP_POS 1U -#define ACMP_IFM_WARMUP_MSK BIT(ACMP_IFM_WARMUP_POS) - -#define ACMP_IFM_EDGE_POS 0U -#define ACMP_IFM_EDGE_MSK BIT(ACMP_IFM_EDGE_POS) - -/****************** Bit definition for ACMP_IFC register ************************/ - -#define ACMP_IFC_WARMUP_POS 1U -#define ACMP_IFC_WARMUP_MSK BIT(ACMP_IFC_WARMUP_POS) - -#define ACMP_IFC_EDGE_POS 0U -#define ACMP_IFC_EDGE_MSK BIT(ACMP_IFC_EDGE_POS) - -/****************** Bit definition for ACMP_PORT register ************************/ - -#define ACMP_PORT_PEN_POS 0U -#define ACMP_PORT_PEN_MSK BIT(ACMP_PORT_PEN_POS) - -typedef struct -{ - __IO uint32_t CON; - __IO uint32_t INPUTSEL; - __I uint32_t STAT; - __O uint32_t IES; - __I uint32_t IEV; - __O uint32_t IEC; - __I uint32_t RIF; - __O uint32_t IFM; - __O uint32_t IFC; - __IO uint32_t PORT; -} ACMP_TypeDef; - -/****************** Bit definition for CALC_SQRTSR register ************************/ - -#define CALC_SQRTSR_BUSY_POS 0U -#define CALC_SQRTSR_BUSY_MSK BIT(CALC_SQRTSR_BUSY_POS) - -/****************** Bit definition for CALC_RDCND register ************************/ - -#define CALC_RDCND_RADICAND_POSS 0U -#define CALC_RDCND_RADICAND_POSE 31U -#define CALC_RDCND_RADICAND_MSK BITS(CALC_RDCND_RADICAND_POSS,CALC_RDCND_RADICAND_POSE) - -/****************** Bit definition for CALC_SQRTRES register ************************/ - -#define CALC_SQRTRES_RESULT_POSS 0U -#define CALC_SQRTRES_RESULT_POSE 15U -#define CALC_SQRTRES_RESULT_MSK BITS(CALC_SQRTRES_RESULT_POSS,CALC_SQRTRES_RESULT_POSE) - -/****************** Bit definition for CALC_DIVDR register ************************/ - -#define CALC_DIVDR_DIVD_POSS 0U -#define CALC_DIVDR_DIVD_POSE 31U -#define CALC_DIVDR_DIVD_MSK BITS(CALC_DIVDR_DIVD_POSS,CALC_DIVDR_DIVD_POSE) - -/****************** Bit definition for CALC_DIVSR register ************************/ - -#define CALC_DIVSR_DIVS_POSS 0U -#define CALC_DIVSR_DIVS_POSE 31U -#define CALC_DIVSR_DIVS_MSK BITS(CALC_DIVSR_DIVS_POSS,CALC_DIVSR_DIVS_POSE) - -/****************** Bit definition for CALC_DIVQR register ************************/ - -#define CALC_DIVQR_DIVQ_POSS 0U -#define CALC_DIVQR_DIVQ_POSE 31U -#define CALC_DIVQR_DIVQ_MSK BITS(CALC_DIVQR_DIVQ_POSS,CALC_DIVQR_DIVQ_POSE) - -/****************** Bit definition for CALC_DIVRR register ************************/ - -#define CALC_DIVRR_DIVS_POSS 0U -#define CALC_DIVRR_DIVS_POSE 31U -#define CALC_DIVRR_DIVS_MSK BITS(CALC_DIVRR_DIVS_POSS,CALC_DIVRR_DIVS_POSE) - -/****************** Bit definition for CALC_DIVCSR register ************************/ - -#define CALC_DIVCSR_TRM_POS 9U -#define CALC_DIVCSR_TRM_MSK BIT(CALC_DIVCSR_TRM_POS) - -#define CALC_DIVCSR_SIGN_POS 8U -#define CALC_DIVCSR_SIGN_MSK BIT(CALC_DIVCSR_SIGN_POS) - -#define CALC_DIVCSR_DZ_POS 1U -#define CALC_DIVCSR_DZ_MSK BIT(CALC_DIVCSR_DZ_POS) - -#define CALC_DIVCSR_BUSY_POS 0U -#define CALC_DIVCSR_BUSY_MSK BIT(CALC_DIVCSR_BUSY_POS) - -typedef struct -{ - __I uint32_t SQRTSR; - __IO uint32_t RDCND; - __I uint32_t SQRTRES; - uint32_t RESERVED0[5] ; - __IO uint32_t DIVDR; - __IO uint32_t DIVSR; - __I uint32_t DIVQR; - __I uint32_t DIVRR; - __IO uint32_t DIVCSR; -} CALC_TypeDef; - -/****************** Bit definition for TRNG_CR register ************************/ - -#define TRNG_CR_ADJC_POSS 16U -#define TRNG_CR_ADJC_POSE 17U -#define TRNG_CR_ADJC_MSK BITS(TRNG_CR_ADJC_POSS,TRNG_CR_ADJC_POSE) - -#define TRNG_CR_SDSEL_POSS 10U -#define TRNG_CR_SDSEL_POSE 11U -#define TRNG_CR_SDSEL_MSK BITS(TRNG_CR_SDSEL_POSS,TRNG_CR_SDSEL_POSE) - -#define TRNG_CR_DSEL_POSS 8U -#define TRNG_CR_DSEL_POSE 9U -#define TRNG_CR_DSEL_MSK BITS(TRNG_CR_DSEL_POSS,TRNG_CR_DSEL_POSE) - -#define TRNG_CR_POSTEN_POS 3U -#define TRNG_CR_POSTEN_MSK BIT(TRNG_CR_POSTEN_POS) - -#define TRNG_CR_TRNGSEL_POS 2U -#define TRNG_CR_TRNGSEL_MSK BIT(TRNG_CR_TRNGSEL_POS) - -#define TRNG_CR_ADJM_POS 1U -#define TRNG_CR_ADJM_MSK BIT(TRNG_CR_ADJM_POS) - -#define TRNG_CR_TRNGEN_POS 0U -#define TRNG_CR_TRNGEN_MSK BIT(TRNG_CR_TRNGEN_POS) - -/****************** Bit definition for TRNG_SR register ************************/ - -#define TRNG_SR_OVER_POS 3U -#define TRNG_SR_OVER_MSK BIT(TRNG_SR_OVER_POS) - -#define TRNG_SR_SERR_POS 2U -#define TRNG_SR_SERR_MSK BIT(TRNG_SR_SERR_POS) - -#define TRNG_SR_DAVLD_POS 1U -#define TRNG_SR_DAVLD_MSK BIT(TRNG_SR_DAVLD_POS) - -#define TRNG_SR_START_POS 0U -#define TRNG_SR_START_MSK BIT(TRNG_SR_START_POS) - -/****************** Bit definition for TRNG_DR register ************************/ - -#define TRNG_DR_DATA_POSS 0U -#define TRNG_DR_DATA_POSE 31U -#define TRNG_DR_DATA_MSK BITS(TRNG_DR_DATA_POSS,TRNG_DR_DATA_POSE) - -/****************** Bit definition for TRNG_SEED register ************************/ - -#define TRNG_SEED_SEED_POSS 0U -#define TRNG_SEED_SEED_POSE 31U -#define TRNG_SEED_SEED_MSK BITS(TRNG_SEED_SEED_POSS,TRNG_SEED_SEED_POSE) - -/****************** Bit definition for TRNG_CFGR register ************************/ - -#define TRNG_CFGR_TOPLMT_POSS 16U -#define TRNG_CFGR_TOPLMT_POSE 24U -#define TRNG_CFGR_TOPLMT_MSK BITS(TRNG_CFGR_TOPLMT_POSS,TRNG_CFGR_TOPLMT_POSE) - -#define TRNG_CFGR_CKDIV_POSS 8U -#define TRNG_CFGR_CKDIV_POSE 11U -#define TRNG_CFGR_CKDIV_MSK BITS(TRNG_CFGR_CKDIV_POSS,TRNG_CFGR_CKDIV_POSE) - -#define TRNG_CFGR_TSTART_POSS 0U -#define TRNG_CFGR_TSTART_POSE 2U -#define TRNG_CFGR_TSTART_MSK BITS(TRNG_CFGR_TSTART_POSS,TRNG_CFGR_TSTART_POSE) - -/****************** Bit definition for TRNG_IER register ************************/ - -#define TRNG_IER_SERR_POS 2U -#define TRNG_IER_SERR_MSK BIT(TRNG_IER_SERR_POS) - -#define TRNG_IER_DAVLD_POS 1U -#define TRNG_IER_DAVLD_MSK BIT(TRNG_IER_DAVLD_POS) - -#define TRNG_IER_START_POS 0U -#define TRNG_IER_START_MSK BIT(TRNG_IER_START_POS) - -/****************** Bit definition for TRNG_IFR register ************************/ - -#define TRNG_IFR_SERR_POS 2U -#define TRNG_IFR_SERR_MSK BIT(TRNG_IFR_SERR_POS) - -#define TRNG_IFR_DAVLD_POS 1U -#define TRNG_IFR_DAVLD_MSK BIT(TRNG_IFR_DAVLD_POS) - -#define TRNG_IFR_START_POS 0U -#define TRNG_IFR_START_MSK BIT(TRNG_IFR_START_POS) - -/****************** Bit definition for TRNG_IFCR register ************************/ - -#define TRNG_IFCR_SERRC_POS 2U -#define TRNG_IFCR_SERRC_MSK BIT(TRNG_IFCR_SERRC_POS) - -#define TRNG_IFCR_DAVLDC_POS 1U -#define TRNG_IFCR_DAVLDC_MSK BIT(TRNG_IFCR_DAVLDC_POS) - -#define TRNG_IFCR_STARTC_POS 0U -#define TRNG_IFCR_STARTC_MSK BIT(TRNG_IFCR_STARTC_POS) - -/****************** Bit definition for TRNG_ISR register ************************/ - -#define TRNG_ISR_SERR_POS 2U -#define TRNG_ISR_SERR_MSK BIT(TRNG_ISR_SERR_POS) - -#define TRNG_ISR_DAVLD_POS 1U -#define TRNG_ISR_DAVLD_MSK BIT(TRNG_ISR_DAVLD_POS) - -#define TRNG_ISR_START_POS 0U -#define TRNG_ISR_START_MSK BIT(TRNG_ISR_START_POS) - -typedef struct -{ - __IO uint32_t CR; - __I uint32_t SR; - __I uint32_t DR; - __IO uint32_t SEED; - __IO uint32_t CFGR; - __IO uint32_t IER; - __I uint32_t IFR; - __O uint32_t IFCR; - __I uint32_t ISR; -} TRNG_TypeDef; - -/****************** Bit definition for TEMP_WPR register ************************/ - -#define TEMP_WPR_WP_POS 0U -#define TEMP_WPR_WP_MSK BIT(TEMP_WPR_WP_POS) - -/****************** Bit definition for TEMP_CR register ************************/ - -#define TEMP_CR_TSU_POSS 12U -#define TEMP_CR_TSU_POSE 14U -#define TEMP_CR_TSU_MSK BITS(TEMP_CR_TSU_POSS,TEMP_CR_TSU_POSE) - -#define TEMP_CR_TOM_POSS 8U -#define TEMP_CR_TOM_POSE 10U -#define TEMP_CR_TOM_MSK BITS(TEMP_CR_TOM_POSS,TEMP_CR_TOM_POSE) - -#define TEMP_CR_CTN_POS 4U -#define TEMP_CR_CTN_MSK BIT(TEMP_CR_CTN_POS) - -#define TEMP_CR_RST_POS 3U -#define TEMP_CR_RST_MSK BIT(TEMP_CR_RST_POS) - -#define TEMP_CR_ENS_POS 2U -#define TEMP_CR_ENS_MSK BIT(TEMP_CR_ENS_POS) - -#define TEMP_CR_REQEN_POS 1U -#define TEMP_CR_REQEN_MSK BIT(TEMP_CR_REQEN_POS) - -#define TEMP_CR_EN_POS 0U -#define TEMP_CR_EN_MSK BIT(TEMP_CR_EN_POS) - -/****************** Bit definition for TEMP_DR register ************************/ - -#define TEMP_DR_ERR_POS 31U -#define TEMP_DR_ERR_MSK BIT(TEMP_DR_ERR_POS) - -#define TEMP_DR_DATA_POSS 0U -#define TEMP_DR_DATA_POSE 15U -#define TEMP_DR_DATA_MSK BITS(TEMP_DR_DATA_POSS,TEMP_DR_DATA_POSE) - -/****************** Bit definition for TEMP_PSR register ************************/ - -#define TEMP_PSR_PRS_POSS 0U -#define TEMP_PSR_PRS_POSE 7U -#define TEMP_PSR_PRS_MSK BITS(TEMP_PSR_PRS_POSS,TEMP_PSR_PRS_POSE) - -/****************** Bit definition for TEMP_IE register ************************/ - -#define TEMP_IE_TEMP_POS 0U -#define TEMP_IE_TEMP_MSK BIT(TEMP_IE_TEMP_POS) - -/****************** Bit definition for TEMP_IF register ************************/ - -#define TEMP_IF_TEMP_POS 0U -#define TEMP_IF_TEMP_MSK BIT(TEMP_IF_TEMP_POS) - -/****************** Bit definition for TEMP_IFCR register ************************/ - -#define TEMP_IFCR_TEMP_POS 0U -#define TEMP_IFCR_TEMP_MSK BIT(TEMP_IFCR_TEMP_POS) - -/****************** Bit definition for TEMP_LTGR register ************************/ - -#define TEMP_LTGR_LTG_POSS 0U -#define TEMP_LTGR_LTG_POSE 20U -#define TEMP_LTGR_LTG_MSK BITS(TEMP_LTGR_LTG_POSS,TEMP_LTGR_LTG_POSE) - -/****************** Bit definition for TEMP_HTGR register ************************/ - -#define TEMP_HTGR_HTG_POSS 0U -#define TEMP_HTGR_HTG_POSE 20U -#define TEMP_HTGR_HTG_MSK BITS(TEMP_HTGR_HTG_POSS,TEMP_HTGR_HTG_POSE) - -/****************** Bit definition for TEMP_TBDR register ************************/ - -#define TEMP_TBDR_TBD_POSS 0U -#define TEMP_TBDR_TBD_POSE 15U -#define TEMP_TBDR_TBD_MSK BITS(TEMP_TBDR_TBD_POSS,TEMP_TBDR_TBD_POSE) - -/****************** Bit definition for TEMP_TCALBDR register ************************/ - -#define TEMP_TCALBDR_TCAL_POSS 0U -#define TEMP_TCALBDR_TCAL_POSE 16U -#define TEMP_TCALBDR_TCAL_MSK BITS(TEMP_TCALBDR_TCAL_POSS,TEMP_TCALBDR_TCAL_POSE) - -/****************** Bit definition for TEMP_SR register ************************/ - -#define TEMP_SR_TSOUT_POS 31U -#define TEMP_SR_TSOUT_MSK BIT(TEMP_SR_TSOUT_POS) - -#define TEMP_SR_NVLD_POS 25U -#define TEMP_SR_NVLD_MSK BIT(TEMP_SR_NVLD_POS) - -#define TEMP_SR_TCAL_POSS 0U -#define TEMP_SR_TCAL_POSE 24U -#define TEMP_SR_TCAL_MSK BITS(TEMP_SR_TCAL_POSS,TEMP_SR_TCAL_POSE) - -typedef struct -{ - __IO uint32_t WPR; - __IO uint32_t CR; - __I uint32_t DR; - __IO uint32_t PSR; - __IO uint32_t IE; - __I uint32_t IF; - __IO uint32_t IFCR; - __IO uint32_t LTGR; - __IO uint32_t HTGR; - __IO uint32_t TBDR; - __IO uint32_t TCALBDR; - __I uint32_t SR; -} TEMP_TypeDef; - -/****************** Bit definition for IWDT_LOAD register ************************/ - -#define IWDT_LOAD_LOAD_POSS 0U -#define IWDT_LOAD_LOAD_POSE 31U -#define IWDT_LOAD_LOAD_MSK BITS(IWDT_LOAD_LOAD_POSS,IWDT_LOAD_LOAD_POSE) - -/****************** Bit definition for IWDT_VALUE register ************************/ - -#define IWDT_VALUE_VALUE_POSS 0U -#define IWDT_VALUE_VALUE_POSE 31U -#define IWDT_VALUE_VALUE_MSK BITS(IWDT_VALUE_VALUE_POSS,IWDT_VALUE_VALUE_POSE) - -/****************** Bit definition for IWDT_CON register ************************/ - -#define IWDT_CON_CLKS_POS 3U -#define IWDT_CON_CLKS_MSK BIT(IWDT_CON_CLKS_POS) - -#define IWDT_CON_RSTEN_POS 2U -#define IWDT_CON_RSTEN_MSK BIT(IWDT_CON_RSTEN_POS) - -#define IWDT_CON_IE_POS 1U -#define IWDT_CON_IE_MSK BIT(IWDT_CON_IE_POS) - -#define IWDT_CON_EN_POS 0U -#define IWDT_CON_EN_MSK BIT(IWDT_CON_EN_POS) - -/****************** Bit definition for IWDT_INTCLR register ************************/ - -#define IWDT_INTCLR_INTCLR_POSS 0U -#define IWDT_INTCLR_INTCLR_POSE 31U -#define IWDT_INTCLR_INTCLR_MSK BITS(IWDT_INTCLR_INTCLR_POSS,IWDT_INTCLR_INTCLR_POSE) - -/****************** Bit definition for IWDT_RIS register ************************/ - -#define IWDT_RIS_WDTIF_POS 0U -#define IWDT_RIS_WDTIF_MSK BIT(IWDT_RIS_WDTIF_POS) - -/****************** Bit definition for IWDT_LOCK register ************************/ - -#define IWDT_LOCK_LOCK_POS 0U -#define IWDT_LOCK_LOCK_MSK BIT(IWDT_LOCK_LOCK_POS) - -typedef struct -{ - __O uint32_t LOAD; - __I uint32_t VALUE; - __IO uint32_t CON; - __O uint32_t INTCLR; - __I uint32_t RIS; - uint32_t RESERVED0[59] ; - __IO uint32_t LOCK; -} IWDT_TypeDef; - -/****************** Bit definition for WWDT_LOAD register ************************/ - -#define WWDT_LOAD_LOAD_POSS 0U -#define WWDT_LOAD_LOAD_POSE 31U -#define WWDT_LOAD_LOAD_MSK BITS(WWDT_LOAD_LOAD_POSS,WWDT_LOAD_LOAD_POSE) - -/****************** Bit definition for WWDT_VALUE register ************************/ - -#define WWDT_VALUE_VALUE_POSS 0U -#define WWDT_VALUE_VALUE_POSE 31U -#define WWDT_VALUE_VALUE_MSK BITS(WWDT_VALUE_VALUE_POSS,WWDT_VALUE_VALUE_POSE) - -/****************** Bit definition for WWDT_CON register ************************/ - -#define WWDT_CON_WWDTWIN_POSS 4U -#define WWDT_CON_WWDTWIN_POSE 5U -#define WWDT_CON_WWDTWIN_MSK BITS(WWDT_CON_WWDTWIN_POSS,WWDT_CON_WWDTWIN_POSE) - -#define WWDT_CON_CLKS_POS 3U -#define WWDT_CON_CLKS_MSK BIT(WWDT_CON_CLKS_POS) - -#define WWDT_CON_RSTEN_POS 2U -#define WWDT_CON_RSTEN_MSK BIT(WWDT_CON_RSTEN_POS) - -#define WWDT_CON_IE_POS 1U -#define WWDT_CON_IE_MSK BIT(WWDT_CON_IE_POS) - -#define WWDT_CON_EN_POS 0U -#define WWDT_CON_EN_MSK BIT(WWDT_CON_EN_POS) - -/****************** Bit definition for WWDT_INTCLR register ************************/ - -#define WWDT_INTCLR_INTCLR_POSS 0U -#define WWDT_INTCLR_INTCLR_POSE 31U -#define WWDT_INTCLR_INTCLR_MSK BITS(WWDT_INTCLR_INTCLR_POSS,WWDT_INTCLR_INTCLR_POSE) - -/****************** Bit definition for WWDT_RIS register ************************/ - -#define WWDT_RIS_WWDTIF_POS 0U -#define WWDT_RIS_WWDTIF_MSK BIT(WWDT_RIS_WWDTIF_POS) - -/****************** Bit definition for WWDT_LOCK register ************************/ - -#define WWDT_LOCK_LOCK_POS 0U -#define WWDT_LOCK_LOCK_MSK BIT(WWDT_LOCK_LOCK_POS) - -typedef struct -{ - __O uint32_t LOAD; - __I uint32_t VALUE; - __IO uint32_t CON; - __O uint32_t INTCLR; - __I uint32_t RIS; - uint32_t RESERVED0[59]; - __IO uint32_t LOCK; -} WWDT_TypeDef; - -/****************** Bit definition for LP16T_CON0 register ************************/ - -#define LP16T_CON0_PRELOAD_POS 22U -#define LP16T_CON0_PRELOAD_MSK BIT(LP16T_CON0_PRELOAD_POS) - -#define LP16T_CON0_WAVEPOL_POS 21U -#define LP16T_CON0_WAVEPOL_MSK BIT(LP16T_CON0_WAVEPOL_POS) - -#define LP16T_CON0_WAVE_POSS 19U -#define LP16T_CON0_WAVE_POSE 20U -#define LP16T_CON0_WAVE_MSK BITS(LP16T_CON0_WAVE_POSS,LP16T_CON0_WAVE_POSE) - -#define LP16T_CON0_TRIGEN_POSS 17U -#define LP16T_CON0_TRIGEN_POSE 18U -#define LP16T_CON0_TRIGEN_MSK BITS(LP16T_CON0_TRIGEN_POSS,LP16T_CON0_TRIGEN_POSE) - -#define LP16T_CON0_TRIGSEL_POSS 13U -#define LP16T_CON0_TRIGSEL_POSE 15U -#define LP16T_CON0_TRIGSEL_MSK BITS(LP16T_CON0_TRIGSEL_POSS,LP16T_CON0_TRIGSEL_POSE) - -#define LP16T_CON0_PRESC_POSS 9U -#define LP16T_CON0_PRESC_POSE 11U -#define LP16T_CON0_PRESC_MSK BITS(LP16T_CON0_PRESC_POSS,LP16T_CON0_PRESC_POSE) - -#define LP16T_CON0_TRGFLT_POSS 6U -#define LP16T_CON0_TRGFLT_POSE 7U -#define LP16T_CON0_TRGFLT_MSK BITS(LP16T_CON0_TRGFLT_POSS,LP16T_CON0_TRGFLT_POSE) - -#define LP16T_CON0_CKFLT_POSS 3U -#define LP16T_CON0_CKFLT_POSE 4U -#define LP16T_CON0_CKFLT_MSK BITS(LP16T_CON0_CKFLT_POSS,LP16T_CON0_CKFLT_POSE) - -#define LP16T_CON0_CKPOL_POS 1U -#define LP16T_CON0_CKPOL_MSK BIT(LP16T_CON0_CKPOL_POS) - -#define LP16T_CON0_CKSEL_POS 0U -#define LP16T_CON0_CKSEL_MSK BIT(LP16T_CON0_CKSEL_POS) - -/****************** Bit definition for LP16T_CON1 register ************************/ - -#define LP16T_CON1_CNTSTRT_POS 2U -#define LP16T_CON1_CNTSTRT_MSK BIT(LP16T_CON1_CNTSTRT_POS) - -#define LP16T_CON1_SNGSTRT_POS 1U -#define LP16T_CON1_SNGSTRT_MSK BIT(LP16T_CON1_SNGSTRT_POS) - -#define LP16T_CON1_ENABLE_POS 0U -#define LP16T_CON1_ENABLE_MSK BIT(LP16T_CON1_ENABLE_POS) - -/****************** Bit definition for LP16T_ARR register ************************/ - -#define LP16T_ARR_ARR_POSS 0U -#define LP16T_ARR_ARR_POSE 15U -#define LP16T_ARR_ARR_MSK BITS(LP16T_ARR_ARR_POSS,LP16T_ARR_ARR_POSE) - -/****************** Bit definition for LP16T_CNT register ************************/ - -#define LP16T_CNT_CNT_POSS 0U -#define LP16T_CNT_CNT_POSE 15U -#define LP16T_CNT_CNT_MSK BITS(LP16T_CNT_CNT_POSS,LP16T_CNT_CNT_POSE) - -/****************** Bit definition for LP16T_CMP register ************************/ - -#define LP16T_CMP_CMP_POSS 0U -#define LP16T_CMP_CMP_POSE 15U -#define LP16T_CMP_CMP_MSK BITS(LP16T_CMP_CMP_POSS,LP16T_CMP_CMP_POSE) - -/****************** Bit definition for LP16T_IER register ************************/ - -#define LP16T_IER_EXTTRIGIE_POS 2U -#define LP16T_IER_EXTTRIGIE_MSK BIT(LP16T_IER_EXTTRIGIE_POS) - -#define LP16T_IER_ARRMIE_POS 1U -#define LP16T_IER_ARRMIE_MSK BIT(LP16T_IER_ARRMIE_POS) - -#define LP16T_IER_CMPMIE_POS 0U -#define LP16T_IER_CMPMIE_MSK BIT(LP16T_IER_CMPMIE_POS) - -/****************** Bit definition for LP16T_ISR register ************************/ - -#define LP16T_ISR_EXTTRIG_POS 2U -#define LP16T_ISR_EXTTRIG_MSK BIT(LP16T_ISR_EXTTRIG_POS) - -#define LP16T_ISR_ARRM_POS 1U -#define LP16T_ISR_ARRM_MSK BIT(LP16T_ISR_ARRM_POS) - -#define LP16T_ISR_CMPM_POS 0U -#define LP16T_ISR_CMPM_MSK BIT(LP16T_ISR_CMPM_POS) - -/****************** Bit definition for LP16T_IFC register ************************/ - -#define LP16T_IFC_EXTTRIG_POS 2U -#define LP16T_IFC_EXTTRIG_MSK BIT(LP16T_IFC_EXTTRIG_POS) - -#define LP16T_IFC_ARRM_POS 1U -#define LP16T_IFC_ARRM_MSK BIT(LP16T_IFC_ARRM_POS) - -#define LP16T_IFC_CMPM_POS 0U -#define LP16T_IFC_CMPM_MSK BIT(LP16T_IFC_CMPM_POS) - -/****************** Bit definition for LP16T_UPDATE register ************************/ - -#define LP16T_UPDATE_UDIS_POS 0U -#define LP16T_UPDATE_UDIS_MSK BIT(LP16T_UPDATE_UDIS_POS) - -/****************** Bit definition for LP16T_SYNCSTAT register ************************/ - -#define LP16T_SYNCSTAT_CMPWBSY_POS 3U -#define LP16T_SYNCSTAT_CMPWBSY_MSK BIT(LP16T_SYNCSTAT_CMPWBSY_POS) - -#define LP16T_SYNCSTAT_ARRWBSY_POS 2U -#define LP16T_SYNCSTAT_ARRWBSY_MSK BIT(LP16T_SYNCSTAT_ARRWBSY_POS) - -#define LP16T_SYNCSTAT_CON1WBSY_POS 1U -#define LP16T_SYNCSTAT_CON1WBSY_MSK BIT(LP16T_SYNCSTAT_CON1WBSY_POS) - -typedef struct -{ - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t ARR; - __I uint32_t CNT; - __IO uint32_t CMP; - uint32_t RESERVED0 ; - __IO uint32_t IER; - __I uint32_t ISR; - __O uint32_t IFC; - uint32_t RESERVED1[3] ; - __IO uint32_t UPDATE; - __I uint32_t SYNCSTAT; -} LPTIM_TypeDef; - -/****************** Bit definition for DBGC_IDCODE register ************************/ - -#define DBGC_IDCODE_REV_ID_POSS 16U -#define DBGC_IDCODE_REV_ID_POSE 31U -#define DBGC_IDCODE_REV_ID_MSK BITS(DBGC_IDCODE_REV_ID_POSS,DBGC_IDCODE_REV_ID_POSE) - -#define DBGC_IDCODE_CORE_ID_POSS 12U -#define DBGC_IDCODE_CORE_ID_POSE 15U -#define DBGC_IDCODE_CORE_ID_MSK BITS(DBGC_IDCODE_CORE_ID_POSS,DBGC_IDCODE_CORE_ID_POSE) - -#define DBGC_IDCODE_DEV_ID_POSS 0U -#define DBGC_IDCODE_DEV_ID_POSE 11U -#define DBGC_IDCODE_DEV_ID_MSK BITS(DBGC_IDCODE_DEV_ID_POSS,DBGC_IDCODE_DEV_ID_POSE) - -/****************** Bit definition for DBGC_CR register ************************/ - -#define DBGC_CR_DBG_STANDBY_POS 3U -#define DBGC_CR_DBG_STANDBY_MSK BIT(DBGC_CR_DBG_STANDBY_POS) - -#define DBGC_CR_DBG_STOP2_POS 2U -#define DBGC_CR_DBG_STOP2_MSK BIT(DBGC_CR_DBG_STOP2_POS) - -#define DBGC_CR_DBG_STOP1_POS 1U -#define DBGC_CR_DBG_STOP1_MSK BIT(DBGC_CR_DBG_STOP1_POS) - -#define DBGC_CR_DBG_SLEEP_POS 0U -#define DBGC_CR_DBG_SLEEP_MSK BIT(DBGC_CR_DBG_SLEEP_POS) - -/****************** Bit definition for DBGC_APB1FZ register ************************/ - -#define DBGC_APB1FZ_CAN_STOP_POS 12U -#define DBGC_APB1FZ_CAN_STOP_MSK BIT(DBGC_APB1FZ_CAN_STOP_POS) - -#define DBGC_APB1FZ_I2C1_SMBUS_TO_POS 9U -#define DBGC_APB1FZ_I2C1_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C1_SMBUS_TO_POS) - -#define DBGC_APB1FZ_I2C0_SMBUS_TO_POS 8U -#define DBGC_APB1FZ_I2C0_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C0_SMBUS_TO_POS) - -#define DBGC_APB1FZ_TIM7_STOP_POS 7U -#define DBGC_APB1FZ_TIM7_STOP_MSK BIT(DBGC_APB1FZ_TIM7_STOP_POS) - -#define DBGC_APB1FZ_TIM6_STOP_POS 6U -#define DBGC_APB1FZ_TIM6_STOP_MSK BIT(DBGC_APB1FZ_TIM6_STOP_POS) - -#define DBGC_APB1FZ_TIM5_STOP_POS 5U -#define DBGC_APB1FZ_TIM5_STOP_MSK BIT(DBGC_APB1FZ_TIM5_STOP_POS) - -#define DBGC_APB1FZ_TIM4_STOP_POS 4U -#define DBGC_APB1FZ_TIM4_STOP_MSK BIT(DBGC_APB1FZ_TIM4_STOP_POS) - -#define DBGC_APB1FZ_TIM3_STOP_POS 3U -#define DBGC_APB1FZ_TIM3_STOP_MSK BIT(DBGC_APB1FZ_TIM3_STOP_POS) - -#define DBGC_APB1FZ_TIM2_STOP_POS 2U -#define DBGC_APB1FZ_TIM2_STOP_MSK BIT(DBGC_APB1FZ_TIM2_STOP_POS) - -#define DBGC_APB1FZ_TIM1_STOP_POS 1U -#define DBGC_APB1FZ_TIM1_STOP_MSK BIT(DBGC_APB1FZ_TIM1_STOP_POS) - -#define DBGC_APB1FZ_TIM0_STOP_POS 0U -#define DBGC_APB1FZ_TIM0_STOP_MSK BIT(DBGC_APB1FZ_TIM0_STOP_POS) - -/****************** Bit definition for DBGC_APB2FZ register ************************/ - -#define DBGC_APB2FZ_RTC_STOP_POS 10U -#define DBGC_APB2FZ_RTC_STOP_MSK BIT(DBGC_APB2FZ_RTC_STOP_POS) - -#define DBGC_APB2FZ_WWDT_STOP_POS 9U -#define DBGC_APB2FZ_WWDT_STOP_MSK BIT(DBGC_APB2FZ_WWDT_STOP_POS) - -#define DBGC_APB2FZ_IWDT_STOP_POS 8U -#define DBGC_APB2FZ_IWDT_STOP_MSK BIT(DBGC_APB2FZ_IWDT_STOP_POS) - -#define DBGC_APB2FZ_LPTIM0_STOP_POS 0U -#define DBGC_APB2FZ_LPTIM0_STOP_MSK BIT(DBGC_APB2FZ_LPTIM0_STOP_POS) - -typedef struct -{ - __I uint32_t IDCODE; - __IO uint32_t CR; - __IO uint32_t APB1FZ; - __IO uint32_t APB2FZ; -} DBGC_TypeDef; - - -/* Base addresses */ -#define SRAM_BASE (0x20000000UL) -#define APB1_BASE (0x40000000UL) -#define APB2_BASE (0x40040000UL) -#define AHB_BASE (0x40080000UL) - -/* Timer memory map */ -#define TIMER0_BASE (APB1_BASE + 0x0000) -#define TIMER1_BASE (APB1_BASE + 0x0400) -#define TIMER2_BASE (APB1_BASE + 0x0800) -#define TIMER3_BASE (APB1_BASE + 0x0C00) -#define TIMER4_BASE (APB1_BASE + 0x1000) -#define TIMER5_BASE (APB1_BASE + 0x1400) -#define TIMER6_BASE (APB1_BASE + 0x1800) -#define TIMER7_BASE (APB1_BASE + 0x1C00) - -/* SPI memory map */ -#define SPI0_BASE (APB1_BASE + 0x6000) -#define SPI1_BASE (APB1_BASE + 0x6400) -#define SPI2_BASE (APB1_BASE + 0x6800) - -/* I2C memory map */ -#define I2C0_BASE (APB1_BASE + 0x8000) -#define I2C1_BASE (APB1_BASE + 0x8400) - -/* AHB peripherals */ -#define SYSTEM_BASE (AHB_BASE + 0x0000) -#define GPIOA_BASE (AHB_BASE + 0x4000) -#define GPIOB_BASE (AHB_BASE + 0x4040) -#define GPIOC_BASE (AHB_BASE + 0x4080) -#define GPIOD_BASE (AHB_BASE + 0x40C0) -#define GPIOE_BASE (AHB_BASE + 0x4100) -#define GPIOF_BASE (AHB_BASE + 0x4140) -#define GPIOG_BASE (AHB_BASE + 0x4180) -#define GPIOH_BASE (AHB_BASE + 0x41C0) -#define EXTI_BASE (AHB_BASE + 0x4300) -#define CRC_BASE (AHB_BASE + 0x5000) -#define CALC_BASE (AHB_BASE + 0x5400) -#define TRNG_BASE (AHB_BASE + 0x5C00) -#define CRYPT_BASE (AHB_BASE + 0x5800) - -#define SYSCFG_BASE (SYSTEM_BASE + 0x0000) -#define CMU_BASE (SYSTEM_BASE + 0x0400) -#define RMU_BASE (SYSTEM_BASE + 0x0800) -#define PMU_BASE (SYSTEM_BASE + 0x0C00) -#define MSC_BASE (SYSTEM_BASE + 0x1000) -#define PIS_BASE (SYSTEM_BASE + 0x6000) - -/* APB1 peripherals */ -#define CAN0_BASE (APB1_BASE + 0xB000) -#define USART0_BASE (APB1_BASE + 0x5000) -#define USART1_BASE (APB1_BASE + 0x5400) -#define UART0_BASE (APB1_BASE + 0x4000) -#define UART1_BASE (APB1_BASE + 0x4400) -#define UART2_BASE (APB1_BASE + 0x4800) -#define UART3_BASE (APB1_BASE + 0x4C00) -#define DMA0_BASE (APB1_BASE + 0xC000) - -/* APB2 peripherals */ -#define LPTIM0_BASE (APB2_BASE + 0x0000) -#define LPUART0_BASE (APB2_BASE + 0x1000) -#define DBGC_BASE (APB2_BASE + 0xA000) -#define WWDT_BASE (APB2_BASE + 0x6000) -#define IWDT_BASE (APB2_BASE + 0x6400) -#define RTC_BASE (APB2_BASE + 0x8400) -#define LCD_BASE (APB2_BASE + 0x7000) -#define ADC0_BASE (APB2_BASE + 0x2000) -#define ADC1_BASE (APB2_BASE + 0x2400) -#define ACMP0_BASE (APB2_BASE + 0x3000) -#define ACMP1_BASE (APB2_BASE + 0x3400) -#define OPAMP_BASE (APB2_BASE + 0x4000) -#define DAC0_BASE (APB2_BASE + 0x5000) -#define BKPC_BASE (APB2_BASE + 0x8000) -#define TEMP_BASE (APB2_BASE + 0x8800) - -/* RTC Peripheral declaration */ -#define RTC ((RTC_TypeDef *)RTC_BASE) - -/* GPIO Peripheral_declaration */ -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *)GPIOH_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) - -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define TRNG ((TRNG_TypeDef *)TRNG_BASE) -#define CALC ((CALC_TypeDef *)CALC_BASE) -#define CRYPT ((CRYPT_TypeDef *)CRYPT_BASE) -#define PIS ((PIS_TypeDef *)PIS_BASE) - -/* LCD Peripheral declaration */ -#define LCD ((LCD_TypeDef *)LCD_BASE) -/* ADC Peripheral declaration */ -#define ADC0 ((ADC_TypeDef *)ADC0_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -/* ACMP Peripheral declaration */ -#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) -#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) -/* OPAMP Peripheral declaration */ -#define OPAMP ((OPAMP_TypeDef *)OPAMP_BASE) -/* DAC Peripheral declaration */ -#define DAC0 ((DAC_TypeDef *)DAC0_BASE) -/* TEMP Peripheral declaration */ -#define TEMP ((TEMP_TypeDef *)TEMP_BASE) -/* BKPC Peripheral declaration */ -#define BKPC ((BKPC_TypeDef *)BKPC_BASE) - -/* Timer Peripheral_declaration */ -#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) -#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) -#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) -#define TIMER3 ((TIMER_TypeDef *)TIMER3_BASE) -#define TIMER4 ((TIMER_TypeDef *)TIMER4_BASE) -#define TIMER5 ((TIMER_TypeDef *)TIMER5_BASE) -#define TIMER6 ((TIMER_TypeDef *)TIMER6_BASE) -#define TIMER7 ((TIMER_TypeDef *)TIMER7_BASE) - -#define AD16C4T0 TIMER0 -#define GP16C4T0 TIMER6 -#define GP16C2T0 TIMER2 -#define GP16C2T1 TIMER3 -#define BS16T0 TIMER1 -#define BS16T1 TIMER4 -#define BS16T2 TIMER5 -#define BS16T3 TIMER7 - -/* SPI Peripheral_declaration */ -#define SPI0 ((SPI_TypeDef *)SPI0_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) - -/* I2C Peripheral_declaration */ -#define I2C0 ((I2C_TypeDef *)I2C0_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) - -/* CAN Peripheral_declaration */ -#define CAN0 ((CAN_TypeDef *)CAN0_BASE) - -/* DMA Peripheral_declaration */ -#define DMA0 ((DMA_TypeDef *)DMA0_BASE) - -/* UART Peripheral_declaration */ -#define USART0 ((USART_TypeDef *)USART0_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define UART0 ((UART_TypeDef *)UART0_BASE) -#define UART1 ((UART_TypeDef *)UART1_BASE) -#define UART2 ((UART_TypeDef *)UART2_BASE) -#define UART3 ((UART_TypeDef *)UART3_BASE) -#define LPTIM0 ((LPTIM_TypeDef *)LPTIM0_BASE) -#define LPUART0 ((LPUART_TypeDef *)LPUART0_BASE) -#define DBGC ((DBGC_TypeDef *)DBGC_BASE) -#define WWDT ((WWDT_TypeDef *)WWDT_BASE) -#define IWDT ((IWDT_TypeDef *)IWDT_BASE) - -#define SYSCFG ((SYSCFG_TypeDef *)SYSCFG_BASE) -#define CMU ((CMU_TypeDef *)CMU_BASE) -#define RMU ((RMU_TypeDef *)RMU_BASE) -#define PMU ((PMU_TypeDef *)PMU_BASE) -#define MSC ((MSC_TypeDef *)MSC_BASE) - -#endif diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h b/bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h deleted file mode 100644 index b4ac4c7b05a799590575c0b5c8e24c51748ee20b..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1763 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h b/bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h deleted file mode 100644 index dc840ebf2221382b8ca8e9ed8ce72b99e4027ad1..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1937 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h b/bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h deleted file mode 100644 index 3b7530ad505b57d283cc6f07e7f51b9a54be9a0b..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2512 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) - { - return 2UL; /* Double + Single precision FPU */ - } - else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) - { - return 1UL; /* Single precision FPU */ - } - else - { - return 0UL; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/es32f0654/libraries/CMSIS/RTOS/Template/cmsis_os.h b/bsp/es32f0654/libraries/CMSIS/RTOS/Template/cmsis_os.h deleted file mode 100644 index 02930af3e61a20ac95d8d52c23ceb923a9d99c23..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/CMSIS/RTOS/Template/cmsis_os.h +++ /dev/null @@ -1,707 +0,0 @@ -/* ---------------------------------------------------------------------- - * $Date: 5. February 2013 - * $Revision: V1.02 - * - * Project: CMSIS-RTOS API - * Title: cmsis_os.h template header file - * - * Version 0.02 - * Initial Proposal Phase - * Version 0.03 - * osKernelStart added, optional feature: main started as thread - * osSemaphores have standard behavior - * osTimerCreate does not start the timer, added osTimerStart - * osThreadPass is renamed to osThreadYield - * Version 1.01 - * Support for C++ interface - * - const attribute removed from the osXxxxDef_t typedef's - * - const attribute added to the osXxxxDef macros - * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete - * Added: osKernelInitialize - * Version 1.02 - * Control functions for short timeouts in microsecond resolution: - * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec - * Removed: osSignalGet - *---------------------------------------------------------------------------- - * - * Copyright (c) 2013 ARM LIMITED - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------*/ - - -#ifndef _CMSIS_OS_H -#define _CMSIS_OS_H - -/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. -#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) - -/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. -#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) - -/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. -#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string - -/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. -#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available -#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available -#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available -#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available -#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread -#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function -#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available -#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available - -#include -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - - -// ==== Enumeration, structures, defines ==== - -/// Priority used for thread control. -/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. -typedef enum { - osPriorityIdle = -3, ///< priority: idle (lowest) - osPriorityLow = -2, ///< priority: low - osPriorityBelowNormal = -1, ///< priority: below normal - osPriorityNormal = 0, ///< priority: normal (default) - osPriorityAboveNormal = +1, ///< priority: above normal - osPriorityHigh = +2, ///< priority: high - osPriorityRealtime = +3, ///< priority: realtime (highest) - osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority -} osPriority; - -/// Timeout value. -/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. -#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value - -/// Status code values returned by CMSIS-RTOS functions. -/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. -typedef enum { - osOK = 0, ///< function completed; no error or event occurred. - osEventSignal = 0x08, ///< function completed; signal event occurred. - osEventMessage = 0x10, ///< function completed; message event occurred. - osEventMail = 0x20, ///< function completed; mail event occurred. - osEventTimeout = 0x40, ///< function completed; timeout occurred. - osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. - osErrorResource = 0x81, ///< resource not available: a specified resource was not available. - osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. - osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. - osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. - osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. - osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. - osErrorValue = 0x86, ///< value of a parameter is out of range. - osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. - os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. -} osStatus; - - -/// Timer type value for the timer definition. -/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. -typedef enum { - osTimerOnce = 0, ///< one-shot timer - osTimerPeriodic = 1 ///< repeating timer -} os_timer_type; - -/// Entry point of a thread. -/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. -typedef void (*os_pthread) (void const *argument); - -/// Entry point of a timer call back function. -/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. -typedef void (*os_ptimer) (void const *argument); - -// >>> the following data type definitions may shall adapted towards a specific RTOS - -/// Thread ID identifies the thread (pointer to a thread control block). -/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_thread_cb *osThreadId; - -/// Timer ID identifies the timer (pointer to a timer control block). -/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_timer_cb *osTimerId; - -/// Mutex ID identifies the mutex (pointer to a mutex control block). -/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_mutex_cb *osMutexId; - -/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). -/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_semaphore_cb *osSemaphoreId; - -/// Pool ID identifies the memory pool (pointer to a memory pool control block). -/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_pool_cb *osPoolId; - -/// Message ID identifies the message queue (pointer to a message queue control block). -/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_messageQ_cb *osMessageQId; - -/// Mail ID identifies the mail queue (pointer to a mail queue control block). -/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_mailQ_cb *osMailQId; - - -/// Thread Definition structure contains startup information of a thread. -/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. -typedef struct os_thread_def { - os_pthread pthread; ///< start address of thread function - osPriority tpriority; ///< initial thread priority - uint32_t instances; ///< maximum number of instances of that thread function - uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size -} osThreadDef_t; - -/// Timer Definition structure contains timer parameters. -/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. -typedef struct os_timer_def { - os_ptimer ptimer; ///< start address of a timer function -} osTimerDef_t; - -/// Mutex Definition structure contains setup information for a mutex. -/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. -typedef struct os_mutex_def { - uint32_t dummy; ///< dummy value. -} osMutexDef_t; - -/// Semaphore Definition structure contains setup information for a semaphore. -/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. -typedef struct os_semaphore_def { - uint32_t dummy; ///< dummy value. -} osSemaphoreDef_t; - -/// Definition structure for memory block allocation. -/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. -typedef struct os_pool_def { - uint32_t pool_sz; ///< number of items (elements) in the pool - uint32_t item_sz; ///< size of an item - void *pool; ///< pointer to memory for pool -} osPoolDef_t; - -/// Definition structure for message queue. -/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. -typedef struct os_messageQ_def { - uint32_t queue_sz; ///< number of elements in the queue - uint32_t item_sz; ///< size of an item - void *pool; ///< memory array for messages -} osMessageQDef_t; - -/// Definition structure for mail queue. -/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. -typedef struct os_mailQ_def { - uint32_t queue_sz; ///< number of elements in the queue - uint32_t item_sz; ///< size of an item - void *pool; ///< memory array for mail -} osMailQDef_t; - -/// Event structure contains detailed information about an event. -/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. -/// However the struct may be extended at the end. -typedef struct { - osStatus status; ///< status code: event or error information - union { - uint32_t v; ///< message as 32-bit value - void *p; ///< message or mail as void pointer - int32_t signals; ///< signal flags - } value; ///< event value - union { - osMailQId mail_id; ///< mail id obtained by \ref osMailCreate - osMessageQId message_id; ///< message id obtained by \ref osMessageCreate - } def; ///< event definition -} osEvent; - - -// ==== Kernel Control Functions ==== - -/// Initialize the RTOS Kernel for creating objects. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. -osStatus osKernelInitialize (void); - -/// Start the RTOS Kernel. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. -osStatus osKernelStart (void); - -/// Check if the RTOS kernel is already started. -/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. -/// \return 0 RTOS is not started, 1 RTOS is started. -int32_t osKernelRunning(void); - -#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available - -/// Get the RTOS kernel system timer counter -/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. -/// \return RTOS kernel system timer as 32-bit value -uint32_t osKernelSysTick (void); - -/// The RTOS kernel system timer frequency in Hz -/// \note Reflects the system timer setting and is typically defined in a configuration file. -#define osKernelSysTickFrequency 100000000 - -/// Convert a microseconds value to a RTOS kernel system timer value. -/// \param microsec time value in microseconds. -/// \return time value normalized to the \ref osKernelSysTickFrequency -#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) - -#endif // System Timer available - -// ==== Thread Management ==== - -/// Create a Thread Definition with function, priority, and stack requirements. -/// \param name name of the thread function. -/// \param priority initial priority of the thread function. -/// \param instances number of possible thread instances. -/// \param stacksz stack size (in bytes) requirements for the thread function. -/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osThreadDef(name, priority, instances, stacksz) \ -extern const osThreadDef_t os_thread_def_##name -#else // define the object -#define osThreadDef(name, priority, instances, stacksz) \ -const osThreadDef_t os_thread_def_##name = \ -{ (name), (priority), (instances), (stacksz) } -#endif - -/// Access a Thread definition. -/// \param name name of the thread definition object. -/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osThread(name) \ -&os_thread_def_##name - -/// Create a thread and add it to Active Threads and set it to state READY. -/// \param[in] thread_def thread definition referenced with \ref osThread. -/// \param[in] argument pointer that is passed to the thread function as start argument. -/// \return thread ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. -osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); - -/// Return the thread ID of the current running thread. -/// \return thread ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. -osThreadId osThreadGetId (void); - -/// Terminate execution of a thread and remove it from Active Threads. -/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. -osStatus osThreadTerminate (osThreadId thread_id); - -/// Pass control to next thread that is in state \b READY. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. -osStatus osThreadYield (void); - -/// Change priority of an active thread. -/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. -/// \param[in] priority new priority value for the thread function. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. -osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); - -/// Get current priority of an active thread. -/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. -/// \return current priority value of the thread function. -/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. -osPriority osThreadGetPriority (osThreadId thread_id); - - -// ==== Generic Wait Functions ==== - -/// Wait for Timeout (Time Delay). -/// \param[in] millisec time delay value -/// \return status code that indicates the execution status of the function. -osStatus osDelay (uint32_t millisec); - -#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available - -/// Wait for Signal, Message, Mail, or Timeout. -/// \param[in] millisec timeout value or 0 in case of no time-out -/// \return event that contains signal, message, or mail information or error code. -/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. -osEvent osWait (uint32_t millisec); - -#endif // Generic Wait available - - -// ==== Timer Management Functions ==== -/// Define a Timer object. -/// \param name name of the timer object. -/// \param function name of the timer call back function. -/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osTimerDef(name, function) \ -extern const osTimerDef_t os_timer_def_##name -#else // define the object -#define osTimerDef(name, function) \ -const osTimerDef_t os_timer_def_##name = \ -{ (function) } -#endif - -/// Access a Timer definition. -/// \param name name of the timer object. -/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osTimer(name) \ -&os_timer_def_##name - -/// Create a timer. -/// \param[in] timer_def timer object referenced with \ref osTimer. -/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. -/// \param[in] argument argument to the timer call back function. -/// \return timer ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. -osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); - -/// Start or restart a timer. -/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. -/// \param[in] millisec time delay value of the timer. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. -osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); - -/// Stop the timer. -/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. -osStatus osTimerStop (osTimerId timer_id); - -/// Delete a timer that was created by \ref osTimerCreate. -/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. -osStatus osTimerDelete (osTimerId timer_id); - - -// ==== Signal Management ==== - -/// Set the specified Signal Flags of an active thread. -/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. -/// \param[in] signals specifies the signal flags of the thread that should be set. -/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. -/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. -int32_t osSignalSet (osThreadId thread_id, int32_t signals); - -/// Clear the specified Signal Flags of an active thread. -/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. -/// \param[in] signals specifies the signal flags of the thread that shall be cleared. -/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. -/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. -int32_t osSignalClear (osThreadId thread_id, int32_t signals); - -/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. -/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. -/// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return event flag information or error code. -/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. -osEvent osSignalWait (int32_t signals, uint32_t millisec); - - -// ==== Mutex Management ==== - -/// Define a Mutex. -/// \param name name of the mutex object. -/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osMutexDef(name) \ -extern const osMutexDef_t os_mutex_def_##name -#else // define the object -#define osMutexDef(name) \ -const osMutexDef_t os_mutex_def_##name = { 0 } -#endif - -/// Access a Mutex definition. -/// \param name name of the mutex object. -/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osMutex(name) \ -&os_mutex_def_##name - -/// Create and Initialize a Mutex object. -/// \param[in] mutex_def mutex definition referenced with \ref osMutex. -/// \return mutex ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. -osMutexId osMutexCreate (const osMutexDef_t *mutex_def); - -/// Wait until a Mutex becomes available. -/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. -osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); - -/// Release a Mutex that was obtained by \ref osMutexWait. -/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. -osStatus osMutexRelease (osMutexId mutex_id); - -/// Delete a Mutex that was created by \ref osMutexCreate. -/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. -osStatus osMutexDelete (osMutexId mutex_id); - - -// ==== Semaphore Management Functions ==== - -#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available - -/// Define a Semaphore object. -/// \param name name of the semaphore object. -/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osSemaphoreDef(name) \ -extern const osSemaphoreDef_t os_semaphore_def_##name -#else // define the object -#define osSemaphoreDef(name) \ -const osSemaphoreDef_t os_semaphore_def_##name = { 0 } -#endif - -/// Access a Semaphore definition. -/// \param name name of the semaphore object. -/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osSemaphore(name) \ -&os_semaphore_def_##name - -/// Create and Initialize a Semaphore object used for managing resources. -/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. -/// \param[in] count number of available resources. -/// \return semaphore ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. -osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); - -/// Wait until a Semaphore token becomes available. -/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return number of available tokens, or -1 in case of incorrect parameters. -/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. -int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); - -/// Release a Semaphore token. -/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. -osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); - -/// Delete a Semaphore that was created by \ref osSemaphoreCreate. -/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. -osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); - -#endif // Semaphore available - - -// ==== Memory Pool Management Functions ==== - -#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available - -/// \brief Define a Memory Pool. -/// \param name name of the memory pool. -/// \param no maximum number of blocks (objects) in the memory pool. -/// \param type data type of a single block (object). -/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osPoolDef(name, no, type) \ -extern const osPoolDef_t os_pool_def_##name -#else // define the object -#define osPoolDef(name, no, type) \ -const osPoolDef_t os_pool_def_##name = \ -{ (no), sizeof(type), NULL } -#endif - -/// \brief Access a Memory Pool definition. -/// \param name name of the memory pool -/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osPool(name) \ -&os_pool_def_##name - -/// Create and Initialize a memory pool. -/// \param[in] pool_def memory pool definition referenced with \ref osPool. -/// \return memory pool ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. -osPoolId osPoolCreate (const osPoolDef_t *pool_def); - -/// Allocate a memory block from a memory pool. -/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. -/// \return address of the allocated memory block or NULL in case of no memory available. -/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. -void *osPoolAlloc (osPoolId pool_id); - -/// Allocate a memory block from a memory pool and set memory block to zero. -/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. -/// \return address of the allocated memory block or NULL in case of no memory available. -/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. -void *osPoolCAlloc (osPoolId pool_id); - -/// Return an allocated memory block back to a specific memory pool. -/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. -/// \param[in] block address of the allocated memory block that is returned to the memory pool. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. -osStatus osPoolFree (osPoolId pool_id, void *block); - -#endif // Memory Pool Management available - - -// ==== Message Queue Management Functions ==== - -#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available - -/// \brief Create a Message Queue Definition. -/// \param name name of the queue. -/// \param queue_sz maximum number of messages in the queue. -/// \param type data type of a single message element (for debugger). -/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osMessageQDef(name, queue_sz, type) \ -extern const osMessageQDef_t os_messageQ_def_##name -#else // define the object -#define osMessageQDef(name, queue_sz, type) \ -const osMessageQDef_t os_messageQ_def_##name = \ -{ (queue_sz), sizeof (type) } -#endif - -/// \brief Access a Message Queue Definition. -/// \param name name of the queue -/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osMessageQ(name) \ -&os_messageQ_def_##name - -/// Create and Initialize a Message Queue. -/// \param[in] queue_def queue definition referenced with \ref osMessageQ. -/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. -/// \return message queue ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. -osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); - -/// Put a Message to a Queue. -/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. -/// \param[in] info message information. -/// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. -osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); - -/// Get a Message or Wait for a Message from a Queue. -/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return event information that includes status code. -/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. -osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); - -#endif // Message Queues available - - -// ==== Mail Queue Management Functions ==== - -#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available - -/// \brief Create a Mail Queue Definition. -/// \param name name of the queue -/// \param queue_sz maximum number of messages in queue -/// \param type data type of a single message element -/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osMailQDef(name, queue_sz, type) \ -extern const osMailQDef_t os_mailQ_def_##name -#else // define the object -#define osMailQDef(name, queue_sz, type) \ -const osMailQDef_t os_mailQ_def_##name = \ -{ (queue_sz), sizeof (type) } -#endif - -/// \brief Access a Mail Queue Definition. -/// \param name name of the queue -/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osMailQ(name) \ -&os_mailQ_def_##name - -/// Create and Initialize mail queue. -/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ -/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. -/// \return mail queue ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. -osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); - -/// Allocate a memory block from a mail. -/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out -/// \return pointer to memory block that can be filled with mail or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. -void *osMailAlloc (osMailQId queue_id, uint32_t millisec); - -/// Allocate a memory block from a mail and set memory block to zero. -/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out -/// \return pointer to memory block that can be filled with mail or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. -void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); - -/// Put a mail to a queue. -/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. -/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. -osStatus osMailPut (osMailQId queue_id, void *mail); - -/// Get a mail from a queue. -/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out -/// \return event that contains mail information or error code. -/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. -osEvent osMailGet (osMailQId queue_id, uint32_t millisec); - -/// Free a memory block from a mail. -/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. -/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. -osStatus osMailFree (osMailQId queue_id, void *mail); - -#endif // Mail Queues available - - -#ifdef __cplusplus -} -#endif - -#endif // _CMSIS_OS_H diff --git a/bsp/es32f0654/libraries/CMSIS/index.html b/bsp/es32f0654/libraries/CMSIS/index.html deleted file mode 100644 index c6da0802b47f310a1c6ae260189b80a126f0a3bb..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/CMSIS/index.html +++ /dev/null @@ -1,14 +0,0 @@ - - - -Redirect to the CMSIS main page after 0 seconds - - - - - - -If the automatic redirection is failing, click open CMSIS Documentation. - - - diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h deleted file mode 100644 index 8c39f28af2e318c32c2f04789b94e86565fc83eb..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h +++ /dev/null @@ -1,374 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_acmp.h - * @brief Header file of ACMP module driver. - * - * @version V1.0 - * @date 13 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_ACMP_H__ -#define __ALD_ACMP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup ACMP - * @{ - */ - -/** @defgroup ACMP_Public_Types ACMP Public Types - * @{ - */ - -/** - * @brief Acmp interrupt - */ -typedef enum -{ - ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ - ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ -} acmp_it_t; - -/** - * @brief Acmp interrupt - */ -typedef enum -{ - ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ - ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ -} acmp_flag_t; - -/** - * @brief Acmp interrupt flag - */ -typedef enum -{ - ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */ - ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */ -} acmp_status_t; - -/** - * @brief Acmp positive input - */ -typedef enum -{ - ACMP_POS_CH0 = 0, /**< Channel 0 as positive input */ - ACMP_POS_CH1 = 1, /**< Channel 1 as positive input */ - ACMP_POS_CH2 = 2, /**< Channel 2 as positive input */ - ACMP_POS_CH3 = 3, /**< Channel 3 as positive input */ - ACMP_POS_CH4 = 4, /**< Channel 4 as positive input */ - ACMP_POS_CH5 = 5, /**< Channel 5 as positive input */ - ACMP_POS_CH6 = 6, /**< Channel 6 as positive input */ - ACMP_POS_CH7 = 7, /**< Channel 7 as positive input */ -} acmp_pos_input_t; - -/** - * @brief Acmp negative input - */ -typedef enum -{ - ACMP_NEG_CH0 = 0, /**< Channel 0 as negative input */ - ACMP_NEG_CH1 = 1, /**< Channel 1 as negative input */ - ACMP_NEG_CH2 = 2, /**< Channel 2 as negative input */ - ACMP_NEG_CH3 = 3, /**< Channel 3 as negative input */ - ACMP_NEG_CH4 = 4, /**< Channel 4 as negative input */ - ACMP_NEG_CH5 = 5, /**< Channel 5 as negative input */ - ACMP_NEG_CH6 = 6, /**< Channel 6 as negative input */ - ACMP_NEG_CH7 = 7, /**< Channel 7 as negative input */ - ACMP_NEG_1V25 = 8, /**< 1.25v as negative input */ - ACMP_NEG_2V5 = 9, /**< 2.5v as negative input */ - ACMP_NEG_VDD = 10, /**< VDD as negative input */ - ACMP_NEG_CAP = 11, /**< Capacitive as negative input */ - ACMP_NEG_DAC0_CH0 = 12, /**< DAC0 channel 0 as negative input */ - ACMP_NEG_DAC0_CH1 = 13, /**< DAC0 channel 1 as negative input */ -} acmp_neg_input_t; - -/** - * @brief Acmp mode - */ -typedef enum -{ - ACMP_ULTRA_LOW_POWER = 0, /**< Ultra low power mode */ - ACMP_LOW_POWER = 1, /**< Low power mode */ - ACMP_MIDDLE_POWER = 2, /**< Middle power mode */ - ACMP_HIGH_POWER = 3, /**< High power mode */ -} acmp_mode_t; - -/** - * @brief Acmp warm-up time - */ -typedef enum -{ - ACMP_4_PCLK = 0, /**< 4 hfperclk cycles */ - ACMP_8_PCLK = 1, /**< 4 hfperclk cycles */ - ACMP_16_PCLK = 2, /**< 4 hfperclk cycles */ - ACMP_32_PCLK = 3, /**< 4 hfperclk cycles */ - ACMP_64_PCLK = 4, /**< 4 hfperclk cycles */ - ACMP_128_PCLK = 5, /**< 4 hfperclk cycles */ - ACMP_256_PCLK = 6, /**< 4 hfperclk cycles */ - ACMP_512_PCLK = 7, /**< 4 hfperclk cycles */ -} acmp_warm_time_t; - -/** - * @brief Acmp hysteresis level - */ -typedef enum -{ - ACMP_HYST_0 = 0, /**< No hysteresis */ - ACMP_HYST_15 = 1, /**< 15mV hysteresis */ - ACMP_HYST_22 = 2, /**< 22mV hysteresis */ - ACMP_HYST_29 = 3, /**< 29mV hysteresis */ - ACMP_HYST_36 = 4, /**< 36mV hysteresis */ - ACMP_HYST_43 = 5, /**< 43mV hysteresis */ - ACMP_HYST_50 = 6, /**< 50mV hysteresis */ - ACMP_HYST_57 = 7, /**< 57mV hysteresis */ -} acmp_hystsel_t; - -/** - * @brief Acmp inactive state - */ -typedef enum -{ - ACMP_INACTVAL_LOW = 0, /**< The inactive value is 0 */ - ACMP_INACTVAL_HIGH = 1, /**< The inactive value is 1 */ -} acmp_inactval_t; - -/** - * @brief which edges set up interrupt - */ -typedef enum -{ - ACMP_EDGE_NONE = 0, /**< Disable EDGE interrupt */ - ACMP_EDGE_FALL = 1, /**< Falling edges set EDGE interrupt */ - ACMP_EDGE_RISE = 2, /**< rise edges set EDGE interrupt */ - ACMP_EDGE_ALL = 3, /**< Falling edges and rise edges set EDGE interrupt */ -} acmp_edge_t; - -/** - * @brief Acmp output function - */ -typedef enum -{ - ACMP_OUT_DISABLE = 0, /**< Disable acmp output */ - ACMP_OUT_ENABLE = 1, /**< Enable acmp output */ -} acmp_out_func_t; - -/** - * @brief Acmp warm-up interrupt function - */ -typedef enum -{ - ACMP_WARM_DISABLE = 0, /**< Disable acmp warm-up interrupt */ - ACMP_WARM_ENABLE = 1, /**< Enable acmp warm-up interrupt */ -} acmp_warm_it_func; - -/** - * @brief Acmp gpio output invert - */ -typedef enum -{ - ACMP_GPIO_NO_INV = 0, /**< Acmp output to gpio is not inverted */ - ACMP_GPIO_INV = 1, /**< Acmp output to gpio is inverted */ -} acmp_invert_t; - -/** - * @brief The location of the acmp i/o pin - */ -typedef enum -{ - ACMP_LOCATION_O = 0, /**< Location 0 */ - ACMP_LOCATION_1 = 1, /**< Location 1 */ - ACMP_LOCATION_2 = 2, /**< Location 2 */ -} acmp_location_t; - -/** - * @brief Acmp output config structure definition - */ -typedef struct -{ - acmp_out_func_t out_func; /**< Acmp output function */ - acmp_invert_t gpio_inv; /**< If invert gpio output */ - acmp_location_t location; /**< The location of acmp I/0 pin */ -} acmp_output_config_t; - -/** - * @brief Acmp init structure definition - */ -typedef struct -{ - acmp_mode_t mode; /**< Acmp operation mode */ - acmp_warm_time_t warm_time; /**< Acmp warm up time */ - acmp_hystsel_t hystsel; /**< Acmp hysteresis level */ - acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */ - acmp_pos_input_t pos_port; /**< Acmp positive port select */ - acmp_neg_input_t neg_port; /**< Acmp negative port select */ - acmp_inactval_t inactval; /**< Acmp inavtive output value */ - acmp_edge_t edge; /** Select edges to set interrupt flag */ - uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */ -} acmp_init_t; - -/** - * @brief ACMP Handle Structure definition - */ -typedef struct acmp_handle_s -{ - ACMP_TypeDef *perh; /**< Register base address */ - acmp_init_t init; /**< ACMP required parameters */ - lock_state_t lock; /**< Locking object */ - - void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */ - void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */ -} acmp_handle_t; -/** - * @} - */ - -/** @defgroup ACMP_Public_Macros ACMP Public Macros - * @{ - */ -#define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) -#define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) -/** - * @} - */ - -/** @defgroup ACMP_Private_Macros ACMP Private Macros - * @{ - */ -#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \ - ((x) == ACMP1)) -#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \ - ((x) == ACMP_LOW_POWER) || \ - ((x) == ACMP_MIDDLE_POWER) || \ - ((x) == ACMP_HIGH_POWER)) -#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \ - ((x) == ACMP_IT_WARMUP)) -#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \ - ((x) == ACMP_FLAG_WARMUP)) -#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \ - ((x) == ACMP_STATUS_WARMUP)) -#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \ - ((x) == ACMP_POS_CH1) || \ - ((x) == ACMP_POS_CH2) || \ - ((x) == ACMP_POS_CH3) || \ - ((x) == ACMP_POS_CH4) || \ - ((x) == ACMP_POS_CH5) || \ - ((x) == ACMP_POS_CH6) || \ - ((x) == ACMP_POS_CH7)) -#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \ - ((x) == ACMP_NEG_CH1) || \ - ((x) == ACMP_NEG_CH2) || \ - ((x) == ACMP_NEG_CH3) || \ - ((x) == ACMP_NEG_CH4) || \ - ((x) == ACMP_NEG_CH5) || \ - ((x) == ACMP_NEG_CH6) || \ - ((x) == ACMP_NEG_CH7) || \ - ((x) == ACMP_NEG_1V25) || \ - ((x) == ACMP_NEG_2V5) || \ - ((x) == ACMP_NEG_VDD) || \ - ((x) == ACMP_NEG_CAP) || \ - ((x) == ACMP_NEG_DAC0_CH0) || \ - ((x) == ACMP_NEG_DAC0_CH1)) -#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \ - ((x) == ACMP_8_PCLK) || \ - ((x) == ACMP_16_PCLK) || \ - ((x) == ACMP_32_PCLK) || \ - ((x) == ACMP_64_PCLK) || \ - ((x) == ACMP_128_PCLK) || \ - ((x) == ACMP_256_PCLK) || \ - ((x) == ACMP_512_PCLK)) -#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \ - ((x) == ACMP_HYST_15) || \ - ((x) == ACMP_HYST_22) || \ - ((x) == ACMP_HYST_29) || \ - ((x) == ACMP_HYST_36) || \ - ((x) == ACMP_HYST_43) || \ - ((x) == ACMP_HYST_50) || \ - ((x) == ACMP_HYST_57)) -#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \ - ((x) == ACMP_INACTVAL_HIGH)) -#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \ - ((x) == ACMP_EDGE_FALL) || \ - ((x) == ACMP_EDGE_RISE) || \ - ((x) == ACMP_EDGE_ALL)) -#define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \ - ((x) == ACMP_OUT_ENABLE)) -#define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \ - ((x) == ACMP_GPIO_INV)) -#define IS_ACMP_LOCATION_TYPE(x) (((x) == ACMP_LOCATION_O) || \ - ((x) == ACMP_LOCATION_1) || \ - ((x) == ACMP_LOCATION_2)) -#define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \ - ((x) == ACMP_WARM_ENABLE)) -/** - * @} - */ - -/** @addtogroup ACMP_Public_Functions - * @{ - */ - -/** @addtogroup ACMP_Public_Functions_Group1 - * @{ - */ -ald_status_t acmp_init(acmp_handle_t *hperh); - -/** - * @} - */ - -/** @addtogroup ACMP_Public_Functions_Group2 - * @{ - */ -ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state); -ald_status_t acmp_set_interrupt_mask(acmp_handle_t *hperh, acmp_it_t it); -it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t it); -ald_status_t acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t it); -flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t flag); - -/** - * @} - */ - -/** @addtogroup ACMP_Public_Functions_Group3 - * @{ - */ -void acmp_irq_handle(acmp_handle_t *hperh); -ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config); -uint8_t acmp_out_result(acmp_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -extern "C" -} -#endif - -#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h deleted file mode 100644 index b4f4f029d13e737bc324e90837a3d1b42d197697..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h +++ /dev/null @@ -1,585 +0,0 @@ -/** - ****************************************************************************** - * @file ald_adc.h - * @brief Header file of ADC Module library. - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ****************************************************************************** - */ - -#ifndef __ALD_ADC_H__ -#define __ALD_ADC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" -#include "ald_pis.h" -#include "ald_timer.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Pubulic_Types ADC Pubulic Types - * @{ - */ - -/** - * @brief ADC State structures definition - */ -typedef enum -{ - ADC_STATE_RESET = 0x0, /**< ADC not yet initialized or disabled */ - ADC_STATE_READY = 0x1, /**< ADC peripheral ready for use */ - ADC_STATE_BUSY_INTERNAL = 0x2, /**< ADC is busy to internal process */ - ADC_STATE_TIMEOUT = 0x4, /**< TimeOut occurrence */ - ADC_STATE_ERROR = 0x10, /**< Internal error occurrence */ - ADC_STATE_NM_BUSY = 0x100, /**< Conversion on group normal is ongoing or can occur */ - ADC_STATE_NM_EOC = 0x200, /**< Conversion data available on group normal */ - ADC_STATE_IST_BUSY = 0x1000, /**< Conversion on group insert is ongoing or can occur */ - ADC_STATE_IST_EOC = 0x2000, /**< Conversion data available on group insert */ - ADC_STATE_AWD = 0x10000, /**< Out-of-window occurrence of analog watchdog */ -} adc_state_t; - -/** - *@brief ADC Error Code - */ -typedef enum -{ - ADC_ERROR_NONE = 0x0, /**< No error */ - ADC_ERROR_INTERNAL = 0x1, /**< ADC IP internal error*/ - ADC_ERROR_OVR = 0x2, /**< Overrun error */ - ADC_ERROR_DMA = 0x4, /**< DMA transfer error */ -} adc_error_t; - -/** - *@brief ADC data alignment - */ -typedef enum -{ - ADC_DATAALIGN_RIGHT = 0x0, /**< ADC data alignment right */ - ADC_DATAALIGN_LEFT = 0x1, /**< ADC data alignment left */ -} adc_align_t; - -/** - *@brief ADC scan mode - */ -typedef enum -{ - ADC_SCAN_DISABLE = 0x0, /**< ADC scan disable */ - ADC_SCAN_ENABLE = 0x1, /**< ADC scan enable */ -} adc_scan_t; - -/** - *@brief ADC config hannal trigger the EOC IT mode - */ -typedef enum -{ - ADC_NCHESEL_MODE_ALL = 0x0, /**< ADC set RCHE after convert sequence finish */ - ADC_NCHESEL_MODE_ONE = 0x1, /**< ADC set RCHE after one convert finish */ -} adc_nchesel_t; - -/** - *@brief ADC channels - */ -typedef enum -{ - ADC_CHANNEL_0 = 0x0, /**< ADC channel 0 */ - ADC_CHANNEL_1 = 0x1, /**< ADC channel 1 */ - ADC_CHANNEL_2 = 0x2, /**< ADC channel 2 */ - ADC_CHANNEL_3 = 0x3, /**< ADC channel 3 */ - ADC_CHANNEL_4 = 0x4, /**< ADC channel 4 */ - ADC_CHANNEL_5 = 0x5, /**< ADC channel 5 */ - ADC_CHANNEL_6 = 0x6, /**< ADC channel 6 */ - ADC_CHANNEL_7 = 0x7, /**< ADC channel 7 */ - ADC_CHANNEL_8 = 0x8, /**< ADC channel 8 */ - ADC_CHANNEL_9 = 0x9, /**< ADC channel 9 */ - ADC_CHANNEL_10 = 0xA, /**< ADC channel 10 */ - ADC_CHANNEL_11 = 0xB, /**< ADC channel 11 */ - ADC_CHANNEL_12 = 0xC, /**< ADC channel 12 */ - ADC_CHANNEL_13 = 0xD, /**< ADC channel 13 */ - ADC_CHANNEL_14 = 0xE, /**< ADC channel 14 */ - ADC_CHANNEL_15 = 0xF, /**< ADC channel 15 */ - ADC_CHANNEL_16 = 0x10, /**< ADC channel 16 */ - ADC_CHANNEL_17 = 0x11, /**< ADC channel 17 */ - ADC_CHANNEL_18 = 0x12, /**< ADC channel 18 */ - ADC_CHANNEL_19 = 0x13, /**< ADC channel 19 */ -} adc_channel_t; - -/** - *@brief ADC sampling times - */ -typedef enum -{ - ADC_SAMPLETIME_1 = 0x0, /**< ADC sampling times 1 clk */ - ADC_SAMPLETIME_2 = 0x1, /**< ADC sampling times 2 clk */ - ADC_SAMPLETIME_4 = 0x2, /**< ADC sampling times 4 clk */ - ADC_SAMPLETIME_15 = 0x3, /**< ADC sampling times 15 clk */ -} adc_samp_t; - -/** - *@brief ADC rank into normal group - */ -typedef enum -{ - ADC_NC_RANK_1 = 0x1, /**< ADC normal channel rank 1 */ - ADC_NC_RANK_2 = 0x2, /**< ADC normal channel rank 2 */ - ADC_NC_RANK_3 = 0x3, /**< ADC normal channel rank 3 */ - ADC_NC_RANK_4 = 0x4, /**< ADC normal channel rank 4 */ - ADC_NC_RANK_5 = 0x5, /**< ADC normal channel rank 5 */ - ADC_NC_RANK_6 = 0x6, /**< ADC normal channel rank 6 */ - ADC_NC_RANK_7 = 0x7, /**< ADC normal channel rank 7 */ - ADC_NC_RANK_8 = 0x8, /**< ADC normal channel rank 8 */ - ADC_NC_RANK_9 = 0x9, /**< ADC normal channel rank 9 */ - ADC_NC_RANK_10 = 0xA, /**< ADC normal channel rank 10 */ - ADC_NC_RANK_11 = 0xB, /**< ADC normal channel rank 11 */ - ADC_NC_RANK_12 = 0xC, /**< ADC normal channel rank 12 */ - ADC_NC_RANK_13 = 0xD, /**< ADC normal channel rank 13 */ - ADC_NC_RANK_14 = 0xE, /**< ADC normal channel rank 14 */ - ADC_NC_RANK_15 = 0xF, /**< ADC normal channel rank 15 */ - ADC_NC_RANK_16 = 0x10, /**< ADC normal channel rank 16 */ -} adc_nc_rank_t; - -/** - * @brief ADC rank into insert group - */ -typedef enum -{ - ADC_IH_RANK_1 = 0x1, /**< ADC insert channel rank 1 */ - ADC_IH_RANK_2 = 0x2, /**< ADC insert channel rank 2 */ - ADC_IH_RANK_3 = 0x3, /**< ADC insert channel rank 3 */ - ADC_IH_RANK_4 = 0x4, /**< ADC insert channel rank 4 */ -} adc_ih_rank_t; - -/** - * @brief ADC analog watchdog mode - */ -typedef enum -{ - ADC_ANAWTD_NONE = 0x0, /**< No watch dog */ - ADC_ANAWTD_SING_NM = 0x800200, /**< One normal channel watch dog */ - ADC_ANAWTD_SING_IST = 0x400200, /**< One inset channel Injec watch dog */ - ADC_ANAWTD_SING_NMIST = 0xC00200, /**< One normal and inset channel watch dog */ - ADC_ANAWTD_ALL_NM = 0x800000, /**< All normal channel watch dog */ - ADC_ANAWTD_ALL_IST = 0x400000, /**< All inset channel watch dog */ - ADC_ANAWTD_ALL_NMIST = 0xC00000, /**< All normal and inset channel watch dog */ -} adc_ana_wtd_t; - -/** - * @brief ADC Event type - */ -typedef enum -{ - ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ -} adc_event_type_t; - -/** - * @brief ADC interrupts definition - */ -typedef enum -{ - ADC_IT_NH = (1U << 5), /**< ADC it normal */ - ADC_IT_AWD = (1U << 6), /**< ADC it awd */ - ADC_IT_IH = (1U << 7), /**< ADC it insert */ - ADC_IT_OVR = (1U << 26), /**< ADC it overring */ -} adc_it_t; - -/** - * @brief ADC flags definition - */ -typedef enum -{ - ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) -#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) -#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) -#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) -#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) -/** - * @} - */ - -/** @defgroup ADC_Private_Macros ADC Private Macros - * @{ - */ -#define IS_ADC_IH_RANK_TYPE(x) ((x) <= ADC_IH_RANK_4) -#define IS_ADC_NC_RANK_TYPE(x) ((x) <= ADC_NC_RANK_16) -#define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \ - ((x) == ADC_SAMPLETIME_2) || \ - ((x) == ADC_SAMPLETIME_4) || \ - ((x) == ADC_SAMPLETIME_15)) -#define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_19) -#define IS_ADC_SCAN_MODE_TYPE(x) (((x) == ADC_SCAN_DISABLE) || \ - ((x) == ADC_SCAN_ENABLE) ) -#define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \ - ((x) == ADC_DATAALIGN_LEFT)) -#define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \ - ((x) == ADC_ANAWTD_SING_NM) || \ - ((x) == ADC_ANAWTD_SING_IST) || \ - ((x) == ADC_ANAWTD_SING_NMIST) || \ - ((x) == ADC_ANAWTD_ALL_NM) || \ - ((x) == ADC_ANAWTD_ALL_IST) || \ - ((x) == ADC_ANAWTD_ALL_NMIST)) -#define IS_ADC_IT_TYPE(x) (((x) == ADC_IT_NH) || \ - ((x) == ADC_IT_AWD) || \ - ((x) == ADC_IT_IH) || \ - ((x) == ADC_IT_OVR )) -#define IS_ADC_FLAGS_TYPE(x) (((x) == ADC_FLAG_AWD) || \ - ((x) == ADC_FLAG_NH) || \ - ((x) == ADC_FLAG_IH) || \ - ((x) == ADC_FLAG_OVR) || \ - ((x) == ADC_FLAG_NHS) || \ - ((x) == ADC_FLAG_IHS)) -#define IS_ADC_CLK_DIV_TYPE(x) (((x) == ADC_CKDIV_1) || \ - ((x) == ADC_CKDIV_2) || \ - ((x) == ADC_CKDIV_4) || \ - ((x) == ADC_CKDIV_8) || \ - ((x) == ADC_CKDIV_16) || \ - ((x) == ADC_CKDIV_32) || \ - ((x) == ADC_CKDIV_64) || \ - ((x) == ADC_CKDIV_128)) -#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \ - ((x) == ADC_NEG_REF_VREFN )) -#define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \ - ((x) == ADC_POS_REF_2V) || \ - ((x) == ADC_POS_REF_VREEFP) || \ - ((x) == ADC_POS_REF_VREEFP_BUF)) -#define IS_ADC_NBR_OF_NM_TYPE(x) ((x) <= ADC_NM_NBR_16) -#define IS_ADC_NBR_OF_IST_TYPE(x) ((x) <= ADC_IST_NBR_4) -#define IS_ADC_DISC_NBR_TYPE(x) ((x) <= ADC_DISC_NBR_8) -#define IS_ADC_CONV_RES_TYPE(x) (((x) == ADC_CONV_RES_12) || \ - ((x) == ADC_CONV_RES_6) || \ - ((x) == ADC_CONV_RES_8) || \ - ((x) == ADC_CONV_RES_10)) -#define IS_ADC_TRIG_MODE_TYPE(x) (((x) == ADC_TRIG_SOFT) || \ - ((x) == ADC_TRIG_PIS) || \ - ((x) == ADC_TRIG_PIS_SOFT)) -#define IS_ADC_TYPE(x) (((x) == ADC0) || \ - ((x) == ADC1)) -#define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \ - ((x) == ADC_NCHESEL_MODE_ONE)) -#define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT) -#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff) -#define IS_HTR_TYPE(x) ((x) <= 0xfff) -#define IS_LTR_TYPE(x) ((x) <= 0xfff) -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions - * @{ - */ - -/** @addtogroup ADC_Public_Functions_Group1 - * @{ - */ -ald_status_t adc_init(adc_handle_t *hperh); -ald_status_t adc_reset(adc_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions_Group2 - * @{ - */ -ald_status_t adc_normal_start(adc_handle_t *hperh); -ald_status_t adc_normal_stop(adc_handle_t *hperh); -ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); -ald_status_t adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout); -ald_status_t adc_normal_start_by_it(adc_handle_t *hperh); -ald_status_t adc_normal_stop_by_it(adc_handle_t *hperh); -#ifdef ALD_DMA -ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); -ald_status_t adc_stop_by_dma(adc_handle_t *hperh); -ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config); -#endif -uint32_t adc_normal_get_value(adc_handle_t *hperh); -ald_status_t adc_insert_start(adc_handle_t *hperh); -ald_status_t adc_insert_stop(adc_handle_t *hperh); -ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); -ald_status_t adc_insert_start_by_it(adc_handle_t *hperh); -ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh); -uint32_t adc_insert_get_value(adc_handle_t *hperh, adc_ih_rank_t ih_rank); -void adc_irq_handler(adc_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions_Group3 - * @{ - */ -ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t *config); -ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *config); -ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config); -void adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state); -it_status_t adc_get_it_status(adc_handle_t *hperh, adc_it_t it); -flag_status_t adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag); -void adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag); -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions_Group4 - * @{ - */ -uint32_t adc_get_state(adc_handle_t *hperh); -uint32_t adc_get_error(adc_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -extern "C" -} -#endif - -#endif /* __ALD_ADC_H */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h deleted file mode 100644 index 67923d9a3a2fe9d48cdbf2a77655e1cb57e644f0..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h +++ /dev/null @@ -1,186 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_bkpc.h - * @brief Header file of BKPC module driver. - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_BKPC_H__ -#define __ALD_BKPC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup BKPC - * @{ - */ - -/** @defgroup BKPC_Public_Macros BKPC Public Macros - * @{ - */ -#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0)) -#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55)) -#define BKPC_LRC_ENABLE() \ -do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LRC_DISABLE() \ -do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSM_ENABLE() \ -do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSM_DISABLE() \ -do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSC_ENABLE() \ -do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSC_DISABLE() \ -do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ - BKPC_LOCK(); \ -} while (0) -/** - * @} - */ - -/** @defgroup BKPC_Public_Types BKPC Public Types - * @{ - */ -/** - * @brief BKPC ldo output select - */ -typedef enum -{ - BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */ - BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */ - BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */ - BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */ -} bkpc_ldo_output_t; - -/** - * @brief BKPC BOR voltage select - */ -typedef enum -{ - BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */ - BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */ - BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */ - BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */ - BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */ - BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */ - BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */ - BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */ - BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */ - BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */ - BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */ - BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */ - BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */ - BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */ - BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */ - BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */ -} bkpc_bor_vol_t; - -/** - * @} - */ - -/** - * @defgroup BKPC_Private_Macros BKPC Private Macros - * @{ - */ -#define IS_BKPC_LDO_OUTPUT(x) (((x) == BKPC_LDO_OUTPUT_1_6) || \ - ((x) == BKPC_LDO_OUTPUT_1_3) || \ - ((x) == BKPC_LDO_OUTPUT_1_4) || \ - ((x) == BKPC_LDO_OUTPUT_1_5)) -#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \ - ((x) == BKPC_BOR_VOL_2_0) || \ - ((x) == BKPC_BOR_VOL_2_1) || \ - ((x) == BKPC_BOR_VOL_2_2) || \ - ((x) == BKPC_BOR_VOL_2_3) || \ - ((x) == BKPC_BOR_VOL_2_4) || \ - ((x) == BKPC_BOR_VOL_2_5) || \ - ((x) == BKPC_BOR_VOL_2_6) || \ - ((x) == BKPC_BOR_VOL_2_8) || \ - ((x) == BKPC_BOR_VOL_3_0) || \ - ((x) == BKPC_BOR_VOL_3_1) || \ - ((x) == BKPC_BOR_VOL_3_3) || \ - ((x) == BKPC_BOR_VOL_3_6) || \ - ((x) == BKPC_BOR_VOL_3_7) || \ - ((x) == BKPC_BOR_VOL_4_0) || \ - ((x) == BKPC_BOR_VOL_4_3)) -#define IS_BKPC_RAM_IDX(x) ((x) < 32) -/** - * @} - */ - -/** @addtogroup BKPC_Public_Functions - * @{ - */ -/** @addtogroup BKPC_Public_Functions_Group1 - * @{ - */ -/* control functions */ -extern void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state); -extern void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state); -/** - * @} - */ -/** @addtogroup BKPC_Public_Functions_Group2 - * @{ - */ -/* IO operation functions */ -extern void bkpc_write_ram(uint8_t idx, uint32_t value); -extern uint32_t bkpc_read_ram(uint8_t idx); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_BKPC_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h deleted file mode 100644 index ebe2e2a479e6c5b0ad29bf96dea38c45cd3e6b27..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h +++ /dev/null @@ -1,485 +0,0 @@ -/** - ****************************************************************************** - * @file ald_can.h - * @brief Header file of CAN Module driver. - * - * @version V1.0 - * @date 16 Apr 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ****************************************************************************** - */ - -#ifndef __ALD_CAN_H -#define __ALD_CAN_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/** @defgroup CAN_Public_Types CAN Public Types - * @{ - */ -/** - * @brief ALD State structures definition - */ -typedef enum -{ - CAN_STATE_RESET = 0x00, /**< CAN not yet initialized or disabled */ - CAN_STATE_READY = 0x01, /**< CAN initialized and ready for use */ - CAN_STATE_BUSY = 0x02, /**< CAN process is ongoing */ - CAN_STATE_BUSY_TX = 0x11, /**< CAN process is ongoing */ - CAN_STATE_BUSY_RX = 0x21, /**< CAN process is ongoing */ - CAN_STATE_BUSY_TX_RX = 0x31, /**< CAN process is ongoing */ - CAN_STATE_TIMEOUT = 0x03, /**< CAN in Timeout state */ - CAN_STATE_ERROR = 0x04, /**< CAN error state */ -} can_state_t; - -/** - * @brief CAN Error Code - */ -typedef enum -{ - CAN_ERROR_NONE = 0x00, /**< No error */ - CAN_ERROR_EWG = 0x01, /**< EWG error */ - CAN_ERROR_EPV = 0x02, /**< EPV error */ - CAN_ERROR_BOF = 0x04, /**< BOF error */ - CAN_ERROR_STF = 0x08, /**< Stuff error */ - CAN_ERROR_FOR = 0x10, /**< Form error */ - CAN_ERROR_ACK = 0x20, /**< Acknowledgment error */ - CAN_ERROR_BR = 0x40, /**< Bit recessive */ - CAN_ERROR_BD = 0x80, /**< LEC dominant */ - CAN_ERROR_CRC = 0x100, /**< LEC transfer error */ -} can_error_t; - -/** - * @brief CAN Operating Mode - */ -typedef enum -{ - CAN_MODE_NORMAL = 0x00, /**< Normal mode */ - CAN_MODE_LOOPBACK = 0x01, /**< Loopback mode */ - CAN_MODE_SILENT = 0x02, /**< Silent mode */ - CAN_MODE_SILENT_LOOPBACK = 0x03, /**< Loopback combined with silent mode */ -} can_operate_mode_t; - -/** - * @brief CAN Synchronization Jump Width - */ -typedef enum -{ - CAN_SJW_1 = 0x0, /**< 1 time quantum */ - CAN_SJW_2 = 0x1, /**< 2 time quantum */ - CAN_SJW_3 = 0x2, /**< 3 time quantum */ - CAN_SJW_4 = 0x3, /**< 4 time quantum */ -} can_sjw_t; - -/** - * @brief CAN Time Quantum in Bit Segment 1 - */ -typedef enum -{ - CAN_SEG1_1 = 0x0, /**< 1 time quantum */ - CAN_SEG1_2 = 0x1, /**< 2 time quantum */ - CAN_SEG1_3 = 0x2, /**< 3 time quantum */ - CAN_SEG1_4 = 0x3, /**< 4 time quantum */ - CAN_SEG1_5 = 0x4, /**< 5 time quantum */ - CAN_SEG1_6 = 0x5, /**< 6 time quantum */ - CAN_SEG1_7 = 0x6, /**< 7 time quantum */ - CAN_SEG1_8 = 0x7, /**< 8 time quantum */ - CAN_SEG1_9 = 0x8, /**< 9 time quantum */ - CAN_SEG1_10 = 0x9, /**< 10 time quantum */ - CAN_SEG1_11 = 0xA, /**< 11 time quantum */ - CAN_SEG1_12 = 0xB, /**< 12 time quantum */ - CAN_SEG1_13 = 0xC, /**< 13 time quantum */ - CAN_SEG1_14 = 0xD, /**< 14 time quantum */ - CAN_SEG1_15 = 0xE, /**< 15 time quantum */ - CAN_SEG1_16 = 0xF, /**< 16 time quantum */ -} can_seg1_t; - -/** - * @brief CAN Time Quantum in Bit Segment 2 - */ -typedef enum -{ - CAN_SEG2_1 = 0x0, /**< 1 time quantum */ - CAN_SEG2_2 = 0x1, /**< 2 time quantum */ - CAN_SEG2_3 = 0x2, /**< 3 time quantum */ - CAN_SEG2_4 = 0x3, /**< 4 time quantum */ - CAN_SEG2_5 = 0x4, /**< 5 time quantum */ - CAN_SEG2_6 = 0x5, /**< 6 time quantum */ - CAN_SEG2_7 = 0x6, /**< 7 time quantum */ - CAN_SEG2_8 = 0x7, /**< 8 time quantum */ -} can_seg2_t; - -/** - * @brief CAN Filter Mode - */ -typedef enum -{ - CAN_FILTER_MODE_MASK = 0x0, /**< Identifier mask mode */ - CAN_FILTER_MODE_LIST = 0x1, /**< Identifier list mode */ -} can_filter_mode_t; - -/** - * @brief CAN Filter Scale - */ -typedef enum -{ - CAN_FILTER_SCALE_16 = 0x0, /**< Two 16-bit filters */ - CAN_FILTER_SCALE_32 = 0x1, /**< One 32-bit filter */ -} can_filter_scale_t; - -/** - * @brief CAN Filter fifo - */ -typedef enum -{ - CAN_FILTER_FIFO0 = 0x0, /**< FIFO 0 assignment for filter */ - CAN_FILTER_FIFO1 = 0x1, /**< FIFO 1 assignment for filter */ -} can_filter_fifo_t; - -/** - * @brief CAN Identifier Type - */ -typedef enum -{ - CAN_ID_STD = 0x0, /**< Standard Id */ - CAN_ID_EXT = 0x1, /**< Extended Id */ -} can_id_type_t; - -/** - * @brief CAN Remote Transmission Request - */ -typedef enum -{ - CAN_RTR_DATA = 0x0, /**< Data frame */ - CAN_RTR_REMOTE = 0x1, /**< Remote frame */ -} can_remote_req_t; - -/** - * @brief CAN Transmit Constants - */ -typedef enum -{ - CAN_TX_MAILBOX_0 = 0x0, /**< TX mailbox index 0 */ - CAN_TX_MAILBOX_1 = 0x1, /**< TX mailbox index 1 */ - CAN_TX_MAILBOX_2 = 0x2, /**< TX mailbox index 2 */ - CAN_TX_MAILBOX_NONE = 0x3, /**< MailBox can't be used */ -} can_tx_mailbox_t; - -/** - * @brief CAN Receive fifo Number - */ -typedef enum -{ - CAN_RX_FIFO0 = 0x0, /**< CAN fifo 0 used to receive */ - CAN_RX_FIFO1 = 0x1, /**< CAN fifo 1 used to receive */ -} can_rx_fifo_t; - -/** - * @brief CAN Flags - */ -typedef enum -{ - CAN_FLAG_SLAK = (1U << 1), /**< Sleep acknowledge flag */ - CAN_FLAG_WKU = (1U << 3), /**< Wake up flag */ - CAN_FLAG_SLAKI = (1U << 4), /**< Sleep acknowledge flag */ - CAN_FLAG_RQCP0 = (1U << 20) | (1U << 0), /**< Request MailBox0 flag */ - CAN_FLAG_TXOK0 = (1U << 20) | (1U << 1), /**< Transmission OK MailBox0 flag */ - CAN_FLAG_RQCP1 = (1U << 20) | (1U << 8), /**< Request MailBox1 flag */ - CAN_FLAG_TXOK1 = (1U << 20) | (1U << 9), /**< Transmission OK MailBox1 flag */ - CAN_FLAG_RQCP2 = (1U << 20) | (1U << 16), /**< Request MailBox2 flag */ - CAN_FLAG_TXOK2 = (1U << 20) | (1U << 17), /**< Transmission OK MailBox2 flag */ - CAN_FLAG_TME0 = (1U << 20) | (1U << 26), /**< Transmit mailbox 0 empty flag */ - CAN_FLAG_TME1 = (1U << 20) | (1U << 27), /**< Transmit mailbox 1 empty flag */ - CAN_FLAG_TME2 = (1U << 20) | (1U << 28), /**< Transmit mailbox 2 empty flag */ - CAN_FLAG_FF0 = (2U << 20) | (1U << 3), /**< FIFO 0 Full flag */ - CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), /**< FIFO 0 Overrun flag */ - CAN_FLAG_FF1 = (3U << 20) | (1U << 3), /**< FIFO 1 Full flag */ - CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), /**< FIFO 1 Overrun flag */ - CAN_FLAG_EWG = (4U << 20) | (1U << 0), /**< Error warning flag */ - CAN_FLAG_EPV = (4U << 20) | (1U << 1), /**< Error passive flag */ - CAN_FLAG_BOF = (4U << 20) | (1U << 2), /**< Bus-Off flag */ -} can_flag_t; - -/** - * @brief CAN Interrupts - */ -typedef enum -{ - CAN_IT_TME = (1U << 0), /**< Transmit mailbox empty interrupt bit */ - CAN_IT_FMP0 = (1U << 1), /**< FIFO0 message pending interrupt bit */ - CAN_IT_FF0 = (1U << 2), /**< FIFO0 full interrupt bit */ - CAN_IT_FOV0 = (1U << 3), /**< FIFO0 overrun interrupt bit */ - CAN_IT_FMP1 = (1U << 4), /**< FIFO1 message pending interrupt bit */ - CAN_IT_FF1 = (1U << 5), /**< FIFO1 full interrupt bit */ - CAN_IT_FOV1 = (1U << 6), /**< FIFO1 overrun interrupt bit */ - CAN_IT_EWG = (1U << 8), /**< Error warning interrupt bit */ - CAN_IT_EPV = (1U << 9), /**< Error passive interrupt bit */ - CAN_IT_BOF = (1U << 10), /**< Bus-off interrupt bit */ - CAN_IT_LEC = (1U << 11), /**< Last error code interrupt bit */ - CAN_IT_ERR = (1U << 15), /**< Error interrupt bit */ - CAN_IT_WKU = (1U << 16), /**< wake-up interrupt bit */ - CAN_IT_SLK = (1U << 17), /**< sleep interrupt bit */ -} can_it_t; - -/** - * @brief CAN filter configuration structure definition - */ -typedef struct -{ - uint32_t id_high; /**< Specifies the filter identification number */ - uint32_t id_low; /**< Specifies the filter identification number */ - uint32_t mask_id_high; /**< Specifies the filter mask number or identification number */ - uint32_t mask_id_low; /**< Specifies the filter mask number or identification number */ - can_filter_fifo_t fifo; /**< Specifies the fifo (0 or 1) which will be assigned to the filter. */ - uint32_t number; /**< Specifies the filter which will be initialized. */ - can_filter_mode_t mode; /**< Specifies the filter mode to be initialized. */ - can_filter_scale_t scale; /**< Specifies the filter scale. */ - type_func_t active; /**< Enable or disable the filter. */ - uint32_t bank_number; /**< Select the start slave bank filter. */ -} can_filter_t; - -/** - * @brief CAN init structure definition - */ -typedef struct -{ - uint32_t psc; /**< Specifies the length of a time quantum. */ - can_operate_mode_t mode; /**< Specifies the CAN operating mode. */ - can_sjw_t sjw; /**< Specifies the maximum number of time quanta the CAN hardware is - allowed to lengthen or shorten a bit to perform resynchronization. */ - can_seg1_t seg1; /**< Specifies the number of time quanta in Bit Segment 1. */ - can_seg2_t seg2; /**< Specifies the number of time quanta in Bit Segment 2. */ - type_func_t ttcm; /**< Enable or disable the time triggered communication mode. */ - type_func_t abom; /**< Enable or disable the automatic bus-off management. */ - type_func_t awk; /**< Enable or disable the automatic wake-up mode. */ - type_func_t artx; /**< Enable or disable the non-automatic retransmission mode. */ - type_func_t rfom; /**< Enable or disable the Receive fifo Locked mode. */ - type_func_t txmp; /**< Enable or disable the transmit fifo priority. */ -} can_init_t; - -/** - * @brief CAN Tx message structure definition - */ -typedef struct -{ - uint32_t std; /**< Specifies the standard identifier. */ - uint32_t ext; /**< Specifies the extended identifier. */ - can_id_type_t type; /**< Specifies the type of identifier for the message that will be transmitted. */ - can_remote_req_t rtr; /**< Specifies the type of frame for the message that will be transmitted. */ - uint32_t len; /**< Specifies the length of the frame that will be transmitted. */ - uint8_t data[8]; /**< Contains the data to be transmitted. */ -} can_tx_msg_t; - -/** - * @brief CAN Rx message structure definition - */ -typedef struct -{ - uint32_t std; /**< Specifies the standard identifier. */ - uint32_t ext; /**< Specifies the extended identifier. */ - can_id_type_t type; /**< Specifies the type of identifier for the message that will be received. */ - can_remote_req_t rtr; /**< Specifies the type of frame for the received message. */ - uint32_t len; /**< Specifies the length of the frame that will be received. */ - uint8_t data[8]; /**< Contains the data to be received. */ - uint32_t fmi; /**< Specifies the index of the filter the message stored in the mailbox passes through. */ - can_rx_fifo_t num; /**< Specifies the receive fifo number. */ -} can_rx_msg_t; - -/** - * @brief CAN handle Structure definition - */ -typedef struct can_handle_s -{ - CAN_TypeDef *perh; /**< Register base address */ - can_init_t init; /**< CAN required parameters */ - can_rx_msg_t *rx_msg; /**< Pointer to receive message */ - lock_state_t lock; /**< CAN locking object */ - can_state_t state; /**< CAN communication state */ - can_error_t err; /**< CAN Error code */ - - void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct can_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct can_handle_s *arg); /**< error callback */ -} can_handle_t; -/** - * @} - */ - -/** @defgroup CAN_Public_Macro CAN Public Macros - * @{ - */ -#define CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET) -#define CAN_RX_MSG_PENDING(x, y) (((y) == CAN_RX_FIFO0) ? \ - (READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK))) -#define CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS)) -/** - * @} - */ - -/** @defgroup CAN_Private_Macros CAN Private Macros - * @{ - */ -#define IS_CAN_ALL(x) ((x) == CAN0) -#define IS_CAN_FILTER_NUMBER(x) ((x) <= 13) -#define IS_CAN_MODE(x) (((x) == CAN_MODE_NORMAL) || \ - ((x) == CAN_MODE_LOOPBACK) || \ - ((x) == CAN_MODE_SILENT) || \ - ((x) == CAN_MODE_SILENT_LOOPBACK)) -#define IS_CAN_SJW(x) (((x) == CAN_SJW_1) || \ - ((x) == CAN_SJW_2) || \ - ((x) == CAN_SJW_3) || \ - ((x) == CAN_SJW_4)) -#define IS_CAN_BS1(x) ((x) <= CAN_SEG1_16) -#define IS_CAN_BS2(x) ((x) <= CAN_SEG2_8) -#define IS_CAN_FILTER_MODE(x) (((x) == CAN_FILTER_MODE_MASK) || \ - ((x) == CAN_FILTER_MODE_LIST)) -#define IS_CAN_FILTER_SCALE(x) (((x) == CAN_FILTER_SCALE_16) || \ - ((x) == CAN_FILTER_SCALE_32)) -#define IS_CAN_FILTER_FIFO(x) (((x) == CAN_FILTER_FIFO0) || \ - ((x) == CAN_FILTER_FIFO1)) -#define IS_CAN_IDTYPE(x) (((x) == CAN_ID_STD) || \ - ((x) == CAN_ID_EXT)) -#define IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE)) -#define IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1)) -#define IS_CAN_BANKNUMBER(x) ((x) <= 28) -#define IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE) -#define IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08)) -#define IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024)) -#define IS_CAN_GET_FLAG(x) (((x) == CAN_FLAG_SLAK) || \ - ((x) == CAN_FLAG_WKU) || \ - ((x) == CAN_FLAG_SLAKI) || \ - ((x) == CAN_FLAG_RQCP0) || \ - ((x) == CAN_FLAG_TXOK0) || \ - ((x) == CAN_FLAG_RQCP1) || \ - ((x) == CAN_FLAG_TXOK1) || \ - ((x) == CAN_FLAG_RQCP2) || \ - ((x) == CAN_FLAG_TXOK2) || \ - ((x) == CAN_FLAG_TME0) || \ - ((x) == CAN_FLAG_TME1) || \ - ((x) == CAN_FLAG_TME2) || \ - ((x) == CAN_FLAG_FF0) || \ - ((x) == CAN_FLAG_FOV0) || \ - ((x) == CAN_FLAG_FF1) || \ - ((x) == CAN_FLAG_FOV1) || \ - ((x) == CAN_FLAG_EWG) || \ - ((x) == CAN_FLAG_EPV) || \ - ((x) == CAN_FLAG_BOF)) -#define IS_CAN_CLEAR_FLAG(x) (((x) == CAN_FLAG_WKU) || \ - ((x) == CAN_FLAG_SLAKI) || \ - ((x) == CAN_FLAG_RQCP0) || \ - ((x) == CAN_FLAG_RQCP1) || \ - ((x) == CAN_FLAG_RQCP2) || \ - ((x) == CAN_FLAG_FF0) || \ - ((x) == CAN_FLAG_FOV0) || \ - ((x) == CAN_FLAG_FF1) || \ - ((x) == CAN_FLAG_FOV1)) -#define IS_CAN_IT(x) (((x) == CAN_IT_TME) || \ - ((x) == CAN_IT_FMP0) || \ - ((x) == CAN_IT_FF0) || \ - ((x) == CAN_IT_FOV0) || \ - ((x) == CAN_IT_FMP1) || \ - ((x) == CAN_IT_FF1) || \ - ((x) == CAN_IT_FOV1) || \ - ((x) == CAN_IT_EWG) || \ - ((x) == CAN_IT_EPV) || \ - ((x) == CAN_IT_BOF) || \ - ((x) == CAN_IT_LEC) || \ - ((x) == CAN_IT_ERR) || \ - ((x) == CAN_IT_WKU) || \ - ((x) == CAN_IT_SLK)) -#define CAN_TIMEOUT_VALUE 100 -#define CAN_STATE_TX_MASK (1U << 4) -#define CAN_STATE_RX_MASK (1U << 5) -/** - * @} - */ - -/** @addtogroup CAN_Public_Functions - * @{ - */ - -/** @addtogroup CAN_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -void can_reset(can_handle_t *hperh); -ald_status_t can_init(can_handle_t *hperh); -ald_status_t can_filter_config(can_handle_t *hperh, can_filter_t *config); -/** - * @} - */ - -/** @addtogroup CAN_Public_Functions_Group2 - * @{ - */ -/* IO operation functions */ -ald_status_t can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout); -ald_status_t can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg); -ald_status_t can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout); -ald_status_t can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg); -/** - * @} - */ - -/** @addtogroup CAN_Public_Functions_Group3 - * @{ - */ -/* Control function */ -ald_status_t can_sleep(can_handle_t *hperh); -ald_status_t can_wake_up(can_handle_t *hperh); -void can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box); -void can_irq_handler(can_handle_t *hperh); -type_bool_t can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box); -void can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state); -it_status_t can_get_it_status(can_handle_t *hperh, can_it_t it); -flag_status_t can_get_flag_status(can_handle_t *hperh, can_flag_t flag); -void can_clear_flag_status(can_handle_t *hperh, can_flag_t flag); -/** - * @} - */ - -/** @addtogroup CAN_Public_Functions_Group4 - * @{ - */ -/* State and Error functions */ -can_state_t can_get_state(can_handle_t *hperh); -can_error_t can_get_error(can_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_CAN_H */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h deleted file mode 100644 index ced2976ea8b7b119657182e32fd0e3357b6046c0..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h +++ /dev/null @@ -1,632 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_cmu.h - * @brief Header file of CMU module driver. - * - * @version V1.0 - * @date 22 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_CMU_H__ -#define __ALD_CMU_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_syscfg.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup CMU - * @{ - */ - -/** @defgroup CMU_Public_Macros CMU Public Macros - * @{ - */ -#define CMU_LOSC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LOSC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_ULRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_ULRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -/* Low power mode control */ -#define CMU_LP_LRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_LRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_LOSC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_LOSC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_HRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_HRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_HOSC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_HOSC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -/** - * @} - */ - - -/** @defgroup CMU_Public_Types CMU Public Types - * @{ - */ -/** - * @brief CMU state structure definition - */ -typedef enum -{ - CMU_CLOCK_HRC = 0x1, /**< HRC */ - CMU_CLOCK_LRC = 0x2, /**< LRC */ - CMU_CLOCK_LOSC = 0x3, /**< LOSC */ - CMU_CLOCK_PLL1 = 0x4, /**< PLL1 */ - CMU_CLOCK_HOSC = 0x5, /**< HOSC */ -} cmu_clock_t; - -/** - * @brief PLL1 output clock - */ -typedef enum -{ - CMU_PLL1_OUTPUT_32M = 0x0, /**< x8 (32MHz) */ - CMU_PLL1_OUTPUT_48M = 0x1, /**< x12 (48MHz) */ -} cmu_pll1_output_t; - -/** - * @brief PLL1 referance clock - */ -typedef enum -{ - CMU_PLL1_INPUT_HRC_6 = 0x0, /**< HRC / 6 */ - CMU_PLL1_INPUT_PLL2 = 0x1, /**< PLL2 */ - CMU_PLL1_INPUT_HOSC = 0x2, /**< HOSC / 1 */ - CMU_PLL1_INPUT_HOSC_2 = 0x3, /**< HOSC / 2 */ - CMU_PLL1_INPUT_HOSC_3 = 0x4, /**< HOSC / 3 */ - CMU_PLL1_INPUT_HOSC_4 = 0x5, /**< HOSC / 4 */ - CMU_PLL1_INPUT_HOSC_5 = 0x6, /**< HOSC / 5 */ - CMU_PLL1_INPUT_HOSC_6 = 0x7, /**< HOSC / 6 */ -} cmu_pll1_input_t; - -/** - * @brief HOSC range - */ -typedef enum -{ - CMU_HOSC_2M = 0x0, - CMU_HOSC_4M = 0x1, - CMU_HOSC_8M = 0x2, - CMU_HOSC_16M = 0x3, - CMU_HOSC_24M = 0x4, -} cmu_hosc_range_t; - -/** - * @brief Auto-calibrate input - */ -typedef enum -{ - CMU_AUTO_CALIB_INPUT_LOSE = 0x0, - CMU_AUTO_CALIB_INPUT_HOSE = 0x1, -} cmu_auto_calib_input_t; - -/** - * @brief Auto-calibrate output - */ -typedef enum -{ - CMU_AUTO_CALIB_OUTPUT_24M = 0x0, - CMU_AUTO_CALIB_OUTPUT_2M = 0x1, -} cmu_auto_calib_output_t; - -/** - * @brief Frequency division select bit - */ -typedef enum -{ - CMU_DIV_1 = 0x0, /**< Division by 1 */ - CMU_DIV_2 = 0x1, /**< Division by 2 */ - CMU_DIV_4 = 0x2, /**< Division by 4 */ - CMU_DIV_8 = 0x3, /**< Division by 8 */ - CMU_DIV_16 = 0x4, /**< Division by 16 */ - CMU_DIV_32 = 0x5, /**< Division by 32 */ - CMU_DIV_64 = 0x6, /**< Division by 64 */ - CMU_DIV_128 = 0x7, /**< Division by 128 */ - CMU_DIV_256 = 0x8, /**< Division by 256 */ - CMU_DIV_512 = 0x9, /**< Division by 512 */ - CMU_DIV_1024 = 0xA, /**< Division by 1024 */ - CMU_DIV_2048 = 0xB, /**< Division by 2048 */ - CMU_DIV_4096 = 0xC, /**< Division by 4096 */ -} cmu_div_t; - -/** - * @brief Bus type - */ -typedef enum -{ - CMU_HCLK_1 = 0x0, /**< AHB1 bus */ - CMU_SYS = 0x1, /**< SYS bus */ - CMU_PCLK_1 = 0x2, /**< APB1 bus */ - CMU_PCLK_2 = 0x3, /**< APB2 bus */ -} cmu_bus_t; - -/** - * @brief Output high clock select - */ -typedef enum -{ - CMU_OUTPUT_HIGH_SEL_HOSC = 0x0, /**< Select HOSC */ - CMU_OUTPUT_HIGH_SEL_LOSC = 0x1, /**< Select LOSC */ - CMU_OUTPUT_HIGH_SEL_HRC = 0x2, /**< Select HRC */ - CMU_OUTPUT_HIGH_SEL_LRC = 0x3, /**< Select LRC */ - CMU_OUTPUT_HIGH_SEL_HOSM = 0x4, /**< Select HOSM */ - CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5, /**< Select PLL1 */ - CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6, /**< Select PLL2 */ - CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7, /**< Select SYSCLK */ -} cmu_output_high_sel_t; - -/** - * @brief Output frequency division - */ -typedef enum -{ - CMU_OUTPUT_DIV_1 = 0x0, /**< Division by 1 */ - CMU_OUTPUT_DIV_2 = 0x1, /**< Division by 2 */ - CMU_OUTPUT_DIV_4 = 0x2, /**< Division by 4 */ - CMU_OUTPUT_DIV_8 = 0x3, /**< Division by 8 */ - CMU_OUTPUT_DIV_16 = 0x4, /**< Division by 16 */ - CMU_OUTPUT_DIV_32 = 0x5, /**< Division by 32 */ - CMU_OUTPUT_DIV_64 = 0x6, /**< Division by 64 */ - CMU_OUTPUT_DIV_128 = 0x7, /**< Division by 128 */ -} cmu_output_high_div_t; - -/** - * @brief Output low clock select - */ -typedef enum -{ - CMU_OUTPUT_LOW_SEL_LOSC = 0x0, /**< Select LOSC */ - CMU_OUTPUT_LOW_SEL_LRC = 0x1, /**< Select LRC */ - CMU_OUTPUT_LOW_SEL_LOSM = 0x2, /**< Select LOSM */ - CMU_OUTPUT_LOW_SEL_BUZZ = 0x3, /**< Select BUZZ */ - CMU_OUTPUT_LOW_SEL_ULRC = 0x4, /**< Select ULRC */ -} cmu_output_low_sel_t; - -/** - * @brief BUZZ frequency division - */ -typedef enum -{ - CMU_BUZZ_DIV_2 = 0x0, /**< Division by 2 */ - CMU_BUZZ_DIV_4 = 0x1, /**< Division by 4 */ - CMU_BUZZ_DIV_8 = 0x2, /**< Division by 8 */ - CMU_BUZZ_DIV_16 = 0x3, /**< Division by 16 */ - CMU_BUZZ_DIV_32 = 0x4, /**< Division by 32 */ - CMU_BUZZ_DIV_64 = 0x5, /**< Division by 64 */ - CMU_BUZZ_DIV_128 = 0x6, /**< Division by 128 */ - CMU_BUZZ_DIV_256 = 0x7, /**< Division by 256 */ -} cmu_buzz_div_t; - -/** - * @brief Low power peripheral clock select - */ -typedef enum -{ - CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0, /**< Select PCLK2 */ - CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1, /**< Select PLL1 */ - CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2, /**< Select PLL2 */ - CMU_LP_PERH_CLOCK_SEL_HRC = 0x3, /**< Select HRC */ - CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4, /**< Select HOSC */ - CMU_LP_PERH_CLOCK_SEL_LRC = 0x5, /**< Select LRC */ - CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6, /**< Select LOSC */ - CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7, /**< Select ULRC */ - CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8, /**< Select HRC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9, /**< Select HOSC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_LOSM = 0xA, /**< Select LOSM */ - CMU_LP_PERH_CLOCK_SEL_HOSM = 0xB, /**< Select HOSM */ -} cmu_lp_perh_clock_sel_t; - -/** - * @brief LCD clock select - */ -typedef enum -{ - CMU_LCD_SEL_LOSM = 0x0, /**< Select LOSM */ - CMU_LCD_SEL_LOSC = 0x1, /**< Select LOSC */ - CMU_LCD_SEL_LRC = 0x2, /**< Select LRC */ - CMU_LCD_SEL_ULRC = 0x3, /**< Select ULRC */ - CMU_LCD_SEL_HRC_1M = 0x4, /**< Select HRC down to 1MHz */ - CMU_LCD_SEL_HOSC_1M = 0x5, /**< Select HOSC down to 1MHz */ -} cmu_lcd_clock_sel_t; - -/** - * @brief Peripheral clock enable/disable - */ -typedef enum -{ - CMU_PERH_GPIO = (1U << 0), /**< GPIO */ - CMU_PERH_CRC = (1U << 1), /**< CRC */ - CMU_PERH_CALC = (1U << 2), /**< CALC */ - CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ - CMU_PERH_TRNG = (1U << 4), /**< TRNG */ - CMU_PERH_PIS = (1U << 5), /**< PIS */ - CMU_PERH_TIM0 = (1U << 0) | (1U << 27), /**< TIM0 */ - CMU_PERH_TIM1 = (1U << 1) | (1U << 27), /**< TIM1 */ - CMU_PERH_TIM2 = (1U << 2) | (1U << 27), /**< TIM2 */ - CMU_PERH_TIM3 = (1U << 3) | (1U << 27), /**< TIM3 */ - CMU_PERH_TIM4 = (1U << 4) | (1U << 27), /**< TIM4 */ - CMU_PERH_TIM5 = (1U << 5) | (1U << 27), /**< TIM5 */ - CMU_PERH_TIM6 = (1U << 6) | (1U << 27), /**< TIM6 */ - CMU_PERH_TIM7 = (1U << 7) | (1U << 27), /**< TIM7 */ - CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ - CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ - CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ - CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ - CMU_PERH_USART0 = (1U << 12) | (1U << 27), /**< USART0 */ - CMU_PERH_USART1 = (1U << 13) | (1U << 27), /**< USART1 */ - CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ - CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ - CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ - CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ - CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ - CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ - CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ - CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ - CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ - CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ - CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ - CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ - CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ - CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ - CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ - CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ - CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ - CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ - CMU_PERH_TEMP = (1U << 16) | (1U << 28), /**< TEMP */ - CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ - CMU_PERH_BKRPAM = (1U << 18) | (1U << 28), /**< BKPRAM */ - CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ - CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ -} cmu_perh_t; - -/** - * @brief CMU interrupt type - */ -typedef enum -{ - CMU_LOSC_STOP = 0x0, /**< LOSC STOP INTERRUPT */ - CMU_HOSC_STOP = 0x1, /**< HOSC STOP INTERRUPT */ - CMU_PLL1_UNLOCK = 0x2, /**< PLL1 UNLOCK INTERRUPT */ - CMU_LOSC_START = 0x3, /**< LOSC START INTERRUPT */ - CMU_HOSC_START = 0x4, /**< HOSC START INTERRUPT */ -} cmu_security_t; - -/** - * @brief CMU clock state type - */ -typedef enum -{ - CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ - CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ - CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ - CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ - CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ - CMU_CLOCK_STATE_PLLACT = (1U << 8), /**< PLL active */ - CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ - CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ - CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ - CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ - CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ -} cmu_clock_state_t; -/** - * @} - */ - -/** - * @defgroup CMU_Private_Macros CMU Private Macros - * @{ - */ -#define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \ - ((x) == CMU_CLOCK_LRC) || \ - ((x) == CMU_CLOCK_LOSC) || \ - ((x) == CMU_CLOCK_PLL1) || \ - ((x) == CMU_CLOCK_HOSC)) -#define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_32M) || \ - ((x) == CMU_PLL1_OUTPUT_48M)) -#define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ - ((x) == CMU_PLL1_INPUT_PLL2) || \ - ((x) == CMU_PLL1_INPUT_HOSC) || \ - ((x) == CMU_PLL1_INPUT_HOSC_2) || \ - ((x) == CMU_PLL1_INPUT_HOSC_3) || \ - ((x) == CMU_PLL1_INPUT_HOSC_4) || \ - ((x) == CMU_PLL1_INPUT_HOSC_5) || \ - ((x) == CMU_PLL1_INPUT_HOSC_6)) -#define IS_CMU_HOSC_RANGE(x) (((x) == CMU_HOSC_2M) || \ - ((x) == CMU_HOSC_4M) || \ - ((x) == CMU_HOSC_8M) || \ - ((x) == CMU_HOSC_16M) || \ - ((x) == CMU_HOSC_24M)) -#define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \ - ((x) == CMU_DIV_2) || \ - ((x) == CMU_DIV_4) || \ - ((x) == CMU_DIV_8) || \ - ((x) == CMU_DIV_16) || \ - ((x) == CMU_DIV_32) || \ - ((x) == CMU_DIV_64) || \ - ((x) == CMU_DIV_128) || \ - ((x) == CMU_DIV_256) || \ - ((x) == CMU_DIV_512) || \ - ((x) == CMU_DIV_1024) || \ - ((x) == CMU_DIV_2048) || \ - ((x) == CMU_DIV_4096)) -#define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \ - ((x) == CMU_SYS) || \ - ((x) == CMU_PCLK_1) || \ - ((x) == CMU_PCLK_2)) -#define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) -#define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \ - ((x) == CMU_OUTPUT_DIV_2) || \ - ((x) == CMU_OUTPUT_DIV_4) || \ - ((x) == CMU_OUTPUT_DIV_8) || \ - ((x) == CMU_OUTPUT_DIV_16) || \ - ((x) == CMU_OUTPUT_DIV_32) || \ - ((x) == CMU_OUTPUT_DIV_64) || \ - ((x) == CMU_OUTPUT_DIV_128)) -#define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \ - ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ - ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ - ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ - ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) -#define IS_CMU_AUTO_CALIB_INPUT(x) (((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \ - ((x) == CMU_AUTO_CALIB_INPUT_HOSE)) -#define IS_CMU_AUTO_CALIB_OUTPUT(x) (((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \ - ((x) == CMU_AUTO_CALIB_OUTPUT_2M)) -#define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ - ((x) == CMU_BUZZ_DIV_4) || \ - ((x) == CMU_BUZZ_DIV_8) || \ - ((x) == CMU_BUZZ_DIV_16) || \ - ((x) == CMU_BUZZ_DIV_32) || \ - ((x) == CMU_BUZZ_DIV_64) || \ - ((x) == CMU_BUZZ_DIV_128) || \ - ((x) == CMU_BUZZ_DIV_256)) -#define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) -#define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \ - ((x) == CMU_LCD_SEL_LOSC) || \ - ((x) == CMU_LCD_SEL_LRC) || \ - ((x) == CMU_LCD_SEL_ULRC) || \ - ((x) == CMU_LCD_SEL_HRC_1M) || \ - ((x) == CMU_LCD_SEL_HOSC_1M)) -#define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \ - ((x) == CMU_PERH_CRC) || \ - ((x) == CMU_PERH_CALC) || \ - ((x) == CMU_PERH_CRYPT) || \ - ((x) == CMU_PERH_TRNG) || \ - ((x) == CMU_PERH_PIS) || \ - ((x) == CMU_PERH_TIM0) || \ - ((x) == CMU_PERH_TIM1) || \ - ((x) == CMU_PERH_TIM2) || \ - ((x) == CMU_PERH_TIM3) || \ - ((x) == CMU_PERH_TIM4) || \ - ((x) == CMU_PERH_TIM5) || \ - ((x) == CMU_PERH_TIM6) || \ - ((x) == CMU_PERH_TIM7) || \ - ((x) == CMU_PERH_UART0) || \ - ((x) == CMU_PERH_UART1) || \ - ((x) == CMU_PERH_UART2) || \ - ((x) == CMU_PERH_UART3) || \ - ((x) == CMU_PERH_USART0) || \ - ((x) == CMU_PERH_USART1) || \ - ((x) == CMU_PERH_SPI0) || \ - ((x) == CMU_PERH_SPI1) || \ - ((x) == CMU_PERH_SPI2) || \ - ((x) == CMU_PERH_I2C0) || \ - ((x) == CMU_PERH_I2C1) || \ - ((x) == CMU_PERH_CAN) || \ - ((x) == CMU_PERH_LPTIM0) || \ - ((x) == CMU_PERH_LPUART0) || \ - ((x) == CMU_PERH_ADC0) || \ - ((x) == CMU_PERH_ADC1) || \ - ((x) == CMU_PERH_ACMP0) || \ - ((x) == CMU_PERH_ACMP1) || \ - ((x) == CMU_PERH_OPAMP) || \ - ((x) == CMU_PERH_DAC0) || \ - ((x) == CMU_PERH_WWDT) || \ - ((x) == CMU_PERH_LCD) || \ - ((x) == CMU_PERH_IWDT) || \ - ((x) == CMU_PERH_RTC) || \ - ((x) == CMU_PERH_TEMP) || \ - ((x) == CMU_PERH_BKPC) || \ - ((x) == CMU_PERH_BKRPAM ) || \ - ((x) == CMU_PERH_DBGC) || \ - ((x) == CMU_PERH_ALL)) -#define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ - ((x) == CMU_CLOCK_STATE_LOSCACT) || \ - ((x) == CMU_CLOCK_STATE_HRCACT) || \ - ((x) == CMU_CLOCK_STATE_LRCACT) || \ - ((x) == CMU_CLOCK_STATE_ULRCACT) || \ - ((x) == CMU_CLOCK_STATE_PLLACT) || \ - ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ - ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ - ((x) == CMU_CLOCK_STATE_HRCRDY) || \ - ((x) == CMU_CLOCK_STATE_LRCRDY) || \ - ((x) == CMU_CLOCK_STATE_PLLRDY)) -/** - * @} - */ - -/** @addtogroup CMU_Public_Functions - * @{ - */ -/** @addtogroup CMU_Public_Functions_Group1 - * @{ - */ -/* System clock configure */ -ald_status_t cmu_clock_config_default(void); -ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock); -void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output); -uint32_t cmu_get_clock(void); -int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq); -/** - * @} - */ - -/** @addtogroup CMU_Public_Functions_Group2 - * @{ - */ -/* BUS division control */ -void cmu_div_config(cmu_bus_t bus, cmu_div_t div); -uint32_t cmu_get_hclk1_clock(void); -uint32_t cmu_get_sys_clock(void); -uint32_t cmu_get_pclk1_clock(void); -uint32_t cmu_get_pclk2_clock(void); -/** - * @} - */ - -/** @addtogroup CMU_Public_Functions_Group3 - * @{ - */ -/* Clock safe configure */ -void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); -void cmu_losc_safe_config(type_func_t status); -void cmu_pll_safe_config(type_func_t status); -flag_status_t cmu_get_clock_state(cmu_clock_state_t sr); -void cmu_irq_cbk(cmu_security_t se); -/** - * @} - */ - -/** @addtogroup CMU_Public_Functions_Group4 - * @{ - */ -/* Clock output configure */ -void cmu_output_high_clock_config(cmu_output_high_sel_t sel, - cmu_output_high_div_t div, type_func_t status); -void cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); -/** - * @} - */ - -/** @addtogroup CMU_Public_Functions_Group5 - * @{ - */ -/* Peripheral Clock configure */ -void cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status); -void cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock); -void cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock); -void cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock); -void cmu_perh_clock_config(cmu_perh_t perh, type_func_t status); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_CMU_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h deleted file mode 100644 index 5562db71f48cbec008d18f9cf98f22c4261360c9..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h +++ /dev/null @@ -1,197 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_crc.h - * @brief Header file of CRC module driver. - * - * @version V1.0 - * @date 6 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_CRC_H__ -#define __ALD_CRC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/** @defgroup CRC_Public_Types CRC Public Types - * @{ - */ - -/** - * @brief CRC mode - */ -typedef enum -{ - CRC_MODE_CCITT = 0, /**< Ccitt */ - CRC_MODE_8 = 1, /**< Crc8 */ - CRC_MODE_16 = 2, /**< Crc16 */ - CRC_MODE_32 = 3, /**< Crc32 */ -} crc_mode_t; - -/** - * @brief CRC input length - */ -typedef enum -{ - CRC_LEN_AUTO = 0, /**< Auto */ - CRC_DATASIZE_8 = 1, /**< Byte */ - CRC_DATASIZE_16 = 2, /**< Half word */ - CRC_DATASIZE_32 = 3, /**< Word */ -} crc_datasize_t; - -/** - * @brief CRC whether write error or no - */ -typedef enum -{ - CRC_WERR_NO = 0, /**< No error */ - CRC_WERR_ERR = 1, /**< Error */ -} crc_werr_t; - -/** - * @brief CRC state structures definition - */ -typedef enum -{ - CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - CRC_STATE_ERROR = 0x4, /**< Error */ -} crc_state_t; - -/** - * @brief CRC init structure definition - */ -typedef struct -{ - crc_mode_t mode; /**< CRC mode */ - type_func_t data_rev; /**< CRC data reverse or no */ - type_func_t data_inv; /**< CRC data inverse or no */ - type_func_t chs_rev; /**< CRC check sum reverse or no */ - type_func_t chs_inv; /**< CRC check sum inverse or no */ - uint32_t seed; /**< CRC seed */ -} crc_init_t; - -/** - * @brief CRC Handle Structure definition - */ -typedef struct crc_handle_s -{ - CRC_TypeDef *perh; /**< Register base address */ - crc_init_t init; /**< CRC required parameters */ - uint8_t *cal_buf; /**< The pointer of preparing buffer */ - uint32_t *cal_res; /**< The pointer of result */ -#ifdef ALD_DMA - dma_handle_t hdma; /**< CRC DMA handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - crc_state_t state; /**< CRC operation state */ - - void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ - void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ -} crc_handle_t; -/** - * @} - */ - -/** @defgroup CRC_Public_Macros CRC Public Macros - * @{ - */ -#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) -#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) -#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK)) -#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) -#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) -#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK)) -/** - * @} - */ - -/** @defgroup CRC_Private_Macros CRC Private Macros - * @{ - */ -#define IS_CRC(x) ((x) == CRC) -#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \ - ((x) == CRC_MODE_8) || \ - ((x) == CRC_MODE_16) || \ - ((x) == CRC_MODE_32)) -/** - * @} - */ - -/** @addtogroup CRC_Public_Functions - * @{ - */ - -/** @addtogroup CRC_Public_Functions_Group1 - * @{ - */ -ald_status_t crc_init(crc_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup CRC_Public_Functions_Group2 - * @{ - */ -uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size); -/** - * @} - */ - -#ifdef ALD_DMA -/** @addtogroup CRC_Public_Functions_Group3 - * @{ - */ -ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel); -ald_status_t crc_dma_pause(crc_handle_t *hperh); -ald_status_t crc_dma_resume(crc_handle_t *hperh); -ald_status_t crc_dma_stop(crc_handle_t *hperh); -/** - * @} - */ -#endif -/** @addtogroup CRC_Public_Functions_Group4 - * @{ - */ -crc_state_t crc_get_state(crc_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_CRC_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h deleted file mode 100644 index f3a5ebaeb563231a9b2d018e4e941d3a9b0359a2..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h +++ /dev/null @@ -1,264 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_crypt.h - * @brief Header file of CRYPT module driver. - * - * @version V1.0 - * @date 7 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_CRYPT_H__ -#define __ALD_CRYPT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup CRYPT - * @{ - */ - -/** @defgroup CRYPT_Public_Types CRYPT Public Types - * @{ - */ - -/** - * @brief CRYPT encrypt or decrypt select - */ -typedef enum -{ - CRYPT_DECRYPT = 0, /**< Decrypt */ - CRYPT_ENCRYPT = 1, /**< Encrypt */ -} crypt_encs_t; - -/** - * @brief CRYPT mode select - */ -typedef enum -{ - CRYPT_MODE_ECB = 0, /**< ECB */ - CRYPT_MODE_CBC = 1, /**< CBC */ - CRYPT_MODE_CTR = 2, /**< CTR */ -} crypt_mode_t; - -/** - * @brief CRYPT data type - */ -typedef enum -{ - CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */ - CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */ - CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */ - CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */ -} crypt_datatype_t; - -/** - * @brief CRYPT interrupt - */ -typedef enum -{ - CRYPT_IT_IT = 0x80, /**< Interrupt */ -} crypt_it_t; - -/** - * @brief CRYPT interrupt flag - */ -typedef enum -{ - CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */ - CRYPT_FLAG_DONE = 0x100, /**< Complete flag */ -} crypt_flag_t; - -/** - * @brief CRYPT state structures definition - */ -typedef enum -{ - CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - CRYPT_STATE_ERROR = 0x4, /**< Error */ -} crypt_state_t; - -/** - * @brief CRYPT data type - */ -typedef enum -{ - DATA_32_BIT = 0, /**< 32 bit data,don't swap */ - DATA_16_BIT = 1, /**< 16 bit data,swap */ - DATA_8_BIT = 2, /**< 8 bit data,swap */ - DATA_1_BIT = 3, /**< 1 bit data, swap */ -} crypt_data_t; - -/** - * @brief CRYPT init structure definition - */ -typedef struct -{ - crypt_mode_t mode; /**< Crypt mode */ - crypt_data_t type; /**< Data type select */ -} crypt_init_t; - -/** - * @brief CRYPT Handle Structure definition - */ -typedef struct crypt_handle_s -{ - CRYPT_TypeDef *perh; /**< Register base address */ - crypt_init_t init; /**< CRYPT required parameters */ -#ifdef ALD_DMA - dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ - dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ -#endif - uint8_t *plain_text; /**< Pointer to plain text */ - uint8_t *cipher_text; /**< Pointer to cipher text */ - uint32_t size; /**< The size of crypt data buf */ - uint32_t count; /**< The count of crypt data buf */ - uint32_t step; /**< The step of once crypt 4(aes) */ - uint32_t dir; /**< ENCRYPT or DECRYPT */ - uint32_t iv[4]; /**< The iv of crypt */ - uint32_t key[4]; /**< The key of crypt */ - lock_state_t lock; /**< Locking object */ - crypt_state_t state; /**< CRYPT operation state */ - - void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ - void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ -} crypt_handle_t; -/** - * @} - */ - -/** @defgroup CRYPT_Public_Macros CRYPT Public Macros - * @{ - */ -#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK)) -#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) -#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) -#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) -#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) -#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) -#define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) -#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) -#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) -#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \ - (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) -#define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data)) -#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO) -/** - * @} - */ - -/** @defgroup CRYPT_Private_Macros CRYPT Private Macros - * @{ - */ -#define IS_CRYPT(x) ((x) == CRYPT) -#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \ - ((x) == CRYPT_MODE_CBC) || \ - ((x) == CRYPT_MODE_CTR)) -#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT) -#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \ - ((x) == CRYPT_FLAG_DONE)) -#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \ - ((x) == IV_4_LEN)) -/** - * @} - */ - -/** @addtogroup CRYPT_Public_Functions - * @{ - */ - -/** @addtogroup CRYPT_Public_Functions_Group1 - * @{ - */ -ald_status_t crypt_init(crypt_handle_t *hperh); -ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key); -ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key); -ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv); -ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv); -/** - * @} - */ - -/** @addtogroup CRYPT_Public_Functions_Group2 - * @{ - */ -ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); -ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); -ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag); -ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); -ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); -#ifdef ALD_DMA -ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, - uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); -ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, - uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); -#endif -/** - * @} - */ - -/** @addtogroup CRYPT_Public_Functions_Group3 - * @{ - */ -#ifdef ALD_DMA -ald_status_t crypt_dma_pause(crypt_handle_t *hperh); -ald_status_t crypt_dma_resume(crypt_handle_t *hperh); -ald_status_t crypt_dma_stop(crypt_handle_t *hperh); -#endif -void crypt_irq_handle(crypt_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup CRYPT_Public_Functions_Group4 - * @{ - */ -void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state); -flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); -void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); -it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it); -/** - * @} - */ - -/** @addtogroup CRYPT_Public_Functions_Group5 - * @{ - */ -crypt_state_t crypt_get_state(crypt_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h deleted file mode 100644 index 646ae02a67a21be1f3361f1ab35c924625fed973..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h +++ /dev/null @@ -1,389 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_dma.h - * @brief DMA module Library. - * - * @version V1.0 - * @date 09 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_DMA_H__ -#define __ALD_DMA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** - * @defgroup DMA_Public_Macros DMA Public Macros - * @{ - */ -#define DMA_CH_COUNT 6 -#define DMA_ERR 31 -/** - * @} - */ - -/** - * @defgroup DMA_Public_Types DMA Public Types - * @{ - */ - -/** - * @brief Input source to DMA channel - */ -typedef enum -{ - DMA_MSEL_NONE = 0x0, /**< NONE */ - DMA_MSEL_GPIO = 0x1, /**< GPIO */ - DMA_MSEL_CRYPT = 0x2, /**< CRYPT */ - DMA_MSEL_ACMP = 0x3, /**< ACMP */ - DMA_MSEL_DAC0 = 0x4, /**< DAC0 */ - DMA_MSEL_ADC0 = 0x6, /**< ADC0 */ - DMA_MSEL_CRC = 0x7, /**< CRC */ - DMA_MSEL_UART0 = 0x8, /**< UART0 */ - DMA_MSEL_UART1 = 0x9, /**< UART1 */ - DMA_MSEL_UART2 = 0xA, /**< UART2 */ - DMA_MSEL_UART3 = 0xB, /**< UART3 */ - DMA_MSEL_USART0 = 0xC, /**< USART0 */ - DMA_MSEL_USART1 = 0xD, /**< USART1 */ - DMA_MSEL_SPI0 = 0xE, /**< SPI0 */ - DMA_MSEL_SPI1 = 0xF, /**< SPI1 */ - DMA_MSEL_I2C0 = 0x10, /**< I2C0 */ - DMA_MSEL_I2C1 = 0x11, /**< I2C1 */ - DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */ - DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */ - DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */ - DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */ - DMA_MSEL_RTC = 0x16, /**< RTC */ - DMA_MSEL_LPTIM0 = 0x17, /**< LPTIM0 */ - DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */ - DMA_MSEL_DMA = 0x19, /**< DMA */ - DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */ - DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */ - DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */ - DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */ - DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */ - DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */ - DMA_MSEL_PIS = 0x20, /**< PIS */ - DMA_MSEL_TRNG = 0x21, /**< TRNG */ -} dma_msel_t; - -/** - * @brief Input signal to DMA channel - */ -typedef enum -{ - DMA_MSIGSEL_NONE = 0x0, /**< NONE */ - DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */ - DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */ - DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */ - DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */ - DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */ - DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */ - DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */ - DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */ - DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */ - DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */ - DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */ - DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */ - DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */ - DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */ - DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */ - DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */ - DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */ - DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */ - DMA_MSIGSEL_CALC_WRITE = 0x0, /**< CALC write mode */ - DMA_MSIGSEL_CALC_READ = 0x1, /**< CALC read mode */ - DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */ - DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */ - DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */ - DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART transmit */ - DMA_MSIGSEL_UART_RNR = 0x1, /**< UART receive */ - DMA_MSIGSEL_USART_RNR = 0x0, /**< USART reveive */ - DMA_MSIGSEL_USART_TXEMPTY = 0x1, /**< USART transmit */ - DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */ - DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */ - DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */ - DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */ - DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */ - DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */ - DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */ - DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */ - DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */ - DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */ - DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */ - DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */ - DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */ - DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */ - DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */ - DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */ - DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */ - DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */ - DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */ - DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */ - DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */ - DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */ - DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */ - DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */ - DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */ - DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */ - DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */ - DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */ - DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */ -} dma_msigsel_t; - -/** - * @brief DMA Descriptor control type - */ -typedef union -{ - struct - { - uint32_t cycle_ctrl : 3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ - uint32_t next_useburst : 1; /**< Uses the alternate data structure when complete a DMA cycle */ - uint32_t n_minus_1 : 10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ - uint32_t R_power : 4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ - uint32_t src_prot_ctrl : 3; /**< Control the state of HPROT when reads the source data. */ - uint32_t dst_prot_ctrl : 3; /**< Control the state of HPROT when writes the destination data */ - uint32_t src_size : 2; /**< Source data size @ref dma_data_size_t */ - uint32_t src_inc : 2; /**< Control the source address increment. @ref dma_data_inc_t */ - uint32_t dst_size : 2; /**< Destination data size. @ref dma_data_size_t */ - uint32_t dst_inc : 2; /**< Destination address increment. @ref dma_data_inc_t */ - }; - uint32_t word; -} dma_ctrl_t; - -/** - * @brief Channel control data structure - */ -typedef struct -{ - void *src; /**< Source data end pointer */ - void *dst; /**< Destination data end pointer */ - dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ - uint32_t use; /**< Reserve for user */ -} dma_descriptor_t; - -/** - * @brief data increment - */ -typedef enum -{ - DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */ - DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */ - DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */ - DMA_DATA_INC_NONE = 0x3, /**< No increment */ -} dma_data_inc_t; - -/** - * @brief Data size - */ -typedef enum -{ - DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */ - DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */ - DMA_DATA_SIZE_WORD = 0x2, /**< Word */ -} dma_data_size_t; - -/** - * @brief The operating mode of the DMA cycle - */ -typedef enum -{ - DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */ - DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */ - DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */ - DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */ - DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */ - DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */ -} dma_cycle_ctrl_t; - -/** - * @brief Control how many DMA transfers can occur - * before the controller re-arbitrates - */ -typedef enum -{ - DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */ - DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */ - DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */ - DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */ - DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */ - DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */ - DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */ - DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */ - DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */ - DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */ - DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */ -} dma_arbiter_config_t; - -/** - * @brief Callback function pointer and param - */ -typedef struct -{ - void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ - void (*err_cbk)(void *arg); /**< DMA occurs error callback */ - void *cplt_arg; /**< The parameter of cplt_cbk() */ - void *err_arg; /**< The parameter of err_cbk() */ -} dma_call_back_t; - -/** - * @brief DMA channal configure structure - */ -typedef struct -{ - void *src; /**< Source data begin pointer */ - void *dst; /**< Destination data begin pointer */ - uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ - dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ - dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ - dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ - dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ - type_func_t primary; /**< Use primary descriptor or alternate descriptor */ - type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */ - type_func_t high_prio; /**< High priority or default priority */ - type_func_t iterrupt; /**< Enable/disable interrupt */ - dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ - dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ - uint8_t channel; /**< Channel index */ -} dma_config_t; - -/** - * @brief DMA handle structure definition - */ -typedef struct -{ - DMA_TypeDef *perh; /**< DMA registers base address */ - dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ - void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ - void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ - void *cplt_arg; /**< The parameter of cplt_cbk() */ - void *err_arg; /**< The parameter of err_cbk() */ -} dma_handle_t; -/** - * @} - */ - -/** - * @defgroup DMA_Private_Macros DMA Private Macros - * @{ - */ -#define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_TRNG) -#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF) -#define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \ - ((x) == DMA_DATA_INC_HALFWORD) || \ - ((x) == DMA_DATA_INC_WORD) || \ - ((x) == DMA_DATA_INC_NONE)) -#define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ - ((x) == DMA_DATA_SIZE_HALFWORD) || \ - ((x) == DMA_DATA_SIZE_WORD)) -#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ - ((x) == DMA_CYCLE_CTRL_BASIC) || \ - ((x) == DMA_CYCLE_CTRL_AUTO) || \ - ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ - ((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \ - ((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER)) -#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ - ((x) == DMA_R_POWER_2) || \ - ((x) == DMA_R_POWER_4) || \ - ((x) == DMA_R_POWER_8) || \ - ((x) == DMA_R_POWER_16) || \ - ((x) == DMA_R_POWER_32) || \ - ((x) == DMA_R_POWER_64) || \ - ((x) == DMA_R_POWER_128) || \ - ((x) == DMA_R_POWER_256) || \ - ((x) == DMA_R_POWER_512) || \ - ((x) == DMA_R_POWER_1024)) -#define IS_DMA(x) ((x) == DMA0) -#define IS_DMA_CHANNEL(x) ((x) <= 5) -#define IS_DMA_DATA_SIZE(x) ((x) <= 1024) -#define IS_DMA_IT_TYPE(x) (((x) <= 5) || ((x) == 31)) -/** - * @} - */ - -/** - * @addtogroup DMA_Public_Functions - * @{ - */ - -/** @addtogroup DMA_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -extern void dma_reset(DMA_TypeDef *DMAx); -extern void dma_init(DMA_TypeDef *DMAx); -extern void dma_config_struct(dma_config_t *p); -/** - * @} - */ - - -/** @addtogroup DMA_Public_Functions_Group2 - * @{ - */ -/* Configure DMA channel functions */ -extern void dma_config_auto(dma_handle_t *hperh); -extern void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size); -extern void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, - uint16_t size, uint8_t channel, void (*cbk)(void *arg)); -extern void dma_config_basic(dma_handle_t *hperh); -extern void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); -extern void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, - dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); -/** - * @} - */ - -/** @addtogroup DMA_Public_Functions_Group3 - * @{ - */ -/* DMA control functions */ -extern void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); -extern void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); -extern it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); -extern flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); -extern void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); -void dma0_irq_cbk(void); -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__ALD_DMA_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h deleted file mode 100644 index 71449f946b42c3799864f70809ddcbdc7f9c0755..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_flash.h - * @brief Header file of FLASH driver - * - * @version V1.0 - * @date 20 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_FLASH_H__ -#define __ALD_FLASH_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** - * @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ -#define FLASH_REG_UNLOCK() \ -do { \ - if (op_cmd == OP_FLASH) { \ - WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \ - WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \ - } \ - else { \ - WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \ - WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \ - } \ -} while (0) -#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) -#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) -#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) -#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) -#define FLASH_BASE_ADDR 0x00000000 -#define FLASH_PAGE_SIZE 1024UL -#define FLASH_WORD_SIZE 8UL -#define FLASH_TOTAL_SIZE 256UL -#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) -#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1) -#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE)) -#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0) -#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK)) -#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK) -#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK)) -#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK) -#define INFO_PAGE_SIZE 1024UL -#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1) -#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK)) - -#ifdef USE_FLASH_FIFO -#define FLASH_FIFO 1 -#else -#define FLASH_FIFO 0 -#endif -/** - * @} - */ - -/** @defgroup FLASH_Private_Types FLASH Private Types - * @{ - */ -typedef enum -{ - FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */ - FLASH_CMD_PE = 0x00005EA1, /**< Page erase */ - FLASH_CMD_WP = 0x00005DA2, /**< Word program */ - FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */ - FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */ -} flash_cmd_type; - -typedef enum -{ - OP_FLASH = 0, /**< Operate Pragram area */ - OP_INFO = 1, /**< Operate info area */ -} op_cmd_type; - -/** - * @} - */ - -/** @addtogroup Flash_Public_Functions - * @{ - */ -ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len); -ald_status_t flash_erase(uint32_t addr, uint16_t len); -ald_status_t flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_FLASH_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h deleted file mode 100644 index 7e93a9575181ab372a6318ab5385074f966889c0..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ /dev/null @@ -1,288 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_gpio.h - * @brief Header file of GPIO module driver - * - * @version V1.0 - * @date 07 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_GPIO_H__ -#define __ALD_GPIO_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/** - * @defgroup GPIO_Public_Macros GPIO Public Macros - * @{ - */ -#define GPIO_PIN_0 (1U << 0) -#define GPIO_PIN_1 (1U << 1) -#define GPIO_PIN_2 (1U << 2) -#define GPIO_PIN_3 (1U << 3) -#define GPIO_PIN_4 (1U << 4) -#define GPIO_PIN_5 (1U << 5) -#define GPIO_PIN_6 (1U << 6) -#define GPIO_PIN_7 (1U << 7) -#define GPIO_PIN_8 (1U << 8) -#define GPIO_PIN_9 (1U << 9) -#define GPIO_PIN_10 (1U << 10) -#define GPIO_PIN_11 (1U << 11) -#define GPIO_PIN_12 (1U << 12) -#define GPIO_PIN_13 (1U << 13) -#define GPIO_PIN_14 (1U << 14) -#define GPIO_PIN_15 (1U << 15) -#define GPIO_PIN_ALL (0xFFFF) -/** - * @} - */ - -/** - * @defgroup GPIO_Public_Types GPIO Public Types - * @{ - */ - -/** - * @brief GPIO mode - */ -typedef enum -{ - GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */ - GPIO_MODE_INPUT = 0x1, /**< Input */ - GPIO_MODE_OUTPUT = 0x2, /**< Output */ -} gpio_mode_t; - -/** - * @brief GPIO open-drain or push-pull - */ -typedef enum -{ - GPIO_PUSH_PULL = 0x0, /**< Push-Pull */ - GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */ - GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */ -} gpio_odos_t; - -/** - * @brief GPIO push-up or push-down - */ -typedef enum -{ - GPIO_FLOATING = 0x0,/**< Floating */ - GPIO_PUSH_UP = 0x1,/**< Push-Up */ - GPIO_PUSH_DOWN = 0x2,/**< Push-Down */ - GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */ -} gpio_push_t; - -/** - * @brief GPIO output drive - */ -typedef enum -{ - GPIO_OUT_DRIVE_NORMAL = 0x0, /**< Normal current flow */ - GPIO_OUT_DRIVE_STRONG = 0x1, /**< Strong current flow */ -} gpio_out_drive_t; - -/** - * @brief GPIO filter - */ -typedef enum -{ - GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */ - GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */ -} gpio_filter_t; - -/** - * @brief GPIO type - */ -typedef enum -{ - GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */ - GPIO_TYPE_TTL = 0x1, /**< TTL Type */ -} gpio_type_t; - -/** - * @brief GPIO functions - */ -typedef enum -{ - GPIO_FUNC_0 = 0, /**< function #0 */ - GPIO_FUNC_1 = 1, /**< function #1 */ - GPIO_FUNC_2 = 2, /**< function #2 */ - GPIO_FUNC_3 = 3, /**< function #3 */ - GPIO_FUNC_4 = 4, /**< function #4 */ - GPIO_FUNC_5 = 5, /**< function #5 */ - GPIO_FUNC_6 = 6, /**< function #6 */ - GPIO_FUNC_7 = 7, /**< function #7 */ -} gpio_func_t; - - -/** - * @brief GPIO Init Structure definition - */ -typedef struct -{ - gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. - This parameter can be any value of @ref gpio_mode_t */ - gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. - This parameter can be a value of @ref gpio_odos_t */ - gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. - This parameter can be a value of @ref gpio_push_t */ - gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins. - This parameter can be a value of @ref gpio_out_drive_t */ - gpio_filter_t flt; /**< Specifies the input filter for the selected pins. - This parameter can be a value of @ref gpio_filter_t */ - gpio_type_t type; /**< Specifies the type for the selected pins. - This parameter can be a value of @ref gpio_type_t */ - gpio_func_t func; /**< Specifies the function for the selected pins. - This parameter can be a value of @ref gpio_func_t */ -} gpio_init_t; - -/** - * @brief EXTI trigger style - */ -typedef enum -{ - EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */ - EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */ - EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */ -} exti_trigger_style_t; - -/** - * @brief EXTI filter clock select - */ -typedef enum -{ - EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */ - EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */ -} exti_filter_clock_t; - -/** - * @brief EXTI Init Structure definition - */ -typedef struct -{ - type_func_t filter; /**< Enable filter. */ - exti_filter_clock_t cks; /**< Filter clock select. */ - uint8_t filter_time; /**< Filter duration */ -} exti_init_t; -/** - * @} - */ - -/** - * @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -#define PIN_MASK 0xFFFF -#define UNLOCK_KEY 0x55AA - -#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) -#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ - (GPIOx == GPIOB) || \ - (GPIOx == GPIOC) || \ - (GPIOx == GPIOD) || \ - (GPIOx == GPIOE) || \ - (GPIOx == GPIOF) || \ - (GPIOx == GPIOG) || \ - (GPIOx == GPIOH)) -#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \ - ((x) == GPIO_MODE_INPUT) || \ - ((x) == GPIO_MODE_OUTPUT)) -#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \ - ((x) == GPIO_OPEN_DRAIN) || \ - ((x) == GPIO_OPEN_SOURCE)) -#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \ - ((x) == GPIO_PUSH_UP) || \ - ((x) == GPIO_PUSH_DOWN) || \ - ((x) == GPIO_PUSH_UP_DOWN)) -#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \ - ((x) == GPIO_OUT_DRIVE_STRONG)) -#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \ - ((x) == GPIO_FILTER_ENABLE)) -#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \ - ((x) == GPIO_TYPE_CMOS)) -#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \ - ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \ - ((x) == EXTI_TRIGGER_BOTH_EDGE)) -#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \ - ((x) == EXTI_FILTER_CLOCK_32K)) -#define IS_GPIO_FUNC(x) ((x) <= 7) -/** - * @} - */ - -/** @addtogroup GPIO_Public_Functions - * @{ - */ - -/** @addtogroup GPIO_Public_Functions_Group1 - * @{ - */ -void gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init); -void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin); -void gpio_func_default(GPIO_TypeDef *GPIOx); -void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init); -/** - * @} - */ - -/** @addtogroup GPIO_Public_Functions_Group2 - * @{ - */ -uint8_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin); -void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val); -void gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin); -void gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin); -void gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin); -uint16_t gpio_read_port(GPIO_TypeDef *GPIOx); -void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val); -/** - * @} - */ - -/** @addtogroup GPIO_Public_Functions_Group3 - * @{ - */ -void gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status); -flag_status_t gpio_exti_get_flag_status(uint16_t pin); -void gpio_exti_clear_flag_status(uint16_t pin); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_GPIO_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h deleted file mode 100644 index f20384d7e194684a56a110b97ed5834af6776d46..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ /dev/null @@ -1,534 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_i2c.h - * @brief Header file of I2C driver - * - * @version V1.0 - * @date 15 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_I2C_H__ -#define __ALD_I2C_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" -#include "ald_cmu.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Public_Types I2C Public Types - * @{ - */ -/** - * @brief I2C Error Code - */ -typedef enum -{ - I2C_ERROR_NONE = 0x0, /**< No error */ - I2C_ERROR_BERR = 0x1, /**< Berr error */ - I2C_ERROR_ARLO = 0x2, /**< Arlo error */ - I2C_ERROR_AF = 0x4, /**< Af error */ - I2C_ERROR_OVR = 0x8, /**< Ovr error */ - I2C_ERROR_DMA = 0x10, /**< Dma error */ - I2C_ERROR_TIMEOUT = 0x20, /**< Timeout error */ -} i2c_error_t; - -/** - * @brief I2C state structure definition - */ -typedef enum -{ - I2C_STATE_RESET = 0x0, /**< Peripheral is not yet Initialized */ - I2C_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - I2C_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - I2C_STATE_BUSY_TX = 0x3, /**< Data Transmission process is ongoing */ - I2C_STATE_BUSY_RX = 0x4, /**< Data Reception process is ongoing */ - I2C_STATE_TIMEOUT = 0x5, /**< timeout state */ - I2C_STATE_ERROR = 0x6, /**< Error */ -} i2c_state_t; - -/** - * @brief I2C Duty Cycle - */ -typedef enum -{ - I2C_DUTYCYCLE_2 = 0x0, /**< duty cycle is 2 */ - I2C_DUTYCYCLE_16_9 = 0x4000, /**< duty cycle is 16/9 */ -} i2c_duty_t; - -/** - * @brief I2C Addressing Mode - */ -typedef enum -{ - I2C_ADDR_7BIT = 0x1, /**< 7 bit address */ - I2C_ADDR_10BIT = 0x2, /**< 10 bit address */ -} i2c_addr_t; - -/** - * @brief I2C Dual Addressing Mode - */ -typedef enum -{ - I2C_DUALADDR_DISABLE = 0x0, /**< dual address is disable */ - I2C_DUALADDR_ENABLE = 0x1, /**< dual address is enable */ -} i2c_dual_addr_t; - -/** - * @brief I2C General Call Addressing mode - */ -typedef enum -{ - I2C_GENERALCALL_DISABLE = 0x0, /**< feneral call address is disable */ - I2C_GENERALCALL_ENABLE = 0x40, /**< feneral call address is enable */ -} i2c_general_addr_t; - -/** - * @brief I2C Nostretch Mode - */ -typedef enum -{ - I2C_NOSTRETCH_DISABLE = 0x0, /**< Nostretch disable */ - I2C_NOSTRETCH_ENABLE = 0x80, /**< Nostretch enable */ -} i2c_nostretch_t; - -/** - * @brief I2C Memory Address Size - */ -typedef enum -{ - I2C_MEMADD_SIZE_8BIT = 0x1, /**< 8 bit memory address size */ - I2C_MEMADD_SIZE_16BIT = 0x10 /**< 10 bit memory address size */ -} i2c_addr_size_t; - -/** - * @brief I2C Flag Definition - */ -typedef enum -{ - I2C_FLAG_SB = (1U << 0), - I2C_FLAG_ADDR = (1U << 1), - I2C_FLAG_BTF = (1U << 2), - I2C_FLAG_ADD10 = (1U << 3), - I2C_FLAG_STOPF = (1U << 4), - I2C_FLAG_RXNE = (1U << 6), - I2C_FLAG_TXE = (1U << 7), - I2C_FLAG_BERR = (1U << 8), - I2C_FLAG_ARLO = (1U << 9), - I2C_FLAG_AF = (1U << 10), - I2C_FLAG_OVR = (1U << 11), - I2C_FLAG_PECERR = (1U << 12), - I2C_FLAG_TIMEOUT = (1U << 14), - I2C_FLAG_SMBALERT = (1U << 15), - I2C_FLAG_MSL = (1U << 16), - I2C_FLAG_BUSY = (1U << 17), - I2C_FLAG_TRA = (1U << 18), - I2C_FLAG_GENCALL = (1U << 20), - I2C_FLAG_SMBDEFAULT = (1U << 21), - I2C_FLAG_SMBHOST = (1U << 22), - I2C_FLAG_DUALF = (1U << 23), -} i2c_flag_t; - -/** - * @brief I2C mode structure definition - */ -typedef enum -{ - I2C_MODE_NONE = 0x0, /**< No I2C communication on going */ - I2C_MODE_MASTER = 0x10, /**< I2C communication is in Master mode */ - I2C_MODE_SLAVE = 0x20, /**< I2C communication is in Slave mode */ - I2C_MODE_MEM = 0x40, /**< I2C communication is in Memory mode */ -} i2c_mode_t; - -/** - * @brief I2C Clock - */ -typedef enum -{ - I2C_STANDARD_MODE_MAX_CLK = 100000, /**< Standard mode clock */ - I2C_FAST_MODE_MAX_CLK = 400000, /**< Fast mode clock */ -} i2c_clock_t; - -/** - * @brief Interrupt Configuration Definition - */ -typedef enum -{ - I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */ - I2C_IT_EVT = (1U << 9), /**< Event interrupt */ - I2C_IT_ERR = (1U << 8), /**< Error interrupt */ -} i2c_interrupt_t; - -/** - * @brief I2C CON1 Register - */ -typedef enum -{ - I2C_CON1_PEN = (1U << 0), /**< PEN BIT */ - I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */ - I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */ - I2C_CON1_ARPEN = (1U << 4), /**< ARPEN BIT */ - I2C_CON1_PECEN = (1U << 5), /**< PECEN BIT */ - I2C_CON1_GCEN = (1U << 6), /**< GCEN BIT */ - I2C_CON1_DISCS = (1U << 7), /**< DISCS BIT */ - I2C_CON1_START = (1U << 8), /**< START BIT */ - I2C_CON1_STOP = (1U << 9), /**< STOP BIT */ - I2C_CON1_ACKEN = (1U << 10), /**< ACKEN BIT */ - I2C_CON1_POSAP = (1U << 11), /**< POSAP BIT */ - I2C_CON1_TRPEC = (1U << 12), /**< TRPEC BIT */ - I2C_CON1_ALARM = (1U << 13), /**< ALARM BIT */ - I2C_CON1_SRST = (1U << 15), /**< SRST BIT */ -} i2c_con1_t; - -/** - * @brief I2C CON2 Register - */ -typedef enum -{ - I2C_CON2_CLKF = 0x3F, /**< CLKF BITS */ - I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */ - I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */ - I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */ - I2C_CON2_CLKF_3 = (1U << 3), /**< CLKF_3 BIT */ - I2C_CON2_CLKF_4 = (1U << 4), /**< CLKF_4 BIT */ - I2C_CON2_CLKF_5 = (1U << 5), /**< CLKF_5 BIT */ - I2C_CON2_ERRIE = (1U << 8), /**< ERRIE BIT */ - I2C_CON2_EVTIE = (1U << 9), /**< EVTIE BIT */ - I2C_CON2_BUFIE = (1U << 10), /**< BUFIE BIT */ - I2C_CON2_DMAEN = (1U << 11), /**< DMAEN BIT */ - I2C_CON2_LDMA = (1U << 12), /**< LDMA BIT */ -} i2c_con2_t; - -/** - * @brief I2C ADDR1 Register - */ -typedef enum -{ - I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */ - I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */ - I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */ - I2C_ADDR1_ADDH3 = (1U << 3), /**< ADDH3 BIT */ - I2C_ADDR1_ADDH4 = (1U << 4), /**< ADDH4 BIT */ - I2C_ADDR1_ADDH5 = (1U << 5), /**< ADDH5 BIT */ - I2C_ADDR1_ADDH6 = (1U << 6), /**< ADDH6 BIT */ - I2C_ADDR1_ADDH7 = (1U << 7), /**< ADDH7 BIT */ - I2C_ADDR1_ADDH8 = (1U << 8), /**< ADDH8 BIT */ - I2C_ADDR1_ADDH9 = (1U << 9), /**< ADDH9 BIT */ - I2C_ADDR1_ADDTYPE = (1U << 15), /**< ADDTYPE BIT */ -} i2c_addr1_t; - -/** - * @brief I2C ADDR2 Register - */ -typedef enum -{ - I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */ - I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */ -} i2c_addr2_t; - -/** - * @brief I2C STAT1 Register - */ -typedef enum -{ - I2C_STAT1_SB = (1U << 0), /**< SB BIT */ - I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */ - I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */ - I2C_STAT1_SENDADD10 = (1U << 3), /**< SENDADD10 BIT */ - I2C_STAT1_DETSTP = (1U << 4), /**< DETSTP BIT */ - I2C_STAT1_RXBNE = (1U << 6), /**< RXBNE BIT */ - I2C_STAT1_TXBE = (1U << 7), /**< TXBE BIT */ - I2C_STAT1_BUSERR = (1U << 8), /**< BUSERR BIT */ - I2C_STAT1_LARB = (1U << 9), /**< LARB BIT */ - I2C_STAT1_ACKERR = (1U << 10), /**< ACKERR BIT */ - I2C_STAT1_ROUERR = (1U << 11), /**< ROUERR BIT */ - I2C_STAT1_PECERR = (1U << 12), /**< PECERR BIT */ - I2C_STAT1_SMBTO = (1U << 14), /**< SMBTO BIT */ - I2C_STAT1_SMBALARM = (1U << 15), /**< SMBALARM BIT */ -} i2c_stat1_t; - -/** - * @brief I2C STAT2 Register - */ -typedef enum -{ - I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */ - I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */ - I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */ - I2C_STAT2_RXGCF = (1U << 4), /**< RXGCF BIT */ - I2C_STAT2_SMBDEF = (1U << 5), /**< SMBDEF BIT */ - I2C_STAT2_SMBHH = (1U << 6), /**< SMBHH BIT */ - I2C_STAT2_DUALF = (1U << 7), /**< DMF BIT */ - I2C_STAT2_PECV = (1U << 8), /**< PECV BIT */ -} i2c_stat2_t; - -/** - * @brief I2C CKCFG Register - */ -typedef enum -{ - I2C_CKCFG_CLKSET = 0xFFF, /**< CLKSET BITS */ - I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */ - I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */ -} i2c_ckcfg_t; - -/** - * @brief I2C RT Register - */ -typedef enum -{ - I2C_RT_RISET = 0x3F, /**< RISET BITS */ -} i2c_trise_t; - -/** - * @brief I2C Configuration Structure definition - */ -typedef struct -{ - uint32_t clk_speed; /**< Specifies the clock frequency */ - i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */ - uint32_t own_addr1; /**< Specifies the first device own address */ - i2c_addr_t addr_mode; /**< Specifies addressing mode */ - i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ - uint32_t own_addr2; /**< Specifies the second device own address */ - i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ - i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ -} i2c_init_t; - -/** - * @brief I2C handle Structure definition - */ -typedef struct i2c_handle_s -{ - I2C_TypeDef *perh; /**< I2C registers base address */ - i2c_init_t init; /**< I2C communication parameters */ - uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ - uint16_t xfer_size; /**< I2C transfer size */ - __IO uint16_t xfer_count; /**< I2C transfer counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ -#endif - lock_state_t lock; /**< I2C locking object */ - __IO i2c_state_t state; /**< I2C communication state */ - __IO i2c_mode_t mode; /**< I2C communication mode */ - __IO uint32_t error_code; /**< I2C Error code */ - - void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ - void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ - void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ - void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ - void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ - void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ - void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ -} i2c_handle_t; - -/** - * @} - */ - -/** @defgroup I2C_Public_Macro I2C Public Macros - * @{ - */ -#define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) -#define I2C_CLEAR_ADDRFLAG(x) \ -do { \ - __IO uint32_t tmpreg; \ - tmpreg = (x)->perh->STAT1; \ - tmpreg = (x)->perh->STAT2; \ - UNUSED(tmpreg); \ -} while (0) -#define __I2C_CLEAR_STOPFLAG(x) \ -do { \ - __IO uint32_t tmpreg; \ - tmpreg = (x)->perh->STAT1; \ - tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \ - UNUSED(tmpreg); \ -} while (0) -#define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) -#define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) -/** - * @} - */ - -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ -#define IS_I2C_TYPE(x) (((x) == I2C0) || \ - ((x) == I2C1)) -#define IS_I2C_ADDRESSING_MODE(x) (((x) == I2C_ADDR_7BIT) || \ - ((x) == I2C_ADDR_10BIT)) -#define IS_I2C_DUAL_ADDRESS(x) (((x) == I2C_DUALADDR_DISABLE) || \ - ((x) == I2C_DUALADDR_ENABLE)) -#define IS_I2C_GENERAL_CALL(x) (((x) == I2C_GENERALCALL_DISABLE) || \ - ((x) == I2C_GENERALCALL_ENABLE)) -#define IS_I2C_MEMADD_size(x) (((x) == I2C_MEMADD_SIZE_8BIT) || \ - ((x) == I2C_MEMADD_SIZE_16BIT)) -#define IS_I2C_NO_STRETCH(x) (((x) == I2C_NOSTRETCH_DISABLE) || \ - ((x) == I2C_NOSTRETCH_ENABLE)) -#define IS_I2C_OWN_ADDRESS1(x) (((x) & (uint32_t)(0xFFFFFC00)) == 0) -#define IS_I2C_OWN_ADDRESS2(x) (((x) & (uint32_t)(0xFFFFFF01)) == 0) -#define IS_I2C_CLOCK_SPEED(x) (((x) > 0) && ((x) <= I2C_FAST_MODE_MAX_CLK)) -#define IS_I2C_DUTY_CYCLE(x) (((x) == I2C_DUTYCYCLE_2) || \ - ((x) == I2C_DUTYCYCLE_16_9)) -#define IS_I2C_IT_TYPE(x) (((x) == I2C_IT_BUF) || \ - ((x) == I2C_IT_EVT) || \ - ((x) == I2C_IT_ERR)) -#define IS_I2C_FLAG(x) (((x) == I2C_FLAG_SB) || \ - ((x) == I2C_FLAG_ADDR) || \ - ((x) == I2C_FLAG_BTF) || \ - ((x) == I2C_FLAG_ADD10) || \ - ((x) == I2C_FLAG_STOPF) || \ - ((x) == I2C_FLAG_RXNE) || \ - ((x) == I2C_FLAG_TXE) || \ - ((x) == I2C_FLAG_BERR) || \ - ((x) == I2C_FLAG_ARLO) || \ - ((x) == I2C_FLAG_AF) || \ - ((x) == I2C_FLAG_OVR) || \ - ((x) == I2C_FLAG_PECERR) || \ - ((x) == I2C_FLAG_TIMEOUT) || \ - ((x) == I2C_FLAG_SMBALERT) || \ - ((x) == I2C_FLAG_MSL) || \ - ((x) == I2C_FLAG_BUSY) || \ - ((x) == I2C_FLAG_TRA) || \ - ((x) == I2C_FLAG_GENCALL) || \ - ((x) == I2C_FLAG_SMBDEFAULT) || \ - ((x) == I2C_FLAG_SMBHOST) || \ - ((x) == I2C_FLAG_DUALF)) - -#define I2C_FREQ_RANGE(x) ((x) / 1000000) -#define I2C_RISE_TIME(x, u) (((u) <= I2C_STANDARD_MODE_MAX_CLK) ? ((x) + 1) :\ - ((((x) * 300) / 1000) + 1)) -#define I2C_SPEED_STANDARD(x, y) (((((x) / ((y) << 1)) & I2C_CKCFG_CLKSET) < 4) ? 4:\ - ((x) / ((y) << 1))) -#define I2C_SPEED_FAST(x, y, z) (((z) == I2C_DUTYCYCLE_2) ? ((x) / ((y) * 3)) :\ - (((x) / ((y) * 25)) | I2C_DUTYCYCLE_16_9)) -#define I2C_SPEED(x, y, z) (((y) <= 100000) ? (I2C_SPEED_STANDARD((x), (y))) :\ - ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \ - ((I2C_SPEED_FAST((x), (y), (z))) | I2C_CKCFG_CLKMOD)) -#define I2C_MEM_ADD_MSB(x) ((uint8_t)((uint16_t)(((uint16_t)((x) &\ - (uint16_t)(0xFF00))) >> 8))) -#define I2C_MEM_ADD_LSB(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) -#define I2C_7BIT_ADD_WRITE(x) ((uint8_t)((x) & (~I2C_ADDR1_ADDH0))) -#define I2C_7BIT_ADD_READ(x) ((uint8_t)((x) | I2C_ADDR1_ADDH0)) -#define I2C_10BIT_ADDRESS(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) -#define I2C_10BIT_HEADER_WRITE(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ - (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) -#define I2C_10BIT_HEADER_READ(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ - (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions - * @{ - */ - -/** @addtogroup I2C_Public_Functions_Group1 - * @{ - */ -ald_status_t i2c_init(i2c_handle_t *hperh); -ald_status_t i2c_reset(i2c_handle_t *hperh); - -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions_Group2 - * @{ - */ -/** Blocking mode: Polling */ -ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout); - -/** Non-Blocking mode: Interrupt */ -ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); -ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); -ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); -ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); - -#ifdef ALD_DMA -/** Non-Blocking mode: DMA */ -ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); -#endif -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions_Group3 - * @{ - */ -i2c_state_t i2c_get_state(i2c_handle_t *hperh); -uint32_t i2c_get_error(i2c_handle_t *hperh); -flag_status_t i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); -flag_status_t i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it); -void i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions_Group4 - * @{ - */ -void i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state); -void i2c_ev_irq_handler(i2c_handle_t *hperh); -void i2c_er_irq_handler(i2c_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_I2C_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h deleted file mode 100644 index 3b7c12cf0f9fe75de5a6703d335d4fd32ab77f66..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h +++ /dev/null @@ -1,633 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_pis.h - * @brief Header file of PIS driver. - * - * @version V1.0 - * @date 27 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_PIS_H__ -#define __ALD_PIS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup PIS - * @{ - */ - -/** @defgroup PIS_Public_Types PIS Public Types - * @{ - */ - -/** - * @brief Producer entry - */ -typedef enum -{ - PIS_NON = 0x0, /**< No async */ - PIS_GPIO_PIN0 = 0x10, /**< Pin0, level,support async */ - PIS_GPIO_PIN1 = 0x11, /**< Pin1, level,support async */ - PIS_GPIO_PIN2 = 0x12, /**< Pin2, level,support async */ - PIS_GPIO_PIN3 = 0x13, /**< Pin3, level,support async */ - PIS_GPIO_PIN4 = 0x14, /**< Pin4, level,support async */ - PIS_GPIO_PIN5 = 0x15, /**< Pin5, level,support async */ - PIS_GPIO_PIN6 = 0x16, /**< Pin6, level,support async */ - PIS_GPIO_PIN7 = 0x17, /**< Pin7, level,support async */ - PIS_GPIO_PIN8 = 0x18, /**< Pin8, level,support async */ - PIS_GPIO_PIN9 = 0x19, /**< Pin9, level,support async */ - PIS_GPIO_PIN10 = 0x1a, /**< Pin10, level,support async */ - PIS_GPIO_PIN11 = 0x1b, /**< Pin11, level,support async */ - PIS_GPIO_PIN12 = 0x1c, /**< Pin12, level,support async */ - PIS_GPIO_PIN13 = 0x1d, /**< Pin13, level,support async */ - PIS_GPIO_PIN14 = 0x1e, /**< Pin14, level,support async */ - PIS_GPIO_PIN15 = 0x1f, /**< Pin15, level,support async */ - PIS_ACMP_OUT0 = 0x30, /**< Acmp0 output, level,support async */ - PIS_ACMP_OUT1 = 0x31, /**< Acmp1 output, level,support async */ - PIS_DAC0_CH0 = 0x40, /**< Dac0 channel 0, pclk2 pulse,support async */ - PIS_DAC0_CH1 = 0x41, /**< Dac0 channel 1, pclk2 pulse,support async */ - PIS_ADC0_INJECT = 0x60, /**< Adc0 inject, pclk2 pulse,support async */ - PIS_ADC0_REGULAT = 0x61, /**< Adc0 regulat, pclk2 pulse,support async */ - PIS_ADC0_WINDOW = 0x62, /**< Adc0 window, no have */ - PIS_LVD = 0x70, /**< Lvd, level,support async */ - PIS_UART0_ASY_SEND = 0x80, /**< Uart0 asy send, pulse,support async */ - PIS_UART0_ASY_RECV = 0x81, /**< Uart0 asy recv, pulse,support async */ - PIS_UART0_IRDAOUT = 0x82, /**< Uart0 irdaout, level,support async */ - PIS_UART0_RTSOUT = 0x83, /**< Uart0 rtsout, level,support async */ - PIS_UART0_TXOUT = 0x84, /**< Uart0 txout, level,support async */ - PIS_UART0_SYN_SEND = 0x85, /**< Uart0 syn send, pulse,support async */ - PIS_UART0_SYN_RECV = 0x86, /**< Uart0 syn recv, pulse,support async */ - PIS_UART1_ASY_SEND = 0x90, /**< Uart1 asy send, pulse,support async */ - PIS_UART1_ASY_RECV = 0x91, /**< Uart1 asy recv, pulse,support async */ - PIS_UART1_IRDA = 0x92, /**< Uart1 irdaout, level,support async */ - PIS_UART1_RTS = 0x93, /**< Uart1 rtsout, level,support async */ - PIS_UART1_TXOUT = 0x94, /**< Uart1 txout, level,support async */ - PIS_UART1_SYN_SEND = 0x95, /**< Uart1 syn send, pulse,support async */ - PIS_UART1_SYN_RECV = 0x96, /**< Uart1 syn recv, pulse,support async */ - PIS_UART2_ASY_SEND = 0xa0, /**< Uart2 asy send, pulse,support async */ - PIS_UART2_ASY_RECV = 0xa1, /**< Uart2 asy recv, pulse,support async */ - PIS_UART2_IRDA = 0xa2, /**< Uart2 irdaout, level,support async */ - PIS_UART2_RTS = 0xa3, /**< Uart2 rtsout, level,support async */ - PIS_UART2_TXOUT = 0xa4, /**< Uart2 txout, level,support async */ - PIS_UART2_SYN_SEND = 0xa5, /**< Uart2 syn send, pulse,support async */ - PIS_UART2_SYN_RECV = 0xa6, /**< Uart2 syn recv, pulse,support async */ - PIS_UART3_ASY_SEND = 0xb1, /**< Uart3 asy send, pulse,support async */ - PIS_UART3_ASY_RECV = 0xb2, /**< Uart3 asy recv, pulse,support async */ - PIS_UART3_IRDA = 0xb3, /**< Uart3 irdaout, level,support async */ - PIS_UART3_RTS = 0xb4, /**< Uart3 rtsout, level,support async */ - PIS_UART3_TXOUT = 0xb5, /**< Uart3 txout, level,support async */ - PIS_UART3_SYN_SEND = 0xb6, /**< Uart3 syn send, pulse,support async */ - PIS_UART3_SYN_RECV = 0xb7, /**< Uart3 syn recv, pulse,support async */ - PIS_EUART0_RECV = 0xc0, /**< Euart0 recv, plck1 pulse */ - PIS_EUART0_SEND = 0xc1, /**< Euart0 send, plck1 pulse */ - PIS_EUART0_TXOUT = 0xc2, /**< Euart0 txout, plck1 level */ - PIS_EUART1_RECV = 0xd0, /**< Euart1 recv, plck1 pulse */ - PIS_EUART1_SEND = 0xd1, /**< Euart1 send, plck1 pulse */ - PIS_EUART1_TXOUT = 0xd2, /**< Euart1 txout, plck1 level */ - PIS_SPI0_RECV = 0xe0, /**< Spi0 recv, plck1 pulse */ - PIS_SPI0_SEND = 0xe1, /**< Spi0 send, plck1 pulse */ - PIS_SPI0_NE = 0xe2, /**< Spi0 ne, plck1 level */ - PIS_SPI1_RECV = 0xf0, /**< Spi1 recv, plck1 pulse */ - PIS_SPI1_SEND = 0xf1, /**< Spi1 send, plck1 pulse */ - PIS_SPI1_NE = 0xf2, /**< Spi1 ne, plck1 level */ - PIS_I2C0_RECV = 0x100, /**< I2c0 recv, plck1 level */ - PIS_I2C0_SEND = 0x101, /**< I2c0 send, plck1 level */ - PIS_I2C1_RECV = 0x110, /**< I2c1 recv, plck1 level */ - PIS_I2C1_SEND = 0x111, /**< I2c1 send, plck1 level */ - PIS_TIMER0_UPDATA = 0x120, /**< Timer0 updata, plck1 pulse */ - PIS_TIMER0_TRIG = 0x121, /**< Timer0 trig, plck1 pulse */ - PIS_TIMER0_INPUT = 0x122, /**< Timer0 input, plck1 pulse */ - PIS_TIMER0_OUTPUT = 0x123, /**< Timer0 output, plck1 pulse */ - PIS_TIMER1_UPDATA = 0x130, /**< Timer1 updata, plck1 pulse */ - PIS_TIMER1_TRIG = 0x131, /**< Timer1 trig, plck1 pulse */ - PIS_TIMER1_INPUT = 0x132, /**< Timer1 input, plck1 pulse */ - PIS_TIMER1_OUTPUT = 0x133, /**< Timer1 output, plck1 pulse */ - PIS_TIMER2_UPDATA = 0x140, /**< Timer2 updata, plck1 pulse */ - PIS_TIMER2_TRIG = 0x141, /**< Timer2 trig, plck1 pulse */ - PIS_TIMER2_INPUT = 0x142, /**< Timer2 input, plck1 pulse */ - PIS_TIMER2_OUTPUT = 0x143, /**< Timer2 output, plck1 pulse */ - PIS_TIMER3_UPDATA = 0x150, /**< Timer0 updata, plck1 pulse */ - PIS_TIMER3_TRIG = 0x151, /**< Timer0 trig, plck1 pulse */ - PIS_TIMER3_INPUT = 0x152, /**< Timer0 input, plck1 pulse */ - PIS_TIMER3_OUTPUT = 0x153, /**< Timer0 output, plck1 pulse */ - PIS_RTC_CLOCK = 0x160, /**< Rtc clock, pulse,support async */ - PIS_RTC_ALARM = 0x161, /**< Rtc alarm, pulse,support async */ - PIS_LPTIM0_SYN_UPDATA = 0x170, /**< Lptimer0 syn updata, pulse,support async */ - PIS_LPTIM0_ASY_UPDATA = 0x171, /**< Lptimer0 asy updata, pulse,support async */ - PIS_LPUART0_ASY_RECV = 0x180, /**< Lpuart0 asy recv, pulse,support async */ - PIS_LPUART0_ASY_SEND = 0x181, /**< Lpuart0 asy send, pulse,support async */ - PIS_LPUART0_SYN_RECV = 0x182, /**< Lpuart0 syn recv, pulse,support async */ - PIS_LPUART0_SYN_SEND = 0x183, /**< Lpuart0 syn recv, pulse,support async */ - PIS_DMA = 0x190, /**< Dma, pulse,support async */ - PIS_ADC1_INJECT = 0x1a0, /**< Adc1 inject, pclk2 pulse,support async */ - PIS_ADC1_REGULAT = 0x1a1, /**< Adc1 regulat, pclk2 pulse,support async */ - PIS_ADC1_WINDOW = 0x1a2, /**< Adc1 window, no have */ -} pis_src_t; - -/** - * @brief Consumer entry - */ -typedef enum -{ - PIS_CH0_TIMER0_BRKIN = 0x4000, /**< Timer0 brkin */ - PIS_CH0_SPI1_CLK = 0xF010, /**< Spi1 clk */ - PIS_CH0_LPTIM0_EXT0 = 0x0030, /**< Lptimer0 ext0 */ - PIS_CH0_ADC1_NORMAL = 0x0030, /**< Adc1 normal */ - PIS_CH1_TIMER0_CH1IN = 0x0001, /**< Timer0 ch1in */ - PIS_CH1_TIMER2_CH1IN = 0x0101, /**< Timer2 ch1in */ - PIS_CH1_TIMER3_CH1IN = 0x8101, /**< Timer3 ch1in */ - PIS_CH1_LPTIM0_EXT1 = 0x0031, /**< Lptime0 ext1 */ - PIS_CH1_UART0_RX_IRDA = 0x0011, /**< Uart0 rx irda */ - PIS_CH1_ADC1_INSERT = 0x0031, /**< Adc1 insert */ - PIS_CH2_TIMER0_CH2IN = 0x1002, /**< Timer0 ch2in */ - PIS_CH2_TIMER2_CH2IN = 0x1102, /**< Timer2 ch2in */ - PIS_CH2_TIMER3_CH2IN = 0x9102, /**< Timer3 ch2in */ - PIS_CH2_LPTIM0_EXT2 = 0x0032, /**< Lptime0 ext2 */ - PIS_CH2_UART1_RX_IRDA = 0x1012, /**< Uart1 rx irda */ - PIS_CH3_TIMER0_CH3IN = 0x2003, /**< Timer0 ch3in */ - PIS_CH3_LPTIM0_EXT3 = 0x0033, /**< Lptime0 ext3 */ - PIS_CH3_UART2_RX_IRDA = 0x2013, /**< Uart2 rx irda */ - PIS_CH4_TIMER0_CH4IN = 0x0004, /**< Timer0 ch4in */ - PIS_CH4_TIMER0_ITR0 = 0x0034, /**< Timer0 itr0 */ - PIS_CH4_TIMER2_ITR0 = 0x0034, /**< Timer2 itr0 */ - PIS_CH4_TIMER3_ITR0 = 0x0034, /**< Timer3 itr0 */ - PIS_CH4_LPTIM0_EXT4 = 0x4034, /**< Lptime0 ext4 */ - PIS_CH4_UART3_RX_IRDA = 0x3014, /**< Uart3 rx irda */ - PIS_CH5_SPI0_RX = 0xC015, /**< Spi0 rx */ - PIS_CH5_LPTIM0_EXT5 = 0x0035, /**< Lptime0 ext5 */ - PIS_CH5_EUART0_RX = 0x6015, /**< Euart0 rx */ - PIS_CH5_TIMER0_ITR1 = 0x0035, /**< Timer0 itr1 */ - PIS_CH5_TIMER2_ITR1 = 0x0035, /**< Timer2 itr1 */ - PIS_CH5_TIMER3_ITR1 = 0x0035, /**< Timer3 itr1 */ - PIS_CH6_SPI0_CLK = 0xD016, /**< Spi0 clk */ - PIS_CH6_ADC0_NORMAL = 0x0036, /**< Adc0 normal */ - PIS_CH6_LPTIM0_EXT6 = 0x0036, /**< Lptime0 ext6 */ - PIS_CH6_EUART1_RX = 0x7016, /**< Euart1 rx */ - PIS_CH6_TIMER0_ITR2 = 0x0036, /**< Timer0 itr2 */ - PIS_CH6_TIMER2_ITR2 = 0x0036, /**< Timer2 itr2 */ - PIS_CH6_TIMER3_ITR2 = 0x0036, /**< Timer3 itr2 */ - PIS_CH6_DAC_CH1 = 0x0036, /**< Dac channel 1 */ - PIS_CH7_SPI1_RX = 0xE017, /**< Spi1 rx */ - PIS_CH7_ADC0_INSERT = 0x0037, /**< Adc0 insert */ - PIS_CH7_LPTIM0_EXT7 = 0x0037, /**< Lptime0 ext7 */ - PIS_CH7_DMA = 0x0037, /**< Dma */ - PIS_CH7_TIMER0_ITR3 = 0x0037, /**< Timer0 itr3 */ - PIS_CH7_TIMER2_ITR3 = 0x0037, /**< Timer2 itr3 */ - PIS_CH7_TIMER3_ITR3 = 0x0037, /**< Timer3 itr3 */ - PIS_CH7_LPUART_RX = 0x8017, /**< Lpuart rx */ - PIS_CH7_DAC_CH0 = 0x0037, /**< Dac channel 0 */ -} pis_trig_t; - -/** - * @brief Clock select - */ -typedef enum -{ - PIS_CLK_PCLK1 = 0, /**< Pclock1 */ - PIS_CLK_PCLK2 = 1, /**< Pclock2 */ - PIS_CLK_SYS = 2, /**< Sys clock */ - PIS_CLK_LP = 3, /**< Low power clock */ -} pis_clock_t; - -/** - * @brief Level select - */ -typedef enum -{ - PIS_EDGE_NONE = 0, /**< None edge */ - PIS_EDGE_UP = 1, /**< Up edge */ - PIS_EDGE_DOWN = 2, /**< Down edge */ - PIS_EDGE_UP_DOWN = 3, /**< Up and down edge */ -} pis_edge_t; - -/** - * @brief Output style - */ -typedef enum -{ - PIS_OUT_LEVEL = 0, /**< Level */ - PIS_OUT_PULSE = 1, /**< Pulse */ -} pis_output_t; -/** - * @brief Sync select - */ -typedef enum -{ - PIS_SYN_DIRECT = 0, /**< Direct */ - PIS_SYN_ASY_PCLK1 = 1, /**< Asy pclk1 */ - PIS_SYN_ASY_PCLK2 = 2, /**< Asy pclk2 */ - PIS_SYN_ASY_PCLK = 3, /**< Asy pclk */ - PIS_SYN_PCLK2_PCLK1 = 4, /**< Pclk2 to pclk1 */ - PIS_SYN_PCLK1_PCLK2 = 5, /**< Pclk1 to pclk2 */ - PIS_SYN_PCLK12_SYS = 6, /**< Pclk1 or pclk2 to sysclk */ -} pis_syncsel_t; - -/** - * @brief Pis channel - */ -typedef enum -{ - PIS_CH_0 = 0, /**< Channel 0 */ - PIS_CH_1 = 1, /**< Channel 1 */ - PIS_CH_2 = 2, /**< Channel 2 */ - PIS_CH_3 = 3, /**< Channel 3 */ - PIS_CH_4 = 4, /**< Channel 4 */ - PIS_CH_5 = 5, /**< Channel 5 */ - PIS_CH_6 = 6, /**< Channel 6 */ - PIS_CH_7 = 7, /**< Channel 7 */ -} pis_ch_t; - -/** - * @brief Pis output channel - */ -typedef enum -{ - PIS_OUT_CH_0 = 0, /**< Channel 0 */ - PIS_OUT_CH_1 = 1, /**< Channel 1 */ - PIS_OUT_CH_2 = 2, /**< Channel 2 */ - PIS_OUT_CH_3 = 3, /**< Channel 3 */ -} pis_out_ch_t; - -/** - * @brief Indirect value,no care of it. - */ -typedef enum -{ - PIS_CON_0 = 0, /**< Con 0 */ - PIS_CON_1 = 1, /**< Con 1 */ - PIS_CON_NONE = 2, /**< None */ -} pis_con_t; - -/** - * @brief Indirect value,no care of it. - */ -typedef union -{ - struct - { - uint8_t ch : 4; /**< Channel */ - uint8_t con : 4; /**< Contorl */ - uint8_t shift : 8; /**< Shift */ - }; - uint16_t HalfWord; -} pis_divide_t; - -/** - * @brief PIS state structures definition - */ -typedef enum -{ - PIS_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - PIS_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - PIS_STATE_BUSY = 0x02, /**< An internal process is ongoing */ - PIS_STATE_TIMEOUT = 0x03, /**< Timeout state */ - PIS_STATE_ERROR = 0x04, /**< Error */ -} pis_state_t; - -/** - * @brief PIS modulate target - */ -typedef enum -{ - PIS_UART0_TX = 0, /**< Modulate uart0 tx */ - PIS_UART1_TX = 1, /**< Modulate uart1 tx */ - PIS_UART2_TX = 2, /**< Modulate uart2 tx */ - PIS_UART3_TX = 3, /**< Modulate uart3 tx */ - PIS_LPUART0_TX = 4, /**< Modulate lpuart0 tx */ -} pis_modu_targ_t; - -/** - * @brief PIS modulate level - */ -typedef enum -{ - PIS_LOW_LEVEL = 0, /**< Modulate low level */ - PIS_HIGH_LEVEL = 1, /**< Modulate high level */ -} pis_modu_level_t; - -/** - * @brief PIS modulate source - */ -typedef enum -{ - PIS_SRC_NONE = 0, /**< Stop modulate */ - PIS_SRC_TIMER0 = 1, /**< Modulate source is TIMER0 */ - PIS_SRC_TIMER1 = 2, /**< Modulate source is TIMER1 */ - PIS_SRC_TIMER2 = 3, /**< Modulate source is TIMER2 */ - PIS_SRC_TIMER3 = 4, /**< Modulate source is TIMER3 */ - PIS_SRC_TIMER6 = 5, /**< Modulate source is TIMER6 */ - PIS_SRC_TIMER7 = 6, /**< Modulate source is TIMER7 */ - PIS_SRC_LPTIM0 = 7, /**< Modulate source is LPTIM0 */ - PIS_SRC_BUZ = 8, /**< Modulate source is buz */ -} pis_modu_src_t; - -/** - * @brief PIS modulate channel - */ -typedef enum -{ - PIS_TIMER_CH1 = 0, /**< Src is TIMERx and choose channel 1 */ - PIS_TIMER_CH2 = 1, /**< Src is TIMERx and choose channel 2 */ - PIS_TIMER_CH3 = 2, /**< Src is TIMERx and choose channel 3 */ - PIS_TIMER_CH4 = 3, /**< Src is TIMERx and choose channel 4 */ -} pis_modu_channel_t; - -/** - * @brief PIS init structure definition - */ -typedef struct -{ - pis_src_t producer_src; /**< Producer entry */ - pis_clock_t producer_clk; /**< Producer module clock */ - pis_edge_t producer_edge; /**< Producer module pin output edge */ - pis_trig_t consumer_trig; /**< Consumer entry */ - pis_clock_t consumer_clk; /**< Consumer clock */ -} pis_init_t; - -/** - * @brief PIS modulate config structure definition - */ -typedef struct -{ - pis_modu_targ_t target; /**< Modulate target */ - pis_modu_level_t level; /**< Modulate level */ - pis_modu_src_t src; /**< Modulate src */ - pis_modu_channel_t channel; /**< Modulate channel */ -} pis_modulate_config_t; - -/** - * @brief PIS Handle Structure definition - */ -typedef struct pis_handle_s -{ - PIS_TypeDef *perh; /**< Register base address */ - pis_init_t init; /**< PIS required parameters */ - pis_ch_t consumer_ch; /**< Indirect value, no care of it */ - pis_con_t consumer_con; /**< Indirect value, no care of it */ - uint8_t consumer_pos; /**< Indirect value, no care of it */ - uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ - lock_state_t lock; /**< Locking object */ - pis_state_t state; /**< PIS operation state */ -} pis_handle_t; -/** - * @} - */ - - -/** @defgroup PIS_Private_Macros PIS Private Macros - * @{ - */ -#define IS_PIS(x) (((x) == PIS)) -#define IS_PIS_SRC(x) (((x) == PIS_NON) || \ - ((x) == PIS_GPIO_PIN0) || \ - ((x) == PIS_GPIO_PIN1) || \ - ((x) == PIS_GPIO_PIN2) || \ - ((x) == PIS_GPIO_PIN3) || \ - ((x) == PIS_GPIO_PIN4) || \ - ((x) == PIS_GPIO_PIN5) || \ - ((x) == PIS_GPIO_PIN6) || \ - ((x) == PIS_GPIO_PIN7) || \ - ((x) == PIS_GPIO_PIN8) || \ - ((x) == PIS_GPIO_PIN9) || \ - ((x) == PIS_GPIO_PIN10) || \ - ((x) == PIS_GPIO_PIN11) || \ - ((x) == PIS_GPIO_PIN12) || \ - ((x) == PIS_GPIO_PIN13) || \ - ((x) == PIS_GPIO_PIN14) || \ - ((x) == PIS_GPIO_PIN15) || \ - ((x) == PIS_ACMP_OUT0) || \ - ((x) == PIS_ACMP_OUT1) || \ - ((x) == PIS_DAC0_CH1) || \ - ((x) == PIS_ACMP_OUT1) || \ - ((x) == PIS_ADC0_INJECT) || \ - ((x) == PIS_ADC0_REGULAT) || \ - ((x) == PIS_ADC0_WINDOW) || \ - ((x) == PIS_LVD) || \ - ((x) == PIS_UART0_ASY_SEND) || \ - ((x) == PIS_UART0_ASY_RECV) || \ - ((x) == PIS_UART0_IRDAOUT) || \ - ((x) == PIS_UART0_RTSOUT) || \ - ((x) == PIS_UART0_TXOUT) || \ - ((x) == PIS_UART0_SYN_SEND) || \ - ((x) == PIS_UART0_SYN_RECV) || \ - ((x) == PIS_UART1_ASY_SEND) || \ - ((x) == PIS_UART1_ASY_RECV) || \ - ((x) == PIS_UART1_IRDA) || \ - ((x) == PIS_UART1_RTS) || \ - ((x) == PIS_UART1_TXOUT) || \ - ((x) == PIS_UART1_SYN_SEND) || \ - ((x) == PIS_UART1_SYN_RECV) || \ - ((x) == PIS_UART2_ASY_SEND) || \ - ((x) == PIS_UART2_ASY_RECV) || \ - ((x) == PIS_UART2_IRDA) || \ - ((x) == PIS_UART2_RTS) || \ - ((x) == PIS_UART2_TXOUT) || \ - ((x) == PIS_UART2_SYN_SEND) || \ - ((x) == PIS_UART2_SYN_RECV) || \ - ((x) == PIS_UART3_ASY_SEND) || \ - ((x) == PIS_UART3_ASY_RECV) || \ - ((x) == PIS_UART3_IRDA) || \ - ((x) == PIS_UART3_RTS) || \ - ((x) == PIS_UART3_TXOUT) || \ - ((x) == PIS_UART3_SYN_SEND) || \ - ((x) == PIS_UART3_SYN_RECV) || \ - ((x) == PIS_EUART0_RECV) || \ - ((x) == PIS_EUART0_SEND) || \ - ((x) == PIS_EUART0_TXOUT) || \ - ((x) == PIS_EUART1_RECV) || \ - ((x) == PIS_EUART1_SEND) || \ - ((x) == PIS_EUART1_TXOUT) || \ - ((x) == PIS_SPI0_RECV) || \ - ((x) == PIS_SPI0_SEND) || \ - ((x) == PIS_SPI0_NE) || \ - ((x) == PIS_SPI1_RECV) || \ - ((x) == PIS_SPI1_SEND) || \ - ((x) == PIS_SPI1_NE) || \ - ((x) == PIS_I2C0_RECV) || \ - ((x) == PIS_I2C0_SEND) || \ - ((x) == PIS_I2C1_RECV) || \ - ((x) == PIS_I2C1_SEND) || \ - ((x) == PIS_TIMER0_UPDATA) || \ - ((x) == PIS_TIMER0_TRIG) || \ - ((x) == PIS_TIMER0_INPUT) || \ - ((x) == PIS_TIMER0_OUTPUT) || \ - ((x) == PIS_TIMER1_UPDATA) || \ - ((x) == PIS_TIMER1_TRIG) || \ - ((x) == PIS_TIMER1_INPUT) || \ - ((x) == PIS_TIMER1_OUTPUT) || \ - ((x) == PIS_TIMER2_UPDATA) || \ - ((x) == PIS_TIMER2_TRIG) || \ - ((x) == PIS_TIMER2_INPUT) || \ - ((x) == PIS_TIMER2_OUTPUT) || \ - ((x) == PIS_TIMER3_UPDATA) || \ - ((x) == PIS_TIMER3_TRIG) || \ - ((x) == PIS_TIMER3_INPUT) || \ - ((x) == PIS_TIMER3_OUTPUT) || \ - ((x) == PIS_RTC_CLOCK) || \ - ((x) == PIS_RTC_ALARM) || \ - ((x) == PIS_LPTIM0_SYN_UPDATA) || \ - ((x) == PIS_LPTIM0_ASY_UPDATA) || \ - ((x) == PIS_LPUART0_ASY_RECV) || \ - ((x) == PIS_LPUART0_ASY_SEND) || \ - ((x) == PIS_LPUART0_SYN_RECV) || \ - ((x) == PIS_LPUART0_SYN_SEND) || \ - ((x) == PIS_DMA) || \ - ((x) == PIS_ADC1_INJECT) || \ - ((x) == PIS_ADC1_REGULAT) || \ - ((x) == PIS_ADC1_WINDOW)) -#define IS_PIS_TRIG(x) (((x) == PIS_CH0_TIMER0_BRKIN) || \ - ((x) == PIS_CH0_SPI1_CLK) || \ - ((x) == PIS_CH0_LPTIM0_EXT0) || \ - ((x) == PIS_CH0_ADC1_NORMAL) || \ - ((x) == PIS_CH1_TIMER0_CH1IN) || \ - ((x) == PIS_CH1_TIMER2_CH1IN) || \ - ((x) == PIS_CH1_TIMER3_CH1IN) || \ - ((x) == PIS_CH1_UART0_RX_IRDA) || \ - ((x) == PIS_CH1_LPTIM0_EXT1) || \ - ((x) == PIS_CH1_ADC1_INSERT) || \ - ((x) == PIS_CH2_TIMER0_CH2IN) || \ - ((x) == PIS_CH2_TIMER2_CH2IN) || \ - ((x) == PIS_CH2_TIMER3_CH2IN) || \ - ((x) == PIS_CH2_LPTIM0_EXT2) || \ - ((x) == PIS_CH2_UART1_RX_IRDA) || \ - ((x) == PIS_CH3_TIMER0_CH3IN) || \ - ((x) == PIS_CH3_LPTIM0_EXT3) || \ - ((x) == PIS_CH3_UART2_RX_IRDA) || \ - ((x) == PIS_CH4_TIMER0_CH4IN) || \ - ((x) == PIS_CH4_TIMER0_ITR0) || \ - ((x) == PIS_CH4_TIMER2_ITR0) || \ - ((x) == PIS_CH4_TIMER3_ITR0) || \ - ((x) == PIS_CH4_LPTIM0_EXT4) || \ - ((x) == PIS_CH4_UART3_RX_IRDA) || \ - ((x) == PIS_CH5_SPI0_RX) || \ - ((x) == PIS_CH5_LPTIM0_EXT5) || \ - ((x) == PIS_CH5_EUART0_RX) || \ - ((x) == PIS_CH5_TIMER0_ITR1) || \ - ((x) == PIS_CH5_TIMER2_ITR1) || \ - ((x) == PIS_CH5_TIMER3_ITR1) || \ - ((x) == PIS_CH6_SPI0_CLK) || \ - ((x) == PIS_CH6_ADC0_NORMAL) || \ - ((x) == PIS_CH6_LPTIM0_EXT6) || \ - ((x) == PIS_CH6_EUART1_RX) || \ - ((x) == PIS_CH6_TIMER0_ITR2) || \ - ((x) == PIS_CH6_TIMER2_ITR2) || \ - ((x) == PIS_CH6_TIMER3_ITR2) || \ - ((x) == PIS_CH6_DAC_CH1) || \ - ((x) == PIS_CH7_SPI1_RX) || \ - ((x) == PIS_CH7_ADC0_INSERT) || \ - ((x) == PIS_CH7_LPTIM0_EXT7) || \ - ((x) == PIS_CH7_DMA) || \ - ((x) == PIS_CH7_TIMER0_ITR3) || \ - ((x) == PIS_CH7_TIMER2_ITR3) || \ - ((x) == PIS_CH7_TIMER3_ITR3) || \ - ((x) == PIS_CH7_DAC_CH0) || \ - ((x) == PIS_CH7_LPUART_RX)) -#define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \ - ((x) == PIS_CLK_PCLK2) || \ - ((x) == PIS_CLK_SYS) || \ - ((x) == PIS_CLK_LP)) -#define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \ - ((x) == PIS_EDGE_UP) || \ - ((x) == PIS_EDGE_DOWN) || \ - ((x) == PIS_EDGE_UP_DOWN)) -#define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \ - ((x) == PIS_OUT_PULSE)) -#define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \ - ((x) == PIS_OUT_CH_1) || \ - ((x) == PIS_OUT_CH_2) || \ - ((x) == PIS_OUT_CH_3)) -#define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \ - ((x) == PIS_UART1_TX) || \ - ((x) == PIS_UART2_TX) || \ - ((x) == PIS_UART3_TX) || \ - ((x) == PIS_LPUART0_TX)) -#define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \ - ((x) == PIS_HIGH_LEVEL)) -#define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \ - ((x) == PIS_SRC_TIMER0) || \ - ((x) == PIS_SRC_TIMER1) || \ - ((x) == PIS_SRC_TIMER2) || \ - ((x) == PIS_SRC_TIMER3) || \ - ((x) == PIS_SRC_TIMER6) || \ - ((x) == PIS_SRC_TIMER7) || \ - ((x) == PIS_SRC_LPTIM0) || \ - ((x) == PIS_SRC_BUZ)) -#define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \ - ((x) == PIS_TIMER_CH2) || \ - ((x) == PIS_TIMER_CH3) || \ - ((x) == PIS_TIMER_CH4)) -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions - * @{ - */ - -/** @addtogroup PIS_Public_Functions_Group1 - * @{ - */ -ald_status_t pis_create(pis_handle_t *hperh); -ald_status_t pis_destroy(pis_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions_Group2 - * @{ - */ -ald_status_t pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch); -ald_status_t pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch); -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions_Group3 - * @{ - */ -pis_state_t pis_get_state(pis_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions_Group4 - * @{ - */ -ald_status_t pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_PIS_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h deleted file mode 100644 index c7e3327e59d01baf9da61025daab5627c2ce01b5..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h +++ /dev/null @@ -1,241 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_pmu.h - * @brief Header file of PMU module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_PMU_H__ -#define __ALD_PMU_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_syscfg.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup PMU - * @{ - */ - -/** @defgroup PMU_Public_Macros PMU Public Macros - * @{ - */ -#define PMU_SRAM0_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_SRAM0_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_SRAM1_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_SRAM1_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_BXCAN_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_BXCAN_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) -/** - * @} - */ - - -/** @defgroup PMU_Public_Types PMU Public Types - * @{ - */ -/** - * @brief Standby wakeup port select - */ -typedef enum -{ - PMU_STANDBY_PORT_SEL_PA0 = 0x0, /**< PA0 */ - PMU_STANDBY_PORT_SEL_PA1 = 0x1, /**< PA1 */ - PMU_STANDBY_PORT_SEL_PA2 = 0x2, /**< PA2 */ - PMU_STANDBY_PORT_SEL_PA3 = 0x3, /**< PA3 */ - PMU_STANDBY_PORT_SEL_PA4 = 0x4, /**< PA4 */ - PMU_STANDBY_PORT_SEL_PA5 = 0x5, /**< PA5 */ - PMU_STANDBY_PORT_SEL_PA6 = 0x6, /**< PA6 */ - PMU_STANDBY_PORT_SEL_PA7 = 0x7, /**< PA7 */ - PMU_STANDBY_PORT_NONE = 0xF, /**< NONE */ -} pmu_standby_wakeup_sel_t; - -/** - * @brief Low power mode - */ -typedef enum -{ - PMU_LP_STOP1 = 0x0, /**< Stop1 */ - PMU_LP_STOP2 = 0x1, /**< Stop2 */ - PMU_LP_STANDBY = 0x2, /**< Standby */ -} pmu_lp_mode_t; - -typedef enum -{ - PMU_SR_WUF = (1U << 0), - PMU_SR_STANDBYF = (1U << 1), -} pmu_status_t; - -/** - * @brief LVD voltage select - */ -typedef enum -{ - PMU_LVD_VOL_SEL_2_0 = 0x0, /**< 2.0V ~ 2.05V */ - PMU_LVD_VOL_SEL_2_1 = 0x1, /**< 2.1V ~ 2.15V */ - PMU_LVD_VOL_SEL_2_2 = 0x2, /**< 2.2V ~ 2.25V */ - PMU_LVD_VOL_SEL_2_4 = 0x3, /**< 2.4V ~ 2.45V */ - PMU_LVD_VOL_SEL_2_6 = 0x4, /**< 2.6V ~ 2.65V */ - PMU_LVD_VOL_SEL_2_8 = 0x5, /**< 2.8V ~ 2.85V */ - PMU_LVD_VOL_SEL_3_0 = 0x6, /**< 3.0V ~ 3.05V */ - PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */ - PMU_LVD_VOL_SEL_4_0 = 0x8, /**< 4.0V ~ 4.05V */ - PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */ - PMU_LVD_VOL_SEL_2_3 = 0xA, /**< 2.3V ~ 2.35V */ - PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */ -} pmu_lvd_voltage_sel_t; - -/** - * @brief LVD trigger mode - */ -typedef enum -{ - PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */ - PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */ - PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */ - PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */ - PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */ -} pmu_lvd_trigger_mode_t; - -/** - * @} - */ - -/** - * @defgroup PMU_Private_Macros PMU Private Macros - * @{ - */ -#define IS_PMU_STANDBY_PORT_SEL(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA1) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA2) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA3) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA4) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA5) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA6) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA7) || \ - ((x) == PMU_STANDBY_PORT_NONE)) -#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \ - ((x) == PMU_LP_STOP2) || \ - ((x) == PMU_LP_STANDBY)) -#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || \ - ((x) == PMU_SR_STANDBYF)) -#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \ - ((x) == PMU_LVD_VOL_SEL_2_1) || \ - ((x) == PMU_LVD_VOL_SEL_2_2) || \ - ((x) == PMU_LVD_VOL_SEL_2_4) || \ - ((x) == PMU_LVD_VOL_SEL_2_6) || \ - ((x) == PMU_LVD_VOL_SEL_2_8) || \ - ((x) == PMU_LVD_VOL_SEL_3_0) || \ - ((x) == PMU_LVD_VOL_SEL_3_6) || \ - ((x) == PMU_LVD_VOL_SEL_4_0) || \ - ((x) == PMU_LVD_VOL_SEL_4_6) || \ - ((x) == PMU_LVD_VOL_SEL_2_3) || \ - ((x) == PMU_LVD_VOL_SEL_EXT)) -#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \ - ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \ - ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \ - ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \ - ((x) == PMU_LVD_TRIGGER_RISING_FALLING)) -/** - * @} - */ - -/** @addtogroup PMU_Public_Functions - * @{ - */ -/** @addtogroup PMU_Public_Functions_Group1 - * @{ - */ -/* Low power mode select */ -__STATIC_INLINE__ void __sleep() -{ - __WFI(); -} - -__STATIC_INLINE__ void __sleep_deep() -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); -} - -void pmu_stop1_enter(void); -void pmu_stop2_enter(void); -void pmu_standby_enter(pmu_standby_wakeup_sel_t port); -flag_status_t pmu_get_status(pmu_status_t sr); -void pmu_clear_status(pmu_status_t sr); -/** - * @} - */ -/** @addtogroup PMU_Public_Functions_Group2 - * @{ - */ -/* LVD configure */ -void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state); -void lvd_irq_cbk(void); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_PMU_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h deleted file mode 100644 index 22b8fd21a13eb044fb73c67268a2cbcea857dc3b..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h +++ /dev/null @@ -1,265 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_rmu.h - * @brief Header file of RMU module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_RMU_H__ -#define __ALD_RMU_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup RMU - * @{ - */ - -/** @defgroup RMU_Public_Types RMU Public Types - * @{ - */ -/** - * @brief RMU BOR fliter - */ -typedef enum -{ - RMU_BORFLT_1 = 0x1, /**< 1 cycle */ - RMU_BORFLT_2 = 0x2, /**< 2 cycles */ - RMU_BORFLT_3 = 0x3, /**< 3 cycles */ - RMU_BORFLT_4 = 0x4, /**< 4 cycles */ - RMU_BORFLT_5 = 0x5, /**< 5 cycles */ - RMU_BORFLT_6 = 0x6, /**< 6 cycles */ - RMU_BORFLT_7 = 0x7, /**< 7 cycles */ -} rmu_bor_filter_t; - -/** - * @brief RMU BOR voltage - */ -typedef enum -{ - RMU_VOL_1_7 = 0x0, /**< 1.7V */ - RMU_VOL_2_0 = 0x1, /**< 2.0V */ - RMU_VOL_2_1 = 0x2, /**< 2.1V */ - RMU_VOL_2_2 = 0x3, /**< 2.2V */ - RMU_VOL_2_3 = 0x4, /**< 2.3V */ - RMU_VOL_2_4 = 0x5, /**< 2.4V */ - RMU_VOL_2_5 = 0x6, /**< 2.5V */ - RMU_VOL_2_6 = 0x7, /**< 2.6V */ - RMU_VOL_2_8 = 0x8, /**< 2.8V */ - RMU_VOL_3_0 = 0x9, /**< 3.0V */ - RMU_VOL_3_1 = 0xA, /**< 3.1V */ - RMU_VOL_3_3 = 0xB, /**< 3.3V */ - RMU_VOL_3_6 = 0xC, /**< 3.6V */ - RMU_VOL_3_7 = 0xD, /**< 3.7V */ - RMU_VOL_4_0 = 0xE, /**< 4.0V */ - RMU_VOL_4_3 = 0xF, /**< 4.3V */ -} rmu_bor_vol_t; - -/** - * @brief RMU reset status - */ -typedef enum -{ - RMU_RST_POR = (1U << 0), /**< POR */ - RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ - RMU_RST_BOR = (1U << 2), /**< BOR */ - RMU_RST_NMRST = (1U << 3), /**< NMRST */ - RMU_RST_IWDT = (1U << 4), /**< IWDT */ - RMU_RST_WWDT = (1U << 5), /**< WWDT */ - RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ - RMU_RST_CHIP = (1U << 7), /**< CHIP */ - RMU_RST_MCU = (1U << 8), /**< MCU */ - RMU_RST_CPU = (1U << 9), /**< CPU */ - RMU_RST_CFG = (1U << 10), /**< CFG */ - RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ -} rmu_state_t; - -/** - * @brief RMU periperal select bit - */ -typedef enum -{ - RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ - RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ - RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ - RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ - RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ - RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ - RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ - RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ - RMU_PERH_TIM0 = (1U << 0) | (1U << 28), /**< APB1: TIM0 */ - RMU_PERH_TIM1 = (1U << 1) | (1U << 28), /**< APB1: TIM1 */ - RMU_PERH_TIM2 = (1U << 2) | (1U << 28), /**< APB1: TIM2 */ - RMU_PERH_TIM3 = (1U << 3) | (1U << 28), /**< APB1: TIM3 */ - RMU_PERH_TIM4 = (1U << 4) | (1U << 28), /**< APB1: TIM4 */ - RMU_PERH_TIM5 = (1U << 5) | (1U << 28), /**< APB1: TIM5 */ - RMU_PERH_TIM6 = (1U << 6) | (1U << 28), /**< APB1: TIM6 */ - RMU_PERH_TIM7 = (1U << 7) | (1U << 28), /**< APB1: TIM7 */ - RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ - RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ - RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ - RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ - RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */ - RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */ - RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ - RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ - RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ - RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ - RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ - RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ - RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ - RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ - RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ - RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ - RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ - RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ - RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ - RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ - RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ - RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ - RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ - RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ - RMU_PERH_TEMP = (1U << 16) | (1U << 29), /**< APB2: TEMP */ - RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ - RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ -} rmu_peripheral_t; -/** - * @} - */ - -/** - * @defgroup RMU_Private_Macros RMU Private Macros - * @{ - */ -#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \ - ((x) == RMU_BORFLT_2) || \ - ((x) == RMU_BORFLT_3) || \ - ((x) == RMU_BORFLT_4) || \ - ((x) == RMU_BORFLT_5) || \ - ((x) == RMU_BORFLT_6) || \ - ((x) == RMU_BORFLT_7)) -#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_7) || \ - ((x) == RMU_VOL_2_0) || \ - ((x) == RMU_VOL_2_1) || \ - ((x) == RMU_VOL_2_2) || \ - ((x) == RMU_VOL_2_3) || \ - ((x) == RMU_VOL_2_4) || \ - ((x) == RMU_VOL_2_5) || \ - ((x) == RMU_VOL_2_6) || \ - ((x) == RMU_VOL_2_8) || \ - ((x) == RMU_VOL_3_0) || \ - ((x) == RMU_VOL_3_1) || \ - ((x) == RMU_VOL_3_3) || \ - ((x) == RMU_VOL_3_6) || \ - ((x) == RMU_VOL_3_7) || \ - ((x) == RMU_VOL_4_0) || \ - ((x) == RMU_VOL_4_3)) -#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \ - ((x) == RMU_RST_WAKEUP) || \ - ((x) == RMU_RST_BOR) || \ - ((x) == RMU_RST_NMRST) || \ - ((x) == RMU_RST_IWDT) || \ - ((x) == RMU_RST_WWDT) || \ - ((x) == RMU_RST_LOCKUP) || \ - ((x) == RMU_RST_CHIP) || \ - ((x) == RMU_RST_MCU) || \ - ((x) == RMU_RST_CPU) || \ - ((x) == RMU_RST_CFG) || \ - ((x) == RMU_RST_CFGERR)) -#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \ - ((x) == RMU_RST_WAKEUP) || \ - ((x) == RMU_RST_BOR) || \ - ((x) == RMU_RST_NMRST) || \ - ((x) == RMU_RST_IWDT) || \ - ((x) == RMU_RST_WWDT) || \ - ((x) == RMU_RST_LOCKUP) || \ - ((x) == RMU_RST_CHIP) || \ - ((x) == RMU_RST_MCU) || \ - ((x) == RMU_RST_CPU) || \ - ((x) == RMU_RST_CFG)) -#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \ - ((x) == RMU_PERH_CRC) || \ - ((x) == RMU_PERH_CALC) || \ - ((x) == RMU_PERH_CRYPT) || \ - ((x) == RMU_PERH_TRNG) || \ - ((x) == RMU_PERH_PIS) || \ - ((x) == RMU_PERH_CHIP) || \ - ((x) == RMU_PERH_CPU) || \ - ((x) == RMU_PERH_TIM0) || \ - ((x) == RMU_PERH_TIM1) || \ - ((x) == RMU_PERH_TIM2) || \ - ((x) == RMU_PERH_TIM3) || \ - ((x) == RMU_PERH_TIM4) || \ - ((x) == RMU_PERH_TIM5) || \ - ((x) == RMU_PERH_TIM6) || \ - ((x) == RMU_PERH_TIM7) || \ - ((x) == RMU_PERH_UART0) || \ - ((x) == RMU_PERH_UART1) || \ - ((x) == RMU_PERH_UART2) || \ - ((x) == RMU_PERH_UART3) || \ - ((x) == RMU_PERH_USART0) || \ - ((x) == RMU_PERH_USART1) || \ - ((x) == RMU_PERH_SPI0) || \ - ((x) == RMU_PERH_SPI1) || \ - ((x) == RMU_PERH_SPI2) || \ - ((x) == RMU_PERH_I2C0) || \ - ((x) == RMU_PERH_I2C1) || \ - ((x) == RMU_PERH_CAN0) || \ - ((x) == RMU_PERH_LPTIM0) || \ - ((x) == RMU_PERH_LPUART0) || \ - ((x) == RMU_PERH_ADC0) || \ - ((x) == RMU_PERH_ADC1) || \ - ((x) == RMU_PERH_ACMP0) || \ - ((x) == RMU_PERH_ACMP1) || \ - ((x) == RMU_PERH_OPAMP) || \ - ((x) == RMU_PERH_DAC0) || \ - ((x) == RMU_PERH_WWDT) || \ - ((x) == RMU_PERH_LCD) || \ - ((x) == RMU_PERH_IWDT) || \ - ((x) == RMU_PERH_RTC) || \ - ((x) == RMU_PERH_TEMP) || \ - ((x) == RMU_PERH_BKPC) || \ - ((x) == RMU_PERH_BKPRAM)) -/** - * @} - */ - -/** @addtogroup RMU_Public_Functions - * @{ - */ -void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state); -flag_status_t rmu_get_reset_status(rmu_state_t state); -void rmu_clear_reset_status(rmu_state_t state); -void rmu_reset_periperal(rmu_peripheral_t perh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_RMU_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h deleted file mode 100644 index 9d0bce383f27b04dedbe1a93d052241d9c16ec21..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h +++ /dev/null @@ -1,699 +0,0 @@ -/** - ****************************************************************************** - * @file ald_rtc.h - * @brief Header file of RTC Module driver. - * - * @version V1.0 - * @date 16 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************* - */ - -#ifndef __ALD_RTC_H__ -#define __ALD_RTC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/** @defgroup RTC_Public_Types RTC Public Types - * @{ - */ - -/** - * @brief Hours format - */ -typedef enum -{ - RTC_HOUR_FORMAT_24 = 0x0, /**< 24-hours format */ - RTC_HOUR_FORMAT_12 = 0x1, /**< 12-hours format */ -} rtc_hour_format_t; - -/** - * @brief Output mode - */ -typedef enum -{ - RTC_OUTPUT_DISABLE = 0x0, /**< Disable output */ - RTC_OUTPUT_ALARM_A = 0x1, /**< Output alarm_a signal */ - RTC_OUTPUT_ALARM_B = 0x2, /**< Output alarm_b signal */ - RTC_OUTPUT_WAKEUP = 0x3, /**< Output wakeup signal */ -} rtc_output_select_t; - -/** - * @brief Output polarity - */ -typedef enum -{ - RTC_OUTPUT_POLARITY_HIGH = 0x0, /**< Polarity is high */ - RTC_OUTPUT_POLARITY_LOW = 0x0, /**< Polarity is low */ -} rtc_output_polarity_t; - -/** - * @brief Initialization structure - */ -typedef struct -{ - rtc_hour_format_t hour_format; /**< Hours format */ - uint32_t asynch_pre_div; /**< Asynchronous predivider value */ - uint32_t synch_pre_div; /**< Synchronous predivider value */ - rtc_output_select_t output; /**< Output signal type */ - rtc_output_polarity_t output_polarity; /**< Output polarity */ -} rtc_init_t; - -/** - * @brief Source select - */ -typedef enum -{ - RTC_SOURCE_LOSC = 0x0, /**< LOSC */ - RTC_SOURCE_LRC = 0x1, /**< LRC */ - RTC_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ - RTC_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ -} rtc_source_sel_t; - -/** - * @brief Time structure - */ -typedef struct -{ - uint8_t hour; /**< Hours */ - uint8_t minute; /**< Minutes */ - uint8_t second; /**< Seconds */ - uint16_t sub_sec; /**< Sub-seconds */ -} rtc_time_t; - -/** - * @brief Date structure - */ -typedef struct -{ - uint8_t week; /**< Weeks */ - uint8_t day; /**< days */ - uint8_t month; /**< months */ - uint8_t year; /**< years */ -} rtc_date_t; - -/** - * @brief Data format - */ -typedef enum -{ - RTC_FORMAT_DEC = 0, - RTC_FORMAT_BCD = 1, -} rtc_format_t; - -/** - * @brief Index of alarm - */ -typedef enum -{ - RTC_ALARM_A = 0x0, /**< Alarm-A */ - RTC_ALARM_B = 0x1, /**< Alarm-B */ -} rtc_alarm_idx_t; - -/** - * @brief Alarm mask - */ -typedef enum -{ - RTC_ALARM_MASK_NONE = 0x0, /**< Mask is disable */ - RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ - RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ - RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ - RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ - RTC_ALARM_MASK_ALL = 0x40808080, /**< Mask all */ -} rtc_alarm_mask_t; - -/** - * @brief Alarm sub-second mask - */ -typedef enum -{ - RTC_ALARM_SS_MASK_NONE = 0xF, /**< Mask is disable */ - RTC_ALARM_SS_MASK_14_1 = 0x1, /**< Mask bit(1-14) */ - RTC_ALARM_SS_MASK_14_2 = 0x2, /**< Mask bit(2-14) */ - RTC_ALARM_SS_MASK_14_3 = 0x3, /**< Mask bit(3-14) */ - RTC_ALARM_SS_MASK_14_4 = 0x4, /**< Mask bit(4-14) */ - RTC_ALARM_SS_MASK_14_5 = 0x5, /**< Mask bit(5-14) */ - RTC_ALARM_SS_MASK_14_6 = 0x6, /**< Mask bit(6-14) */ - RTC_ALARM_SS_MASK_14_7 = 0x7, /**< Mask bit(7-14) */ - RTC_ALARM_SS_MASK_14_8 = 0x8, /**< Mask bit(8-14) */ - RTC_ALARM_SS_MASK_14_9 = 0x9, /**< Mask bit(9-14) */ - RTC_ALARM_SS_MASK_14_10 = 0xA, /**< Mask bit(10-14) */ - RTC_ALARM_SS_MASK_14_11 = 0xB, /**< Mask bit(11-14) */ - RTC_ALARM_SS_MASK_14_12 = 0xC, /**< Mask bit(12-14) */ - RTC_ALARM_SS_MASK_14_13 = 0xD, /**< Mask bit(13-14) */ - RTC_ALARM_SS_MASK_14 = 0xE, /**< Mask bit14 */ - RTC_ALARM_SS_MASK_ALL = 0x0, /**< Mask bit(0-14) */ -} rtc_sub_second_mask_t; - -/** - * @brief Alarm select week or day */ -typedef enum -{ - RTC_SELECT_DAY = 0x0, /**< Alarm select day */ - RTC_SELECT_WEEK = 0x1, /**< Alarm select week */ -} rtc_week_day_sel_t; - -/** - * @brief Alarm structure - */ -typedef struct -{ - rtc_alarm_idx_t idx; /**< Index of alarm */ - rtc_time_t time; /**< Time structure */ - uint32_t mask; /**< Alarm mask */ - rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ - rtc_week_day_sel_t sel; /**< Select week or day */ - - union - { - uint8_t week; /**< Alarm select week */ - uint8_t day; /**< Alarm select day */ - }; -} rtc_alarm_t; - -/** - * @brief Time stamp signel select - */ -typedef enum -{ - RTC_TS_SIGNAL_SEL_TAMPER0 = 0, /**< Select tamper0 */ - RTC_TS_SIGNAL_SEL_TAMPER1 = 1, /**< Select tamper1 */ -} rtc_ts_signal_sel_t; - -/** - * @brief Time stamp trigger style - */ -typedef enum -{ - RTC_TS_RISING_EDGE = 0, /**< Rising edge */ - RTC_TS_FALLING_EDGE = 1, /**< Falling edge */ -} rtc_ts_trigger_style_t; - -/** - * @brief Index of tamper - */ -typedef enum -{ - RTC_TAMPER_0 = 0, /**< Tamper0 */ - RTC_TAMPER_1 = 1, /**< Tamper1 */ -} rtc_tamper_idx_t; - -/** - * @brief Tamper trigger type - */ -typedef enum -{ - RTC_TAMPER_TRIGGER_LOW = 0, /**< High trigger */ - RTC_TAMPER_TRIGGER_HIGH = 1, /**< Low trigger */ -} rtc_tamper_trigger_t; - -/** - * @brief Tamper sampling frequency - */ -typedef enum -{ - RTC_TAMPER_SAMPLING_FREQ_32768 = 0, /**< RTCCLK / 32768 */ - RTC_TAMPER_SAMPLING_FREQ_16384 = 1, /**< RTCCLK / 16384 */ - RTC_TAMPER_SAMPLING_FREQ_8192 = 2, /**< RTCCLK / 8192 */ - RTC_TAMPER_SAMPLING_FREQ_4096 = 3, /**< RTCCLK / 4096 */ - RTC_TAMPER_SAMPLING_FREQ_2048 = 4, /**< RTCCLK / 2048 */ - RTC_TAMPER_SAMPLING_FREQ_1024 = 5, /**< RTCCLK / 1024 */ - RTC_TAMPER_SAMPLING_FREQ_512 = 6, /**< RTCCLK / 512 */ - RTC_TAMPER_SAMPLING_FREQ_256 = 7, /**< RTCCLK / 256 */ -} rtc_tamper_sampling_freq_t; - -/** - * @brief Tamper filter time - */ -typedef enum -{ - RTC_TAMPER_DURATION_1 = 0, /**< Duration 1 sampling */ - RTC_TAMPER_DURATION_2 = 1, /**< Duration 2 sampling */ - RTC_TAMPER_DURATION_4 = 2, /**< Duration 4 sampling */ - RTC_TAMPER_DURATION_8 = 3, /**< Duration 8 sampling */ -} rtc_tamper_duration_t; - -/** - * @brief Tamper structure - */ -typedef struct -{ - rtc_tamper_idx_t idx; /**< Index of tamper */ - rtc_tamper_trigger_t trig; /**< Trigger type */ - rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ - rtc_tamper_duration_t dur; /**< Filter time */ - type_func_t ts; /**< Enable/Disable trigger time stamp event */ -} rtc_tamper_t; - -/** - * @brief Wake-up clock - */ -typedef enum -{ - RTC_WAKEUP_CLOCK_DIV_16 = 0, /**< RTCCLK / 16 */ - RTC_WAKEUP_CLOCK_DIV_8 = 1, /**< RTCCLK / 8 */ - RTC_WAKEUP_CLOCK_DIV_4 = 2, /**< RTCCLK / 4 */ - RTC_WAKEUP_CLOCK_DIV_2 = 3, /**< RTCCLK / 2 */ - RTC_WAKEUP_CLOCK_1HZ = 4, /**< 1Hz */ - RTC_WAKEUP_CLOCK_1HZ_PULS = 6, /**< 1Hz and WUT + 65536 */ -} rtc_wakeup_clock_t; - -/** - * @brief RTC clock output type - */ -typedef enum -{ - RTC_CLOCK_OUTPUT_32768 = 0, /**< 32768Hz */ - RTC_CLOCK_OUTPUT_1024 = 1, /**< 1024Hz */ - RTC_CLOCK_OUTPUT_32 = 2, /**< 32Hz */ - RTC_CLOCK_OUTPUT_1 = 3, /**< 1Hz */ - RTC_CLOCK_OUTPUT_CAL_1 = 4, /**< 1Hz after calibration */ - RTC_CLOCK_OUTPUT_EXA_1 = 5, /**< Exact 1Hz */ -} rtc_clock_output_t; - -/** - * @ Calibration frequency - */ -typedef enum -{ - RTC_CALI_FREQ_10_SEC = 0, /**< Calibrate every 10 seconds */ - RTC_CALI_FREQ_20_SEC = 1, /**< Calibrate every 20 seconds */ - RTC_CALI_FREQ_1_MIN = 2, /**< Calibrate every 1 minute */ - RTC_CALI_FREQ_2_MIN = 3, /**< Calibrate every 2 minutes */ - RTC_CALI_FREQ_5_MIN = 4, /**< Calibrate every 5 minutes */ - RTC_CALI_FREQ_10_MIN = 5, /**< Calibrate every 10 minutes */ - RTC_CALI_FREQ_20_MIN = 6, /**< Calibrate every 20 minutes */ - RTC_CALI_FREQ_1_SEC = 7, /**< Calibrate every 1 second */ -} rtc_cali_freq_t; - -/** - * @brief Temperature compensate type - */ -typedef enum -{ - RTC_CALI_TC_NONE = 0, /**< Temperature compensate disable */ - RTC_CALI_TC_AUTO_BY_HW = 1, /**< Temperature compensate by hardware */ - RTC_CALI_TC_AUTO_BY_SF = 2, /**< Temperature compensate by software */ - RTC_CALI_TC_AUTO_BY_HW_SF = 3, /**< Temperature compensate by hardware, trigger by software */ -} rtc_cali_tc_t; - -/** - * @ Calculate frequency - */ -typedef enum -{ - RTC_CALI_CALC_FREQ_10_SEC = 0, /**< Calculate every 10 seconds */ - RTC_CALI_CALC_FREQ_20_SEC = 1, /**< Calculate every 20 seconds */ - RTC_CALI_CALC_FREQ_1_MIN = 2, /**< Calculate every 1 minute */ - RTC_CALI_CALC_FREQ_2_MIN = 3, /**< Calculate every 2 minutes */ - RTC_CALI_CALC_FREQ_5_MIN = 4, /**< Calculate every 5 minutes */ - RTC_CALI_CALC_FREQ_10_MIN = 5, /**< Calculate every 10 minutes */ - RTC_CALI_CALC_FREQ_20_MIN = 6, /**< Calculate every 20 minutes */ - RTC_CALI_CALC_FREQ_1_HOUR = 7, /**< Calculate every 1 hour */ -} rtc_cali_calc_freq_t; - -/** - * @brief Calibration algorithm - */ -typedef enum -{ - RTC_CALI_CALC_4 = 0, /**< 4-polynomial */ - RTC_CALI_CALC_2 = 1, /**< 2-parabola */ -} rtc_cali_calc_t; - -/** - * @brief Calibration structure - */ -typedef struct -{ - rtc_cali_freq_t cali_freq; /**< calibrate frequency */ - rtc_cali_tc_t tc; /**< Temperature compensate type */ - rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ - rtc_cali_calc_t calc; /**< algorithm */ - type_func_t acc; /**< Enable/Disable decimal accumulate */ -} rtc_cali_t; - -/** - * @brief Interrupt type - */ -typedef enum -{ - RTC_IT_SEC = (1U << 0), /**< Second */ - RTC_IT_MIN = (1U << 1), /**< Minute */ - RTC_IT_HR = (1U << 2), /**< Hour */ - RTC_IT_DAY = (1U << 3), /**< Day */ - RTC_IT_MON = (1U << 4), /**< Month */ - RTC_IT_YR = (1U << 5), /**< Year */ - RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ - RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ - RTC_IT_TS = (1U << 10), /**< Time stamp */ - RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ - RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ - RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ - RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ - RTC_IT_SFC = (1U << 17), /**< Shift complete */ - RTC_IT_WU = (1U << 18), /**< Wake-up */ - RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ - RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ -} rtc_it_t; - -/** - * @brief Interrupt flag - */ -typedef enum -{ - RTC_IF_SEC = (1U << 0), /**< Second */ - RTC_IF_MIN = (1U << 1), /**< Minute */ - RTC_IF_HR = (1U << 2), /**< Hour */ - RTC_IF_DAY = (1U << 3), /**< Day */ - RTC_IF_MON = (1U << 4), /**< Month */ - RTC_IF_YR = (1U << 5), /**< Year */ - RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ - RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ - RTC_IF_TS = (1U << 10), /**< Time stamp */ - RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ - RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ - RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ - RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ - RTC_IF_SFC = (1U << 17), /**< Shift complete */ - RTC_IF_WU = (1U << 18), /**< Wake-up */ - RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ - RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ -} rtc_flag_t; -/** - * @} - */ - -/** @defgroup RTC_Public_Macro RTC Public Macros - * @{ - */ -#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55)) -#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0)) -#define RTC_BY_PASS_ENABLE() \ -do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ - RTC_LOCK(); \ -} while (0) -#define RTC_BY_PASS_DISABLE() \ -do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ - RTC_LOCK(); \ -} while (0) -#define RTC_SUMMER_TIME_ENABLE() \ -do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ - RTC_LOCK(); \ -} while (0) -#define RTC_SUMMER_TIME_DISABLE() \ -do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ - RTC_LOCK(); \ -} while (0) -#define RTC_WINTER_TIME_ENABLE() \ -do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ - RTC_LOCK(); \ -} while (0) -#define RTC_WINTER_TIME_DISABLE() \ -do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ - RTC_LOCK(); \ -} while (0) -/** - * @} - */ - -/** @defgroup CAN_Private_Macros CAN Private Macros - * @{ - */ -#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AA)) -#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0)) -#define ALARM_MASK_ALL 0x40808080 -#define RTC_TIMEOUT_VALUE 100 - -#define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15)) -#define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \ - ((x) == RTC_HOUR_FORMAT_12)) -#define IS_RTC_OUTPUT_SEL(x) (((x) == RTC_OUTPUT_DISABLE) || \ - ((x) == RTC_OUTPUT_ALARM_A) || \ - ((x) == RTC_OUTPUT_ALARM_B) || \ - ((x) == RTC_OUTPUT_WAKEUP)) -#define IS_RTC_OUTPUT_POLARITY(x) (((x) == RTC_OUTPUT_POLARITY_HIGH) || \ - ((x) == RTC_OUTPUT_POLARITY_LOW)) -#define IS_RTC_SOURCE_SEL(x) (((x) == RTC_SOURCE_LOSC) || \ - ((x) == RTC_SOURCE_LRC) || \ - ((x) == RTC_SOURCE_HRC_DIV_1M ) || \ - ((x) == RTC_SOURCE_HOSC_DIV_1M)) -#define IS_RTC_ALARM(x) (((x) == RTC_ALARM_A) || \ - ((x) == RTC_ALARM_B)) -#define IS_RTC_ALARM_SEL(x) (((x) == RTC_SELECT_DAY) || \ - ((x) == RTC_SELECT_WEEK)) -#define IS_RTC_ALARM_MASK(x) (((x) == RTC_ALARM_MASK_NONE) || \ - ((x) == RTC_ALARM_MASK_WEEK_DAY) || \ - ((x) == RTC_ALARM_MASK_HOUR) || \ - ((x) == RTC_ALARM_MASK_MINUTE) || \ - ((x) == RTC_ALARM_MASK_SECOND) || \ - ((x) == RTC_ALARM_MASK_ALL)) -#define IS_RTC_ALARM_SS_MASK(x) (((x) == RTC_ALARM_SS_MASK_NONE) || \ - ((x) == RTC_ALARM_SS_MASK_14_1) || \ - ((x) == RTC_ALARM_SS_MASK_14_2) || \ - ((x) == RTC_ALARM_SS_MASK_14_3) || \ - ((x) == RTC_ALARM_SS_MASK_14_4) || \ - ((x) == RTC_ALARM_SS_MASK_14_5) || \ - ((x) == RTC_ALARM_SS_MASK_14_6) || \ - ((x) == RTC_ALARM_SS_MASK_14_7) || \ - ((x) == RTC_ALARM_SS_MASK_14_8) || \ - ((x) == RTC_ALARM_SS_MASK_14_9) || \ - ((x) == RTC_ALARM_SS_MASK_14_10) || \ - ((x) == RTC_ALARM_SS_MASK_14_11) || \ - ((x) == RTC_ALARM_SS_MASK_14_12) || \ - ((x) == RTC_ALARM_SS_MASK_14_13) || \ - ((x) == RTC_ALARM_SS_MASK_14) || \ - ((x) == RTC_ALARM_SS_MASK_ALL)) -#define IS_RTC_TS_SIGNAL(x) (((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \ - ((x) == RTC_TS_SIGNAL_SEL_TAMPER1)) -#define IS_RTC_TS_STYLE(x) (((x) == RTC_TS_RISING_EDGE) || \ - ((x) == RTC_TS_FALLING_EDGE)) -#define IS_RTC_FORMAT(x) (((x) == RTC_FORMAT_DEC) || \ - ((x) == RTC_FORMAT_BCD)) -#define IS_RTC_TAMPER(x) (((x) == RTC_TAMPER_0) || \ - ((x) == RTC_TAMPER_1)) -#define IS_RTC_TAMPER_TRIGGER(x) (((x) == RTC_TAMPER_TRIGGER_LOW) || \ - ((x) == RTC_TAMPER_TRIGGER_HIGH)) -#define IS_RTC_TAMPER_SAMPLING_FREQ(x) (((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_256)) -#define IS_RTC_TAMPER_DURATION(x) (((x) == RTC_TAMPER_DURATION_1) || \ - ((x) == RTC_TAMPER_DURATION_2) || \ - ((x) == RTC_TAMPER_DURATION_4) || \ - ((x) == RTC_TAMPER_DURATION_8)) -#define IS_RTC_WAKEUP_CLOCK(x) (((x) == RTC_WAKEUP_CLOCK_DIV_16) || \ - ((x) == RTC_WAKEUP_CLOCK_DIV_8) || \ - ((x) == RTC_WAKEUP_CLOCK_DIV_4) || \ - ((x) == RTC_WAKEUP_CLOCK_DIV_2) || \ - ((x) == RTC_WAKEUP_CLOCK_1HZ) || \ - ((x) == RTC_WAKEUP_CLOCK_1HZ_PULS)) -#define IS_RTC_CLOCK_OUTPUT(x) (((x) == RTC_CLOCK_OUTPUT_32768) || \ - ((x) == RTC_CLOCK_OUTPUT_1024) || \ - ((x) == RTC_CLOCK_OUTPUT_32) || \ - ((x) == RTC_CLOCK_OUTPUT_1) || \ - ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \ - ((x) == RTC_CLOCK_OUTPUT_EXA_1)) -#define IS_RTC_CALI_FREQ(x) (((x) == RTC_CALI_FREQ_10_SEC) || \ - ((x) == RTC_CALI_FREQ_20_SEC) || \ - ((x) == RTC_CALI_FREQ_1_MIN) || \ - ((x) == RTC_CALI_FREQ_2_MIN) || \ - ((x) == RTC_CALI_FREQ_5_MIN) || \ - ((x) == RTC_CALI_FREQ_10_MIN) || \ - ((x) == RTC_CALI_FREQ_20_MIN) || \ - ((x) == RTC_CALI_FREQ_1_SEC)) -#define IS_RTC_CALI_TC(x) (((x) == RTC_CALI_TC_NONE) || \ - ((x) == RTC_CALI_TC_AUTO_BY_HW) || \ - ((x) == RTC_CALI_TC_AUTO_BY_SF) || \ - ((x) == RTC_CALI_TC_AUTO_BY_HW_SF)) -#define IS_RTC_CALC_FREQ(x) (((x) == RTC_CALI_CALC_FREQ_10_SEC) || \ - ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \ - ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_5_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_1_HOUR)) -#define IS_RTC_CALI_CALC(x) (((x) == RTC_CALI_CALC_4) || \ - ((x) == RTC_CALI_CALC_2)) -#define IS_RTC_IT(x) (((x) == RTC_IT_SEC) || \ - ((x) == RTC_IT_MIN) || \ - ((x) == RTC_IT_HR) || \ - ((x) == RTC_IT_DAY) || \ - ((x) == RTC_IT_MON) || \ - ((x) == RTC_IT_YR) || \ - ((x) == RTC_IT_ALMA) || \ - ((x) == RTC_IT_ALMB) || \ - ((x) == RTC_IT_TS) || \ - ((x) == RTC_IT_TSOV) || \ - ((x) == RTC_IT_TP0) || \ - ((x) == RTC_IT_TP1) || \ - ((x) == RTC_IT_RSC) || \ - ((x) == RTC_IT_SFC) || \ - ((x) == RTC_IT_WU) || \ - ((x) == RTC_IT_TCC) || \ - ((x) == RTC_IT_TCE)) -#define IS_RTC_IF(x) (((x) == RTC_IF_SEC) || \ - ((x) == RTC_IF_MIN) || \ - ((x) == RTC_IF_HR) || \ - ((x) == RTC_IF_DAY) || \ - ((x) == RTC_IF_MON) || \ - ((x) == RTC_IF_YR) || \ - ((x) == RTC_IF_ALMA) || \ - ((x) == RTC_IF_ALMB) || \ - ((x) == RTC_IF_TS) || \ - ((x) == RTC_IF_TSOV) || \ - ((x) == RTC_IF_TP0) || \ - ((x) == RTC_IF_TP1) || \ - ((x) == RTC_IF_RSC) || \ - ((x) == RTC_IF_SFC) || \ - ((x) == RTC_IF_WU) || \ - ((x) == RTC_IF_TCC) || \ - ((x) == RTC_IF_TCE)) -#define IS_RTC_SECOND(x) ((x) < 60) -#define IS_RTC_MINUTE(x) ((x) < 60) -#define IS_RTC_HOUR(x) ((x) < 24) -#define IS_RTC_DAY(x) (((x) > 0) && ((x) < 32)) -#define IS_RTC_MONTH(x) (((x) > 0) && ((x) < 13)) -#define IS_RTC_YEAR(x) ((x) < 100) -/** - * @} - */ - -/** @addtogroup RTC_Public_Functions - * @{ - */ - -/** @addtogroup RTC_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -void rtc_reset(void); -void rtc_init(rtc_init_t *init); -void rtc_source_selcet(rtc_source_sel_t sel); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group2 - * @{ - */ -/* Time and date operation functions */ -ald_status_t rtc_set_time(rtc_time_t *time, rtc_format_t format); -ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format); -void rtc_get_time(rtc_time_t *time, rtc_format_t format); -void rtc_get_date(rtc_date_t *date, rtc_format_t format); -int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group3 - * @{ - */ -/* Alarm functions */ -void rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format); -void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group4 - * @{ - */ -/* Time stamp functions */ -void rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style); -void rtc_cancel_time_stamp(void); -void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group5 - * @{ - */ -/* Tamper functions */ -void rtc_set_tamper(rtc_tamper_t *tamper); -void rtc_cancel_tamper(rtc_tamper_idx_t idx); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group6 - * @{ - */ -/* Wakeup functions */ -void rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value); -void rtc_cancel_wakeup(void); -uint16_t rtc_get_wakeup_timer_value(void); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group7 - * @{ - */ -/* Clock output functions */ -ald_status_t rtc_set_clock_output(rtc_clock_output_t clock); -void rtc_cancel_clock_output(void); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group8 - * @{ - */ -/* Control functions */ -void rtc_interrupt_config(rtc_it_t it, type_func_t state); -void rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state); -ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss); -void rtc_set_cali(rtc_cali_t *config); -void rtc_cancel_cali(void); -ald_status_t rtc_get_cali_status(void); -void rtc_write_temp(uint16_t temp); -it_status_t rtc_get_it_status(rtc_it_t it); -flag_status_t rtc_get_flag_status(rtc_flag_t flag); -void rtc_clear_flag_status(rtc_flag_t flag); -/** - * @} - */ -/** - * @} - */ -/** - * @} - */ -/** - * @} - */ -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h deleted file mode 100644 index 1d5564bd765842869e83e06f420f0da4b38deef1..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h +++ /dev/null @@ -1,279 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_usart.h - * @brief Header file of SMARTCARD driver module. - * - * @version V1.0 - * @date 25 Apr 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_SMARTCARD_H__ -#define __ALD_SMARTCARD_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" -#include "ald_usart.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup SMARTCARD - * @{ - */ - -/** @defgroup SMARTCARD_Public_Constants SMARTCARD Public constants - * @{ - */ - -/** - * @brief SMARTCARD error codes - */ -typedef enum -{ - SMARTCARD_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - SMARTCARD_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - SMARTCARD_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - SMARTCARD_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - SMARTCARD_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - SMARTCARD_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ -} smartcard_error_t; - -/** - * @brief SMARTCARD Prescaler - */ -typedef enum -{ - SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1), /**< SYSCLK divided by 2 */ - SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2), /**< SYSCLK divided by 4 */ - SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3), /**< SYSCLK divided by 6 */ - SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4), /**< SYSCLK divided by 8 */ - SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5), /**< SYSCLK divided by 10 */ - SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6), /**< SYSCLK divided by 12 */ - SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7), /**< SYSCLK divided by 14 */ - SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8), /**< SYSCLK divided by 16 */ - SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9), /**< SYSCLK divided by 18 */ - SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA), /**< SYSCLK divided by 20 */ - SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB), /**< SYSCLK divided by 22 */ - SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC), /**< SYSCLK divided by 24 */ - SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD), /**< SYSCLK divided by 26 */ - SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE), /**< SYSCLK divided by 28 */ - SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF), /**< SYSCLK divided by 30 */ - SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10), /**< SYSCLK divided by 32 */ - SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11), /**< SYSCLK divided by 34 */ - SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12), /**< SYSCLK divided by 36 */ - SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13), /**< SYSCLK divided by 38 */ - SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14), /**< SYSCLK divided by 40 */ - SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15), /**< SYSCLK divided by 42 */ - SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16), /**< SYSCLK divided by 44 */ - SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17), /**< SYSCLK divided by 46 */ - SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18), /**< SYSCLK divided by 48 */ - SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19), /**< SYSCLK divided by 50 */ - SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A), /**< SYSCLK divided by 52 */ - SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B), /**< SYSCLK divided by 54 */ - SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C), /**< SYSCLK divided by 56 */ - SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D), /**< SYSCLK divided by 58 */ - SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E), /**< SYSCLK divided by 60 */ - SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F), /**< SYSCLK divided by 62 */ -} smartcard_prescaler_t; - -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Types SMARTCARD Public Types - * @{ - */ - -/** - * @brief SMARTCARD Init Structure definition - */ -typedef struct -{ - uint32_t baud; /**< This member configures the SmartCard communication baud rate. */ - usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ - usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ - usart_parity_t parity; /**< Specifies the parity mode. - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits).*/ - usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */ - usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ - usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/ - usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref usart_last_bit_t */ - smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock - to provide the smartcard clock. The value given in the register (5 significant bits) - is multiplied by 2 to give the division factor of the source clock frequency. */ - uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ - type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */ -} smartcard_init_t; - -/** - * @brief ALD state structures definition - */ -typedef enum -{ - SMARTCARD_STATE_RESET = 0x00, /**< Peripheral is not yet Initialized */ - SMARTCARD_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - SMARTCARD_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - SMARTCARD_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - SMARTCARD_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - SMARTCARD_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission and Reception process is ongoing */ - SMARTCARD_STATE_TIMEOUT = 0x03, /**< Timeout state */ - SMARTCARD_STATE_ERROR = 0x04 /**< Error */ -} smartcard_state_t; - - -/** - * @brief SMARTCARD handle structure definition - */ -typedef struct smartcard_handle_s -{ - USART_TypeDef *perh; /**< USART registers base address */ - smartcard_init_t init; /**< SmartCard communication parameters */ - uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */ - uint16_t tx_size; /**< SmartCard Tx Transfer size */ - uint16_t tx_count; /**< SmartCard Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */ - uint16_t rx_size; /**< SmartCard Rx Transfer size */ - uint16_t rx_count; /**< SmartCard Rx Transfer Counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - smartcard_state_t state; /**< SmartCard communication state */ - uint32_t err_code; /**< SmartCard Error code */ - - void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */ -} smartcard_handle_t; - -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Macros SMARTCARD Public Macros - * @{ - */ - -/** @defgroup SMARTCARD_Public_Macros_1 SMARTCARD handle reset - * @{ - */ -#define SMARTCARD_RESET_HANDLE_STATE(handle) ((handle)->state = SMARTCARD_STATE_RESET) -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Macros_2 SMARTCARD flush data - * @{ - */ -#define SMARTCARD_FLUSH_DRREGISTER(handle) ((handle)->perh->DATA) -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Macros_3 SMARTCARD enable - * @{ - */ -#define SMARTCARD_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Macros_4 SMARTCARD disable - * @{ - */ -#define SMARTCARD_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros - * @{ - */ - -#define IS_SMARTCARD_PRESCALER(x) (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \ - ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62)) -/** - * @} - */ - -/** @addtogroup SMARTCARD_Public_Functions - * @{ - */ - -/** @addtogroup SMARTCARD_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -ald_status_t smartcard_init(smartcard_handle_t *hperh); -ald_status_t smartcard_reset(smartcard_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup SMARTCARD_Public_Functions_Group2 - * @{ - */ -/* IO operation functions */ -ald_status_t smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -#endif -void smartcard_irq_handle(smartcard_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup SMARTCARD_Public_Functions_Group3 - * @{ - */ -/* Peripheral State and Errors functions functions */ -smartcard_state_t smartcard_get_state(smartcard_handle_t *hperh); -uint32_t smartcard_get_error(smartcard_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_SMARTCARD_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h deleted file mode 100644 index 467e92b07fc8b94673ca111179b7ebb7757772e3..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h +++ /dev/null @@ -1,377 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_spi.c - * @brief Header file of SPI module driver. - * - * @version V1.0 - * @date 13 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_SPI_H__ -#define __ALD_SPI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Public_Types SPI Public Types - * @{ - */ - -/** - * @brief clock phase - */ -typedef enum -{ - SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */ - SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */ -} spi_cpha_t; - -/** - * @brief clock polarity - */ -typedef enum -{ - SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */ - SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */ -} spi_cpol_t; - -/** - * @brief master selection - */ -typedef enum -{ - SPI_MODE_SLAVER = 0, /**< Slave mode */ - SPI_MODE_MASTER = 1, /**< Master mode */ -} spi_mode_t; - -/** - * @brief baud rate control - */ -typedef enum -{ - SPI_BAUD_2 = 0, /**< fpclk/2 */ - SPI_BAUD_4 = 1, /**< fpclk/4 */ - SPI_BAUD_8 = 2, /**< fpclk/8 */ - SPI_BAUD_16 = 3, /**< fpclk/16 */ - SPI_BAUD_32 = 4, /**< fpclk/32 */ - SPI_BAUD_64 = 5, /**< fpclk/64 */ - SPI_BAUD_128 = 6, /**< fpclk/128 */ - SPI_BAUD_256 = 7, /**< fpclk/256 */ -} spi_baud_t; - -/** - * @brief frame format - */ -typedef enum -{ - SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */ - SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */ -} spi_firstbit_t; - -/** - * @brief data frame format - */ -typedef enum -{ - SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */ - SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */ -} spi_datasize_t; - -/** - * @brief interrupt control - */ -typedef enum -{ - SPI_IT_ERR = (1U << 5), /**< error interrupt */ - SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */ - SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */ -} spi_it_t; - -/** - * @brief interrupt flag - */ -typedef enum -{ - SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */ - SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */ - SPI_IF_CRCERR = (1U << 4), /**< crc error flag */ - SPI_IF_MODF = (1U << 5), /**< mode fault */ - SPI_IF_OVE = (1U << 6), /**< overrun flag */ - SPI_IF_BUSY = (1U << 7), /**< busy flag */ -} spi_flag_t; - -/** - * @brief SPI error status - */ -typedef enum -{ - SPI_ERROR_NONE = 0, /**< none */ - SPI_ERROR_MODF = 1, /**< mode fault */ - SPI_ERROR_CRC = 2, /**< crc error */ - SPI_ERROR_OVE = 4, /**< overrun error */ - SPI_ERROR_DMA = 8, /**< dma error */ - SPI_ERROR_FLAG = 0x10, /**< interrupt flag error */ -} spi_error_t; - - - -/** - * @brief SPI state structures definition - */ -typedef enum -{ - SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */ - SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */ - SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */ - SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */ - SPI_STATE_ERROR = 0x04, /**< Error */ -} spi_state_t; - - -/** - * @brief SPI direction definition - */ -typedef enum -{ - SPI_DIRECTION_2LINES = 0, /**< 2 lines */ - SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */ - SPI_DIRECTION_1LINE = 2, /**< 1 line */ - SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */ -} spi_direction_t; - -/** - * @brief SPI dma request definition - */ -typedef enum -{ - SPI_DMA_REQ_TX = 0, /**< TX dma request */ - SPI_DMA_REQ_RX = 1, /**< RX dma request */ -} spi_dma_req_t; - -/** - * @brief SPI TXE/RXNE status definition - */ -typedef enum -{ - SPI_SR_TXBE = 0, /**< SR.TXE set */ - SPI_SR_RXBNE = 1, /**< SR.RXNE set */ - SPI_SR_TXBE_RXBNE = 2, /**< SR.TXE and SR.RXNE set */ -} spi_sr_status_t; - -/** - * @brief SPI init structure definition - */ -typedef struct -{ - spi_mode_t mode; /**< SPI mode */ - spi_direction_t dir; /**< SPI direction */ - spi_datasize_t data_size; /**< SPI data size */ - spi_baud_t baud; /**< SPI baudrate prescaler */ - spi_cpha_t phase; /**< SPI clock phase */ - spi_cpol_t polarity; /**< SPI clock polarity */ - spi_firstbit_t first_bit; /**< SPI first bit */ - type_func_t ss_en; /**< SPI ssm enable or disable */ - type_func_t crc_calc; /**< SPI crc calculation */ - uint16_t crc_poly; /**< SPI crc polynomial */ -} spi_init_t; - -/** - * @brief SPI handle structure definition - */ -typedef struct spi_handle_s -{ - SPI_TypeDef *perh; /**< SPI registers base address */ - spi_init_t init; /**< SPI communication parameters */ - uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ - uint16_t tx_size; /**< SPI Tx transfer size */ - uint16_t tx_count; /**< SPI Tx transfer counter */ - uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ - uint16_t rx_size; /**< SPI Rx Transfer size */ - uint16_t rx_count; /**< SPI Rx Transfer Counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - spi_state_t state; /**< SPI communication state */ - uint32_t err_code; /**< SPI error code */ - - void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ - void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ - void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ -} spi_handle_t; -/** - * @} - */ - -/** @defgroup SPI_Public_Macros SPI Public Macros - * @{ - */ -#define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET) -#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) -#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) -#define SPI_CRC_RESET(x) \ -do { \ - CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ - SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ -} while (0) -#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) -#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) -#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) -#define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) -#define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) -#define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) -#define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) -#define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) -#define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) -#define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) -/** - * @} - */ - -/** @defgroup SPI_Private_Macros SPI Private Macros - * @{ - */ -#define IS_SPI(x) (((x) == SPI0) || \ - ((x) == SPI1) || \ - ((x) == SPI2)) -#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \ - ((x) == SPI_CPHA_SECOND)) -#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \ - ((x) == SPI_CPOL_HIGH)) -#define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \ - ((x) == SPI_MODE_MASTER)) -#define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \ - ((x) == SPI_BAUD_4) || \ - ((x) == SPI_BAUD_8) || \ - ((x) == SPI_BAUD_16) || \ - ((x) == SPI_BAUD_32) || \ - ((x) == SPI_BAUD_64) || \ - ((x) == SPI_BAUD_128) || \ - ((x) == SPI_BAUD_256)) -#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \ - ((x) == SPI_DATA_SIZE_16)) -#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \ - ((x) == SPI_BID_TX)) -#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \ - ((x) == SPI_BIDMODE_SOLE)) -#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \ - ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((x) == SPI_DIRECTION_1LINE) || \ - ((x) == SPI_DIRECTION_1LINE_RX)) -#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \ - ((x) == SPI_DMA_REQ_RX)) -#define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \ - ((x) == SPI_SR_RXBNE) || \ - ((x) == SPI_SR_TXBE_RXBNE)) -#define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \ - ((x) == SPI_IT_RXBNE) || \ - ((x) == SPI_IT_TXBE)) -#define IS_SPI_IF(x) (((x) == SPI_IF_RXBNE) || \ - ((x) == SPI_IF_TXBE) || \ - ((x) == SPI_IF_CRCERR) || \ - ((x) == SPI_IF_MODF) || \ - ((x) == SPI_IF_OVE) || \ - ((x) == SPI_IF_BUSY)) -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions - * @{ - */ - -/** @addtogroup SPI_Public_Functions_Group1 - * @{ - */ - -ald_status_t spi_init(spi_handle_t *hperh); -void spi_reset(spi_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions_Group2 - * @{ - */ -int32_t spi_send_byte_fast(spi_handle_t *hperh, uint8_t data); -uint8_t spi_recv_byte_fast(spi_handle_t *hperh); -ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); -ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); -ald_status_t spi_dma_pause(spi_handle_t *hperh); -ald_status_t spi_dma_resume(spi_handle_t *hperh); -ald_status_t spi_dma_stop(spi_handle_t *hperh); -#endif -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions_Group3 - * @{ - */ -void spi_irq_handle(spi_handle_t *hperh); -void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state); -void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed); -void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state); -it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it); -flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag); -void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag); -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions_Group4 - * @{ - */ -spi_state_t spi_get_state(spi_handle_t *hperh); -uint32_t spi_get_error(spi_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_temp.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_temp.h deleted file mode 100644 index b9d5c15d15141e54860ea79a606d82e06eca64fb..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_temp.h +++ /dev/null @@ -1,203 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_temp.h - * @brief Header file of TEMP module driver. - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_TEMP_H__ -#define __ALD_TEMP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup TEMP - * @{ - */ - -/** @defgroup TEMP_Public_Macros TEMP Public Macros - * @{ - */ -#define TEMP_LOCK() (WRITE_REG(TEMP->WPR, 0x0)) -#define TEMP_UNLOCK() (WRITE_REG(TEMP->WPR, 0xA55A9669)) -#define TEMP_ENABLE() \ -do { \ - TEMP_UNLOCK(); \ - SET_BIT(TEMP->CR, TEMP_CR_EN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_DISABLE() \ -do { \ - TEMP_UNLOCK(); \ - CLEAR_BIT(TEMP->CR, TEMP_CR_EN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_REQ_ENABLE() \ -do { \ - TEMP_UNLOCK(); \ - SET_BIT(TEMP->CR, TEMP_CR_REQEN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_REQ_DISABLE() \ -do { \ - TEMP_UNLOCK(); \ - CLEAR_BIT(TEMP->CR, TEMP_CR_REQEN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_CTN_ENABLE() \ -do { \ - TEMP_UNLOCK(); \ - SET_BIT(TEMP->CR, TEMP_CR_CTN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_CTN_DISABLE() \ -do { \ - TEMP_UNLOCK(); \ - CLEAR_BIT(TEMP->CR, TEMP_CR_CTN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_RESET() \ -do { \ - TEMP_UNLOCK(); \ - SET_BIT(TEMP->CR, TEMP_CR_RST_MSK); \ - TEMP_LOCK(); \ -} while (0) -/** - * @} - */ - -/** @defgroup TEMP_Public_Types TEMP Public Types - * @{ - */ -/** - * @brief Temperature update time - */ -typedef enum -{ - TEMP_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */ - TEMP_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */ - TEMP_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */ - TEMP_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */ - TEMP_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */ -} temp_update_cycle_t; - -/** - * @brief Temperature output mode - */ -typedef enum -{ - TEMP_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */ - TEMP_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */ - TEMP_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */ - TEMP_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */ - TEMP_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */ -} temp_output_mode_t; - -/** - * @brief Source select - */ -typedef enum -{ - TEMP_SOURCE_LOSC = 0x0, /**< LOSC */ - TEMP_SOURCE_LRC = 0x1, /**< LRC */ - TEMP_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ - TEMP_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ -} temp_source_sel_t; - - -/** - * @brief TEMP init structure definition - */ -typedef struct -{ - temp_update_cycle_t cycle; /**< Temperature update time */ - temp_output_mode_t mode; /**< Temperature output mode */ - uint8_t ctn; /**< Continue mode */ - uint8_t psc; /**< Perscaler */ -} temp_init_t; - -/** - * @brief Define callback function type - */ -typedef void (*temp_cbk)(uint16_t value, ald_status_t status); -/** - * @} - */ - -/** - * @defgroup TEMP_Private_Macros TEMP Private Macros - * @{ - */ -#define IS_TEMP_UPDATE_CYCLE(x) (((x) == TEMP_UPDATE_CYCLE_3) || \ - ((x) == TEMP_UPDATE_CYCLE_4) || \ - ((x) == TEMP_UPDATE_CYCLE_5) || \ - ((x) == TEMP_UPDATE_CYCLE_6) || \ - ((x) == TEMP_UPDATE_CYCLE_7)) -#define IS_TEMP_OUTPUT_MODE(x) (((x) == TEMP_OUTPUT_MODE_200) || \ - ((x) == TEMP_OUTPUT_MODE_400) || \ - ((x) == TEMP_OUTPUT_MODE_800) || \ - ((x) == TEMP_OUTPUT_MODE_1600) || \ - ((x) == TEMP_OUTPUT_MODE_3200)) -#define IS_TEMP_SOURCE_SEL(x) (((x) == TEMP_SOURCE_LOSC) || \ - ((x) == TEMP_SOURCE_LRC) || \ - ((x) == TEMP_SOURCE_HRC_DIV_1M ) || \ - ((x) == TEMP_SOURCE_HOSC_DIV_1M)) -/** - * @} - */ - -/** @addtogroup TEMP_Public_Functions - * @{ - */ -/** @addtogroup TEMP_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -extern void temp_init(temp_init_t *init); -extern void temp_source_selcet(temp_source_sel_t sel); -/** - * @} - */ -/** @addtogroup TEMP_Public_Functions_Group2 - * @{ - */ -/* Control functions */ -extern ald_status_t temp_get_value(uint16_t *temp); -extern void temp_get_value_by_it(temp_cbk cbk); -void temp_irq_handle(void); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_TEMP_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h deleted file mode 100644 index 6eaf44da44a485e87c788d546aff00cc54f77efe..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h +++ /dev/null @@ -1,1130 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_timer.h - * @brief TIMER module driver. - * This is the common part of the TIMER initialization - * - * @version V1.0 - * @date 06 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_TIMER_H__ -#define __ALD_TIMER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup TIMER - * @{ - */ - -/** @defgroup TIMER_Public_Types TIMER Public Types - * @{ - */ - -/** - * @brief TIMER counter mode - */ -typedef enum -{ - TIMER_CNT_MODE_UP = 0, /**< Counter mode up */ - TIMER_CNT_MODE_DOWN = 1, /**< Counter mode down */ - TIMER_CNT_MODE_CENTER1 = 2, /**< Counter mode center1 */ - TIMER_CNT_MODE_CENTER2 = 3, /**< Counter mode center2 */ - TIMER_CNT_MODE_CENTER3 = 4, /**< Counter mode center3 */ -} timer_cnt_mode_t; - -/** - * @brief TIMER clock division - */ -typedef enum -{ - TIMER_CLOCK_DIV1 = 0, /**< No prescaler is used */ - TIMER_CLOCK_DIV2 = 1, /** Clock is divided by 2 */ - TIMER_CLOCK_DIV4 = 2, /** Clock is divided by 4 */ -} timer_clock_division_t; - -/** - * @brief TIMER output compare and PWM modes - */ -typedef enum -{ - TIMER_OC_MODE_TIMERING = 0, /**< Output compare mode is timering */ - TIMER_OC_MODE_ACTIVE = 1, /**< Output compare mode is active */ - TIMER_OC_MODE_INACTIVE = 2, /**< Output compare mode is inactive */ - TIMER_OC_MODE_TOGGLE = 3, /**< Output compare mode is toggle */ - TIMER_OC_MODE_FORCE_INACTIVE = 4, /**< Output compare mode is force inactive */ - TIMER_OC_MODE_FORCE_ACTIVE = 5, /**< Output compare mode is force active */ - TIMER_OC_MODE_PWM1 = 6, /**< Output compare mode is pwm1 */ - TIMER_OC_MODE_PWM2 = 7, /**< Output compare mode is pwm2 */ -} timer_oc_mode_t; - -/** - * @brief TIMER output compare polarity - */ -typedef enum -{ - TIMER_OC_POLARITY_HIGH = 0, /**< Output compare polarity is high */ - TIMER_OC_POLARITY_LOW = 1, /**< Output compare polarity is low */ -} timer_oc_polarity_t; - -/** - * @brief TIMER complementary output compare polarity - */ -typedef enum -{ - TIMER_OCN_POLARITY_HIGH = 0, /**< Complementary output compare polarity is high */ - TIMER_OCN_POLARITY_LOW = 1, /**< Complementary output compare polarity is low */ -} timer_ocn_polarity_t; - -/** - * @brief TIMER output compare idle state - */ -typedef enum -{ - TIMER_OC_IDLE_RESET = 0, /**< Output compare idle state is reset */ - TIMER_OC_IDLE_SET = 1, /**< Output compare idle state is set */ -} timer_oc_idle_t; - -/** - * @brief TIMER complementary output compare idle state - */ -typedef enum -{ - TIMER_OCN_IDLE_RESET = 0, /**< Complementary output compare idle state is reset */ - TIMER_OCN_IDLE_SET = 1, /**< Complementary output compare idle state is set */ -} timer_ocn_idle_t; - -/** - * @brief TIMER channel - */ -typedef enum -{ - TIMER_CHANNEL_1 = 0, /**< Channel 1 */ - TIMER_CHANNEL_2 = 1, /**< Channel 2 */ - TIMER_CHANNEL_3 = 2, /**< Channel 3 */ - TIMER_CHANNEL_4 = 4, /**< Channel 4 */ - TIMER_CHANNEL_ALL = 0xF, /**< All channel */ -} timer_channel_t; - -/** - * @brief TIMER one pulse mode - */ -typedef enum -{ - TIMER_OP_MODE_REPEAT = 0, /**< Repetitive */ - TIMER_OP_MODE_SINGLE = 1, /**< single */ -} timer_op_mode_t; - -/** - * @brief TIMER one pulse output channel - */ -typedef enum -{ - TIMER_OP_OUTPUT_CHANNEL_1 = 0, /**< One pulse output channal 1 */ - TIMER_OP_OUTPUT_CHANNEL_2 = 1, /**< One pulse output channal 2 */ -} timer_op_output_channel_t; - -/** - * @brief TIMER time base configuration structure definition - */ -typedef struct -{ - uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ - timer_cnt_mode_t mode; /**< Specifies the counter mode. */ - uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ - timer_clock_division_t clk_div; /**< Specifies the clock division.*/ - uint32_t re_cnt; /**< Specifies the repetition counter value. */ -} timer_base_init_t; - -/** - * @brief TIMER output compare configuration structure definition - */ -typedef struct -{ - timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ - uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ - timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ - timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ - type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ - timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ - timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ -} timer_oc_init_t; - -/** - * @brief State structures definition - */ -typedef enum -{ - TIMER_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */ - TIMER_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - TIMER_STATE_BUSY = 0x02, /**< An internal process is ongoing */ - TIMER_STATE_TIMEREOUT = 0x03, /**< Timeout state */ - TIMER_STATE_ERROR = 0x04, /**< Reception process is ongoing */ -} timer_state_t; - -/** - * @brief Active channel structures definition - */ -typedef enum -{ - TIMER_ACTIVE_CHANNEL_1 = 0x01, /**< The active channel is 1 */ - TIMER_ACTIVE_CHANNEL_2 = 0x02, /**< The active channel is 2 */ - TIMER_ACTIVE_CHANNEL_3 = 0x04, /**< The active channel is 3 */ - TIMER_ACTIVE_CHANNEL_4 = 0x08, /**< The active channel is 4 */ - TIMER_ACTIVE_CHANNEL_CLEARED = 0x00, /**< All active channels cleared */ -} timer_active_channel_t; - -/** - * @brief TIMER time base handle structure definition - */ -typedef struct timer_handle_s -{ - TIMER_TypeDef *perh; /**< Register base address */ - timer_base_init_t init; /**< TIMER Time Base required parameters */ - timer_active_channel_t ch; /**< Active channel */ - lock_state_t lock; /**< Locking object */ - timer_state_t state; /**< TIMER operation state */ - - void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ - void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ - void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ - void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ - void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ - void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ - void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ - void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ -} timer_handle_t; - - -/** - * @brief TIMER encoder mode - */ -typedef enum -{ - TIMER_ENC_MODE_TI1 = 1, /**< encoder mode 1 */ - TIMER_ENC_MODE_TI2 = 2, /**< encoder mode 2 */ - TIMER_ENC_MODE_TI12 = 3, /**< encoder mode 3 */ -} timer_encoder_mode_t; - -/** - * @brief TIMER input capture polarity - */ -typedef enum -{ - TIMER_IC_POLARITY_RISE = 0, /**< Input capture polarity rising */ - TIMER_IC_POLARITY_FALL = 1, /**< Input capture polarity falling */ - TIMER_IC_POLARITY_BOTH = 3, /**< Input capture polarity rising and falling */ -} timer_ic_polarity_t; - -/** - *@brief TIMER input capture selection - */ -typedef enum -{ - TIMER_IC_SEL_DIRECT = 1, /**< IC1 -- TI1 */ - TIMER_IC_SEL_INDIRECT = 2, /**< IC1 -- TI2 */ - TIMER_IC_SEL_TRC = 3, /**< IC1 -- TRC */ -} timer_ic_select_t; - -/** - * @brief TIMER input capture prescaler - */ -typedef enum -{ - TIMER_IC_PSC_DIV1 = 0, /**< Capture performed once every 1 events */ - TIMER_IC_PSC_DIV2 = 1, /**< Capture performed once every 2 events */ - TIMER_IC_PSC_DIV4 = 2, /**< Capture performed once every 4 events */ - TIMER_IC_PSC_DIV8 = 3, /**< Capture performed once every 4 events */ -} timer_ic_prescaler_t; - -/** - * @brief TIMER encoder configuration structure definition - */ -typedef struct -{ - timer_encoder_mode_t mode; /**< Specifies the encoder mode */ - timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t ic1_sel; /**< Specifies the input */ - timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ - uint32_t ic1_filter; /**< Specifies the input capture filter */ - timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t ic2_sel; /**< Specifies the input */ - timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ - uint32_t ic2_filter; /**< Specifies the input capture filter */ -} timer_encoder_init_t; - -/** - * @brief TIMER input capture configuration structure definition - */ -typedef struct -{ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t sel; /**< Specifies the input */ - timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ - uint32_t filter; /**< Specifies the input capture filter */ -} timer_ic_init_t; - -/** - * @brief TIMER one pulse mode configuration structure definition - */ -typedef struct -{ - timer_oc_mode_t mode; /**< Specifies the TIMER mode */ - uint16_t pulse; /**< Specifies the pulse value */ - timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ - timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ - timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ - timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t sel; /**< Specifies the input */ - uint32_t filter; /**< Specifies the input capture filter */ -} timer_one_pulse_init_t; - -/** @brief TIMER clear input source - */ -typedef enum -{ - TIMER_INPUT_NONE = 0, /**< Clear input none */ - TIMER_INPUT_ETR = 1, /**< Clear input etr */ -} timer_clear_input_source_t; - -/** @brief TIMER clear input polarity - */ -typedef enum -{ - TIMER_POLARITY_NO_INV = 0, /**< Polarity for ETRx pin */ - TIMER_POLARITY_INV = 1, /**< Polarity for ETRx pin */ -} timer_clear_input_polarity_t; - -/** @brief TIMER clear input polarity - */ -typedef enum -{ - TIMER_ETR_PSC_DIV1 = 0, /**< No prescaler is used */ - TIMER_ETR_PSC_DIV2 = 1, /**< ETR input source is divided by 2 */ - TIMER_ETR_PSC_DIV4 = 2, /**< ETR input source is divided by 4 */ - TIMER_ETR_PSC_DIV8 = 3, /**< ETR input source is divided by 8 */ -} timer_etr_psc_t; - -/** - * @brief TIMER clear input configuration handle structure definition - */ -typedef struct -{ - type_func_t state; /**< TIMER clear Input state */ - timer_clear_input_source_t source; /**< TIMER clear Input sources */ - timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ - timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ - uint32_t filter; /**< TIMER Clear Input filter */ -} timer_clear_input_config_t; - -/** @brief TIMER clock source - */ -typedef enum -{ - TIMER_SRC_ETRMODE2 = 0, /**< Clock source is etr mode2 */ - TIMER_SRC_INTER = 1, /**< Clock source is etr internal */ - TIMER_SRC_ITR0 = 2, /**< Clock source is etr itr0 */ - TIMER_SRC_ITR1 = 3, /**< Clock source is etr itr1 */ - TIMER_SRC_ITR2 = 4, /**< Clock source is etr itr2 */ - TIMER_SRC_ITR3 = 5, /**< Clock source is etr itr3 */ - TIMER_SRC_TI1ED = 6, /**< Clock source is etr ti1ed */ - TIMER_SRC_TI1 = 7, /**< Clock source is etr ti1 */ - TIMER_SRC_TI2 = 8, /**< Clock source is etr ti2 */ - TIMER_SRC_ETRMODE1 = 9, /**< Clock source is etr mode1 */ -} timer_clock_source_t; - -/** @brief TIMER clock polarity - */ -typedef enum -{ - TIMER_CLK_POLARITY_INV = 1, /**< Polarity for ETRx clock sources */ - TIMER_CLK_POLARITY_NO_INV = 0, /**< Polarity for ETRx clock sources */ - TIMER_CLK_POLARITY_RISE = 0, /**< Polarity for TIx clock sources */ - TIMER_CLK_POLARITY_FALL = 1, /**< Polarity for TIx clock sources */ - TIMER_CLK_POLARITY_BOTH = 3, /**< Polarity for TIx clock sources */ -} timer_clock_polarity_t; - -/** - * @brief TIMER clock config structure definition - */ -typedef struct -{ - timer_clock_source_t source; /**< TIMER clock sources */ - timer_clock_polarity_t polarity; /**< TIMER clock polarity */ - timer_etr_psc_t psc; /**< TIMER clock prescaler */ - uint32_t filter; /**< TIMER clock filter */ -} timer_clock_config_t; - -/** - * @brief TIMER slave mode - */ -typedef enum -{ - TIMER_MODE_DISABLE = 0, /**< Slave mode is disable */ - TIMER_MODE_ENC1 = 1, /**< Slave mode is encoder1 */ - TIMER_MODE_ENC2 = 2, /**< Slave mode is encoder2 */ - TIMER_MODE_ENC3 = 3, /**< Slave mode is encoder3 */ - TIMER_MODE_RESET = 4, /**< Slave mode is reset */ - TIMER_MODE_GATED = 5, /**< Slave mode is gated */ - TIMER_MODE_TRIG = 6, /**< Slave mode is trigger */ - TIMER_MODE_EXTERNAL1 = 7, /**< Slave mode is external1 */ -} timer_slave_mode_t; - -/** - * @brief TIMER ts definition - */ -typedef enum -{ - TIMER_TS_ITR0 = 0, /**< ITR0 */ - TIMER_TS_ITR1 = 1, /**< ITR1 */ - TIMER_TS_ITR2 = 2, /**< ITR2 */ - TIMER_TS_ITR3 = 3, /**< ITR3 */ - TIMER_TS_TI1F_ED = 4, /**< TI1F_ED */ - TIMER_TS_TI1FP1 = 5, /**< TI1FP1 */ - TIMER_TS_TI2FP2 = 6, /**< TI2FP2 */ - TIMER_TS_ETRF = 7, /**< ETRF */ -} timer_ts_t; - -/** - * @brief TIMER slave configuration structure definition - */ -typedef struct -{ - timer_slave_mode_t mode; /**< Slave mode selection */ - timer_ts_t input; /**< Input Trigger source */ - timer_clock_polarity_t polarity; /**< Input Trigger polarity */ - timer_etr_psc_t psc; /**< Input trigger prescaler */ - uint32_t filter; /**< Input trigger filter */ -} timer_slave_config_t; - -/** - * @brief TIMER hall sensor configuretion structure definition - */ -typedef struct -{ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ - uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */ - uint32_t delay; /**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */ -} timer_hall_sensor_init_t; - -/** - * @brief TIMER lock level - */ -typedef enum -{ - TIMER_LOCK_LEVEL_OFF = 0, /**< Lock off */ - TIMER_LOCK_LEVEL_1 = 1, /**< Lock level 1 */ - TIMER_LOCK_LEVEL_2 = 2, /**< Lock level 2 */ - TIMER_LOCK_LEVEL_3 = 3, /**< Lock level 3 */ -} timer_lock_level_t; - -/** - * @brief TIMER break polarity - */ -typedef enum -{ - TIMER_BREAK_POLARITY_LOW = 0, /**< LOW */ - TIMER_BREAK_POLARITY_HIGH = 1, /**< HIGH */ -} timer_break_polarity_t; - -/** - * @brief TIMER break and dead time configuretion structure definition - */ -typedef struct -{ - type_func_t off_run; /**< Enalbe/Disable off state in run mode */ - type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */ - timer_lock_level_t lock_level; /**< Lock level */ - uint32_t dead_time; /**< Dead time, [0x0, 0xFF] */ - type_func_t break_state; /**< Break state */ - timer_break_polarity_t polarity; /**< Break input polarity */ - type_func_t auto_out; /**< Enalbe/Disable automatic output */ -} timer_break_dead_time_t; - -/** - * @brief TIMER commutation event channel configuretion structure definition - */ -typedef struct -{ - type_func_t en; /**< Enalbe/Disable the channel */ - type_func_t n_en; /**< Enalbe/Disable the complementary channel */ - timer_oc_mode_t mode; /**< Mode of the channel */ -} timer_channel_config_t; - -/** - * @brief TIMER commutation event configuretion structure definition - */ -typedef struct -{ - timer_channel_config_t ch[3]; /**< Configure of channel */ -} timer_com_channel_config_t; - -/** - * @brief TIMER master mode selection - */ -typedef enum -{ - TIMER_TRGO_RESET = 0, /**< RESET */ - TIMER_TRGO_ENABLE = 1, /**< ENABLE */ - TIMER_TRGO_UPDATE = 2, /**< UPDATE */ - TIMER_TRGO_OC1 = 3, /**< OC1 */ - TIMER_TRGO_OC1REF = 4, /**< OC1REF */ - TIMER_TRGO_OC2REF = 5, /**< OC2REF */ - TIMER_TRGO_OC3REF = 6, /**< OC3REF */ - TIMER_TRGO_OC4REF = 7, /**< OC4REF */ -} timer_master_mode_sel_t; - -/** - * @brief TIMER master configuretion structure definition - */ -typedef struct -{ - timer_master_mode_sel_t sel; /**< Specifies the active edge of the input signal */ - type_func_t master_en; /**< Master/Slave mode selection */ -} timer_master_config_t; - -/** - * @brief Specifies the event source - */ -typedef enum -{ - TIMER_SRC_UPDATE = (1U << 0), /**< Event source is update */ - TIMER_SRC_CC1 = (1U << 1), /**< Event source is channel1 */ - TIMER_SRC_CC2 = (1U << 2), /**< Event source is channel2 */ - TIMER_SRC_CC3 = (1U << 3), /**< Event source is channel3 */ - TIMER_SRC_CC4 = (1U << 4), /**< Event source is channel4 */ - TIMER_SRC_COM = (1U << 5), /**< Event source is compare */ - TIMER_SRC_TRIG = (1U << 6), /**< Event source is trigger */ - TIMER_SRC_BREAK = (1U << 7), /**< Event source is break */ -} timer_event_source_t; - -/** - * @brief TIMER interrupt definition - */ -typedef enum -{ - TIMER_IT_UPDATE = (1U << 0), /**< Update interrupt bit */ - TIMER_IT_CC1 = (1U << 1), /**< Channel1 interrupt bit */ - TIMER_IT_CC2 = (1U << 2), /**< Channel2 interrupt bit */ - TIMER_IT_CC3 = (1U << 3), /**< Channel3 interrupt bit */ - TIMER_IT_CC4 = (1U << 4), /**< Channel4 interrupt bit */ - TIMER_IT_COM = (1U << 5), /**< compare interrupt bit */ - TIMER_IT_TRIGGER = (1U << 6), /**< Trigger interrupt bit */ - TIMER_IT_BREAK = (1U << 7), /**< Break interrupt bit */ -} timer_it_t; - -/** - * @brief TIMER DMA request - */ -typedef enum -{ - TIMER_DMA_UPDATE = (1U << 8), /**< DMA request from update */ - TIMER_DMA_CC1 = (1U << 9), /**< DMA request from channel1 */ - TIMER_DMA_CC2 = (1U << 10), /**< DMA request from channel2 */ - TIMER_DMA_CC3 = (1U << 11), /**< DMA request from channel3 */ - TIMER_DMA_CC4 = (1U << 12), /**< DMA request from channel4 */ - TIMER_DMA_COM = (1U << 13), /**< DMA request from compare */ - TIMER_DMA_TRIGGER = (1U << 14), /**< DMA request from trigger */ -} timer_dma_req_t; - -/** - * @brief TIMER flag definition - */ -typedef enum -{ - TIMER_FLAG_UPDATE = (1U << 0), /**< Update interrupt flag */ - TIMER_FLAG_CC1 = (1U << 1), /**< Channel1 interrupt flag */ - TIMER_FLAG_CC2 = (1U << 2), /**< Channel2 interrupt flag */ - TIMER_FLAG_CC3 = (1U << 3), /**< Channel3 interrupt flag */ - TIMER_FLAG_CC4 = (1U << 4), /**< Channel4 interrupt flag */ - TIMER_FLAG_COM = (1U << 5), /**< Compare interrupt flag */ - TIMER_FLAG_TRIGGER = (1U << 6), /**< Trigger interrupt flag */ - TIMER_FLAG_BREAK = (1U << 7), /**< Break interrupt flag */ - TIMER_FLAG_CC1OF = (1U << 9), /**< Channel1 override state flag */ - TIMER_FLAG_CC2OF = (1U << 10), /**< Channel2 override state flag */ - TIMER_FLAG_CC3OF = (1U << 11), /**< Channel3 override state flag */ - TIMER_FLAG_CC4OF = (1U << 12), /**< Channel4 override state flag */ -} timer_flag_t; -/** - * @} - */ - -/** @defgroup TIMER_Public_Macros TIMER Public Macros - * @{ - */ -#define CCER_CCxE_MASK ((1U << 0) | (1U << 4) | (1U << 8) | (1U << 12)) -#define CCER_CCxNE_MASK ((1U << 2) | (1U << 6) | (1U << 10)) - -/** - * @brief Reset TIMER handle state - */ -#define TIMER_RESET_HANDLE_STATE(hperh) ((hperh)->state = TIMER_STATE_RESET) - -/** - * @brief Enable the TIMER peripheral. - */ -#define TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK)) - -/** - * @brief Enable the TIMER main output. - */ -#define TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK)) - -/** - * @brief Disable the TIMER peripheral. - */ -#define TIMER_DISABLE(hperh) \ -do { \ - if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ - && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ - CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ -} while (0) - -/** - * @brief Disable the TIMER main output. - * @note The Main Output Enable of a timer instance is disabled only if - * all the CCx and CCxN channels have been disabled - */ -#define TIMER_MOE_DISABLE(hperh) \ -do { \ - if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ - && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ - CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ -} while (0) - -/** - * @brief Sets the TIMER autoreload register value on runtime without calling - * another time any Init function. - */ -#define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ -do { \ - (handle)->perh->AR = (AUTORELOAD); \ - (handle)->init.period = (AUTORELOAD); \ -} while (0) - -/** - * @brief Gets the TIMER autoreload register value on runtime - */ -#define TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR) - -/** - * @brief Gets the TIMER count register value on runtime - */ -#define TIMER_GET_CNT(handle) ((handle)->perh->COUNT) - -/** - * @brief Gets the TIMER count direction value on runtime - */ -#define TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS)) - -/** - * @brief CCx DMA request sent when CCx event occurs - */ -#define TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) - -/** - * @brief CCx DMA request sent when update event occurs - */ -#define TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) - -/** - * @brief Enable channel - * @param handle: TIMER handle - * @param ch: Must be one of this: - * TIMER_CHANNEL_1 - * TIMER_CHANNEL_2 - * TIMER_CHANNEL_3 - * TIMER_CHANNEL_4 - */ -#define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ -(SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) - -/** - * @brief Disable channel - * @param handle: TIMER handle - * @param ch: Must be one of this: - * TIMER_CHANNEL_1 - * TIMER_CHANNEL_2 - * TIMER_CHANNEL_3 - * TIMER_CHANNEL_4 - */ -#define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ -(CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) - -/** - * @brief Enable complementary channel - * @param handle: TIMER handle - * @param ch: Must be one of this: - * TIMER_CHANNEL_1 - * TIMER_CHANNEL_2 - * TIMER_CHANNEL_3 - */ -#define TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) - -/** - * @brief Disable complementary channel - * @param handle: TIMER handle - * @param ch: Must be one of this: - * TIMER_CHANNEL_1 - * TIMER_CHANNEL_2 - * TIMER_CHANNEL_3 - */ -#define TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) -/** - * @} - */ - -/** @defgroup TIMER_Private_Macros TIMER Private Macros - * @{ - */ -#define IS_TIMER_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER1) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3) || \ - ((x) == TIMER4) || \ - ((x) == TIMER5) || \ - ((x) == TIMER6) || \ - ((x) == TIMER7)) -#define IS_ADTIMER_INSTANCE(x) ((x) == TIMER0) -#define IS_TIMER_XOR_INSTANCE(x) (((x) == TIMER0) || ((x) == TIMER6)) -#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3)) -#define IS_TIMER_CC2_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3) || \ - ((x) == TIMER6)) -#define IS_TIMER_CC4_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER6)) -#define IS_TIMER_BREAK_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3)) -#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == TIMER0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == TIMER2) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == TIMER3) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == TIMER6) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2)))) -#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == TIMER0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) || \ - (((x) == TIMER2) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == TIMER3) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == TIMER6) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4)))) -#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == TIMER0) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3)) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) -#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3)) -#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) -#define IS_TIMER_COUNTER_MODE(x) (((x) == TIMER_CNT_MODE_UP) || \ - ((x) == TIMER_CNT_MODE_DOWN) || \ - ((x) == TIMER_CNT_MODE_CENTER1) || \ - ((x) == TIMER_CNT_MODE_CENTER2) || \ - ((x) == TIMER_CNT_MODE_CENTER3)) -#define IS_TIMER_CLOCK_DIVISION(x) (((x) == TIMER_CLOCK_DIV1) || \ - ((x) == TIMER_CLOCK_DIV2) || \ - ((x) == TIMER_CLOCK_DIV4)) -#define IS_TIMER_PWM_MODE(x) (((x) == TIMER_OC_MODE_PWM1) || \ - ((x) == TIMER_OC_MODE_PWM2)) -#define IS_TIMER_OC_MODE(x) (((x) == TIMER_OC_MODE_TIMERING) || \ - ((x) == TIMER_OC_MODE_ACTIVE) || \ - ((x) == TIMER_OC_MODE_INACTIVE) || \ - ((x) == TIMER_OC_MODE_TOGGLE) || \ - ((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \ - ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \ - ((x) == TIMER_OC_MODE_PWM1) || \ - ((x) == TIMER_OC_MODE_PWM2)) -#define IS_TIMER_OC_POLARITY(x) (((x) == TIMER_OC_POLARITY_HIGH) || \ - ((x) == TIMER_OC_POLARITY_LOW)) -#define IS_TIMER_OCN_POLARITY(x) (((x) == TIMER_OCN_POLARITY_HIGH) || \ - ((x) == TIMER_OCN_POLARITY_LOW)) -#define IS_TIMER_OCIDLE_STATE(x) (((x) == TIMER_OC_IDLE_RESET) || \ - ((x) == TIMER_OC_IDLE_SET)) -#define IS_TIMER_OCNIDLE_STATE(x) (((x) == TIMER_OCN_IDLE_RESET) || \ - ((x) == TIMER_OCN_IDLE_SET)) -#define IS_TIMER_CHANNELS(x) (((x) == TIMER_CHANNEL_1) || \ - ((x) == TIMER_CHANNEL_2) || \ - ((x) == TIMER_CHANNEL_3) || \ - ((x) == TIMER_CHANNEL_4) || \ - ((x) == TIMER_CHANNEL_ALL)) -#define IS_TIMER_OP_MODE(x) (((x) == TIMER_OP_MODE_REPEAT) || \ - ((x) == TIMER_OP_MODE_SINGLE)) -#define IS_TIMER_OP_OUTPUT_CH(x) (((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \ - ((x) == TIMER_OP_OUTPUT_CHANNEL_2)) -#define IS_TIMER_ENCODER_MODE(x) (((x) == TIMER_ENC_MODE_TI1) || \ - ((x) == TIMER_ENC_MODE_TI2) || \ - ((x) == TIMER_ENC_MODE_TI12)) -#define IS_TIMER_IC_POLARITY(x) (((x) == TIMER_IC_POLARITY_RISE) || \ - ((x) == TIMER_IC_POLARITY_FALL) || \ - ((x) == TIMER_IC_POLARITY_BOTH)) -#define IS_TIMER_IC_SELECT(x) (((x) == TIMER_IC_SEL_DIRECT) || \ - ((x) == TIMER_IC_SEL_INDIRECT) || \ - ((x) == TIMER_IC_SEL_TRC)) -#define IS_TIMER_IC_PSC(x) (((x) == TIMER_IC_PSC_DIV1) || \ - ((x) == TIMER_IC_PSC_DIV2) || \ - ((x) == TIMER_IC_PSC_DIV4) || \ - ((x) == TIMER_IC_PSC_DIV8)) -#define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) -#define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) -#define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == TIMER_INPUT_NONE) || \ - ((x) == TIMER_INPUT_ETR)) -#define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == TIMER_POLARITY_NO_INV) || \ - ((x) == TIMER_POLARITY_INV)) -#define IS_TIMER_ETR_PSC(x) (((x) == TIMER_ETR_PSC_DIV1) || \ - ((x) == TIMER_ETR_PSC_DIV2) || \ - ((x) == TIMER_ETR_PSC_DIV4) || \ - ((x) == TIMER_ETR_PSC_DIV8)) -#define IS_TIMER_CLOCK_SOURCE(x) (((x) == TIMER_SRC_ETRMODE2) || \ - ((x) == TIMER_SRC_INTER) || \ - ((x) == TIMER_SRC_ITR0) || \ - ((x) == TIMER_SRC_ITR1) || \ - ((x) == TIMER_SRC_ITR2) || \ - ((x) == TIMER_SRC_ITR3) || \ - ((x) == TIMER_SRC_TI1ED) || \ - ((x) == TIMER_SRC_TI1) || \ - ((x) == TIMER_SRC_TI2) || \ - ((x) == TIMER_SRC_ETRMODE1)) -#define IS_TIMER_CLOCK_POLARITY(x) (((x) == TIMER_CLK_POLARITY_INV) || \ - ((x) == TIMER_CLK_POLARITY_NO_INV) || \ - ((x) == TIMER_CLK_POLARITY_RISE) || \ - ((x) == TIMER_CLK_POLARITY_FALL) || \ - ((x) == TIMER_CLK_POLARITY_BOTH)) -#define IS_TIMER_SLAVE_MODE(x) (((x) == TIMER_MODE_DISABLE) || \ - ((x) == TIMER_MODE_ENC1) || \ - ((x) == TIMER_MODE_ENC2) || \ - ((x) == TIMER_MODE_ENC3) || \ - ((x) == TIMER_MODE_RESET) || \ - ((x) == TIMER_MODE_GATED) || \ - ((x) == TIMER_MODE_TRIG) || \ - ((x) == TIMER_MODE_EXTERNAL1)) -#define IS_TIMER_EVENT_SOURCE(x) (((x) == TIMER_SRC_UPDATE) || \ - ((x) == TIMER_SRC_CC1) || \ - ((x) == TIMER_SRC_CC2) || \ - ((x) == TIMER_SRC_CC3) || \ - ((x) == TIMER_SRC_CC4) || \ - ((x) == TIMER_SRC_COM) || \ - ((x) == TIMER_SRC_TRIG) || \ - ((x) == TIMER_SRC_BREAK)) -#define IS_TIMER_TS(x) (((x) == TIMER_TS_ITR0) || \ - ((x) == TIMER_TS_ITR1) || \ - ((x) == TIMER_TS_ITR2) || \ - ((x) == TIMER_TS_ITR3) || \ - ((x) == TIMER_TS_TI1F_ED) || \ - ((x) == TIMER_TS_TI1FP1) || \ - ((x) == TIMER_TS_TI2FP2) || \ - ((x) == TIMER_TS_ETRF)) -#define IS_TIMER_CLOCK_LEVEL(x) (((x) == TIMER_LOCK_LEVEL_OFF) || \ - ((x) == TIMER_LOCK_LEVEL_1) || \ - ((x) == TIMER_LOCK_LEVEL_2) || \ - ((x) == TIMER_LOCK_LEVEL_3)) -#define IS_TIMER_BREAK_POLARITY(x) (((x) == TIMER_BREAK_POLARITY_LOW) || \ - ((x) == TIMER_BREAK_POLARITY_HIGH)) -#define IS_TIMER_MASTER_MODE_SEL(x) (((x) == TIMER_TRGO_RESET) || \ - ((x) == TIMER_TRGO_ENABLE) || \ - ((x) == TIMER_TRGO_UPDATE) || \ - ((x) == TIMER_TRGO_OC1) || \ - ((x) == TIMER_TRGO_OC1REF) || \ - ((x) == TIMER_TRGO_OC2REF) || \ - ((x) == TIMER_TRGO_OC3REF) || \ - ((x) == TIMER_TRGO_OC4REF)) -#define IS_TIMER_IT(x) (((x) == TIMER_IT_UPDATE) || \ - ((x) == TIMER_IT_CC1) || \ - ((x) == TIMER_IT_CC2) || \ - ((x) == TIMER_IT_CC3) || \ - ((x) == TIMER_IT_CC4) || \ - ((x) == TIMER_IT_COM) || \ - ((x) == TIMER_IT_TRIGGER) || \ - ((x) == TIMER_IT_BREAK)) -#define IS_TIMER_DMA_REQ(x) (((x) == TIMER_DMA_UPDATE) || \ - ((x) == TIMER_DMA_CC1) || \ - ((x) == TIMER_DMA_CC2) || \ - ((x) == TIMER_DMA_CC3) || \ - ((x) == TIMER_DMA_CC4) || \ - ((x) == TIMER_DMA_COM) || \ - ((x) == TIMER_DMA_TRIGGER)) -#define IS_TIMER_FLAG(x) (((x) == TIMER_FLAG_UPDATE) || \ - ((x) == TIMER_FLAG_CC1) || \ - ((x) == TIMER_FLAG_CC2) || \ - ((x) == TIMER_FLAG_CC3) || \ - ((x) == TIMER_FLAG_CC4) || \ - ((x) == TIMER_FLAG_COM) || \ - ((x) == TIMER_FLAG_TRIGGER) || \ - ((x) == TIMER_FLAG_BREAK) || \ - ((x) == TIMER_FLAG_CC1OF) || \ - ((x) == TIMER_FLAG_CC2OF) || \ - ((x) == TIMER_FLAG_CC3OF) || \ - ((x) == TIMER_FLAG_CC4OF)) -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions - * @{ - */ -/** @addtogroup TIMER_Public_Functions_Group1 - * @{ - */ -/* Time Base functions */ -ald_status_t timer_base_init(timer_handle_t *hperh); -void timer_base_reset(timer_handle_t *hperh); -void timer_base_start(timer_handle_t *hperh); -void timer_base_stop(timer_handle_t *hperh); -void timer_base_start_by_it(timer_handle_t *hperh); -void timer_base_stop_by_it(timer_handle_t *hperh); -#ifdef ALD_DMA -ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_base_stop_by_dma(timer_handle_t *hperh); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group2 - * @{ - */ -/* Timer Output Compare functions */ -ald_status_t timer_oc_init(timer_handle_t *hperh); -void timer_oc_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group3 - * @{ - */ -/* Timer PWM functions */ -ald_status_t timer_pwm_init(timer_handle_t *hperh); -void timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq); -void timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty); -void timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group4 - * @{ - */ -/* Timer Input Capture functions */ -ald_status_t timer_ic_init(timer_handle_t *hperh); -void timer_ic_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group5 - * @{ - */ -/* Timer One Pulse functions */ -ald_status_t timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode); -void timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch); -void timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch); -void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); -void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group6 - * @{ - */ -/* Timer encoder functions */ -ald_status_t timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config); -void timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, - uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2); -void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group7 - * @{ - */ -/* Timer hall sensor functions */ -ald_status_t timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config); -void timer_hall_sensor_start(timer_handle_t *hperh); -void timer_hall_sensor_stop(timer_handle_t *hperh); -void timer_hall_sensor_start_by_it(timer_handle_t *hperh); -void timer_hall_sensor_stop_by_it(timer_handle_t *hperh); -#ifdef ALD_DMA -ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group8 - * @{ - */ -/* Timer complementary output compare functions */ -void timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group9 - * @{ - */ -/* Timer complementary PWM functions */ -void timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group10 - * @{ - */ -/* Timer complementary one pulse functions */ -void timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group11 - * @{ - */ -/* Control functions */ -ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch); -ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch); -ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, - timer_channel_t ch_out, timer_channel_t ch_in); -ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch); -ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config); -ald_status_t timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select); -ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config); -ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config); -ald_status_t timer_generate_event(timer_handle_t *hperh, timer_event_source_t event); -uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch); -void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch); -void timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config); -void timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); -void timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); -void timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config); -void timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config); -void timer_irq_handle(timer_handle_t *hperh); -void timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state); -void timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state); -it_status_t timer_get_it_status(timer_handle_t *hperh, timer_it_t it); -flag_status_t timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag); -void timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag); -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group12 - * @{ - */ -/* State functions */ -timer_state_t timer_get_state(timer_handle_t *hperh); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_TIMER_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h deleted file mode 100644 index 072f892184e98c63b3fce50002da56babe0edbbb..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h +++ /dev/null @@ -1,182 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_trng.h - * @brief Header file of TRNG module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_TRNG_H__ -#define __ALD_TRNG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup TRNG - * @{ - */ - -/** @defgroup TRNG_Public_Macros TRNG Public Macros - * @{ - */ -#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) -#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) -#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) -#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) -/** - * @} - */ - -/** @defgroup TRNG_Public_Types TRNG Public Types - * @{ - */ -/** - * @brief Data width - */ -typedef enum -{ - TRNG_DSEL_1B = 0x0, /**< 1-bit */ - TRNG_DSEL_8B = 0x1, /**< 8-bit */ - TRNG_DSEL_16B = 0x2, /**< 16-bit */ - TRNG_DSEL_32B = 0x3, /**< 32-bit */ -} trng_data_width_t; - -/** - * @brief seed type - */ -typedef enum -{ - TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */ - TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */ - TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */ - TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */ -} trng_seed_type_t; - -/** - * @brief TRNG init structure definition - */ -typedef struct -{ - trng_data_width_t data_width; /**< The width of data */ - trng_seed_type_t seed_type; /**< The seed type */ - uint32_t seed; /**< The value of seed */ - uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */ - uint8_t adjc; /**< Adjust parameter */ - uint8_t posten; -} trng_init_t; - -/** - * @brief State type - */ -typedef enum -{ - TRNG_STATUS_START = (1U << 0), /**< Start state */ - TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ - TRNG_STATUS_SERR = (1U << 2), /**< Error state */ -} trng_status_t; - -/** - * @brief Interrupt type - */ -typedef enum -{ - TRNG_IT_START = (1U << 0), /**< Start */ - TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ - TRNG_IT_SERR = (1U << 2), /**< Error */ -} trng_it_t; - -/** - * @brief Interrupt flag type - */ -typedef enum -{ - TRNG_IF_START = (1U << 0), /**< Start */ - TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ - TRNG_IF_SERR = (1U << 2), /**< Error */ -} trng_flag_t; -/** - * @} - */ - -/** - * @defgroup TRNG_Private_Macros TRNG Private Macros - * @{ - */ -#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \ - ((x) == TRNG_DSEL_8B) || \ - ((x) == TRNG_DSEL_16B) || \ - ((x) == TRNG_DSEL_32B)) -#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \ - ((x) == TRNG_SEED_TYPE_1) || \ - ((x) == TRNG_SEED_TYPE_LAST) || \ - ((x) == TRNG_SEED_TYPE_SEED)) -#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \ - ((x) == TRNG_STATUS_DAVLD) || \ - ((x) == TRNG_STATUS_SERR)) -#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ - ((x) == TRNG_IT_DAVLD) || \ - ((x) == TRNG_IT_SERR)) -#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ - ((x) == TRNG_IF_DAVLD) || \ - ((x) == TRNG_IF_SERR)) -#define IS_TRNG_ADJC(x) ((x) < 4) -/** - * @} - */ - -/** @addtogroup TRNG_Public_Functions - * @{ - */ -/** @addtogroup TRNG_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -extern void trng_init(trng_init_t *init); -/** - * @} - */ -/** @addtogroup TRNG_Public_Functions_Group2 - * @{ - */ -/* Control functions */ -extern uint32_t trng_get_result(void); -extern void trng_interrupt_config(trng_it_t it, type_func_t state); -extern flag_status_t trng_get_status(trng_status_t status); -extern it_status_t trng_get_it_status(trng_it_t it); -extern flag_status_t trng_get_flag_status(trng_flag_t flag); -extern void trng_clear_flag_status(trng_flag_t flag); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_TRNG_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h deleted file mode 100644 index 0d8b1899318a382fdfaf77b7bbeebce63a5a094e..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h +++ /dev/null @@ -1,478 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_uart.h - * @brief Header file of UART module library. - * - * @version V1.0 - * @date 21 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_UART_H__ -#define __ALD_UART_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/** - * @defgroup UART_Public_Macros UART Public Macros - * @{ - */ -#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) -#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) -#define UART_BRR_WRITE_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) -#define UART_BRR_WRITE_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) -#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) -#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) -#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) -#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) -#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) -#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) -#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) -#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) -#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) -#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) -#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) -#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) -#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) -#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) -#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_TFRST_MSK)) -#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_RFRST_MSK)) -#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) -#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) -#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) -#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) -#define UART_AUTOBR_RESTART(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABRRS_MSK)) -#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR)) -#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS)) -/** - * @} - */ - -/** @defgroup UART_Public_Types UART Public Types - * @{ - */ -/** - * @brief UART word length - */ -typedef enum -{ - UART_WORD_LENGTH_5B = 0x0, /**< 5-bits */ - UART_WORD_LENGTH_6B = 0x1, /**< 6-bits */ - UART_WORD_LENGTH_7B = 0x2, /**< 7-bits */ - UART_WORD_LENGTH_8B = 0x3, /**< 8-bits */ -} uart_word_length_t; - -/** - * @brief UART stop bits - */ -typedef enum -{ - UART_STOP_BITS_1 = 0x0, /**< 1-bits */ - UART_STOP_BITS_2 = 0x1, /**< 2-bits */ - UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */ - UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */ -} uart_stop_bits_t; - -/** - * @brief UART parity - */ -typedef enum -{ - UART_PARITY_NONE = 0x0, /**< Not parity */ - UART_PARITY_ODD = 0x1, /**< Odd parity */ - UART_PARITY_EVEN = 0x3, /**< Even parity */ -} uart_parity_t; - -/** - * @brief UART mode - */ -typedef enum -{ - UART_MODE_UART = 0x0, /**< UART */ - UART_MODE_LIN = 0x1, /**< LIN */ - UART_MODE_IrDA = 0x2, /**< IrDA */ - UART_MODE_RS485 = 0x3, /**< RS485 */ - UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */ -} uart_mode_t; - -/** - * @brief UART hardware flow control - */ -typedef enum -{ - UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */ - UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */ -} uart_hw_flow_ctl_t; - -/** - * @brief ALD UART state - */ -typedef enum -{ - UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ - UART_STATE_TIMEOUT = 0x03, /**< Timeout state */ - UART_STATE_ERROR = 0x04, /**< Error */ -} uart_state_t; - -/** - * @brief UART error codes - */ -typedef enum -{ - UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ -} uart_error_t; - -/** - * @brief UART init structure definition - */ -typedef struct -{ - uint32_t baud; /**< Specifies the uart communication baud rate */ - uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ - uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ - uart_parity_t parity; /**< Specifies the parity mode */ - uart_mode_t mode; /**< Specifies uart mode */ - uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ -} uart_init_t; - -/** - * @brief UART handle structure definition - */ -typedef struct uart_handle_s -{ - UART_TypeDef *perh; /**< UART registers base address */ - uart_init_t init; /**< UART communication parameters */ - uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ - uint16_t tx_size; /**< UART Tx Transfer size */ - uint16_t tx_count; /**< UART Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ - uint16_t rx_size; /**< UART Rx Transfer size */ - uint16_t rx_count; /**< UART Rx Transfer Counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - uart_state_t state; /**< UART communication state */ - uart_error_t err_code; /**< UART Error code */ - - void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ -} uart_handle_t; - -/** - * @brief UART RS485 configure structure definition - */ -typedef struct -{ - type_func_t normal; /**< Normal mode */ - type_func_t dir; /**< Auto-direction mode */ - type_func_t invert; /**< Address detection invert */ - uint8_t addr; /**< Address for compare */ -} uart_rs485_config_t; - -/** - * @brief LIN detection break length - */ -typedef enum -{ - LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */ - LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */ -} uart_lin_break_len_t; - -/** - * @brief UART TXFIFO size - */ -typedef enum -{ - UART_TXFIFO_EMPTY = 0x0, /**< Empty */ - UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */ - UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */ - UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */ -} uart_txfifo_t; - -/** - * @brief UART RXFIFO size - */ -typedef enum -{ - UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */ - UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */ - UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */ - UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */ -} uart_rxfifo_t; - -/** - * @brief UART auto-baud mode - */ -typedef enum -{ - UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */ - UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */ - UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */ -} uart_auto_baud_mode_t; - -/** - * @brief UART status types - */ -typedef enum -{ - UART_STATUS_DR = (1U << 0), /**< Data ready */ - UART_STATUS_OE = (1U << 1), /**< Overrun error */ - UART_STATUS_PE = (1U << 2), /**< Parity error */ - UART_STATUS_FE = (1U << 3), /**< Framing error */ - UART_STATUS_BI = (1U << 4), /**< Break interrupt */ - UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */ - UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */ - UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */ - UART_STATUS_BUSY = (1U << 8), /**< UART busy */ - UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */ - UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */ - UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */ - UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */ - UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */ - UART_STATUS_CTS = (1U << 15), /**< Clear to send */ -} uart_status_t; - -/** - * @brief UART interrupt types - */ -typedef enum -{ - UART_IT_RXRD = (1U << 0), /**< Receive data available */ - UART_IT_TXS = (1U << 1), /**< Tx empty status */ - UART_IT_RXS = (1U << 2), /**< Rx line status */ - UART_IT_MDS = (1U << 3), /**< Modem status */ - UART_IT_RTO = (1U << 4), /**< Receiver timeout */ - UART_IT_BZ = (1U << 5), /**< Busy status */ - UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */ - UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ - UART_IT_LINBK = (1U << 8), /**< Lin break detection */ - UART_IT_TC = (1U << 9), /**< Transmission complete */ - UART_IT_EOB = (1U << 10), /**< End of block */ - UART_IT_CM = (1U << 11), /**< Character match */ -} uart_it_t; - -/** - * @brief UART flags types - */ -typedef enum -{ - UART_IF_RXRD = (1U << 0), /**< Receive data available */ - UART_IF_TXS = (1U << 1), /**< Tx empty status */ - UART_IF_RXS = (1U << 2), /**< Rx line status */ - UART_IF_MDS = (1U << 3), /**< Modem status */ - UART_IF_RTO = (1U << 4), /**< Receiver timeout */ - UART_IF_BZ = (1U << 5), /**< Busy status */ - UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */ - UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ - UART_IF_LINBK = (1U << 8), /**< Lin break detection */ - UART_IF_TC = (1U << 9), /**< Transmission complete */ - UART_IF_EOB = (1U << 10), /**< End of block */ - UART_IF_CM = (1U << 11), /**< Character match */ -} uart_flag_t; -/** - * @} - */ - -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ -#define IS_UART_ALL(x) (((x) == UART0) || \ - ((x) == UART1) || \ - ((x) == UART2) || \ - ((x) == UART3)) -#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \ - ((x) == UART_WORD_LENGTH_6B) || \ - ((x) == UART_WORD_LENGTH_7B) || \ - ((x) == UART_WORD_LENGTH_8B)) -#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \ - ((x) == UART_STOP_BITS_2) || \ - ((x) == UART_STOP_BITS_0_5) || \ - ((x) == UART_STOP_BITS_1_5)) -#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \ - ((x) == UART_PARITY_ODD) || \ - ((x) == UART_PARITY_EVEN)) -#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \ - ((x) == UART_MODE_LIN) || \ - ((x) == UART_MODE_IrDA) || \ - ((x) == UART_MODE_RS485) || \ - ((x) == UART_MODE_HDSEL)) -#define IS_UART_HARDWARE_FLOW_CONTROL(x) \ - (((x) == UART_HW_FLOW_CTL_DISABLE) || \ - ((x) == UART_HW_FLOW_CTL_ENABLE)) -#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \ - ((x) == LIN_BREAK_LEN_11B)) -#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \ - ((x) == UART_TXFIFO_2BYTE) || \ - ((x) == UART_TXFIFO_4BYTE) || \ - ((x) == UART_TXFIFO_8BYTE)) -#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \ - ((x) == UART_RXFIFO_4BYTE) || \ - ((x) == UART_RXFIFO_8BYTE) || \ - ((x) == UART_RXFIFO_14BYTE)) -#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \ - ((x) == UART_ABRMOD_1) || \ - ((x) == UART_ABRMOD_0_TO_1)) -#define IS_UART_STATUS(x) (((x) == UART_STATUS_DR) || \ - ((x) == UART_STATUS_OE) || \ - ((x) == UART_STATUS_PE) || \ - ((x) == UART_STATUS_FE) || \ - ((x) == UART_STATUS_BI) || \ - ((x) == UART_STATUS_TBEM) || \ - ((x) == UART_STATUS_TEM) || \ - ((x) == UART_STATUS_RFE) || \ - ((x) == UART_STATUS_BUSY) || \ - ((x) == UART_STATUS_TFNF) || \ - ((x) == UART_STATUS_TFEM) || \ - ((x) == UART_STATUS_RFNE) || \ - ((x) == UART_STATUS_RFF) || \ - ((x) == UART_STATUS_DCTS) || \ - ((x) == UART_STATUS_CTS)) -#define IS_UART_IT(x) (((x) == UART_IT_RXRD) || \ - ((x) == UART_IT_TXS) || \ - ((x) == UART_IT_RXS) || \ - ((x) == UART_IT_MDS) || \ - ((x) == UART_IT_RTO) || \ - ((x) == UART_IT_BZ) || \ - ((x) == UART_IT_ABE) || \ - ((x) == UART_IT_ABTO) || \ - ((x) == UART_IT_LINBK) || \ - ((x) == UART_IT_TC) || \ - ((x) == UART_IT_EOB) || \ - ((x) == UART_IT_CM)) -#define IS_UART_IF(x) (((x) == UART_IF_RXRD) || \ - ((x) == UART_IF_TXS) || \ - ((x) == UART_IF_RXS) || \ - ((x) == UART_IF_MDS) || \ - ((x) == UART_IF_RTO) || \ - ((x) == UART_IF_BZ) || \ - ((x) == UART_IF_ABE) || \ - ((x) == UART_IF_ABTO) || \ - ((x) == UART_IF_LINBK) || \ - ((x) == UART_IF_TC) || \ - ((x) == UART_IF_EOB) || \ - ((x) == UART_IF_CM)) -#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) -#define IS_UART_DATA(x) ((x) <= 0x1FF) - -#define UART_STATE_TX_MASK (1U << 4) -#define UART_STATE_RX_MASK (1U << 5) -/** - * @} - */ - -/** @addtogroup UART_Public_Functions - * @{ - */ - -/** @addtogroup UART_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -void uart_init(uart_handle_t *hperh); -void uart_reset(uart_handle_t *hperh); -void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config); -/** - * @} - */ - -/** @addtogroup UART_Public_Functions_Group2 - * @{ - */ -/* IO operation functions */ -ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t uart_dma_pause(uart_handle_t *hperh); -ald_status_t uart_dma_resume(uart_handle_t *hperh); -ald_status_t uart_dma_stop(uart_handle_t *hperh); -#endif -void uart_irq_handle(uart_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup UART_Public_Functions_Group3 - * @{ - */ -/* Peripheral Control functions */ -void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state); -void uart_dma_req_config(uart_handle_t *hperh, type_func_t state); -void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); -void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); -void uart_lin_send_break(uart_handle_t *hperh); -void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len); -void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode); -ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout); -it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it); -flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status); -flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag); -flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag); -void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag); -/** - * @} - */ - -/** @addtogroup UART_Public_Functions_Group4 - * @{ - */ -/* Peripheral State and Errors functions */ -uart_state_t uart_get_state(uart_handle_t *hperh); -uint32_t uart_get_error(uart_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_UART_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h deleted file mode 100644 index 07aac584f1a16535df2add0a1001ec93bd99d690..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h +++ /dev/null @@ -1,580 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_usart.h - * @brief Header file of USART module library. - * - * @version V1.0 - * @date 16 Apr 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_USART_H__ -#define __ALD_USART_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/** @defgroup USART_Public_Types USART Public Types - * @{ - */ - -/** - * @brief usart_word_length - */ -typedef enum -{ - USART_WORD_LENGTH_8B = 0x0, /**< Word length is 8-bits */ - USART_WORD_LENGTH_9B = 0x1, /**< Word length is 9-bits */ -} usart_word_length_t; - -/** - * @brief usart_stop_bits - */ -typedef enum -{ - USART_STOP_BITS_1 = 0x0, /**< Stop bits is 1-bits */ - USART_STOP_BITS_0_5 = 0x1, /**< Stop bits is 0.5-bits */ - USART_STOP_BITS_2 = 0x2, /**< Stop bits is 2-bits */ - USART_STOP_BITS_1_5 = 0x3, /**< Stop bits is 1.5-bits */ -} usart_stop_bits_t; - -/** - * @brief usart_parity - */ -typedef enum -{ - USART_PARITY_NONE = 0x0, /**< Not parity */ - USART_PARITY_EVEN = 0x2, /**< Even parity */ - USART_PARITY_ODD = 0x3, /**< Odd parity */ -} usart_parity_t; - -/** - * @brief usart_mode - */ -typedef enum -{ - USART_MODE_RX = 0x1, /**< TX mode */ - USART_MODE_TX = 0x2, /**< RX mode */ - USART_MODE_TX_RX = 0x3, /**< TX & RX mode */ -} usart_mode_t; - -/** - * @brief usart_hardware_flow_control - */ -typedef enum -{ - USART_HW_FLOW_CTL_NONE = 0x0, /**< Not flow control */ - USART_HW_FLOW_CTL_RTS = 0x1, /**< RTS flow control */ - USART_HW_FLOW_CTL_CTS = 0x2, /**< CTS flow control */ - USART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS flow control */ -} usart_hw_flow_ctl_t; - -/** - * @brief usart_clock - */ -typedef enum -{ - USART_CLOCK_DISABLE = 0x0, /**< Disable clock output */ - USART_CLOCK_ENABLE = 0x1, /**< Enable clock output */ -} usart_clock_t; - -/** - * @brief usart_clock_polarity - */ -typedef enum -{ - USART_CPOL_LOW = 0x0, /**< Clock polarity low */ - USART_CPOL_HIGH = 0x1, /**< Clock polarity high */ -} usart_cpol_t; - -/** - * @brief usart_clock_phase - */ -typedef enum -{ - USART_CPHA_1EDGE = 0x0, /**< Clock phase first edge */ - USART_CPHA_2EDGE = 0x1, /**< Clock phase second edge */ -} usart_cpha_t; - -/** - * @brief usart_last_bit - */ -typedef enum -{ - USART_LAST_BIT_DISABLE = 0x0, /**< Disable last bit clock output */ - USART_LAST_BIT_ENABLE = 0x1, /**< Enable last bit clock output */ -} usart_last_bit_t; - -/** - * @brief usart state structures definition - */ -typedef enum -{ - USART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - USART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - USART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - USART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - USART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - USART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ - USART_STATE_TIMEOUT = 0x03, /**< Timeout state */ - USART_STATE_ERROR = 0x04, /**< Error */ -} usart_state_t; - -/** - * @brief usart error codes - */ -typedef enum -{ - USART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - USART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - USART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - USART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - USART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - USART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ -} usart_error_t; - - -/** - * @brief usart init structure definition - */ -typedef struct -{ - uint32_t baud; /**< This member configures the Usart communication baud rate. */ - usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ - usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ - usart_parity_t parity; /**< Specifies the parity mode. - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - usart_mode_t mode; /**< Specifies wether the Receive or Transmit mode is enabled or disabled. */ - usart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled. */ - type_func_t over_sampling; /**< Specifies whether the Over sampling 8 is enabled or disabled. */ -} usart_init_t; - -/** - * @brief USART handle structure definition - */ -typedef struct usart_handle_s -{ - USART_TypeDef *perh; /**< USART registers base address */ - usart_init_t init; /**< USART communication parameters */ - uint8_t *tx_buf; /**< Pointer to USART Tx transfer buffer */ - uint16_t tx_size; /**< USART Tx transfer size */ - uint16_t tx_count; /**< USART Tx transfer counter */ - uint8_t *rx_buf; /**< Pointer to USART Rx transfer buffer */ - uint16_t rx_size; /**< USART Rx Transfer size */ - uint16_t rx_count; /**< USART Rx Transfer Counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< USART Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< USART Rx DMA handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - usart_state_t state; /**< USART communication state */ - uint32_t err_code; /**< USART error code */ - - void (*tx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct usart_handle_s *arg); /**< Rx completed callback */ - void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx & Rx completed callback */ - void (*error_cbk)(struct usart_handle_s *arg); /**< error callback */ -} usart_handle_t; - - -/** - * @brief USART clock init structure definition - */ -typedef struct -{ - usart_clock_t clk; /**< Pecifies whether the USART clock is enable or disable. */ - usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ - usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made. */ - usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. */ -} usart_clock_init_t; - - -/** - * @brief usart_dma_request - */ -typedef enum -{ - USART_DMA_REQ_TX = (1U << 7), /**< TX dma bit */ - USART_DMA_REQ_RX = (1U << 6), /**< RX dma bit */ -} usart_dma_req_t; - -/** - * @brief usart_wakeup_methods - */ -typedef enum -{ - USART_WAKEUP_IDLE = 0x0, /**< Wake up the machine when bus-line is idle */ - USART_WAKEUP_ADDR = 0x1, /**< Wake up the machine when match the address */ -} usart_wakeup_t; - -/** - * @brief usart_IrDA_low_power - */ -typedef enum -{ - USART_IrDA_MODE_NORMAL = 0x0, /**< Normal IrDA mode */ - USART_IrDA_MODE_LOW_POWER = 0x1, /**< Low-power IrDA mode */ -} usart_IrDA_mode_t; - -/** - * @brief USART interrupts definition - */ -typedef enum -{ - USART_IT_PE = ((1U << 8) | (1U << 16)), /**< Parity error */ - USART_IT_TXE = ((1U << 7) | (1U << 16)), /**< Tx empty */ - USART_IT_TC = ((1U << 6) | (1U << 16)), /**< Tx complete */ - USART_IT_RXNE = ((1U << 5) | (1U << 16)), /**< Rx not empty */ - USART_IT_IDLE = ((1U << 4) | (1U << 16)), /**< Idle */ - USART_IT_CTS = ((1U << 10) | (1U << 18)), /**< CTS */ - USART_IT_ERR = ((1U << 0) | (1U << 18)), /**< Error */ - USART_IT_ORE = (1U << 3), /**< Overrun error */ - USART_IT_NE = (1U << 2), /**< Noise error */ - USART_IT_FE = (1U << 0), /**< Frame error */ -} usart_it_t; - -/** - * @brief USART flags - */ -typedef enum -{ - USART_FLAG_CTS = (1U << 9), /**< CTS */ - USART_FLAG_TXE = (1U << 7), /**< Tx empty */ - USART_FLAG_TC = (1U << 6), /**< Tx complete */ - USART_FLAG_RXNE = (1U << 5), /**< Rx not empty */ - USART_FLAG_IDLE = (1U << 4), /**< Idle */ - USART_FLAG_ORE = (1U << 3), /**< Overrun error */ - USART_FLAG_NE = (1U << 2), /**< Noise error */ - USART_FLAG_FE = (1U << 1), /**< Frame error */ - USART_FLAG_PE = (1U << 0), /**< Parity error */ -} usart_flag_t; - -/** - * @} - */ - - -/** @defgroup USART_Public_Macros USART Public Macros - * @{ - */ - -/** @defgroup USART_Public_Macros_1 USART handle reset - * @{ - */ -#define USART_RESET_HANDLE_STATE(handle) ((handle)->state = USART_STATE_RESET) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_2 USART clear PE flag - * @{ - */ -#define USART_CLEAR_PEFLAG(handle) \ -do { \ - __IO uint32_t tmpreg; \ - tmpreg = (handle)->perh->STAT; \ - tmpreg = (handle)->perh->DATA; \ - UNUSED(tmpreg); \ -} while (0) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_3 USART clear FE flag - * @{ - */ -#define USART_CLEAR_FEFLAG(handle) USART_CLEAR_PEFLAG(handle) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_4 USART clear NE flag - * @{ - */ -#define USART_CLEAR_NEFLAG(handle) USART_CLEAR_PEFLAG(handle) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_5 USART clear ORE flag - * @{ - */ -#define USART_CLEAR_OREFLAG(handle) USART_CLEAR_PEFLAG(handle) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_6 USART clear IDLE flag - * @{ - */ -#define USART_CLEAR_IDLEFLAG(handle) USART_CLEAR_PEFLAG(handle) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_7 USART enable CTS flow control - * @{ - */ -#define USART_HWCONTROL_CTS_ENABLE(handle) \ - (SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_8 USART disable CTS flow control - * @{ - */ -#define USART_HWCONTROL_CTS_DISABLE(handle) \ - (CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_9 USART enable RTS flow control - * @{ - */ -#define USART_HWCONTROL_RTS_ENABLE(handle) \ - (SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_10 USART disable RTS flow control - * @{ - */ -#define USART_HWCONTROL_RTS_DISABLE(handle) \ - (CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_11 USART enable - * @{ - */ -#define USART_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_12 USART disable - * @{ - */ -#define USART_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Macros USART Private Macros - * @{ - */ - -#define IS_USART(x) (((x) == USART0) || ((x) == USART1)) -#define IS_USART_WORD_LENGTH(x) (((x) == USART_WORD_LENGTH_8B) || \ - ((x) == USART_WORD_LENGTH_9B)) -#define IS_USART_STOPBITS(x) (((x) == USART_STOP_BITS_1) || \ - ((x) == USART_STOP_BITS_0_5) || \ - ((x) == USART_STOP_BITS_2) || \ - ((x) == USART_STOP_BITS_1_5)) -#define IS_USART_PARITY(x) (((x) == USART_PARITY_NONE) || \ - ((x) == USART_PARITY_EVEN) || \ - ((x) == USART_PARITY_ODD)) -#define IS_USART_MODE(x) (((x) == USART_MODE_RX) || \ - ((x) == USART_MODE_TX) || \ - ((x) == USART_MODE_TX_RX)) -#define IS_USART_HARDWARE_FLOW_CONTROL(x)\ - (((x) == USART_HW_FLOW_CTL_NONE) || \ - ((x) == USART_HW_FLOW_CTL_RTS) || \ - ((x) == USART_HW_FLOW_CTL_CTS) || \ - ((x) == USART_HW_FLOW_CTL_RTS_CTS)) -#define IS_USART_CLOCK(x) (((x) == USART_CLOCK_DISABLE) || \ - ((x) == USART_CLOCK_ENABLE)) -#define IS_USART_CPOL(x) (((x) == USART_CPOL_LOW) || ((x) == USART_CPOL_HIGH)) -#define IS_USART_CPHA(x) (((x) == USART_CPHA_1EDGE) || ((x) == USART_CPHA_2EDGE)) -#define IS_USART_LASTBIT(x) (((x) == USART_LAST_BIT_DISABLE) || \ - ((x) == USART_LAST_BIT_ENABLE)) -#define IS_USART_DMAREQ(x) (((x) == USART_DMA_REQ_TX) || \ - ((x) == USART_DMA_REQ_RX)) -#define IS_USART_WAKEUP(x) (((x) == USART_WAKEUP_IDLE) || \ - ((x) == USART_WAKEUP_ADDR)) -#define IS_USART_IRDA_MODE(x) (((x) == USART_IrDA_MODE_NORMAL) || \ - ((x) == USART_IrDA_MODE_LOW_POWER)) -#define IS_USART_CONFIG_IT(x) (((x) == USART_IT_PE) || ((x) == USART_IT_TXE) || \ - ((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ - ((x) == USART_IT_IDLE) || \ - ((x) == USART_IT_CTS) || ((x) == USART_IT_ERR)) -#define IS_USART_GET_IT(x) (((x) == USART_IT_PE) || ((x) == USART_IT_TXE) || \ - ((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ - ((x) == USART_IT_IDLE) || \ - ((x) == USART_IT_CTS) || ((x) == USART_IT_ORE) || \ - ((x) == USART_IT_NE) || ((x) == USART_IT_FE) || \ - ((x) == USART_IT_ERR)) -#define IS_USART_CLEAR_IT(x) (((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ - ((x) == USART_IT_CTS)) - -#define IS_USART_FLAG(x) (((x) == USART_FLAG_PE) || ((x) == USART_FLAG_TXE) || \ - ((x) == USART_FLAG_TC) || ((x) == USART_FLAG_RXNE) || \ - ((x) == USART_FLAG_IDLE) || \ - ((x) == USART_FLAG_CTS) || ((x) == USART_FLAG_ORE) || \ - ((x) == USART_FLAG_NE) || ((x) == USART_FLAG_FE)) -#define IS_USART_CLEAR_FLAG(x) (((x) == USART_FLAG_CTS) || \ - ((x) == USART_FLAG_TC) || \ - ((x) == USART_FLAG_RXNE)) -#define IS_USART_BAUDRATE(x) (((x) > 0) && ((x) < 0x0044AA21)) -#define IS_USART_ADDRESS(x) ((x) <= 0xF) -#define IS_USART_DATA(x) ((x) <= 0x1FF) -#define DUMMY_DATA 0xFFFF -#define USART_STATE_TX_MASK (1 << 4) -#define USART_STATE_RX_MASK (1 << 5) - -/** - * @} - */ - -/** @addtogroup USART_Public_Functions - * @{ - */ - -/** @addtogroup USART_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -void usart_reset(usart_handle_t *hperh); -ald_status_t usart_init(usart_handle_t *hperh); -ald_status_t usart_half_duplex_init(usart_handle_t *hperh); -ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup); -ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init); -/** - * @} - */ - -/** @addtogroup USART_Public_Functions_Group2 - * @{ - */ - -/** @addtogroup USART_Public_Functions_Group2_1 - * @{ - */ -/* Asynchronization IO operation functions */ -ald_status_t usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -#endif -/** - * @} - */ - -/** @addtogroup USART_Public_Functions_Group2_2 - * @{ - */ -/* Synchronization IO operation functions */ -ald_status_t usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); -ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); -ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, - uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); -#endif -/** - * @} - */ - -/** @addtogroup USART_Public_Functions_Group2_3 - * @{ - */ -/* Utilities functions */ -#ifdef ALD_DMA -ald_status_t usart_dma_pause(usart_handle_t *hperh); -ald_status_t usart_dma_resume(usart_handle_t *hperh); -ald_status_t usart_dma_stop(usart_handle_t *hperh); -#endif -void usart_irq_handle(usart_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup USART_Public_Functions_Group3 - * @{ - */ -/* Peripheral control functions */ -ald_status_t usart_multi_processor_enter_mute_mode(usart_handle_t *hperh); -ald_status_t usart_multi_processor_exit_mute_mode(usart_handle_t *hperh); -ald_status_t usart_half_duplex_enable_send(usart_handle_t *hperh); -ald_status_t usart_half_duplex_enable_recv(usart_handle_t *hperh); -void usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state); -void usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state); -flag_status_t usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag); -void usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag); -it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it); -/** - * @} - */ - -/** @addtogroup USART_Public_Functions_Group4 - * @{ - */ - -/* Peripheral state and error functions */ -usart_state_t usart_get_state(usart_handle_t *hperh); -uint32_t usart_get_error(usart_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_USART_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html deleted file mode 100644 index a57c58046d66d43f9d1161783c33531f4309db61..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html +++ /dev/null @@ -1,14 +0,0 @@ - - - - -ReleaseNote -

ES32F065x MD Release Note

-

V1.00 2018-12-26

-
    -
  1. First release
    2. - -
-

 

- - \ No newline at end of file diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c deleted file mode 100644 index 4f311d1285362794aba74e534ce6534b002e2522..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c +++ /dev/null @@ -1,213 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_temp.c - * @brief TEMP module driver. - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_temp.h" -#include "ald_bkpc.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup TEMP TEMP - * @brief TEMP module driver - * @{ - */ -#ifdef ALD_TEMP - - -/** @defgroup TEMP_Private_Variables TEMP Private Variables - * @{ - */ -temp_cbk __temp_cbk; -/** - * @} - */ - -/** @defgroup TEMP_Public_Functions TEMP Public Functions - * @{ - */ - -/** @addtogroup TEMP_Public_Functions_Group1 Initialization functions - * @brief Initialization functions - * - * @verbatim - ============================================================================== - ##### Initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to initialize the TEMP: - (+) This parameters can be configured: - (++) Update Cycle - (++) Output Mode - (++) Perscaler - (+) Select TEMP source clock(default LOSC) - - @endverbatim - * @{ - */ - -/** - * @brief Initializes the TEMP according to the specified - * parameters in the temp_init_t. - * @param init: Pointer to a temp_init_t structure that contains - * the configuration information. - * @retval None - */ -void temp_init(temp_init_t *init) -{ - assert_param(IS_TEMP_UPDATE_CYCLE(init->cycle)); - assert_param(IS_TEMP_OUTPUT_MODE(init->mode)); - - TEMP_UNLOCK(); - MODIFY_REG(TEMP->CR, TEMP_CR_TSU_MSK, init->cycle << TEMP_CR_TSU_POSS); - MODIFY_REG(TEMP->CR, TEMP_CR_TOM_MSK, init->mode << TEMP_CR_TOM_POSS); - MODIFY_REG(TEMP->CR, TEMP_CR_CTN_MSK, init->ctn << TEMP_CR_CTN_POS); - MODIFY_REG(TEMP->PSR, TEMP_PSR_PRS_MSK, init->psc << TEMP_PSR_PRS_POSS); - TEMP_LOCK(); - - return; -} - -/** - * @brief Configure the TEMP source. - * @param sel: TEMP source type. - * @retval None - */ -void temp_source_selcet(temp_source_sel_t sel) -{ - assert_param(IS_TEMP_SOURCE_SEL(sel)); - - BKPC_UNLOCK(); - MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TEMPCS_MSK, sel << BKPC_PCCR_TEMPCS_POSS); - - if (sel == TEMP_SOURCE_LOSC) - { - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); - } - else if (sel == TEMP_SOURCE_LRC) - { - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); - } - else - { - ; /* do nothing */ - } - - BKPC_LOCK(); - return; -} -/** - * @} - */ - -/** @addtogroup TEMP_Public_Functions_Group2 Peripheral Control functions - * @brief Peripheral Control functions - * - * @verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) temp_get_value() API can get the current temperature. - (+) temp_get_value_by_it() API can get the current temperature by interrupt. - (+) temp_irq_handle() API can handle the interrupt request. - - @endverbatim - * @{ - */ - -/** - * @brief Get the current temperature - * @param temp: The value of current temperature. - * @retval ALD status: - * @arg @ref OK The value is valid - * @arg @ref ERROR The value is invalid - */ -ald_status_t temp_get_value(uint16_t *temp) -{ - TEMP_UNLOCK(); - SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); - SET_BIT(TEMP->CR, TEMP_CR_EN_MSK); - TEMP_LOCK(); - - while (!(READ_BIT(TEMP->IF, TEMP_IF_TEMP_MSK))); - - TEMP_UNLOCK(); - SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); - TEMP_LOCK(); - - if (READ_BIT(TEMP->DR, TEMP_DR_ERR_MSK)) - return ERROR; - - *temp = READ_BITS(TEMP->DR, TEMP_DR_DATA_MSK, TEMP_DR_DATA_POSS); - return OK; -} - -/** - * @brief Get the current temperature by interrupt - * @param cbk: The callback function - * @retval None - */ -void temp_get_value_by_it(temp_cbk cbk) -{ - __temp_cbk = cbk; - - TEMP_UNLOCK(); - SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); - SET_BIT(TEMP->IE, TEMP_IE_TEMP_MSK); - SET_BIT(TEMP->CR, TEMP_CR_EN_MSK); - TEMP_LOCK(); - - return; -} - -/** - * @brief This function handles TEMP interrupt request. - * @retval None - */ -void temp_irq_handle(void) -{ - TEMP_UNLOCK(); - SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); - TEMP_LOCK(); - - if (__temp_cbk == NULL) - return; - - if (READ_BIT(TEMP->DR, TEMP_DR_ERR_MSK)) - { - __temp_cbk(0, ERROR); - return; - } - - __temp_cbk(READ_BITS(TEMP->DR, TEMP_DR_DATA_MSK, TEMP_DR_DATA_POSS), OK); - - return; -} -/** - * @} - */ -/** - * @} - */ -#endif /* ALD_TEMP */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c deleted file mode 100644 index 5a682f91950a36724243b155b54b62647f334dd7..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c +++ /dev/null @@ -1,222 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_trng.c - * @brief TRNG module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_trng.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup TRNG TRNG - * @brief TRNG module driver - * @{ - */ -#ifdef ALD_TRNG - -/** @defgroup TRNG_Public_Functions TRNG Public Functions - * @{ - */ - -/** @addtogroup TRNG_Public_Functions_Group1 Initialization functions - * @brief Initialization functions - * - * @verbatim - ============================================================================== - ##### Initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to initialize the TRNG: - (+) This parameters can be configured: - (++) Word Width - (++) Seed Type - (++) Seed - (++) Start Time - (++) Adjust parameter - - @endverbatim - * @{ - */ - - -/** - * @brief Initializes the TRNG according to the specified - * parameters in the trng_init_t. - * @param init: Pointer to a trng_init_t structure that contains - * the configuration information. - * @retval None - */ -void trng_init(trng_init_t *init) -{ - assert_param(IS_TRNG_DATA_WIDTH(init->data_width)); - assert_param(IS_TRNG_SEED_TYPE(init->seed_type)); - assert_param(IS_TRNG_ADJC(init->adjc)); - - SET_BIT(TRNG->CR, TRNG_CR_TRNGSEL_MSK); - MODIFY_REG(TRNG->CR, TRNG_CR_DSEL_MSK, (init->data_width) << TRNG_CR_DSEL_POSS); - MODIFY_REG(TRNG->CR, TRNG_CR_SDSEL_MSK, (init->seed_type) << TRNG_CR_SDSEL_POSS); - MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (init->adjc) << TRNG_CR_ADJC_POSS); - - if (init->adjc == 0) - { - MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (0) << TRNG_CR_ADJC_POSS); - } - else - { - MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (1) << TRNG_CR_ADJC_POSS); - } - - WRITE_REG(TRNG->SEED, init->seed); - MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (init->t_start) << TRNG_CFGR_TSTART_POSS); - MODIFY_REG(TRNG->CR, TRNG_CR_POSTEN_MSK, (init->posten) << TRNG_CR_POSTEN_MSK); - - return; -} -/** - * @} - */ - -/** @addtogroup TRNG_Public_Functions_Group2 Peripheral Control functions - * @brief Peripheral Control functions - * - * @verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) trng_get_result() API can Get the result. - (+) trng_interrupt_config() API can be helpful to configure TRNG interrupt source. - (+) trng_get_it_status() API can get the status of interrupt source. - (+) trng_get_status() API can get the status of SR register. - (+) trng_get_flag_status() API can get the status of interrupt flag. - (+) trng_clear_flag_status() API can clear interrupt flag. - - @endverbatim - * @{ - */ - -/** - * @brief Get the result. - * @retval The resultl - */ -uint32_t trng_get_result(void) -{ - return (uint32_t)TRNG->DR; -} - -/** - * @brief Enable/disable the specified interrupts. - * @param it: Specifies the interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref trng_it_t. - * @param state: New state of the specified interrupts. - * This parameter can be: - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void trng_interrupt_config(trng_it_t it, type_func_t state) -{ - assert_param(IS_TRNG_IT(it)); - assert_param(IS_FUNC_STATE(state)); - - if (state) - SET_BIT(TRNG->IER, it); - else - CLEAR_BIT(TRNG->IER, it); - - return; -} - -/** - * @brief Get the status of SR register. - * @param status: Specifies the TRNG status type. - * This parameter can be one of the @ref trng_status_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -flag_status_t trng_get_status(trng_status_t status) -{ - assert_param(IS_TRNG_STATUS(status)); - - if (READ_BIT(TRNG->SR, status)) - return SET; - - return RESET; -} - -/** - * @brief Get the status of interrupt source. - * @param it: Specifies the interrupt source. - * This parameter can be one of the @ref trng_it_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -it_status_t trng_get_it_status(trng_it_t it) -{ - assert_param(IS_TRNG_IT(it)); - - if (READ_BIT(TRNG->IER, it)) - return SET; - - return RESET; -} - -/** - * @brief Get the status of interrupt flag. - * @param flag: Specifies the interrupt flag. - * This parameter can be one of the @ref trng_flag_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -flag_status_t trng_get_flag_status(trng_flag_t flag) -{ - assert_param(IS_TRNG_FLAG(flag)); - - if (READ_BIT(TRNG->IFR, flag)) - return SET; - - return RESET; -} - -/** - * @brief Clear the interrupt flag. - * @param flag: Specifies the interrupt flag. - * This parameter can be one of the @ref trng_flag_t. - * @retval None - */ -void trng_clear_flag_status(trng_flag_t flag) -{ - assert_param(IS_TRNG_FLAG(flag)); - WRITE_REG(TRNG->IFCR, flag); - - return; -} -/** - * @} - */ -/** - * @} - */ -#endif /* ALD_TRNG */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/es32f0654/.config b/bsp/essemi/es32f0654/.config similarity index 69% rename from bsp/es32f0654/.config rename to bsp/essemi/es32f0654/.config index 9853f9b6d0bff953a2dd6fb01c753cd28b09642e..56a52e8087befe972a89219b5be2a16eb17e682b 100644 --- a/bsp/es32f0654/.config +++ b/bsp/essemi/es32f0654/.config @@ -7,6 +7,7 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -63,7 +64,8 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" -CONFIG_RT_VER_NUM=0x40001 +CONFIG_RT_VER_NUM=0x40002 +# CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # @@ -108,6 +110,7 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 @@ -120,7 +123,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -128,10 +130,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -145,6 +147,7 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set # # Network @@ -156,14 +159,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -178,7 +181,6 @@ CONFIG_RT_USING_PIN=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set @@ -192,10 +194,13 @@ CONFIG_RT_USING_PIN=y # # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -213,10 +218,14 @@ CONFIG_RT_USING_PIN=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set # # IoT Cloud @@ -225,6 +234,21 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set # # security packages @@ -245,6 +269,9 @@ CONFIG_RT_USING_PIN=y # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set # # tools packages @@ -253,6 +280,12 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set # # system packages @@ -266,17 +299,42 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set # # peripheral libraries and drivers # -# CONFIG_PKG_USING_STM32F4_HAL is not set -# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_LCD_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set # # miscellaneous packages @@ -287,13 +345,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set - -# -# sample package -# +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -302,11 +362,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set CONFIG_SOC_ES32F0654LT=y # @@ -350,7 +414,6 @@ CONFIG_BSP_USING_UART2=y # HWtimer Drivers # # CONFIG_BSP_USING_HWTIMER0 is not set -# CONFIG_BSP_USING_HWTIMER1 is not set # CONFIG_BSP_USING_HWTIMER2 is not set # CONFIG_BSP_USING_HWTIMER3 is not set diff --git a/bsp/es32f0654/Kconfig b/bsp/essemi/es32f0654/Kconfig similarity index 94% rename from bsp/es32f0654/Kconfig rename to bsp/essemi/es32f0654/Kconfig index 188eb5bfc04c1de7403688f56f5ee0a36b5445de..2d3814dfe94d8504578e98a619ca6e5f48f425e1 100644 --- a/bsp/es32f0654/Kconfig +++ b/bsp/essemi/es32f0654/Kconfig @@ -8,7 +8,7 @@ config BSP_DIR config RTT_DIR string option env="RTT_ROOT" - default "../.." + default "../../.." config PKGS_DIR string diff --git a/bsp/es32f0654/README.md b/bsp/essemi/es32f0654/README.md similarity index 98% rename from bsp/es32f0654/README.md rename to bsp/essemi/es32f0654/README.md index 8111adeda57a5ff9d6cbf520a81ec2bd1b35d2c0..120cf0f4798abcf7a494d5deab8d37490e80f83c 100644 --- a/bsp/es32f0654/README.md +++ b/bsp/essemi/es32f0654/README.md @@ -40,6 +40,7 @@ ES-PDS-ES32F0654-V1.1 | UART | 支持 | UART0/1/2/3 | | SPI | 支持 | SPI0/1 | | I2C | 支持 | I2C0/1 | +| CAN | 支持 | CAN0 | | PWM | 支持 | PWM0/1/2/3 | | TIMER | 支持 | TIMER0/1/2/3 | | RTC | 支持 | RTC | diff --git a/bsp/es32f0654/SConscript b/bsp/essemi/es32f0654/SConscript similarity index 100% rename from bsp/es32f0654/SConscript rename to bsp/essemi/es32f0654/SConscript diff --git a/bsp/es32f0654/SConstruct b/bsp/essemi/es32f0654/SConstruct similarity index 94% rename from bsp/es32f0654/SConstruct rename to bsp/essemi/es32f0654/SConstruct index ac791958337caba15ec8cd8f32fe5f13b21c13d7..e75d75371b9d36fe3c5bd73b14db2d5f0fa5a95b 100644 --- a/bsp/es32f0654/SConstruct +++ b/bsp/essemi/es32f0654/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/es32f0654/applications/SConscript b/bsp/essemi/es32f0654/applications/SConscript similarity index 100% rename from bsp/es32f0654/applications/SConscript rename to bsp/essemi/es32f0654/applications/SConscript diff --git a/bsp/es32f0654/applications/main.c b/bsp/essemi/es32f0654/applications/main.c similarity index 100% rename from bsp/es32f0654/applications/main.c rename to bsp/essemi/es32f0654/applications/main.c diff --git a/bsp/es32f0654/drivers/Kconfig b/bsp/essemi/es32f0654/drivers/Kconfig similarity index 95% rename from bsp/es32f0654/drivers/Kconfig rename to bsp/essemi/es32f0654/drivers/Kconfig index f7a64ea678b920dc8f238bc5d1774b302bc3fdf6..888308497ae24c4c7a45bad8e58e01f353ba27de 100644 --- a/bsp/es32f0654/drivers/Kconfig +++ b/bsp/essemi/es32f0654/drivers/Kconfig @@ -56,6 +56,13 @@ menu "Hardware Drivers Config" default n endmenu + menu "CAN Drivers" + config BSP_USING_CAN + bool "Enable CAN BUS PA11/PA12(RX/TX)" + select RT_USING_CAN + default n + endmenu + menu "PWM Drivers" config BSP_USING_PWM0 bool "Using PWM0 PA08/PA09/PA10/PA11" diff --git a/bsp/es32f0654/drivers/SConscript b/bsp/essemi/es32f0654/drivers/SConscript similarity index 94% rename from bsp/es32f0654/drivers/SConscript rename to bsp/essemi/es32f0654/drivers/SConscript index a5ecf863ab5a3631ddbce451d1e52ca832d33429..ad5cf3c7836b27f4741ae3c66f922ad2be01f446 100644 --- a/bsp/es32f0654/drivers/SConscript +++ b/bsp/essemi/es32f0654/drivers/SConscript @@ -23,6 +23,10 @@ if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1'): if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'): src += ['drv_i2c.c'] +# add can driver code +if GetDepend('BSP_USING_CAN'): + src += ['drv_can.c'] + # add spi flash driver code if GetDepend('BSP_USING_SPI_FLASH'): src += ['drv_spiflash.c'] diff --git a/bsp/es32f0654/drivers/board.c b/bsp/essemi/es32f0654/drivers/board.c similarity index 89% rename from bsp/es32f0654/drivers/board.c rename to bsp/essemi/es32f0654/drivers/board.c index 46b3d472a03b1431856e02094d70e7fecd9d1cbb..94b259e48524b9cc3c1cb899711e92ed4ed64380 100644 --- a/bsp/es32f0654/drivers/board.c +++ b/bsp/essemi/es32f0654/drivers/board.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -43,10 +44,10 @@ void NVIC_Configuration(void) void SystemClock_Config(void) { /* hosc 12MHz, from hosc/3 pll to 48MHz */ - cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M); + ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M); /* MCLK 48MHz*/ - cmu_clock_config(CMU_CLOCK_PLL1, 48000000); + ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000); } /******************************************************************************* @@ -59,14 +60,14 @@ void SystemClock_Config(void) void SysTick_Configuration(void) { /* ticks = sysclk / RT_TICK_PER_SECOND */ - SysTick_Config(cmu_get_sys_clock() / RT_TICK_PER_SECOND); + SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND); } /** * This is the timer interrupt service routine. * */ -void systick_irq_cbk(void) +void SysTick_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -113,7 +114,7 @@ void rt_hw_us_delay(rt_uint32_t us) unsigned int start, now, delta, reload, us_tick; start = SysTick->VAL; reload = SysTick->LOAD; - us_tick = cmu_get_sys_clock() / 1000000UL; + us_tick = ald_cmu_get_sys_clock() / 1000000UL; do { now = SysTick->VAL; diff --git a/bsp/es32f0654/drivers/board.h b/bsp/essemi/es32f0654/drivers/board.h similarity index 100% rename from bsp/es32f0654/drivers/board.h rename to bsp/essemi/es32f0654/drivers/board.h diff --git a/bsp/es32f0654/drivers/drv_adc.c b/bsp/essemi/es32f0654/drivers/drv_adc.c similarity index 71% rename from bsp/es32f0654/drivers/drv_adc.c rename to bsp/essemi/es32f0654/drivers/drv_adc.c index 9a90e4d3944e48eb7d3737407848fab555709931..81a269d5c3eb5a9e9a874120bc395d10855cdce6 100644 --- a/bsp/es32f0654/drivers/drv_adc.c +++ b/bsp/essemi/es32f0654/drivers/drv_adc.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-04-03 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -58,67 +59,67 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel) { case 0: es32f0_channel = ADC_CHANNEL_0; - gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct); break; case 1: es32f0_channel = ADC_CHANNEL_1; - gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct); break; case 2: es32f0_channel = ADC_CHANNEL_2; - gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct); break; case 3: es32f0_channel = ADC_CHANNEL_3; - gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct); break; case 4: es32f0_channel = ADC_CHANNEL_4; - gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct); break; case 5: es32f0_channel = ADC_CHANNEL_5; - gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct); break; case 6: es32f0_channel = ADC_CHANNEL_6; - gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct); break; case 7: es32f0_channel = ADC_CHANNEL_7; - gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct); break; case 8: es32f0_channel = ADC_CHANNEL_8; - gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct); break; case 9: es32f0_channel = ADC_CHANNEL_9; - gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct); break; case 10: es32f0_channel = ADC_CHANNEL_10; - gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct); break; case 11: es32f0_channel = ADC_CHANNEL_11; - gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct); break; case 12: es32f0_channel = ADC_CHANNEL_12; - gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct); break; case 13: es32f0_channel = ADC_CHANNEL_13; - gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct); break; case 14: es32f0_channel = ADC_CHANNEL_14; - gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct); break; case 15: es32f0_channel = ADC_CHANNEL_15; - gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct); break; case 16: es32f0_channel = ADC_CHANNEL_16; @@ -139,21 +140,21 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel) static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) { adc_handle_t *_hadc = (adc_handle_t *)device->parent.user_data; - adc_channel_conf_t nm_config; + adc_nch_conf_t nm_config; RT_ASSERT(device != RT_NULL); RT_ASSERT(value != RT_NULL); /* config adc channel */ nm_config.channel = es32f0_adc_get_channel(channel); - nm_config.rank = ADC_NC_RANK_1; - nm_config.sampling_time = ADC_SAMPLETIME_4; - adc_normal_channel_config(_hadc, &nm_config); + nm_config.rank = ADC_NCH_RANK_1; + nm_config.samp_time = ADC_SAMPLETIME_4; + ald_adc_normal_channel_config(_hadc, &nm_config); - adc_normal_start(_hadc); + ald_adc_normal_start(_hadc); - if (adc_normal_poll_for_conversion(_hadc, 5000) == OK) - *value = adc_normal_get_value(_hadc); + if (ald_adc_normal_poll_for_conversion(_hadc, 5000) == OK) + *value = ald_adc_normal_get_value(_hadc); return RT_EOK; } @@ -172,17 +173,16 @@ int rt_hw_adc_init(void) /* adc function initialization */ _h_adc0.perh = ADC0; _h_adc0.init.data_align = ADC_DATAALIGN_RIGHT; - _h_adc0.init.scan_mode = ADC_SCAN_DISABLE; + _h_adc0.init.scan_mode = DISABLE; _h_adc0.init.cont_mode = DISABLE; - _h_adc0.init.conv_nbr = ADC_NM_NBR_1; - _h_adc0.init.disc_mode = DISABLE; + _h_adc0.init.disc_mode = ADC_ALL_DISABLE; _h_adc0.init.disc_nbr = ADC_DISC_NBR_1; _h_adc0.init.conv_res = ADC_CONV_RES_10; _h_adc0.init.clk_div = ADC_CKDIV_128; - _h_adc0.init.nche_mode = ADC_NCHESEL_MODE_ALL; + _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL; _h_adc0.init.neg_ref = ADC_NEG_REF_VSS; _h_adc0.init.pos_ref = ADC_POS_REF_VDD; - adc_init(&_h_adc0); + ald_adc_init(&_h_adc0); rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0); diff --git a/bsp/es32f0654/drivers/drv_adc.h b/bsp/essemi/es32f0654/drivers/drv_adc.h similarity index 100% rename from bsp/es32f0654/drivers/drv_adc.h rename to bsp/essemi/es32f0654/drivers/drv_adc.h diff --git a/bsp/essemi/es32f0654/drivers/drv_can.c b/bsp/essemi/es32f0654/drivers/drv_can.c new file mode 100644 index 0000000000000000000000000000000000000000..0524fdaf07aa909a1d7c9b9e5f2d5ee6f4168cdd --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/drv_can.c @@ -0,0 +1,605 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-11-09 wangyq the first version + */ + +#include "drv_can.h" + +#ifdef BSP_USING_CAN + +static struct es32f0_can can; + +/* attention !!! baud calculation example: Pclk / ((sjw + seg1 + seg2) * psc) 48 / ((1 + 3 + 2) * 8) = 1MHz */ +static const struct es32f0_baud_rate_tab can_baud_rate_tab[] = +{ + {CAN1MBaud, 8}, + {CAN800kBaud, 10}, + {CAN500kBaud, 16}, + {CAN250kBaud, 32}, + {CAN125kBaud, 64}, + {CAN100kBaud, 80}, + {CAN50kBaud, 160}, + {CAN20kBaud, 400}, + {CAN10kBaud, 800} +}; + +static rt_uint32_t get_can_baud_index(rt_uint32_t baud) +{ + rt_uint32_t len, index; + + len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); + for (index = 0; index < len; index++) + { + if (can_baud_rate_tab[index].baud_rate == baud) + return index; + } + + return 0; /* default baud is CAN1MBaud */ +} + +static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configure *cfg) +{ + struct es32f0_can *drv_can; + rt_uint32_t baud_index; + + RT_ASSERT(can_device); + RT_ASSERT(cfg); + drv_can = (struct es32f0_can *)can_device->parent.user_data; + RT_ASSERT(drv_can); + + drv_can->CanHandle.perh = CAN0; + drv_can->CanHandle.init.ttcm = DISABLE; + drv_can->CanHandle.init.abom = ENABLE; + drv_can->CanHandle.init.awk = DISABLE; + drv_can->CanHandle.init.artx = DISABLE; + drv_can->CanHandle.init.rfom = DISABLE; + drv_can->CanHandle.init.txmp = ENABLE; + + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: + drv_can->CanHandle.init.mode = CAN_MODE_NORMAL; + break; + case RT_CAN_MODE_LISEN: + drv_can->CanHandle.init.mode = CAN_MODE_SILENT; + break; + case RT_CAN_MODE_LOOPBACK: + drv_can->CanHandle.init.mode = CAN_MODE_LOOPBACK; + break; + case RT_CAN_MODE_LOOPBACKANLISEN: + drv_can->CanHandle.init.mode = CAN_MODE_SILENT_LOOPBACK; + break; + } + + baud_index = get_can_baud_index(cfg->baud_rate); + drv_can->CanHandle.init.sjw = CAN_SJW_1; + drv_can->CanHandle.init.seg1 = CAN_SEG1_3; + drv_can->CanHandle.init.seg2 = CAN_SEG2_2; + drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data; + /* init can */ + if (ald_can_init(&drv_can->CanHandle) != OK) + { + return -RT_ERROR; + } + /* default filter config */ + ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); + + return RT_EOK; +} + +static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *arg) +{ + rt_uint32_t argval; + struct es32f0_can *drv_can; + struct rt_can_filter_config *filter_cfg; + + RT_ASSERT(can_device != RT_NULL); + drv_can = (struct es32f0_can *)can_device->parent.user_data; + RT_ASSERT(drv_can != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX) + { + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | + CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), DISABLE); + } + else if (argval == RT_DEVICE_FLAG_INT_TX) + { + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, DISABLE); + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | + CAN_IT_PRERR | CAN_IT_ERR), DISABLE); + } + break; + case RT_DEVICE_CTRL_SET_INT: + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX) + { + NVIC_SetPriority(CAN0_IRQn, 1); + NVIC_EnableIRQ(CAN0_IRQn); + + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FP1), ENABLE); + } + else if (argval == RT_DEVICE_FLAG_INT_TX) + { + NVIC_SetPriority(CAN0_IRQn, 1); + NVIC_EnableIRQ(CAN0_IRQn); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, ENABLE); + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + NVIC_SetPriority(CAN0_IRQn, 1); + NVIC_EnableIRQ(CAN0_IRQn); + + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | + CAN_IT_PRERR | CAN_IT_ERR), ENABLE); + } + break; + case RT_CAN_CMD_SET_FILTER: + if (RT_NULL == arg) + { + /* default filter config */ + ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); + } + else + { + filter_cfg = (struct rt_can_filter_config *)arg; + /* get default filter */ + for (int i = 0; i < filter_cfg->count; i++) + { + drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + drv_can->FilterConfig.id_high = (filter_cfg->items[i].id >> 13) & 0xFFFF; + drv_can->FilterConfig.id_low = ((filter_cfg->items[i].id << 3) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)) & 0xFFFF; + drv_can->FilterConfig.mask_id_high = (filter_cfg->items[i].mask >> 16) & 0xFFFF; + drv_can->FilterConfig.mask_id_low = filter_cfg->items[i].mask & 0xFFFF; + drv_can->FilterConfig.mode = (can_filter_mode_t)filter_cfg->items[i].mode; + /* Filter conf */ + ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); + } + } + break; + case RT_CAN_CMD_SET_MODE: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_NORMAL && + argval != RT_CAN_MODE_LISEN && + argval != RT_CAN_MODE_LOOPBACK && + argval != RT_CAN_MODE_LOOPBACKANLISEN) + { + return -RT_ERROR; + } + if (argval != drv_can->device.config.mode) + { + drv_can->device.config.mode = argval; + return _can_config(&drv_can->device, &drv_can->device.config); + } + break; + case RT_CAN_CMD_SET_BAUD: + argval = (rt_uint32_t) arg; + if (argval != CAN1MBaud && + argval != CAN800kBaud && + argval != CAN500kBaud && + argval != CAN250kBaud && + argval != CAN125kBaud && + argval != CAN100kBaud && + argval != CAN50kBaud && + argval != CAN20kBaud && + argval != CAN10kBaud) + { + return -RT_ERROR; + } + if (argval != drv_can->device.config.baud_rate) + { + drv_can->device.config.baud_rate = argval; + return _can_config(&drv_can->device, &drv_can->device.config); + } + break; + case RT_CAN_CMD_SET_PRIV: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_PRIV && + argval != RT_CAN_MODE_NOPRIV) + { + return -RT_ERROR; + } + if (argval != drv_can->device.config.privmode) + { + drv_can->device.config.privmode = argval; + return _can_config(&drv_can->device, &drv_can->device.config); + } + break; + case RT_CAN_CMD_GET_STATUS: + { + rt_uint32_t errtype; + errtype = drv_can->CanHandle.perh->ERRSTAT; + drv_can->device.status.rcverrcnt = errtype >> 24; + drv_can->device.status.snderrcnt = (errtype >> 16 & 0xFF); + drv_can->device.status.lasterrtype = errtype & 0x70; + drv_can->device.status.errcode = errtype & 0x07; + + rt_memcpy(arg, &drv_can->device.status, sizeof(drv_can->device.status)); + } + break; + } + + return RT_EOK; +} + +static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num) +{ + can_handle_t *h_can; + h_can = &((struct es32f0_can *) can->parent.user_data)->CanHandle; + struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; + can_tx_msg_t txheader = {0}; + can_state_t state = h_can->state; + + /* Check the parameters */ + RT_ASSERT(IS_CAN_DATA_LEN(pmsg->len)); + + if ((state == CAN_STATE_READY) || + (state == CAN_STATE_BUSY_RX)) + { + /*check select mailbox is empty */ + switch (1 << box_num) + { + case CAN_TX_MAILBOX_0: + if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM0) != SET) + { + /* Change CAN state */ + h_can->state = CAN_STATE_ERROR; + /* Return function status */ + return -RT_ERROR; + } + break; + case CAN_TX_MAILBOX_1: + if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM1) != SET) + { + /* Change CAN state */ + h_can->state = CAN_STATE_ERROR; + /* Return function status */ + return -RT_ERROR; + } + break; + case CAN_TX_MAILBOX_2: + if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM2) != SET) + { + /* Change CAN state */ + h_can->state = CAN_STATE_ERROR; + /* Return function status */ + return -RT_ERROR; + } + break; + default: + RT_ASSERT(0); + break; + } + + if (RT_CAN_STDID == pmsg->ide) + { + txheader.type = CAN_ID_STD; + RT_ASSERT(IS_CAN_STDID(pmsg->id)); + txheader.std = pmsg->id; + } + else + { + txheader.type = CAN_ID_EXT; + RT_ASSERT(IS_CAN_EXTID(pmsg->id)); + txheader.ext = pmsg->id; + } + + if (RT_CAN_DTR == pmsg->rtr) + { + txheader.rtr = CAN_RTR_DATA; + } + else + { + txheader.rtr = CAN_RTR_REMOTE; + } + /* clear TIR */ + h_can->perh->TxMailBox[box_num].TXID &= CAN_TXID0_TXMREQ_MSK; + /* Set up the Id */ + if (RT_CAN_STDID == pmsg->ide) + { + h_can->perh->TxMailBox[box_num].TXID |= (txheader.std << CAN_TXID0_STDID_POSS) | txheader.rtr; + } + else + { + h_can->perh->TxMailBox[box_num].TXID |= (txheader.ext << CAN_TXID0_EXID_POSS) | txheader.type | txheader.rtr; + } + /* Set up the DLC */ + h_can->perh->TxMailBox[box_num].TXFCON = pmsg->len & 0x0FU; + /* Set up the data field */ + WRITE_REG(h_can->perh->TxMailBox[box_num].TXDH, + ((uint32_t)pmsg->data[7] << CAN_TXDH0_BYTE7_POSS) | + ((uint32_t)pmsg->data[6] << CAN_TXDH0_BYTE6_POSS) | + ((uint32_t)pmsg->data[5] << CAN_TXDH0_BYTE5_POSS) | + ((uint32_t)pmsg->data[4] << CAN_TXDH0_BYTE4_POSS)); + WRITE_REG(h_can->perh->TxMailBox[box_num].TXDL, + ((uint32_t)pmsg->data[3] << CAN_TXDL0_BYTE3_POSS) | + ((uint32_t)pmsg->data[2] << CAN_TXDL0_BYTE2_POSS) | + ((uint32_t)pmsg->data[1] << CAN_TXDL0_BYTE1_POSS) | + ((uint32_t)pmsg->data[0] << CAN_TXDL0_BYTE0_POSS)); + /* Request transmission */ + SET_BIT(h_can->perh->TxMailBox[box_num].TXID, CAN_TXID0_TXMREQ_MSK); + + return RT_EOK; + } + else + { + /* Update error code */ + h_can->err |= 0x00040000U; + + return -RT_ERROR; + } +} + +static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) +{ + can_handle_t *h_can; + struct rt_can_msg *pmsg; + can_rx_msg_t rxheader = {0}; + + RT_ASSERT(can); + + h_can = &((struct es32f0_can *)can->parent.user_data)->CanHandle; + pmsg = (struct rt_can_msg *) buf; + + /* get data */ + if (ald_can_recv(h_can, (can_rx_fifo_t)fifo, &rxheader, 0xFFFF) != OK) + return -RT_ERROR; + pmsg->data[0] = rxheader.data[0]; + pmsg->data[1] = rxheader.data[1]; + pmsg->data[2] = rxheader.data[2]; + pmsg->data[3] = rxheader.data[3]; + pmsg->data[4] = rxheader.data[4]; + pmsg->data[5] = rxheader.data[5]; + pmsg->data[6] = rxheader.data[6]; + pmsg->data[7] = rxheader.data[7]; + + /* get id */ + if (CAN_ID_STD == rxheader.type) + { + pmsg->ide = RT_CAN_STDID; + pmsg->id = rxheader.std; + } + else + { + pmsg->ide = RT_CAN_EXTID; + pmsg->id = rxheader.ext; + } + /* get type */ + if (CAN_RTR_DATA == rxheader.rtr) + { + pmsg->rtr = RT_CAN_DTR; + } + else + { + pmsg->rtr = RT_CAN_RTR; + } + /* get len */ + pmsg->len = rxheader.len; + /* get hdr */ + pmsg->hdr = (rxheader.fmi + 1) >> 1; + + return RT_EOK; +} + + +static const struct rt_can_ops _can_ops = +{ + _can_config, + _can_control, + _can_sendmsg, + _can_recvmsg, +}; + +static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) +{ + can_handle_t *h_can; + RT_ASSERT(can); + h_can = &((struct es32f0_can *) can->parent.user_data)->CanHandle; + + switch (fifo) + { + case CAN_RX_FIFO0: + /* Check Overrun flag for FIFO0 */ + if (ald_can_get_flag_status(h_can, CAN_FLAG_FOV0) && ald_can_get_it_status(h_can, CAN_IT_FOV0)) + { + /* Clear FIFO0 Overrun Flag */ + ald_can_clear_flag_status(h_can, CAN_FLAG_FOV0); + rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8); + } + /* RX interrupt */ + else + { + /* save to user list */ + rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + + /* Clear FIFO0 rx Flag */ + SET_BIT(h_can->perh->RXF0, CAN_RXF0_FREE_MSK); + } + break; + case CAN_RX_FIFO1: + /* Check Overrun flag for FIFO1 */ + if (ald_can_get_flag_status(h_can, CAN_FLAG_FOV1) && ald_can_get_it_status(h_can, CAN_IT_FOV1)) + { + /* Clear FIFO1 Overrun Flag */ + ald_can_clear_flag_status(h_can, CAN_FLAG_FOV1); + rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8); + } + /* RX interrupt */ + else + { + /* save to user list */ + rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + + /* Clear FIFO0 rx Flag */ + SET_BIT(h_can->perh->RXF1, CAN_RXF1_FREE_MSK); + } + break; + } +} + +/** + * @brief This function handles CAN interrupts. + */ +void CAN0_Handler(void) +{ + rt_interrupt_enter(); + + rt_uint32_t errtype; + can_handle_t *h_can; + h_can = &can.CanHandle; + + /* RX FIFO0 interrupt */ + if ((ald_can_get_it_status(h_can, CAN_IT_FP0)) && (CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO0) != 0)) + { + _can_rx_isr(&can.device, CAN_RX_FIFO0); + } + + /* RX FIFO1 interrupt */ + if ((ald_can_get_it_status(h_can, CAN_IT_FP1)) && (CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO1) != 0)) + { + _can_rx_isr(&can.device, CAN_RX_FIFO1); + } + + /* TX interrupt. transmit fifo0/1/2 is empty can trigger this interrupt */ + if (ald_can_get_flag_status(h_can, CAN_FLAG_M0REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM)) + { + if (ald_can_get_flag_status(h_can, CAN_FLAG_M0TXC)) + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 0 << 8); + } + else + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 0 << 8); + } + /* Clear transmission status flag M0REQC */ + ald_can_clear_flag_status(h_can, CAN_FLAG_M0REQC); + } + else if (ald_can_get_flag_status(h_can, CAN_FLAG_M1REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM)) + { + if (ald_can_get_flag_status(h_can, CAN_FLAG_M1TXC)) + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 1 << 8); + } + else + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 1 << 8); + } + ald_can_clear_flag_status(h_can, CAN_FLAG_M1REQC); + } + else if (ald_can_get_flag_status(h_can, CAN_FLAG_M2REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM)) + { + if (ald_can_get_flag_status(h_can, CAN_FLAG_M2REQC)) + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 2 << 8); + } + else + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 2 << 8); + } + ald_can_clear_flag_status(h_can, CAN_FLAG_M2REQC); + } + + /* CAN error interrupt */ + if (ald_can_get_flag_status(h_can, CAN_FLAG_ERR) && ald_can_get_it_status(h_can, CAN_IT_ERR)) + { + errtype = h_can->perh->ERRSTAT; + switch ((errtype & 0x70) >> 4) + { + case RT_CAN_BUS_BIT_PAD_ERR: + can.device.status.bitpaderrcnt++; + break; + case RT_CAN_BUS_FORMAT_ERR: + can.device.status.formaterrcnt++; + break; + case RT_CAN_BUS_ACK_ERR:/* attention !!! test ack err's unit is transmit unit */ + can.device.status.ackerrcnt++; + if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC)) + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 0 << 8); + else if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC)) + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 1 << 8); + else if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC)) + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 2 << 8); + break; + case RT_CAN_BUS_IMPLICIT_BIT_ERR: + case RT_CAN_BUS_EXPLICIT_BIT_ERR: + can.device.status.biterrcnt++; + break; + case RT_CAN_BUS_CRC_ERR: + can.device.status.crcerrcnt++; + break; + } + + can.device.status.lasterrtype = errtype & 0x70; + can.device.status.rcverrcnt = errtype >> 24; + can.device.status.snderrcnt = (errtype >> 16 & 0xFF); + can.device.status.errcode = errtype & 0x07; + h_can->perh->IFC |= CAN_IFC_ERRIFC_MSK; + } + + rt_interrupt_leave(); +} + +int rt_hw_can_init(void) +{ + gpio_init_t h_gpio; + struct can_configure config = CANDEFAULTCONFIG; + + config.privmode = RT_CAN_MODE_NOPRIV; + config.ticks = 50; +#ifdef RT_CAN_USING_HDR + config.maxhdr = 14; +#endif + + /* Initialize can common pin */ + h_gpio.odos = GPIO_PUSH_PULL; + h_gpio.pupd = GPIO_PUSH_UP; + h_gpio.odrv = GPIO_OUT_DRIVE_NORMAL; + h_gpio.flt = GPIO_FILTER_DISABLE; + h_gpio.type = GPIO_TYPE_TTL; + h_gpio.func = GPIO_FUNC_4; + + /* Initialize can rx pin */ + h_gpio.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOA, GPIO_PIN_11, &h_gpio); + + /* Initialize can tx pin */ + h_gpio.mode = GPIO_MODE_OUTPUT; + ald_gpio_init(GPIOA, GPIO_PIN_12, &h_gpio); + + /* config default filter */ + can_filter_t filter = {0}; + filter.id_high = 0x0000; + filter.id_low = 0x0000; + filter.mask_id_high = 0x0000; + filter.mask_id_low = 0x0000; + filter.fifo = CAN_FILTER_FIFO0; + filter.number = 0; + filter.mode = CAN_FILTER_MODE_MASK; + filter.scale = CAN_FILTER_SCALE_32; + filter.active = ENABLE; + filter.bank_number = 14; + + can.FilterConfig = filter; + can.device.config = config; + /* register CAN1 device */ + rt_hw_can_register(&can.device, "can", &_can_ops, &can); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_can_init); + +#endif /* BSP_USING_CAN */ diff --git a/bsp/essemi/es32f0654/drivers/drv_can.h b/bsp/essemi/es32f0654/drivers/drv_can.h new file mode 100644 index 0000000000000000000000000000000000000000..798a3a8653bced33147f4c71b14d3575d9cacffe --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/drv_can.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-11-09 wangyq the first version + */ + +#ifndef DRV_CAN_H__ +#define DRV_CAN_H__ + +#include +#include +#include + +#include +#include + +struct es32f0_baud_rate_tab +{ + rt_uint32_t baud_rate; + rt_uint32_t config_data; +}; + +/* es32f0 can device */ +struct es32f0_can +{ + can_handle_t CanHandle; + can_filter_t FilterConfig; + struct rt_can_device device; /* inherit from can device */ +}; + +int rt_hw_can_init(void); + +#endif /*DRV_CAN_H__ */ diff --git a/bsp/es32f0654/drivers/drv_gpio.c b/bsp/essemi/es32f0654/drivers/drv_gpio.c similarity index 93% rename from bsp/es32f0654/drivers/drv_gpio.c rename to bsp/essemi/es32f0654/drivers/drv_gpio.c index 4374772ede4538c6468d4bb87ba55601b53e520e..680860757f750ece7fd56ea74fe6f32b5d6580ea 100644 --- a/bsp/es32f0654/drivers/drv_gpio.c +++ b/bsp/essemi/es32f0654/drivers/drv_gpio.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -167,7 +168,7 @@ void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { return; } - gpio_write_pin(index->gpio, index->pin, value); + ald_gpio_write_pin(index->gpio, index->pin, value); } int es32f0_pin_read(rt_device_t dev, rt_base_t pin) @@ -180,7 +181,7 @@ int es32f0_pin_read(rt_device_t dev, rt_base_t pin) { return value; } - value = gpio_read_pin(index->gpio, index->pin); + value = ald_gpio_read_pin(index->gpio, index->pin); return value; } @@ -233,7 +234,7 @@ void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) gpio_initstruct.pupd = GPIO_FLOATING; gpio_initstruct.odos = GPIO_OPEN_DRAIN; } - gpio_init(index->gpio, index->pin, &gpio_initstruct); + ald_gpio_init(index->gpio, index->pin, &gpio_initstruct); } rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) @@ -360,7 +361,7 @@ rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin, return RT_ENOSYS; } irqmap = &pin_irq_map[irqindex]; - gpio_exti_init(index->gpio, index->pin, &exti_initstruct); + ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct); /* Configure GPIO_InitStructure */ gpio_initstruct.mode = GPIO_MODE_INPUT; gpio_initstruct.func = GPIO_FUNC_1; @@ -368,18 +369,18 @@ rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin, { case PIN_IRQ_MODE_RISING: gpio_initstruct.pupd = GPIO_PUSH_DOWN; - gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE); + ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE); break; case PIN_IRQ_MODE_FALLING: gpio_initstruct.pupd = GPIO_PUSH_UP; - gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE); + ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE); break; case PIN_IRQ_MODE_RISING_FALLING: gpio_initstruct.pupd = GPIO_FLOATING; - gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE); + ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE); break; } - gpio_init(index->gpio, index->pin, &gpio_initstruct); + ald_gpio_init(index->gpio, index->pin, &gpio_initstruct); NVIC_EnableIRQ(irqmap->irqno); rt_hw_interrupt_enable(level); } @@ -412,7 +413,7 @@ const static struct rt_pin_ops _es32f0_pin_ops = int rt_hw_pin_init(void) { int result; - cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); + ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL); return result; } @@ -439,9 +440,9 @@ rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) void GPIO_EXTI_Callback(uint16_t GPIO_Pin) { - if (gpio_exti_get_flag_status(GPIO_Pin) != RESET) + if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET) { - gpio_exti_clear_flag_status(GPIO_Pin); + ald_gpio_exti_clear_flag_status(GPIO_Pin); pin_irq_hdr(GPIO_Pin); } } diff --git a/bsp/es32f0654/drivers/drv_gpio.h b/bsp/essemi/es32f0654/drivers/drv_gpio.h similarity index 100% rename from bsp/es32f0654/drivers/drv_gpio.h rename to bsp/essemi/es32f0654/drivers/drv_gpio.h diff --git a/bsp/es32f0654/drivers/drv_hwtimer.c b/bsp/essemi/es32f0654/drivers/drv_hwtimer.c similarity index 77% rename from bsp/es32f0654/drivers/drv_hwtimer.c rename to bsp/essemi/es32f0654/drivers/drv_hwtimer.c index 6eceab627be96ae7e9b5f2d67c9473f8c2965768..4d7614a3234b91746e66d907dedeee0e3e390ff4 100644 --- a/bsp/es32f0654/drivers/drv_hwtimer.c +++ b/bsp/essemi/es32f0654/drivers/drv_hwtimer.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-3-19 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -30,12 +31,12 @@ static struct es32f0_hwtimer_dev hwtimer0; void BS16T0_Handler(void) { - timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE); + ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE); rt_device_hwtimer_isr(&hwtimer0.parent); if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) { - timer_base_stop(hwtimer0.hwtimer_periph); + ald_timer_base_stop(hwtimer0.hwtimer_periph); } } #endif @@ -46,15 +47,15 @@ static struct es32f0_hwtimer_dev hwtimer1; void BS16T1_UART2_Handler(void) { /* if BS16T1 it */ - if (timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) && - timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE)) + if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) && + ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE)) { - timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE); + ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE); rt_device_hwtimer_isr(&hwtimer1.parent); if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) { - timer_base_stop(hwtimer1.hwtimer_periph); + ald_timer_base_stop(hwtimer1.hwtimer_periph); } } } @@ -66,15 +67,15 @@ static struct es32f0_hwtimer_dev hwtimer2; void BS16T2_UART3_Handler(void) { /* if BS16T2 it */ - if (timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) && - timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE)) + if (ald_timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) && + ald_timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE)) { - timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE); + ald_timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE); rt_device_hwtimer_isr(&hwtimer2.parent); if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode) { - timer_base_stop(hwtimer2.hwtimer_periph); + ald_timer_base_stop(hwtimer2.hwtimer_periph); } } } @@ -86,15 +87,15 @@ static struct es32f0_hwtimer_dev hwtimer3; void BS16T3_DAC0_Handler(void) { /* if BS16T3 it */ - if (timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) && - timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE)) + if (ald_timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) && + ald_timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE)) { - timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE); + ald_timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE); rt_device_hwtimer_isr(&hwtimer3.parent); if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode) { - timer_base_stop(hwtimer3.hwtimer_periph); + ald_timer_base_stop(hwtimer3.hwtimer_periph); } } } @@ -116,13 +117,13 @@ static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) if (1 == state) { - timer_base_init(hwtimer->hwtimer_periph); - timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); + ald_timer_base_init(hwtimer->hwtimer_periph); + ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); NVIC_EnableIRQ(hwtimer->IRQn); } - hwtimer->parent.freq = cmu_get_pclk1_clock(); - es32f0_hwtimer_info.maxfreq = cmu_get_pclk1_clock(); - es32f0_hwtimer_info.minfreq = cmu_get_pclk1_clock(); + hwtimer->parent.freq = ald_cmu_get_pclk1_clock(); + es32f0_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock(); + es32f0_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock(); } static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, @@ -134,7 +135,7 @@ static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, RT_ASSERT(hwtimer != RT_NULL); WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt); - timer_base_start(hwtimer->hwtimer_periph); + ald_timer_base_start(hwtimer->hwtimer_periph); return RT_EOK; } @@ -145,7 +146,7 @@ static void es32f0_hwtimer_stop(rt_hwtimer_t *timer) RT_ASSERT(hwtimer != RT_NULL); - timer_base_stop(hwtimer->hwtimer_periph); + ald_timer_base_stop(hwtimer->hwtimer_periph); } static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer) @@ -174,14 +175,14 @@ static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer, { case HWTIMER_CTRL_FREQ_SET: freq = *(rt_uint32_t *)args; - if (freq != cmu_get_pclk1_clock()) + if (freq != ald_cmu_get_pclk1_clock()) { ret = -RT_ERROR; } break; case HWTIMER_CTRL_STOP: - timer_base_stop(hwtimer->hwtimer_periph); + ald_timer_base_stop(hwtimer->hwtimer_periph); break; default: diff --git a/bsp/es32f0654/drivers/drv_hwtimer.h b/bsp/essemi/es32f0654/drivers/drv_hwtimer.h similarity index 100% rename from bsp/es32f0654/drivers/drv_hwtimer.h rename to bsp/essemi/es32f0654/drivers/drv_hwtimer.h diff --git a/bsp/es32f0654/drivers/drv_i2c.c b/bsp/essemi/es32f0654/drivers/drv_i2c.c similarity index 86% rename from bsp/es32f0654/drivers/drv_i2c.c rename to bsp/essemi/es32f0654/drivers/drv_i2c.c index ce726ae7ad43c6642f84b6471f7e3ccd28045f3e..c40902047f6a0c2afa81c8b50f2702c96209b9fb 100644 --- a/bsp/es32f0654/drivers/drv_i2c.c +++ b/bsp/essemi/es32f0654/drivers/drv_i2c.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-01-24 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -45,10 +46,10 @@ static void _i2c_init(void) _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE; _h_i2c0.init.no_stretch = I2C_NOSTRETCH_ENABLE; - i2c_reset(&_h_i2c0); - i2c_init(&_h_i2c0); + ald_i2c_reset(&_h_i2c0); + ald_i2c_init(&_h_i2c0); /* I2C0_SCL->PB8, I2C0_SDA->PB9 */ - gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct); #endif #ifdef BSP_USING_I2C1 @@ -61,10 +62,10 @@ static void _i2c_init(void) _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE; _h_i2c1.init.no_stretch = I2C_NOSTRETCH_ENABLE; - i2c_reset(&_h_i2c1); - i2c_init(&_h_i2c1); + ald_i2c_reset(&_h_i2c1); + ald_i2c_init(&_h_i2c1); /* I2C1_SCL->PB10, I2C1_SDA->PB11 */ - gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct); #endif } @@ -81,7 +82,7 @@ static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus, msg = &msgs[i]; if (msg->flags & RT_I2C_RD) { - if (i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) + if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) { i2c_dbg("i2c bus write failed,i2c bus stop!\n"); goto out; @@ -89,7 +90,7 @@ static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus, } else { - if (i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) + if (ald_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) { i2c_dbg("i2c bus write failed,i2c bus stop!\n"); goto out; diff --git a/bsp/es32f0654/drivers/drv_i2c.h b/bsp/essemi/es32f0654/drivers/drv_i2c.h similarity index 100% rename from bsp/es32f0654/drivers/drv_i2c.h rename to bsp/essemi/es32f0654/drivers/drv_i2c.h diff --git a/bsp/essemi/es32f0654/drivers/drv_pm.c b/bsp/essemi/es32f0654/drivers/drv_pm.c new file mode 100644 index 0000000000000000000000000000000000000000..821d3bc843f138cbbeb73715912e17d5972e6de0 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/drv_pm.c @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-08 wangyq the first version + * 2019-11-01 wangyq adapt to the new power management interface + */ + +#include +#include +#include +#include + +#ifdef RT_USING_PM + +static void uart_console_reconfig(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); +} + +/** + * This function will put ES32F033x into sleep mode. + * + * @param pm pointer to power manage structure + */ +static void sleep(struct rt_pm *pm, uint8_t mode) +{ + switch (mode) + { + case PM_SLEEP_MODE_NONE: + break; + + case PM_SLEEP_MODE_IDLE: + //__WFI(); + break; + + case PM_SLEEP_MODE_LIGHT: + /* Enter SLEEP Mode, Main regulator is ON */ + ald_pmu_stop1_enter(); + break; + + case PM_SLEEP_MODE_DEEP: + /* Enter STOP 2 mode */ + ald_pmu_stop2_enter(); + break; + + case PM_SLEEP_MODE_STANDBY: + /* Enter STANDBY mode */ + ald_pmu_stop2_enter(); + break; + + case PM_SLEEP_MODE_SHUTDOWN: + /* Enter SHUTDOWNN mode */ + ald_pmu_stop2_enter(); + break; + + default: + RT_ASSERT(0); + break; + } +} + +static uint8_t run_speed[PM_RUN_MODE_MAX][2] = +{ + {48, 0}, + {48, 1}, + {24, 2}, + {2, 3}, +}; + +static void run(struct rt_pm *pm, uint8_t mode) +{ + static uint8_t last_mode; + static char *run_str[] = PM_RUN_MODE_NAMES; + extern uint32_t __system_clock; + + if (mode == last_mode) + return; + last_mode = mode; + + ald_cmu_clock_config_default(); + __system_clock = 24000000; + switch (mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + /* hosc 12MHz, from hosc/3 pll to 48MHz */ + ald_cmu_pll1_config(CMU_PLL1_INPUT_HRC_6, CMU_PLL1_OUTPUT_48M); + /* MCLK 48MHz */ + ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000); + break; + case PM_RUN_MODE_MEDIUM_SPEED: + break; + case PM_RUN_MODE_LOW_SPEED: + ald_cmu_clock_config(CMU_CLOCK_HRC, 2000000); + break; + default: + break; + } + + /* 4. 更新外设时钟 */ + uart_console_reconfig(); + /* Re-Configure the Systick time */ + SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND); + + rt_kprintf("switch to %s mode, frequency = %d MHz\n", run_str[mode], run_speed[mode][0]); +} + +/** + * This function caculate the PM tick from OS tick + * + * @param tick OS tick + * + * @return the PM tick + */ +static rt_tick_t es32f0_pm_tick_from_os_tick(rt_tick_t tick) +{ + rt_uint32_t freq = 1; + + return (freq * tick / RT_TICK_PER_SECOND); +} + +/** + * This function caculate the OS tick from PM tick + * + * @param tick PM tick + * + * @return the OS tick + */ +static rt_tick_t es32f0_os_tick_from_pm_tick(rt_uint32_t tick) +{ + static rt_uint32_t os_tick_remain = 0; + rt_uint32_t ret, freq; + + freq = 1; + ret = (tick * RT_TICK_PER_SECOND + os_tick_remain) / freq; + + os_tick_remain += (tick * RT_TICK_PER_SECOND); + os_tick_remain %= freq; + + return ret; +} + +/** + * This function start the timer of pm + * + * @param pm Pointer to power manage structure + * @param timeout How many OS Ticks that MCU can sleep + */ +static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout) +{ + RT_ASSERT(pm != RT_NULL); + RT_ASSERT(timeout > 0); + + if (timeout != RT_TICK_MAX) + { + /* Convert OS Tick to pmtimer timeout value */ + timeout = es32f0_pm_tick_from_os_tick(timeout); + /* MAX 0xFFFF */ + if (timeout > 0xFFFF) + { + timeout = 0xFFFF; + } + } +} + +/** + * This function stop the timer of pm + * + * @param pm Pointer to power manage structure + */ +static void pm_timer_stop(struct rt_pm *pm) +{ + RT_ASSERT(pm != RT_NULL); +} + +/** + * This function calculate how many OS Ticks that MCU have suspended + * + * @param pm Pointer to power manage structure + * + * @return OS Ticks + */ +static rt_tick_t pm_timer_get_tick(struct rt_pm *pm) +{ + rt_uint32_t timer_tick; + + RT_ASSERT(pm != RT_NULL); + + timer_tick = 1; + + return es32f0_os_tick_from_pm_tick(timer_tick); +} + +/** + * This function initialize the power manager + */ +int drv_pm_hw_init(void) +{ + static const struct rt_pm_ops _ops = + { + sleep, + run, + pm_timer_start, + pm_timer_stop, + pm_timer_get_tick + }; + + rt_uint8_t timer_mask = 0; + + /* initialize timer mask */ + timer_mask = 1UL << PM_SLEEP_MODE_DEEP; + + /* initialize system pm module */ + rt_system_pm_init(&_ops, timer_mask, RT_NULL); + + return 0; +} +INIT_BOARD_EXPORT(drv_pm_hw_init); + +#endif diff --git a/bsp/es32f0654/drivers/drv_pm.h b/bsp/essemi/es32f0654/drivers/drv_pm.h similarity index 100% rename from bsp/es32f0654/drivers/drv_pm.h rename to bsp/essemi/es32f0654/drivers/drv_pm.h diff --git a/bsp/es32f0654/drivers/drv_pwm.c b/bsp/essemi/es32f0654/drivers/drv_pwm.c similarity index 79% rename from bsp/es32f0654/drivers/drv_pwm.c rename to bsp/essemi/es32f0654/drivers/drv_pwm.c index 4bb747654d2d814520d676417f96d31448931431..d324e2bbbb12c6d38a0b33e7d1b5c683c709c4a7 100644 --- a/bsp/es32f0654/drivers/drv_pwm.c +++ b/bsp/essemi/es32f0654/drivers/drv_pwm.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-03-11 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -18,7 +19,7 @@ static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns) { - uint64_t _arr = (uint64_t)cmu_get_pclk1_clock() * ns / 1000000000 / + uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 / (timer_initstruct->init.prescaler + 1); WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); @@ -27,7 +28,7 @@ static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns) static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns) { - uint64_t tmp = (uint64_t)cmu_get_pclk1_clock() * ns / 1000000000 / + uint64_t tmp = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 / (timer_initstruct->init.prescaler + 1); if (ch == TIMER_CHANNEL_1) @@ -87,11 +88,11 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void * switch (cmd) { case PWM_CMD_ENABLE: - timer_pwm_start(timer_initstruct, pwm_channel); + ald_timer_pwm_start(timer_initstruct, pwm_channel); break; case PWM_CMD_DISABLE: - timer_pwm_stop(timer_initstruct, pwm_channel); + ald_timer_pwm_stop(timer_initstruct, pwm_channel); break; case PWM_CMD_SET: @@ -105,13 +106,13 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void * while (timer_initstruct->init.period > 0xFFFF); /* update prescaler */ WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler); - timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse); timer_initstruct->perh->CCEP = _ccep; break; case PWM_CMD_GET: - cfg->pulse = timer_read_capture_value(timer_initstruct, pwm_channel) * 100 / + cfg->pulse = ald_timer_read_capture_value(timer_initstruct, pwm_channel) * 100 / READ_REG(timer_initstruct->perh->AR); break; @@ -143,14 +144,14 @@ int rt_hw_pwm_init(void) static timer_handle_t timer_initstruct0; timer_initstruct0.perh = AD16C4T0; - timer_pwm_init(&timer_initstruct0); + ald_timer_pwm_init(&timer_initstruct0); /* gpio initialization */ gpio_initstructure.func = GPIO_FUNC_2; - gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure); - gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure); - gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure); - gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure); ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f0_pwm_ops, &timer_initstruct0); @@ -161,14 +162,14 @@ int rt_hw_pwm_init(void) static timer_handle_t timer_initstruct1; timer_initstruct1.perh = GP16C4T0; - timer_pwm_init(&timer_initstruct1); + ald_timer_pwm_init(&timer_initstruct1); /* gpio initialization */ gpio_initstructure.func = GPIO_FUNC_2; - gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); - gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); - gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); - gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f0_pwm_ops, &timer_initstruct1); @@ -179,12 +180,12 @@ int rt_hw_pwm_init(void) static timer_handle_t timer_initstruct2; timer_initstruct2.perh = GP16C2T0; - timer_pwm_init(&timer_initstruct2); + ald_timer_pwm_init(&timer_initstruct2); /* gpio initialization */ gpio_initstructure.func = GPIO_FUNC_2; - gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure); - gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure); ret = rt_device_pwm_register(&pwm_dev2, "pwm2", &es32f0_pwm_ops, &timer_initstruct2); @@ -195,12 +196,12 @@ int rt_hw_pwm_init(void) static timer_handle_t timer_initstruct3; timer_initstruct3.perh = GP16C2T1; - timer_pwm_init(&timer_initstruct3); + ald_timer_pwm_init(&timer_initstruct3); /* gpio initialization */ gpio_initstructure.func = GPIO_FUNC_3; - gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure); - gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure); ret = rt_device_pwm_register(&pwm_dev3, "pwm3", &es32f0_pwm_ops, &timer_initstruct3); diff --git a/bsp/es32f0654/drivers/drv_pwm.h b/bsp/essemi/es32f0654/drivers/drv_pwm.h similarity index 100% rename from bsp/es32f0654/drivers/drv_pwm.h rename to bsp/essemi/es32f0654/drivers/drv_pwm.h diff --git a/bsp/es32f0654/drivers/drv_rtc.c b/bsp/essemi/es32f0654/drivers/drv_rtc.c similarity index 93% rename from bsp/es32f0654/drivers/drv_rtc.c rename to bsp/essemi/es32f0654/drivers/drv_rtc.c index a16d4f179cb32d73582dc0af57ec5e1052fb4d15..32a68c3011016fd20ef6c42e446abf926dcc95fc 100644 --- a/bsp/es32f0654/drivers/drv_rtc.c +++ b/bsp/essemi/es32f0654/drivers/drv_rtc.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-03-22 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -25,7 +26,7 @@ static void __rtc_init(rtc_init_t *init) assert_param(IS_RTC_OUTPUT_SEL(init->output)); assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); - rtc_reset(); + ald_rtc_reset(); RTC_UNLOCK(); MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); @@ -51,7 +52,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) { case RT_DEVICE_CTRL_RTC_GET_TIME: - rtc_get_date_time(&date, &time, RTC_FORMAT_DEC); + ald_rtc_get_date_time(&date, &time, RTC_FORMAT_DEC); time_temp.tm_sec = time.second; time_temp.tm_min = time.minute; time_temp.tm_hour = time.hour; @@ -77,8 +78,8 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) date.year = time_temp.tm_year + 1900 - 2000; date.month = time_temp.tm_mon + 1; date.day = time_temp.tm_mday; - rtc_set_time(&time, RTC_FORMAT_DEC); - rtc_set_date(&date, RTC_FORMAT_DEC); + ald_rtc_set_time(&time, RTC_FORMAT_DEC); + ald_rtc_set_date(&date, RTC_FORMAT_DEC); /* start RTC */ RTC_UNLOCK(); SET_BIT(RTC->CON, RTC_CON_GO_MSK); @@ -118,7 +119,7 @@ int rt_hw_rtc_init(void) /* enable external 32.768kHz */ CMU_LOSC_ENABLE(); - cmu_losc_safe_config(ENABLE); + ald_cmu_losc_safe_config(ENABLE); /* set default time */ RTC_UNLOCK(); WRITE_REG(RTC->TIME, 0x134251); diff --git a/bsp/es32f0654/drivers/drv_rtc.h b/bsp/essemi/es32f0654/drivers/drv_rtc.h similarity index 100% rename from bsp/es32f0654/drivers/drv_rtc.h rename to bsp/essemi/es32f0654/drivers/drv_rtc.h diff --git a/bsp/es32f0654/drivers/drv_spi.c b/bsp/essemi/es32f0654/drivers/drv_spi.c similarity index 82% rename from bsp/es32f0654/drivers/drv_spi.c rename to bsp/essemi/es32f0654/drivers/drv_spi.c index f79258df3ac95db68008f9266192e639a1683a14..a029c6c772849e6809371425574ecaf7dd86a7e8 100644 --- a/bsp/es32f0654/drivers/drv_spi.c +++ b/bsp/essemi/es32f0654/drivers/drv_spi.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-01-24 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -80,14 +81,14 @@ rt_err_t spi_configure(struct rt_spi_device *device, } /* config spi clock */ - if (cfg->max_hz >= cmu_get_pclk1_clock() / 2) + if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 2) { /* pclk1 max speed 48MHz, spi master max speed 10MHz */ - if (cmu_get_pclk1_clock() / 2 <= 10000000) + if (ald_cmu_get_pclk1_clock() / 2 <= 10000000) { hspi->init.baud = SPI_BAUD_2; } - else if (cmu_get_pclk1_clock() / 4 <= 10000000) + else if (ald_cmu_get_pclk1_clock() / 4 <= 10000000) { hspi->init.baud = SPI_BAUD_4; } @@ -96,10 +97,10 @@ rt_err_t spi_configure(struct rt_spi_device *device, hspi->init.baud = SPI_BAUD_8; } } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 4) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 4) { /* pclk1 max speed 48MHz, spi master max speed 10MHz */ - if (cmu_get_pclk1_clock() / 4 <= 10000000) + if (ald_cmu_get_pclk1_clock() / 4 <= 10000000) { hspi->init.baud = SPI_BAUD_4; } @@ -108,23 +109,23 @@ rt_err_t spi_configure(struct rt_spi_device *device, hspi->init.baud = SPI_BAUD_8; } } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 8) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 8) { hspi->init.baud = SPI_BAUD_8; } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 16) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 16) { hspi->init.baud = SPI_BAUD_16; } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 32) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 32) { hspi->init.baud = SPI_BAUD_32; } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 64) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 64) { hspi->init.baud = SPI_BAUD_64; } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 128) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 128) { hspi->init.baud = SPI_BAUD_128; } @@ -132,7 +133,7 @@ rt_err_t spi_configure(struct rt_spi_device *device, { hspi->init.baud = SPI_BAUD_256; } - spi_init(hspi); + ald_spi_init(hspi); return RT_EOK; } @@ -157,7 +158,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * { rt_pin_write(cs->pin, 0); } - res = spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); + res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); if (message->cs_release) { rt_pin_write(cs->pin, 1); @@ -173,7 +174,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * { rt_pin_write(cs->pin, 0); } - res = spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); + res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); if (message->cs_release) { rt_pin_write(cs->pin, 1); @@ -189,8 +190,8 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * { rt_pin_write(cs->pin, 0); } - res = spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, - (rt_int32_t)message->length, SPITIMEOUT); + res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, + (rt_int32_t)message->length, SPITIMEOUT); if (message->cs_release) { rt_pin_write(cs->pin, 1); @@ -230,11 +231,11 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) gpio_instruct.flt = GPIO_FILTER_DISABLE; /* PB3->SPI0_SCK, PB5->SPI0_MOSI */ - gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct); /* PB4->SPI0_MISO */ gpio_instruct.mode = GPIO_MODE_INPUT; - gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); } else if (SPIx == SPI1) { @@ -250,11 +251,11 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) gpio_instruct.flt = GPIO_FILTER_DISABLE; /* PB13->SPI1_SCK, PB15->SPI1_MOSI */ - gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct); /* PB14->SPI1_MISO */ gpio_instruct.mode = GPIO_MODE_INPUT; - gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct); } else { diff --git a/bsp/es32f0654/drivers/drv_spi.h b/bsp/essemi/es32f0654/drivers/drv_spi.h similarity index 100% rename from bsp/es32f0654/drivers/drv_spi.h rename to bsp/essemi/es32f0654/drivers/drv_spi.h diff --git a/bsp/es32f0654/drivers/drv_spiflash.c b/bsp/essemi/es32f0654/drivers/drv_spiflash.c similarity index 92% rename from bsp/es32f0654/drivers/drv_spiflash.c rename to bsp/essemi/es32f0654/drivers/drv_spiflash.c index 0ed0dcc4458a63bc230b265b655f0290dc87a162..c84fe1be78c063358e9b93e48bc8ee3314c033c5 100644 --- a/bsp/es32f0654/drivers/drv_spiflash.c +++ b/bsp/essemi/es32f0654/drivers/drv_spiflash.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-02-15 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include diff --git a/bsp/es32f0654/drivers/drv_spiflash.h b/bsp/essemi/es32f0654/drivers/drv_spiflash.h similarity index 100% rename from bsp/es32f0654/drivers/drv_spiflash.h rename to bsp/essemi/es32f0654/drivers/drv_spiflash.h diff --git a/bsp/es32f0654/drivers/drv_uart.c b/bsp/essemi/es32f0654/drivers/drv_uart.c similarity index 90% rename from bsp/es32f0654/drivers/drv_uart.c rename to bsp/essemi/es32f0654/drivers/drv_uart.c index 776f1de9ad3c695b9bb426bd7a8ecc5c9b3a555b..4ebd18f826389393e36d87ded7418803db58ac5d 100644 --- a/bsp/es32f0654/drivers/drv_uart.c +++ b/bsp/essemi/es32f0654/drivers/drv_uart.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -43,38 +44,38 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial #ifdef BSP_USING_UART0 gpio_initstructure.func = GPIO_FUNC_3; - gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure); /* Initialize rx pin ,the same as txpin except mode */ gpio_initstructure.mode = GPIO_MODE_INPUT; - gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure); #endif /* uart0 gpio init */ #ifdef BSP_USING_UART1 gpio_initstructure.func = GPIO_FUNC_3; - gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure); /* Initialize rx pin ,the same as txpin except mode */ gpio_initstructure.mode = GPIO_MODE_INPUT; - gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure); #endif /* uart1 gpio init */ #ifdef BSP_USING_UART2 gpio_initstructure.func = GPIO_FUNC_5; - gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure); /* Initialize rx pin ,the same as txpin except mode */ gpio_initstructure.mode = GPIO_MODE_INPUT; - gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure); + ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure); #endif /* uart2 gpio init */ #ifdef BSP_USING_UART3 gpio_initstructure.func = GPIO_FUNC_4; - gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure); /* Initialize rx pin ,the same as txpin except mode */ gpio_initstructure.mode = GPIO_MODE_INPUT; - gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure); #endif /* uart3 gpio init */ uart->huart.init.mode = UART_MODE_UART; @@ -82,7 +83,7 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5); uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; - uart_init(&uart->huart); + ald_uart_init(&uart->huart); if (cfg->bit_order == BIT_ORDER_MSB) { @@ -103,7 +104,7 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial } /* enable rx int */ - uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); return RT_EOK; } @@ -120,14 +121,14 @@ static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void * /* disable rx irq */ NVIC_DisableIRQ(uart->irq); /* disable interrupt */ - uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE); + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ NVIC_EnableIRQ(uart->irq); /* enable interrupt */ - uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); break; } diff --git a/bsp/es32f0654/drivers/drv_uart.h b/bsp/essemi/es32f0654/drivers/drv_uart.h similarity index 100% rename from bsp/es32f0654/drivers/drv_uart.h rename to bsp/essemi/es32f0654/drivers/drv_uart.h diff --git a/bsp/es32f0654/drivers/linker_scripts/link.sct b/bsp/essemi/es32f0654/drivers/linker_scripts/link.sct similarity index 100% rename from bsp/es32f0654/drivers/linker_scripts/link.sct rename to bsp/essemi/es32f0654/drivers/linker_scripts/link.sct diff --git a/bsp/es32f0654/figures/ES-PDS-ES32F0654-V1.1.jpg b/bsp/essemi/es32f0654/figures/ES-PDS-ES32F0654-V1.1.jpg similarity index 100% rename from bsp/es32f0654/figures/ES-PDS-ES32F0654-V1.1.jpg rename to bsp/essemi/es32f0654/figures/ES-PDS-ES32F0654-V1.1.jpg diff --git a/bsp/es32f0654/figures/ESLinkII-mini.jpg b/bsp/essemi/es32f0654/figures/ESLinkII-mini.jpg similarity index 100% rename from bsp/es32f0654/figures/ESLinkII-mini.jpg rename to bsp/essemi/es32f0654/figures/ESLinkII-mini.jpg diff --git a/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h new file mode 100644 index 0000000000000000000000000000000000000000..645d1ff801340d0295408f37f927435cc5648918 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h @@ -0,0 +1,6631 @@ +/** + ********************************************************************************* + * + * @file es32f065x.h + * @brief ES32F065x Device Head File + * + * @version V1.0 + * @date 07 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ES32F0XX_H__ +#define __ES32F0XX_H__ + + +#define __I volatile const /* defines 'read only' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +#define __CHECK_DEVICE_DEFINES +#define __NVIC_PRIO_BITS 2U +#define __CM0_REV 0x0000U +#define __Vendor_SysTickConfig 0U + +typedef enum IRQn { + /* Cortex-M0 processor cxceptions index */ + Reset_IRQn = -15, + NMI_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* es32f0xx specific interrupt index */ + WWDG_IWDG_IRQn = 0, + LVD_IRQn = 1, + RTC_TSENSE_IRQn = 2, + CRYPT_TRNG_IRQn = 3, + CMU_IRQn = 4, + EXTI0_3_IRQn = 5, + EXTI4_7_IRQn = 6, + EXTI8_11_IRQn = 7, + EXTI12_15_IRQn = 8, + DMA_IRQn = 9, + CAN0_IRQn = 10, + LPTIM0_SPI2_IRQn = 11, + ADC_ACMP_IRQn = 12, + AD16C4T0_BRK_UP_TRIG_COM_IRQn = 13, + AD16C4T0_CC_IRQn = 14, + BS16T0_IRQn = 15, + GP16C2T0_IRQn = 17, + GP16C2T1_IRQn = 18, + BS16T1_UART2_IRQn = 19, + BS16T2_UART3_IRQn = 20, + GP16C4T0_LCD_IRQn = 21, + BS16T3_DAC0_IRQn = 22, + I2C0_IRQn = 23, + I2C1_IRQn = 24, + SPI0_IRQn = 25, + SPI1_IRQn = 26, + UART0_IRQn = 27, + UART1_IRQn = 28, + USART0_IRQn = 29, + USART1_IRQn = 30, + LPUART0_IRQn = 31, +} IRQn_Type; + + +#include +#include "core_cm0.h" + +#if defined (__CC_ARM) +#pragma anon_unions +#endif + +/* Peripheral register define */ + +/****************** Bit definition for SYSCFG_PROT register ************************/ + +#define SYSCFG_PROT_KEY_POSS 1U +#define SYSCFG_PROT_KEY_POSE 31U +#define SYSCFG_PROT_KEY_MSK BITS(SYSCFG_PROT_KEY_POSS,SYSCFG_PROT_KEY_POSE) + +#define SYSCFG_PROT_PROT_POS 0U +#define SYSCFG_PROT_PROT_MSK BIT(SYSCFG_PROT_PROT_POS) + +/****************** Bit definition for SYSCFG_MEMRMP register ************************/ + +#define SYSCFG_MEMRMP_VTOEN_POS 16U +#define SYSCFG_MEMRMP_VTOEN_MSK BIT(SYSCFG_MEMRMP_VTOEN_POS) + +#define SYSCFG_MEMRMP_BFRMPEN_POS 8U +#define SYSCFG_MEMRMP_BFRMPEN_MSK BIT(SYSCFG_MEMRMP_BFRMPEN_POS) + +#define SYSCFG_MEMRMP_BRRMPEN_POS 0U +#define SYSCFG_MEMRMP_BRRMPEN_MSK BIT(SYSCFG_MEMRMP_BRRMPEN_POS) + +/****************** Bit definition for SYSCFG_VTOR register ************************/ + +#define SYSCFG_VTOR_VTO_POSS 0U +#define SYSCFG_VTOR_VTO_POSE 29U +#define SYSCFG_VTOR_VTO_MSK BITS(SYSCFG_VTOR_VTO_POSS,SYSCFG_VTOR_VTO_POSE) + +typedef struct +{ + __IO uint32_t PROT; + __IO uint32_t MEMRMP; + __IO uint32_t VTOR; +} SYSCFG_TypeDef; + +/****************** Bit definition for MSC_FLASHKEY register ************************/ + +#define MSC_FLASHKEY_STATUS_POSS 0U +#define MSC_FLASHKEY_STATUS_POSE 1U +#define MSC_FLASHKEY_STATUS_MSK BITS(MSC_FLASHKEY_STATUS_POSS,MSC_FLASHKEY_STATUS_POSE) + +/****************** Bit definition for MSC_INFOKEY register ************************/ + +#define MSC_INFOKEY_STATUS_POSS 0U +#define MSC_INFOKEY_STATUS_POSE 1U +#define MSC_INFOKEY_STATUS_MSK BITS(MSC_INFOKEY_STATUS_POSS,MSC_INFOKEY_STATUS_POSE) + +/****************** Bit definition for MSC_FLASHADDR register ************************/ + +#define MSC_FLASHADDR_IFREN_POS 18U +#define MSC_FLASHADDR_IFREN_MSK BIT(MSC_FLASHADDR_IFREN_POS) + +#define MSC_FLASHADDR_ADDR_POSS 0U +#define MSC_FLASHADDR_ADDR_POSE 17U +#define MSC_FLASHADDR_ADDR_MSK BITS(MSC_FLASHADDR_ADDR_POSS,MSC_FLASHADDR_ADDR_POSE) + +/****************** Bit definition for MSC_FLASHFIFO register ************************/ + +#define MSC_FLASHFIFO_FIFO_POSS 0U +#define MSC_FLASHFIFO_FIFO_POSE 31U +#define MSC_FLASHFIFO_FIFO_MSK BITS(MSC_FLASHFIFO_FIFO_POSS,MSC_FLASHFIFO_FIFO_POSE) + +/****************** Bit definition for MSC_FLASHDL register ************************/ + +#define MSC_FLASHDL_DATAL_POSS 0U +#define MSC_FLASHDL_DATAL_POSE 31U +#define MSC_FLASHDL_DATAL_MSK BITS(MSC_FLASHDL_DATAL_POSS,MSC_FLASHDL_DATAL_POSE) + +/****************** Bit definition for MSC_FLASHDH register ************************/ + +#define MSC_FLASHDH_DATAH_POSS 0U +#define MSC_FLASHDH_DATAH_POSE 31U +#define MSC_FLASHDH_DATAH_MSK BITS(MSC_FLASHDH_DATAH_POSS,MSC_FLASHDH_DATAH_POSE) + +/****************** Bit definition for MSC_FLASHCMD register ************************/ + +#define MSC_FLASHCMD_CMD_POSS 0U +#define MSC_FLASHCMD_CMD_POSE 31U +#define MSC_FLASHCMD_CMD_MSK BITS(MSC_FLASHCMD_CMD_POSS,MSC_FLASHCMD_CMD_POSE) + +/****************** Bit definition for MSC_FLASHCR register ************************/ + +#define MSC_FLASHCR_FIFOEN_POS 5U +#define MSC_FLASHCR_FIFOEN_MSK BIT(MSC_FLASHCR_FIFOEN_POS) + +#define MSC_FLASHCR_FLASHREQ_POS 4U +#define MSC_FLASHCR_FLASHREQ_MSK BIT(MSC_FLASHCR_FLASHREQ_POS) + +#define MSC_FLASHCR_IAPRST_POS 1U +#define MSC_FLASHCR_IAPRST_MSK BIT(MSC_FLASHCR_IAPRST_POS) + +#define MSC_FLASHCR_IAPEN_POS 0U +#define MSC_FLASHCR_IAPEN_MSK BIT(MSC_FLASHCR_IAPEN_POS) + +/****************** Bit definition for MSC_FLASHSR register ************************/ + +#define MSC_FLASHSR_TIMEOUT_POS 7U +#define MSC_FLASHSR_TIMEOUT_MSK BIT(MSC_FLASHSR_TIMEOUT_POS) + +#define MSC_FLASHSR_PROG_POS 6U +#define MSC_FLASHSR_PROG_MSK BIT(MSC_FLASHSR_PROG_POS) + +#define MSC_FLASHSR_SERA_POS 5U +#define MSC_FLASHSR_SERA_MSK BIT(MSC_FLASHSR_SERA_POS) + +#define MSC_FLASHSR_MASE_POS 4U +#define MSC_FLASHSR_MASE_MSK BIT(MSC_FLASHSR_MASE_POS) + +#define MSC_FLASHSR_ADDR_OV_POS 3U +#define MSC_FLASHSR_ADDR_OV_MSK BIT(MSC_FLASHSR_ADDR_OV_POS) + +#define MSC_FLASHSR_WRP_FLAG_POS 2U +#define MSC_FLASHSR_WRP_FLAG_MSK BIT(MSC_FLASHSR_WRP_FLAG_POS) + +#define MSC_FLASHSR_BUSY_POS 1U +#define MSC_FLASHSR_BUSY_MSK BIT(MSC_FLASHSR_BUSY_POS) + +#define MSC_FLASHSR_FLASHACK_POS 0U +#define MSC_FLASHSR_FLASHACK_MSK BIT(MSC_FLASHSR_FLASHACK_POS) + +/****************** Bit definition for MSC_FLASHPL register ************************/ + +#define MSC_FLASHPL_PROG_LEN_POSS 0U +#define MSC_FLASHPL_PROG_LEN_POSE 15U +#define MSC_FLASHPL_PROG_LEN_MSK BITS(MSC_FLASHPL_PROG_LEN_POSS,MSC_FLASHPL_PROG_LEN_POSE) + +/****************** Bit definition for MSC_MEMWAIT register ************************/ + +#define MSC_MEMWAIT_SRAM_W_POSS 8U +#define MSC_MEMWAIT_SRAM_W_POSE 9U +#define MSC_MEMWAIT_SRAM_W_MSK BITS(MSC_MEMWAIT_SRAM_W_POSS,MSC_MEMWAIT_SRAM_W_POSE) + +#define MSC_MEMWAIT_FLASH_W_POSS 0U +#define MSC_MEMWAIT_FLASH_W_POSE 3U +#define MSC_MEMWAIT_FLASH_W_MSK BITS(MSC_MEMWAIT_FLASH_W_POSS,MSC_MEMWAIT_FLASH_W_POSE) + +typedef struct +{ + __IO uint32_t FLASHKEY; + __IO uint32_t INFOKEY; + __IO uint32_t FLASHADDR; + __O uint32_t FLASHFIFO; + __IO uint32_t FLASHDL; + __IO uint32_t FLASHDH; + __O uint32_t FLASHCMD; + __IO uint32_t FLASHCR; + __I uint32_t FLASHSR; + __IO uint32_t FLASHPL; + __IO uint32_t MEMWAIT; +} MSC_TypeDef; + +/****************** Bit definition for BKPC_PROT register ************************/ + +#define BKPC_PROT_KEY_POSS 1U +#define BKPC_PROT_KEY_POSE 31U +#define BKPC_PROT_KEY_MSK BITS(BKPC_PROT_KEY_POSS,BKPC_PROT_KEY_POSE) + +#define BKPC_PROT_PROT_POS 0U +#define BKPC_PROT_PROT_MSK BIT(BKPC_PROT_PROT_POS) + +/****************** Bit definition for BKPC_CR register ************************/ + +#define BKPC_CR_LDO_VSEL_POSS 24U +#define BKPC_CR_LDO_VSEL_POSE 26U +#define BKPC_CR_LDO_VSEL_MSK BITS(BKPC_CR_LDO_VSEL_POSS,BKPC_CR_LDO_VSEL_POSE) + +#define BKPC_CR_MT_STDB_POS 19U +#define BKPC_CR_MT_STDB_MSK BIT(BKPC_CR_MT_STDB_POS) + +#define BKPC_CR_VR1P5_VSEL_POSS 16U +#define BKPC_CR_VR1P5_VSEL_POSE 18U +#define BKPC_CR_VR1P5_VSEL_MSK BITS(BKPC_CR_VR1P5_VSEL_POSS,BKPC_CR_VR1P5_VSEL_POSE) + +#define BKPC_CR_TC_PWRDWN_POS 13U +#define BKPC_CR_TC_PWRDWN_MSK BIT(BKPC_CR_TC_PWRDWN_POS) + +#define BKPC_CR_WKPOL_POS 12U +#define BKPC_CR_WKPOL_MSK BIT(BKPC_CR_WKPOL_POS) + +#define BKPC_CR_WKPS_POSS 9U +#define BKPC_CR_WKPS_POSE 11U +#define BKPC_CR_WKPS_MSK BITS(BKPC_CR_WKPS_POSS,BKPC_CR_WKPS_POSE) + +#define BKPC_CR_WKPEN_POS 8U +#define BKPC_CR_WKPEN_MSK BIT(BKPC_CR_WKPEN_POS) + +#define BKPC_CR_LRCEN_POS 2U +#define BKPC_CR_LRCEN_MSK BIT(BKPC_CR_LRCEN_POS) + +#define BKPC_CR_LOSMEN_POS 1U +#define BKPC_CR_LOSMEN_MSK BIT(BKPC_CR_LOSMEN_POS) + +#define BKPC_CR_LOSCEN_POS 0U +#define BKPC_CR_LOSCEN_MSK BIT(BKPC_CR_LOSCEN_POS) + +/****************** Bit definition for BKPC_PCCR register ************************/ + +#define BKPC_PCCR_TSENSECS_POSS 4U +#define BKPC_PCCR_TSENSECS_POSE 5U +#define BKPC_PCCR_TSENSECS_MSK BITS(BKPC_PCCR_TSENSECS_POSS,BKPC_PCCR_TSENSECS_POSE) + +#define BKPC_PCCR_RTCCS_POSS 0U +#define BKPC_PCCR_RTCCS_POSE 1U +#define BKPC_PCCR_RTCCS_MSK BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE) + +/****************** Bit definition for BKPC_PCR register ************************/ + +#define BKPC_PCR_BORS_POSS 1U +#define BKPC_PCR_BORS_POSE 4U +#define BKPC_PCR_BORS_MSK BITS(BKPC_PCR_BORS_POSS,BKPC_PCR_BORS_POSE) + +#define BKPC_PCR_BOREN_POS 0U +#define BKPC_PCR_BOREN_MSK BIT(BKPC_PCR_BOREN_POS) + +typedef struct +{ + __IO uint32_t PROT; + __IO uint32_t CR; + __IO uint32_t PCCR; + __IO uint32_t PCR; +} BKPC_TypeDef; + +/****************** Bit definition for PMU_CR register ************************/ + +#define PMU_CR_MTSTOP_POS 21U +#define PMU_CR_MTSTOP_MSK BIT(PMU_CR_MTSTOP_POS) + +#define PMU_CR_LPSTOP_POS 20U +#define PMU_CR_LPSTOP_MSK BIT(PMU_CR_LPSTOP_POS) + +#define PMU_CR_LPRUN_POS 19U +#define PMU_CR_LPRUN_MSK BIT(PMU_CR_LPRUN_POS) + +#define PMU_CR_LPVS_POSS 16U +#define PMU_CR_LPVS_POSE 18U +#define PMU_CR_LPVS_MSK BITS(PMU_CR_LPVS_POSS,PMU_CR_LPVS_POSE) + +#define PMU_CR_WKPS_POSS 9U +#define PMU_CR_WKPS_POSE 11U +#define PMU_CR_WKPS_MSK BITS(PMU_CR_WKPS_POSS,PMU_CR_WKPS_POSE) + +#define PMU_CR_WKPEN_POS 8U +#define PMU_CR_WKPEN_MSK BIT(PMU_CR_WKPEN_POS) + +#define PMU_CR_CSTANDBYF_POS 3U +#define PMU_CR_CSTANDBYF_MSK BIT(PMU_CR_CSTANDBYF_POS) + +#define PMU_CR_CWUF_POS 2U +#define PMU_CR_CWUF_MSK BIT(PMU_CR_CWUF_POS) + +#define PMU_CR_LPM_POSS 0U +#define PMU_CR_LPM_POSE 1U +#define PMU_CR_LPM_MSK BITS(PMU_CR_LPM_POSS,PMU_CR_LPM_POSE) + +/****************** Bit definition for PMU_SR register ************************/ + +#define PMU_SR_STANDBYF_POS 1U +#define PMU_SR_STANDBYF_MSK BIT(PMU_SR_STANDBYF_POS) + +#define PMU_SR_WUF_POS 0U +#define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS) + +/****************** Bit definition for PMU_LVDCR register ************************/ + +#define PMU_LVDCR_LVDO_POS 15U +#define PMU_LVDCR_LVDO_MSK BIT(PMU_LVDCR_LVDO_POS) + +#define PMU_LVDCR_LVDFLT_POS 11U +#define PMU_LVDCR_LVDFLT_MSK BIT(PMU_LVDCR_LVDFLT_POS) + +#define PMU_LVDCR_LVIFS_POSS 8U +#define PMU_LVDCR_LVIFS_POSE 10U +#define PMU_LVDCR_LVIFS_MSK BITS(PMU_LVDCR_LVIFS_POSS,PMU_LVDCR_LVIFS_POSE) + +#define PMU_LVDCR_LVDS_POSS 4U +#define PMU_LVDCR_LVDS_POSE 7U +#define PMU_LVDCR_LVDS_MSK BITS(PMU_LVDCR_LVDS_POSS,PMU_LVDCR_LVDS_POSE) + +#define PMU_LVDCR_LVDCIF_POS 3U +#define PMU_LVDCR_LVDCIF_MSK BIT(PMU_LVDCR_LVDCIF_POS) + +#define PMU_LVDCR_LVDIF_POS 2U +#define PMU_LVDCR_LVDIF_MSK BIT(PMU_LVDCR_LVDIF_POS) + +#define PMU_LVDCR_LVDIE_POS 1U +#define PMU_LVDCR_LVDIE_MSK BIT(PMU_LVDCR_LVDIE_POS) + +#define PMU_LVDCR_LVDEN_POS 0U +#define PMU_LVDCR_LVDEN_MSK BIT(PMU_LVDCR_LVDEN_POS) + +/****************** Bit definition for PMU_PWRCR register ************************/ + +#define PMU_PWRCR_BXCAN_POS 4U +#define PMU_PWRCR_BXCAN_MSK BIT(PMU_PWRCR_BXCAN_POS) + +#define PMU_PWRCR_SRAM_POSS 0U +#define PMU_PWRCR_SRAM_POSE 1U +#define PMU_PWRCR_SRAM_MSK BITS(PMU_PWRCR_SRAM_POSS,PMU_PWRCR_SRAM_POSE) + +/****************** Bit definition for PMU_TWUR register ************************/ + +#define PMU_TWUR_TWU_POSS 0U +#define PMU_TWUR_TWU_POSE 11U +#define PMU_TWUR_TWU_MSK BITS(PMU_TWUR_TWU_POSS,PMU_TWUR_TWU_POSE) + +/****************** Bit definition for PMU_VREFCR register ************************/ + +#define PMU_VREFCR_FLTS_POSS 13U +#define PMU_VREFCR_FLTS_POSE 14U +#define PMU_VREFCR_FLTS_MSK BITS(PMU_VREFCR_FLTS_POSS,PMU_VREFCR_FLTS_POSE) + +#define PMU_VREFCR_CHOPCS_POSS 10U +#define PMU_VREFCR_CHOPCS_POSE 12U +#define PMU_VREFCR_CHOPCS_MSK BITS(PMU_VREFCR_CHOPCS_POSS,PMU_VREFCR_CHOPCS_POSE) + +#define PMU_VREFCR_CHOP1EN_POS 9U +#define PMU_VREFCR_CHOP1EN_MSK BIT(PMU_VREFCR_CHOP1EN_POS) + +#define PMU_VREFCR_CHOPEN_POS 8U +#define PMU_VREFCR_CHOPEN_MSK BIT(PMU_VREFCR_CHOPEN_POS) + +#define PMU_VREFCR_VREFEN_POS 0U +#define PMU_VREFCR_VREFEN_MSK BIT(PMU_VREFCR_VREFEN_POS) + +typedef struct +{ + __IO uint32_t CR; + __I uint32_t SR; + __IO uint32_t LVDCR; + __IO uint32_t PWRCR; + __IO uint32_t TWUR; + __IO uint32_t VREFCR; +} PMU_TypeDef; + +/****************** Bit definition for RMU_CR register ************************/ + +#define RMU_CR_BORVS_POSS 4U +#define RMU_CR_BORVS_POSE 7U +#define RMU_CR_BORVS_MSK BITS(RMU_CR_BORVS_POSS,RMU_CR_BORVS_POSE) + +#define RMU_CR_BORFLT_POSS 1U +#define RMU_CR_BORFLT_POSE 3U +#define RMU_CR_BORFLT_MSK BITS(RMU_CR_BORFLT_POSS,RMU_CR_BORFLT_POSE) + +#define RMU_CR_BOREN_POS 0U +#define RMU_CR_BOREN_MSK BIT(RMU_CR_BOREN_POS) + +/****************** Bit definition for RMU_RSTSR register ************************/ + +#define RMU_RSTSR_CFGERR_POS 16U +#define RMU_RSTSR_CFGERR_MSK BIT(RMU_RSTSR_CFGERR_POS) + +#define RMU_RSTSR_CFG_POS 10U +#define RMU_RSTSR_CFG_MSK BIT(RMU_RSTSR_CFG_POS) + +#define RMU_RSTSR_CPU_POS 9U +#define RMU_RSTSR_CPU_MSK BIT(RMU_RSTSR_CPU_POS) + +#define RMU_RSTSR_MCU_POS 8U +#define RMU_RSTSR_MCU_MSK BIT(RMU_RSTSR_MCU_POS) + +#define RMU_RSTSR_CHIP_POS 7U +#define RMU_RSTSR_CHIP_MSK BIT(RMU_RSTSR_CHIP_POS) + +#define RMU_RSTSR_LOCKUP_POS 6U +#define RMU_RSTSR_LOCKUP_MSK BIT(RMU_RSTSR_LOCKUP_POS) + +#define RMU_RSTSR_WWDT_POS 5U +#define RMU_RSTSR_WWDT_MSK BIT(RMU_RSTSR_WWDT_POS) + +#define RMU_RSTSR_IWDT_POS 4U +#define RMU_RSTSR_IWDT_MSK BIT(RMU_RSTSR_IWDT_POS) + +#define RMU_RSTSR_NMRST_POS 3U +#define RMU_RSTSR_NMRST_MSK BIT(RMU_RSTSR_NMRST_POS) + +#define RMU_RSTSR_BOR_POS 2U +#define RMU_RSTSR_BOR_MSK BIT(RMU_RSTSR_BOR_POS) + +#define RMU_RSTSR_WAKEUP_POS 1U +#define RMU_RSTSR_WAKEUP_MSK BIT(RMU_RSTSR_WAKEUP_POS) + +#define RMU_RSTSR_POR_POS 0U +#define RMU_RSTSR_POR_MSK BIT(RMU_RSTSR_POR_POS) + +/****************** Bit definition for RMU_CRSTSR register ************************/ + +#define RMU_CRSTSR_CFG_POS 10U +#define RMU_CRSTSR_CFG_MSK BIT(RMU_CRSTSR_CFG_POS) + +#define RMU_CRSTSR_CPU_POS 9U +#define RMU_CRSTSR_CPU_MSK BIT(RMU_CRSTSR_CPU_POS) + +#define RMU_CRSTSR_MCU_POS 8U +#define RMU_CRSTSR_MCU_MSK BIT(RMU_CRSTSR_MCU_POS) + +#define RMU_CRSTSR_CHIP_POS 7U +#define RMU_CRSTSR_CHIP_MSK BIT(RMU_CRSTSR_CHIP_POS) + +#define RMU_CRSTSR_LOCKUP_POS 6U +#define RMU_CRSTSR_LOCKUP_MSK BIT(RMU_CRSTSR_LOCKUP_POS) + +#define RMU_CRSTSR_WWDT_POS 5U +#define RMU_CRSTSR_WWDT_MSK BIT(RMU_CRSTSR_WWDT_POS) + +#define RMU_CRSTSR_IWDT_POS 4U +#define RMU_CRSTSR_IWDT_MSK BIT(RMU_CRSTSR_IWDT_POS) + +#define RMU_CRSTSR_NMRST_POS 3U +#define RMU_CRSTSR_NMRST_MSK BIT(RMU_CRSTSR_NMRST_POS) + +#define RMU_CRSTSR_BOR_POS 2U +#define RMU_CRSTSR_BOR_MSK BIT(RMU_CRSTSR_BOR_POS) + +#define RMU_CRSTSR_WAKEUP_POS 1U +#define RMU_CRSTSR_WAKEUP_MSK BIT(RMU_CRSTSR_WAKEUP_POS) + +#define RMU_CRSTSR_POR_POS 0U +#define RMU_CRSTSR_POR_MSK BIT(RMU_CRSTSR_POR_POS) + +/****************** Bit definition for RMU_AHB1RSTR register ************************/ + +#define RMU_AHB1RSTR_PISRST_POS 5U +#define RMU_AHB1RSTR_PISRST_MSK BIT(RMU_AHB1RSTR_PISRST_POS) + +#define RMU_AHB1RSTR_TRNGRST_POS 4U +#define RMU_AHB1RSTR_TRNGRST_MSK BIT(RMU_AHB1RSTR_TRNGRST_POS) + +#define RMU_AHB1RSTR_CRYPTRST_POS 3U +#define RMU_AHB1RSTR_CRYPTRST_MSK BIT(RMU_AHB1RSTR_CRYPTRST_POS) + +#define RMU_AHB1RSTR_CALCRST_POS 2U +#define RMU_AHB1RSTR_CALCRST_MSK BIT(RMU_AHB1RSTR_CALCRST_POS) + +#define RMU_AHB1RSTR_CRCRST_POS 1U +#define RMU_AHB1RSTR_CRCRST_MSK BIT(RMU_AHB1RSTR_CRCRST_POS) + +#define RMU_AHB1RSTR_GPIORST_POS 0U +#define RMU_AHB1RSTR_GPIORST_MSK BIT(RMU_AHB1RSTR_GPIORST_POS) + +/****************** Bit definition for RMU_AHB2RSTR register ************************/ + +#define RMU_AHB2RSTR_CPURST_POS 1U +#define RMU_AHB2RSTR_CPURST_MSK BIT(RMU_AHB2RSTR_CPURST_POS) + +#define RMU_AHB2RSTR_CHIPRST_POS 0U +#define RMU_AHB2RSTR_CHIPRST_MSK BIT(RMU_AHB2RSTR_CHIPRST_POS) + +/****************** Bit definition for RMU_APB1RSTR register ************************/ + +#define RMU_APB1RSTR_CAN0RST_POS 24U +#define RMU_APB1RSTR_CAN0RST_MSK BIT(RMU_APB1RSTR_CAN0RST_POS) + +#define RMU_APB1RSTR_I2C1RST_POS 21U +#define RMU_APB1RSTR_I2C1RST_MSK BIT(RMU_APB1RSTR_I2C1RST_POS) + +#define RMU_APB1RSTR_I2C0RST_POS 20U +#define RMU_APB1RSTR_I2C0RST_MSK BIT(RMU_APB1RSTR_I2C0RST_POS) + +#define RMU_APB1RSTR_SPI2RST_POS 18U +#define RMU_APB1RSTR_SPI2RST_MSK BIT(RMU_APB1RSTR_SPI2RST_POS) + +#define RMU_APB1RSTR_SPI1RST_POS 17U +#define RMU_APB1RSTR_SPI1RST_MSK BIT(RMU_APB1RSTR_SPI1RST_POS) + +#define RMU_APB1RSTR_SPI0RST_POS 16U +#define RMU_APB1RSTR_SPI0RST_MSK BIT(RMU_APB1RSTR_SPI0RST_POS) + +#define RMU_APB1RSTR_USART1RST_POS 13U +#define RMU_APB1RSTR_USART1RST_MSK BIT(RMU_APB1RSTR_USART1RST_POS) + +#define RMU_APB1RSTR_USART0RST_POS 12U +#define RMU_APB1RSTR_USART0RST_MSK BIT(RMU_APB1RSTR_USART0RST_POS) + +#define RMU_APB1RSTR_UART3RST_POS 11U +#define RMU_APB1RSTR_UART3RST_MSK BIT(RMU_APB1RSTR_UART3RST_POS) + +#define RMU_APB1RSTR_UART2RST_POS 10U +#define RMU_APB1RSTR_UART2RST_MSK BIT(RMU_APB1RSTR_UART2RST_POS) + +#define RMU_APB1RSTR_UART1RST_POS 9U +#define RMU_APB1RSTR_UART1RST_MSK BIT(RMU_APB1RSTR_UART1RST_POS) + +#define RMU_APB1RSTR_UART0RST_POS 8U +#define RMU_APB1RSTR_UART0RST_MSK BIT(RMU_APB1RSTR_UART0RST_POS) + +#define RMU_APB1RSTR_TIM7RST_POS 7U +#define RMU_APB1RSTR_TIM7RST_MSK BIT(RMU_APB1RSTR_TIM7RST_POS) + +#define RMU_APB1RSTR_TIM6RST_POS 6U +#define RMU_APB1RSTR_TIM6RST_MSK BIT(RMU_APB1RSTR_TIM6RST_POS) + +#define RMU_APB1RSTR_TIM5RST_POS 5U +#define RMU_APB1RSTR_TIM5RST_MSK BIT(RMU_APB1RSTR_TIM5RST_POS) + +#define RMU_APB1RSTR_TIM4RST_POS 4U +#define RMU_APB1RSTR_TIM4RST_MSK BIT(RMU_APB1RSTR_TIM4RST_POS) + +#define RMU_APB1RSTR_TIM3RST_POS 3U +#define RMU_APB1RSTR_TIM3RST_MSK BIT(RMU_APB1RSTR_TIM3RST_POS) + +#define RMU_APB1RSTR_TIM2RST_POS 2U +#define RMU_APB1RSTR_TIM2RST_MSK BIT(RMU_APB1RSTR_TIM2RST_POS) + +#define RMU_APB1RSTR_TIM1RST_POS 1U +#define RMU_APB1RSTR_TIM1RST_MSK BIT(RMU_APB1RSTR_TIM1RST_POS) + +#define RMU_APB1RSTR_TIM0RST_POS 0U +#define RMU_APB1RSTR_TIM0RST_MSK BIT(RMU_APB1RSTR_TIM0RST_POS) + +/****************** Bit definition for RMU_APB2RSTR register ************************/ + +#define RMU_APB2RSTR_BKPRAMRST_POS 18U +#define RMU_APB2RSTR_BKPRAMRST_MSK BIT(RMU_APB2RSTR_BKPRAMRST_POS) + +#define RMU_APB2RSTR_BKPCRST_POS 17U +#define RMU_APB2RSTR_BKPCRST_MSK BIT(RMU_APB2RSTR_BKPCRST_POS) + +#define RMU_APB2RSTR_TSENSERST_POS 16U +#define RMU_APB2RSTR_TSENSERST_MSK BIT(RMU_APB2RSTR_TSENSERST_POS) + +#define RMU_APB2RSTR_RTCRST_POS 15U +#define RMU_APB2RSTR_RTCRST_MSK BIT(RMU_APB2RSTR_RTCRST_POS) + +#define RMU_APB2RSTR_IWDTRST_POS 14U +#define RMU_APB2RSTR_IWDTRST_MSK BIT(RMU_APB2RSTR_IWDTRST_POS) + +#define RMU_APB2RSTR_LCDRST_POS 13U +#define RMU_APB2RSTR_LCDRST_MSK BIT(RMU_APB2RSTR_LCDRST_POS) + +#define RMU_APB2RSTR_WWDTRST_POS 12U +#define RMU_APB2RSTR_WWDTRST_MSK BIT(RMU_APB2RSTR_WWDTRST_POS) + +#define RMU_APB2RSTR_OPAMPRST_POS 8U +#define RMU_APB2RSTR_OPAMPRST_MSK BIT(RMU_APB2RSTR_OPAMPRST_POS) + +#define RMU_APB2RSTR_ACMP1RST_POS 7U +#define RMU_APB2RSTR_ACMP1RST_MSK BIT(RMU_APB2RSTR_ACMP1RST_POS) + +#define RMU_APB2RSTR_ACMP0RST_POS 6U +#define RMU_APB2RSTR_ACMP0RST_MSK BIT(RMU_APB2RSTR_ACMP0RST_POS) + +#define RMU_APB2RSTR_ADC0RST_POS 4U +#define RMU_APB2RSTR_ADC0RST_MSK BIT(RMU_APB2RSTR_ADC0RST_POS) + +#define RMU_APB2RSTR_LPUART0RST_POS 2U +#define RMU_APB2RSTR_LPUART0RST_MSK BIT(RMU_APB2RSTR_LPUART0RST_POS) + +#define RMU_APB2RSTR_LPTIM0RST_POS 0U +#define RMU_APB2RSTR_LPTIM0RST_MSK BIT(RMU_APB2RSTR_LPTIM0RST_POS) + +typedef struct +{ + __IO uint32_t CR; + uint32_t RESERVED0[3] ; + __I uint32_t RSTSR; + __O uint32_t CRSTSR; + uint32_t RESERVED1[2] ; + __O uint32_t AHB1RSTR; + __O uint32_t AHB2RSTR; + uint32_t RESERVED2[2] ; + __O uint32_t APB1RSTR; + __O uint32_t APB2RSTR; +} RMU_TypeDef; + +/****************** Bit definition for CMU_CSR register ************************/ + +#define CMU_CSR_CFT_RDYN_POS 25U +#define CMU_CSR_CFT_RDYN_MSK BIT(CMU_CSR_CFT_RDYN_POS) + +#define CMU_CSR_CFT_STU_POS 24U +#define CMU_CSR_CFT_STU_MSK BIT(CMU_CSR_CFT_STU_POS) + +#define CMU_CSR_CFT_CMD_POSS 16U +#define CMU_CSR_CFT_CMD_POSE 23U +#define CMU_CSR_CFT_CMD_MSK BITS(CMU_CSR_CFT_CMD_POSS,CMU_CSR_CFT_CMD_POSE) + +#define CMU_CSR_SYS_RDYN_POS 12U +#define CMU_CSR_SYS_RDYN_MSK BIT(CMU_CSR_SYS_RDYN_POS) + +#define CMU_CSR_SYS_STU_POSS 8U +#define CMU_CSR_SYS_STU_POSE 10U +#define CMU_CSR_SYS_STU_MSK BITS(CMU_CSR_SYS_STU_POSS,CMU_CSR_SYS_STU_POSE) + +#define CMU_CSR_SYS_CMD_POSS 0U +#define CMU_CSR_SYS_CMD_POSE 2U +#define CMU_CSR_SYS_CMD_MSK BITS(CMU_CSR_SYS_CMD_POSS,CMU_CSR_SYS_CMD_POSE) + +/****************** Bit definition for CMU_CFGR register ************************/ + +#define CMU_CFGR_HRCFST_POS 25U +#define CMU_CFGR_HRCFST_MSK BIT(CMU_CFGR_HRCFST_POS) + +#define CMU_CFGR_HRCFSW_POS 24U +#define CMU_CFGR_HRCFSW_MSK BIT(CMU_CFGR_HRCFSW_POS) + +#define CMU_CFGR_PCLK2DIV_POSS 20U +#define CMU_CFGR_PCLK2DIV_POSE 23U +#define CMU_CFGR_PCLK2DIV_MSK BITS(CMU_CFGR_PCLK2DIV_POSS,CMU_CFGR_PCLK2DIV_POSE) + +#define CMU_CFGR_PCLK1DIV_POSS 16U +#define CMU_CFGR_PCLK1DIV_POSE 19U +#define CMU_CFGR_PCLK1DIV_MSK BITS(CMU_CFGR_PCLK1DIV_POSS,CMU_CFGR_PCLK1DIV_POSE) + +#define CMU_CFGR_SYSDIV_POSS 12U +#define CMU_CFGR_SYSDIV_POSE 15U +#define CMU_CFGR_SYSDIV_MSK BITS(CMU_CFGR_SYSDIV_POSS,CMU_CFGR_SYSDIV_POSE) + +#define CMU_CFGR_HCLK1DIV_POSS 0U +#define CMU_CFGR_HCLK1DIV_POSE 3U +#define CMU_CFGR_HCLK1DIV_MSK BITS(CMU_CFGR_HCLK1DIV_POSS,CMU_CFGR_HCLK1DIV_POSE) + +/****************** Bit definition for CMU_CLKENR register ************************/ + +#define CMU_CLKENR_PLL2EN_POS 9U +#define CMU_CLKENR_PLL2EN_MSK BIT(CMU_CLKENR_PLL2EN_POS) + +#define CMU_CLKENR_PLL1EN_POS 8U +#define CMU_CLKENR_PLL1EN_MSK BIT(CMU_CLKENR_PLL1EN_POS) + +#define CMU_CLKENR_ULRCEN_POS 4U +#define CMU_CLKENR_ULRCEN_MSK BIT(CMU_CLKENR_ULRCEN_POS) + +#define CMU_CLKENR_LRCEN_POS 3U +#define CMU_CLKENR_LRCEN_MSK BIT(CMU_CLKENR_LRCEN_POS) + +#define CMU_CLKENR_HRCEN_POS 2U +#define CMU_CLKENR_HRCEN_MSK BIT(CMU_CLKENR_HRCEN_POS) + +#define CMU_CLKENR_LOSCEN_POS 1U +#define CMU_CLKENR_LOSCEN_MSK BIT(CMU_CLKENR_LOSCEN_POS) + +#define CMU_CLKENR_HOSCEN_POS 0U +#define CMU_CLKENR_HOSCEN_MSK BIT(CMU_CLKENR_HOSCEN_POS) + +/****************** Bit definition for CMU_CLKSR register ************************/ + +#define CMU_CLKSR_PLL2RDY_POS 25U +#define CMU_CLKSR_PLL2RDY_MSK BIT(CMU_CLKSR_PLL2RDY_POS) + +#define CMU_CLKSR_PLL1RDY_POS 24U +#define CMU_CLKSR_PLL1RDY_MSK BIT(CMU_CLKSR_PLL1RDY_POS) + +#define CMU_CLKSR_LRCRDY_POS 19U +#define CMU_CLKSR_LRCRDY_MSK BIT(CMU_CLKSR_LRCRDY_POS) + +#define CMU_CLKSR_HRCRDY_POS 18U +#define CMU_CLKSR_HRCRDY_MSK BIT(CMU_CLKSR_HRCRDY_POS) + +#define CMU_CLKSR_LOSCRDY_POS 17U +#define CMU_CLKSR_LOSCRDY_MSK BIT(CMU_CLKSR_LOSCRDY_POS) + +#define CMU_CLKSR_HOSCRDY_POS 16U +#define CMU_CLKSR_HOSCRDY_MSK BIT(CMU_CLKSR_HOSCRDY_POS) + +#define CMU_CLKSR_PLL2ACT_POS 9U +#define CMU_CLKSR_PLL2ACT_MSK BIT(CMU_CLKSR_PLL2ACT_POS) + +#define CMU_CLKSR_PLL1ACT_POS 8U +#define CMU_CLKSR_PLL1ACT_MSK BIT(CMU_CLKSR_PLL1ACT_POS) + +#define CMU_CLKSR_ULRCACT_POS 4U +#define CMU_CLKSR_ULRCACT_MSK BIT(CMU_CLKSR_ULRCACT_POS) + +#define CMU_CLKSR_LRCACT_POS 3U +#define CMU_CLKSR_LRCACT_MSK BIT(CMU_CLKSR_LRCACT_POS) + +#define CMU_CLKSR_HRCACT_POS 2U +#define CMU_CLKSR_HRCACT_MSK BIT(CMU_CLKSR_HRCACT_POS) + +#define CMU_CLKSR_LOSCACT_POS 1U +#define CMU_CLKSR_LOSCACT_MSK BIT(CMU_CLKSR_LOSCACT_POS) + +#define CMU_CLKSR_HOSCACT_POS 0U +#define CMU_CLKSR_HOSCACT_MSK BIT(CMU_CLKSR_HOSCACT_POS) + +/****************** Bit definition for CMU_PLLCFG register ************************/ + +#define CMU_PLLCFG_PLL2LCKN_POS 17U +#define CMU_PLLCFG_PLL2LCKN_MSK BIT(CMU_PLLCFG_PLL2LCKN_POS) + +#define CMU_PLLCFG_PLL1LCKN_POS 16U +#define CMU_PLLCFG_PLL1LCKN_MSK BIT(CMU_PLLCFG_PLL1LCKN_POS) + +#define CMU_PLLCFG_PLL2RFS_POSS 8U +#define CMU_PLLCFG_PLL2RFS_POSE 9U +#define CMU_PLLCFG_PLL2RFS_MSK BITS(CMU_PLLCFG_PLL2RFS_POSS,CMU_PLLCFG_PLL2RFS_POSE) + +#define CMU_PLLCFG_PLL1OS_POS 4U +#define CMU_PLLCFG_PLL1OS_MSK BIT(CMU_PLLCFG_PLL1OS_POS) + +#define CMU_PLLCFG_PLL1RFS_POSS 0U +#define CMU_PLLCFG_PLL1RFS_POSE 2U +#define CMU_PLLCFG_PLL1RFS_MSK BITS(CMU_PLLCFG_PLL1RFS_POSS,CMU_PLLCFG_PLL1RFS_POSE) + +/****************** Bit definition for CMU_HOSCCFG register ************************/ + +#define CMU_HOSCCFG_FREQ_POSS 0U +#define CMU_HOSCCFG_FREQ_POSE 4U +#define CMU_HOSCCFG_FREQ_MSK BITS(CMU_HOSCCFG_FREQ_POSS,CMU_HOSCCFG_FREQ_POSE) + +/****************** Bit definition for CMU_HOSMCR register ************************/ + +#define CMU_HOSMCR_NMIE_POS 20U +#define CMU_HOSMCR_NMIE_MSK BIT(CMU_HOSMCR_NMIE_POS) + +#define CMU_HOSMCR_STPIF_POS 19U +#define CMU_HOSMCR_STPIF_MSK BIT(CMU_HOSMCR_STPIF_POS) + +#define CMU_HOSMCR_STRIF_POS 18U +#define CMU_HOSMCR_STRIF_MSK BIT(CMU_HOSMCR_STRIF_POS) + +#define CMU_HOSMCR_STPIE_POS 17U +#define CMU_HOSMCR_STPIE_MSK BIT(CMU_HOSMCR_STPIE_POS) + +#define CMU_HOSMCR_STRIE_POS 16U +#define CMU_HOSMCR_STRIE_MSK BIT(CMU_HOSMCR_STRIE_POS) + +#define CMU_HOSMCR_FRQS_POSS 8U +#define CMU_HOSMCR_FRQS_POSE 10U +#define CMU_HOSMCR_FRQS_MSK BITS(CMU_HOSMCR_FRQS_POSS,CMU_HOSMCR_FRQS_POSE) + +#define CMU_HOSMCR_CLKS_POS 1U +#define CMU_HOSMCR_CLKS_MSK BIT(CMU_HOSMCR_CLKS_POS) + +#define CMU_HOSMCR_EN_POS 0U +#define CMU_HOSMCR_EN_MSK BIT(CMU_HOSMCR_EN_POS) + +/****************** Bit definition for CMU_LOSMCR register ************************/ + +#define CMU_LOSMCR_NMIE_POS 20U +#define CMU_LOSMCR_NMIE_MSK BIT(CMU_LOSMCR_NMIE_POS) + +#define CMU_LOSMCR_STPIF_POS 19U +#define CMU_LOSMCR_STPIF_MSK BIT(CMU_LOSMCR_STPIF_POS) + +#define CMU_LOSMCR_STRIF_POS 18U +#define CMU_LOSMCR_STRIF_MSK BIT(CMU_LOSMCR_STRIF_POS) + +#define CMU_LOSMCR_STPIE_POS 17U +#define CMU_LOSMCR_STPIE_MSK BIT(CMU_LOSMCR_STPIE_POS) + +#define CMU_LOSMCR_STRIE_POS 16U +#define CMU_LOSMCR_STRIE_MSK BIT(CMU_LOSMCR_STRIE_POS) + +#define CMU_LOSMCR_CLKS_POS 1U +#define CMU_LOSMCR_CLKS_MSK BIT(CMU_LOSMCR_CLKS_POS) + +#define CMU_LOSMCR_EN_POS 0U +#define CMU_LOSMCR_EN_MSK BIT(CMU_LOSMCR_EN_POS) + +/****************** Bit definition for CMU_PULMCR register ************************/ + +#define CMU_PULMCR_NMIE_POS 20U +#define CMU_PULMCR_NMIE_MSK BIT(CMU_PULMCR_NMIE_POS) + +#define CMU_PULMCR_ULKIF_POS 19U +#define CMU_PULMCR_ULKIF_MSK BIT(CMU_PULMCR_ULKIF_POS) + +#define CMU_PULMCR_LCKIF_POS 18U +#define CMU_PULMCR_LCKIF_MSK BIT(CMU_PULMCR_LCKIF_POS) + +#define CMU_PULMCR_ULKIE_POS 17U +#define CMU_PULMCR_ULKIE_MSK BIT(CMU_PULMCR_ULKIE_POS) + +#define CMU_PULMCR_LCKIE_POS 16U +#define CMU_PULMCR_LCKIE_MSK BIT(CMU_PULMCR_LCKIE_POS) + +#define CMU_PULMCR_MODE_POSS 8U +#define CMU_PULMCR_MODE_POSE 9U +#define CMU_PULMCR_MODE_MSK BITS(CMU_PULMCR_MODE_POSS,CMU_PULMCR_MODE_POSE) + +#define CMU_PULMCR_CLKS_POS 1U +#define CMU_PULMCR_CLKS_MSK BIT(CMU_PULMCR_CLKS_POS) + +#define CMU_PULMCR_EN_POS 0U +#define CMU_PULMCR_EN_MSK BIT(CMU_PULMCR_EN_POS) + +/****************** Bit definition for CMU_CLKOCR register ************************/ + +#define CMU_CLKOCR_LSCOS_POSS 24U +#define CMU_CLKOCR_LSCOS_POSE 26U +#define CMU_CLKOCR_LSCOS_MSK BITS(CMU_CLKOCR_LSCOS_POSS,CMU_CLKOCR_LSCOS_POSE) + +#define CMU_CLKOCR_LSCOEN_POS 16U +#define CMU_CLKOCR_LSCOEN_MSK BIT(CMU_CLKOCR_LSCOEN_POS) + +#define CMU_CLKOCR_HSCODIV_POSS 12U +#define CMU_CLKOCR_HSCODIV_POSE 14U +#define CMU_CLKOCR_HSCODIV_MSK BITS(CMU_CLKOCR_HSCODIV_POSS,CMU_CLKOCR_HSCODIV_POSE) + +#define CMU_CLKOCR_HSCOS_POSS 8U +#define CMU_CLKOCR_HSCOS_POSE 10U +#define CMU_CLKOCR_HSCOS_MSK BITS(CMU_CLKOCR_HSCOS_POSS,CMU_CLKOCR_HSCOS_POSE) + +#define CMU_CLKOCR_HSCOEN_POS 0U +#define CMU_CLKOCR_HSCOEN_MSK BIT(CMU_CLKOCR_HSCOEN_POS) + +/****************** Bit definition for CMU_BUZZCR register ************************/ + +#define CMU_BUZZCR_DAT_POSS 16U +#define CMU_BUZZCR_DAT_POSE 31U +#define CMU_BUZZCR_DAT_MSK BITS(CMU_BUZZCR_DAT_POSS,CMU_BUZZCR_DAT_POSE) + +#define CMU_BUZZCR_DIV_POSS 8U +#define CMU_BUZZCR_DIV_POSE 10U +#define CMU_BUZZCR_DIV_MSK BITS(CMU_BUZZCR_DIV_POSS,CMU_BUZZCR_DIV_POSE) + +#define CMU_BUZZCR_EN_POS 0U +#define CMU_BUZZCR_EN_MSK BIT(CMU_BUZZCR_EN_POS) + +/****************** Bit definition for CMU_AHB1ENR register ************************/ + +#define CMU_AHB1ENR_PISEN_POS 5U +#define CMU_AHB1ENR_PISEN_MSK BIT(CMU_AHB1ENR_PISEN_POS) + +#define CMU_AHB1ENR_TRNGEN_POS 4U +#define CMU_AHB1ENR_TRNGEN_MSK BIT(CMU_AHB1ENR_TRNGEN_POS) + +#define CMU_AHB1ENR_CRYPTEN_POS 3U +#define CMU_AHB1ENR_CRYPTEN_MSK BIT(CMU_AHB1ENR_CRYPTEN_POS) + +#define CMU_AHB1ENR_CALCEN_POS 2U +#define CMU_AHB1ENR_CALCEN_MSK BIT(CMU_AHB1ENR_CALCEN_POS) + +#define CMU_AHB1ENR_CRCEN_POS 1U +#define CMU_AHB1ENR_CRCEN_MSK BIT(CMU_AHB1ENR_CRCEN_POS) + +#define CMU_AHB1ENR_GPIOEN_POS 0U +#define CMU_AHB1ENR_GPIOEN_MSK BIT(CMU_AHB1ENR_GPIOEN_POS) + +/****************** Bit definition for CMU_APB1ENR register ************************/ + +#define CMU_APB1ENR_CAN0EN_POS 24U +#define CMU_APB1ENR_CAN0EN_MSK BIT(CMU_APB1ENR_CAN0EN_POS) + +#define CMU_APB1ENR_I2C1EN_POS 21U +#define CMU_APB1ENR_I2C1EN_MSK BIT(CMU_APB1ENR_I2C1EN_POS) + +#define CMU_APB1ENR_I2C0EN_POS 20U +#define CMU_APB1ENR_I2C0EN_MSK BIT(CMU_APB1ENR_I2C0EN_POS) + +#define CMU_APB1ENR_SPI2EN_POS 18U +#define CMU_APB1ENR_SPI2EN_MSK BIT(CMU_APB1ENR_SPI2EN_POS) + +#define CMU_APB1ENR_SPI1EN_POS 17U +#define CMU_APB1ENR_SPI1EN_MSK BIT(CMU_APB1ENR_SPI1EN_POS) + +#define CMU_APB1ENR_SPI0EN_POS 16U +#define CMU_APB1ENR_SPI0EN_MSK BIT(CMU_APB1ENR_SPI0EN_POS) + +#define CMU_APB1ENR_USART1EN_POS 13U +#define CMU_APB1ENR_USART1EN_MSK BIT(CMU_APB1ENR_USART1EN_POS) + +#define CMU_APB1ENR_USART0EN_POS 12U +#define CMU_APB1ENR_USART0EN_MSK BIT(CMU_APB1ENR_USART0EN_POS) + +#define CMU_APB1ENR_UART3EN_POS 11U +#define CMU_APB1ENR_UART3EN_MSK BIT(CMU_APB1ENR_UART3EN_POS) + +#define CMU_APB1ENR_UART2EN_POS 10U +#define CMU_APB1ENR_UART2EN_MSK BIT(CMU_APB1ENR_UART2EN_POS) + +#define CMU_APB1ENR_UART1EN_POS 9U +#define CMU_APB1ENR_UART1EN_MSK BIT(CMU_APB1ENR_UART1EN_POS) + +#define CMU_APB1ENR_UART0EN_POS 8U +#define CMU_APB1ENR_UART0EN_MSK BIT(CMU_APB1ENR_UART0EN_POS) + +#define CMU_APB1ENR_TIM7EN_POS 7U +#define CMU_APB1ENR_TIM7EN_MSK BIT(CMU_APB1ENR_TIM7EN_POS) + +#define CMU_APB1ENR_TIM6EN_POS 6U +#define CMU_APB1ENR_TIM6EN_MSK BIT(CMU_APB1ENR_TIM6EN_POS) + +#define CMU_APB1ENR_TIM5EN_POS 5U +#define CMU_APB1ENR_TIM5EN_MSK BIT(CMU_APB1ENR_TIM5EN_POS) + +#define CMU_APB1ENR_TIM4EN_POS 4U +#define CMU_APB1ENR_TIM4EN_MSK BIT(CMU_APB1ENR_TIM4EN_POS) + +#define CMU_APB1ENR_TIM3EN_POS 3U +#define CMU_APB1ENR_TIM3EN_MSK BIT(CMU_APB1ENR_TIM3EN_POS) + +#define CMU_APB1ENR_TIM2EN_POS 2U +#define CMU_APB1ENR_TIM2EN_MSK BIT(CMU_APB1ENR_TIM2EN_POS) + +#define CMU_APB1ENR_TIM1EN_POS 1U +#define CMU_APB1ENR_TIM1EN_MSK BIT(CMU_APB1ENR_TIM1EN_POS) + +#define CMU_APB1ENR_TIM0EN_POS 0U +#define CMU_APB1ENR_TIM0EN_MSK BIT(CMU_APB1ENR_TIM0EN_POS) + +/****************** Bit definition for CMU_APB2ENR register ************************/ + +#define CMU_APB2ENR_DBGCEN_POS 19U +#define CMU_APB2ENR_DBGCEN_MSK BIT(CMU_APB2ENR_DBGCEN_POS) + +#define CMU_APB2ENR_BKPCEN_POS 17U +#define CMU_APB2ENR_BKPCEN_MSK BIT(CMU_APB2ENR_BKPCEN_POS) + +#define CMU_APB2ENR_TSENSEEN_POS 16U +#define CMU_APB2ENR_TSENSEEN_MSK BIT(CMU_APB2ENR_TSENSEEN_POS) + +#define CMU_APB2ENR_RTCEN_POS 15U +#define CMU_APB2ENR_RTCEN_MSK BIT(CMU_APB2ENR_RTCEN_POS) + +#define CMU_APB2ENR_IWDTEN_POS 14U +#define CMU_APB2ENR_IWDTEN_MSK BIT(CMU_APB2ENR_IWDTEN_POS) + +#define CMU_APB2ENR_LCDEN_POS 13U +#define CMU_APB2ENR_LCDEN_MSK BIT(CMU_APB2ENR_LCDEN_POS) + +#define CMU_APB2ENR_WWDTEN_POS 12U +#define CMU_APB2ENR_WWDTEN_MSK BIT(CMU_APB2ENR_WWDTEN_POS) + +#define CMU_APB2ENR_OPAMPEN_POS 8U +#define CMU_APB2ENR_OPAMPEN_MSK BIT(CMU_APB2ENR_OPAMPEN_POS) + +#define CMU_APB2ENR_ACMP1EN_POS 7U +#define CMU_APB2ENR_ACMP1EN_MSK BIT(CMU_APB2ENR_ACMP1EN_POS) + +#define CMU_APB2ENR_ACMP0EN_POS 6U +#define CMU_APB2ENR_ACMP0EN_MSK BIT(CMU_APB2ENR_ACMP0EN_POS) + +#define CMU_APB2ENR_ADC0EN_POS 4U +#define CMU_APB2ENR_ADC0EN_MSK BIT(CMU_APB2ENR_ADC0EN_POS) + +#define CMU_APB2ENR_LPUART0EN_POS 2U +#define CMU_APB2ENR_LPUART0EN_MSK BIT(CMU_APB2ENR_LPUART0EN_POS) + +#define CMU_APB2ENR_LPTIM0EN_POS 0U +#define CMU_APB2ENR_LPTIM0EN_MSK BIT(CMU_APB2ENR_LPTIM0EN_POS) + +/****************** Bit definition for CMU_LPENR register ************************/ + +#define CMU_LPENR_HOSCEN_POS 3U +#define CMU_LPENR_HOSCEN_MSK BIT(CMU_LPENR_HOSCEN_POS) + +#define CMU_LPENR_HRCEN_POS 2U +#define CMU_LPENR_HRCEN_MSK BIT(CMU_LPENR_HRCEN_POS) + +#define CMU_LPENR_LOSCEN_POS 1U +#define CMU_LPENR_LOSCEN_MSK BIT(CMU_LPENR_LOSCEN_POS) + +#define CMU_LPENR_LRCEN_POS 0U +#define CMU_LPENR_LRCEN_MSK BIT(CMU_LPENR_LRCEN_POS) + +/****************** Bit definition for CMU_PERICR register ************************/ + +#define CMU_PERICR_LCD_POSS 16U +#define CMU_PERICR_LCD_POSE 18U +#define CMU_PERICR_LCD_MSK BITS(CMU_PERICR_LCD_POSS,CMU_PERICR_LCD_POSE) + +#define CMU_PERICR_LPUART0_POSS 8U +#define CMU_PERICR_LPUART0_POSE 11U +#define CMU_PERICR_LPUART0_MSK BITS(CMU_PERICR_LPUART0_POSS,CMU_PERICR_LPUART0_POSE) + +#define CMU_PERICR_LPTIM0_POSS 0U +#define CMU_PERICR_LPTIM0_POSE 3U +#define CMU_PERICR_LPTIM0_MSK BITS(CMU_PERICR_LPTIM0_POSS,CMU_PERICR_LPTIM0_POSE) + +/****************** Bit definition for CMU_HRCACR register ************************/ + +#define CMU_HRCACR_IB_POSS 28U +#define CMU_HRCACR_IB_POSE 29U +#define CMU_HRCACR_IB_MSK BITS(CMU_HRCACR_IB_POSS,CMU_HRCACR_IB_POSE) + +#define CMU_HRCACR_CAP_POSS 26U +#define CMU_HRCACR_CAP_POSE 27U +#define CMU_HRCACR_CAP_MSK BITS(CMU_HRCACR_CAP_POSS,CMU_HRCACR_CAP_POSE) + +#define CMU_HRCACR_CAL_POSS 16U +#define CMU_HRCACR_CAL_POSE 25U +#define CMU_HRCACR_CAL_MSK BITS(CMU_HRCACR_CAL_POSS,CMU_HRCACR_CAL_POSE) + +#define CMU_HRCACR_IBSET_POSS 14U +#define CMU_HRCACR_IBSET_POSE 15U +#define CMU_HRCACR_IBSET_MSK BITS(CMU_HRCACR_IBSET_POSS,CMU_HRCACR_IBSET_POSE) + +#define CMU_HRCACR_CAPSET_POSS 12U +#define CMU_HRCACR_CAPSET_POSE 13U +#define CMU_HRCACR_CAPSET_MSK BITS(CMU_HRCACR_CAPSET_POSS,CMU_HRCACR_CAPSET_POSE) + +#define CMU_HRCACR_STA_POSS 9U +#define CMU_HRCACR_STA_POSE 10U +#define CMU_HRCACR_STA_MSK BITS(CMU_HRCACR_STA_POSS,CMU_HRCACR_STA_POSE) + +#define CMU_HRCACR_BUSY_POS 8U +#define CMU_HRCACR_BUSY_MSK BIT(CMU_HRCACR_BUSY_POS) + +#define CMU_HRCACR_WRTRG_POS 7U +#define CMU_HRCACR_WRTRG_MSK BIT(CMU_HRCACR_WRTRG_POS) + +#define CMU_HRCACR_AC_POSS 4U +#define CMU_HRCACR_AC_POSE 6U +#define CMU_HRCACR_AC_MSK BITS(CMU_HRCACR_AC_POSS,CMU_HRCACR_AC_POSE) + +#define CMU_HRCACR_IBS_POS 3U +#define CMU_HRCACR_IBS_MSK BIT(CMU_HRCACR_IBS_POS) + +#define CMU_HRCACR_RFSEL_POS 2U +#define CMU_HRCACR_RFSEL_MSK BIT(CMU_HRCACR_RFSEL_POS) + +#define CMU_HRCACR_FREQ_POS 1U +#define CMU_HRCACR_FREQ_MSK BIT(CMU_HRCACR_FREQ_POS) + +#define CMU_HRCACR_EN_POS 0U +#define CMU_HRCACR_EN_MSK BIT(CMU_HRCACR_EN_POS) + +typedef struct +{ + __O uint32_t CSR; + __IO uint32_t CFGR; + uint32_t RESERVED0[2] ; + __IO uint32_t CLKENR; + __I uint32_t CLKSR; + __IO uint32_t PLLCFG; + __IO uint32_t HOSCCFG; + __IO uint32_t HOSMCR; + __IO uint32_t LOSMCR; + __IO uint32_t PULMCR; + uint32_t RESERVED1 ; + __IO uint32_t CLKOCR; + __IO uint32_t BUZZCR; + uint32_t RESERVED2[2] ; + __IO uint32_t AHB1ENR; + uint32_t RESERVED3[3] ; + __IO uint32_t APB1ENR; + __IO uint32_t APB2ENR; + uint32_t RESERVED4[2] ; + __IO uint32_t LPENR; + uint32_t RESERVED5[7] ; + __IO uint32_t PERICR; + uint32_t RESERVED6[3] ; + __IO uint32_t HRCACR; +} CMU_TypeDef; + +/****************** Bit definition for DMA_STATUS register ************************/ + +#define DMA_STATUS_STATUS_POSS 4U +#define DMA_STATUS_STATUS_POSE 7U +#define DMA_STATUS_STATUS_MSK BITS(DMA_STATUS_STATUS_POSS,DMA_STATUS_STATUS_POSE) + +#define DMA_STATUS_MASTER_ENABLE_POS 0U +#define DMA_STATUS_MASTER_ENABLE_MSK BIT(DMA_STATUS_MASTER_ENABLE_POS) + +/****************** Bit definition for DMA_CFG register ************************/ + +#define DMA_CFG_CHNL_PROT_CTRL_POSS 5U +#define DMA_CFG_CHNL_PROT_CTRL_POSE 7U +#define DMA_CFG_CHNL_PROT_CTRL_MSK BITS(DMA_CFG_CHNL_PROT_CTRL_POSS,DMA_CFG_CHNL_PROT_CTRL_POSE) + +#define DMA_CFG_MASTER_ENABLE_POS 0U +#define DMA_CFG_MASTER_ENABLE_MSK BIT(DMA_CFG_MASTER_ENABLE_POS) + +/****************** Bit definition for DMA_CTRLBASE register ************************/ + +#define DMA_CTRLBASE_CTRL_BASE_PTR_POSS 9U +#define DMA_CTRLBASE_CTRL_BASE_PTR_POSE 31U +#define DMA_CTRLBASE_CTRL_BASE_PTR_MSK BITS(DMA_CTRLBASE_CTRL_BASE_PTR_POSS,DMA_CTRLBASE_CTRL_BASE_PTR_POSE) + +/****************** Bit definition for DMA_ALTCTRLBASE register ************************/ + +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS 0U +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE 31U +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_MSK BITS(DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS,DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE) + +/****************** Bit definition for DMA_CHWAITSTATUS register ************************/ + +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS 0U +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE 31U +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_MSK BITS(DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS,DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE) + +/****************** Bit definition for DMA_CHSWREQ register ************************/ + +#define DMA_CHSWREQ_CHSWREQ_POSS 0U +#define DMA_CHSWREQ_CHSWREQ_POSE 31U +#define DMA_CHSWREQ_CHSWREQ_MSK BITS(DMA_CHSWREQ_CHSWREQ_POSS,DMA_CHSWREQ_CHSWREQ_POSE) + +/****************** Bit definition for DMA_CHUSEBURSTSET register ************************/ + +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS 0U +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE 31U +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_MSK BITS(DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS,DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE) + +/****************** Bit definition for DMA_CHUSEBURSTCLR register ************************/ + +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS 0U +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE 31U +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_MSK BITS(DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS,DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE) + +/****************** Bit definition for DMA_CHREQMASKSET register ************************/ + +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS 0U +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE 31U +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_MSK BITS(DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS,DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE) + +/****************** Bit definition for DMA_CHREQMASKCLR register ************************/ + +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS 0U +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE 31U +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_MSK BITS(DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS,DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE) + +/****************** Bit definition for DMA_CHENSET register ************************/ + +#define DMA_CHENSET_CHNL_ENABLE_SET_POSS 0U +#define DMA_CHENSET_CHNL_ENABLE_SET_POSE 31U +#define DMA_CHENSET_CHNL_ENABLE_SET_MSK BITS(DMA_CHENSET_CHNL_ENABLE_SET_POSS,DMA_CHENSET_CHNL_ENABLE_SET_POSE) + +/****************** Bit definition for DMA_CHENCLR register ************************/ + +#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSS 0U +#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSE 31U +#define DMA_CHENCLR_CHNL_ENABLE_CLR_MSK BITS(DMA_CHENCLR_CHNL_ENABLE_CLR_POSS,DMA_CHENCLR_CHNL_ENABLE_CLR_POSE) + +/****************** Bit definition for DMA_CHPRIALTSET register ************************/ + +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS 0U +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE 31U +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_MSK BITS(DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS,DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE) + +/****************** Bit definition for DMA_CHPRIALTCLR register ************************/ + +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS 0U +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE 31U +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_MSK BITS(DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS,DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE) + +/****************** Bit definition for DMA_CHPRSET register ************************/ + +#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSS 0U +#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSE 31U +#define DMA_CHPRSET_CHNL_PRIORITY_SET_MSK BITS(DMA_CHPRSET_CHNL_PRIORITY_SET_POSS,DMA_CHPRSET_CHNL_PRIORITY_SET_POSE) + +/****************** Bit definition for DMA_CHPRCLR register ************************/ + +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS 0U +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE 31U +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_MSK BITS(DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS,DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE) + +/****************** Bit definition for DMA_ERRCLR register ************************/ + +#define DMA_ERRCLR_ERR_CLR_POS 0U +#define DMA_ERRCLR_ERR_CLR_MSK BIT(DMA_ERRCLR_ERR_CLR_POS) + +/****************** Bit definition for DMA_IFLAG register ************************/ + +#define DMA_IFLAG_DMAERRIF_POS 31U +#define DMA_IFLAG_DMAERRIF_MSK BIT(DMA_IFLAG_DMAERRIF_POS) + +#define DMA_IFLAG_CH5DONEIF_POS 5U +#define DMA_IFLAG_CH5DONEIF_MSK BIT(DMA_IFLAG_CH5DONEIF_POS) + +#define DMA_IFLAG_CH4DONEIF_POS 4U +#define DMA_IFLAG_CH4DONEIF_MSK BIT(DMA_IFLAG_CH4DONEIF_POS) + +#define DMA_IFLAG_CH3DONEIF_POS 3U +#define DMA_IFLAG_CH3DONEIF_MSK BIT(DMA_IFLAG_CH3DONEIF_POS) + +#define DMA_IFLAG_CH2DONEIF_POS 2U +#define DMA_IFLAG_CH2DONEIF_MSK BIT(DMA_IFLAG_CH2DONEIF_POS) + +#define DMA_IFLAG_CH1DONEIF_POS 1U +#define DMA_IFLAG_CH1DONEIF_MSK BIT(DMA_IFLAG_CH1DONEIF_POS) + +#define DMA_IFLAG_CH0DONEIF_POS 0U +#define DMA_IFLAG_CH0DONEIF_MSK BIT(DMA_IFLAG_CH0DONEIF_POS) + +/****************** Bit definition for DMA_ICFR register ************************/ + +#define DMA_ICFR_DMAERRC_POS 31U +#define DMA_ICFR_DMAERRC_MSK BIT(DMA_ICFR_DMAERRC_POS) + +#define DMA_ICFR_CH5DONEC_POS 5U +#define DMA_ICFR_CH5DONEC_MSK BIT(DMA_ICFR_CH5DONEC_POS) + +#define DMA_ICFR_CH4DONEC_POS 4U +#define DMA_ICFR_CH4DONEC_MSK BIT(DMA_ICFR_CH4DONEC_POS) + +#define DMA_ICFR_CH3DONEC_POS 3U +#define DMA_ICFR_CH3DONEC_MSK BIT(DMA_ICFR_CH3DONEC_POS) + +#define DMA_ICFR_CH2DONEC_POS 2U +#define DMA_ICFR_CH2DONEC_MSK BIT(DMA_ICFR_CH2DONEC_POS) + +#define DMA_ICFR_CH1DONEC_POS 1U +#define DMA_ICFR_CH1DONEC_MSK BIT(DMA_ICFR_CH1DONEC_POS) + +#define DMA_ICFR_CH0DONEC_POS 0U +#define DMA_ICFR_CH0DONEC_MSK BIT(DMA_ICFR_CH0DONEC_POS) + +/****************** Bit definition for DMA_IER register ************************/ + +#define DMA_IER_DMAERRIE_POS 31U +#define DMA_IER_DMAERRIE_MSK BIT(DMA_IER_DMAERRIE_POS) + +#define DMA_IER_CH5DONEIE_POS 5U +#define DMA_IER_CH5DONEIE_MSK BIT(DMA_IER_CH5DONEIE_POS) + +#define DMA_IER_CH4DONEIE_POS 4U +#define DMA_IER_CH4DONEIE_MSK BIT(DMA_IER_CH4DONEIE_POS) + +#define DMA_IER_CH3DONEIE_POS 3U +#define DMA_IER_CH3DONEIE_MSK BIT(DMA_IER_CH3DONEIE_POS) + +#define DMA_IER_CH2DONEIE_POS 2U +#define DMA_IER_CH2DONEIE_MSK BIT(DMA_IER_CH2DONEIE_POS) + +#define DMA_IER_CH1DONEIE_POS 1U +#define DMA_IER_CH1DONEIE_MSK BIT(DMA_IER_CH1DONEIE_POS) + +#define DMA_IER_CH0DONEIE_POS 0U +#define DMA_IER_CH0DONEIE_MSK BIT(DMA_IER_CH0DONEIE_POS) + +/****************** Bit definition for DMA_CH0_SELCON register ************************/ + +#define DMA_CH0_SELCON_MSEL_POSS 8U +#define DMA_CH0_SELCON_MSEL_POSE 13U +#define DMA_CH0_SELCON_MSEL_MSK BITS(DMA_CH0_SELCON_MSEL_POSS,DMA_CH0_SELCON_MSEL_POSE) + +#define DMA_CH0_SELCON_MSIGSEL_POSS 0U +#define DMA_CH0_SELCON_MSIGSEL_POSE 3U +#define DMA_CH0_SELCON_MSIGSEL_MSK BITS(DMA_CH0_SELCON_MSIGSEL_POSS,DMA_CH0_SELCON_MSIGSEL_POSE) + +typedef struct +{ + __I uint32_t STATUS; + __IO uint32_t CFG; + __IO uint32_t CTRLBASE; + __I uint32_t ALTCTRLBASE; + __I uint32_t CHWAITSTATUS; + __IO uint32_t CHSWREQ; + __IO uint32_t CHUSEBURSTSET; + __O uint32_t CHUSEBURSTCLR; + __IO uint32_t CHREQMASKSET; + __O uint32_t CHREQMASKCLR; + __IO uint32_t CHENSET; + __O uint32_t CHENCLR; + __IO uint32_t CHPRIALTSET; + __O uint32_t CHPRIALTCLR; + __IO uint32_t CHPRSET; + __O uint32_t CHPRCLR; + uint32_t RESERVED0[3] ; + __IO uint32_t ERRCLR; + uint32_t RESERVED1[1004] ; + __I uint32_t IFLAG; + uint32_t RESERVED2 ; + __O uint32_t ICFR; + __IO uint32_t IER; + uint32_t RESERVED3[60] ; + __IO uint32_t CH_SELCON[6]; +} DMA_TypeDef; + +/****************** Bit definition for PIS_CH0_CON register ************************/ + +#define PIS_CH0_CON_SYNCSEL_POSS 24U +#define PIS_CH0_CON_SYNCSEL_POSE 26U +#define PIS_CH0_CON_SYNCSEL_MSK BITS(PIS_CH0_CON_SYNCSEL_POSS,PIS_CH0_CON_SYNCSEL_POSE) + +#define PIS_CH0_CON_PULCK_POSS 18U +#define PIS_CH0_CON_PULCK_POSE 19U +#define PIS_CH0_CON_PULCK_MSK BITS(PIS_CH0_CON_PULCK_POSS,PIS_CH0_CON_PULCK_POSE) + +#define PIS_CH0_CON_EDGS_POSS 16U +#define PIS_CH0_CON_EDGS_POSE 17U +#define PIS_CH0_CON_EDGS_MSK BITS(PIS_CH0_CON_EDGS_POSS,PIS_CH0_CON_EDGS_POSE) + +#define PIS_CH0_CON_SRCS_POSS 8U +#define PIS_CH0_CON_SRCS_POSE 13U +#define PIS_CH0_CON_SRCS_MSK BITS(PIS_CH0_CON_SRCS_POSS,PIS_CH0_CON_SRCS_POSE) + +#define PIS_CH0_CON_MSIGS_POSS 0U +#define PIS_CH0_CON_MSIGS_POSE 3U +#define PIS_CH0_CON_MSIGS_MSK BITS(PIS_CH0_CON_MSIGS_POSS,PIS_CH0_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH_OER register ************************/ + +#define PIS_CH_OER_CH3OE_POS 3U +#define PIS_CH_OER_CH3OE_MSK BIT(PIS_CH_OER_CH3OE_POS) + +#define PIS_CH_OER_CH2OE_POS 2U +#define PIS_CH_OER_CH2OE_MSK BIT(PIS_CH_OER_CH2OE_POS) + +#define PIS_CH_OER_CH1OE_POS 1U +#define PIS_CH_OER_CH1OE_MSK BIT(PIS_CH_OER_CH1OE_POS) + +#define PIS_CH_OER_CH0OE_POS 0U +#define PIS_CH_OER_CH0OE_MSK BIT(PIS_CH_OER_CH0OE_POS) + +/****************** Bit definition for PIS_TAR_CON0 register ************************/ + +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_POS 25U +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_POS 24U +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_POS 17U +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_POS 16U +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_POS 4U +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_BRKIN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_POS 3U +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_POS 2U +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_POS 1U +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_POS 0U +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH1IN_SEL_POS) + +/****************** Bit definition for PIS_TAR_CON1 register ************************/ + +#define PIS_TAR_CON1_SPI1_CLK_SEL_POS 15U +#define PIS_TAR_CON1_SPI1_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI1_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI1_RX_SEL_POS 14U +#define PIS_TAR_CON1_SPI1_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI1_RX_SEL_POS) + +#define PIS_TAR_CON1_SPI0_CLK_SEL_POS 13U +#define PIS_TAR_CON1_SPI0_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI0_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI0_RX_SEL_POS 12U +#define PIS_TAR_CON1_SPI0_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI0_RX_SEL_POS) + +#define PIS_TAR_CON1_LPUART0_RXD_SEL_POS 8U +#define PIS_TAR_CON1_LPUART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_LPUART0_RXD_SEL_POS) + +#define PIS_TAR_CON1_USART1_RXD_SEL_POS 7U +#define PIS_TAR_CON1_USART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART1_RXD_SEL_POS) + +#define PIS_TAR_CON1_USART0_RXD_SEL_POS 6U +#define PIS_TAR_CON1_USART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART0_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART3_RXD_SEL_POS 3U +#define PIS_TAR_CON1_UART3_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART3_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART2_RXD_SEL_POS 2U +#define PIS_TAR_CON1_UART2_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART2_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART1_RXD_SEL_POS 1U +#define PIS_TAR_CON1_UART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART1_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART0_RXD_SEL_POS 0U +#define PIS_TAR_CON1_UART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART0_RXD_SEL_POS) + +/****************** Bit definition for PIS_TXMCR register ************************/ + +#define PIS_TXMCR_TXMLVLS_POS 8U +#define PIS_TXMCR_TXMLVLS_MSK BIT(PIS_TXMCR_TXMLVLS_POS) + +#define PIS_TXMCR_TXMSS_POSS 4U +#define PIS_TXMCR_TXMSS_POSE 7U +#define PIS_TXMCR_TXMSS_MSK BITS(PIS_TXMCR_TXMSS_POSS,PIS_TXMCR_TXMSS_POSE) + +#define PIS_TXMCR_TXSIGS_POSS 0U +#define PIS_TXMCR_TXSIGS_POSE 3U +#define PIS_TXMCR_TXSIGS_MSK BITS(PIS_TXMCR_TXSIGS_POSS,PIS_TXMCR_TXSIGS_POSE) + +typedef struct +{ + __IO uint32_t CH_CON[8]; + uint32_t RESERVED0[8] ; + __IO uint32_t CH_OER; + __IO uint32_t TAR_CON0; + __IO uint32_t TAR_CON1; + uint32_t RESERVED1[5] ; + __IO uint32_t UART0_TXMCR; + __IO uint32_t UART1_TXMCR; + __IO uint32_t UART2_TXMCR; + __IO uint32_t UART3_TXMCR; + __IO uint32_t LPUART0_TXMCR; +} PIS_TypeDef; + +/****************** Bit definition for GPIO_DIN register ************************/ + +#define GPIO_DIN_DIN_POSS 0U +#define GPIO_DIN_DIN_POSE 15U +#define GPIO_DIN_DIN_MSK BITS(GPIO_DIN_DIN_POSS,GPIO_DIN_DIN_POSE) + +/****************** Bit definition for GPIO_DOUT register ************************/ + +#define GPIO_DOUT_DOUT_POSS 0U +#define GPIO_DOUT_DOUT_POSE 15U +#define GPIO_DOUT_DOUT_MSK BITS(GPIO_DOUT_DOUT_POSS,GPIO_DOUT_DOUT_POSE) + +/****************** Bit definition for GPIO_BSRR register ************************/ + +#define GPIO_BSRR_BRR_POSS 16U +#define GPIO_BSRR_BRR_POSE 31U +#define GPIO_BSRR_BRR_MSK BITS(GPIO_BSRR_BRR_POSS,GPIO_BSRR_BRR_POSE) + +#define GPIO_BSRR_BSR_POSS 0U +#define GPIO_BSRR_BSR_POSE 15U +#define GPIO_BSRR_BSR_MSK BITS(GPIO_BSRR_BSR_POSS,GPIO_BSRR_BSR_POSE) + +/****************** Bit definition for GPIO_BIR register ************************/ + +#define GPIO_BIR_BIR_POSS 0U +#define GPIO_BIR_BIR_POSE 15U +#define GPIO_BIR_BIR_MSK BITS(GPIO_BIR_BIR_POSS,GPIO_BIR_BIR_POSE) + +/****************** Bit definition for GPIO_MODE register ************************/ + +#define GPIO_MODE_MODE_POSS 0U +#define GPIO_MODE_MODE_POSE 31U +#define GPIO_MODE_MODE_MSK BITS(GPIO_MODE_MODE_POSS,GPIO_MODE_MODE_POSE) + +/****************** Bit definition for GPIO_ODOS register ************************/ + +#define GPIO_ODOS_ODOS_POSS 0U +#define GPIO_ODOS_ODOS_POSE 31U +#define GPIO_ODOS_ODOS_MSK BITS(GPIO_ODOS_ODOS_POSS,GPIO_ODOS_ODOS_POSE) + +/****************** Bit definition for GPIO_PUPD register ************************/ + +#define GPIO_PUPD_PUPD_POSS 0U +#define GPIO_PUPD_PUPD_POSE 31U +#define GPIO_PUPD_PUPD_MSK BITS(GPIO_PUPD_PUPD_POSS,GPIO_PUPD_PUPD_POSE) + +/****************** Bit definition for GPIO_ODRV register ************************/ + +#define GPIO_ODRV_ODRV_POSS 0U +#define GPIO_ODRV_ODRV_POSE 31U +#define GPIO_ODRV_ODRV_MSK BITS(GPIO_ODRV_ODRV_POSS,GPIO_ODRV_ODRV_POSE) + +/****************** Bit definition for GPIO_FLT register ************************/ + +#define GPIO_FLT_FLT_POSS 0U +#define GPIO_FLT_FLT_POSE 15U +#define GPIO_FLT_FLT_MSK BITS(GPIO_FLT_FLT_POSS,GPIO_FLT_FLT_POSE) + +/****************** Bit definition for GPIO_TYPE register ************************/ + +#define GPIO_TYPE_TYPE_POSS 0U +#define GPIO_TYPE_TYPE_POSE 15U +#define GPIO_TYPE_TYPE_MSK BITS(GPIO_TYPE_TYPE_POSS,GPIO_TYPE_TYPE_POSE) + +/****************** Bit definition for GPIO_FUNC0 register ************************/ + +#define GPIO_FUNC0_FSEL_IO7_POSS 28U +#define GPIO_FUNC0_FSEL_IO7_POSE 31U +#define GPIO_FUNC0_FSEL_IO7_MSK BITS(GPIO_FUNC0_FSEL_IO7_POSS,GPIO_FUNC0_FSEL_IO7_POSE) + +#define GPIO_FUNC0_FSEL_IO6_POSS 24U +#define GPIO_FUNC0_FSEL_IO6_POSE 27U +#define GPIO_FUNC0_FSEL_IO6_MSK BITS(GPIO_FUNC0_FSEL_IO6_POSS,GPIO_FUNC0_FSEL_IO6_POSE) + +#define GPIO_FUNC0_FSEL_IO5_POSS 20U +#define GPIO_FUNC0_FSEL_IO5_POSE 23U +#define GPIO_FUNC0_FSEL_IO5_MSK BITS(GPIO_FUNC0_FSEL_IO5_POSS,GPIO_FUNC0_FSEL_IO5_POSE) + +#define GPIO_FUNC0_FSEL_IO4_POSS 16U +#define GPIO_FUNC0_FSEL_IO4_POSE 19U +#define GPIO_FUNC0_FSEL_IO4_MSK BITS(GPIO_FUNC0_FSEL_IO4_POSS,GPIO_FUNC0_FSEL_IO4_POSE) + +#define GPIO_FUNC0_FSEL_IO3_POSS 12U +#define GPIO_FUNC0_FSEL_IO3_POSE 15U +#define GPIO_FUNC0_FSEL_IO3_MSK BITS(GPIO_FUNC0_FSEL_IO3_POSS,GPIO_FUNC0_FSEL_IO3_POSE) + +#define GPIO_FUNC0_FSEL_IO2_POSS 8U +#define GPIO_FUNC0_FSEL_IO2_POSE 11U +#define GPIO_FUNC0_FSEL_IO2_MSK BITS(GPIO_FUNC0_FSEL_IO2_POSS,GPIO_FUNC0_FSEL_IO2_POSE) + +#define GPIO_FUNC0_FSEL_IO1_POSS 4U +#define GPIO_FUNC0_FSEL_IO1_POSE 7U +#define GPIO_FUNC0_FSEL_IO1_MSK BITS(GPIO_FUNC0_FSEL_IO1_POSS,GPIO_FUNC0_FSEL_IO1_POSE) + +#define GPIO_FUNC0_FSEL_IO0_POSS 0U +#define GPIO_FUNC0_FSEL_IO0_POSE 3U +#define GPIO_FUNC0_FSEL_IO0_MSK BITS(GPIO_FUNC0_FSEL_IO0_POSS,GPIO_FUNC0_FSEL_IO0_POSE) + +/****************** Bit definition for GPIO_FUNC1 register ************************/ + +#define GPIO_FUNC1_FSEL_IO15_POSS 28U +#define GPIO_FUNC1_FSEL_IO15_POSE 31U +#define GPIO_FUNC1_FSEL_IO15_MSK BITS(GPIO_FUNC1_FSEL_IO15_POSS,GPIO_FUNC1_FSEL_IO15_POSE) + +#define GPIO_FUNC1_FSEL_IO14_POSS 24U +#define GPIO_FUNC1_FSEL_IO14_POSE 27U +#define GPIO_FUNC1_FSEL_IO14_MSK BITS(GPIO_FUNC1_FSEL_IO14_POSS,GPIO_FUNC1_FSEL_IO14_POSE) + +#define GPIO_FUNC1_FSEL_IO13_POSS 20U +#define GPIO_FUNC1_FSEL_IO13_POSE 23U +#define GPIO_FUNC1_FSEL_IO13_MSK BITS(GPIO_FUNC1_FSEL_IO13_POSS,GPIO_FUNC1_FSEL_IO13_POSE) + +#define GPIO_FUNC1_FSEL_IO12_POSS 16U +#define GPIO_FUNC1_FSEL_IO12_POSE 19U +#define GPIO_FUNC1_FSEL_IO12_MSK BITS(GPIO_FUNC1_FSEL_IO12_POSS,GPIO_FUNC1_FSEL_IO12_POSE) + +#define GPIO_FUNC1_FSEL_IO11_POSS 12U +#define GPIO_FUNC1_FSEL_IO11_POSE 15U +#define GPIO_FUNC1_FSEL_IO11_MSK BITS(GPIO_FUNC1_FSEL_IO11_POSS,GPIO_FUNC1_FSEL_IO11_POSE) + +#define GPIO_FUNC1_FSEL_IO10_POSS 8U +#define GPIO_FUNC1_FSEL_IO10_POSE 11U +#define GPIO_FUNC1_FSEL_IO10_MSK BITS(GPIO_FUNC1_FSEL_IO10_POSS,GPIO_FUNC1_FSEL_IO10_POSE) + +#define GPIO_FUNC1_FSEL_IO9_POSS 4U +#define GPIO_FUNC1_FSEL_IO9_POSE 7U +#define GPIO_FUNC1_FSEL_IO9_MSK BITS(GPIO_FUNC1_FSEL_IO9_POSS,GPIO_FUNC1_FSEL_IO9_POSE) + +#define GPIO_FUNC1_FSEL_IO8_POSS 0U +#define GPIO_FUNC1_FSEL_IO8_POSE 3U +#define GPIO_FUNC1_FSEL_IO8_MSK BITS(GPIO_FUNC1_FSEL_IO8_POSS,GPIO_FUNC1_FSEL_IO8_POSE) + +/****************** Bit definition for GPIO_LOCK register ************************/ + +#define GPIO_LOCK_KEY_POSS 16U +#define GPIO_LOCK_KEY_POSE 31U +#define GPIO_LOCK_KEY_MSK BITS(GPIO_LOCK_KEY_POSS,GPIO_LOCK_KEY_POSE) + +#define GPIO_LOCK_LOCK_POSS 0U +#define GPIO_LOCK_LOCK_POSE 15U +#define GPIO_LOCK_LOCK_MSK BITS(GPIO_LOCK_LOCK_POSS,GPIO_LOCK_LOCK_POSE) + +typedef struct +{ + __I uint32_t DIN; + __IO uint32_t DOUT; + __O uint32_t BSRR; + __O uint32_t BIR; + __IO uint32_t MODE; + __IO uint32_t ODOS; + __IO uint32_t PUPD; + __IO uint32_t ODRV; + __IO uint32_t FLT; + __IO uint32_t TYPE; + __IO uint32_t FUNC0; + __IO uint32_t FUNC1; + __IO uint32_t LOCK; +} GPIO_TypeDef; + +/****************** Bit definition for GPIO_EXTIRER register ************************/ + +#define GPIO_EXTIRER_EXTIRER_POSS 0U +#define GPIO_EXTIRER_EXTIRER_POSE 15U +#define GPIO_EXTIRER_EXTIRER_MSK BITS(GPIO_EXTIRER_EXTIRER_POSS,GPIO_EXTIRER_EXTIRER_POSE) + +/****************** Bit definition for GPIO_EXTIFER register ************************/ + +#define GPIO_EXTIFER_EXTIFER_POSS 0U +#define GPIO_EXTIFER_EXTIFER_POSE 15U +#define GPIO_EXTIFER_EXTIFER_MSK BITS(GPIO_EXTIFER_EXTIFER_POSS,GPIO_EXTIFER_EXTIFER_POSE) + +/****************** Bit definition for GPIO_EXTIEN register ************************/ + +#define GPIO_EXTIEN_EXTIEN_POSS 0U +#define GPIO_EXTIEN_EXTIEN_POSE 15U +#define GPIO_EXTIEN_EXTIEN_MSK BITS(GPIO_EXTIEN_EXTIEN_POSS,GPIO_EXTIEN_EXTIEN_POSE) + +/****************** Bit definition for GPIO_EXTIFLAG register ************************/ + +#define GPIO_EXTIFLAG_EXTIFLAG_POSS 0U +#define GPIO_EXTIFLAG_EXTIFLAG_POSE 15U +#define GPIO_EXTIFLAG_EXTIFLAG_MSK BITS(GPIO_EXTIFLAG_EXTIFLAG_POSS,GPIO_EXTIFLAG_EXTIFLAG_POSE) + +/****************** Bit definition for GPIO_EXTISFR register ************************/ + +#define GPIO_EXTISFR_EXTISFR_POSS 0U +#define GPIO_EXTISFR_EXTISFR_POSE 15U +#define GPIO_EXTISFR_EXTISFR_MSK BITS(GPIO_EXTISFR_EXTISFR_POSS,GPIO_EXTISFR_EXTISFR_POSE) + +/****************** Bit definition for GPIO_EXTICFR register ************************/ + +#define GPIO_EXTICFR_EXTICFR_POSS 0U +#define GPIO_EXTICFR_EXTICFR_POSE 15U +#define GPIO_EXTICFR_EXTICFR_MSK BITS(GPIO_EXTICFR_EXTICFR_POSS,GPIO_EXTICFR_EXTICFR_POSE) + +/****************** Bit definition for GPIO_EXTIPSR0 register ************************/ + +#define GPIO_EXTIPSR0_EXTIS7_POSS 28U +#define GPIO_EXTIPSR0_EXTIS7_POSE 30U +#define GPIO_EXTIPSR0_EXTIS7_MSK BITS(GPIO_EXTIPSR0_EXTIS7_POSS,GPIO_EXTIPSR0_EXTIS7_POSE) + +#define GPIO_EXTIPSR0_EXTIS6_POSS 24U +#define GPIO_EXTIPSR0_EXTIS6_POSE 26U +#define GPIO_EXTIPSR0_EXTIS6_MSK BITS(GPIO_EXTIPSR0_EXTIS6_POSS,GPIO_EXTIPSR0_EXTIS6_POSE) + +#define GPIO_EXTIPSR0_EXTIS5_POSS 20U +#define GPIO_EXTIPSR0_EXTIS5_POSE 22U +#define GPIO_EXTIPSR0_EXTIS5_MSK BITS(GPIO_EXTIPSR0_EXTIS5_POSS,GPIO_EXTIPSR0_EXTIS5_POSE) + +#define GPIO_EXTIPSR0_EXTIS4_POSS 16U +#define GPIO_EXTIPSR0_EXTIS4_POSE 18U +#define GPIO_EXTIPSR0_EXTIS4_MSK BITS(GPIO_EXTIPSR0_EXTIS4_POSS,GPIO_EXTIPSR0_EXTIS4_POSE) + +#define GPIO_EXTIPSR0_EXTIS3_POSS 12U +#define GPIO_EXTIPSR0_EXTIS3_POSE 14U +#define GPIO_EXTIPSR0_EXTIS3_MSK BITS(GPIO_EXTIPSR0_EXTIS3_POSS,GPIO_EXTIPSR0_EXTIS3_POSE) + +#define GPIO_EXTIPSR0_EXTIS2_POSS 8U +#define GPIO_EXTIPSR0_EXTIS2_POSE 10U +#define GPIO_EXTIPSR0_EXTIS2_MSK BITS(GPIO_EXTIPSR0_EXTIS2_POSS,GPIO_EXTIPSR0_EXTIS2_POSE) + +#define GPIO_EXTIPSR0_EXTIS1_POSS 4U +#define GPIO_EXTIPSR0_EXTIS1_POSE 6U +#define GPIO_EXTIPSR0_EXTIS1_MSK BITS(GPIO_EXTIPSR0_EXTIS1_POSS,GPIO_EXTIPSR0_EXTIS1_POSE) + +#define GPIO_EXTIPSR0_EXTIS0_POSS 0U +#define GPIO_EXTIPSR0_EXTIS0_POSE 2U +#define GPIO_EXTIPSR0_EXTIS0_MSK BITS(GPIO_EXTIPSR0_EXTIS0_POSS,GPIO_EXTIPSR0_EXTIS0_POSE) + +/****************** Bit definition for GPIO_EXTIPSR1 register ************************/ + +#define GPIO_EXTIPSR1_EXTIS15_POSS 28U +#define GPIO_EXTIPSR1_EXTIS15_POSE 30U +#define GPIO_EXTIPSR1_EXTIS15_MSK BITS(GPIO_EXTIPSR1_EXTIS15_POSS,GPIO_EXTIPSR1_EXTIS15_POSE) + +#define GPIO_EXTIPSR1_EXTIS14_POSS 24U +#define GPIO_EXTIPSR1_EXTIS14_POSE 26U +#define GPIO_EXTIPSR1_EXTIS14_MSK BITS(GPIO_EXTIPSR1_EXTIS14_POSS,GPIO_EXTIPSR1_EXTIS14_POSE) + +#define GPIO_EXTIPSR1_EXTIS13_POSS 20U +#define GPIO_EXTIPSR1_EXTIS13_POSE 22U +#define GPIO_EXTIPSR1_EXTIS13_MSK BITS(GPIO_EXTIPSR1_EXTIS13_POSS,GPIO_EXTIPSR1_EXTIS13_POSE) + +#define GPIO_EXTIPSR1_EXTIS12_POSS 16U +#define GPIO_EXTIPSR1_EXTIS12_POSE 18U +#define GPIO_EXTIPSR1_EXTIS12_MSK BITS(GPIO_EXTIPSR1_EXTIS12_POSS,GPIO_EXTIPSR1_EXTIS12_POSE) + +#define GPIO_EXTIPSR1_EXTIS11_POSS 12U +#define GPIO_EXTIPSR1_EXTIS11_POSE 14U +#define GPIO_EXTIPSR1_EXTIS11_MSK BITS(GPIO_EXTIPSR1_EXTIS11_POSS,GPIO_EXTIPSR1_EXTIS11_POSE) + +#define GPIO_EXTIPSR1_EXTIS10_POSS 8U +#define GPIO_EXTIPSR1_EXTIS10_POSE 10U +#define GPIO_EXTIPSR1_EXTIS10_MSK BITS(GPIO_EXTIPSR1_EXTIS10_POSS,GPIO_EXTIPSR1_EXTIS10_POSE) + +#define GPIO_EXTIPSR1_EXTIS9_POSS 4U +#define GPIO_EXTIPSR1_EXTIS9_POSE 6U +#define GPIO_EXTIPSR1_EXTIS9_MSK BITS(GPIO_EXTIPSR1_EXTIS9_POSS,GPIO_EXTIPSR1_EXTIS9_POSE) + +#define GPIO_EXTIPSR1_EXTIS8_POSS 0U +#define GPIO_EXTIPSR1_EXTIS8_POSE 2U +#define GPIO_EXTIPSR1_EXTIS8_MSK BITS(GPIO_EXTIPSR1_EXTIS8_POSS,GPIO_EXTIPSR1_EXTIS8_POSE) + +/****************** Bit definition for GPIO_EXTIFLTCR register ************************/ + +#define GPIO_EXTIFLTCR_FLTCKS_POSS 24U +#define GPIO_EXTIFLTCR_FLTCKS_POSE 25U +#define GPIO_EXTIFLTCR_FLTCKS_MSK BITS(GPIO_EXTIFLTCR_FLTCKS_POSS,GPIO_EXTIFLTCR_FLTCKS_POSE) + +#define GPIO_EXTIFLTCR_FLTSEL_POSS 16U +#define GPIO_EXTIFLTCR_FLTSEL_POSE 23U +#define GPIO_EXTIFLTCR_FLTSEL_MSK BITS(GPIO_EXTIFLTCR_FLTSEL_POSS,GPIO_EXTIFLTCR_FLTSEL_POSE) + +#define GPIO_EXTIFLTCR_FLTEN_POSS 0U +#define GPIO_EXTIFLTCR_FLTEN_POSE 15U +#define GPIO_EXTIFLTCR_FLTEN_MSK BITS(GPIO_EXTIFLTCR_FLTEN_POSS,GPIO_EXTIFLTCR_FLTEN_POSE) + +typedef struct +{ + __IO uint32_t EXTIRER; + uint32_t RESERVED0 ; + __IO uint32_t EXTIFER; + uint32_t RESERVED1 ; + __IO uint32_t EXTIEN; + uint32_t RESERVED2 ; + __I uint32_t EXTIFLAG; + uint32_t RESERVED3 ; + __O uint32_t EXTISFR; + uint32_t RESERVED4 ; + __O uint32_t EXTICFR; + uint32_t RESERVED5 ; + __IO uint32_t EXTIPSR0; + __IO uint32_t EXTIPSR1; + uint32_t RESERVED6[2] ; + __IO uint32_t EXTIFLTCR; +} EXTI_TypeDef; + +/****************** Bit definition for RTC_WPR register ************************/ + +#define RTC_WPR_WP_POS 0U +#define RTC_WPR_WP_MSK BIT(RTC_WPR_WP_POS) + +/****************** Bit definition for RTC_CON register ************************/ + +#define RTC_CON_SSEC_POS 25U +#define RTC_CON_SSEC_MSK BIT(RTC_CON_SSEC_POS) + +#define RTC_CON_BUSY_POS 24U +#define RTC_CON_BUSY_MSK BIT(RTC_CON_BUSY_POS) + +#define RTC_CON_POL_POS 22U +#define RTC_CON_POL_MSK BIT(RTC_CON_POL_POS) + +#define RTC_CON_EOS_POSS 20U +#define RTC_CON_EOS_POSE 21U +#define RTC_CON_EOS_MSK BITS(RTC_CON_EOS_POSS,RTC_CON_EOS_POSE) + +#define RTC_CON_CKOS_POSS 17U +#define RTC_CON_CKOS_POSE 19U +#define RTC_CON_CKOS_MSK BITS(RTC_CON_CKOS_POSS,RTC_CON_CKOS_POSE) + +#define RTC_CON_CKOE_POS 16U +#define RTC_CON_CKOE_MSK BIT(RTC_CON_CKOE_POS) + +#define RTC_CON_WUCKS_POSS 13U +#define RTC_CON_WUCKS_POSE 15U +#define RTC_CON_WUCKS_MSK BITS(RTC_CON_WUCKS_POSS,RTC_CON_WUCKS_POSE) + +#define RTC_CON_WUTE_POS 12U +#define RTC_CON_WUTE_MSK BIT(RTC_CON_WUTE_POS) + +#define RTC_CON_DSTS_POS 10U +#define RTC_CON_DSTS_MSK BIT(RTC_CON_DSTS_POS) + +#define RTC_CON_SUB1H_POS 9U +#define RTC_CON_SUB1H_MSK BIT(RTC_CON_SUB1H_POS) + +#define RTC_CON_ADD1H_POS 8U +#define RTC_CON_ADD1H_MSK BIT(RTC_CON_ADD1H_POS) + +#define RTC_CON_TSPIN_POS 7U +#define RTC_CON_TSPIN_MSK BIT(RTC_CON_TSPIN_POS) + +#define RTC_CON_TSSEL_POS 6U +#define RTC_CON_TSSEL_MSK BIT(RTC_CON_TSSEL_POS) + +#define RTC_CON_TSEN_POS 5U +#define RTC_CON_TSEN_MSK BIT(RTC_CON_TSEN_POS) + +#define RTC_CON_SHDBP_POS 4U +#define RTC_CON_SHDBP_MSK BIT(RTC_CON_SHDBP_POS) + +#define RTC_CON_HFM_POS 3U +#define RTC_CON_HFM_MSK BIT(RTC_CON_HFM_POS) + +#define RTC_CON_ALMBEN_POS 2U +#define RTC_CON_ALMBEN_MSK BIT(RTC_CON_ALMBEN_POS) + +#define RTC_CON_ALMAEN_POS 1U +#define RTC_CON_ALMAEN_MSK BIT(RTC_CON_ALMAEN_POS) + +#define RTC_CON_GO_POS 0U +#define RTC_CON_GO_MSK BIT(RTC_CON_GO_POS) + +/****************** Bit definition for RTC_PSR register ************************/ + +#define RTC_PSR_APRS_POSS 16U +#define RTC_PSR_APRS_POSE 22U +#define RTC_PSR_APRS_MSK BITS(RTC_PSR_APRS_POSS,RTC_PSR_APRS_POSE) + +#define RTC_PSR_SPRS_POSS 0U +#define RTC_PSR_SPRS_POSE 14U +#define RTC_PSR_SPRS_MSK BITS(RTC_PSR_SPRS_POSS,RTC_PSR_SPRS_POSE) + +/****************** Bit definition for RTC_TAMPCON register ************************/ + +#define RTC_TAMPCON_TAMPFLT_POSS 20U +#define RTC_TAMPCON_TAMPFLT_POSE 21U +#define RTC_TAMPCON_TAMPFLT_MSK BITS(RTC_TAMPCON_TAMPFLT_POSS,RTC_TAMPCON_TAMPFLT_POSE) + +#define RTC_TAMPCON_TAMPCKS_POSS 17U +#define RTC_TAMPCON_TAMPCKS_POSE 19U +#define RTC_TAMPCON_TAMPCKS_MSK BITS(RTC_TAMPCON_TAMPCKS_POSS,RTC_TAMPCON_TAMPCKS_POSE) + +#define RTC_TAMPCON_TAMPTS_POS 16U +#define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS) + +#define RTC_TAMPCON_TAMP2LV_POS 9U +#define RTC_TAMPCON_TAMP2LV_MSK BIT(RTC_TAMPCON_TAMP2LV_POS) + +#define RTC_TAMPCON_TAMP2EN_POS 8U +#define RTC_TAMPCON_TAMP2EN_MSK BIT(RTC_TAMPCON_TAMP2EN_POS) + +#define RTC_TAMPCON_TAMP1LV_POS 1U +#define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS) + +#define RTC_TAMPCON_TAMP1EN_POS 0U +#define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS) + +/****************** Bit definition for RTC_TIME register ************************/ + +#define RTC_TIME_PM_POS 22U +#define RTC_TIME_PM_MSK BIT(RTC_TIME_PM_POS) + +#define RTC_TIME_HRT_POSS 20U +#define RTC_TIME_HRT_POSE 21U +#define RTC_TIME_HRT_MSK BITS(RTC_TIME_HRT_POSS,RTC_TIME_HRT_POSE) + +#define RTC_TIME_HRU_POSS 16U +#define RTC_TIME_HRU_POSE 19U +#define RTC_TIME_HRU_MSK BITS(RTC_TIME_HRU_POSS,RTC_TIME_HRU_POSE) + +#define RTC_TIME_MINT_POSS 12U +#define RTC_TIME_MINT_POSE 14U +#define RTC_TIME_MINT_MSK BITS(RTC_TIME_MINT_POSS,RTC_TIME_MINT_POSE) + +#define RTC_TIME_MINU_POSS 8U +#define RTC_TIME_MINU_POSE 11U +#define RTC_TIME_MINU_MSK BITS(RTC_TIME_MINU_POSS,RTC_TIME_MINU_POSE) + +#define RTC_TIME_SECT_POSS 4U +#define RTC_TIME_SECT_POSE 6U +#define RTC_TIME_SECT_MSK BITS(RTC_TIME_SECT_POSS,RTC_TIME_SECT_POSE) + +#define RTC_TIME_SECU_POSS 0U +#define RTC_TIME_SECU_POSE 3U +#define RTC_TIME_SECU_MSK BITS(RTC_TIME_SECU_POSS,RTC_TIME_SECU_POSE) + +/****************** Bit definition for RTC_DATE register ************************/ + +#define RTC_DATE_WD_POSS 24U +#define RTC_DATE_WD_POSE 26U +#define RTC_DATE_WD_MSK BITS(RTC_DATE_WD_POSS,RTC_DATE_WD_POSE) + +#define RTC_DATE_YRT_POSS 20U +#define RTC_DATE_YRT_POSE 23U +#define RTC_DATE_YRT_MSK BITS(RTC_DATE_YRT_POSS,RTC_DATE_YRT_POSE) + +#define RTC_DATE_YRU_POSS 16U +#define RTC_DATE_YRU_POSE 19U +#define RTC_DATE_YRU_MSK BITS(RTC_DATE_YRU_POSS,RTC_DATE_YRU_POSE) + +#define RTC_DATE_MONT_POS 12U +#define RTC_DATE_MONT_MSK BIT(RTC_DATE_MONT_POS) + +#define RTC_DATE_MONU_POSS 8U +#define RTC_DATE_MONU_POSE 11U +#define RTC_DATE_MONU_MSK BITS(RTC_DATE_MONU_POSS,RTC_DATE_MONU_POSE) + +#define RTC_DATE_DAYT_POSS 4U +#define RTC_DATE_DAYT_POSE 5U +#define RTC_DATE_DAYT_MSK BITS(RTC_DATE_DAYT_POSS,RTC_DATE_DAYT_POSE) + +#define RTC_DATE_DAYU_POSS 0U +#define RTC_DATE_DAYU_POSE 3U +#define RTC_DATE_DAYU_MSK BITS(RTC_DATE_DAYU_POSS,RTC_DATE_DAYU_POSE) + +/****************** Bit definition for RTC_SSEC register ************************/ + +#define RTC_SSEC_VAL_POSS 0U +#define RTC_SSEC_VAL_POSE 15U +#define RTC_SSEC_VAL_MSK BITS(RTC_SSEC_VAL_POSS,RTC_SSEC_VAL_POSE) + +/****************** Bit definition for RTC_WUMAT register ************************/ + +#define RTC_WUMAT_VAL_POSS 0U +#define RTC_WUMAT_VAL_POSE 15U +#define RTC_WUMAT_VAL_MSK BITS(RTC_WUMAT_VAL_POSS,RTC_WUMAT_VAL_POSE) + +/****************** Bit definition for RTC_ALMA register ************************/ + +#define RTC_ALMA_WDS_POS 31U +#define RTC_ALMA_WDS_MSK BIT(RTC_ALMA_WDS_POS) + +#define RTC_ALMA_DAWD_POSS 24U +#define RTC_ALMA_DAWD_POSE 30U +#define RTC_ALMA_DAWD_MSK BITS(RTC_ALMA_DAWD_POSS,RTC_ALMA_DAWD_POSE) + +#define RTC_ALMA_DAYMSK_POS 30U +#define RTC_ALMA_DAYMSK_MSK BIT(RTC_ALMA_DAYMSK_POS) + +#define RTC_ALMA_DAWD_DAYT_POSS 28U +#define RTC_ALMA_DAWD_DAYT_POSE 29U +#define RTC_ALMA_DAWD_DAYT_MSK BITS(RTC_ALMA_DAWD_DAYT_POSS, RTC_ALMA_DAWD_DAYT_POSE) + +#define RTC_ALMA_DAWD_DAYU_POSS 24U +#define RTC_ALMA_DAWD_DAYU_POSE 27U +#define RTC_ALMA_DAWD_DAYU_MSK BITS(RTC_ALMA_DAWD_DAYU_POSS, RTC_ALMA_DAWD_DAYU_POSE) + +#define RTC_ALMA_HRMSK_POS 23U +#define RTC_ALMA_HRMSK_MSK BIT(RTC_ALMA_HRMSK_POS) + +#define RTC_ALMA_PM_POS 22U +#define RTC_ALMA_PM_MSK BIT(RTC_ALMA_PM_POS) + +#define RTC_ALMA_HRT_POSS 20U +#define RTC_ALMA_HRT_POSE 21U +#define RTC_ALMA_HRT_MSK BITS(RTC_ALMA_HRT_POSS,RTC_ALMA_HRT_POSE) + +#define RTC_ALMA_HRU_POSS 16U +#define RTC_ALMA_HRU_POSE 19U +#define RTC_ALMA_HRU_MSK BITS(RTC_ALMA_HRU_POSS,RTC_ALMA_HRU_POSE) + +#define RTC_ALMA_MINMSK_POS 15U +#define RTC_ALMA_MINMSK_MSK BIT(RTC_ALMA_MINMSK_POS) + +#define RTC_ALMA_MINT_POSS 12U +#define RTC_ALMA_MINT_POSE 14U +#define RTC_ALMA_MINT_MSK BITS(RTC_ALMA_MINT_POSS,RTC_ALMA_MINT_POSE) + +#define RTC_ALMA_MINU_POSS 8U +#define RTC_ALMA_MINU_POSE 11U +#define RTC_ALMA_MINU_MSK BITS(RTC_ALMA_MINU_POSS,RTC_ALMA_MINU_POSE) + +#define RTC_ALMA_SECMSK_POS 7U +#define RTC_ALMA_SECMSK_MSK BIT(RTC_ALMA_SECMSK_POS) + +#define RTC_ALMA_SECT_POSS 4U +#define RTC_ALMA_SECT_POSE 6U +#define RTC_ALMA_SECT_MSK BITS(RTC_ALMA_SECT_POSS,RTC_ALMA_SECT_POSE) + +#define RTC_ALMA_SECU_POSS 0U +#define RTC_ALMA_SECU_POSE 3U +#define RTC_ALMA_SECU_MSK BITS(RTC_ALMA_SECU_POSS,RTC_ALMA_SECU_POSE) + +/****************** Bit definition for RTC_ALMB register ************************/ + +#define RTC_ALMB_WDS_POS 31U +#define RTC_ALMB_WDS_MSK BIT(RTC_ALMB_WDS_POS) + +#define RTC_ALMB_DAWD_POSS 24U +#define RTC_ALMB_DAWD_POSE 30U +#define RTC_ALMB_DAWD_MSK BITS(RTC_ALMB_DAWD_POSS,RTC_ALMB_DAWD_POSE) + +#define RTC_ALMB_DAYMSK_POS 30U +#define RTC_ALMB_DAYMSK_MSK BIT(RTC_ALMB_DAYMSK_POS) + +#define RTC_ALMB_DAWD_DAYT_POSS 28U +#define RTC_ALMB_DAWD_DAYT_POSE 29U +#define RTC_ALMB_DAWD_DAYT_MSK BITS(RTC_ALMB_DAWD_DAYT_POSS, RTC_ALMB_DAWD_DAYT_POSE) + +#define RTC_ALMB_DAWD_DAYU_POSS 24U +#define RTC_ALMB_DAWD_DAYU_POSE 27U +#define RTC_ALMB_DAWD_DAYU_MSK BITS(RTC_ALMB_DAWD_DAYU_POSS, RTC_ALMB_DAWD_DAYU_POSE) + +#define RTC_ALMB_HRMSK_POS 23U +#define RTC_ALMB_HRMSK_MSK BIT(RTC_ALMB_HRMSK_POS) + +#define RTC_ALMB_PM_POS 22U +#define RTC_ALMB_PM_MSK BIT(RTC_ALMB_PM_POS) + +#define RTC_ALMB_HRT_POSS 20U +#define RTC_ALMB_HRT_POSE 21U +#define RTC_ALMB_HRT_MSK BITS(RTC_ALMB_HRT_POSS,RTC_ALMB_HRT_POSE) + +#define RTC_ALMB_HRU_POSS 16U +#define RTC_ALMB_HRU_POSE 19U +#define RTC_ALMB_HRU_MSK BITS(RTC_ALMB_HRU_POSS,RTC_ALMB_HRU_POSE) + +#define RTC_ALMB_MINMSK_POS 15U +#define RTC_ALMB_MINMSK_MSK BIT(RTC_ALMB_MINMSK_POS) + +#define RTC_ALMB_MINT_POSS 12U +#define RTC_ALMB_MINT_POSE 14U +#define RTC_ALMB_MINT_MSK BITS(RTC_ALMB_MINT_POSS,RTC_ALMB_MINT_POSE) + +#define RTC_ALMB_MINU_POSS 8U +#define RTC_ALMB_MINU_POSE 11U +#define RTC_ALMB_MINU_MSK BITS(RTC_ALMB_MINU_POSS,RTC_ALMB_MINU_POSE) + +#define RTC_ALMB_SECMSK_POS 7U +#define RTC_ALMB_SECMSK_MSK BIT(RTC_ALMB_SECMSK_POS) + +#define RTC_ALMB_SECT_POSS 4U +#define RTC_ALMB_SECT_POSE 6U +#define RTC_ALMB_SECT_MSK BITS(RTC_ALMB_SECT_POSS,RTC_ALMB_SECT_POSE) + +#define RTC_ALMB_SECU_POSS 0U +#define RTC_ALMB_SECU_POSE 3U +#define RTC_ALMB_SECU_MSK BITS(RTC_ALMB_SECU_POSS,RTC_ALMB_SECU_POSE) + +/****************** Bit definition for RTC_ALMASSEC register ************************/ + +#define RTC_ALMASSEC_SSECM_POSS 24U +#define RTC_ALMASSEC_SSECM_POSE 27U +#define RTC_ALMASSEC_SSECM_MSK BITS(RTC_ALMASSEC_SSECM_POSS,RTC_ALMASSEC_SSECM_POSE) + +#define RTC_ALMASSEC_SSEC_POSS 0U +#define RTC_ALMASSEC_SSEC_POSE 14U +#define RTC_ALMASSEC_SSEC_MSK BITS(RTC_ALMASSEC_SSEC_POSS,RTC_ALMASSEC_SSEC_POSE) + +/****************** Bit definition for RTC_ALMBSSEC register ************************/ + +#define RTC_ALMBSSEC_SSECM_POSS 24U +#define RTC_ALMBSSEC_SSECM_POSE 27U +#define RTC_ALMBSSEC_SSECM_MSK BITS(RTC_ALMBSSEC_SSECM_POSS,RTC_ALMBSSEC_SSECM_POSE) + +#define RTC_ALMBSSEC_SSEC_POSS 0U +#define RTC_ALMBSSEC_SSEC_POSE 14U +#define RTC_ALMBSSEC_SSEC_MSK BITS(RTC_ALMBSSEC_SSEC_POSS,RTC_ALMBSSEC_SSEC_POSE) + +/****************** Bit definition for RTC_TSTIME register ************************/ + +#define RTC_TSTIME_PM_POS 22U +#define RTC_TSTIME_PM_MSK BIT(RTC_TSTIME_PM_POS) + +#define RTC_TSTIME_HRT_POSS 20U +#define RTC_TSTIME_HRT_POSE 21U +#define RTC_TSTIME_HRT_MSK BITS(RTC_TSTIME_HRT_POSS,RTC_TSTIME_HRT_POSE) + +#define RTC_TSTIME_HRU_POSS 16U +#define RTC_TSTIME_HRU_POSE 19U +#define RTC_TSTIME_HRU_MSK BITS(RTC_TSTIME_HRU_POSS,RTC_TSTIME_HRU_POSE) + +#define RTC_TSTIME_MINT_POSS 12U +#define RTC_TSTIME_MINT_POSE 14U +#define RTC_TSTIME_MINT_MSK BITS(RTC_TSTIME_MINT_POSS,RTC_TSTIME_MINT_POSE) + +#define RTC_TSTIME_MINU_POSS 8U +#define RTC_TSTIME_MINU_POSE 11U +#define RTC_TSTIME_MINU_MSK BITS(RTC_TSTIME_MINU_POSS,RTC_TSTIME_MINU_POSE) + +#define RTC_TSTIME_SECT_POSS 4U +#define RTC_TSTIME_SECT_POSE 6U +#define RTC_TSTIME_SECT_MSK BITS(RTC_TSTIME_SECT_POSS,RTC_TSTIME_SECT_POSE) + +#define RTC_TSTIME_SECU_POSS 0U +#define RTC_TSTIME_SECU_POSE 3U +#define RTC_TSTIME_SECU_MSK BITS(RTC_TSTIME_SECU_POSS,RTC_TSTIME_SECU_POSE) + +/****************** Bit definition for RTC_TSDATE register ************************/ + +#define RTC_TSDATE_WD_POSS 24U +#define RTC_TSDATE_WD_POSE 26U +#define RTC_TSDATE_WD_MSK BITS(RTC_TSDATE_WD_POSS,RTC_TSDATE_WD_POSE) + +#define RTC_TSDATE_YRT_POSS 20U +#define RTC_TSDATE_YRT_POSE 23U +#define RTC_TSDATE_YRT_MSK BITS(RTC_TSDATE_YRT_POSS,RTC_TSDATE_YRT_POSE) + +#define RTC_TSDATE_YRU_POSS 16U +#define RTC_TSDATE_YRU_POSE 19U +#define RTC_TSDATE_YRU_MSK BITS(RTC_TSDATE_YRU_POSS,RTC_TSDATE_YRU_POSE) + +#define RTC_TSDATE_MONT_POS 12U +#define RTC_TSDATE_MONT_MSK BIT(RTC_TSDATE_MONT_POS) + +#define RTC_TSDATE_MONU_POSS 8U +#define RTC_TSDATE_MONU_POSE 11U +#define RTC_TSDATE_MONU_MSK BITS(RTC_TSDATE_MONU_POSS,RTC_TSDATE_MONU_POSE) + +#define RTC_TSDATE_DAYT_POSS 4U +#define RTC_TSDATE_DAYT_POSE 5U +#define RTC_TSDATE_DAYT_MSK BITS(RTC_TSDATE_DAYT_POSS,RTC_TSDATE_DAYT_POSE) + +#define RTC_TSDATE_DAYU_POSS 0U +#define RTC_TSDATE_DAYU_POSE 3U +#define RTC_TSDATE_DAYU_MSK BITS(RTC_TSDATE_DAYU_POSS,RTC_TSDATE_DAYU_POSE) + +/****************** Bit definition for RTC_TSSSEC register ************************/ + +#define RTC_TSSSEC_SSEC_POSS 0U +#define RTC_TSSSEC_SSEC_POSE 15U +#define RTC_TSSSEC_SSEC_MSK BITS(RTC_TSSSEC_SSEC_POSS,RTC_TSSSEC_SSEC_POSE) + +/****************** Bit definition for RTC_SSECTR register ************************/ + +#define RTC_SSECTR_INC_POS 31U +#define RTC_SSECTR_INC_MSK BIT(RTC_SSECTR_INC_POS) + +#define RTC_SSECTR_TRIM_POSS 0U +#define RTC_SSECTR_TRIM_POSE 14U +#define RTC_SSECTR_TRIM_MSK BITS(RTC_SSECTR_TRIM_POSS,RTC_SSECTR_TRIM_POSE) + +/****************** Bit definition for RTC_IER register ************************/ + +#define RTC_IER_TCE_POS 25U +#define RTC_IER_TCE_MSK BIT(RTC_IER_TCE_POS) + +#define RTC_IER_TCC_POS 24U +#define RTC_IER_TCC_MSK BIT(RTC_IER_TCC_POS) + +#define RTC_IER_WU_POS 18U +#define RTC_IER_WU_MSK BIT(RTC_IER_WU_POS) + +#define RTC_IER_SSTC_POS 17U +#define RTC_IER_SSTC_MSK BIT(RTC_IER_SSTC_POS) + +#define RTC_IER_RSC_POS 16U +#define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS) + +#define RTC_IER_TAMP2_POS 13U +#define RTC_IER_TAMP2_MSK BIT(RTC_IER_TAMP2_POS) + +#define RTC_IER_TAMP1_POS 12U +#define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS) + +#define RTC_IER_TSOV_POS 11U +#define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS) + +#define RTC_IER_TS_POS 10U +#define RTC_IER_TS_MSK BIT(RTC_IER_TS_POS) + +#define RTC_IER_ALMB_POS 9U +#define RTC_IER_ALMB_MSK BIT(RTC_IER_ALMB_POS) + +#define RTC_IER_ALMA_POS 8U +#define RTC_IER_ALMA_MSK BIT(RTC_IER_ALMA_POS) + +#define RTC_IER_YR_POS 5U +#define RTC_IER_YR_MSK BIT(RTC_IER_YR_POS) + +#define RTC_IER_MON_POS 4U +#define RTC_IER_MON_MSK BIT(RTC_IER_MON_POS) + +#define RTC_IER_DAY_POS 3U +#define RTC_IER_DAY_MSK BIT(RTC_IER_DAY_POS) + +#define RTC_IER_HR_POS 2U +#define RTC_IER_HR_MSK BIT(RTC_IER_HR_POS) + +#define RTC_IER_MIN_POS 1U +#define RTC_IER_MIN_MSK BIT(RTC_IER_MIN_POS) + +#define RTC_IER_SEC_POS 0U +#define RTC_IER_SEC_MSK BIT(RTC_IER_SEC_POS) + +/****************** Bit definition for RTC_IFR register ************************/ + +#define RTC_IFR_TCEF_POS 25U +#define RTC_IFR_TCEF_MSK BIT(RTC_IFR_TCEF_POS) + +#define RTC_IFR_TCCF_POS 24U +#define RTC_IFR_TCCF_MSK BIT(RTC_IFR_TCCF_POS) + +#define RTC_IFR_WUF_POS 18U +#define RTC_IFR_WUF_MSK BIT(RTC_IFR_WUF_POS) + +#define RTC_IFR_SSTCF_POS 17U +#define RTC_IFR_SSTCF_MSK BIT(RTC_IFR_SSTCF_POS) + +#define RTC_IFR_RSCF_POS 16U +#define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS) + +#define RTC_IFR_TAMP2F_POS 13U +#define RTC_IFR_TAMP2F_MSK BIT(RTC_IFR_TAMP2F_POS) + +#define RTC_IFR_TAMP1F_POS 12U +#define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS) + +#define RTC_IFR_TSOVF_POS 11U +#define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS) + +#define RTC_IFR_TSF_POS 10U +#define RTC_IFR_TSF_MSK BIT(RTC_IFR_TSF_POS) + +#define RTC_IFR_ALMBF_POS 9U +#define RTC_IFR_ALMBF_MSK BIT(RTC_IFR_ALMBF_POS) + +#define RTC_IFR_ALMAF_POS 8U +#define RTC_IFR_ALMAF_MSK BIT(RTC_IFR_ALMAF_POS) + +#define RTC_IFR_YRF_POS 5U +#define RTC_IFR_YRF_MSK BIT(RTC_IFR_YRF_POS) + +#define RTC_IFR_MONF_POS 4U +#define RTC_IFR_MONF_MSK BIT(RTC_IFR_MONF_POS) + +#define RTC_IFR_DAYF_POS 3U +#define RTC_IFR_DAYF_MSK BIT(RTC_IFR_DAYF_POS) + +#define RTC_IFR_HRF_POS 2U +#define RTC_IFR_HRF_MSK BIT(RTC_IFR_HRF_POS) + +#define RTC_IFR_MINF_POS 1U +#define RTC_IFR_MINF_MSK BIT(RTC_IFR_MINF_POS) + +#define RTC_IFR_SECF_POS 0U +#define RTC_IFR_SECF_MSK BIT(RTC_IFR_SECF_POS) + +/****************** Bit definition for RTC_IFCR register ************************/ + +#define RTC_IFCR_TCEFC_POS 25U +#define RTC_IFCR_TCEFC_MSK BIT(RTC_IFCR_TCEFC_POS) + +#define RTC_IFCR_TCCFC_POS 24U +#define RTC_IFCR_TCCFC_MSK BIT(RTC_IFCR_TCCFC_POS) + +#define RTC_IFCR_WUFC_POS 18U +#define RTC_IFCR_WUFC_MSK BIT(RTC_IFCR_WUFC_POS) + +#define RTC_IFCR_SSTCFC_POS 17U +#define RTC_IFCR_SSTCFC_MSK BIT(RTC_IFCR_SSTCFC_POS) + +#define RTC_IFCR_RSCFC_POS 16U +#define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS) + +#define RTC_IFCR_TAMP2FC_POS 13U +#define RTC_IFCR_TAMP2FC_MSK BIT(RTC_IFCR_TAMP2FC_POS) + +#define RTC_IFCR_TAMP1FC_POS 12U +#define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS) + +#define RTC_IFCR_TSOVFC_POS 11U +#define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS) + +#define RTC_IFCR_TSSTC_POS 10U +#define RTC_IFCR_TSSTC_MSK BIT(RTC_IFCR_TSSTC_POS) + +#define RTC_IFCR_ALMBFC_POS 9U +#define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS) + +#define RTC_IFCR_ALMAFC_POS 8U +#define RTC_IFCR_ALMAFC_MSK BIT(RTC_IFCR_ALMAFC_POS) + +#define RTC_IFCR_YRFC_POS 5U +#define RTC_IFCR_YRFC_MSK BIT(RTC_IFCR_YRFC_POS) + +#define RTC_IFCR_MONFC_POS 4U +#define RTC_IFCR_MONFC_MSK BIT(RTC_IFCR_MONFC_POS) + +#define RTC_IFCR_DAYFC_POS 3U +#define RTC_IFCR_DAYFC_MSK BIT(RTC_IFCR_DAYFC_POS) + +#define RTC_IFCR_HRFC_POS 2U +#define RTC_IFCR_HRFC_MSK BIT(RTC_IFCR_HRFC_POS) + +#define RTC_IFCR_MINFC_POS 1U +#define RTC_IFCR_MINFC_MSK BIT(RTC_IFCR_MINFC_POS) + +#define RTC_IFCR_SECFC_POS 0U +#define RTC_IFCR_SECFC_MSK BIT(RTC_IFCR_SECFC_POS) + +/****************** Bit definition for RTC_ISR register ************************/ + +#define RTC_ISR_TCEF_POS 25U +#define RTC_ISR_TCEF_MSK BIT(RTC_ISR_TCEF_POS) + +#define RTC_ISR_TCCF_POS 24U +#define RTC_ISR_TCCF_MSK BIT(RTC_ISR_TCCF_POS) + +#define RTC_ISR_WUF_POS 18U +#define RTC_ISR_WUF_MSK BIT(RTC_ISR_WUF_POS) + +#define RTC_ISR_SSTCF_POS 17U +#define RTC_ISR_SSTCF_MSK BIT(RTC_ISR_SSTCF_POS) + +#define RTC_ISR_RSCF_POS 16U +#define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS) + +#define RTC_ISR_TAMP2F_POS 13U +#define RTC_ISR_TAMP2F_MSK BIT(RTC_ISR_TAMP2F_POS) + +#define RTC_ISR_TAMP1F_POS 12U +#define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS) + +#define RTC_ISR_TSOVF_POS 11U +#define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS) + +#define RTC_ISR_TSF_POS 10U +#define RTC_ISR_TSF_MSK BIT(RTC_ISR_TSF_POS) + +#define RTC_ISR_ALMBF_POS 9U +#define RTC_ISR_ALMBF_MSK BIT(RTC_ISR_ALMBF_POS) + +#define RTC_ISR_ALMAF_POS 8U +#define RTC_ISR_ALMAF_MSK BIT(RTC_ISR_ALMAF_POS) + +#define RTC_ISR_YRF_POS 5U +#define RTC_ISR_YRF_MSK BIT(RTC_ISR_YRF_POS) + +#define RTC_ISR_MONF_POS 4U +#define RTC_ISR_MONF_MSK BIT(RTC_ISR_MONF_POS) + +#define RTC_ISR_DAYF_POS 3U +#define RTC_ISR_DAYF_MSK BIT(RTC_ISR_DAYF_POS) + +#define RTC_ISR_HRF_POS 2U +#define RTC_ISR_HRF_MSK BIT(RTC_ISR_HRF_POS) + +#define RTC_ISR_MINF_POS 1U +#define RTC_ISR_MINF_MSK BIT(RTC_ISR_MINF_POS) + +#define RTC_ISR_SECF_POS 0U +#define RTC_ISR_SECF_MSK BIT(RTC_ISR_SECF_POS) + +/****************** Bit definition for RTC_CALWPR register ************************/ + +#define RTC_CALWPR_WP_POS 0U +#define RTC_CALWPR_WP_MSK BIT(RTC_CALWPR_WP_POS) + +/****************** Bit definition for RTC_CALCON register ************************/ + +#define RTC_CALCON_DCMACC_POS 24U +#define RTC_CALCON_DCMACC_MSK BIT(RTC_CALCON_DCMACC_POS) + +#define RTC_CALCON_ALG_POS 23U +#define RTC_CALCON_ALG_MSK BIT(RTC_CALCON_ALG_POS) + +#define RTC_CALCON_TCP_POSS 20U +#define RTC_CALCON_TCP_POSE 22U +#define RTC_CALCON_TCP_MSK BITS(RTC_CALCON_TCP_POSS,RTC_CALCON_TCP_POSE) + +#define RTC_CALCON_ERR_POS 19U +#define RTC_CALCON_ERR_MSK BIT(RTC_CALCON_ERR_POS) + +#define RTC_CALCON_BUSY_POS 18U +#define RTC_CALCON_BUSY_MSK BIT(RTC_CALCON_BUSY_POS) + +#define RTC_CALCON_TCM_POSS 16U +#define RTC_CALCON_TCM_POSE 17U +#define RTC_CALCON_TCM_MSK BITS(RTC_CALCON_TCM_POSS,RTC_CALCON_TCM_POSE) + +#define RTC_CALCON_CALP_POSS 1U +#define RTC_CALCON_CALP_POSE 3U +#define RTC_CALCON_CALP_MSK BITS(RTC_CALCON_CALP_POSS,RTC_CALCON_CALP_POSE) + +#define RTC_CALCON_CALEN_POS 0U +#define RTC_CALCON_CALEN_MSK BIT(RTC_CALCON_CALEN_POS) + +/****************** Bit definition for RTC_CALDR register ************************/ + +#define RTC_CALDR_DATA_POSS 16U +#define RTC_CALDR_DATA_POSE 31U +#define RTC_CALDR_DATA_MSK BITS(RTC_CALDR_DATA_POSS,RTC_CALDR_DATA_POSE) + +#define RTC_CALDR_VAL_POSS 0U +#define RTC_CALDR_VAL_POSE 15U +#define RTC_CALDR_VAL_MSK BITS(RTC_CALDR_VAL_POSS,RTC_CALDR_VAL_POSE) + +/****************** Bit definition for RTC_TEMPR register ************************/ + +#define RTC_TEMPR_DATA_POSS 16U +#define RTC_TEMPR_DATA_POSE 31U +#define RTC_TEMPR_DATA_MSK BITS(RTC_TEMPR_DATA_POSS,RTC_TEMPR_DATA_POSE) + +#define RTC_TEMPR_VAL_POSS 0U +#define RTC_TEMPR_VAL_POSE 15U +#define RTC_TEMPR_VAL_MSK BITS(RTC_TEMPR_VAL_POSS,RTC_TEMPR_VAL_POSE) + +/****************** Bit definition for RTC_TEMPBDR register ************************/ + +#define RTC_TEMPBDR_VAL_POSS 0U +#define RTC_TEMPBDR_VAL_POSE 15U +#define RTC_TEMPBDR_VAL_MSK BITS(RTC_TEMPBDR_VAL_POSS,RTC_TEMPBDR_VAL_POSE) + +/****************** Bit definition for RTC_BKP register ************************/ + +#define RTC_BKP_BKP_POSS 0U +#define RTC_BKP_BKP_POSE 31U +#define RTC_BKP_BKP_MSK BITS(RTC_BKP_BKP_POSS,RTC_BKP_BKP_POSE) + +typedef struct +{ + __IO uint32_t WPR; + __IO uint32_t CON; + __IO uint32_t PSR; + __IO uint32_t TAMPCON; + __IO uint32_t TIME; + __IO uint32_t DATE; + __IO uint32_t SSEC; + __IO uint32_t WUMAT; + __IO uint32_t ALMA; + __IO uint32_t ALMB; + __IO uint32_t ALMASSEC; + __IO uint32_t ALMBSSEC; + __I uint32_t TSTIME; + __I uint32_t TSDATE; + __I uint32_t TSSSEC; + __O uint32_t SSECTR; + __IO uint32_t IER; + __I uint32_t IFR; + __O uint32_t IFCR; + __I uint32_t ISR; + __IO uint32_t CALWPR; + __IO uint32_t CALCON; + __IO uint32_t CALDR; + __IO uint32_t TEMPR; + __IO uint32_t LTCAR; + __IO uint32_t LTCBR; + __IO uint32_t LTCCR; + __IO uint32_t LTCDR; + __IO uint32_t LTCER; + __IO uint32_t HTCAR; + __IO uint32_t HTCBR; + __IO uint32_t HTCCR; + __IO uint32_t HTCDR; + __IO uint32_t HTCER; + __IO uint32_t TEMPBDR; + uint32_t RESERVED0[29] ; + __IO uint32_t BKPR[32]; +} RTC_TypeDef; + +/****************** Bit definition for TIMER_CON1 register ************************/ + +#define TIMER_CON1_DFCKSEL_POSS 8U +#define TIMER_CON1_DFCKSEL_POSE 9U +#define TIMER_CON1_DFCKSEL_MSK BITS(TIMER_CON1_DFCKSEL_POSS,TIMER_CON1_DFCKSEL_POSE) + +#define TIMER_CON1_ARPEN_POS 7U +#define TIMER_CON1_ARPEN_MSK BIT(TIMER_CON1_ARPEN_POS) + +#define TIMER_CON1_CMSEL_POSS 5U +#define TIMER_CON1_CMSEL_POSE 6U +#define TIMER_CON1_CMSEL_MSK BITS(TIMER_CON1_CMSEL_POSS,TIMER_CON1_CMSEL_POSE) + +#define TIMER_CON1_DIRSEL_POS 4U +#define TIMER_CON1_DIRSEL_MSK BIT(TIMER_CON1_DIRSEL_POS) + +#define TIMER_CON1_SPMEN_POS 3U +#define TIMER_CON1_SPMEN_MSK BIT(TIMER_CON1_SPMEN_POS) + +#define TIMER_CON1_UERSEL_POS 2U +#define TIMER_CON1_UERSEL_MSK BIT(TIMER_CON1_UERSEL_POS) + +#define TIMER_CON1_DISUE_POS 1U +#define TIMER_CON1_DISUE_MSK BIT(TIMER_CON1_DISUE_POS) + +#define TIMER_CON1_CNTEN_POS 0U +#define TIMER_CON1_CNTEN_MSK BIT(TIMER_CON1_CNTEN_POS) + +/****************** Bit definition for TIMER_CON2 register ************************/ + +#define TIMER_CON2_OISS4_POS 14U +#define TIMER_CON2_OISS4_MSK BIT(TIMER_CON2_OISS4_POS) + +#define TIMER_CON2_OISS3N_POS 13U +#define TIMER_CON2_OISS3N_MSK BIT(TIMER_CON2_OISS3N_POS) + +#define TIMER_CON2_OISS3_POS 12U +#define TIMER_CON2_OISS3_MSK BIT(TIMER_CON2_OISS3_POS) + +#define TIMER_CON2_OISS2N_POS 11U +#define TIMER_CON2_OISS2N_MSK BIT(TIMER_CON2_OISS2N_POS) + +#define TIMER_CON2_OISS2_POS 10U +#define TIMER_CON2_OISS2_MSK BIT(TIMER_CON2_OISS2_POS) + +#define TIMER_CON2_OISS1N_POS 9U +#define TIMER_CON2_OISS1N_MSK BIT(TIMER_CON2_OISS1N_POS) + +#define TIMER_CON2_OISS1_POS 8U +#define TIMER_CON2_OISS1_MSK BIT(TIMER_CON2_OISS1_POS) + +#define TIMER_CON2_I1FSEL_POS 7U +#define TIMER_CON2_I1FSEL_MSK BIT(TIMER_CON2_I1FSEL_POS) + +#define TIMER_CON2_TRGOSEL_POSS 4U +#define TIMER_CON2_TRGOSEL_POSE 6U +#define TIMER_CON2_TRGOSEL_MSK BITS(TIMER_CON2_TRGOSEL_POSS,TIMER_CON2_TRGOSEL_POSE) + +#define TIMER_CON2_CCDMASEL_POS 3U +#define TIMER_CON2_CCDMASEL_MSK BIT(TIMER_CON2_CCDMASEL_POS) + +#define TIMER_CON2_CCUSEL_POS 2U +#define TIMER_CON2_CCUSEL_MSK BIT(TIMER_CON2_CCUSEL_POS) + +#define TIMER_CON2_CCPCEN_POS 0U +#define TIMER_CON2_CCPCEN_MSK BIT(TIMER_CON2_CCPCEN_POS) + +/****************** Bit definition for TIMER_SMCON register ************************/ + +#define TIMER_SMCON_ETPOL_POS 15U +#define TIMER_SMCON_ETPOL_MSK BIT(TIMER_SMCON_ETPOL_POS) + +#define TIMER_SMCON_ECM2EN_POS 14U +#define TIMER_SMCON_ECM2EN_MSK BIT(TIMER_SMCON_ECM2EN_POS) + +#define TIMER_SMCON_ETPSEL_POSS 12U +#define TIMER_SMCON_ETPSEL_POSE 13U +#define TIMER_SMCON_ETPSEL_MSK BITS(TIMER_SMCON_ETPSEL_POSS,TIMER_SMCON_ETPSEL_POSE) + +#define TIMER_SMCON_ETFLT_POSS 8U +#define TIMER_SMCON_ETFLT_POSE 11U +#define TIMER_SMCON_ETFLT_MSK BITS(TIMER_SMCON_ETFLT_POSS,TIMER_SMCON_ETFLT_POSE) + +#define TIMER_SMCON_MSCFG_POS 7U +#define TIMER_SMCON_MSCFG_MSK BIT(TIMER_SMCON_MSCFG_POS) + +#define TIMER_SMCON_TSSEL_POSS 4U +#define TIMER_SMCON_TSSEL_POSE 6U +#define TIMER_SMCON_TSSEL_MSK BITS(TIMER_SMCON_TSSEL_POSS,TIMER_SMCON_TSSEL_POSE) + +#define TIMER_SMCON_SMODS_POSS 0U +#define TIMER_SMCON_SMODS_POSE 2U +#define TIMER_SMCON_SMODS_MSK BITS(TIMER_SMCON_SMODS_POSS,TIMER_SMCON_SMODS_POSE) + +/****************** Bit definition for TIMER_DIER register ************************/ + +#define TIMER_DIER_TRGDMA_POS 14U +#define TIMER_DIER_TRGDMA_MSK BIT(TIMER_DIER_TRGDMA_POS) + +#define TIMER_DIER_COMDMA_POS 13U +#define TIMER_DIER_COMDMA_MSK BIT(TIMER_DIER_COMDMA_POS) + +#define TIMER_DIER_CC4DMA_POS 12U +#define TIMER_DIER_CC4DMA_MSK BIT(TIMER_DIER_CC4DMA_POS) + +#define TIMER_DIER_CC3DMA_POS 11U +#define TIMER_DIER_CC3DMA_MSK BIT(TIMER_DIER_CC3DMA_POS) + +#define TIMER_DIER_CC2DMA_POS 10U +#define TIMER_DIER_CC2DMA_MSK BIT(TIMER_DIER_CC2DMA_POS) + +#define TIMER_DIER_CC1DMA_POS 9U +#define TIMER_DIER_CC1DMA_MSK BIT(TIMER_DIER_CC1DMA_POS) + +#define TIMER_DIER_UDMA_POS 8U +#define TIMER_DIER_UDMA_MSK BIT(TIMER_DIER_UDMA_POS) + +#define TIMER_DIER_BRKIT_POS 7U +#define TIMER_DIER_BRKIT_MSK BIT(TIMER_DIER_BRKIT_POS) + +#define TIMER_DIER_TRGIT_POS 6U +#define TIMER_DIER_TRGIT_MSK BIT(TIMER_DIER_TRGIT_POS) + +#define TIMER_DIER_COMIT_POS 5U +#define TIMER_DIER_COMIT_MSK BIT(TIMER_DIER_COMIT_POS) + +#define TIMER_DIER_CC4IT_POS 4U +#define TIMER_DIER_CC4IT_MSK BIT(TIMER_DIER_CC4IT_POS) + +#define TIMER_DIER_CC3IT_POS 3U +#define TIMER_DIER_CC3IT_MSK BIT(TIMER_DIER_CC3IT_POS) + +#define TIMER_DIER_CC2IT_POS 2U +#define TIMER_DIER_CC2IT_MSK BIT(TIMER_DIER_CC2IT_POS) + +#define TIMER_DIER_CC1IT_POS 1U +#define TIMER_DIER_CC1IT_MSK BIT(TIMER_DIER_CC1IT_POS) + +#define TIMER_DIER_UIT_POS 0U +#define TIMER_DIER_UIT_MSK BIT(TIMER_DIER_UIT_POS) + +/****************** Bit definition for TIMER_DIDR register ************************/ + +#define TIMER_DIDR_TRGDMA_POS 14U +#define TIMER_DIDR_TRGDMA_MSK BIT(TIMER_DIDR_TRGDMA_POS) + +#define TIMER_DIDR_COMD_POS 13U +#define TIMER_DIDR_COMD_MSK BIT(TIMER_DIDR_COMD_POS) + +#define TIMER_DIDR_CC4D_POS 12U +#define TIMER_DIDR_CC4D_MSK BIT(TIMER_DIDR_CC4D_POS) + +#define TIMER_DIDR_CC3D_POS 11U +#define TIMER_DIDR_CC3D_MSK BIT(TIMER_DIDR_CC3D_POS) + +#define TIMER_DIDR_CC2D_POS 10U +#define TIMER_DIDR_CC2D_MSK BIT(TIMER_DIDR_CC2D_POS) + +#define TIMER_DIDR_CC1D_POS 9U +#define TIMER_DIDR_CC1D_MSK BIT(TIMER_DIDR_CC1D_POS) + +#define TIMER_DIDR_UD_POS 8U +#define TIMER_DIDR_UD_MSK BIT(TIMER_DIDR_UD_POS) + +#define TIMER_DIDR_BRKI_POS 7U +#define TIMER_DIDR_BRKI_MSK BIT(TIMER_DIDR_BRKI_POS) + +#define TIMER_DIDR_TRGI_POS 6U +#define TIMER_DIDR_TRGI_MSK BIT(TIMER_DIDR_TRGI_POS) + +#define TIMER_DIDR_COMI_POS 5U +#define TIMER_DIDR_COMI_MSK BIT(TIMER_DIDR_COMI_POS) + +#define TIMER_DIDR_CC4I_POS 4U +#define TIMER_DIDR_CC4I_MSK BIT(TIMER_DIDR_CC4I_POS) + +#define TIMER_DIDR_CC3I_POS 3U +#define TIMER_DIDR_CC3I_MSK BIT(TIMER_DIDR_CC3I_POS) + +#define TIMER_DIDR_CC2I_POS 2U +#define TIMER_DIDR_CC2I_MSK BIT(TIMER_DIDR_CC2I_POS) + +#define TIMER_DIDR_CC1I_POS 1U +#define TIMER_DIDR_CC1I_MSK BIT(TIMER_DIDR_CC1I_POS) + +#define TIMER_DIDR_UI_POS 0U +#define TIMER_DIDR_UI_MSK BIT(TIMER_DIDR_UI_POS) + +/****************** Bit definition for TIMER_DIVS register ************************/ + +#define TIMER_DIVS_TRGDMA_POS 14U +#define TIMER_DIVS_TRGDMA_MSK BIT(TIMER_DIVS_TRGDMA_POS) + +#define TIMER_DIVS_COMDMA_POS 13U +#define TIMER_DIVS_COMDMA_MSK BIT(TIMER_DIVS_COMDMA_POS) + +#define TIMER_DIVS_CC4DMA_POS 12U +#define TIMER_DIVS_CC4DMA_MSK BIT(TIMER_DIVS_CC4DMA_POS) + +#define TIMER_DIVS_CC3DMA_POS 11U +#define TIMER_DIVS_CC3DMA_MSK BIT(TIMER_DIVS_CC3DMA_POS) + +#define TIMER_DIVS_CC2DMA_POS 10U +#define TIMER_DIVS_CC2DMA_MSK BIT(TIMER_DIVS_CC2DMA_POS) + +#define TIMER_DIVS_CC1DMA_POS 9U +#define TIMER_DIVS_CC1DMA_MSK BIT(TIMER_DIVS_CC1DMA_POS) + +#define TIMER_DIVS_UEDTR_POS 8U +#define TIMER_DIVS_UEDTR_MSK BIT(TIMER_DIVS_UEDTR_POS) + +#define TIMER_DIVS_BKI_POS 7U +#define TIMER_DIVS_BKI_MSK BIT(TIMER_DIVS_BKI_POS) + +#define TIMER_DIVS_TRGI_POS 6U +#define TIMER_DIVS_TRGI_MSK BIT(TIMER_DIVS_TRGI_POS) + +#define TIMER_DIVS_COMI_POS 5U +#define TIMER_DIVS_COMI_MSK BIT(TIMER_DIVS_COMI_POS) + +#define TIMER_DIVS_CC4I_POS 4U +#define TIMER_DIVS_CC4I_MSK BIT(TIMER_DIVS_CC4I_POS) + +#define TIMER_DIVS_CC3I_POS 3U +#define TIMER_DIVS_CC3I_MSK BIT(TIMER_DIVS_CC3I_POS) + +#define TIMER_DIVS_CC2I_POS 2U +#define TIMER_DIVS_CC2I_MSK BIT(TIMER_DIVS_CC2I_POS) + +#define TIMER_DIVS_CC1I_POS 1U +#define TIMER_DIVS_CC1I_MSK BIT(TIMER_DIVS_CC1I_POS) + +#define TIMER_DIVS_UEI_POS 0U +#define TIMER_DIVS_UEI_MSK BIT(TIMER_DIVS_UEI_POS) + +/****************** Bit definition for TIMER_RIF register ************************/ + +#define TIMER_RIF_CH4OVIF_POS 12U +#define TIMER_RIF_CH4OVIF_MSK BIT(TIMER_RIF_CH4OVIF_POS) + +#define TIMER_RIF_CH3OVIF_POS 11U +#define TIMER_RIF_CH3OVIF_MSK BIT(TIMER_RIF_CH3OVIF_POS) + +#define TIMER_RIF_CH2OVIF_POS 10U +#define TIMER_RIF_CH2OVIF_MSK BIT(TIMER_RIF_CH2OVIF_POS) + +#define TIMER_RIF_CH1OVIF_POS 9U +#define TIMER_RIF_CH1OVIF_MSK BIT(TIMER_RIF_CH1OVIF_POS) + +#define TIMER_RIF_BRKIF_POS 7U +#define TIMER_RIF_BRKIF_MSK BIT(TIMER_RIF_BRKIF_POS) + +#define TIMER_RIF_TRGIF_POS 6U +#define TIMER_RIF_TRGIF_MSK BIT(TIMER_RIF_TRGIF_POS) + +#define TIMER_RIF_COMIF_POS 5U +#define TIMER_RIF_COMIF_MSK BIT(TIMER_RIF_COMIF_POS) + +#define TIMER_RIF_CH4IF_POS 4U +#define TIMER_RIF_CH4IF_MSK BIT(TIMER_RIF_CH4IF_POS) + +#define TIMER_RIF_CH3IF_POS 3U +#define TIMER_RIF_CH3IF_MSK BIT(TIMER_RIF_CH3IF_POS) + +#define TIMER_RIF_CH2IF_POS 2U +#define TIMER_RIF_CH2IF_MSK BIT(TIMER_RIF_CH2IF_POS) + +#define TIMER_RIF_CH1IF_POS 1U +#define TIMER_RIF_CH1IF_MSK BIT(TIMER_RIF_CH1IF_POS) + +#define TIMER_RIF_UEVTIF_POS 0U +#define TIMER_RIF_UEVTIF_MSK BIT(TIMER_RIF_UEVTIF_POS) + +/****************** Bit definition for TIMER_IFM register ************************/ + +#define TIMER_IFM_BRKIM_POS 7U +#define TIMER_IFM_BRKIM_MSK BIT(TIMER_IFM_BRKIM_POS) + +#define TIMER_IFM_TRGI_POS 6U +#define TIMER_IFM_TRGI_MSK BIT(TIMER_IFM_TRGI_POS) + +#define TIMER_IFM_COMI_POS 5U +#define TIMER_IFM_COMI_MSK BIT(TIMER_IFM_COMI_POS) + +#define TIMER_IFM_CH4CCI_POS 4U +#define TIMER_IFM_CH4CCI_MSK BIT(TIMER_IFM_CH4CCI_POS) + +#define TIMER_IFM_CH3CCI_POS 3U +#define TIMER_IFM_CH3CCI_MSK BIT(TIMER_IFM_CH3CCI_POS) + +#define TIMER_IFM_CH2CCI_POS 2U +#define TIMER_IFM_CH2CCI_MSK BIT(TIMER_IFM_CH2CCI_POS) + +#define TIMER_IFM_CH1CCI_POS 1U +#define TIMER_IFM_CH1CCI_MSK BIT(TIMER_IFM_CH1CCI_POS) + +#define TIMER_IFM_UEI_POS 0U +#define TIMER_IFM_UEI_MSK BIT(TIMER_IFM_UEI_POS) + +/****************** Bit definition for TIMER_ICR register ************************/ + +#define TIMER_ICR_BRKIC_POS 7U +#define TIMER_ICR_BRKIC_MSK BIT(TIMER_ICR_BRKIC_POS) + +#define TIMER_ICR_TRGIC_POS 6U +#define TIMER_ICR_TRGIC_MSK BIT(TIMER_ICR_TRGIC_POS) + +#define TIMER_ICR_COMIC_POS 5U +#define TIMER_ICR_COMIC_MSK BIT(TIMER_ICR_COMIC_POS) + +#define TIMER_ICR_CH4CCIC_POS 4U +#define TIMER_ICR_CH4CCIC_MSK BIT(TIMER_ICR_CH4CCIC_POS) + +#define TIMER_ICR_CH3CCIC_POS 3U +#define TIMER_ICR_CH3CCIC_MSK BIT(TIMER_ICR_CH3CCIC_POS) + +#define TIMER_ICR_CH2CCIC_POS 2U +#define TIMER_ICR_CH2CCIC_MSK BIT(TIMER_ICR_CH2CCIC_POS) + +#define TIMER_ICR_CH1CCIC_POS 1U +#define TIMER_ICR_CH1CCIC_MSK BIT(TIMER_ICR_CH1CCIC_POS) + +#define TIMER_ICR_UEIC_POS 0U +#define TIMER_ICR_UEIC_MSK BIT(TIMER_ICR_UEIC_POS) + +/****************** Bit definition for TIMER_SGE register ************************/ + +#define TIMER_SGE_SGBRK_POS 7U +#define TIMER_SGE_SGBRK_MSK BIT(TIMER_SGE_SGBRK_POS) + +#define TIMER_SGE_SGTRG_POS 6U +#define TIMER_SGE_SGTRG_MSK BIT(TIMER_SGE_SGTRG_POS) + +#define TIMER_SGE_SGCOM_POS 5U +#define TIMER_SGE_SGCOM_MSK BIT(TIMER_SGE_SGCOM_POS) + +#define TIMER_SGE_SGCC4E_POS 4U +#define TIMER_SGE_SGCC4E_MSK BIT(TIMER_SGE_SGCC4E_POS) + +#define TIMER_SGE_SGCC3E_POS 3U +#define TIMER_SGE_SGCC3E_MSK BIT(TIMER_SGE_SGCC3E_POS) + +#define TIMER_SGE_SGCC2E_POS 2U +#define TIMER_SGE_SGCC2E_MSK BIT(TIMER_SGE_SGCC2E_POS) + +#define TIMER_SGE_SGCC1E_POS 1U +#define TIMER_SGE_SGCC1E_MSK BIT(TIMER_SGE_SGCC1E_POS) + +#define TIMER_SGE_SGU_POS 0U +#define TIMER_SGE_SGU_MSK BIT(TIMER_SGE_SGU_POS) + +/****************** Bit definition for TIMER_CHMR1 register ************************/ +/* Output */ +#define TIMER_CHMR1_CH2OCLREN_POS 15U +#define TIMER_CHMR1_CH2OCLREN_MSK BIT(TIMER_CHMR1_CH2OCLREN_POS) + +#define TIMER_CHMR1_CH2OMOD_POSS 12U +#define TIMER_CHMR1_CH2OMOD_POSE 14U +#define TIMER_CHMR1_CH2OMOD_MSK BITS(TIMER_CHMR1_CH2OMOD_POSS,TIMER_CHMR1_CH2OMOD_POSE) + +#define TIMER_CHMR1_CH2OPEN_POS 11U +#define TIMER_CHMR1_CH2OPEN_MSK BIT(TIMER_CHMR1_CH2OPEN_POS) + +#define TIMER_CHMR1_CH2OFEN_POS 10U +#define TIMER_CHMR1_CH2OFEN_MSK BIT(TIMER_CHMR1_CH2OFEN_POS) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_CH1OCLREN_POS 7U +#define TIMER_CHMR1_CH1OCLREN_MSK BIT(TIMER_CHMR1_CH1OCLREN_POS) + +#define TIMER_CHMR1_CH1OMOD_POSS 4U +#define TIMER_CHMR1_CH1OMOD_POSE 6U +#define TIMER_CHMR1_CH1OMOD_MSK BITS(TIMER_CHMR1_CH1OMOD_POSS,TIMER_CHMR1_CH1OMOD_POSE) + +#define TIMER_CHMR1_CH1OPREN_POS 3U +#define TIMER_CHMR1_CH1OPREN_MSK BIT(TIMER_CHMR1_CH1OPREN_POS) + +#define TIMER_CHMR1_CH1OHSEN_POS 2U +#define TIMER_CHMR1_CH1OHSEN_MSK BIT(TIMER_CHMR1_CH1OHSEN_POS) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/* Input */ +#define TIMER_CHMR1_I2FLT_POSS 12U +#define TIMER_CHMR1_I2FLT_POSE 15U +#define TIMER_CHMR1_I2FLT_MSK BITS(TIMER_CHMR1_I2FLT_POSS,TIMER_CHMR1_I2FLT_POSE) + +#define TIMER_CHMR1_IC2PRES_POSS 10U +#define TIMER_CHMR1_IC2PRES_POSE 11U +#define TIMER_CHMR1_IC2PRES_MSK BITS(TIMER_CHMR1_IC2PRES_POSS,TIMER_CHMR1_IC2PRES_POSE) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_I1FLT_POSS 4U +#define TIMER_CHMR1_I1FLT_POSE 7U +#define TIMER_CHMR1_I1FLT_MSK BITS(TIMER_CHMR1_I1FLT_POSS,TIMER_CHMR1_I1FLT_POSE) + +#define TIMER_CHMR1_IC1PRES_POSS 2U +#define TIMER_CHMR1_IC1PRES_POSE 3U +#define TIMER_CHMR1_IC1PRES_MSK BITS(TIMER_CHMR1_IC1PRES_POSS,TIMER_CHMR1_IC1PRES_POSE) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/****************** Bit definition for TIMER_CHMR2 register ************************/ +/* Output */ +#define TIMER_CHMR2_CH4OCLREN_POS 15U +#define TIMER_CHMR2_CH4OCLREN_MSK BIT(TIMER_CHMR2_CH4OCLREN_POS) + +#define TIMER_CHMR2_CH4OMOD_POSS 12U +#define TIMER_CHMR2_CH4OMOD_POSE 14U +#define TIMER_CHMR2_CH4OMOD_MSK BITS(TIMER_CHMR2_CH4OMOD_POSS,TIMER_CHMR2_CH4OMOD_POSE) + +#define TIMER_CHMR2_CH4OPEN_POS 11U +#define TIMER_CHMR2_CH4OPEN_MSK BIT(TIMER_CHMR2_CH4OPEN_POS) + +#define TIMER_CHMR2_CH4OHSEN_POS 10U +#define TIMER_CHMR2_CH4OHSEN_MSK BIT(TIMER_CHMR2_CH4OHSEN_POS) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_CH3OCLREN_POS 7U +#define TIMER_CHMR2_CH3OCLREN_MSK BIT(TIMER_CHMR2_CH3OCLREN_POS) + +#define TIMER_CHMR2_CH3OMOD_POSS 4U +#define TIMER_CHMR2_CH3OMOD_POSE 6U +#define TIMER_CHMR2_CH3OMOD_MSK BITS(TIMER_CHMR2_CH3OMOD_POSS,TIMER_CHMR2_CH3OMOD_POSE) + +#define TIMER_CHMR2_CH3OPEN_POS 3U +#define TIMER_CHMR2_CH3OPEN_MSK BIT(TIMER_CHMR2_CH3OPEN_POS) + +#define TIMER_CHMR2_CH3OFEN_POS 2U +#define TIMER_CHMR2_CH3OFEN_MSK BIT(TIMER_CHMR2_CH3OFEN_POS) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/* Input */ +#define TIMER_CHMR2_I4FLT_POSS 12U +#define TIMER_CHMR2_I4FLT_POSE 15U +#define TIMER_CHMR2_I4FLT_MSK BITS(TIMER_CHMR2_I4FLT_POSS,TIMER_CHMR2_I4FLT_POSE) + +#define TIMER_CHMR2_IC4PRES_POSS 10U +#define TIMER_CHMR2_IC4PRES_POSE 11U +#define TIMER_CHMR2_IC4PRES_MSK BITS(TIMER_CHMR2_IC4PRES_POSS,TIMER_CHMR2_IC4PRES_POSE) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_I3FLT_POSS 4U +#define TIMER_CHMR2_I3FLT_POSE 7U +#define TIMER_CHMR2_I3FLT_MSK BITS(TIMER_CHMR2_I3FLT_POSS,TIMER_CHMR2_I3FLT_POSE) + +#define TIMER_CHMR2_IC3PRES_POSS 2U +#define TIMER_CHMR2_IC3PRES_POSE 3U +#define TIMER_CHMR2_IC3PRES_MSK BITS(TIMER_CHMR2_IC3PRES_POSS,TIMER_CHMR2_IC3PRES_POSE) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/****************** Bit definition for TIMER_CCEP register ************************/ + +#define TIMER_CCEP_CC4POL_POS 13U +#define TIMER_CCEP_CC4POL_MSK BIT(TIMER_CCEP_CC4POL_POS) + +#define TIMER_CCEP_CC4EN_POS 12U +#define TIMER_CCEP_CC4EN_MSK BIT(TIMER_CCEP_CC4EN_POS) + +#define TIMER_CCEP_CC3NPOL_POS 11U +#define TIMER_CCEP_CC3NPOL_MSK BIT(TIMER_CCEP_CC3NPOL_POS) + +#define TIMER_CCEP_CC3NEN_POS 10U +#define TIMER_CCEP_CC3NEN_MSK BIT(TIMER_CCEP_CC3NEN_POS) + +#define TIMER_CCEP_CC3POL_POS 9U +#define TIMER_CCEP_CC3POL_MSK BIT(TIMER_CCEP_CC3POL_POS) + +#define TIMER_CCEP_CC3EN_POS 8U +#define TIMER_CCEP_CC3EN_MSK BIT(TIMER_CCEP_CC3EN_POS) + +#define TIMER_CCEP_CC2NPOL_POS 7U +#define TIMER_CCEP_CC2NPOL_MSK BIT(TIMER_CCEP_CC2NPOL_POS) + +#define TIMER_CCEP_CC2NEN_POS 6U +#define TIMER_CCEP_CC2NEN_MSK BIT(TIMER_CCEP_CC2NEN_POS) + +#define TIMER_CCEP_CC2POL_POS 5U +#define TIMER_CCEP_CC2POL_MSK BIT(TIMER_CCEP_CC2POL_POS) + +#define TIMER_CCEP_CC2EN_POS 4U +#define TIMER_CCEP_CC2EN_MSK BIT(TIMER_CCEP_CC2EN_POS) + +#define TIMER_CCEP_CC1NPOL_POS 3U +#define TIMER_CCEP_CC1NPOL_MSK BIT(TIMER_CCEP_CC1NPOL_POS) + +#define TIMER_CCEP_CC1NEN_POS 2U +#define TIMER_CCEP_CC1NEN_MSK BIT(TIMER_CCEP_CC1NEN_POS) + +#define TIMER_CCEP_CC1POL_POS 1U +#define TIMER_CCEP_CC1POL_MSK BIT(TIMER_CCEP_CC1POL_POS) + +#define TIMER_CCEP_CC1EN_POS 0U +#define TIMER_CCEP_CC1EN_MSK BIT(TIMER_CCEP_CC1EN_POS) + +/****************** Bit definition for TIMER_COUNT register ************************/ + +#define TIMER_COUNT_CNTV_POSS 0U +#define TIMER_COUNT_CNTV_POSE 15U +#define TIMER_COUNT_CNTV_MSK BITS(TIMER_COUNT_CNTV_POSS,TIMER_COUNT_CNTV_POSE) + +/****************** Bit definition for TIMER_PRES register ************************/ + +#define TIMER_PRES_PSCV_POSS 0U +#define TIMER_PRES_PSCV_POSE 15U +#define TIMER_PRES_PSCV_MSK BITS(TIMER_PRES_PSCV_POSS,TIMER_PRES_PSCV_POSE) + +/****************** Bit definition for TIMER_AR register ************************/ + +#define TIMER_AR_ARRV_POSS 0U +#define TIMER_AR_ARRV_POSE 15U +#define TIMER_AR_ARRV_MSK BITS(TIMER_AR_ARRV_POSS,TIMER_AR_ARRV_POSE) + +/****************** Bit definition for TIMER_REPAR register ************************/ + +#define TIMER_REPAR_REPV_POSS 0U +#define TIMER_REPAR_REPV_POSE 7U +#define TIMER_REPAR_REPV_MSK BITS(TIMER_REPAR_REPV_POSS,TIMER_REPAR_REPV_POSE) + +/****************** Bit definition for TIMER_CCVAL1 register ************************/ + +#define TIMER_CCVAL1_CCRV1_POSS 0U +#define TIMER_CCVAL1_CCRV1_POSE 15U +#define TIMER_CCVAL1_CCRV1_MSK BITS(TIMER_CCVAL1_CCRV1_POSS,TIMER_CCVAL1_CCRV1_POSE) + +/****************** Bit definition for TIMER_CCVAL2 register ************************/ + +#define TIMER_CCVAL2_CCRV2_POSS 0U +#define TIMER_CCVAL2_CCRV2_POSE 15U +#define TIMER_CCVAL2_CCRV2_MSK BITS(TIMER_CCVAL2_CCRV2_POSS,TIMER_CCVAL2_CCRV2_POSE) + +/****************** Bit definition for TIMER_CCVAL3 register ************************/ + +#define TIMER_CCVAL3_CCRV3_POSS 0U +#define TIMER_CCVAL3_CCRV3_POSE 15U +#define TIMER_CCVAL3_CCRV3_MSK BITS(TIMER_CCVAL3_CCRV3_POSS,TIMER_CCVAL3_CCRV3_POSE) + +/****************** Bit definition for TIMER_CCVAL4 register ************************/ + +#define TIMER_CCVAL4_CCRV4_POSS 0U +#define TIMER_CCVAL4_CCRV4_POSE 15U +#define TIMER_CCVAL4_CCRV4_MSK BITS(TIMER_CCVAL4_CCRV4_POSS,TIMER_CCVAL4_CCRV4_POSE) + +/****************** Bit definition for TIMER_BDCFG register ************************/ + +#define TIMER_BDCFG_GOEN_POS 15U +#define TIMER_BDCFG_GOEN_MSK BIT(TIMER_BDCFG_GOEN_POS) + +#define TIMER_BDCFG_AOEN_POS 14U +#define TIMER_BDCFG_AOEN_MSK BIT(TIMER_BDCFG_AOEN_POS) + +#define TIMER_BDCFG_BRKP_POS 13U +#define TIMER_BDCFG_BRKP_MSK BIT(TIMER_BDCFG_BRKP_POS) + +#define TIMER_BDCFG_BRKEN_POS 12U +#define TIMER_BDCFG_BRKEN_MSK BIT(TIMER_BDCFG_BRKEN_POS) + +#define TIMER_BDCFG_OFFSSR_POS 11U +#define TIMER_BDCFG_OFFSSR_MSK BIT(TIMER_BDCFG_OFFSSR_POS) + +#define TIMER_BDCFG_OFFSSI_POS 10U +#define TIMER_BDCFG_OFFSSI_MSK BIT(TIMER_BDCFG_OFFSSI_POS) + +#define TIMER_BDCFG_LOCKLVL_POSS 8U +#define TIMER_BDCFG_LOCKLVL_POSE 9U +#define TIMER_BDCFG_LOCKLVL_MSK BITS(TIMER_BDCFG_LOCKLVL_POSS,TIMER_BDCFG_LOCKLVL_POSE) + +#define TIMER_BDCFG_DT_POSS 0U +#define TIMER_BDCFG_DT_POSE 7U +#define TIMER_BDCFG_DT_MSK BITS(TIMER_BDCFG_DT_POSS,TIMER_BDCFG_DT_POSE) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t SMCON; + __O uint32_t DIER; + __O uint32_t DIDR; + __I uint32_t DIVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __O uint32_t SGE; + __IO uint32_t CHMR1; + __IO uint32_t CHMR2; + __IO uint32_t CCEP; + __IO uint32_t COUNT; + __IO uint32_t PRES; + __IO uint32_t AR; + __IO uint32_t REPAR; + __IO uint32_t CCVAL1; + __IO uint32_t CCVAL2; + __IO uint32_t CCVAL3; + __IO uint32_t CCVAL4; + __IO uint32_t BDCFG; +} TIMER_TypeDef; + +/****************** Bit definition for USART_STAT register ************************/ + +#define USART_STAT_CTSIF_POS 9U +#define USART_STAT_CTSIF_MSK BIT(USART_STAT_CTSIF_POS) + +#define USART_STAT_TXEMPIF_POS 7U +#define USART_STAT_TXEMPIF_MSK BIT(USART_STAT_TXEMPIF_POS) + +#define USART_STAT_TXCIF_POS 6U +#define USART_STAT_TXCIF_MSK BIT(USART_STAT_TXCIF_POS) + +#define USART_STAT_RXNEIF_POS 5U +#define USART_STAT_RXNEIF_MSK BIT(USART_STAT_RXNEIF_POS) + +#define USART_STAT_IDLEIF_POS 4U +#define USART_STAT_IDLEIF_MSK BIT(USART_STAT_IDLEIF_POS) + +#define USART_STAT_OVRIF_POS 3U +#define USART_STAT_OVRIF_MSK BIT(USART_STAT_OVRIF_POS) + +#define USART_STAT_NDETIF_POS 2U +#define USART_STAT_NDETIF_MSK BIT(USART_STAT_NDETIF_POS) + +#define USART_STAT_FERRIF_POS 1U +#define USART_STAT_FERRIF_MSK BIT(USART_STAT_FERRIF_POS) + +#define USART_STAT_PERRIF_POS 0U +#define USART_STAT_PERRIF_MSK BIT(USART_STAT_PERRIF_POS) + +/****************** Bit definition for USART_DATA register ************************/ + +#define USART_DATA_VAL_POSS 0U +#define USART_DATA_VAL_POSE 8U +#define USART_DATA_VAL_MSK BITS(USART_DATA_VAL_POSS,USART_DATA_VAL_POSE) + +/****************** Bit definition for USART_BAUDCON register ************************/ + +#define USART_BAUDCON_DIV_M_POSS 4U +#define USART_BAUDCON_DIV_M_POSE 15U +#define USART_BAUDCON_DIV_M_MSK BITS(USART_BAUDCON_DIV_M_POSS,USART_BAUDCON_DIV_M_POSE) + +#define USART_BAUDCON_DIV_F_POSS 0U +#define USART_BAUDCON_DIV_F_POSE 3U +#define USART_BAUDCON_DIV_F_MSK BITS(USART_BAUDCON_DIV_F_POSS,USART_BAUDCON_DIV_F_POSE) + +/****************** Bit definition for USART_CON0 register ************************/ + +#define USART_CON0_EN_POS 13U +#define USART_CON0_EN_MSK BIT(USART_CON0_EN_POS) + +#define USART_CON0_DLEN_POS 12U +#define USART_CON0_DLEN_MSK BIT(USART_CON0_DLEN_POS) + +#define USART_CON0_WKMOD_POS 11U +#define USART_CON0_WKMOD_MSK BIT(USART_CON0_WKMOD_POS) + +#define USART_CON0_PEN_POS 10U +#define USART_CON0_PEN_MSK BIT(USART_CON0_PEN_POS) + +#define USART_CON0_PSEL_POS 9U +#define USART_CON0_PSEL_MSK BIT(USART_CON0_PSEL_POS) + +#define USART_CON0_PERRIE_POS 8U +#define USART_CON0_PERRIE_MSK BIT(USART_CON0_PERRIE_POS) + +#define USART_CON0_TXEMPIE_POS 7U +#define USART_CON0_TXEMPIE_MSK BIT(USART_CON0_TXEMPIE_POS) + +#define USART_CON0_TXCIE_POS 6U +#define USART_CON0_TXCIE_MSK BIT(USART_CON0_TXCIE_POS) + +#define USART_CON0_RXNEIE_POS 5U +#define USART_CON0_RXNEIE_MSK BIT(USART_CON0_RXNEIE_POS) + +#define USART_CON0_IDLEIE_POS 4U +#define USART_CON0_IDLEIE_MSK BIT(USART_CON0_IDLEIE_POS) + +#define USART_CON0_TXEN_POS 3U +#define USART_CON0_TXEN_MSK BIT(USART_CON0_TXEN_POS) + +#define USART_CON0_RXEN_POS 2U +#define USART_CON0_RXEN_MSK BIT(USART_CON0_RXEN_POS) + +#define USART_CON0_RXWK_POS 1U +#define USART_CON0_RXWK_MSK BIT(USART_CON0_RXWK_POS) + +/****************** Bit definition for USART_CON1 register ************************/ + +#define USART_CON1_STPLEN_POSS 12U +#define USART_CON1_STPLEN_POSE 13U +#define USART_CON1_STPLEN_MSK BITS(USART_CON1_STPLEN_POSS,USART_CON1_STPLEN_POSE) + +#define USART_CON1_SCKEN_POS 11U +#define USART_CON1_SCKEN_MSK BIT(USART_CON1_SCKEN_POS) + +#define USART_CON1_SCKPOL_POS 10U +#define USART_CON1_SCKPOL_MSK BIT(USART_CON1_SCKPOL_POS) + +#define USART_CON1_SCKPHA_POS 9U +#define USART_CON1_SCKPHA_MSK BIT(USART_CON1_SCKPHA_POS) + +#define USART_CON1_LBCP_POS 8U +#define USART_CON1_LBCP_MSK BIT(USART_CON1_LBCP_POS) + +#define USART_CON1_ADDR_POSS 0U +#define USART_CON1_ADDR_POSE 3U +#define USART_CON1_ADDR_MSK BITS(USART_CON1_ADDR_POSS,USART_CON1_ADDR_POSE) + +/****************** Bit definition for USART_CON2 register ************************/ + +#define USART_CON2_CTSIE_POS 10U +#define USART_CON2_CTSIE_MSK BIT(USART_CON2_CTSIE_POS) + +#define USART_CON2_CTSEN_POS 9U +#define USART_CON2_CTSEN_MSK BIT(USART_CON2_CTSEN_POS) + +#define USART_CON2_RTSEN_POS 8U +#define USART_CON2_RTSEN_MSK BIT(USART_CON2_RTSEN_POS) + +#define USART_CON2_TXDMAEN_POS 7U +#define USART_CON2_TXDMAEN_MSK BIT(USART_CON2_TXDMAEN_POS) + +#define USART_CON2_RXDMAEN_POS 6U +#define USART_CON2_RXDMAEN_MSK BIT(USART_CON2_RXDMAEN_POS) + +#define USART_CON2_SMARTEN_POS 5U +#define USART_CON2_SMARTEN_MSK BIT(USART_CON2_SMARTEN_POS) + +#define USART_CON2_NACK_POS 4U +#define USART_CON2_NACK_MSK BIT(USART_CON2_NACK_POS) + +#define USART_CON2_HDPSEL_POS 3U +#define USART_CON2_HDPSEL_MSK BIT(USART_CON2_HDPSEL_POS) + +#define USART_CON2_IREN_POS 1U +#define USART_CON2_IREN_MSK BIT(USART_CON2_IREN_POS) + +#define USART_CON2_ERRIE_POS 0U +#define USART_CON2_ERRIE_MSK BIT(USART_CON2_ERRIE_POS) + +/****************** Bit definition for USART_GP register ************************/ + +#define USART_GP_GTVAL_POSS 8U +#define USART_GP_GTVAL_POSE 15U +#define USART_GP_GTVAL_MSK BITS(USART_GP_GTVAL_POSS,USART_GP_GTVAL_POSE) + +#define USART_GP_PSC_POSS 0U +#define USART_GP_PSC_POSE 7U +#define USART_GP_PSC_MSK BITS(USART_GP_PSC_POSS,USART_GP_PSC_POSE) + +typedef struct +{ + __IO uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t BAUDCON; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t GP; +} USART_TypeDef; + +/****************** Bit definition for UART_RBR register ************************/ + +#define UART_RBR_RBR_POSS 0U +#define UART_RBR_RBR_POSE 8U +#define UART_RBR_RBR_MSK BITS(UART_RBR_RBR_POSS,UART_RBR_RBR_POSE) + +/****************** Bit definition for UART_TBR register ************************/ + +#define UART_TBR_TBR_POSS 0U +#define UART_TBR_TBR_POSE 8U +#define UART_TBR_TBR_MSK BITS(UART_TBR_TBR_POSS,UART_TBR_TBR_POSE) + +/****************** Bit definition for UART_BRR register ************************/ + +#define UART_BRR_BRR_POSS 0U +#define UART_BRR_BRR_POSE 15U +#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) + +/****************** Bit definition for UART_LCR register ************************/ + +#define UART_LCR_SWAP_POS 13U +#define UART_LCR_SWAP_MSK BIT(UART_LCR_SWAP_POS) + +#define UART_LCR_TXINV_POS 12U +#define UART_LCR_TXINV_MSK BIT(UART_LCR_TXINV_POS) + +#define UART_LCR_RXINV_POS 11U +#define UART_LCR_RXINV_MSK BIT(UART_LCR_RXINV_POS) + +#define UART_LCR_DATAINV_POS 10U +#define UART_LCR_DATAINV_MSK BIT(UART_LCR_DATAINV_POS) + +#define UART_LCR_MSBFIRST_POS 9U +#define UART_LCR_MSBFIRST_MSK BIT(UART_LCR_MSBFIRST_POS) + +#define UART_LCR_RTOEN_POS 8U +#define UART_LCR_RTOEN_MSK BIT(UART_LCR_RTOEN_POS) + +#define UART_LCR_BRWEN_POS 7U +#define UART_LCR_BRWEN_MSK BIT(UART_LCR_BRWEN_POS) + +#define UART_LCR_BC_POS 6U +#define UART_LCR_BC_MSK BIT(UART_LCR_BC_POS) + +#define UART_LCR_RXEN_POS 5U +#define UART_LCR_RXEN_MSK BIT(UART_LCR_RXEN_POS) + +#define UART_LCR_PS_POS 4U +#define UART_LCR_PS_MSK BIT(UART_LCR_PS_POS) + +#define UART_LCR_PEN_POS 3U +#define UART_LCR_PEN_MSK BIT(UART_LCR_PEN_POS) + +#define UART_LCR_STOP_POS 2U +#define UART_LCR_STOP_MSK BIT(UART_LCR_STOP_POS) + +#define UART_LCR_DLS_POSS 0U +#define UART_LCR_DLS_POSE 1U +#define UART_LCR_DLS_MSK BITS(UART_LCR_DLS_POSS,UART_LCR_DLS_POSE) + +/****************** Bit definition for UART_MCR register ************************/ + +#define UART_MCR_HDSEL_POS 22U +#define UART_MCR_HDSEL_MSK BIT(UART_MCR_HDSEL_POS) + +#define UART_MCR_ABRRS_POS 15U +#define UART_MCR_ABRRS_MSK BIT(UART_MCR_ABRRS_POS) + +#define UART_MCR_ABRMOD_POSS 13U +#define UART_MCR_ABRMOD_POSE 14U +#define UART_MCR_ABRMOD_MSK BITS(UART_MCR_ABRMOD_POSS,UART_MCR_ABRMOD_POSE) + +#define UART_MCR_ABREN_POS 12U +#define UART_MCR_ABREN_MSK BIT(UART_MCR_ABREN_POS) + +#define UART_MCR_DMAEN_POS 11U +#define UART_MCR_DMAEN_MSK BIT(UART_MCR_DMAEN_POS) + +#define UART_MCR_LINBDL_POS 10U +#define UART_MCR_LINBDL_MSK BIT(UART_MCR_LINBDL_POS) + +#define UART_MCR_BKREQ_POS 9U +#define UART_MCR_BKREQ_MSK BIT(UART_MCR_BKREQ_POS) + +#define UART_MCR_LINEN_POS 8U +#define UART_MCR_LINEN_MSK BIT(UART_MCR_LINEN_POS) + +#define UART_MCR_AADINV_POS 7U +#define UART_MCR_AADINV_MSK BIT(UART_MCR_AADINV_POS) + +#define UART_MCR_AADDIR_POS 6U +#define UART_MCR_AADDIR_MSK BIT(UART_MCR_AADDIR_POS) + +#define UART_MCR_AADNOR_POS 5U +#define UART_MCR_AADNOR_MSK BIT(UART_MCR_AADNOR_POS) + +#define UART_MCR_AADEN_POS 4U +#define UART_MCR_AADEN_MSK BIT(UART_MCR_AADEN_POS) + +#define UART_MCR_RTSCTRL_POS 3U +#define UART_MCR_RTSCTRL_MSK BIT(UART_MCR_RTSCTRL_POS) + +#define UART_MCR_AFCEN_POS 2U +#define UART_MCR_AFCEN_MSK BIT(UART_MCR_AFCEN_POS) + +#define UART_MCR_LBEN_POS 1U +#define UART_MCR_LBEN_MSK BIT(UART_MCR_LBEN_POS) + +#define UART_MCR_IREN_POS 0U +#define UART_MCR_IREN_MSK BIT(UART_MCR_IREN_POS) + +/****************** Bit definition for UART_CR register ************************/ + +#define UART_CR_PSC_POSS 16U +#define UART_CR_PSC_POSE 23U +#define UART_CR_PSC_MSK BITS(UART_CR_PSC_POSS,UART_CR_PSC_POSE) + +#define UART_CR_DLY_POSS 8U +#define UART_CR_DLY_POSE 15U +#define UART_CR_DLY_MSK BITS(UART_CR_DLY_POSS,UART_CR_DLY_POSE) + +#define UART_CR_ADDR_POSS 0U +#define UART_CR_ADDR_POSE 7U +#define UART_CR_ADDR_MSK BITS(UART_CR_ADDR_POSS,UART_CR_ADDR_POSE) + +/****************** Bit definition for UART_RTOR register ************************/ + +#define UART_RTOR_BLEN_POSS 24U +#define UART_RTOR_BLEN_POSE 31U +#define UART_RTOR_BLEN_MSK BITS(UART_RTOR_BLEN_POSS,UART_RTOR_BLEN_POSE) + +#define UART_RTOR_RTO_POSS 0U +#define UART_RTOR_RTO_POSE 23U +#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) + +/****************** Bit definition for UART_FCR register ************************/ + +#define UART_FCR_TXFL_POSS 12U +#define UART_FCR_TXFL_POSE 15U +#define UART_FCR_TXFL_MSK BITS(UART_FCR_TXFL_POSS,UART_FCR_TXFL_POSE) + +#define UART_FCR_RXFL_POSS 8U +#define UART_FCR_RXFL_POSE 11U +#define UART_FCR_RXFL_MSK BITS(UART_FCR_RXFL_POSS,UART_FCR_RXFL_POSE) + +#define UART_FCR_TXTL_POSS 6U +#define UART_FCR_TXTL_POSE 7U +#define UART_FCR_TXTL_MSK BITS(UART_FCR_TXTL_POSS,UART_FCR_TXTL_POSE) + +#define UART_FCR_RXTL_POSS 4U +#define UART_FCR_RXTL_POSE 5U +#define UART_FCR_RXTL_MSK BITS(UART_FCR_RXTL_POSS,UART_FCR_RXTL_POSE) + +#define UART_FCR_TFRST_POS 2U +#define UART_FCR_TFRST_MSK BIT(UART_FCR_TFRST_POS) + +#define UART_FCR_RFRST_POS 1U +#define UART_FCR_RFRST_MSK BIT(UART_FCR_RFRST_POS) + +#define UART_FCR_FIFOEN_POS 0U +#define UART_FCR_FIFOEN_MSK BIT(UART_FCR_FIFOEN_POS) + +/****************** Bit definition for UART_SR register ************************/ + +#define UART_SR_CTS_POS 14U +#define UART_SR_CTS_MSK BIT(UART_SR_CTS_POS) + +#define UART_SR_DCTS_POS 13U +#define UART_SR_DCTS_MSK BIT(UART_SR_DCTS_POS) + +#define UART_SR_RFF_POS 12U +#define UART_SR_RFF_MSK BIT(UART_SR_RFF_POS) + +#define UART_SR_RFNE_POS 11U +#define UART_SR_RFNE_MSK BIT(UART_SR_RFNE_POS) + +#define UART_SR_TFEM_POS 10U +#define UART_SR_TFEM_MSK BIT(UART_SR_TFEM_POS) + +#define UART_SR_TFNF_POS 9U +#define UART_SR_TFNF_MSK BIT(UART_SR_TFNF_POS) + +#define UART_SR_BUSY_POS 8U +#define UART_SR_BUSY_MSK BIT(UART_SR_BUSY_POS) + +#define UART_SR_RFE_POS 7U +#define UART_SR_RFE_MSK BIT(UART_SR_RFE_POS) + +#define UART_SR_TEM_POS 6U +#define UART_SR_TEM_MSK BIT(UART_SR_TEM_POS) + +#define UART_SR_TBEM_POS 5U +#define UART_SR_TBEM_MSK BIT(UART_SR_TBEM_POS) + +#define UART_SR_BF_POS 4U +#define UART_SR_BF_MSK BIT(UART_SR_BF_POS) + +#define UART_SR_FE_POS 3U +#define UART_SR_FE_MSK BIT(UART_SR_FE_POS) + +#define UART_SR_PE_POS 2U +#define UART_SR_PE_MSK BIT(UART_SR_PE_POS) + +#define UART_SR_OE_POS 1U +#define UART_SR_OE_MSK BIT(UART_SR_OE_POS) + +#define UART_SR_DR_POS 0U +#define UART_SR_DR_MSK BIT(UART_SR_DR_POS) + +/****************** Bit definition for UART_IER register ************************/ + +#define UART_IER_CMIE_POS 11U +#define UART_IER_CMIE_MSK BIT(UART_IER_CMIE_POS) + +#define UART_IER_EOBIE_POS 10U +#define UART_IER_EOBIE_MSK BIT(UART_IER_EOBIE_POS) + +#define UART_IER_TCIE_POS 9U +#define UART_IER_TCIE_MSK BIT(UART_IER_TCIE_POS) + +#define UART_IER_LINBKIE_POS 8U +#define UART_IER_LINBKIE_MSK BIT(UART_IER_LINBKIE_POS) + +#define UART_IER_ABTOIE_POS 7U +#define UART_IER_ABTOIE_MSK BIT(UART_IER_ABTOIE_POS) + +#define UART_IER_ABEIE_POS 6U +#define UART_IER_ABEIE_MSK BIT(UART_IER_ABEIE_POS) + +#define UART_IER_BZIE_POS 5U +#define UART_IER_BZIE_MSK BIT(UART_IER_BZIE_POS) + +#define UART_IER_RTOIE_POS 4U +#define UART_IER_RTOIE_MSK BIT(UART_IER_RTOIE_POS) + +#define UART_IER_MDSIE_POS 3U +#define UART_IER_MDSIE_MSK BIT(UART_IER_MDSIE_POS) + +#define UART_IER_RXSIE_POS 2U +#define UART_IER_RXSIE_MSK BIT(UART_IER_RXSIE_POS) + +#define UART_IER_TXSIE_POS 1U +#define UART_IER_TXSIE_MSK BIT(UART_IER_TXSIE_POS) + +#define UART_IER_RXRDIE_POS 0U +#define UART_IER_RXRDIE_MSK BIT(UART_IER_RXRDIE_POS) + +/****************** Bit definition for UART_IDR register ************************/ + +#define UART_IDR_CMID_POS 11U +#define UART_IDR_CMID_MSK BIT(UART_IDR_CMID_POS) + +#define UART_IDR_EOBID_POS 10U +#define UART_IDR_EOBID_MSK BIT(UART_IDR_EOBID_POS) + +#define UART_IDR_TCID_POS 9U +#define UART_IDR_TCID_MSK BIT(UART_IDR_TCID_POS) + +#define UART_IDR_LINBKID_POS 8U +#define UART_IDR_LINBKID_MSK BIT(UART_IDR_LINBKID_POS) + +#define UART_IDR_ABTOID_POS 7U +#define UART_IDR_ABTOID_MSK BIT(UART_IDR_ABTOID_POS) + +#define UART_IDR_ABEID_POS 6U +#define UART_IDR_ABEID_MSK BIT(UART_IDR_ABEID_POS) + +#define UART_IDR_BZID_POS 5U +#define UART_IDR_BZID_MSK BIT(UART_IDR_BZID_POS) + +#define UART_IDR_RTOID_POS 4U +#define UART_IDR_RTOID_MSK BIT(UART_IDR_RTOID_POS) + +#define UART_IDR_MDSID_POS 3U +#define UART_IDR_MDSID_MSK BIT(UART_IDR_MDSID_POS) + +#define UART_IDR_RXSID_POS 2U +#define UART_IDR_RXSID_MSK BIT(UART_IDR_RXSID_POS) + +#define UART_IDR_TXSID_POS 1U +#define UART_IDR_TXSID_MSK BIT(UART_IDR_TXSID_POS) + +#define UART_IDR_RXRDID_POS 0U +#define UART_IDR_RXRDID_MSK BIT(UART_IDR_RXRDID_POS) + +/****************** Bit definition for UART_IVS register ************************/ + +#define UART_IVS_CMIS_POS 11U +#define UART_IVS_CMIS_MSK BIT(UART_IVS_CMIS_POS) + +#define UART_IVS_EOBIS_POS 10U +#define UART_IVS_EOBIS_MSK BIT(UART_IVS_EOBIS_POS) + +#define UART_IVS_TCIS_POS 9U +#define UART_IVS_TCIS_MSK BIT(UART_IVS_TCIS_POS) + +#define UART_IVS_LINBKIS_POS 8U +#define UART_IVS_LINBKIS_MSK BIT(UART_IVS_LINBKIS_POS) + +#define UART_IVS_ABTOIS_POS 7U +#define UART_IVS_ABTOIS_MSK BIT(UART_IVS_ABTOIS_POS) + +#define UART_IVS_ABEIS_POS 6U +#define UART_IVS_ABEIS_MSK BIT(UART_IVS_ABEIS_POS) + +#define UART_IVS_BZIS_POS 5U +#define UART_IVS_BZIS_MSK BIT(UART_IVS_BZIS_POS) + +#define UART_IVS_RTOIS_POS 4U +#define UART_IVS_RTOIS_MSK BIT(UART_IVS_RTOIS_POS) + +#define UART_IVS_MDSIS_POS 3U +#define UART_IVS_MDSIS_MSK BIT(UART_IVS_MDSIS_POS) + +#define UART_IVS_RXSIS_POS 2U +#define UART_IVS_RXSIS_MSK BIT(UART_IVS_RXSIS_POS) + +#define UART_IVS_TXSIS_POS 1U +#define UART_IVS_TXSIS_MSK BIT(UART_IVS_TXSIS_POS) + +#define UART_IVS_RXRDIS_POS 0U +#define UART_IVS_RXRDIS_MSK BIT(UART_IVS_RXRDIS_POS) + +/****************** Bit definition for UART_RIF register ************************/ + +#define UART_RIF_CMIF_POS 11U +#define UART_RIF_CMIF_MSK BIT(UART_RIF_CMIF_POS) + +#define UART_RIF_EOBIF_POS 10U +#define UART_RIF_EOBIF_MSK BIT(UART_RIF_EOBIF_POS) + +#define UART_RIF_TCIF_POS 9U +#define UART_RIF_TCIF_MSK BIT(UART_RIF_TCIF_POS) + +#define UART_RIF_LINBKIF_POS 8U +#define UART_RIF_LINBKIF_MSK BIT(UART_RIF_LINBKIF_POS) + +#define UART_RIF_ABTOIF_POS 7U +#define UART_RIF_ABTOIF_MSK BIT(UART_RIF_ABTOIF_POS) + +#define UART_RIF_ABEIF_POS 6U +#define UART_RIF_ABEIF_MSK BIT(UART_RIF_ABEIF_POS) + +#define UART_RIF_BZIF_POS 5U +#define UART_RIF_BZIF_MSK BIT(UART_RIF_BZIF_POS) + +#define UART_RIF_RTOIF_POS 4U +#define UART_RIF_RTOIF_MSK BIT(UART_RIF_RTOIF_POS) + +#define UART_RIF_MDSIF_POS 3U +#define UART_RIF_MDSIF_MSK BIT(UART_RIF_MDSIF_POS) + +#define UART_RIF_RXSIF_POS 2U +#define UART_RIF_RXSIF_MSK BIT(UART_RIF_RXSIF_POS) + +#define UART_RIF_TXSIF_POS 1U +#define UART_RIF_TXSIF_MSK BIT(UART_RIF_TXSIF_POS) + +#define UART_RIF_RXRDIF_POS 0U +#define UART_RIF_RXRDIF_MSK BIT(UART_RIF_RXRDIF_POS) + +/****************** Bit definition for UART_IFM register ************************/ + +#define UART_IFM_CMIM_POS 11U +#define UART_IFM_CMIM_MSK BIT(UART_IFM_CMIM_POS) + +#define UART_IFM_EOBIM_POS 10U +#define UART_IFM_EOBIM_MSK BIT(UART_IFM_EOBIM_POS) + +#define UART_IFM_TCIM_POS 9U +#define UART_IFM_TCIM_MSK BIT(UART_IFM_TCIM_POS) + +#define UART_IFM_LINBKIM_POS 8U +#define UART_IFM_LINBKIM_MSK BIT(UART_IFM_LINBKIM_POS) + +#define UART_IFM_ABTOIM_POS 7U +#define UART_IFM_ABTOIM_MSK BIT(UART_IFM_ABTOIM_POS) + +#define UART_IFM_ABEIM_POS 6U +#define UART_IFM_ABEIM_MSK BIT(UART_IFM_ABEIM_POS) + +#define UART_IFM_BZIM_POS 5U +#define UART_IFM_BZIM_MSK BIT(UART_IFM_BZIM_POS) + +#define UART_IFM_RTOIM_POS 4U +#define UART_IFM_RTOIM_MSK BIT(UART_IFM_RTOIM_POS) + +#define UART_IFM_MDSIM_POS 3U +#define UART_IFM_MDSIM_MSK BIT(UART_IFM_MDSIM_POS) + +#define UART_IFM_RXSIM_POS 2U +#define UART_IFM_RXSIM_MSK BIT(UART_IFM_RXSIM_POS) + +#define UART_IFM_TXSIM_POS 1U +#define UART_IFM_TXSIM_MSK BIT(UART_IFM_TXSIM_POS) + +#define UART_IFM_RXRDIM_POS 0U +#define UART_IFM_RXRDIM_MSK BIT(UART_IFM_RXRDIM_POS) + +/****************** Bit definition for UART_ICR register ************************/ + +#define UART_ICR_CMIC_POS 11U +#define UART_ICR_CMIC_MSK BIT(UART_ICR_CMIC_POS) + +#define UART_ICR_EOBIC_POS 10U +#define UART_ICR_EOBIC_MSK BIT(UART_ICR_EOBIC_POS) + +#define UART_ICR_TCIC_POS 9U +#define UART_ICR_TCIC_MSK BIT(UART_ICR_TCIC_POS) + +#define UART_ICR_LINBKIC_POS 8U +#define UART_ICR_LINBKIC_MSK BIT(UART_ICR_LINBKIC_POS) + +#define UART_ICR_ABTOIC_POS 7U +#define UART_ICR_ABTOIC_MSK BIT(UART_ICR_ABTOIC_POS) + +#define UART_ICR_ABEIC_POS 6U +#define UART_ICR_ABEIC_MSK BIT(UART_ICR_ABEIC_POS) + +#define UART_ICR_BZIC_POS 5U +#define UART_ICR_BZIC_MSK BIT(UART_ICR_BZIC_POS) + +#define UART_ICR_CHTOIC_POS 4U +#define UART_ICR_CHTOIC_MSK BIT(UART_ICR_CHTOIC_POS) + +#define UART_ICR_MDSIC_POS 3U +#define UART_ICR_MDSIC_MSK BIT(UART_ICR_MDSIC_POS) + +#define UART_ICR_RXSIC_POS 2U +#define UART_ICR_RXSIC_MSK BIT(UART_ICR_RXSIC_POS) + +#define UART_ICR_TXSIC_POS 1U +#define UART_ICR_TXSIC_MSK BIT(UART_ICR_TXSIC_POS) + +#define UART_ICR_RXRDIC_POS 0U +#define UART_ICR_RXRDIC_MSK BIT(UART_ICR_RXRDIC_POS) + +typedef struct +{ + __I uint32_t RBR; + __IO uint32_t TBR; + __IO uint32_t BRR; + __IO uint32_t LCR; + __IO uint32_t MCR; + __IO uint32_t CR; + __IO uint32_t RTOR; + __IO uint32_t FCR; + __I uint32_t SR; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} UART_TypeDef; + +/****************** Bit definition for LPUART_CON0 register ************************/ + +#define LPUART_CON0_MODESEL_POSS 30U +#define LPUART_CON0_MODESEL_POSE 31U +#define LPUART_CON0_MODESEL_MSK BITS(LPUART_CON0_MODESEL_POSS,LPUART_CON0_MODESEL_POSE) + +#define LPUART_CON0_TXDMAE_POS 29U +#define LPUART_CON0_TXDMAE_MSK BIT(LPUART_CON0_TXDMAE_POS) + +#define LPUART_CON0_RXDMAE_POS 28U +#define LPUART_CON0_RXDMAE_MSK BIT(LPUART_CON0_RXDMAE_POS) + +#define LPUART_CON0_INTERVAL_POSS 16U +#define LPUART_CON0_INTERVAL_POSE 23U +#define LPUART_CON0_INTERVAL_MSK BITS(LPUART_CON0_INTERVAL_POSS,LPUART_CON0_INTERVAL_POSE) + +#define LPUART_CON0_SYNCBP_POS 15U +#define LPUART_CON0_SYNCBP_MSK BIT(LPUART_CON0_SYNCBP_POS) + +#define LPUART_CON0_CTSPOL_POS 13U +#define LPUART_CON0_CTSPOL_MSK BIT(LPUART_CON0_CTSPOL_POS) + +#define LPUART_CON0_RTSPOL_POS 12U +#define LPUART_CON0_RTSPOL_MSK BIT(LPUART_CON0_RTSPOL_POS) + +#define LPUART_CON0_ATCTSE_POS 11U +#define LPUART_CON0_ATCTSE_MSK BIT(LPUART_CON0_ATCTSE_POS) + +#define LPUART_CON0_ATRTSE_POS 10U +#define LPUART_CON0_ATRTSE_MSK BIT(LPUART_CON0_ATRTSE_POS) + +#define LPUART_CON0_BRKCE_POS 8U +#define LPUART_CON0_BRKCE_MSK BIT(LPUART_CON0_BRKCE_POS) + +#define LPUART_CON0_LPBMOD_POS 7U +#define LPUART_CON0_LPBMOD_MSK BIT(LPUART_CON0_LPBMOD_POS) + +#define LPUART_CON0_STICKPARSEL_POS 6U +#define LPUART_CON0_STICKPARSEL_MSK BIT(LPUART_CON0_STICKPARSEL_POS) + +#define LPUART_CON0_EVENPARSEL_POS 5U +#define LPUART_CON0_EVENPARSEL_MSK BIT(LPUART_CON0_EVENPARSEL_POS) + +#define LPUART_CON0_PARCHKE_POS 4U +#define LPUART_CON0_PARCHKE_MSK BIT(LPUART_CON0_PARCHKE_POS) + +#define LPUART_CON0_STPLENTH_POS 3U +#define LPUART_CON0_STPLENTH_MSK BIT(LPUART_CON0_STPLENTH_POS) + +#define LPUART_CON0_DATLENTH_POSS 0U +#define LPUART_CON0_DATLENTH_POSE 2U +#define LPUART_CON0_DATLENTH_MSK BITS(LPUART_CON0_DATLENTH_POSS,LPUART_CON0_DATLENTH_POSE) + +/****************** Bit definition for LPUART_CON1 register ************************/ + +#define LPUART_CON1_ADDCMP_POSS 24U +#define LPUART_CON1_ADDCMP_POSE 31U +#define LPUART_CON1_ADDCMP_MSK BITS(LPUART_CON1_ADDCMP_POSS,LPUART_CON1_ADDCMP_POSE) + +#define LPUART_CON1_ADETE_POS 23U +#define LPUART_CON1_ADETE_MSK BIT(LPUART_CON1_ADETE_POS) + +#define LPUART_CON1_ATDIRM_POS 22U +#define LPUART_CON1_ATDIRM_MSK BIT(LPUART_CON1_ATDIRM_POS) + +#define LPUART_CON1_ATADETE_POS 21U +#define LPUART_CON1_ATADETE_MSK BIT(LPUART_CON1_ATADETE_POS) + +#define LPUART_CON1_NMPMOD_POS 20U +#define LPUART_CON1_NMPMOD_MSK BIT(LPUART_CON1_NMPMOD_POS) + +#define LPUART_CON1_IRWIDTH_POS 16U +#define LPUART_CON1_IRWIDTH_MSK BIT(LPUART_CON1_IRWIDTH_POS) + +#define LPUART_CON1_TOICMP_POSS 8U +#define LPUART_CON1_TOICMP_POSE 15U +#define LPUART_CON1_TOICMP_MSK BITS(LPUART_CON1_TOICMP_POSS,LPUART_CON1_TOICMP_POSE) + +#define LPUART_CON1_TOCNTE_POS 7U +#define LPUART_CON1_TOCNTE_MSK BIT(LPUART_CON1_TOCNTE_POS) + +#define LPUART_CON1_IRTXINV_POS 3U +#define LPUART_CON1_IRTXINV_MSK BIT(LPUART_CON1_IRTXINV_POS) + +#define LPUART_CON1_IRRXINV_POS 2U +#define LPUART_CON1_IRRXINV_MSK BIT(LPUART_CON1_IRRXINV_POS) + +#define LPUART_CON1_IRTXE_POS 1U +#define LPUART_CON1_IRTXE_MSK BIT(LPUART_CON1_IRTXE_POS) + +#define LPUART_CON1_RTS_POS 0U +#define LPUART_CON1_RTS_MSK BIT(LPUART_CON1_RTS_POS) + +/****************** Bit definition for LPUART_CLKDIV register ************************/ + +#define LPUART_CLKDIV_CLKDIV_POSS 0U +#define LPUART_CLKDIV_CLKDIV_POSE 19U +#define LPUART_CLKDIV_CLKDIV_MSK BITS(LPUART_CLKDIV_CLKDIV_POSS,LPUART_CLKDIV_CLKDIV_POSE) + +/****************** Bit definition for LPUART_FIFOCON register ************************/ + +#define LPUART_FIFOCON_RTSTRGLVL_POSS 12U +#define LPUART_FIFOCON_RTSTRGLVL_POSE 15U +#define LPUART_FIFOCON_RTSTRGLVL_MSK BITS(LPUART_FIFOCON_RTSTRGLVL_POSS,LPUART_FIFOCON_RTSTRGLVL_POSE) + +#define LPUART_FIFOCON_RXTRGLVL_POSS 8U +#define LPUART_FIFOCON_RXTRGLVL_POSE 11U +#define LPUART_FIFOCON_RXTRGLVL_MSK BITS(LPUART_FIFOCON_RXTRGLVL_POSS,LPUART_FIFOCON_RXTRGLVL_POSE) + +#define LPUART_FIFOCON_NMPMRXDIS_POS 2U +#define LPUART_FIFOCON_NMPMRXDIS_MSK BIT(LPUART_FIFOCON_NMPMRXDIS_POS) + +#define LPUART_FIFOCON_TXRESET_POS 1U +#define LPUART_FIFOCON_TXRESET_MSK BIT(LPUART_FIFOCON_TXRESET_POS) + +#define LPUART_FIFOCON_RXRESET_POS 0U +#define LPUART_FIFOCON_RXRESET_MSK BIT(LPUART_FIFOCON_RXRESET_POS) + +/****************** Bit definition for LPUART_RXDR register ************************/ + +#define LPUART_RXDR_FERR_POS 15U +#define LPUART_RXDR_FERR_MSK BIT(LPUART_RXDR_FERR_POS) + +#define LPUART_RXDR_PERR_POS 14U +#define LPUART_RXDR_PERR_MSK BIT(LPUART_RXDR_PERR_POS) + +#define LPUART_RXDR_RXDR_POSS 0U +#define LPUART_RXDR_RXDR_POSE 8U +#define LPUART_RXDR_RXDR_MSK BITS(LPUART_RXDR_RXDR_POSS,LPUART_RXDR_RXDR_POSE) + +/****************** Bit definition for LPUART_TXDR register ************************/ + +#define LPUART_TXDR_TXDR_POSS 0U +#define LPUART_TXDR_TXDR_POSE 8U +#define LPUART_TXDR_TXDR_MSK BITS(LPUART_TXDR_TXDR_POSS,LPUART_TXDR_TXDR_POSE) + +/****************** Bit definition for LPUART_STAT register ************************/ + +#define LPUART_STAT_RTSSTAT_POS 18U +#define LPUART_STAT_RTSSTAT_MSK BIT(LPUART_STAT_RTSSTAT_POS) + +#define LPUART_STAT_CTSSTAT_POS 17U +#define LPUART_STAT_CTSSTAT_MSK BIT(LPUART_STAT_CTSSTAT_POS) + +#define LPUART_STAT_TXIDLE_POS 16U +#define LPUART_STAT_TXIDLE_MSK BIT(LPUART_STAT_TXIDLE_POS) + +#define LPUART_STAT_TXFULL_POS 15U +#define LPUART_STAT_TXFULL_MSK BIT(LPUART_STAT_TXFULL_POS) + +#define LPUART_STAT_TXEMP_POS 14U +#define LPUART_STAT_TXEMP_MSK BIT(LPUART_STAT_TXEMP_POS) + +#define LPUART_STAT_TXPTR_POSS 8U +#define LPUART_STAT_TXPTR_POSE 13U +#define LPUART_STAT_TXPTR_MSK BITS(LPUART_STAT_TXPTR_POSS,LPUART_STAT_TXPTR_POSE) + +#define LPUART_STAT_RXFULL_POS 7U +#define LPUART_STAT_RXFULL_MSK BIT(LPUART_STAT_RXFULL_POS) + +#define LPUART_STAT_RXEMP_POS 6U +#define LPUART_STAT_RXEMP_MSK BIT(LPUART_STAT_RXEMP_POS) + +#define LPUART_STAT_RXPTR_POSS 0U +#define LPUART_STAT_RXPTR_POSE 5U +#define LPUART_STAT_RXPTR_MSK BITS(LPUART_STAT_RXPTR_POSS,LPUART_STAT_RXPTR_POSE) + +/****************** Bit definition for LPUART_IER register ************************/ + +#define LPUART_IER_TCIE_POS 15U +#define LPUART_IER_TCIE_MSK BIT(LPUART_IER_TCIE_POS) + +#define LPUART_IER_ADETIE_POS 12U +#define LPUART_IER_ADETIE_MSK BIT(LPUART_IER_ADETIE_POS) + +#define LPUART_IER_BRKERRIE_POS 11U +#define LPUART_IER_BRKERRIE_MSK BIT(LPUART_IER_BRKERRIE_POS) + +#define LPUART_IER_FERRIE_POS 10U +#define LPUART_IER_FERRIE_MSK BIT(LPUART_IER_FERRIE_POS) + +#define LPUART_IER_PERRIE_POS 9U +#define LPUART_IER_PERRIE_MSK BIT(LPUART_IER_PERRIE_POS) + +#define LPUART_IER_DATWKIE_POS 8U +#define LPUART_IER_DATWKIE_MSK BIT(LPUART_IER_DATWKIE_POS) + +#define LPUART_IER_CTSWKIE_POS 7U +#define LPUART_IER_CTSWKIE_MSK BIT(LPUART_IER_CTSWKIE_POS) + +#define LPUART_IER_TXOVIE_POS 5U +#define LPUART_IER_TXOVIE_MSK BIT(LPUART_IER_TXOVIE_POS) + +#define LPUART_IER_RXOVIE_POS 4U +#define LPUART_IER_RXOVIE_MSK BIT(LPUART_IER_RXOVIE_POS) + +#define LPUART_IER_RXTOIE_POS 3U +#define LPUART_IER_RXTOIE_MSK BIT(LPUART_IER_RXTOIE_POS) + +#define LPUART_IER_CTSDETIE_POS 2U +#define LPUART_IER_CTSDETIE_MSK BIT(LPUART_IER_CTSDETIE_POS) + +#define LPUART_IER_TBEMPIE_POS 1U +#define LPUART_IER_TBEMPIE_MSK BIT(LPUART_IER_TBEMPIE_POS) + +#define LPUART_IER_RBRIE_POS 0U +#define LPUART_IER_RBRIE_MSK BIT(LPUART_IER_RBRIE_POS) + +/****************** Bit definition for LPUART_IFLAG register ************************/ + +#define LPUART_IFLAG_TCIF_POS 15U +#define LPUART_IFLAG_TCIF_MSK BIT(LPUART_IFLAG_TCIF_POS) + +#define LPUART_IFLAG_ADETIF_POS 12U +#define LPUART_IFLAG_ADETIF_MSK BIT(LPUART_IFLAG_ADETIF_POS) + +#define LPUART_IFLAG_BRKERRIF_POS 11U +#define LPUART_IFLAG_BRKERRIF_MSK BIT(LPUART_IFLAG_BRKERRIF_POS) + +#define LPUART_IFLAG_FERRIF_POS 10U +#define LPUART_IFLAG_FERRIF_MSK BIT(LPUART_IFLAG_FERRIF_POS) + +#define LPUART_IFLAG_PERRIF_POS 9U +#define LPUART_IFLAG_PERRIF_MSK BIT(LPUART_IFLAG_PERRIF_POS) + +#define LPUART_IFLAG_DATWKIF_POS 8U +#define LPUART_IFLAG_DATWKIF_MSK BIT(LPUART_IFLAG_DATWKIF_POS) + +#define LPUART_IFLAG_CTSWKIF_POS 7U +#define LPUART_IFLAG_CTSWKIF_MSK BIT(LPUART_IFLAG_CTSWKIF_POS) + +#define LPUART_IFLAG_TXOVIF_POS 5U +#define LPUART_IFLAG_TXOVIF_MSK BIT(LPUART_IFLAG_TXOVIF_POS) + +#define LPUART_IFLAG_RXOVIF_POS 4U +#define LPUART_IFLAG_RXOVIF_MSK BIT(LPUART_IFLAG_RXOVIF_POS) + +#define LPUART_IFLAG_RXTOIF_POS 3U +#define LPUART_IFLAG_RXTOIF_MSK BIT(LPUART_IFLAG_RXTOIF_POS) + +#define LPUART_IFLAG_CTSDETIF_POS 2U +#define LPUART_IFLAG_CTSDETIF_MSK BIT(LPUART_IFLAG_CTSDETIF_POS) + +#define LPUART_IFLAG_TBEMPIF_POS 1U +#define LPUART_IFLAG_TBEMPIF_MSK BIT(LPUART_IFLAG_TBEMPIF_POS) + +#define LPUART_IFLAG_RBRIF_POS 0U +#define LPUART_IFLAG_RBRIF_MSK BIT(LPUART_IFLAG_RBRIF_POS) + +/****************** Bit definition for LPUART_IFC register ************************/ + +#define LPUART_IFC_TCIFC_POS 15U +#define LPUART_IFC_TCIFC_MSK BIT(LPUART_IFC_TCIFC_POS) + +#define LPUART_IFC_ADETIFC_POS 12U +#define LPUART_IFC_ADETIFC_MSK BIT(LPUART_IFC_ADETIFC_POS) + +#define LPUART_IFC_BRKERRIFC_POS 11U +#define LPUART_IFC_BRKERRIFC_MSK BIT(LPUART_IFC_BRKERRIFC_POS) + +#define LPUART_IFC_FERRIFC_POS 10U +#define LPUART_IFC_FERRIFC_MSK BIT(LPUART_IFC_FERRIFC_POS) + +#define LPUART_IFC_PERRIFC_POS 9U +#define LPUART_IFC_PERRIFC_MSK BIT(LPUART_IFC_PERRIFC_POS) + +#define LPUART_IFC_DATWKIFC_POS 8U +#define LPUART_IFC_DATWKIFC_MSK BIT(LPUART_IFC_DATWKIFC_POS) + +#define LPUART_IFC_CTSWKIFC_POS 7U +#define LPUART_IFC_CTSWKIFC_MSK BIT(LPUART_IFC_CTSWKIFC_POS) + +#define LPUART_IFC_TXOVIFC_POS 5U +#define LPUART_IFC_TXOVIFC_MSK BIT(LPUART_IFC_TXOVIFC_POS) + +#define LPUART_IFC_RXOVIFC_POS 4U +#define LPUART_IFC_RXOVIFC_MSK BIT(LPUART_IFC_RXOVIFC_POS) + +#define LPUART_IFC_CTSDETIFC_POS 2U +#define LPUART_IFC_CTSDETIFC_MSK BIT(LPUART_IFC_CTSDETIFC_POS) + +#define LPUART_IFC_TBEMPIFC_POS 1U +#define LPUART_IFC_TBEMPIFC_MSK BIT(LPUART_IFC_TBEMPIFC_POS) + +#define LPUART_IFC_RBRIFC_POS 0U +#define LPUART_IFC_RBRIFC_MSK BIT(LPUART_IFC_RBRIFC_POS) + +/****************** Bit definition for LPUART_ISTAT register ************************/ + +#define LPUART_ISTAT_TCINT_POS 15U +#define LPUART_ISTAT_TCINT_MSK BIT(LPUART_ISTAT_TCINT_POS) + +#define LPUART_ISTAT_RXSTATINT_POS 9U +#define LPUART_ISTAT_RXSTATINT_MSK BIT(LPUART_ISTAT_RXSTATINT_POS) + +#define LPUART_ISTAT_DATWKINT_POS 8U +#define LPUART_ISTAT_DATWKINT_MSK BIT(LPUART_ISTAT_DATWKINT_POS) + +#define LPUART_ISTAT_CTSWKINT_POS 7U +#define LPUART_ISTAT_CTSWKINT_MSK BIT(LPUART_ISTAT_CTSWKINT_POS) + +#define LPUART_ISTAT_BUFERRINT_POS 4U +#define LPUART_ISTAT_BUFERRINT_MSK BIT(LPUART_ISTAT_BUFERRINT_POS) + +#define LPUART_ISTAT_RXTOINT_POS 3U +#define LPUART_ISTAT_RXTOINT_MSK BIT(LPUART_ISTAT_RXTOINT_POS) + +#define LPUART_ISTAT_CTSDETINT_POS 2U +#define LPUART_ISTAT_CTSDETINT_MSK BIT(LPUART_ISTAT_CTSDETINT_POS) + +#define LPUART_ISTAT_TBEMPINT_POS 1U +#define LPUART_ISTAT_TBEMPINT_MSK BIT(LPUART_ISTAT_TBEMPINT_POS) + +#define LPUART_ISTAT_RBRINT_POS 0U +#define LPUART_ISTAT_RBRINT_MSK BIT(LPUART_ISTAT_RBRINT_POS) + +/****************** Bit definition for LPUART_UPDATE register ************************/ + +#define LPUART_UPDATE_UDIS_POS 0U +#define LPUART_UPDATE_UDIS_MSK BIT(LPUART_UPDATE_UDIS_POS) + +/****************** Bit definition for LPUART_SYNCSTAT register ************************/ + +#define LPUART_SYNCSTAT_FIFOCONWBSY_POS 3U +#define LPUART_SYNCSTAT_FIFOCONWBSY_MSK BIT(LPUART_SYNCSTAT_FIFOCONWBSY_POS) + +#define LPUART_SYNCSTAT_CLKDIVWBSY_POS 2U +#define LPUART_SYNCSTAT_CLKDIVWBSY_MSK BIT(LPUART_SYNCSTAT_CLKDIVWBSY_POS) + +#define LPUART_SYNCSTAT_CON1WBSY_POS 1U +#define LPUART_SYNCSTAT_CON1WBSY_MSK BIT(LPUART_SYNCSTAT_CON1WBSY_POS) + +#define LPUART_SYNCSTAT_CON0WBSY_POS 0U +#define LPUART_SYNCSTAT_CON0WBSY_MSK BIT(LPUART_SYNCSTAT_CON0WBSY_POS) + +typedef struct +{ + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t CLKDIV; + __IO uint32_t FIFOCON; + uint32_t RESERVED0 ; + __I uint32_t RXDR; + __O uint32_t TXDR; + __I uint32_t STAT; + __IO uint32_t IER; + __I uint32_t IFLAG; + __O uint32_t IFC; + __I uint32_t ISTAT; + uint32_t RESERVED1[2] ; + __IO uint32_t UPDATE; + __I uint32_t SYNCSTAT; +} LPUART_TypeDef; + +/****************** Bit definition for SPI_CON1 register ************************/ + +#define SPI_CON1_BIDEN_POS 15U +#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) + +#define SPI_CON1_BIDOEN_POS 14U +#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) + +#define SPI_CON1_CRCEN_POS 13U +#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) + +#define SPI_CON1_NXTCRC_POS 12U +#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) + +#define SPI_CON1_FLEN_POS 11U +#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) + +#define SPI_CON1_RXO_POS 10U +#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) + +#define SPI_CON1_SSEN_POS 9U +#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) + +#define SPI_CON1_SSOUT_POS 8U +#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) + +#define SPI_CON1_LSBFST_POS 7U +#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) + +#define SPI_CON1_SPIEN_POS 6U +#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) + +#define SPI_CON1_BAUD_POSS 3U +#define SPI_CON1_BAUD_POSE 5U +#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) + +#define SPI_CON1_MSTREN_POS 2U +#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) + +#define SPI_CON1_CPOL_POS 1U +#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) + +#define SPI_CON1_CPHA_POS 0U +#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) + +/****************** Bit definition for SPI_CON2 register ************************/ + +#define SPI_CON2_TXBEIE_POS 7U +#define SPI_CON2_TXBEIE_MSK BIT(SPI_CON2_TXBEIE_POS) + +#define SPI_CON2_RXBNEIE_POS 6U +#define SPI_CON2_RXBNEIE_MSK BIT(SPI_CON2_RXBNEIE_POS) + +#define SPI_CON2_ERRIE_POS 5U +#define SPI_CON2_ERRIE_MSK BIT(SPI_CON2_ERRIE_POS) + +#define SPI_CON2_NSSOE_POS 2U +#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) + +#define SPI_CON2_TXDMA_POS 1U +#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) + +#define SPI_CON2_RXDMA_POS 0U +#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) + +/****************** Bit definition for SPI_STAT register ************************/ + +#define SPI_STAT_BUSY_POS 7U +#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) + +#define SPI_STAT_OVERR_POS 6U +#define SPI_STAT_OVERR_MSK BIT(SPI_STAT_OVERR_POS) + +#define SPI_STAT_MODERR_POS 5U +#define SPI_STAT_MODERR_MSK BIT(SPI_STAT_MODERR_POS) + +#define SPI_STAT_CRCERR_POS 4U +#define SPI_STAT_CRCERR_MSK BIT(SPI_STAT_CRCERR_POS) + +#define SPI_STAT_TXBE_POS 1U +#define SPI_STAT_TXBE_MSK BIT(SPI_STAT_TXBE_POS) + +#define SPI_STAT_RXBNE_POS 0U +#define SPI_STAT_RXBNE_MSK BIT(SPI_STAT_RXBNE_POS) + +/****************** Bit definition for SPI_DATA register ************************/ + +#define SPI_DATA_VALUE_POSS 0U +#define SPI_DATA_VALUE_POSE 15U +#define SPI_DATA_VALUE_MSK BITS(SPI_DATA_VALUE_POSS,SPI_DATA_VALUE_POSE) + +/****************** Bit definition for SPI_CRCPOLY register ************************/ + +#define SPI_CRCPOLY_VALUE_POSS 0U +#define SPI_CRCPOLY_VALUE_POSE 15U +#define SPI_CRCPOLY_VALUE_MSK BITS(SPI_CRCPOLY_VALUE_POSS,SPI_CRCPOLY_VALUE_POSE) + +/****************** Bit definition for SPI_RXCRC register ************************/ + +#define SPI_RXCRC_CRCVAL_POSS 0U +#define SPI_RXCRC_CRCVAL_POSE 15U +#define SPI_RXCRC_CRCVAL_MSK BITS(SPI_RXCRC_CRCVAL_POSS,SPI_RXCRC_CRCVAL_POSE) + +/****************** Bit definition for SPI_TXCRC register ************************/ + +#define SPI_TXCRC_CRCVAL_POSS 0U +#define SPI_TXCRC_CRCVAL_POSE 15U +#define SPI_TXCRC_CRCVAL_MSK BITS(SPI_TXCRC_CRCVAL_POSS,SPI_TXCRC_CRCVAL_POSE) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t CRCPOLY; + __I uint32_t RXCRC; + __I uint32_t TXCRC; +} SPI_TypeDef; + +/****************** Bit definition for I2C_CON1 register ************************/ + +#define I2C_CON1_SRST_POS 15U +#define I2C_CON1_SRST_MSK BIT(I2C_CON1_SRST_POS) + +#define I2C_CON1_ALARM_POS 13U +#define I2C_CON1_ALARM_MSK BIT(I2C_CON1_ALARM_POS) + +#define I2C_CON1_TRPEC_POS 12U +#define I2C_CON1_TRPEC_MSK BIT(I2C_CON1_TRPEC_POS) + +#define I2C_CON1_POSAP_POS 11U +#define I2C_CON1_POSAP_MSK BIT(I2C_CON1_POSAP_POS) + +#define I2C_CON1_ACKEN_POS 10U +#define I2C_CON1_ACKEN_MSK BIT(I2C_CON1_ACKEN_POS) + +#define I2C_CON1_STOP_POS 9U +#define I2C_CON1_STOP_MSK BIT(I2C_CON1_STOP_POS) + +#define I2C_CON1_START_POS 8U +#define I2C_CON1_START_MSK BIT(I2C_CON1_START_POS) + +#define I2C_CON1_DISCS_POS 7U +#define I2C_CON1_DISCS_MSK BIT(I2C_CON1_DISCS_POS) + +#define I2C_CON1_GCEN_POS 6U +#define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) + +#define I2C_CON1_PECEN_POS 5U +#define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) + +#define I2C_CON1_ARPEN_POS 4U +#define I2C_CON1_ARPEN_MSK BIT(I2C_CON1_ARPEN_POS) + +#define I2C_CON1_SMBMOD_POS 3U +#define I2C_CON1_SMBMOD_MSK BIT(I2C_CON1_SMBMOD_POS) + +#define I2C_CON1_PMOD_POS 1U +#define I2C_CON1_PMOD_MSK BIT(I2C_CON1_PMOD_POS) + +#define I2C_CON1_PEN_POS 0U +#define I2C_CON1_PEN_MSK BIT(I2C_CON1_PEN_POS) + +/****************** Bit definition for I2C_CON2 register ************************/ + +#define I2C_CON2_LDMA_POS 12U +#define I2C_CON2_LDMA_MSK BIT(I2C_CON2_LDMA_POS) + +#define I2C_CON2_DMAEN_POS 11U +#define I2C_CON2_DMAEN_MSK BIT(I2C_CON2_DMAEN_POS) + +#define I2C_CON2_BUFIE_POS 10U +#define I2C_CON2_BUFIE_MSK BIT(I2C_CON2_BUFIE_POS) + +#define I2C_CON2_EVTIE_POS 9U +#define I2C_CON2_EVTIE_MSK BIT(I2C_CON2_EVTIE_POS) + +#define I2C_CON2_ERRIE_POS 8U +#define I2C_CON2_ERRIE_MSK BIT(I2C_CON2_ERRIE_POS) + +#define I2C_CON2_CLKF_POSS 0U +#define I2C_CON2_CLKF_POSE 5U +#define I2C_CON2_CLKF_MSK BITS(I2C_CON2_CLKF_POSS,I2C_CON2_CLKF_POSE) + +/****************** Bit definition for I2C_ADDR1 register ************************/ + +#define I2C_ADDR1_ADDTYPE_POS 15U +#define I2C_ADDR1_ADDTYPE_MSK BIT(I2C_ADDR1_ADDTYPE_POS) + +#define I2C_ADDR1_ADDH_POSS 8U +#define I2C_ADDR1_ADDH_POSE 9U +#define I2C_ADDR1_ADDH_MSK BITS(I2C_ADDR1_ADDH_POSS,I2C_ADDR1_ADDH_POSE) + +#define I2C_ADDR1_ADD_POSS 1U +#define I2C_ADDR1_ADD_POSE 7U +#define I2C_ADDR1_ADD_MSK BITS(I2C_ADDR1_ADD_POSS,I2C_ADDR1_ADD_POSE) + +#define I2C_ADDR1_ADDLSB_POS 0U +#define I2C_ADDR1_ADDLSB_MSK BIT(I2C_ADDR1_ADDLSB_POS) + +/****************** Bit definition for I2C_ADDR2 register ************************/ + +#define I2C_ADDR2_ADD_POSS 1U +#define I2C_ADDR2_ADD_POSE 7U +#define I2C_ADDR2_ADD_MSK BITS(I2C_ADDR2_ADD_POSS,I2C_ADDR2_ADD_POSE) + +#define I2C_ADDR2_DUALEN_POS 0U +#define I2C_ADDR2_DUALEN_MSK BIT(I2C_ADDR2_DUALEN_POS) + +/****************** Bit definition for I2C_DATA register ************************/ + +#define I2C_DATA_TRBUF_POSS 0U +#define I2C_DATA_TRBUF_POSE 7U +#define I2C_DATA_TRBUF_MSK BITS(I2C_DATA_TRBUF_POSS,I2C_DATA_TRBUF_POSE) + +/****************** Bit definition for I2C_STAT1 register ************************/ + +#define I2C_STAT1_SMBALARM_POS 15U +#define I2C_STAT1_SMBALARM_MSK BIT(I2C_STAT1_SMBALARM_POS) + +#define I2C_STAT1_SMBTO_POS 14U +#define I2C_STAT1_SMBTO_MSK BIT(I2C_STAT1_SMBTO_POS) + +#define I2C_STAT1_PECERR_POS 12U +#define I2C_STAT1_PECERR_MSK BIT(I2C_STAT1_PECERR_POS) + +#define I2C_STAT1_ROUERR_POS 11U +#define I2C_STAT1_ROUERR_MSK BIT(I2C_STAT1_ROUERR_POS) + +#define I2C_STAT1_ACKERR_POS 10U +#define I2C_STAT1_ACKERR_MSK BIT(I2C_STAT1_ACKERR_POS) + +#define I2C_STAT1_LARB_POS 9U +#define I2C_STAT1_LARB_MSK BIT(I2C_STAT1_LARB_POS) + +#define I2C_STAT1_BUSERR_POS 8U +#define I2C_STAT1_BUSERR_MSK BIT(I2C_STAT1_BUSERR_POS) + +#define I2C_STAT1_TXBE_POS 7U +#define I2C_STAT1_TXBE_MSK BIT(I2C_STAT1_TXBE_POS) + +#define I2C_STAT1_RXBNE_POS 6U +#define I2C_STAT1_RXBNE_MSK BIT(I2C_STAT1_RXBNE_POS) + +#define I2C_STAT1_DETSTP_POS 4U +#define I2C_STAT1_DETSTP_MSK BIT(I2C_STAT1_DETSTP_POS) + +#define I2C_STAT1_SENDADD10_POS 3U +#define I2C_STAT1_SENDADD10_MSK BIT(I2C_STAT1_SENDADD10_POS) + +#define I2C_STAT1_BTC_POS 2U +#define I2C_STAT1_BTC_MSK BIT(I2C_STAT1_BTC_POS) + +#define I2C_STAT1_ADDR_POS 1U +#define I2C_STAT1_ADDR_MSK BIT(I2C_STAT1_ADDR_POS) + +#define I2C_STAT1_SENDSTR_POS 0U +#define I2C_STAT1_SENDSTR_MSK BIT(I2C_STAT1_SENDSTR_POS) + +/****************** Bit definition for I2C_STAT2 register ************************/ + +#define I2C_STAT2_PECV_POSS 8U +#define I2C_STAT2_PECV_POSE 15U +#define I2C_STAT2_PECV_MSK BITS(I2C_STAT2_PECV_POSS,I2C_STAT2_PECV_POSE) + +#define I2C_STAT2_DMF_POS 7U +#define I2C_STAT2_DMF_MSK BIT(I2C_STAT2_DMF_POS) + +#define I2C_STAT2_SMBHH_POS 6U +#define I2C_STAT2_SMBHH_MSK BIT(I2C_STAT2_SMBHH_POS) + +#define I2C_STAT2_SMBDEF_POS 5U +#define I2C_STAT2_SMBDEF_MSK BIT(I2C_STAT2_SMBDEF_POS) + +#define I2C_STAT2_RXGCF_POS 4U +#define I2C_STAT2_RXGCF_MSK BIT(I2C_STAT2_RXGCF_POS) + +#define I2C_STAT2_TRF_POS 2U +#define I2C_STAT2_TRF_MSK BIT(I2C_STAT2_TRF_POS) + +#define I2C_STAT2_BSYF_POS 1U +#define I2C_STAT2_BSYF_MSK BIT(I2C_STAT2_BSYF_POS) + +#define I2C_STAT2_MASTER_POS 0U +#define I2C_STAT2_MASTER_MSK BIT(I2C_STAT2_MASTER_POS) + +/****************** Bit definition for I2C_CKCFG register ************************/ + +#define I2C_CKCFG_CLKMOD_POS 15U +#define I2C_CKCFG_CLKMOD_MSK BIT(I2C_CKCFG_CLKMOD_POS) + +#define I2C_CKCFG_DUTY_POS 14U +#define I2C_CKCFG_DUTY_MSK BIT(I2C_CKCFG_DUTY_POS) + +#define I2C_CKCFG_CLKSET_POSS 0U +#define I2C_CKCFG_CLKSET_POSE 11U +#define I2C_CKCFG_CLKSET_MSK BITS(I2C_CKCFG_CLKSET_POSS,I2C_CKCFG_CLKSET_POSE) + +/****************** Bit definition for I2C_RT register ************************/ + +#define I2C_RT_RISET_POSS 0U +#define I2C_RT_RISET_POSE 5U +#define I2C_RT_RISET_MSK BITS(I2C_RT_RISET_POSS,I2C_RT_RISET_POSE) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t DATA; + __IO uint32_t STAT1; + __I uint32_t STAT2; + __IO uint32_t CKCFG; + __IO uint32_t RT; +} I2C_TypeDef; + +/****************** Bit definition for CAN_CON register ************************/ + +#define CAN_CON_DBGSTP_POS 16U +#define CAN_CON_DBGSTP_MSK BIT(CAN_CON_DBGSTP_POS) + +#define CAN_CON_RST_POS 15U +#define CAN_CON_RST_MSK BIT(CAN_CON_RST_POS) + +#define CAN_CON_TTCEN_POS 7U +#define CAN_CON_TTCEN_MSK BIT(CAN_CON_TTCEN_POS) + +#define CAN_CON_ABOFFEN_POS 6U +#define CAN_CON_ABOFFEN_MSK BIT(CAN_CON_ABOFFEN_POS) + +#define CAN_CON_AWKEN_POS 5U +#define CAN_CON_AWKEN_MSK BIT(CAN_CON_AWKEN_POS) + +#define CAN_CON_ARTXDIS_POS 4U +#define CAN_CON_ARTXDIS_MSK BIT(CAN_CON_ARTXDIS_POS) + +#define CAN_CON_RXFOPM_POS 3U +#define CAN_CON_RXFOPM_MSK BIT(CAN_CON_RXFOPM_POS) + +#define CAN_CON_TXMP_POS 2U +#define CAN_CON_TXMP_MSK BIT(CAN_CON_TXMP_POS) + +#define CAN_CON_SLPREQ_POS 1U +#define CAN_CON_SLPREQ_MSK BIT(CAN_CON_SLPREQ_POS) + +#define CAN_CON_INIREQ_POS 0U +#define CAN_CON_INIREQ_MSK BIT(CAN_CON_INIREQ_POS) + +/****************** Bit definition for CAN_STAT register ************************/ + +#define CAN_STAT_RX_POS 11U +#define CAN_STAT_RX_MSK BIT(CAN_STAT_RX_POS) + +#define CAN_STAT_PRESMP_POS 10U +#define CAN_STAT_PRESMP_MSK BIT(CAN_STAT_PRESMP_POS) + +#define CAN_STAT_RXSTAT_POS 9U +#define CAN_STAT_RXSTAT_MSK BIT(CAN_STAT_RXSTAT_POS) + +#define CAN_STAT_TXSTAT_POS 8U +#define CAN_STAT_TXSTAT_MSK BIT(CAN_STAT_TXSTAT_POS) + +#define CAN_STAT_SLPIF_POS 4U +#define CAN_STAT_SLPIF_MSK BIT(CAN_STAT_SLPIF_POS) + +#define CAN_STAT_WKIF_POS 3U +#define CAN_STAT_WKIF_MSK BIT(CAN_STAT_WKIF_POS) + +#define CAN_STAT_ERRIF_POS 2U +#define CAN_STAT_ERRIF_MSK BIT(CAN_STAT_ERRIF_POS) + +#define CAN_STAT_SLPSTAT_POS 1U +#define CAN_STAT_SLPSTAT_MSK BIT(CAN_STAT_SLPSTAT_POS) + +#define CAN_STAT_INISTAT_POS 0U +#define CAN_STAT_INISTAT_MSK BIT(CAN_STAT_INISTAT_POS) + +/****************** Bit definition for CAN_IFC register ************************/ + +#define CAN_IFC_SLPIFC_POS 4U +#define CAN_IFC_SLPIFC_MSK BIT(CAN_IFC_SLPIFC_POS) + +#define CAN_IFC_WKIFC_POS 3U +#define CAN_IFC_WKIFC_MSK BIT(CAN_IFC_WKIFC_POS) + +#define CAN_IFC_ERRIFC_POS 2U +#define CAN_IFC_ERRIFC_MSK BIT(CAN_IFC_ERRIFC_POS) + +/****************** Bit definition for CAN_TXSTAT register ************************/ + +#define CAN_TXSTAT_TXM2LPF_POS 31U +#define CAN_TXSTAT_TXM2LPF_MSK BIT(CAN_TXSTAT_TXM2LPF_POS) + +#define CAN_TXSTAT_TXM1LPF_POS 30U +#define CAN_TXSTAT_TXM1LPF_MSK BIT(CAN_TXSTAT_TXM1LPF_POS) + +#define CAN_TXSTAT_TXM0LPF_POS 29U +#define CAN_TXSTAT_TXM0LPF_MSK BIT(CAN_TXSTAT_TXM0LPF_POS) + +#define CAN_TXSTAT_TXM2EF_POS 28U +#define CAN_TXSTAT_TXM2EF_MSK BIT(CAN_TXSTAT_TXM2EF_POS) + +#define CAN_TXSTAT_TXM1EF_POS 27U +#define CAN_TXSTAT_TXM1EF_MSK BIT(CAN_TXSTAT_TXM1EF_POS) + +#define CAN_TXSTAT_TXM0EF_POS 26U +#define CAN_TXSTAT_TXM0EF_MSK BIT(CAN_TXSTAT_TXM0EF_POS) + +#define CAN_TXSTAT_CODE_POSS 24U +#define CAN_TXSTAT_CODE_POSE 25U +#define CAN_TXSTAT_CODE_MSK BITS(CAN_TXSTAT_CODE_POSS,CAN_TXSTAT_CODE_POSE) + +#define CAN_TXSTAT_M2STPREQ_POS 23U +#define CAN_TXSTAT_M2STPREQ_MSK BIT(CAN_TXSTAT_M2STPREQ_POS) + +#define CAN_TXSTAT_M2TXERR_POS 19U +#define CAN_TXSTAT_M2TXERR_MSK BIT(CAN_TXSTAT_M2TXERR_POS) + +#define CAN_TXSTAT_M2ARBLST_POS 18U +#define CAN_TXSTAT_M2ARBLST_MSK BIT(CAN_TXSTAT_M2ARBLST_POS) + +#define CAN_TXSTAT_M2TXC_POS 17U +#define CAN_TXSTAT_M2TXC_MSK BIT(CAN_TXSTAT_M2TXC_POS) + +#define CAN_TXSTAT_M2REQC_POS 16U +#define CAN_TXSTAT_M2REQC_MSK BIT(CAN_TXSTAT_M2REQC_POS) + +#define CAN_TXSTAT_M1STPREQ_POS 15U +#define CAN_TXSTAT_M1STPREQ_MSK BIT(CAN_TXSTAT_M1STPREQ_POS) + +#define CAN_TXSTAT_M1TXERR_POS 11U +#define CAN_TXSTAT_M1TXERR_MSK BIT(CAN_TXSTAT_M1TXERR_POS) + +#define CAN_TXSTAT_M1ARBLST_POS 10U +#define CAN_TXSTAT_M1ARBLST_MSK BIT(CAN_TXSTAT_M1ARBLST_POS) + +#define CAN_TXSTAT_M1TXC_POS 9U +#define CAN_TXSTAT_M1TXC_MSK BIT(CAN_TXSTAT_M1TXC_POS) + +#define CAN_TXSTAT_M1REQC_POS 8U +#define CAN_TXSTAT_M1REQC_MSK BIT(CAN_TXSTAT_M1REQC_POS) + +#define CAN_TXSTAT_M0STPREQ_POS 7U +#define CAN_TXSTAT_M0STPREQ_MSK BIT(CAN_TXSTAT_M0STPREQ_POS) + +#define CAN_TXSTAT_M0TXERR_POS 3U +#define CAN_TXSTAT_M0TXERR_MSK BIT(CAN_TXSTAT_M0TXERR_POS) + +#define CAN_TXSTAT_M0ARBLST_POS 2U +#define CAN_TXSTAT_M0ARBLST_MSK BIT(CAN_TXSTAT_M0ARBLST_POS) + +#define CAN_TXSTAT_M0TXC_POS 1U +#define CAN_TXSTAT_M0TXC_MSK BIT(CAN_TXSTAT_M0TXC_POS) + +#define CAN_TXSTAT_M0REQC_POS 0U +#define CAN_TXSTAT_M0REQC_MSK BIT(CAN_TXSTAT_M0REQC_POS) + +/****************** Bit definition for CAN_TXSTATC register ************************/ + +#define CAN_TXSTATC_M2TXERR_POS 19U +#define CAN_TXSTATC_M2TXERR_MSK BIT(CAN_TXSTATC_M2TXERR_POS) + +#define CAN_TXSTATC_M2ARBLST_POS 18U +#define CAN_TXSTATC_M2ARBLST_MSK BIT(CAN_TXSTATC_M2ARBLST_POS) + +#define CAN_TXSTATC_M2TXC_POS 17U +#define CAN_TXSTATC_M2TXC_MSK BIT(CAN_TXSTATC_M2TXC_POS) + +#define CAN_TXSTATC_M2REQC_POS 16U +#define CAN_TXSTATC_M2REQC_MSK BIT(CAN_TXSTATC_M2REQC_POS) + +#define CAN_TXSTATC_M1TXERR_POS 11U +#define CAN_TXSTATC_M1TXERR_MSK BIT(CAN_TXSTATC_M1TXERR_POS) + +#define CAN_TXSTATC_M1ARBLST_POS 10U +#define CAN_TXSTATC_M1ARBLST_MSK BIT(CAN_TXSTATC_M1ARBLST_POS) + +#define CAN_TXSTATC_M1TXC_POS 9U +#define CAN_TXSTATC_M1TXC_MSK BIT(CAN_TXSTATC_M1TXC_POS) + +#define CAN_TXSTATC_M1REQC_POS 8U +#define CAN_TXSTATC_M1REQC_MSK BIT(CAN_TXSTATC_M1REQC_POS) + +#define CAN_TXSTATC_M0TXERR_POS 3U +#define CAN_TXSTATC_M0TXERR_MSK BIT(CAN_TXSTATC_M0TXERR_POS) + +#define CAN_TXSTATC_M0ARBLST_POS 2U +#define CAN_TXSTATC_M0ARBLST_MSK BIT(CAN_TXSTATC_M0ARBLST_POS) + +#define CAN_TXSTATC_M0TXC_POS 1U +#define CAN_TXSTATC_M0TXC_MSK BIT(CAN_TXSTATC_M0TXC_POS) + +#define CAN_TXSTATC_M0REQC_POS 0U +#define CAN_TXSTATC_M0REQC_MSK BIT(CAN_TXSTATC_M0REQC_POS) + +/****************** Bit definition for CAN_RXF0 register ************************/ + +#define CAN_RXF0_FREE_POS 5U +#define CAN_RXF0_FREE_MSK BIT(CAN_RXF0_FREE_POS) + +#define CAN_RXF0_OVR_POS 4U +#define CAN_RXF0_OVR_MSK BIT(CAN_RXF0_OVR_POS) + +#define CAN_RXF0_FULL_POS 3U +#define CAN_RXF0_FULL_MSK BIT(CAN_RXF0_FULL_POS) + +#define CAN_RXF0_PEND_POSS 0U +#define CAN_RXF0_PEND_POSE 1U +#define CAN_RXF0_PEND_MSK BITS(CAN_RXF0_PEND_POSS,CAN_RXF0_PEND_POSE) + +/****************** Bit definition for CAN_RXF0C register ************************/ + +#define CAN_RXF0C_OVRC_POS 4U +#define CAN_RXF0C_OVRC_MSK BIT(CAN_RXF0C_OVRC_POS) + +#define CAN_RXF0C_FULLC_POS 3U +#define CAN_RXF0C_FULLC_MSK BIT(CAN_RXF0C_FULLC_POS) + +/****************** Bit definition for CAN_RXF1 register ************************/ + +#define CAN_RXF1_FREE_POS 5U +#define CAN_RXF1_FREE_MSK BIT(CAN_RXF1_FREE_POS) + +#define CAN_RXF1_OVR_POS 4U +#define CAN_RXF1_OVR_MSK BIT(CAN_RXF1_OVR_POS) + +#define CAN_RXF1_FULL_POS 3U +#define CAN_RXF1_FULL_MSK BIT(CAN_RXF1_FULL_POS) + +#define CAN_RXF1_PEND_POSS 0U +#define CAN_RXF1_PEND_POSE 1U +#define CAN_RXF1_PEND_MSK BITS(CAN_RXF1_PEND_POSS,CAN_RXF1_PEND_POSE) + +/****************** Bit definition for CAN_RXF1C register ************************/ + +#define CAN_RXF1C_OVRC_POS 4U +#define CAN_RXF1C_OVRC_MSK BIT(CAN_RXF1C_OVRC_POS) + +#define CAN_RXF1C_FULLC_POS 3U +#define CAN_RXF1C_FULLC_MSK BIT(CAN_RXF1C_FULLC_POS) + +/****************** Bit definition for CAN_IE register ************************/ + +#define CAN_IE_SLPIE_POS 17U +#define CAN_IE_SLPIE_MSK BIT(CAN_IE_SLPIE_POS) + +#define CAN_IE_WKIE_POS 16U +#define CAN_IE_WKIE_MSK BIT(CAN_IE_WKIE_POS) + +#define CAN_IE_ERRIE_POS 15U +#define CAN_IE_ERRIE_MSK BIT(CAN_IE_ERRIE_POS) + +#define CAN_IE_PRERRIE_POS 11U +#define CAN_IE_PRERRIE_MSK BIT(CAN_IE_PRERRIE_POS) + +#define CAN_IE_BOFFIE_POS 10U +#define CAN_IE_BOFFIE_MSK BIT(CAN_IE_BOFFIE_POS) + +#define CAN_IE_PERRIE_POS 9U +#define CAN_IE_PERRIE_MSK BIT(CAN_IE_PERRIE_POS) + +#define CAN_IE_WARNIE_POS 8U +#define CAN_IE_WARNIE_MSK BIT(CAN_IE_WARNIE_POS) + +#define CAN_IE_F1OVRIE_POS 6U +#define CAN_IE_F1OVRIE_MSK BIT(CAN_IE_F1OVRIE_POS) + +#define CAN_IE_F1FULIE_POS 5U +#define CAN_IE_F1FULIE_MSK BIT(CAN_IE_F1FULIE_POS) + +#define CAN_IE_F1PIE_POS 4U +#define CAN_IE_F1PIE_MSK BIT(CAN_IE_F1PIE_POS) + +#define CAN_IE_F0OVRIE_POS 3U +#define CAN_IE_F0OVRIE_MSK BIT(CAN_IE_F0OVRIE_POS) + +#define CAN_IE_F0FULIE_POS 2U +#define CAN_IE_F0FULIE_MSK BIT(CAN_IE_F0FULIE_POS) + +#define CAN_IE_F0PIE_POS 1U +#define CAN_IE_F0PIE_MSK BIT(CAN_IE_F0PIE_POS) + +#define CAN_IE_TXMEIE_POS 0U +#define CAN_IE_TXMEIE_MSK BIT(CAN_IE_TXMEIE_POS) + +/****************** Bit definition for CAN_ERRSTAT register ************************/ + +#define CAN_ERRSTAT_RXERRC_POSS 24U +#define CAN_ERRSTAT_RXERRC_POSE 31U +#define CAN_ERRSTAT_RXERRC_MSK BITS(CAN_ERRSTAT_RXERRC_POSS,CAN_ERRSTAT_RXERRC_POSE) + +#define CAN_ERRSTAT_TXERRC_POSS 16U +#define CAN_ERRSTAT_TXERRC_POSE 23U +#define CAN_ERRSTAT_TXERRC_MSK BITS(CAN_ERRSTAT_TXERRC_POSS,CAN_ERRSTAT_TXERRC_POSE) + +#define CAN_ERRSTAT_PRERRF_POSS 4U +#define CAN_ERRSTAT_PRERRF_POSE 6U +#define CAN_ERRSTAT_PRERRF_MSK BITS(CAN_ERRSTAT_PRERRF_POSS,CAN_ERRSTAT_PRERRF_POSE) + +#define CAN_ERRSTAT_BOFF_POS 2U +#define CAN_ERRSTAT_BOFF_MSK BIT(CAN_ERRSTAT_BOFF_POS) + +#define CAN_ERRSTAT_PERRF_POS 1U +#define CAN_ERRSTAT_PERRF_MSK BIT(CAN_ERRSTAT_PERRF_POS) + +#define CAN_ERRSTAT_WARNF_POS 0U +#define CAN_ERRSTAT_WARNF_MSK BIT(CAN_ERRSTAT_WARNF_POS) + +/****************** Bit definition for CAN_BTIME register ************************/ + +#define CAN_BTIME_SILENT_POS 31U +#define CAN_BTIME_SILENT_MSK BIT(CAN_BTIME_SILENT_POS) + +#define CAN_BTIME_LOOP_POS 30U +#define CAN_BTIME_LOOP_MSK BIT(CAN_BTIME_LOOP_POS) + +#define CAN_BTIME_RESJW_POSS 24U +#define CAN_BTIME_RESJW_POSE 25U +#define CAN_BTIME_RESJW_MSK BITS(CAN_BTIME_RESJW_POSS,CAN_BTIME_RESJW_POSE) + +#define CAN_BTIME_SEG2_POSS 20U +#define CAN_BTIME_SEG2_POSE 22U +#define CAN_BTIME_SEG2_MSK BITS(CAN_BTIME_SEG2_POSS,CAN_BTIME_SEG2_POSE) + +#define CAN_BTIME_SEG1_POSS 16U +#define CAN_BTIME_SEG1_POSE 19U +#define CAN_BTIME_SEG1_MSK BITS(CAN_BTIME_SEG1_POSS,CAN_BTIME_SEG1_POSE) + +#define CAN_BTIME_BPSC_POSS 0U +#define CAN_BTIME_BPSC_POSE 9U +#define CAN_BTIME_BPSC_MSK BITS(CAN_BTIME_BPSC_POSS,CAN_BTIME_BPSC_POSE) + +/****************** Bit definition for CAN_TXID0 register ************************/ + +#define CAN_TXID0_STDID_POSS 21U +#define CAN_TXID0_STDID_POSE 31U +#define CAN_TXID0_STDID_MSK BITS(CAN_TXID0_STDID_POSS,CAN_TXID0_STDID_POSE) + +#define CAN_TXID0_EXID_POSS 3U +#define CAN_TXID0_EXID_POSE 20U +#define CAN_TXID0_EXID_MSK BITS(CAN_TXID0_EXID_POSS,CAN_TXID0_EXID_POSE) + +#define CAN_TXID0_IDE_POS 2U +#define CAN_TXID0_IDE_MSK BIT(CAN_TXID0_IDE_POS) + +#define CAN_TXID0_RTR_POS 1U +#define CAN_TXID0_RTR_MSK BIT(CAN_TXID0_RTR_POS) + +#define CAN_TXID0_TXMREQ_POS 0U +#define CAN_TXID0_TXMREQ_MSK BIT(CAN_TXID0_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON0 register ************************/ + +#define CAN_TXFCON0_STAMP_POSS 16U +#define CAN_TXFCON0_STAMP_POSE 31U +#define CAN_TXFCON0_STAMP_MSK BITS(CAN_TXFCON0_STAMP_POSS,CAN_TXFCON0_STAMP_POSE) + +#define CAN_TXFCON0_TXGT_POS 8U +#define CAN_TXFCON0_TXGT_MSK BIT(CAN_TXFCON0_TXGT_POS) + +#define CAN_TXFCON0_DLEN_POSS 0U +#define CAN_TXFCON0_DLEN_POSE 3U +#define CAN_TXFCON0_DLEN_MSK BITS(CAN_TXFCON0_DLEN_POSS,CAN_TXFCON0_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL0 register ************************/ + +#define CAN_TXDL0_BYTE3_POSS 24U +#define CAN_TXDL0_BYTE3_POSE 31U +#define CAN_TXDL0_BYTE3_MSK BITS(CAN_TXDL0_BYTE3_POSS,CAN_TXDL0_BYTE3_POSE) + +#define CAN_TXDL0_BYTE2_POSS 16U +#define CAN_TXDL0_BYTE2_POSE 23U +#define CAN_TXDL0_BYTE2_MSK BITS(CAN_TXDL0_BYTE2_POSS,CAN_TXDL0_BYTE2_POSE) + +#define CAN_TXDL0_BYTE1_POSS 8U +#define CAN_TXDL0_BYTE1_POSE 15U +#define CAN_TXDL0_BYTE1_MSK BITS(CAN_TXDL0_BYTE1_POSS,CAN_TXDL0_BYTE1_POSE) + +#define CAN_TXDL0_BYTE0_POSS 0U +#define CAN_TXDL0_BYTE0_POSE 7U +#define CAN_TXDL0_BYTE0_MSK BITS(CAN_TXDL0_BYTE0_POSS,CAN_TXDL0_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH0 register ************************/ + +#define CAN_TXDH0_BYTE7_POSS 24U +#define CAN_TXDH0_BYTE7_POSE 31U +#define CAN_TXDH0_BYTE7_MSK BITS(CAN_TXDH0_BYTE7_POSS,CAN_TXDH0_BYTE7_POSE) + +#define CAN_TXDH0_BYTE6_POSS 16U +#define CAN_TXDH0_BYTE6_POSE 23U +#define CAN_TXDH0_BYTE6_MSK BITS(CAN_TXDH0_BYTE6_POSS,CAN_TXDH0_BYTE6_POSE) + +#define CAN_TXDH0_BYTE5_POSS 8U +#define CAN_TXDH0_BYTE5_POSE 15U +#define CAN_TXDH0_BYTE5_MSK BITS(CAN_TXDH0_BYTE5_POSS,CAN_TXDH0_BYTE5_POSE) + +#define CAN_TXDH0_BYTE4_POSS 0U +#define CAN_TXDH0_BYTE4_POSE 7U +#define CAN_TXDH0_BYTE4_MSK BITS(CAN_TXDH0_BYTE4_POSS,CAN_TXDH0_BYTE4_POSE) + +/****************** Bit definition for CAN_TXID1 register ************************/ + +#define CAN_TXID1_STDID_POSS 21U +#define CAN_TXID1_STDID_POSE 31U +#define CAN_TXID1_STDID_MSK BITS(CAN_TXID1_STDID_POSS,CAN_TXID1_STDID_POSE) + +#define CAN_TXID1_EXID_POSS 3U +#define CAN_TXID1_EXID_POSE 20U +#define CAN_TXID1_EXID_MSK BITS(CAN_TXID1_EXID_POSS,CAN_TXID1_EXID_POSE) + +#define CAN_TXID1_IDE_POS 2U +#define CAN_TXID1_IDE_MSK BIT(CAN_TXID1_IDE_POS) + +#define CAN_TXID1_RTR_POS 1U +#define CAN_TXID1_RTR_MSK BIT(CAN_TXID1_RTR_POS) + +#define CAN_TXID1_TXMREQ_POS 0U +#define CAN_TXID1_TXMREQ_MSK BIT(CAN_TXID1_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON1 register ************************/ + +#define CAN_TXFCON1_STAMP_POSS 16U +#define CAN_TXFCON1_STAMP_POSE 31U +#define CAN_TXFCON1_STAMP_MSK BITS(CAN_TXFCON1_STAMP_POSS,CAN_TXFCON1_STAMP_POSE) + +#define CAN_TXFCON1_TXGT_POS 8U +#define CAN_TXFCON1_TXGT_MSK BIT(CAN_TXFCON1_TXGT_POS) + +#define CAN_TXFCON1_DLEN_POSS 0U +#define CAN_TXFCON1_DLEN_POSE 3U +#define CAN_TXFCON1_DLEN_MSK BITS(CAN_TXFCON1_DLEN_POSS,CAN_TXFCON1_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL1 register ************************/ + +#define CAN_TXDL1_BYTE3_POSS 24U +#define CAN_TXDL1_BYTE3_POSE 31U +#define CAN_TXDL1_BYTE3_MSK BITS(CAN_TXDL1_BYTE3_POSS,CAN_TXDL1_BYTE3_POSE) + +#define CAN_TXDL1_BYTE2_POSS 16U +#define CAN_TXDL1_BYTE2_POSE 23U +#define CAN_TXDL1_BYTE2_MSK BITS(CAN_TXDL1_BYTE2_POSS,CAN_TXDL1_BYTE2_POSE) + +#define CAN_TXDL1_BYTE1_POSS 8U +#define CAN_TXDL1_BYTE1_POSE 15U +#define CAN_TXDL1_BYTE1_MSK BITS(CAN_TXDL1_BYTE1_POSS,CAN_TXDL1_BYTE1_POSE) + +#define CAN_TXDL1_BYTE0_POSS 0U +#define CAN_TXDL1_BYTE0_POSE 7U +#define CAN_TXDL1_BYTE0_MSK BITS(CAN_TXDL1_BYTE0_POSS,CAN_TXDL1_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH1 register ************************/ + +#define CAN_TXDH1_BYTE7_POSS 24U +#define CAN_TXDH1_BYTE7_POSE 31U +#define CAN_TXDH1_BYTE7_MSK BITS(CAN_TXDH1_BYTE7_POSS,CAN_TXDH1_BYTE7_POSE) + +#define CAN_TXDH1_BYTE6_POSS 16U +#define CAN_TXDH1_BYTE6_POSE 23U +#define CAN_TXDH1_BYTE6_MSK BITS(CAN_TXDH1_BYTE6_POSS,CAN_TXDH1_BYTE6_POSE) + +#define CAN_TXDH1_BYTE5_POSS 8U +#define CAN_TXDH1_BYTE5_POSE 15U +#define CAN_TXDH1_BYTE5_MSK BITS(CAN_TXDH1_BYTE5_POSS,CAN_TXDH1_BYTE5_POSE) + +#define CAN_TXDH1_BYTE4_POSS 0U +#define CAN_TXDH1_BYTE4_POSE 7U +#define CAN_TXDH1_BYTE4_MSK BITS(CAN_TXDH1_BYTE4_POSS,CAN_TXDH1_BYTE4_POSE) + +/****************** Bit definition for CAN_TXID2 register ************************/ + +#define CAN_TXID2_STDID_POSS 21U +#define CAN_TXID2_STDID_POSE 31U +#define CAN_TXID2_STDID_MSK BITS(CAN_TXID2_STDID_POSS,CAN_TXID2_STDID_POSE) + +#define CAN_TXID2_EXID_POSS 3U +#define CAN_TXID2_EXID_POSE 20U +#define CAN_TXID2_EXID_MSK BITS(CAN_TXID2_EXID_POSS,CAN_TXID2_EXID_POSE) + +#define CAN_TXID2_IDE_POS 2U +#define CAN_TXID2_IDE_MSK BIT(CAN_TXID2_IDE_POS) + +#define CAN_TXID2_RTR_POS 1U +#define CAN_TXID2_RTR_MSK BIT(CAN_TXID2_RTR_POS) + +#define CAN_TXID2_TXMREQ_POS 0U +#define CAN_TXID2_TXMREQ_MSK BIT(CAN_TXID2_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON2 register ************************/ + +#define CAN_TXFCON2_STAMP_POSS 16U +#define CAN_TXFCON2_STAMP_POSE 31U +#define CAN_TXFCON2_STAMP_MSK BITS(CAN_TXFCON2_STAMP_POSS,CAN_TXFCON2_STAMP_POSE) + +#define CAN_TXFCON2_TXGT_POS 8U +#define CAN_TXFCON2_TXGT_MSK BIT(CAN_TXFCON2_TXGT_POS) + +#define CAN_TXFCON2_DLEN_POSS 0U +#define CAN_TXFCON2_DLEN_POSE 3U +#define CAN_TXFCON2_DLEN_MSK BITS(CAN_TXFCON2_DLEN_POSS,CAN_TXFCON2_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL2 register ************************/ + +#define CAN_TXDL2_BYTE3_POSS 24U +#define CAN_TXDL2_BYTE3_POSE 31U +#define CAN_TXDL2_BYTE3_MSK BITS(CAN_TXDL2_BYTE3_POSS,CAN_TXDL2_BYTE3_POSE) + +#define CAN_TXDL2_BYTE2_POSS 16U +#define CAN_TXDL2_BYTE2_POSE 23U +#define CAN_TXDL2_BYTE2_MSK BITS(CAN_TXDL2_BYTE2_POSS,CAN_TXDL2_BYTE2_POSE) + +#define CAN_TXDL2_BYTE1_POSS 8U +#define CAN_TXDL2_BYTE1_POSE 15U +#define CAN_TXDL2_BYTE1_MSK BITS(CAN_TXDL2_BYTE1_POSS,CAN_TXDL2_BYTE1_POSE) + +#define CAN_TXDL2_BYTE0_POSS 0U +#define CAN_TXDL2_BYTE0_POSE 7U +#define CAN_TXDL2_BYTE0_MSK BITS(CAN_TXDL2_BYTE0_POSS,CAN_TXDL2_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH2 register ************************/ + +#define CAN_TXDH2_BYTE7_POSS 24U +#define CAN_TXDH2_BYTE7_POSE 31U +#define CAN_TXDH2_BYTE7_MSK BITS(CAN_TXDH2_BYTE7_POSS,CAN_TXDH2_BYTE7_POSE) + +#define CAN_TXDH2_BYTE6_POSS 16U +#define CAN_TXDH2_BYTE6_POSE 23U +#define CAN_TXDH2_BYTE6_MSK BITS(CAN_TXDH2_BYTE6_POSS,CAN_TXDH2_BYTE6_POSE) + +#define CAN_TXDH2_BYTE5_POSS 8U +#define CAN_TXDH2_BYTE5_POSE 15U +#define CAN_TXDH2_BYTE5_MSK BITS(CAN_TXDH2_BYTE5_POSS,CAN_TXDH2_BYTE5_POSE) + +#define CAN_TXDH2_BYTE4_POSS 0U +#define CAN_TXDH2_BYTE4_POSE 7U +#define CAN_TXDH2_BYTE4_MSK BITS(CAN_TXDH2_BYTE4_POSS,CAN_TXDH2_BYTE4_POSE) + +/****************** Bit definition for CAN_RXF0ID register ************************/ + +#define CAN_RXF0ID_STDID_POSS 21U +#define CAN_RXF0ID_STDID_POSE 31U +#define CAN_RXF0ID_STDID_MSK BITS(CAN_RXF0ID_STDID_POSS,CAN_RXF0ID_STDID_POSE) + +#define CAN_RXF0ID_EXID_POSS 3U +#define CAN_RXF0ID_EXID_POSE 20U +#define CAN_RXF0ID_EXID_MSK BITS(CAN_RXF0ID_EXID_POSS,CAN_RXF0ID_EXID_POSE) + +#define CAN_RXF0ID_IDE_POS 2U +#define CAN_RXF0ID_IDE_MSK BIT(CAN_RXF0ID_IDE_POS) + +#define CAN_RXF0ID_RTR_POS 1U +#define CAN_RXF0ID_RTR_MSK BIT(CAN_RXF0ID_RTR_POS) + +/****************** Bit definition for CAN_RXF0INF register ************************/ + +#define CAN_RXF0INF_STAMP_POSS 16U +#define CAN_RXF0INF_STAMP_POSE 31U +#define CAN_RXF0INF_STAMP_MSK BITS(CAN_RXF0INF_STAMP_POSS,CAN_RXF0INF_STAMP_POSE) + +#define CAN_RXF0INF_FLTIDX_POSS 8U +#define CAN_RXF0INF_FLTIDX_POSE 15U +#define CAN_RXF0INF_FLTIDX_MSK BITS(CAN_RXF0INF_FLTIDX_POSS,CAN_RXF0INF_FLTIDX_POSE) + +#define CAN_RXF0INF_DLEN_POSS 0U +#define CAN_RXF0INF_DLEN_POSE 3U +#define CAN_RXF0INF_DLEN_MSK BITS(CAN_RXF0INF_DLEN_POSS,CAN_RXF0INF_DLEN_POSE) + +/****************** Bit definition for CAN_RXF0DL register ************************/ + +#define CAN_RXF0DL_BYTE3_POSS 24U +#define CAN_RXF0DL_BYTE3_POSE 31U +#define CAN_RXF0DL_BYTE3_MSK BITS(CAN_RXF0DL_BYTE3_POSS,CAN_RXF0DL_BYTE3_POSE) + +#define CAN_RXF0DL_BYTE2_POSS 16U +#define CAN_RXF0DL_BYTE2_POSE 23U +#define CAN_RXF0DL_BYTE2_MSK BITS(CAN_RXF0DL_BYTE2_POSS,CAN_RXF0DL_BYTE2_POSE) + +#define CAN_RXF0DL_BYTE1_POSS 8U +#define CAN_RXF0DL_BYTE1_POSE 15U +#define CAN_RXF0DL_BYTE1_MSK BITS(CAN_RXF0DL_BYTE1_POSS,CAN_RXF0DL_BYTE1_POSE) + +#define CAN_RXF0DL_BYTE0_POSS 0U +#define CAN_RXF0DL_BYTE0_POSE 7U +#define CAN_RXF0DL_BYTE0_MSK BITS(CAN_RXF0DL_BYTE0_POSS,CAN_RXF0DL_BYTE0_POSE) + +/****************** Bit definition for CAN_RXF0DH register ************************/ + +#define CAN_RXF0DH_BYTE7_POSS 24U +#define CAN_RXF0DH_BYTE7_POSE 31U +#define CAN_RXF0DH_BYTE7_MSK BITS(CAN_RXF0DH_BYTE7_POSS,CAN_RXF0DH_BYTE7_POSE) + +#define CAN_RXF0DH_BYTE6_POSS 16U +#define CAN_RXF0DH_BYTE6_POSE 23U +#define CAN_RXF0DH_BYTE6_MSK BITS(CAN_RXF0DH_BYTE6_POSS,CAN_RXF0DH_BYTE6_POSE) + +#define CAN_RXF0DH_BYTE5_POSS 8U +#define CAN_RXF0DH_BYTE5_POSE 15U +#define CAN_RXF0DH_BYTE5_MSK BITS(CAN_RXF0DH_BYTE5_POSS,CAN_RXF0DH_BYTE5_POSE) + +#define CAN_RXF0DH_BYTE4_POSS 0U +#define CAN_RXF0DH_BYTE4_POSE 7U +#define CAN_RXF0DH_BYTE4_MSK BITS(CAN_RXF0DH_BYTE4_POSS,CAN_RXF0DH_BYTE4_POSE) + +/****************** Bit definition for CAN_RXF1ID register ************************/ + +#define CAN_RXF1ID_STDID_POSS 21U +#define CAN_RXF1ID_STDID_POSE 31U +#define CAN_RXF1ID_STDID_MSK BITS(CAN_RXF1ID_STDID_POSS,CAN_RXF1ID_STDID_POSE) + +#define CAN_RXF1ID_EXID_POSS 3U +#define CAN_RXF1ID_EXID_POSE 20U +#define CAN_RXF1ID_EXID_MSK BITS(CAN_RXF1ID_EXID_POSS,CAN_RXF1ID_EXID_POSE) + +#define CAN_RXF1ID_IDE_POS 2U +#define CAN_RXF1ID_IDE_MSK BIT(CAN_RXF1ID_IDE_POS) + +#define CAN_RXF1ID_RTR_POS 1U +#define CAN_RXF1ID_RTR_MSK BIT(CAN_RXF1ID_RTR_POS) + +/****************** Bit definition for CAN_RXF1INF register ************************/ + +#define CAN_RXF1INF_STAMP_POSS 16U +#define CAN_RXF1INF_STAMP_POSE 31U +#define CAN_RXF1INF_STAMP_MSK BITS(CAN_RXF1INF_STAMP_POSS,CAN_RXF1INF_STAMP_POSE) + +#define CAN_RXF1INF_FLTIDX_POSS 8U +#define CAN_RXF1INF_FLTIDX_POSE 15U +#define CAN_RXF1INF_FLTIDX_MSK BITS(CAN_RXF1INF_FLTIDX_POSS,CAN_RXF1INF_FLTIDX_POSE) + +#define CAN_RXF1INF_DLEN_POSS 0U +#define CAN_RXF1INF_DLEN_POSE 3U +#define CAN_RXF1INF_DLEN_MSK BITS(CAN_RXF1INF_DLEN_POSS,CAN_RXF1INF_DLEN_POSE) + +/****************** Bit definition for CAN_RXF1DL register ************************/ + +#define CAN_RXF1DL_BYTE3_POSS 24U +#define CAN_RXF1DL_BYTE3_POSE 31U +#define CAN_RXF1DL_BYTE3_MSK BITS(CAN_RXF1DL_BYTE3_POSS,CAN_RXF1DL_BYTE3_POSE) + +#define CAN_RXF1DL_BYTE2_POSS 16U +#define CAN_RXF1DL_BYTE2_POSE 23U +#define CAN_RXF1DL_BYTE2_MSK BITS(CAN_RXF1DL_BYTE2_POSS,CAN_RXF1DL_BYTE2_POSE) + +#define CAN_RXF1DL_BYTE1_POSS 8U +#define CAN_RXF1DL_BYTE1_POSE 15U +#define CAN_RXF1DL_BYTE1_MSK BITS(CAN_RXF1DL_BYTE1_POSS,CAN_RXF1DL_BYTE1_POSE) + +#define CAN_RXF1DL_BYTE0_POSS 0U +#define CAN_RXF1DL_BYTE0_POSE 7U +#define CAN_RXF1DL_BYTE0_MSK BITS(CAN_RXF1DL_BYTE0_POSS,CAN_RXF1DL_BYTE0_POSE) + +/****************** Bit definition for CAN_RXF1DH register ************************/ + +#define CAN_RXF1DH_BYTE7_POSS 24U +#define CAN_RXF1DH_BYTE7_POSE 31U +#define CAN_RXF1DH_BYTE7_MSK BITS(CAN_RXF1DH_BYTE7_POSS,CAN_RXF1DH_BYTE7_POSE) + +#define CAN_RXF1DH_BYTE6_POSS 16U +#define CAN_RXF1DH_BYTE6_POSE 23U +#define CAN_RXF1DH_BYTE6_MSK BITS(CAN_RXF1DH_BYTE6_POSS,CAN_RXF1DH_BYTE6_POSE) + +#define CAN_RXF1DH_BYTE5_POSS 8U +#define CAN_RXF1DH_BYTE5_POSE 15U +#define CAN_RXF1DH_BYTE5_MSK BITS(CAN_RXF1DH_BYTE5_POSS,CAN_RXF1DH_BYTE5_POSE) + +#define CAN_RXF1DH_BYTE4_POSS 0U +#define CAN_RXF1DH_BYTE4_POSE 7U +#define CAN_RXF1DH_BYTE4_MSK BITS(CAN_RXF1DH_BYTE4_POSS,CAN_RXF1DH_BYTE4_POSE) + +/****************** Bit definition for CAN_FLTCON register ************************/ + +#define CAN_FLTCON_FLTINI_POS 0U +#define CAN_FLTCON_FLTINI_MSK BIT(CAN_FLTCON_FLTINI_POS) + +/****************** Bit definition for CAN_FLTM register ************************/ + +#define CAN_FLTM_MOD_POSS 0U +#define CAN_FLTM_MOD_POSE 13U +#define CAN_FLTM_MOD_MSK BITS(CAN_FLTM_MOD_POSS,CAN_FLTM_MOD_POSE) + +/****************** Bit definition for CAN_FLTWS register ************************/ + +#define CAN_FLTWS_SEL_POSS 0U +#define CAN_FLTWS_SEL_POSE 13U +#define CAN_FLTWS_SEL_MSK BITS(CAN_FLTWS_SEL_POSS,CAN_FLTWS_SEL_POSE) + +/****************** Bit definition for CAN_FLTAS register ************************/ + +#define CAN_FLTAS_ASSIGN_POSS 0U +#define CAN_FLTAS_ASSIGN_POSE 13U +#define CAN_FLTAS_ASSIGN_MSK BITS(CAN_FLTAS_ASSIGN_POSS,CAN_FLTAS_ASSIGN_POSE) + +/****************** Bit definition for CAN_FLTGO register ************************/ + +#define CAN_FLTGO_GO_POSS 0U +#define CAN_FLTGO_GO_POSE 13U +#define CAN_FLTGO_GO_MSK BITS(CAN_FLTGO_GO_POSS,CAN_FLTGO_GO_POSE) + +typedef struct { + __IO uint32_t TXID; + __IO uint32_t TXFCON; + __IO uint32_t TXDL; + __IO uint32_t TXDH; +} CAN_TxMailBox_Typedef; + +typedef struct { + __IO uint32_t RXFID; + __IO uint32_t RXFINF; + __IO uint32_t RXFDL; + __IO uint32_t RXFDH; +} CAN_RxFIFO_Typedef; + +typedef struct { + __IO uint32_t FLT1; + __IO uint32_t FLT2; +} CAN_Filter_Typedef; + +typedef struct +{ + __IO uint32_t CON; + __I uint32_t STAT; + __O uint32_t IFC; + __IO uint32_t TXSTAT; + __O uint32_t TXSTATC; + __IO uint32_t RXF0; + __O uint32_t RXF0C; + __IO uint32_t RXF1; + __O uint32_t RXF1C; + __IO uint32_t IE; + __IO uint32_t ERRSTAT; + __IO uint32_t BTIME; + uint32_t RESERVED0[84] ; + CAN_TxMailBox_Typedef TxMailBox[3]; + CAN_RxFIFO_Typedef RxFIFO[2]; + uint32_t RESERVED1[12] ; + __IO uint32_t FLTCON; + __IO uint32_t FLTM; + uint32_t RESERVED2 ; + __IO uint32_t FLTWS; + uint32_t RESERVED3 ; + __IO uint32_t FLTAS; + uint32_t RESERVED4 ; + __IO uint32_t FLTGO; + uint32_t RESERVED5[8] ; + CAN_Filter_Typedef Filter[14]; +} CAN_TypeDef; + +/****************** Bit definition for CRC_CR register ************************/ +#define CRC_CR_BYTORD_POS 24U +#define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS) + +#define CRC_CR_DATLEN_POSS 22U +#define CRC_CR_DATLEN_POSE 23U +#define CRC_CR_DATLEN_MSK BITS(CRC_CR_DATLEN_POSS,CRC_CR_DATLEN_POSE) + +#define CRC_CR_MODE_POSS 20U +#define CRC_CR_MODE_POSE 21U +#define CRC_CR_MODE_MSK BITS(CRC_CR_MODE_POSS,CRC_CR_MODE_POSE) + +#define CRC_CR_CHSINV_POS 19U +#define CRC_CR_CHSINV_MSK BIT(CRC_CR_CHSINV_POS) + +#define CRC_CR_DATINV_POS 18U +#define CRC_CR_DATINV_MSK BIT(CRC_CR_DATINV_POS) + +#define CRC_CR_CHSREV_POS 17U +#define CRC_CR_CHSREV_MSK BIT(CRC_CR_CHSREV_POS) + +#define CRC_CR_DATREV_POS 16U +#define CRC_CR_DATREV_MSK BIT(CRC_CR_DATREV_POS) + +#define CRC_CR_DMAEN_POS 4U +#define CRC_CR_DMAEN_MSK BIT(CRC_CR_DMAEN_POS) + +#define CRC_CR_CWERR_POS 3U +#define CRC_CR_CWERR_MSK BIT(CRC_CR_CWERR_POS) + +#define CRC_CR_WERR_POS 2U +#define CRC_CR_WERR_MSK BIT(CRC_CR_WERR_POS) + +#define CRC_CR_RST_POS 1U +#define CRC_CR_RST_MSK BIT(CRC_CR_RST_POS) + +#define CRC_CR_EN_POS 0U +#define CRC_CR_EN_MSK BIT(CRC_CR_EN_POS) + +/****************** Bit definition for CRC_DATA register ************************/ + +#define CRC_DATA_DATA_POSS 0U +#define CRC_DATA_DATA_POSE 31U +#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) + +/****************** Bit definition for CRC_SEED register ************************/ + +#define CRC_SEED_SEED_POSS 0U +#define CRC_SEED_SEED_POSE 31U +#define CRC_SEED_SEED_MSK BITS(CRC_SEED_SEED_POSS,CRC_SEED_SEED_POSE) + +/****************** Bit definition for CRC_CHECKSUM register ************************/ + +#define CRC_CHECKSUM_CHECKSUM_POSS 0U +#define CRC_CHECKSUM_CHECKSUM_POSE 31U +#define CRC_CHECKSUM_CHECKSUM_MSK BITS(CRC_CHECKSUM_CHECKSUM_POSS,CRC_CHECKSUM_CHECKSUM_POSE) + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t DATA; + __IO uint32_t SEED; + __I uint32_t CHECKSUM; +} CRC_TypeDef; + +/****************** Bit definition for CRYPT_CON register ************************/ + +#define CRYPT_CON_CRYSEL_POS 31U +#define CRYPT_CON_CRYSEL_MSK BIT(CRYPT_CON_CRYSEL_POS) + +#define CRYPT_CON_RESCLR_POS 15U +#define CRYPT_CON_RESCLR_MSK BIT(CRYPT_CON_RESCLR_POS) + +#define CRYPT_CON_DMAEN_POS 14U +#define CRYPT_CON_DMAEN_MSK BIT(CRYPT_CON_DMAEN_POS) + +#define CRYPT_CON_FIFOODR_POS 13U +#define CRYPT_CON_FIFOODR_MSK BIT(CRYPT_CON_FIFOODR_POS) + +#define CRYPT_CON_FIFOEN_POS 12U +#define CRYPT_CON_FIFOEN_MSK BIT(CRYPT_CON_FIFOEN_POS) + +#define CRYPT_CON_DESKS_POS 11U +#define CRYPT_CON_DESKS_MSK BIT(CRYPT_CON_DESKS_POS) + +#define CRYPT_CON_TDES_POS 10U +#define CRYPT_CON_TDES_MSK BIT(CRYPT_CON_TDES_POS) + +#define CRYPT_CON_TYPE_POSS 8U +#define CRYPT_CON_TYPE_POSE 9U +#define CRYPT_CON_TYPE_MSK BITS(CRYPT_CON_TYPE_POSS,CRYPT_CON_TYPE_POSE) + +#define CRYPT_CON_IE_POS 7U +#define CRYPT_CON_IE_MSK BIT(CRYPT_CON_IE_POS) + +#define CRYPT_CON_IVEN_POS 6U +#define CRYPT_CON_IVEN_MSK BIT(CRYPT_CON_IVEN_POS) + +#define CRYPT_CON_MODE_POSS 4U +#define CRYPT_CON_MODE_POSE 5U +#define CRYPT_CON_MODE_MSK BITS(CRYPT_CON_MODE_POSS,CRYPT_CON_MODE_POSE) + +#define CRYPT_CON_AESKS_POSS 2U +#define CRYPT_CON_AESKS_POSE 3U +#define CRYPT_CON_AESKS_MSK BITS(CRYPT_CON_AESKS_POSS,CRYPT_CON_AESKS_POSE) + +#define CRYPT_CON_ENCS_POS 1U +#define CRYPT_CON_ENCS_MSK BIT(CRYPT_CON_ENCS_POS) + +#define CRYPT_CON_GO_POS 0U +#define CRYPT_CON_GO_MSK BIT(CRYPT_CON_GO_POS) + +/****************** Bit definition for CRYPT_IF register ************************/ + +#define CRYPT_IF_DONE_POS 8U +#define CRYPT_IF_DONE_MSK BIT(CRYPT_IF_DONE_POS) + +#define CRYPT_IF_MULTHIF_POS 2U +#define CRYPT_IF_MULTHIF_MSK BIT(CRYPT_IF_MULTHIF_POS) + +#define CRYPT_IF_DESIF_POS 1U +#define CRYPT_IF_DESIF_MSK BIT(CRYPT_IF_DESIF_POS) + +#define CRYPT_IF_AESIF_POS 0U +#define CRYPT_IF_AESIF_MSK BIT(CRYPT_IF_AESIF_POS) + +/****************** Bit definition for CRYPT_IFC register ************************/ + +#define CRYPT_IFC_MULTHIFC_POS 2U +#define CRYPT_IFC_MULTHIFC_MSK BIT(CRYPT_IFC_MULTHIFC_POS) + +#define CRYPT_IFC_DESIFC_POS 1U +#define CRYPT_IFC_DESIFC_MSK BIT(CRYPT_IFC_DESIFC_POS) + +#define CRYPT_IFC_AESIFC_POS 0U +#define CRYPT_IFC_AESIFC_MSK BIT(CRYPT_IFC_AESIFC_POS) + +/****************** Bit definition for CRYPT_FIFO register ************************/ + +#define CRYPT_FIFO_FIFO_POSS 0U +#define CRYPT_FIFO_FIFO_POSE 31U +#define CRYPT_FIFO_FIFO_MSK BITS(CRYPT_FIFO_FIFO_POSS,CRYPT_FIFO_FIFO_POSE) + +typedef struct +{ + __IO uint32_t DATA[4]; + __IO uint32_t KEY[8]; + __IO uint32_t IV[4]; + __I uint32_t RES[4]; + __IO uint32_t CON; + __I uint32_t IF; + __O uint32_t IFC; + __IO uint32_t FIFO; +} CRYPT_TypeDef; + +/****************** Bit definition for LCD_CR register ************************/ + +#define LCD_CR_VCHPS_POSS 24U +#define LCD_CR_VCHPS_POSE 25U +#define LCD_CR_VCHPS_MSK BITS(LCD_CR_VCHPS_POSS,LCD_CR_VCHPS_POSE) + +#define LCD_CR_DSLD_POSS 20U +#define LCD_CR_DSLD_POSE 23U +#define LCD_CR_DSLD_MSK BITS(LCD_CR_DSLD_POSS,LCD_CR_DSLD_POSE) + +#define LCD_CR_DSHD_POSS 16U +#define LCD_CR_DSHD_POSE 19U +#define LCD_CR_DSHD_MSK BITS(LCD_CR_DSHD_POSS,LCD_CR_DSHD_POSE) + +#define LCD_CR_VBUFLD_POS 15U +#define LCD_CR_VBUFLD_MSK BIT(LCD_CR_VBUFLD_POS) + +#define LCD_CR_VBUFHD_POS 14U +#define LCD_CR_VBUFHD_MSK BIT(LCD_CR_VBUFHD_POS) + +#define LCD_CR_RESLD_POSS 12U +#define LCD_CR_RESLD_POSE 13U +#define LCD_CR_RESLD_MSK BITS(LCD_CR_RESLD_POSS,LCD_CR_RESLD_POSE) + +#define LCD_CR_RESHD_POSS 10U +#define LCD_CR_RESHD_POSE 11U +#define LCD_CR_RESHD_MSK BITS(LCD_CR_RESHD_POSS,LCD_CR_RESHD_POSE) + +#define LCD_CR_BIAS_POSS 8U +#define LCD_CR_BIAS_POSE 9U +#define LCD_CR_BIAS_MSK BITS(LCD_CR_BIAS_POSS,LCD_CR_BIAS_POSE) + +#define LCD_CR_DUTY_POSS 4U +#define LCD_CR_DUTY_POSE 6U +#define LCD_CR_DUTY_MSK BITS(LCD_CR_DUTY_POSS,LCD_CR_DUTY_POSE) + +#define LCD_CR_OE_POS 3U +#define LCD_CR_OE_MSK BIT(LCD_CR_OE_POS) + +#define LCD_CR_VSEL_POSS 1U +#define LCD_CR_VSEL_POSE 2U +#define LCD_CR_VSEL_MSK BITS(LCD_CR_VSEL_POSS,LCD_CR_VSEL_POSE) + +#define LCD_CR_EN_POS 0U +#define LCD_CR_EN_MSK BIT(LCD_CR_EN_POS) + +/****************** Bit definition for LCD_FCR register ************************/ + +#define LCD_FCR_WFS_POS 31U +#define LCD_FCR_WFS_MSK BIT(LCD_FCR_WFS_POS) + +#define LCD_FCR_PRS_POSS 24U +#define LCD_FCR_PRS_POSE 27U +#define LCD_FCR_PRS_MSK BITS(LCD_FCR_PRS_POSS,LCD_FCR_PRS_POSE) + +#define LCD_FCR_DIV_POSS 20U +#define LCD_FCR_DIV_POSE 23U +#define LCD_FCR_DIV_MSK BITS(LCD_FCR_DIV_POSS,LCD_FCR_DIV_POSE) + +#define LCD_FCR_BLMOD_POSS 16U +#define LCD_FCR_BLMOD_POSE 17U +#define LCD_FCR_BLMOD_MSK BITS(LCD_FCR_BLMOD_POSS,LCD_FCR_BLMOD_POSE) + +#define LCD_FCR_BLFRQ_POSS 12U +#define LCD_FCR_BLFRQ_POSE 14U +#define LCD_FCR_BLFRQ_MSK BITS(LCD_FCR_BLFRQ_POSS,LCD_FCR_BLFRQ_POSE) + +#define LCD_FCR_DEAD_POSS 8U +#define LCD_FCR_DEAD_POSE 10U +#define LCD_FCR_DEAD_MSK BITS(LCD_FCR_DEAD_POSS,LCD_FCR_DEAD_POSE) + +#define LCD_FCR_HD_POS 7U +#define LCD_FCR_HD_MSK BIT(LCD_FCR_HD_POS) + +#define LCD_FCR_PON_POSS 4U +#define LCD_FCR_PON_POSE 6U +#define LCD_FCR_PON_MSK BITS(LCD_FCR_PON_POSS,LCD_FCR_PON_POSE) + +#define LCD_FCR_VGS_POSS 0U +#define LCD_FCR_VGS_POSE 3U +#define LCD_FCR_VGS_MSK BITS(LCD_FCR_VGS_POSS,LCD_FCR_VGS_POSE) + +/****************** Bit definition for LCD_SEGCR0 register ************************/ + +#define LCD_SEGCR0_SEG_OE_POSS 0U +#define LCD_SEGCR0_SEG_OE_POSE 31U +#define LCD_SEGCR0_SEG_OE_MSK BITS(LCD_SEGCR0_SEG_OE_POSS,LCD_SEGCR0_SEG_OE_POSE) + +/****************** Bit definition for LCD_SEGCR1 register ************************/ + +#define LCD_SEGCR1_SEG_OE_POSS 0U +#define LCD_SEGCR1_SEG_OE_POSE 11U +#define LCD_SEGCR1_SEG_OE_MSK BITS(LCD_SEGCR1_SEG_OE_POSS,LCD_SEGCR1_SEG_OE_POSE) + +/****************** Bit definition for LCD_IE register ************************/ + +#define LCD_IE_UDDIE_POS 1U +#define LCD_IE_UDDIE_MSK BIT(LCD_IE_UDDIE_POS) + +#define LCD_IE_SOFIE_POS 0U +#define LCD_IE_SOFIE_MSK BIT(LCD_IE_SOFIE_POS) + +/****************** Bit definition for LCD_IF register ************************/ + +#define LCD_IF_UDDIF_POS 1U +#define LCD_IF_UDDIF_MSK BIT(LCD_IF_UDDIF_POS) + +#define LCD_IF_SOFIF_POS 0U +#define LCD_IF_SOFIF_MSK BIT(LCD_IF_SOFIF_POS) + +/****************** Bit definition for LCD_IFCR register ************************/ + +#define LCD_IFCR_UDDIFC_POS 1U +#define LCD_IFCR_UDDIFC_MSK BIT(LCD_IFCR_UDDIFC_POS) + +#define LCD_IFCR_SOFIFC_POS 0U +#define LCD_IFCR_SOFIFC_MSK BIT(LCD_IFCR_SOFIFC_POS) + +/****************** Bit definition for LCD_SR register ************************/ + +#define LCD_SR_FCRSF_POS 3U +#define LCD_SR_FCRSF_MSK BIT(LCD_SR_FCRSF_POS) + +#define LCD_SR_UDR_POS 2U +#define LCD_SR_UDR_MSK BIT(LCD_SR_UDR_POS) + +#define LCD_SR_ENS_POS 1U +#define LCD_SR_ENS_MSK BIT(LCD_SR_ENS_POS) + +#define LCD_SR_RDY_POS 0U +#define LCD_SR_RDY_MSK BIT(LCD_SR_RDY_POS) + +/****************** Bit definition for LCD_BUF register ************************/ + +#define LCD_BUF_SEG_DATA_POSS 0U +#define LCD_BUF_SEG_DATA_POSE 31U +#define LCD_BUF_SEG_DATA_MSK BITS(LCD_BUF_SEG_DATA_POSS,LCD_BUF_SEG_DATA_POSE) + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t FCR; + __IO uint32_t SEGCR0; + __IO uint32_t SEGCR1; + __IO uint32_t IE; + __I uint32_t IF; + __O uint32_t IFCR; + __I uint32_t SR; + uint32_t RESERVED0[8] ; + __IO uint32_t BUF[16]; +} LCD_TypeDef; + +/****************** Bit definition for ADC_STAT register ************************/ + +#define ADC_STAT_ICHS_POS 9U +#define ADC_STAT_ICHS_MSK BIT(ADC_STAT_ICHS_POS) + +#define ADC_STAT_NCHS_POS 8U +#define ADC_STAT_NCHS_MSK BIT(ADC_STAT_NCHS_POS) + +#define ADC_STAT_OVR_POS 3U +#define ADC_STAT_OVR_MSK BIT(ADC_STAT_OVR_POS) + +#define ADC_STAT_ICHE_POS 2U +#define ADC_STAT_ICHE_MSK BIT(ADC_STAT_ICHE_POS) + +#define ADC_STAT_NCHE_POS 1U +#define ADC_STAT_NCHE_MSK BIT(ADC_STAT_NCHE_POS) + +#define ADC_STAT_AWDF_POS 0U +#define ADC_STAT_AWDF_MSK BIT(ADC_STAT_AWDF_POS) + +/****************** Bit definition for ADC_CLR register ************************/ + +#define ADC_CLR_ICHS_POS 9U +#define ADC_CLR_ICHS_MSK BIT(ADC_CLR_ICHS_POS) + +#define ADC_CLR_NCHS_POS 8U +#define ADC_CLR_NCHS_MSK BIT(ADC_CLR_NCHS_POS) + +#define ADC_CLR_OVR_POS 3U +#define ADC_CLR_OVR_MSK BIT(ADC_CLR_OVR_POS) + +#define ADC_CLR_ICHE_POS 2U +#define ADC_CLR_ICHE_MSK BIT(ADC_CLR_ICHE_POS) + +#define ADC_CLR_NCHE_POS 1U +#define ADC_CLR_NCHE_MSK BIT(ADC_CLR_NCHE_POS) + +#define ADC_CLR_AWDF_POS 0U +#define ADC_CLR_AWDF_MSK BIT(ADC_CLR_AWDF_POS) + +/****************** Bit definition for ADC_CON0 register ************************/ + +#define ADC_CON0_OVRIE_POS 26U +#define ADC_CON0_OVRIE_MSK BIT(ADC_CON0_OVRIE_POS) + +#define ADC_CON0_RSEL_POSS 24U +#define ADC_CON0_RSEL_POSE 25U +#define ADC_CON0_RSEL_MSK BITS(ADC_CON0_RSEL_POSS,ADC_CON0_RSEL_POSE) + +#define ADC_CON0_NCHWDEN_POS 23U +#define ADC_CON0_NCHWDEN_MSK BIT(ADC_CON0_NCHWDEN_POS) + +#define ADC_CON0_ICHWDTEN_POS 22U +#define ADC_CON0_ICHWDTEN_MSK BIT(ADC_CON0_ICHWDTEN_POS) + +#define ADC_CON0_ETRGN_POSS 13U +#define ADC_CON0_ETRGN_POSE 15U +#define ADC_CON0_ETRGN_MSK BITS(ADC_CON0_ETRGN_POSS,ADC_CON0_ETRGN_POSE) + +#define ADC_CON0_ICHDCEN_POS 12U +#define ADC_CON0_ICHDCEN_MSK BIT(ADC_CON0_ICHDCEN_POS) + +#define ADC_CON0_NCHDCEN_POS 11U +#define ADC_CON0_NCHDCEN_MSK BIT(ADC_CON0_NCHDCEN_POS) + +#define ADC_CON0_IAUTO_POS 10U +#define ADC_CON0_IAUTO_MSK BIT(ADC_CON0_IAUTO_POS) + +#define ADC_CON0_AWDSGL_POS 9U +#define ADC_CON0_AWDSGL_MSK BIT(ADC_CON0_AWDSGL_POS) + +#define ADC_CON0_SCANEN_POS 8U +#define ADC_CON0_SCANEN_MSK BIT(ADC_CON0_SCANEN_POS) + +#define ADC_CON0_ICHEIE_POS 7U +#define ADC_CON0_ICHEIE_MSK BIT(ADC_CON0_ICHEIE_POS) + +#define ADC_CON0_AWDIE_POS 6U +#define ADC_CON0_AWDIE_MSK BIT(ADC_CON0_AWDIE_POS) + +#define ADC_CON0_NCHEIE_POS 5U +#define ADC_CON0_NCHEIE_MSK BIT(ADC_CON0_NCHEIE_POS) + +#define ADC_CON0_AWDCH_POSS 0U +#define ADC_CON0_AWDCH_POSE 4U +#define ADC_CON0_AWDCH_MSK BITS(ADC_CON0_AWDCH_POSS,ADC_CON0_AWDCH_POSE) + +/****************** Bit definition for ADC_CON1 register ************************/ + +#define ADC_CON1_NCHTRG_POS 30U +#define ADC_CON1_NCHTRG_MSK BIT(ADC_CON1_NCHTRG_POS) + +#define ADC_CON1_ICHTRG_POS 22U +#define ADC_CON1_ICHTRG_MSK BIT(ADC_CON1_ICHTRG_POS) + +#define ADC_CON1_ALIGN_POS 11U +#define ADC_CON1_ALIGN_MSK BIT(ADC_CON1_ALIGN_POS) + +#define ADC_CON1_NCHESEL_POS 10U +#define ADC_CON1_NCHESEL_MSK BIT(ADC_CON1_NCHESEL_POS) + +#define ADC_CON1_OVRDIS_POS 8U +#define ADC_CON1_OVRDIS_MSK BIT(ADC_CON1_OVRDIS_POS) + +#define ADC_CON1_CM_POS 1U +#define ADC_CON1_CM_MSK BIT(ADC_CON1_CM_POS) + +#define ADC_CON1_ADCEN_POS 0U +#define ADC_CON1_ADCEN_MSK BIT(ADC_CON1_ADCEN_POS) + +/****************** Bit definition for ADC_SMPT1 register ************************/ + +#define ADC_SMPT1_CHT_POSS 0U +#define ADC_SMPT1_CHT_POSE 31U +#define ADC_SMPT1_CHT_MSK BITS(ADC_SMPT1_CHT_POSS,ADC_SMPT1_CHT_POSE) + +/****************** Bit definition for ADC_SMPT2 register ************************/ + +#define ADC_SMPT2_CHT_POSS 0U +#define ADC_SMPT2_CHT_POSE 7U +#define ADC_SMPT2_CHT_MSK BITS(ADC_SMPT2_CHT_POSS,ADC_SMPT2_CHT_POSE) + +/****************** Bit definition for ADC_ICHOFF1 register ************************/ + +#define ADC_ICHOFF1_IOFF_POSS 0U +#define ADC_ICHOFF1_IOFF_POSE 11U +#define ADC_ICHOFF1_IOFF_MSK BITS(ADC_ICHOFF1_IOFF_POSS,ADC_ICHOFF1_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF2 register ************************/ + +#define ADC_ICHOFF2_IOFF_POSS 0U +#define ADC_ICHOFF2_IOFF_POSE 11U +#define ADC_ICHOFF2_IOFF_MSK BITS(ADC_ICHOFF2_IOFF_POSS,ADC_ICHOFF2_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF3 register ************************/ + +#define ADC_ICHOFF3_IOFF_POSS 0U +#define ADC_ICHOFF3_IOFF_POSE 11U +#define ADC_ICHOFF3_IOFF_MSK BITS(ADC_ICHOFF3_IOFF_POSS,ADC_ICHOFF3_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF4 register ************************/ + +#define ADC_ICHOFF4_IOFF_POSS 0U +#define ADC_ICHOFF4_IOFF_POSE 11U +#define ADC_ICHOFF4_IOFF_MSK BITS(ADC_ICHOFF4_IOFF_POSS,ADC_ICHOFF4_IOFF_POSE) + +/****************** Bit definition for ADC_WDTH register ************************/ + +#define ADC_WDTH_HT_POSS 0U +#define ADC_WDTH_HT_POSE 11U +#define ADC_WDTH_HT_MSK BITS(ADC_WDTH_HT_POSS,ADC_WDTH_HT_POSE) + +/****************** Bit definition for ADC_WDTL register ************************/ + +#define ADC_WDTL_LT_POSS 0U +#define ADC_WDTL_LT_POSE 11U +#define ADC_WDTL_LT_MSK BITS(ADC_WDTL_LT_POSS,ADC_WDTL_LT_POSE) + +/****************** Bit definition for ADC_NCHS1 register ************************/ + +#define ADC_NCHS1_NS4_POSS 24U +#define ADC_NCHS1_NS4_POSE 28U +#define ADC_NCHS1_NS4_MSK BITS(ADC_NCHS1_NS4_POSS,ADC_NCHS1_NS4_POSE) + +#define ADC_NCHS1_NS3_POSS 16U +#define ADC_NCHS1_NS3_POSE 20U +#define ADC_NCHS1_NS3_MSK BITS(ADC_NCHS1_NS3_POSS,ADC_NCHS1_NS3_POSE) + +#define ADC_NCHS1_NS2_POSS 8U +#define ADC_NCHS1_NS2_POSE 12U +#define ADC_NCHS1_NS2_MSK BITS(ADC_NCHS1_NS2_POSS,ADC_NCHS1_NS2_POSE) + +#define ADC_NCHS1_NS1_POSS 0U +#define ADC_NCHS1_NS1_POSE 4U +#define ADC_NCHS1_NS1_MSK BITS(ADC_NCHS1_NS1_POSS,ADC_NCHS1_NS1_POSE) + +/****************** Bit definition for ADC_NCHS2 register ************************/ + +#define ADC_NCHS2_NS8_POSS 24U +#define ADC_NCHS2_NS8_POSE 28U +#define ADC_NCHS2_NS8_MSK BITS(ADC_NCHS2_NS8_POSS,ADC_NCHS2_NS8_POSE) + +#define ADC_NCHS2_NS7_POSS 16U +#define ADC_NCHS2_NS7_POSE 20U +#define ADC_NCHS2_NS7_MSK BITS(ADC_NCHS2_NS7_POSS,ADC_NCHS2_NS7_POSE) + +#define ADC_NCHS2_NS6_POSS 8U +#define ADC_NCHS2_NS6_POSE 12U +#define ADC_NCHS2_NS6_MSK BITS(ADC_NCHS2_NS6_POSS,ADC_NCHS2_NS6_POSE) + +#define ADC_NCHS2_NS5_POSS 0U +#define ADC_NCHS2_NS5_POSE 4U +#define ADC_NCHS2_NS5_MSK BITS(ADC_NCHS2_NS5_POSS,ADC_NCHS2_NS5_POSE) + +/****************** Bit definition for ADC_NCHS3 register ************************/ + +#define ADC_NCHS3_NS12_POSS 24U +#define ADC_NCHS3_NS12_POSE 28U +#define ADC_NCHS3_NS12_MSK BITS(ADC_NCHS3_NS12_POSS,ADC_NCHS3_NS12_POSE) + +#define ADC_NCHS3_NS11_POSS 16U +#define ADC_NCHS3_NS11_POSE 20U +#define ADC_NCHS3_NS11_MSK BITS(ADC_NCHS3_NS11_POSS,ADC_NCHS3_NS11_POSE) + +#define ADC_NCHS3_NS10_POSS 8U +#define ADC_NCHS3_NS10_POSE 12U +#define ADC_NCHS3_NS10_MSK BITS(ADC_NCHS3_NS10_POSS,ADC_NCHS3_NS10_POSE) + +#define ADC_NCHS3_NS9_POSS 0U +#define ADC_NCHS3_NS9_POSE 4U +#define ADC_NCHS3_NS9_MSK BITS(ADC_NCHS3_NS9_POSS,ADC_NCHS3_NS9_POSE) + +/****************** Bit definition for ADC_NCHS4 register ************************/ + +#define ADC_NCHS4_NS16_POSS 24U +#define ADC_NCHS4_NS16_POSE 28U +#define ADC_NCHS4_NS16_MSK BITS(ADC_NCHS4_NS16_POSS,ADC_NCHS4_NS16_POSE) + +#define ADC_NCHS4_NS15_POSS 16U +#define ADC_NCHS4_NS15_POSE 20U +#define ADC_NCHS4_NS15_MSK BITS(ADC_NCHS4_NS15_POSS,ADC_NCHS4_NS15_POSE) + +#define ADC_NCHS4_NS14_POSS 8U +#define ADC_NCHS4_NS14_POSE 12U +#define ADC_NCHS4_NS14_MSK BITS(ADC_NCHS4_NS14_POSS,ADC_NCHS4_NS14_POSE) + +#define ADC_NCHS4_NS13_POSS 0U +#define ADC_NCHS4_NS13_POSE 4U +#define ADC_NCHS4_NS13_MSK BITS(ADC_NCHS4_NS13_POSS,ADC_NCHS4_NS13_POSE) + +/****************** Bit definition for ADC_ICHS register ************************/ + +#define ADC_ICHS_IS4_POSS 24U +#define ADC_ICHS_IS4_POSE 28U +#define ADC_ICHS_IS4_MSK BITS(ADC_ICHS_IS4_POSS,ADC_ICHS_IS4_POSE) + +#define ADC_ICHS_IS3_POSS 16U +#define ADC_ICHS_IS3_POSE 20U +#define ADC_ICHS_IS3_MSK BITS(ADC_ICHS_IS3_POSS,ADC_ICHS_IS3_POSE) + +#define ADC_ICHS_IS2_POSS 8U +#define ADC_ICHS_IS2_POSE 12U +#define ADC_ICHS_IS2_MSK BITS(ADC_ICHS_IS2_POSS,ADC_ICHS_IS2_POSE) + +#define ADC_ICHS_IS1_POSS 0U +#define ADC_ICHS_IS1_POSE 4U +#define ADC_ICHS_IS1_MSK BITS(ADC_ICHS_IS1_POSS,ADC_ICHS_IS1_POSE) + +/****************** Bit definition for ADC_CHSL register ************************/ + +#define ADC_CHSL_ISL_POSS 8U +#define ADC_CHSL_ISL_POSE 9U +#define ADC_CHSL_ISL_MSK BITS(ADC_CHSL_ISL_POSS,ADC_CHSL_ISL_POSE) + +#define ADC_CHSL_NSL_POSS 0U +#define ADC_CHSL_NSL_POSE 3U +#define ADC_CHSL_NSL_MSK BITS(ADC_CHSL_NSL_POSS,ADC_CHSL_NSL_POSE) + +/****************** Bit definition for ADC_ICHDR1 register ************************/ + +#define ADC_ICHDR1_VAL_POSS 0U +#define ADC_ICHDR1_VAL_POSE 15U +#define ADC_ICHDR1_VAL_MSK BITS(ADC_ICHDR1_VAL_POSS,ADC_ICHDR1_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR2 register ************************/ + +#define ADC_ICHDR2_VAL_POSS 0U +#define ADC_ICHDR2_VAL_POSE 15U +#define ADC_ICHDR2_VAL_MSK BITS(ADC_ICHDR2_VAL_POSS,ADC_ICHDR2_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR3 register ************************/ + +#define ADC_ICHDR3_VAL_POSS 0U +#define ADC_ICHDR3_VAL_POSE 15U +#define ADC_ICHDR3_VAL_MSK BITS(ADC_ICHDR3_VAL_POSS,ADC_ICHDR3_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR4 register ************************/ + +#define ADC_ICHDR4_VAL_POSS 0U +#define ADC_ICHDR4_VAL_POSE 15U +#define ADC_ICHDR4_VAL_MSK BITS(ADC_ICHDR4_VAL_POSS,ADC_ICHDR4_VAL_POSE) + +/****************** Bit definition for ADC_NCHDR register ************************/ + +#define ADC_NCHDR_VAL_POSS 0U +#define ADC_NCHDR_VAL_POSE 15U +#define ADC_NCHDR_VAL_MSK BITS(ADC_NCHDR_VAL_POSS,ADC_NCHDR_VAL_POSE) + +/****************** Bit definition for ADC_CCR register ************************/ + +#define ADC_CCR_TRMEN_POS 28U +#define ADC_CCR_TRMEN_MSK BIT(ADC_CCR_TRMEN_POS) + +#define ADC_CCR_GAINCALEN_POS 25U +#define ADC_CCR_GAINCALEN_MSK BIT(ADC_CCR_GAINCALEN_POS) + +#define ADC_CCR_OFFCALEN_POS 24U +#define ADC_CCR_OFFCALEN_MSK BIT(ADC_CCR_OFFCALEN_POS) + +#define ADC_CCR_VREFOEN_POS 19U +#define ADC_CCR_VREFOEN_MSK BIT(ADC_CCR_VREFOEN_POS) + +#define ADC_CCR_VRNSEL_POS 18U +#define ADC_CCR_VRNSEL_MSK BIT(ADC_CCR_VRNSEL_POS) + +#define ADC_CCR_VRPSEL_POSS 16U +#define ADC_CCR_VRPSEL_POSE 17U +#define ADC_CCR_VRPSEL_MSK BITS(ADC_CCR_VRPSEL_POSS,ADC_CCR_VRPSEL_POSE) + +#define ADC_CCR_PWRMODSEL_POS 15U +#define ADC_CCR_PWRMODSEL_MSK BIT(ADC_CCR_PWRMODSEL_POS) + +#define ADC_CCR_DIFFEN_POS 12U +#define ADC_CCR_DIFFEN_MSK BIT(ADC_CCR_DIFFEN_POS) + +#define ADC_CCR_IREFEN_POS 11U +#define ADC_CCR_IREFEN_MSK BIT(ADC_CCR_IREFEN_POS) + +#define ADC_CCR_VRBUFEN_POS 10U +#define ADC_CCR_VRBUFEN_MSK BIT(ADC_CCR_VRBUFEN_POS) + +#define ADC_CCR_VCMBUFEN_POS 9U +#define ADC_CCR_VCMBUFEN_MSK BIT(ADC_CCR_VCMBUFEN_POS) + +#define ADC_CCR_VREFEN_POS 8U +#define ADC_CCR_VREFEN_MSK BIT(ADC_CCR_VREFEN_POS) + +#define ADC_CCR_CKDIV_POSS 0U +#define ADC_CCR_CKDIV_POSE 2U +#define ADC_CCR_CKDIV_MSK BITS(ADC_CCR_CKDIV_POSS,ADC_CCR_CKDIV_POSE) + +typedef struct +{ + __I uint32_t STAT; + __O uint32_t CLR; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t SMPT1; + __IO uint32_t SMPT2; + __IO uint32_t ICHOFF[4]; + __IO uint32_t WDTH; + __IO uint32_t WDTL; + __IO uint32_t NCHS1; + __IO uint32_t NCHS2; + __IO uint32_t NCHS3; + __IO uint32_t NCHS4; + __IO uint32_t ICHS; + __IO uint32_t CHSL; + __I uint32_t ICHDR[4]; + __I uint32_t NCHDR; + __IO uint32_t CCR; +} ADC_TypeDef; + +/****************** Bit definition for ACMP_CON register ************************/ + +#define ACMP_CON_FALLEN_POS 17U +#define ACMP_CON_FALLEN_MSK BIT(ACMP_CON_FALLEN_POS) + +#define ACMP_CON_RISEEN_POS 16U +#define ACMP_CON_RISEEN_MSK BIT(ACMP_CON_RISEEN_POS) + +#define ACMP_CON_MODSEL_POSS 14U +#define ACMP_CON_MODSEL_POSE 15U +#define ACMP_CON_MODSEL_MSK BITS(ACMP_CON_MODSEL_POSS,ACMP_CON_MODSEL_POSE) + +#define ACMP_CON_WARMUPT_POSS 8U +#define ACMP_CON_WARMUPT_POSE 10U +#define ACMP_CON_WARMUPT_MSK BITS(ACMP_CON_WARMUPT_POSS,ACMP_CON_WARMUPT_POSE) + +#define ACMP_CON_HYSTSEL_POSS 4U +#define ACMP_CON_HYSTSEL_POSE 6U +#define ACMP_CON_HYSTSEL_MSK BITS(ACMP_CON_HYSTSEL_POSS,ACMP_CON_HYSTSEL_POSE) + +#define ACMP_CON_OUTINV_POS 3U +#define ACMP_CON_OUTINV_MSK BIT(ACMP_CON_OUTINV_POS) + +#define ACMP_CON_INACTV_POS 2U +#define ACMP_CON_INACTV_MSK BIT(ACMP_CON_INACTV_POS) + +#define ACMP_CON_EN_POS 0U +#define ACMP_CON_EN_MSK BIT(ACMP_CON_EN_POS) + +/****************** Bit definition for ACMP_INPUTSEL register ************************/ + +#define ACMP_INPUTSEL_VDDLVL_POSS 8U +#define ACMP_INPUTSEL_VDDLVL_POSE 13U +#define ACMP_INPUTSEL_VDDLVL_MSK BITS(ACMP_INPUTSEL_VDDLVL_POSS,ACMP_INPUTSEL_VDDLVL_POSE) + +#define ACMP_INPUTSEL_NSEL_POSS 4U +#define ACMP_INPUTSEL_NSEL_POSE 7U +#define ACMP_INPUTSEL_NSEL_MSK BITS(ACMP_INPUTSEL_NSEL_POSS,ACMP_INPUTSEL_NSEL_POSE) + +#define ACMP_INPUTSEL_PSEL_POSS 0U +#define ACMP_INPUTSEL_PSEL_POSE 2U +#define ACMP_INPUTSEL_PSEL_MSK BITS(ACMP_INPUTSEL_PSEL_POSS,ACMP_INPUTSEL_PSEL_POSE) + +/****************** Bit definition for ACMP_STAT register ************************/ + +#define ACMP_STAT_OUT_POS 1U +#define ACMP_STAT_OUT_MSK BIT(ACMP_STAT_OUT_POS) + +#define ACMP_STAT_ACT_POS 0U +#define ACMP_STAT_ACT_MSK BIT(ACMP_STAT_ACT_POS) + +/****************** Bit definition for ACMP_IES register ************************/ + +#define ACMP_IES_WARMUP_POS 1U +#define ACMP_IES_WARMUP_MSK BIT(ACMP_IES_WARMUP_POS) + +#define ACMP_IES_EDGE_POS 0U +#define ACMP_IES_EDGE_MSK BIT(ACMP_IES_EDGE_POS) + +/****************** Bit definition for ACMP_IEV register ************************/ + +#define ACMP_IEV_WARMUP_POS 1U +#define ACMP_IEV_WARMUP_MSK BIT(ACMP_IEV_WARMUP_POS) + +#define ACMP_IEV_EDGE_POS 0U +#define ACMP_IEV_EDGE_MSK BIT(ACMP_IEV_EDGE_POS) + +/****************** Bit definition for ACMP_IEC register ************************/ + +#define ACMP_IEC_WARMUP_POS 1U +#define ACMP_IEC_WARMUP_MSK BIT(ACMP_IEC_WARMUP_POS) + +#define ACMP_IEC_EDGE_POS 0U +#define ACMP_IEC_EDGE_MSK BIT(ACMP_IEC_EDGE_POS) + +/****************** Bit definition for ACMP_RIF register ************************/ + +#define ACMP_RIF_WARMUP_POS 1U +#define ACMP_RIF_WARMUP_MSK BIT(ACMP_RIF_WARMUP_POS) + +#define ACMP_RIF_EDGE_POS 0U +#define ACMP_RIF_EDGE_MSK BIT(ACMP_RIF_EDGE_POS) + +/****************** Bit definition for ACMP_IFM register ************************/ + +#define ACMP_IFM_WARMUP_POS 1U +#define ACMP_IFM_WARMUP_MSK BIT(ACMP_IFM_WARMUP_POS) + +#define ACMP_IFM_EDGE_POS 0U +#define ACMP_IFM_EDGE_MSK BIT(ACMP_IFM_EDGE_POS) + +/****************** Bit definition for ACMP_IFC register ************************/ + +#define ACMP_IFC_WARMUP_POS 1U +#define ACMP_IFC_WARMUP_MSK BIT(ACMP_IFC_WARMUP_POS) + +#define ACMP_IFC_EDGE_POS 0U +#define ACMP_IFC_EDGE_MSK BIT(ACMP_IFC_EDGE_POS) + +/****************** Bit definition for ACMP_PORT register ************************/ + +#define ACMP_PORT_PEN_POS 0U +#define ACMP_PORT_PEN_MSK BIT(ACMP_PORT_PEN_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t INPUTSEL; + __I uint32_t STAT; + __O uint32_t IES; + __I uint32_t IEV; + __O uint32_t IEC; + __I uint32_t RIF; + __O uint32_t IFM; + __O uint32_t IFC; + __IO uint32_t PORT; +} ACMP_TypeDef; + +/****************** Bit definition for CALC_SQRTSR register ************************/ + +#define CALC_SQRTSR_BUSY_POS 0U +#define CALC_SQRTSR_BUSY_MSK BIT(CALC_SQRTSR_BUSY_POS) + +/****************** Bit definition for CALC_RDCND register ************************/ + +#define CALC_RDCND_RADICAND_POSS 0U +#define CALC_RDCND_RADICAND_POSE 31U +#define CALC_RDCND_RADICAND_MSK BITS(CALC_RDCND_RADICAND_POSS,CALC_RDCND_RADICAND_POSE) + +/****************** Bit definition for CALC_SQRTRES register ************************/ + +#define CALC_SQRTRES_RESULT_POSS 0U +#define CALC_SQRTRES_RESULT_POSE 15U +#define CALC_SQRTRES_RESULT_MSK BITS(CALC_SQRTRES_RESULT_POSS,CALC_SQRTRES_RESULT_POSE) + +/****************** Bit definition for CALC_DIVDR register ************************/ + +#define CALC_DIVDR_DIVD_POSS 0U +#define CALC_DIVDR_DIVD_POSE 31U +#define CALC_DIVDR_DIVD_MSK BITS(CALC_DIVDR_DIVD_POSS,CALC_DIVDR_DIVD_POSE) + +/****************** Bit definition for CALC_DIVSR register ************************/ + +#define CALC_DIVSR_DIVS_POSS 0U +#define CALC_DIVSR_DIVS_POSE 31U +#define CALC_DIVSR_DIVS_MSK BITS(CALC_DIVSR_DIVS_POSS,CALC_DIVSR_DIVS_POSE) + +/****************** Bit definition for CALC_DIVQR register ************************/ + +#define CALC_DIVQR_DIVQ_POSS 0U +#define CALC_DIVQR_DIVQ_POSE 31U +#define CALC_DIVQR_DIVQ_MSK BITS(CALC_DIVQR_DIVQ_POSS,CALC_DIVQR_DIVQ_POSE) + +/****************** Bit definition for CALC_DIVRR register ************************/ + +#define CALC_DIVRR_DIVS_POSS 0U +#define CALC_DIVRR_DIVS_POSE 31U +#define CALC_DIVRR_DIVS_MSK BITS(CALC_DIVRR_DIVS_POSS,CALC_DIVRR_DIVS_POSE) + +/****************** Bit definition for CALC_DIVCSR register ************************/ + +#define CALC_DIVCSR_TRM_POS 9U +#define CALC_DIVCSR_TRM_MSK BIT(CALC_DIVCSR_TRM_POS) + +#define CALC_DIVCSR_SIGN_POS 8U +#define CALC_DIVCSR_SIGN_MSK BIT(CALC_DIVCSR_SIGN_POS) + +#define CALC_DIVCSR_DZ_POS 1U +#define CALC_DIVCSR_DZ_MSK BIT(CALC_DIVCSR_DZ_POS) + +#define CALC_DIVCSR_BUSY_POS 0U +#define CALC_DIVCSR_BUSY_MSK BIT(CALC_DIVCSR_BUSY_POS) + +typedef struct +{ + __I uint32_t SQRTSR; + __IO uint32_t RDCND; + __I uint32_t SQRTRES; + uint32_t RESERVED0[5] ; + __IO uint32_t DIVDR; + __IO uint32_t DIVSR; + __I uint32_t DIVQR; + __I uint32_t DIVRR; + __IO uint32_t DIVCSR; +} CALC_TypeDef; + +/****************** Bit definition for TRNG_CR register ************************/ + +#define TRNG_CR_ADJC_POSS 16U +#define TRNG_CR_ADJC_POSE 17U +#define TRNG_CR_ADJC_MSK BITS(TRNG_CR_ADJC_POSS,TRNG_CR_ADJC_POSE) + +#define TRNG_CR_SDSEL_POSS 10U +#define TRNG_CR_SDSEL_POSE 11U +#define TRNG_CR_SDSEL_MSK BITS(TRNG_CR_SDSEL_POSS,TRNG_CR_SDSEL_POSE) + +#define TRNG_CR_DSEL_POSS 8U +#define TRNG_CR_DSEL_POSE 9U +#define TRNG_CR_DSEL_MSK BITS(TRNG_CR_DSEL_POSS,TRNG_CR_DSEL_POSE) + +#define TRNG_CR_POSTEN_POS 3U +#define TRNG_CR_POSTEN_MSK BIT(TRNG_CR_POSTEN_POS) + +#define TRNG_CR_TRNGSEL_POS 2U +#define TRNG_CR_TRNGSEL_MSK BIT(TRNG_CR_TRNGSEL_POS) + +#define TRNG_CR_ADJM_POS 1U +#define TRNG_CR_ADJM_MSK BIT(TRNG_CR_ADJM_POS) + +#define TRNG_CR_TRNGEN_POS 0U +#define TRNG_CR_TRNGEN_MSK BIT(TRNG_CR_TRNGEN_POS) + +/****************** Bit definition for TRNG_SR register ************************/ + +#define TRNG_SR_OVER_POS 3U +#define TRNG_SR_OVER_MSK BIT(TRNG_SR_OVER_POS) + +#define TRNG_SR_SERR_POS 2U +#define TRNG_SR_SERR_MSK BIT(TRNG_SR_SERR_POS) + +#define TRNG_SR_DAVLD_POS 1U +#define TRNG_SR_DAVLD_MSK BIT(TRNG_SR_DAVLD_POS) + +#define TRNG_SR_START_POS 0U +#define TRNG_SR_START_MSK BIT(TRNG_SR_START_POS) + +/****************** Bit definition for TRNG_DR register ************************/ + +#define TRNG_DR_DATA_POSS 0U +#define TRNG_DR_DATA_POSE 31U +#define TRNG_DR_DATA_MSK BITS(TRNG_DR_DATA_POSS,TRNG_DR_DATA_POSE) + +/****************** Bit definition for TRNG_SEED register ************************/ + +#define TRNG_SEED_SEED_POSS 0U +#define TRNG_SEED_SEED_POSE 31U +#define TRNG_SEED_SEED_MSK BITS(TRNG_SEED_SEED_POSS,TRNG_SEED_SEED_POSE) + +/****************** Bit definition for TRNG_CFGR register ************************/ + +#define TRNG_CFGR_TOPLMT_POSS 16U +#define TRNG_CFGR_TOPLMT_POSE 24U +#define TRNG_CFGR_TOPLMT_MSK BITS(TRNG_CFGR_TOPLMT_POSS,TRNG_CFGR_TOPLMT_POSE) + +#define TRNG_CFGR_CKDIV_POSS 8U +#define TRNG_CFGR_CKDIV_POSE 11U +#define TRNG_CFGR_CKDIV_MSK BITS(TRNG_CFGR_CKDIV_POSS,TRNG_CFGR_CKDIV_POSE) + +#define TRNG_CFGR_TSTART_POSS 0U +#define TRNG_CFGR_TSTART_POSE 2U +#define TRNG_CFGR_TSTART_MSK BITS(TRNG_CFGR_TSTART_POSS,TRNG_CFGR_TSTART_POSE) + +/****************** Bit definition for TRNG_IER register ************************/ + +#define TRNG_IER_SERR_POS 2U +#define TRNG_IER_SERR_MSK BIT(TRNG_IER_SERR_POS) + +#define TRNG_IER_DAVLD_POS 1U +#define TRNG_IER_DAVLD_MSK BIT(TRNG_IER_DAVLD_POS) + +#define TRNG_IER_START_POS 0U +#define TRNG_IER_START_MSK BIT(TRNG_IER_START_POS) + +/****************** Bit definition for TRNG_IFR register ************************/ + +#define TRNG_IFR_SERR_POS 2U +#define TRNG_IFR_SERR_MSK BIT(TRNG_IFR_SERR_POS) + +#define TRNG_IFR_DAVLD_POS 1U +#define TRNG_IFR_DAVLD_MSK BIT(TRNG_IFR_DAVLD_POS) + +#define TRNG_IFR_START_POS 0U +#define TRNG_IFR_START_MSK BIT(TRNG_IFR_START_POS) + +/****************** Bit definition for TRNG_IFCR register ************************/ + +#define TRNG_IFCR_SERRC_POS 2U +#define TRNG_IFCR_SERRC_MSK BIT(TRNG_IFCR_SERRC_POS) + +#define TRNG_IFCR_DAVLDC_POS 1U +#define TRNG_IFCR_DAVLDC_MSK BIT(TRNG_IFCR_DAVLDC_POS) + +#define TRNG_IFCR_STARTC_POS 0U +#define TRNG_IFCR_STARTC_MSK BIT(TRNG_IFCR_STARTC_POS) + +/****************** Bit definition for TRNG_ISR register ************************/ + +#define TRNG_ISR_SERR_POS 2U +#define TRNG_ISR_SERR_MSK BIT(TRNG_ISR_SERR_POS) + +#define TRNG_ISR_DAVLD_POS 1U +#define TRNG_ISR_DAVLD_MSK BIT(TRNG_ISR_DAVLD_POS) + +#define TRNG_ISR_START_POS 0U +#define TRNG_ISR_START_MSK BIT(TRNG_ISR_START_POS) + +typedef struct +{ + __IO uint32_t CR; + __I uint32_t SR; + __I uint32_t DR; + __IO uint32_t SEED; + __IO uint32_t CFGR; + __IO uint32_t IER; + __I uint32_t IFR; + __O uint32_t IFCR; + __I uint32_t ISR; +} TRNG_TypeDef; + +/****************** Bit definition for TSENSE_WPR register ************************/ + +#define TSENSE_WPR_WP_POS 0U +#define TSENSE_WPR_WP_MSK BIT(TSENSE_WPR_WP_POS) + +/****************** Bit definition for TSENSE_CR register ************************/ + +#define TSENSE_CR_TSU_POSS 12U +#define TSENSE_CR_TSU_POSE 14U +#define TSENSE_CR_TSU_MSK BITS(TSENSE_CR_TSU_POSS,TSENSE_CR_TSU_POSE) + +#define TSENSE_CR_TOM_POSS 8U +#define TSENSE_CR_TOM_POSE 10U +#define TSENSE_CR_TOM_MSK BITS(TSENSE_CR_TOM_POSS,TSENSE_CR_TOM_POSE) + +#define TSENSE_CR_CTN_POS 4U +#define TSENSE_CR_CTN_MSK BIT(TSENSE_CR_CTN_POS) + +#define TSENSE_CR_RST_POS 3U +#define TSENSE_CR_RST_MSK BIT(TSENSE_CR_RST_POS) + +#define TSENSE_CR_ENS_POS 2U +#define TSENSE_CR_ENS_MSK BIT(TSENSE_CR_ENS_POS) + +#define TSENSE_CR_REQEN_POS 1U +#define TSENSE_CR_REQEN_MSK BIT(TSENSE_CR_REQEN_POS) + +#define TSENSE_CR_EN_POS 0U +#define TSENSE_CR_EN_MSK BIT(TSENSE_CR_EN_POS) + +/****************** Bit definition for TSENSE_DR register ************************/ + +#define TSENSE_DR_ERR_POS 31U +#define TSENSE_DR_ERR_MSK BIT(TSENSE_DR_ERR_POS) + +#define TSENSE_DR_DATA_POSS 0U +#define TSENSE_DR_DATA_POSE 15U +#define TSENSE_DR_DATA_MSK BITS(TSENSE_DR_DATA_POSS,TSENSE_DR_DATA_POSE) + +/****************** Bit definition for TSENSE_PSR register ************************/ + +#define TSENSE_PSR_PRS_POSS 0U +#define TSENSE_PSR_PRS_POSE 7U +#define TSENSE_PSR_PRS_MSK BITS(TSENSE_PSR_PRS_POSS,TSENSE_PSR_PRS_POSE) + +/****************** Bit definition for TSENSE_IE register ************************/ + +#define TSENSE_IE_TSENSE_POS 0U +#define TSENSE_IE_TSENSE_MSK BIT(TSENSE_IE_TSENSE_POS) + +/****************** Bit definition for TSENSE_IF register ************************/ + +#define TSENSE_IF_TSENSE_POS 0U +#define TSENSE_IF_TSENSE_MSK BIT(TSENSE_IF_TSENSE_POS) + +/****************** Bit definition for TSENSE_IFCR register ************************/ + +#define TSENSE_IFCR_TSENSE_POS 0U +#define TSENSE_IFCR_TSENSE_MSK BIT(TSENSE_IFCR_TSENSE_POS) + +/****************** Bit definition for TSENSE_LTGR register ************************/ + +#define TSENSE_LTGR_LTG_POSS 0U +#define TSENSE_LTGR_LTG_POSE 20U +#define TSENSE_LTGR_LTG_MSK BITS(TSENSE_LTGR_LTG_POSS,TSENSE_LTGR_LTG_POSE) + +/****************** Bit definition for TSENSE_HTGR register ************************/ + +#define TSENSE_HTGR_HTG_POSS 0U +#define TSENSE_HTGR_HTG_POSE 20U +#define TSENSE_HTGR_HTG_MSK BITS(TSENSE_HTGR_HTG_POSS,TSENSE_HTGR_HTG_POSE) + +/****************** Bit definition for TSENSE_TBDR register ************************/ + +#define TSENSE_TBDR_TBD_POSS 0U +#define TSENSE_TBDR_TBD_POSE 15U +#define TSENSE_TBDR_TBD_MSK BITS(TSENSE_TBDR_TBD_POSS,TSENSE_TBDR_TBD_POSE) + +/****************** Bit definition for TSENSE_TCALBDR register ************************/ + +#define TSENSE_TCALBDR_TCAL_POSS 0U +#define TSENSE_TCALBDR_TCAL_POSE 16U +#define TSENSE_TCALBDR_TCAL_MSK BITS(TSENSE_TCALBDR_TCAL_POSS,TSENSE_TCALBDR_TCAL_POSE) + +/****************** Bit definition for TSENSE_SR register ************************/ + +#define TSENSE_SR_TSOUT_POS 31U +#define TSENSE_SR_TSOUT_MSK BIT(TSENSE_SR_TSOUT_POS) + +#define TSENSE_SR_NVLD_POS 25U +#define TSENSE_SR_NVLD_MSK BIT(TSENSE_SR_NVLD_POS) + +#define TSENSE_SR_TCAL_POSS 0U +#define TSENSE_SR_TCAL_POSE 24U +#define TSENSE_SR_TCAL_MSK BITS(TSENSE_SR_TCAL_POSS,TSENSE_SR_TCAL_POSE) + +typedef struct +{ + __IO uint32_t WPR; + __IO uint32_t CR; + __I uint32_t DR; + __IO uint32_t PSR; + __IO uint32_t IE; + __I uint32_t IF; + __IO uint32_t IFCR; + __IO uint32_t LTGR; + __IO uint32_t HTGR; + __IO uint32_t TBDR; + __IO uint32_t TCALBDR; + __I uint32_t SR; +} TSENSE_TypeDef; + +/****************** Bit definition for IWDT_LOAD register ************************/ + +#define IWDT_LOAD_LOAD_POSS 0U +#define IWDT_LOAD_LOAD_POSE 31U +#define IWDT_LOAD_LOAD_MSK BITS(IWDT_LOAD_LOAD_POSS,IWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for IWDT_VALUE register ************************/ + +#define IWDT_VALUE_VALUE_POSS 0U +#define IWDT_VALUE_VALUE_POSE 31U +#define IWDT_VALUE_VALUE_MSK BITS(IWDT_VALUE_VALUE_POSS,IWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for IWDT_CON register ************************/ + +#define IWDT_CON_CLKS_POS 3U +#define IWDT_CON_CLKS_MSK BIT(IWDT_CON_CLKS_POS) + +#define IWDT_CON_RSTEN_POS 2U +#define IWDT_CON_RSTEN_MSK BIT(IWDT_CON_RSTEN_POS) + +#define IWDT_CON_IE_POS 1U +#define IWDT_CON_IE_MSK BIT(IWDT_CON_IE_POS) + +#define IWDT_CON_EN_POS 0U +#define IWDT_CON_EN_MSK BIT(IWDT_CON_EN_POS) + +/****************** Bit definition for IWDT_INTCLR register ************************/ + +#define IWDT_INTCLR_INTCLR_POSS 0U +#define IWDT_INTCLR_INTCLR_POSE 31U +#define IWDT_INTCLR_INTCLR_MSK BITS(IWDT_INTCLR_INTCLR_POSS,IWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for IWDT_RIS register ************************/ + +#define IWDT_RIS_WDTIF_POS 0U +#define IWDT_RIS_WDTIF_MSK BIT(IWDT_RIS_WDTIF_POS) + +/****************** Bit definition for IWDT_LOCK register ************************/ + +#define IWDT_LOCK_LOCK_POS 0U +#define IWDT_LOCK_LOCK_MSK BIT(IWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59] ; + __IO uint32_t LOCK; +} IWDT_TypeDef; + +/****************** Bit definition for WWDT_LOAD register ************************/ + +#define WWDT_LOAD_LOAD_POSS 0U +#define WWDT_LOAD_LOAD_POSE 31U +#define WWDT_LOAD_LOAD_MSK BITS(WWDT_LOAD_LOAD_POSS,WWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for WWDT_VALUE register ************************/ + +#define WWDT_VALUE_VALUE_POSS 0U +#define WWDT_VALUE_VALUE_POSE 31U +#define WWDT_VALUE_VALUE_MSK BITS(WWDT_VALUE_VALUE_POSS,WWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for WWDT_CON register ************************/ + +#define WWDT_CON_WWDTWIN_POSS 4U +#define WWDT_CON_WWDTWIN_POSE 5U +#define WWDT_CON_WWDTWIN_MSK BITS(WWDT_CON_WWDTWIN_POSS,WWDT_CON_WWDTWIN_POSE) + +#define WWDT_CON_CLKS_POS 3U +#define WWDT_CON_CLKS_MSK BIT(WWDT_CON_CLKS_POS) + +#define WWDT_CON_RSTEN_POS 2U +#define WWDT_CON_RSTEN_MSK BIT(WWDT_CON_RSTEN_POS) + +#define WWDT_CON_IE_POS 1U +#define WWDT_CON_IE_MSK BIT(WWDT_CON_IE_POS) + +#define WWDT_CON_EN_POS 0U +#define WWDT_CON_EN_MSK BIT(WWDT_CON_EN_POS) + +/****************** Bit definition for WWDT_INTCLR register ************************/ + +#define WWDT_INTCLR_INTCLR_POSS 0U +#define WWDT_INTCLR_INTCLR_POSE 31U +#define WWDT_INTCLR_INTCLR_MSK BITS(WWDT_INTCLR_INTCLR_POSS,WWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for WWDT_RIS register ************************/ + +#define WWDT_RIS_WWDTIF_POS 0U +#define WWDT_RIS_WWDTIF_MSK BIT(WWDT_RIS_WWDTIF_POS) + +/****************** Bit definition for WWDT_LOCK register ************************/ + +#define WWDT_LOCK_LOCK_POS 0U +#define WWDT_LOCK_LOCK_MSK BIT(WWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59]; + __IO uint32_t LOCK; +} WWDT_TypeDef; + +/****************** Bit definition for LP16T_CON0 register ************************/ + +#define LP16T_CON0_PRELOAD_POS 22U +#define LP16T_CON0_PRELOAD_MSK BIT(LP16T_CON0_PRELOAD_POS) + +#define LP16T_CON0_WAVEPOL_POS 21U +#define LP16T_CON0_WAVEPOL_MSK BIT(LP16T_CON0_WAVEPOL_POS) + +#define LP16T_CON0_WAVE_POSS 19U +#define LP16T_CON0_WAVE_POSE 20U +#define LP16T_CON0_WAVE_MSK BITS(LP16T_CON0_WAVE_POSS,LP16T_CON0_WAVE_POSE) + +#define LP16T_CON0_TRIGEN_POSS 17U +#define LP16T_CON0_TRIGEN_POSE 18U +#define LP16T_CON0_TRIGEN_MSK BITS(LP16T_CON0_TRIGEN_POSS,LP16T_CON0_TRIGEN_POSE) + +#define LP16T_CON0_TRIGSEL_POSS 13U +#define LP16T_CON0_TRIGSEL_POSE 15U +#define LP16T_CON0_TRIGSEL_MSK BITS(LP16T_CON0_TRIGSEL_POSS,LP16T_CON0_TRIGSEL_POSE) + +#define LP16T_CON0_PRESC_POSS 9U +#define LP16T_CON0_PRESC_POSE 11U +#define LP16T_CON0_PRESC_MSK BITS(LP16T_CON0_PRESC_POSS,LP16T_CON0_PRESC_POSE) + +#define LP16T_CON0_TRGFLT_POSS 6U +#define LP16T_CON0_TRGFLT_POSE 7U +#define LP16T_CON0_TRGFLT_MSK BITS(LP16T_CON0_TRGFLT_POSS,LP16T_CON0_TRGFLT_POSE) + +#define LP16T_CON0_CKFLT_POSS 3U +#define LP16T_CON0_CKFLT_POSE 4U +#define LP16T_CON0_CKFLT_MSK BITS(LP16T_CON0_CKFLT_POSS,LP16T_CON0_CKFLT_POSE) + +#define LP16T_CON0_CKPOL_POS 1U +#define LP16T_CON0_CKPOL_MSK BIT(LP16T_CON0_CKPOL_POS) + +#define LP16T_CON0_CKSEL_POS 0U +#define LP16T_CON0_CKSEL_MSK BIT(LP16T_CON0_CKSEL_POS) + +/****************** Bit definition for LP16T_CON1 register ************************/ + +#define LP16T_CON1_CNTSTRT_POS 2U +#define LP16T_CON1_CNTSTRT_MSK BIT(LP16T_CON1_CNTSTRT_POS) + +#define LP16T_CON1_SNGSTRT_POS 1U +#define LP16T_CON1_SNGSTRT_MSK BIT(LP16T_CON1_SNGSTRT_POS) + +#define LP16T_CON1_ENABLE_POS 0U +#define LP16T_CON1_ENABLE_MSK BIT(LP16T_CON1_ENABLE_POS) + +/****************** Bit definition for LP16T_ARR register ************************/ + +#define LP16T_ARR_ARR_POSS 0U +#define LP16T_ARR_ARR_POSE 15U +#define LP16T_ARR_ARR_MSK BITS(LP16T_ARR_ARR_POSS,LP16T_ARR_ARR_POSE) + +/****************** Bit definition for LP16T_CNT register ************************/ + +#define LP16T_CNT_CNT_POSS 0U +#define LP16T_CNT_CNT_POSE 15U +#define LP16T_CNT_CNT_MSK BITS(LP16T_CNT_CNT_POSS,LP16T_CNT_CNT_POSE) + +/****************** Bit definition for LP16T_CMP register ************************/ + +#define LP16T_CMP_CMP_POSS 0U +#define LP16T_CMP_CMP_POSE 15U +#define LP16T_CMP_CMP_MSK BITS(LP16T_CMP_CMP_POSS,LP16T_CMP_CMP_POSE) + +/****************** Bit definition for LP16T_IER register ************************/ + +#define LP16T_IER_EXTTRIGIE_POS 2U +#define LP16T_IER_EXTTRIGIE_MSK BIT(LP16T_IER_EXTTRIGIE_POS) + +#define LP16T_IER_ARRMIE_POS 1U +#define LP16T_IER_ARRMIE_MSK BIT(LP16T_IER_ARRMIE_POS) + +#define LP16T_IER_CMPMIE_POS 0U +#define LP16T_IER_CMPMIE_MSK BIT(LP16T_IER_CMPMIE_POS) + +/****************** Bit definition for LP16T_ISR register ************************/ + +#define LP16T_ISR_EXTTRIG_POS 2U +#define LP16T_ISR_EXTTRIG_MSK BIT(LP16T_ISR_EXTTRIG_POS) + +#define LP16T_ISR_ARRM_POS 1U +#define LP16T_ISR_ARRM_MSK BIT(LP16T_ISR_ARRM_POS) + +#define LP16T_ISR_CMPM_POS 0U +#define LP16T_ISR_CMPM_MSK BIT(LP16T_ISR_CMPM_POS) + +/****************** Bit definition for LP16T_IFC register ************************/ + +#define LP16T_IFC_EXTTRIG_POS 2U +#define LP16T_IFC_EXTTRIG_MSK BIT(LP16T_IFC_EXTTRIG_POS) + +#define LP16T_IFC_ARRM_POS 1U +#define LP16T_IFC_ARRM_MSK BIT(LP16T_IFC_ARRM_POS) + +#define LP16T_IFC_CMPM_POS 0U +#define LP16T_IFC_CMPM_MSK BIT(LP16T_IFC_CMPM_POS) + +/****************** Bit definition for LP16T_UPDATE register ************************/ + +#define LP16T_UPDATE_UDIS_POS 0U +#define LP16T_UPDATE_UDIS_MSK BIT(LP16T_UPDATE_UDIS_POS) + +/****************** Bit definition for LP16T_SYNCSTAT register ************************/ + +#define LP16T_SYNCSTAT_CMPWBSY_POS 3U +#define LP16T_SYNCSTAT_CMPWBSY_MSK BIT(LP16T_SYNCSTAT_CMPWBSY_POS) + +#define LP16T_SYNCSTAT_ARRWBSY_POS 2U +#define LP16T_SYNCSTAT_ARRWBSY_MSK BIT(LP16T_SYNCSTAT_ARRWBSY_POS) + +#define LP16T_SYNCSTAT_CON1WBSY_POS 1U +#define LP16T_SYNCSTAT_CON1WBSY_MSK BIT(LP16T_SYNCSTAT_CON1WBSY_POS) + +typedef struct +{ + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t ARR; + __I uint32_t CNT; + __IO uint32_t CMP; + uint32_t RESERVED0 ; + __IO uint32_t IER; + __I uint32_t ISR; + __O uint32_t IFC; + uint32_t RESERVED1[3] ; + __IO uint32_t UPDATE; + __I uint32_t SYNCSTAT; +} LPTIM_TypeDef; + +/****************** Bit definition for DBGC_IDCODE register ************************/ + +#define DBGC_IDCODE_REV_ID_POSS 16U +#define DBGC_IDCODE_REV_ID_POSE 31U +#define DBGC_IDCODE_REV_ID_MSK BITS(DBGC_IDCODE_REV_ID_POSS,DBGC_IDCODE_REV_ID_POSE) + +#define DBGC_IDCODE_CORE_ID_POSS 12U +#define DBGC_IDCODE_CORE_ID_POSE 15U +#define DBGC_IDCODE_CORE_ID_MSK BITS(DBGC_IDCODE_CORE_ID_POSS,DBGC_IDCODE_CORE_ID_POSE) + +#define DBGC_IDCODE_DEV_ID_POSS 0U +#define DBGC_IDCODE_DEV_ID_POSE 11U +#define DBGC_IDCODE_DEV_ID_MSK BITS(DBGC_IDCODE_DEV_ID_POSS,DBGC_IDCODE_DEV_ID_POSE) + +/****************** Bit definition for DBGC_CR register ************************/ + +#define DBGC_CR_DBG_STANDBY_POS 3U +#define DBGC_CR_DBG_STANDBY_MSK BIT(DBGC_CR_DBG_STANDBY_POS) + +#define DBGC_CR_DBG_STOP2_POS 2U +#define DBGC_CR_DBG_STOP2_MSK BIT(DBGC_CR_DBG_STOP2_POS) + +#define DBGC_CR_DBG_STOP1_POS 1U +#define DBGC_CR_DBG_STOP1_MSK BIT(DBGC_CR_DBG_STOP1_POS) + +#define DBGC_CR_DBG_SLEEP_POS 0U +#define DBGC_CR_DBG_SLEEP_MSK BIT(DBGC_CR_DBG_SLEEP_POS) + +/****************** Bit definition for DBGC_APB1FZ register ************************/ + +#define DBGC_APB1FZ_CAN_STOP_POS 12U +#define DBGC_APB1FZ_CAN_STOP_MSK BIT(DBGC_APB1FZ_CAN_STOP_POS) + +#define DBGC_APB1FZ_I2C1_SMBUS_TO_POS 9U +#define DBGC_APB1FZ_I2C1_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C1_SMBUS_TO_POS) + +#define DBGC_APB1FZ_I2C0_SMBUS_TO_POS 8U +#define DBGC_APB1FZ_I2C0_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C0_SMBUS_TO_POS) + +#define DBGC_APB1FZ_TIM7_STOP_POS 7U +#define DBGC_APB1FZ_TIM7_STOP_MSK BIT(DBGC_APB1FZ_TIM7_STOP_POS) + +#define DBGC_APB1FZ_TIM6_STOP_POS 6U +#define DBGC_APB1FZ_TIM6_STOP_MSK BIT(DBGC_APB1FZ_TIM6_STOP_POS) + +#define DBGC_APB1FZ_TIM5_STOP_POS 5U +#define DBGC_APB1FZ_TIM5_STOP_MSK BIT(DBGC_APB1FZ_TIM5_STOP_POS) + +#define DBGC_APB1FZ_TIM4_STOP_POS 4U +#define DBGC_APB1FZ_TIM4_STOP_MSK BIT(DBGC_APB1FZ_TIM4_STOP_POS) + +#define DBGC_APB1FZ_TIM3_STOP_POS 3U +#define DBGC_APB1FZ_TIM3_STOP_MSK BIT(DBGC_APB1FZ_TIM3_STOP_POS) + +#define DBGC_APB1FZ_TIM2_STOP_POS 2U +#define DBGC_APB1FZ_TIM2_STOP_MSK BIT(DBGC_APB1FZ_TIM2_STOP_POS) + +#define DBGC_APB1FZ_TIM1_STOP_POS 1U +#define DBGC_APB1FZ_TIM1_STOP_MSK BIT(DBGC_APB1FZ_TIM1_STOP_POS) + +#define DBGC_APB1FZ_TIM0_STOP_POS 0U +#define DBGC_APB1FZ_TIM0_STOP_MSK BIT(DBGC_APB1FZ_TIM0_STOP_POS) + +/****************** Bit definition for DBGC_APB2FZ register ************************/ + +#define DBGC_APB2FZ_RTC_STOP_POS 10U +#define DBGC_APB2FZ_RTC_STOP_MSK BIT(DBGC_APB2FZ_RTC_STOP_POS) + +#define DBGC_APB2FZ_WWDT_STOP_POS 9U +#define DBGC_APB2FZ_WWDT_STOP_MSK BIT(DBGC_APB2FZ_WWDT_STOP_POS) + +#define DBGC_APB2FZ_IWDT_STOP_POS 8U +#define DBGC_APB2FZ_IWDT_STOP_MSK BIT(DBGC_APB2FZ_IWDT_STOP_POS) + +#define DBGC_APB2FZ_LPTIM0_STOP_POS 0U +#define DBGC_APB2FZ_LPTIM0_STOP_MSK BIT(DBGC_APB2FZ_LPTIM0_STOP_POS) + +typedef struct +{ + __I uint32_t IDCODE; + __IO uint32_t CR; + __IO uint32_t APB1FZ; + __IO uint32_t APB2FZ; +} DBGC_TypeDef; + + +/* Base addresses */ +#define SRAM_BASE (0x20000000UL) +#define APB1_BASE (0x40000000UL) +#define APB2_BASE (0x40040000UL) +#define AHB_BASE (0x40080000UL) + +/* APB1 peripherals Base Address */ +#define AD16C4T0_BASE (APB1_BASE + 0x0000) +#define BS16T0_BASE (APB1_BASE + 0x0400) +#define GP16C2T0_BASE (APB1_BASE + 0x0800) +#define GP16C2T1_BASE (APB1_BASE + 0x0C00) +#define BS16T1_BASE (APB1_BASE + 0x1000) +#define BS16T2_BASE (APB1_BASE + 0x1400) +#define GP16C4T0_BASE (APB1_BASE + 0x1800) +#define BS16T3_BASE (APB1_BASE + 0x1C00) +#define UART0_BASE (APB1_BASE + 0x4000) +#define UART1_BASE (APB1_BASE + 0x4400) +#define UART2_BASE (APB1_BASE + 0x4800) +#define UART3_BASE (APB1_BASE + 0x4C00) +#define USART0_BASE (APB1_BASE + 0x5000) +#define USART1_BASE (APB1_BASE + 0x5400) +#define SPI0_BASE (APB1_BASE + 0x6000) +#define SPI1_BASE (APB1_BASE + 0x6400) +#define SPI2_BASE (APB1_BASE + 0x6800) +#define I2C0_BASE (APB1_BASE + 0x8000) +#define I2C1_BASE (APB1_BASE + 0x8400) +#define CAN0_BASE (APB1_BASE + 0xB000) +#define DMA0_BASE (APB1_BASE + 0xC000) + +/* APB2 peripherals Base Address */ +#define LPTIM0_BASE (APB2_BASE + 0x0000) +#define LPUART0_BASE (APB2_BASE + 0x1000) +#define ADC0_BASE (APB2_BASE + 0x2000) +#define ADC1_BASE (APB2_BASE + 0x2400) +#define ACMP0_BASE (APB2_BASE + 0x3000) +#define ACMP1_BASE (APB2_BASE + 0x3400) +#define OPAMP_BASE (APB2_BASE + 0x4000) +#define DAC0_BASE (APB2_BASE + 0x5000) +#define WWDT_BASE (APB2_BASE + 0x6000) +#define IWDT_BASE (APB2_BASE + 0x6400) +#define LCD_BASE (APB2_BASE + 0x7000) +#define BKPC_BASE (APB2_BASE + 0x8000) +#define RTC_BASE (APB2_BASE + 0x8400) +#define TSENSE_BASE (APB2_BASE + 0x8800) +#define DBGC_BASE (APB2_BASE + 0xA000) + +/* AHB peripherals Base Address */ +#define SYSCFG_BASE (AHB_BASE + 0x0000) +#define CMU_BASE (AHB_BASE + 0x0400) +#define RMU_BASE (AHB_BASE + 0x0800) +#define PMU_BASE (AHB_BASE + 0x0C00) +#define MSC_BASE (AHB_BASE + 0x1000) +#define GPIOA_BASE (AHB_BASE + 0x4000) +#define GPIOB_BASE (AHB_BASE + 0x4040) +#define GPIOC_BASE (AHB_BASE + 0x4080) +#define GPIOD_BASE (AHB_BASE + 0x40C0) +#define GPIOE_BASE (AHB_BASE + 0x4100) +#define GPIOF_BASE (AHB_BASE + 0x4140) +#define GPIOG_BASE (AHB_BASE + 0x4180) +#define GPIOH_BASE (AHB_BASE + 0x41C0) +#define EXTI_BASE (AHB_BASE + 0x4300) +#define CRC_BASE (AHB_BASE + 0x5000) +#define CALC_BASE (AHB_BASE + 0x5400) +#define CRYPT_BASE (AHB_BASE + 0x5800) +#define TRNG_BASE (AHB_BASE + 0x5C00) +#define PIS_BASE (AHB_BASE + 0x6000) + +/* APB1 peripherals */ +#define AD16C4T0 ((TIMER_TypeDef *)AD16C4T0_BASE) +#define BS16T0 ((TIMER_TypeDef *)BS16T0_BASE) +#define GP16C2T0 ((TIMER_TypeDef *)GP16C2T0_BASE) +#define GP16C2T1 ((TIMER_TypeDef *)GP16C2T1_BASE) +#define BS16T1 ((TIMER_TypeDef *)BS16T1_BASE) +#define BS16T2 ((TIMER_TypeDef *)BS16T2_BASE) +#define GP16C4T0 ((TIMER_TypeDef *)GP16C4T0_BASE) +#define BS16T3 ((TIMER_TypeDef *)BS16T3_BASE) +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define UART3 ((UART_TypeDef *)UART3_BASE) +#define USART0 ((USART_TypeDef *)USART0_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define SPI0 ((SPI_TypeDef *)SPI0_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define CAN0 ((CAN_TypeDef *)CAN0_BASE) +#define DMA0 ((DMA_TypeDef *)DMA0_BASE) + +/* APB2 peripherals */ +#define LPTIM0 ((LPTIM_TypeDef *)LPTIM0_BASE) +#define LPUART0 ((LPUART_TypeDef *)LPUART0_BASE) +#define ADC0 ((ADC_TypeDef *)ADC0_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) +#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) +#define OPAMP ((OPAMP_TypeDef *)OPAMP_BASE) +#define DAC0 ((DAC_TypeDef *)DAC0_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) +#define IWDT ((IWDT_TypeDef *)IWDT_BASE) +#define LCD ((LCD_TypeDef *)LCD_BASE) +#define BKPC ((BKPC_TypeDef *)BKPC_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define TSENSE ((TSENSE_TypeDef *)TSENSE_BASE) +#define DBGC ((DBGC_TypeDef *)DBGC_BASE) + +/* AHB peripherals */ +#define SYSCFG ((SYSCFG_TypeDef *)SYSCFG_BASE) +#define CMU ((CMU_TypeDef *)CMU_BASE) +#define RMU ((RMU_TypeDef *)RMU_BASE) +#define PMU ((PMU_TypeDef *)PMU_BASE) +#define MSC ((MSC_TypeDef *)MSC_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *)GPIOH_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CALC ((CALC_TypeDef *)CALC_BASE) +#define CRYPT ((CRYPT_TypeDef *)CRYPT_BASE) +#define TRNG ((TRNG_TypeDef *)TRNG_BASE) +#define PIS ((PIS_TypeDef *)PIS_BASE) + +#endif diff --git a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s rename to bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s diff --git a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s similarity index 56% rename from bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s rename to bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s index 6bf19bc8779764e99877f947c560be2ee61f30a4..dab56328c5b41e64ab73513d230f4e09591e25a5 100644 --- a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s +++ b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s @@ -45,7 +45,7 @@ __Vectors DCD __initial_sp ;0, load top of stack DCD SysTick_Handler ;15, systick handler DCD WWDG_IWDG_Handler ;16, irq0 WWDG_IWDG handler DCD LVD_Handler ;17, irq1 LVD handler - DCD RTC_TEMP_Handler ;18, irq2 RTC handler + DCD RTC_TSENSE_Handler ;18, irq2 RTC handler DCD CRYPT_TRNG_Handler ;19, irq3 CRYPT handler DCD CMU_Handler ;20, irq4 CMU handler DCD EXTI0_3_Handler ;21, irq5 EXTI0_3 handler @@ -58,8 +58,8 @@ __Vectors DCD __initial_sp ;0, load top of stack DCD ADC_ACMP_Handler ;28, irq12 ADC_ACMP handler DCD AD16C4T0_BRK_UP_TRIG_COM_Handler ;29, irq13 AD16C4T0_BRK_UP_TRIG_COM handler DCD AD16C4T0_CC_Handler ;30, irq14 AD16C4T0_CC handler - DCD BS16T0_Handler ;31, irq15 BS16T0 handler - DCD 0 ;32, irq16 Reserved + DCD BS16T0_Handler ;31, irq15 BS16T0 handler + DCD 0 ;32, irq16 Reserved DCD GP16C2T0_Handler ;33, irq17 GP16C2T0 handler DCD GP16C2T1_Handler ;34, irq18 GP16C2T1 handler DCD BS16T1_UART2_Handler ;35, irq19 BS16T1_UART2 handler @@ -81,255 +81,255 @@ __Vectors DCD __initial_sp ;0, load top of stack ;Reset Handler---------------------------------------------- Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - LDR R0, =__main - BX R0 - NOP - ALIGN - ENDP + EXPORT Reset_Handler [WEAK] + IMPORT __main + LDR R0, =__main + BX R0 + NOP + ALIGN + ENDP ;system int------------------------------------------------- NMI_Handler PROC ;int 2 - EXPORT NMI_Handler [WEAK] - B . - ENDP + EXPORT NMI_Handler [WEAK] + B . + ENDP HardFault_Handler \ - PROC ;int3 - EXPORT HardFault_Handler [WEAK] - B . - ENDP + PROC ;int3 + EXPORT HardFault_Handler [WEAK] + B . + ENDP SVC_Handler \ - PROC ;int11 - EXPORT SVC_Handler [WEAK] - B . - ENDP + PROC ;int11 + EXPORT SVC_Handler [WEAK] + B . + ENDP DebugMon_Handler \ - PROC ;int12 - EXPORT DebugMon_Handler [WEAK] - B . - ENDP + PROC ;int12 + EXPORT DebugMon_Handler [WEAK] + B . + ENDP PendSV_Handler PROC ;int14 - EXPORT PendSV_Handler [WEAK] - B . - ENDP + EXPORT PendSV_Handler [WEAK] + B . + ENDP SysTick_Handler \ - PROC ;int15 - EXPORT SysTick_Handler [WEAK] - B . - ENDP + PROC ;int15 + EXPORT SysTick_Handler [WEAK] + B . + ENDP ;peripheral module int ----------------------------------------------- WWDG_IWDG_Handler \ - PROC ;int16 - EXPORT WWDG_IWDG_Handler [WEAK] - B . - ENDP + PROC ;int16 + EXPORT WWDG_IWDG_Handler [WEAK] + B . + ENDP LVD_Handler \ - PROC ;int17 - EXPORT LVD_Handler [WEAK] - B . - ENDP + PROC ;int17 + EXPORT LVD_Handler [WEAK] + B . + ENDP -RTC_TEMP_Handler \ - PROC ;int18 - EXPORT RTC_TEMP_Handler [WEAK] - B . - ENDP +RTC_TSENSE_Handler \ + PROC ;int18 + EXPORT RTC_TSENSE_Handler [WEAK] + B . + ENDP CRYPT_TRNG_Handler \ - PROC ;int19 - EXPORT CRYPT_TRNG_Handler [WEAK] - B . - ENDP + PROC ;int19 + EXPORT CRYPT_TRNG_Handler [WEAK] + B . + ENDP CMU_Handler \ - PROC ;int20 - EXPORT CMU_Handler [WEAK] - B . - ENDP + PROC ;int20 + EXPORT CMU_Handler [WEAK] + B . + ENDP EXTI0_3_Handler \ - PROC ;int21 - EXPORT EXTI0_3_Handler [WEAK] - B . - ENDP + PROC ;int21 + EXPORT EXTI0_3_Handler [WEAK] + B . + ENDP EXTI4_7_Handler \ - PROC ;int22 - EXPORT EXTI4_7_Handler [WEAK] - B . - ENDP + PROC ;int22 + EXPORT EXTI4_7_Handler [WEAK] + B . + ENDP EXTI8_11_Handler \ - PROC ;int23 - EXPORT EXTI8_11_Handler [WEAK] - B . - ENDP + PROC ;int23 + EXPORT EXTI8_11_Handler [WEAK] + B . + ENDP EXTI12_15_Handler \ - PROC ;int24 - EXPORT EXTI12_15_Handler [WEAK] - B . - ENDP + PROC ;int24 + EXPORT EXTI12_15_Handler [WEAK] + B . + ENDP DMA_Handler \ - PROC ;int25 - EXPORT DMA_Handler [WEAK] - B . - ENDP + PROC ;int25 + EXPORT DMA_Handler [WEAK] + B . + ENDP CAN0_Handler \ - PROC ;int26 - EXPORT CAN0_Handler [WEAK] - B . - ENDP + PROC ;int26 + EXPORT CAN0_Handler [WEAK] + B . + ENDP LPTIM0_SPI2_Handler \ - PROC ;int27 - EXPORT LPTIM0_SPI2_Handler [WEAK] - B . - ENDP + PROC ;int27 + EXPORT LPTIM0_SPI2_Handler [WEAK] + B . + ENDP ADC_ACMP_Handler \ - PROC ;int28 - EXPORT ADC_ACMP_Handler [WEAK] - B . - ENDP + PROC ;int28 + EXPORT ADC_ACMP_Handler [WEAK] + B . + ENDP AD16C4T0_BRK_UP_TRIG_COM_Handler \ - PROC ;int29 - EXPORT AD16C4T0_BRK_UP_TRIG_COM_Handler [WEAK] - B . - ENDP + PROC ;int29 + EXPORT AD16C4T0_BRK_UP_TRIG_COM_Handler [WEAK] + B . + ENDP AD16C4T0_CC_Handler \ - PROC ;int30 - EXPORT AD16C4T0_CC_Handler [WEAK] - B . - ENDP + PROC ;int30 + EXPORT AD16C4T0_CC_Handler [WEAK] + B . + ENDP BS16T0_Handler \ - PROC ;int31 - EXPORT BS16T0_Handler [WEAK] - B . - ENDP + PROC ;int31 + EXPORT BS16T0_Handler [WEAK] + B . + ENDP GP16C2T0_Handler PROC ;int33 - EXPORT GP16C2T0_Handler [WEAK] - B . - ENDP + EXPORT GP16C2T0_Handler [WEAK] + B . + ENDP GP16C2T1_Handler PROC ;int34 - EXPORT GP16C2T1_Handler [WEAK] - B . - ENDP + EXPORT GP16C2T1_Handler [WEAK] + B . + ENDP BS16T1_UART2_Handler \ - PROC ;int35 - EXPORT BS16T1_UART2_Handler [WEAK] - B . - ENDP + PROC ;int35 + EXPORT BS16T1_UART2_Handler [WEAK] + B . + ENDP BS16T2_UART3_Handler \ - PROC ;int36 - EXPORT BS16T2_UART3_Handler [WEAK] - B . - ENDP + PROC ;int36 + EXPORT BS16T2_UART3_Handler [WEAK] + B . + ENDP GP16C4T0_LCD_Handler \ - PROC ;int37 - EXPORT GP16C4T0_LCD_Handler [WEAK] - B . - ENDP + PROC ;int37 + EXPORT GP16C4T0_LCD_Handler [WEAK] + B . + ENDP BS16T3_DAC0_Handler \ - PROC ;int38 - EXPORT BS16T3_DAC0_Handler [WEAK] - B . - ENDP + PROC ;int38 + EXPORT BS16T3_DAC0_Handler [WEAK] + B . + ENDP I2C0_Handler \ - PROC ;int39 - EXPORT I2C0_Handler [WEAK] - B . - ENDP + PROC ;int39 + EXPORT I2C0_Handler [WEAK] + B . + ENDP I2C1_Handler \ - PROC ;int40 - EXPORT I2C1_Handler [WEAK] - B . - ENDP + PROC ;int40 + EXPORT I2C1_Handler [WEAK] + B . + ENDP SPI0_Handler \ - PROC ;int41 - EXPORT SPI0_Handler [WEAK] - B . - ENDP + PROC ;int41 + EXPORT SPI0_Handler [WEAK] + B . + ENDP SPI1_Handler \ - PROC ;int42 - EXPORT SPI1_Handler [WEAK] - B . - ENDP + PROC ;int42 + EXPORT SPI1_Handler [WEAK] + B . + ENDP UART0_Handler \ - PROC ;int43 - EXPORT UART0_Handler [WEAK] - B . - ENDP + PROC ;int43 + EXPORT UART0_Handler [WEAK] + B . + ENDP UART1_Handler \ - PROC ;int44 - EXPORT UART1_Handler [WEAK] - B . - ENDP + PROC ;int44 + EXPORT UART1_Handler [WEAK] + B . + ENDP USART0_Handler \ - PROC ;int45 - EXPORT USART0_Handler [WEAK] - B . - ENDP + PROC ;int45 + EXPORT USART0_Handler [WEAK] + B . + ENDP USART1_Handler \ - PROC ;int46 - EXPORT USART1_Handler [WEAK] - B . - ENDP + PROC ;int46 + EXPORT USART1_Handler [WEAK] + B . + ENDP LPUART0_Handler \ - PROC ;int47 - EXPORT LPUART0_Handler [WEAK] - B . - ENDP + PROC ;int47 + EXPORT LPUART0_Handler [WEAK] + B . + ENDP ; User Initial Stack & Heap----------------------------------------------------- - ALIGN - IF :DEF:__MICROLIB + ALIGN + IF :DEF:__MICROLIB - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit - ELSE + ELSE - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR - ALIGN + ALIGN - ENDIF + ENDIF - END + END diff --git a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c rename to bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c diff --git a/bsp/es32f0654/libraries/CMSIS/Include/arm_common_tables.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_common_tables.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/arm_common_tables.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_common_tables.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/arm_const_structs.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_const_structs.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/arm_const_structs.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_const_structs.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/arm_math.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_math.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/arm_math.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_math.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm0.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cm0.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cm0.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cm0.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm0plus.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cm0plus.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cm0plus.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cm0plus.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cmFunc.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmFunc.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cmFunc.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmFunc.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cmInstr.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmInstr.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cmInstr.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmInstr.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cmSimd.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmSimd.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cmSimd.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmSimd.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_sc000.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_sc000.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_sc000.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_sc000.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_sc300.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_sc300.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_sc300.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_sc300.h diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h new file mode 100644 index 0000000000000000000000000000000000000000..452deaf516b8b6506cc0d1493de5f50411737b21 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -0,0 +1,355 @@ +/** + ********************************************************************************* + * + * @file ald_acmp.h + * @brief Header file of ACMP module driver. + * + * @version V1.0 + * @date 13 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_ACMP_H__ +#define __ALD_ACMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup ACMP + * @{ + */ + +/** @defgroup ACMP_Public_Types ACMP Public Types + * @{ + */ + +/** + * @brief Acmp interrupt + */ +typedef enum +{ + ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ + ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ +} acmp_it_t; + +/** + * @brief Acmp interrupt + */ +typedef enum +{ + ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +} acmp_flag_t; + +/** + * @brief Acmp interrupt flag + */ +typedef enum +{ + ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +} acmp_status_t; + +/** + * @brief Acmp positive input + */ +typedef enum +{ + ACMP_POS_CH0 = 0, /**< Channel 0 as positive input */ + ACMP_POS_CH1 = 1, /**< Channel 1 as positive input */ + ACMP_POS_CH2 = 2, /**< Channel 2 as positive input */ + ACMP_POS_CH3 = 3, /**< Channel 3 as positive input */ + ACMP_POS_CH4 = 4, /**< Channel 4 as positive input */ + ACMP_POS_CH5 = 5, /**< Channel 5 as positive input */ + ACMP_POS_CH6 = 6, /**< Channel 6 as positive input */ + ACMP_POS_CH7 = 7, /**< Channel 7 as positive input */ +} acmp_pos_input_t; + +/** + * @brief Acmp negative input + */ +typedef enum +{ + ACMP_NEG_CH0 = 0, /**< Channel 0 as negative input */ + ACMP_NEG_CH1 = 1, /**< Channel 1 as negative input */ + ACMP_NEG_CH2 = 2, /**< Channel 2 as negative input */ + ACMP_NEG_CH3 = 3, /**< Channel 3 as negative input */ + ACMP_NEG_CH4 = 4, /**< Channel 4 as negative input */ + ACMP_NEG_CH5 = 5, /**< Channel 5 as negative input */ + ACMP_NEG_CH6 = 6, /**< Channel 6 as negative input */ + ACMP_NEG_CH7 = 7, /**< Channel 7 as negative input */ + ACMP_NEG_1V25 = 8, /**< 1.25v as negative input */ + ACMP_NEG_2V5 = 9, /**< 2.5v as negative input */ + ACMP_NEG_VDD = 10, /**< VDD as negative input */ +} acmp_neg_input_t; + +/** + * @brief Acmp mode + */ +typedef enum +{ + ACMP_ULTRA_LOW_POWER = 0, /**< Ultra low power mode */ + ACMP_LOW_POWER = 1, /**< Low power mode */ + ACMP_MIDDLE_POWER = 2, /**< Middle power mode */ + ACMP_HIGH_POWER = 3, /**< High power mode */ +} acmp_mode_t; + +/** + * @brief Acmp warm-up time + */ +typedef enum +{ + ACMP_4_PCLK = 0, /**< 4 hfperclk cycles */ + ACMP_8_PCLK = 1, /**< 4 hfperclk cycles */ + ACMP_16_PCLK = 2, /**< 4 hfperclk cycles */ + ACMP_32_PCLK = 3, /**< 4 hfperclk cycles */ + ACMP_64_PCLK = 4, /**< 4 hfperclk cycles */ + ACMP_128_PCLK = 5, /**< 4 hfperclk cycles */ + ACMP_256_PCLK = 6, /**< 4 hfperclk cycles */ + ACMP_512_PCLK = 7, /**< 4 hfperclk cycles */ +} acmp_warm_time_t; + +/** + * @brief Acmp hysteresis level + */ +typedef enum +{ + ACMP_HYST_0 = 0, /**< No hysteresis */ + ACMP_HYST_15 = 1, /**< 15mV hysteresis */ + ACMP_HYST_22 = 2, /**< 22mV hysteresis */ + ACMP_HYST_29 = 3, /**< 29mV hysteresis */ + ACMP_HYST_36 = 4, /**< 36mV hysteresis */ + ACMP_HYST_43 = 5, /**< 43mV hysteresis */ + ACMP_HYST_50 = 6, /**< 50mV hysteresis */ + ACMP_HYST_57 = 7, /**< 57mV hysteresis */ +} acmp_hystsel_t; + +/** + * @brief Acmp inactive state + */ +typedef enum +{ + ACMP_INACTVAL_LOW = 0, /**< The inactive value is 0 */ + ACMP_INACTVAL_HIGH = 1, /**< The inactive value is 1 */ +} acmp_inactval_t; + +/** + * @brief which edges set up interrupt + */ +typedef enum +{ + ACMP_EDGE_NONE = 0, /**< Disable EDGE interrupt */ + ACMP_EDGE_FALL = 1, /**< Falling edges set EDGE interrupt */ + ACMP_EDGE_RISE = 2, /**< rise edges set EDGE interrupt */ + ACMP_EDGE_ALL = 3, /**< Falling edges and rise edges set EDGE interrupt */ +} acmp_edge_t; + +/** + * @brief Acmp output function + */ +typedef enum +{ + ACMP_OUT_DISABLE = 0, /**< Disable acmp output */ + ACMP_OUT_ENABLE = 1, /**< Enable acmp output */ +} acmp_out_func_t; + +/** + * @brief Acmp warm-up interrupt function + */ +typedef enum +{ + ACMP_WARM_DISABLE = 0, /**< Disable acmp warm-up interrupt */ + ACMP_WARM_ENABLE = 1, /**< Enable acmp warm-up interrupt */ +} acmp_warm_it_func; + +/** + * @brief Acmp gpio output invert + */ +typedef enum +{ + ACMP_GPIO_NO_INV = 0, /**< Acmp output to gpio is not inverted */ + ACMP_GPIO_INV = 1, /**< Acmp output to gpio is inverted */ +} acmp_invert_t; + +/** + * @brief Acmp output config structure definition + */ +typedef struct +{ + acmp_out_func_t out_func; /**< Acmp output function */ + acmp_invert_t gpio_inv; /**< If invert gpio output */ +} acmp_output_config_t; + +/** + * @brief Acmp init structure definition + */ +typedef struct +{ + acmp_mode_t mode; /**< Acmp operation mode */ + acmp_warm_time_t warm_time; /**< Acmp warm up time */ + acmp_hystsel_t hystsel; /**< Acmp hysteresis level */ + acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */ + acmp_pos_input_t pos_port; /**< Acmp positive port select */ + acmp_neg_input_t neg_port; /**< Acmp negative port select */ + acmp_inactval_t inactval; /**< Acmp inavtive output value */ + acmp_edge_t edge; /** Select edges to set interrupt flag */ + uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */ +} acmp_init_t; + +/** + * @brief ACMP Handle Structure definition + */ +typedef struct acmp_handle_s +{ + ACMP_TypeDef *perh; /**< Register base address */ + acmp_init_t init; /**< ACMP required parameters */ + lock_state_t lock; /**< Locking object */ + + void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */ + void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */ +} acmp_handle_t; +/** + * @} + */ + +/** @defgroup ACMP_Public_Macros ACMP Public Macros + * @{ + */ +#define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) +#define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) +/** + * @} + */ + +/** @defgroup ACMP_Private_Macros ACMP Private Macros + * @{ + */ +#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \ + ((x) == ACMP1)) +#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \ + ((x) == ACMP_LOW_POWER) || \ + ((x) == ACMP_MIDDLE_POWER) || \ + ((x) == ACMP_HIGH_POWER)) +#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \ + ((x) == ACMP_IT_WARMUP)) +#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \ + ((x) == ACMP_FLAG_WARMUP)) +#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \ + ((x) == ACMP_STATUS_WARMUP)) +#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \ + ((x) == ACMP_POS_CH1) || \ + ((x) == ACMP_POS_CH2) || \ + ((x) == ACMP_POS_CH3) || \ + ((x) == ACMP_POS_CH4) || \ + ((x) == ACMP_POS_CH5) || \ + ((x) == ACMP_POS_CH6) || \ + ((x) == ACMP_POS_CH7)) +#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \ + ((x) == ACMP_NEG_CH1) || \ + ((x) == ACMP_NEG_CH2) || \ + ((x) == ACMP_NEG_CH3) || \ + ((x) == ACMP_NEG_CH4) || \ + ((x) == ACMP_NEG_CH5) || \ + ((x) == ACMP_NEG_CH6) || \ + ((x) == ACMP_NEG_CH7) || \ + ((x) == ACMP_NEG_1V25) || \ + ((x) == ACMP_NEG_2V5) || \ + ((x) == ACMP_NEG_VDD)) +#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \ + ((x) == ACMP_8_PCLK) || \ + ((x) == ACMP_16_PCLK) || \ + ((x) == ACMP_32_PCLK) || \ + ((x) == ACMP_64_PCLK) || \ + ((x) == ACMP_128_PCLK) || \ + ((x) == ACMP_256_PCLK) || \ + ((x) == ACMP_512_PCLK)) +#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \ + ((x) == ACMP_HYST_15) || \ + ((x) == ACMP_HYST_22) || \ + ((x) == ACMP_HYST_29) || \ + ((x) == ACMP_HYST_36) || \ + ((x) == ACMP_HYST_43) || \ + ((x) == ACMP_HYST_50) || \ + ((x) == ACMP_HYST_57)) +#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \ + ((x) == ACMP_INACTVAL_HIGH)) +#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \ + ((x) == ACMP_EDGE_FALL) || \ + ((x) == ACMP_EDGE_RISE) || \ + ((x) == ACMP_EDGE_ALL)) +#define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \ + ((x) == ACMP_OUT_ENABLE)) +#define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \ + ((x) == ACMP_GPIO_INV)) +#define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \ + ((x) == ACMP_WARM_ENABLE)) +/** + * @} + */ + +/** @addtogroup ACMP_Public_Functions + * @{ + */ + +/** @addtogroup ACMP_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_acmp_init(acmp_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup ACMP_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state); +ald_status_t ald_acmp_set_interrupt_mask(acmp_handle_t *hperh, acmp_it_t it); +it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it); +it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t it); +ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t it); +flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t flag); + +/** + * @} + */ + +/** @addtogroup ACMP_Public_Functions_Group3 + * @{ + */ +void ald_acmp_irq_handler(acmp_handle_t *hperh); +ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config); +uint8_t ald_acmp_out_result(acmp_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +extern "C" +} +#endif + +#endif diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..d138f16c88d05e061735d8519e36772fec01a008 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -0,0 +1,572 @@ +/** + ****************************************************************************** + * @file ald_adc.h + * @brief Header file of ADC Module library. + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ****************************************************************************** + */ + +#ifndef __ALD_ADC_H__ +#define __ALD_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_pis.h" +#include "ald_timer.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Pubulic_Types ADC Pubulic Types + * @{ + */ + +/** + * @brief ADC State structures definition + */ +typedef enum +{ + ADC_STATE_RESET = 0x0, /**< ADC not yet initialized or disabled */ + ADC_STATE_READY = 0x1, /**< ADC peripheral ready for use */ + ADC_STATE_BUSY_INTERNAL = 0x2, /**< ADC is busy to internal process */ + ADC_STATE_TIMEOUT = 0x4, /**< TimeOut occurrence */ + ADC_STATE_ERROR = 0x10, /**< Internal error occurrence */ + ADC_STATE_NM_BUSY = 0x100, /**< Conversion on group normal is ongoing or can occur */ + ADC_STATE_NM_EOC = 0x200, /**< Conversion data available on group normal */ + ADC_STATE_IST_BUSY = 0x1000, /**< Conversion on group insert is ongoing or can occur */ + ADC_STATE_IST_EOC = 0x2000, /**< Conversion data available on group insert */ + ADC_STATE_AWD = 0x10000, /**< Out-of-window occurrence of analog watchdog */ +} adc_state_t; + +/** + *@brief ADC Error Code + */ +typedef enum +{ + ADC_ERROR_NONE = 0x0, /**< No error */ + ADC_ERROR_INTERNAL = 0x1, /**< ADC IP internal error*/ + ADC_ERROR_OVR = 0x2, /**< Overrun error */ + ADC_ERROR_DMA = 0x4, /**< DMA transfer error */ +} adc_error_t; + +/** + *@brief ADC data alignment + */ +typedef enum +{ + ADC_DATAALIGN_RIGHT = 0x0, /**< ADC data alignment right */ + ADC_DATAALIGN_LEFT = 0x1, /**< ADC data alignment left */ +} adc_align_t; + +/** + *@brief ADC config hannal trigger the EOC IT mode + */ +typedef enum +{ + ADC_NCHESEL_MODE_ALL = 0x0, /**< ADC set RCHE after convert sequence finish */ + ADC_NCHESEL_MODE_ONE = 0x1, /**< ADC set RCHE after one convert finish */ +} adc_nchesel_t; + +/** + *@brief ADC channels + */ +typedef enum +{ + ADC_CHANNEL_0 = 0x0, /**< ADC channel 0 */ + ADC_CHANNEL_1 = 0x1, /**< ADC channel 1 */ + ADC_CHANNEL_2 = 0x2, /**< ADC channel 2 */ + ADC_CHANNEL_3 = 0x3, /**< ADC channel 3 */ + ADC_CHANNEL_4 = 0x4, /**< ADC channel 4 */ + ADC_CHANNEL_5 = 0x5, /**< ADC channel 5 */ + ADC_CHANNEL_6 = 0x6, /**< ADC channel 6 */ + ADC_CHANNEL_7 = 0x7, /**< ADC channel 7 */ + ADC_CHANNEL_8 = 0x8, /**< ADC channel 8 */ + ADC_CHANNEL_9 = 0x9, /**< ADC channel 9 */ + ADC_CHANNEL_10 = 0xA, /**< ADC channel 10 */ + ADC_CHANNEL_11 = 0xB, /**< ADC channel 11 */ + ADC_CHANNEL_12 = 0xC, /**< ADC channel 12 */ + ADC_CHANNEL_13 = 0xD, /**< ADC channel 13 */ + ADC_CHANNEL_14 = 0xE, /**< ADC channel 14 */ + ADC_CHANNEL_15 = 0xF, /**< ADC channel 15 */ + ADC_CHANNEL_16 = 0x10, /**< ADC channel 16 */ + ADC_CHANNEL_17 = 0x11, /**< ADC channel 17 */ + ADC_CHANNEL_18 = 0x12, /**< ADC channel 18 */ + ADC_CHANNEL_19 = 0x13, /**< ADC channel 19 */ +} adc_channel_t; + +/** + *@brief ADC sampling times + */ +typedef enum +{ + ADC_SAMPLETIME_1 = 0x0, /**< ADC sampling times 1 clk */ + ADC_SAMPLETIME_2 = 0x1, /**< ADC sampling times 2 clk */ + ADC_SAMPLETIME_4 = 0x2, /**< ADC sampling times 4 clk */ + ADC_SAMPLETIME_15 = 0x3, /**< ADC sampling times 15 clk */ +} adc_samp_t; + +/** + *@brief ADC rank into normal group + */ +typedef enum +{ + ADC_NCH_RANK_1 = 0x1, /**< ADC normal channel rank 1 */ + ADC_NCH_RANK_2 = 0x2, /**< ADC normal channel rank 2 */ + ADC_NCH_RANK_3 = 0x3, /**< ADC normal channel rank 3 */ + ADC_NCH_RANK_4 = 0x4, /**< ADC normal channel rank 4 */ + ADC_NCH_RANK_5 = 0x5, /**< ADC normal channel rank 5 */ + ADC_NCH_RANK_6 = 0x6, /**< ADC normal channel rank 6 */ + ADC_NCH_RANK_7 = 0x7, /**< ADC normal channel rank 7 */ + ADC_NCH_RANK_8 = 0x8, /**< ADC normal channel rank 8 */ + ADC_NCH_RANK_9 = 0x9, /**< ADC normal channel rank 9 */ + ADC_NCH_RANK_10 = 0xA, /**< ADC normal channel rank 10 */ + ADC_NCH_RANK_11 = 0xB, /**< ADC normal channel rank 11 */ + ADC_NCH_RANK_12 = 0xC, /**< ADC normal channel rank 12 */ + ADC_NCH_RANK_13 = 0xD, /**< ADC normal channel rank 13 */ + ADC_NCH_RANK_14 = 0xE, /**< ADC normal channel rank 14 */ + ADC_NCH_RANK_15 = 0xF, /**< ADC normal channel rank 15 */ + ADC_NCH_RANK_16 = 0x10, /**< ADC normal channel rank 16 */ +} adc_nch_rank_t; + +/** + * @brief ADC rank into insert group + */ +typedef enum +{ + ADC_ICH_RANK_1 = 0x1, /**< ADC insert channel rank 1 */ + ADC_ICH_RANK_2 = 0x2, /**< ADC insert channel rank 2 */ + ADC_ICH_RANK_3 = 0x3, /**< ADC insert channel rank 3 */ + ADC_ICH_RANK_4 = 0x4, /**< ADC insert channel rank 4 */ +} adc_ich_rank_t; + +/** + * @brief ADC analog watchdog mode + */ +typedef enum +{ + ADC_ANAWTD_NONE = 0x0, /**< No watch dog */ + ADC_ANAWTD_SING_NM = 0x800200, /**< One normal channel watch dog */ + ADC_ANAWTD_SING_IST = 0x400200, /**< One inset channel Injec watch dog */ + ADC_ANAWTD_SING_NMIST = 0xC00200, /**< One normal and inset channel watch dog */ + ADC_ANAWTD_ALL_NM = 0x800000, /**< All normal channel watch dog */ + ADC_ANAWTD_ALL_IST = 0x400000, /**< All inset channel watch dog */ + ADC_ANAWTD_ALL_NMIST = 0xC00000, /**< All normal and inset channel watch dog */ +} adc_ana_wtd_t; + +/** + * @brief ADC Event type + */ +typedef enum +{ + ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ +} adc_event_type_t; + +/** + * @brief ADC interrupts definition + */ +typedef enum +{ + ADC_IT_NCH = (1U << 5), /**< ADC it normal */ + ADC_IT_AWD = (1U << 6), /**< ADC it awd */ + ADC_IT_ICH = (1U << 7), /**< ADC it insert */ + ADC_IT_OVR = (1U << 26), /**< ADC it overring */ +} adc_it_t; + +/** + * @brief ADC flags definition + */ +typedef enum +{ + ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) +#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) +#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) +#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +/** + * @} + */ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +#define IS_ADC_ICH_RANK_TYPE(x) ((x) <= ADC_ICH_RANK_4) +#define IS_ADC_NCH_RANK_TYPE(x) ((x) <= ADC_NCH_RANK_16) +#define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \ + ((x) == ADC_SAMPLETIME_2) || \ + ((x) == ADC_SAMPLETIME_4) || \ + ((x) == ADC_SAMPLETIME_15)) +#define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_19) +#define IS_ADC_SCAN_MODE_TYPE(x) (((x) == DISABLE) || \ + ((x) == ENABLE)) +#define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \ + ((x) == ADC_DATAALIGN_LEFT)) +#define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \ + ((x) == ADC_ANAWTD_SING_NM) || \ + ((x) == ADC_ANAWTD_SING_IST) || \ + ((x) == ADC_ANAWTD_SING_NMIST) || \ + ((x) == ADC_ANAWTD_ALL_NM) || \ + ((x) == ADC_ANAWTD_ALL_IST) || \ + ((x) == ADC_ANAWTD_ALL_NMIST)) +#define IS_ADC_IT_TYPE(x) (((x) == ADC_IT_NCH) || \ + ((x) == ADC_IT_AWD) || \ + ((x) == ADC_IT_ICH) || \ + ((x) == ADC_IT_OVR )) +#define IS_ADC_FLAGS_TYPE(x) (((x) == ADC_FLAG_AWD) || \ + ((x) == ADC_FLAG_NCH) || \ + ((x) == ADC_FLAG_ICH) || \ + ((x) == ADC_FLAG_OVR) || \ + ((x) == ADC_FLAG_NCHS) || \ + ((x) == ADC_FLAG_ICHS)) +#define IS_ADC_CLK_DIV_TYPE(x) (((x) == ADC_CKDIV_1) || \ + ((x) == ADC_CKDIV_2) || \ + ((x) == ADC_CKDIV_4) || \ + ((x) == ADC_CKDIV_8) || \ + ((x) == ADC_CKDIV_16) || \ + ((x) == ADC_CKDIV_32) || \ + ((x) == ADC_CKDIV_64) || \ + ((x) == ADC_CKDIV_128)) +#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \ + ((x) == ADC_NEG_REF_VREFN )) +#define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \ + ((x) == ADC_POS_REF_VREEFP) || \ + ((x) == ADC_POS_REF_VREEFP_BUF)) +#define IS_ADC_NCH_LEN_TYPE(x) ((x) <= ADC_NCH_LEN_16) +#define IS_ADC_NBR_OF_IST_TYPE(x) ((x) <= ADC_ICH_LEN_4) +#define IS_ADC_DISC_MODE_TYPE(x) (((x) == ADC_ALL_DISABLE) || \ + ((x) == ADC_NCH_DISC_EN) || \ + ((x) == ADC_ICH_DISC_EN)) +#define IS_ADC_DISC_NBR_TYPE(x) ((x) <= ADC_DISC_NBR_8) +#define IS_ADC_CONV_RES_TYPE(x) (((x) == ADC_CONV_RES_12) || \ + ((x) == ADC_CONV_RES_6) || \ + ((x) == ADC_CONV_RES_8) || \ + ((x) == ADC_CONV_RES_10)) +#define IS_ADC_TRIG_MODE_TYPE(x) (((x) == ADC_TRIG_SOFT) || \ + ((x) == ADC_TRIG_PIS) || \ + ((x) == ADC_TRIG_PIS_SOFT)) +#define IS_ADC_TYPE(x) (((x) == ADC0) || \ + ((x) == ADC1)) +#define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \ + ((x) == ADC_NCHESEL_MODE_ONE)) +#define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT) +#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff) +#define IS_HTR_TYPE(x) ((x) <= 0xfff) +#define IS_LTR_TYPE(x) ((x) <= 0xfff) +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions + * @{ + */ + +/** @addtogroup ADC_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_adc_init(adc_handle_t *hperh); +ald_status_t ald_adc_reset(adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_adc_normal_start(adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop(adc_handle_t *hperh); +ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout); +ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh); +#ifdef ALD_DMA +ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh); +ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config); +#endif +uint32_t ald_adc_normal_get_value(adc_handle_t *hperh); +uint32_t ald_adc_get_vdd_value(adc_handle_t *hperh); +ald_status_t ald_adc_insert_start(adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop(adc_handle_t *hperh); +ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh); +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank); +void ald_adc_irq_handler(adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config); +ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config); +ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config); +void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state); +it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it); +flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag); +void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group4 + * @{ + */ +uint32_t ald_adc_get_state(adc_handle_t *hperh); +uint32_t ald_adc_get_error(adc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +extern "C" +} +#endif + +#endif /* __ALD_ADC_H */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h new file mode 100644 index 0000000000000000000000000000000000000000..7bac14c70ecbba4ed9a32cebfb28916215252f96 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -0,0 +1,186 @@ +/** + ********************************************************************************* + * + * @file ald_bkpc.h + * @brief Header file of BKPC module driver. + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_BKPC_H__ +#define __ALD_BKPC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup BKPC + * @{ + */ + +/** @defgroup BKPC_Public_Macros BKPC Public Macros + * @{ + */ +#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0)) +#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55)) +#define BKPC_LRC_ENABLE() \ + do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ + } while (0) +#define BKPC_LRC_DISABLE() \ + do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ + } while (0) +#define BKPC_LOSM_ENABLE() \ + do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ + BKPC_LOCK(); \ + } while (0) +#define BKPC_LOSM_DISABLE() \ + do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ + BKPC_LOCK(); \ + } while (0) +#define BKPC_LOSC_ENABLE() \ + do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ + BKPC_LOCK(); \ + } while (0) +#define BKPC_LOSC_DISABLE() \ + do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ + BKPC_LOCK(); \ + } while (0) +/** + * @} + */ + +/** @defgroup BKPC_Public_Types BKPC Public Types + * @{ + */ +/** + * @brief BKPC ldo output select + */ +typedef enum +{ + BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */ + BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */ + BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */ + BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */ +} bkpc_ldo_output_t; + +/** + * @brief BKPC BOR voltage select + */ +typedef enum +{ + BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */ + BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */ + BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */ + BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */ + BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */ + BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */ + BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */ + BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */ + BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */ + BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */ + BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */ + BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */ + BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */ + BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */ + BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */ + BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */ +} bkpc_bor_vol_t; + +/** + * @} + */ + +/** + * @defgroup BKPC_Private_Macros BKPC Private Macros + * @{ + */ +#define IS_BKPC_LDO_OUTPUT(x) (((x) == BKPC_LDO_OUTPUT_1_6) || \ + ((x) == BKPC_LDO_OUTPUT_1_3) || \ + ((x) == BKPC_LDO_OUTPUT_1_4) || \ + ((x) == BKPC_LDO_OUTPUT_1_5)) +#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \ + ((x) == BKPC_BOR_VOL_2_0) || \ + ((x) == BKPC_BOR_VOL_2_1) || \ + ((x) == BKPC_BOR_VOL_2_2) || \ + ((x) == BKPC_BOR_VOL_2_3) || \ + ((x) == BKPC_BOR_VOL_2_4) || \ + ((x) == BKPC_BOR_VOL_2_5) || \ + ((x) == BKPC_BOR_VOL_2_6) || \ + ((x) == BKPC_BOR_VOL_2_8) || \ + ((x) == BKPC_BOR_VOL_3_0) || \ + ((x) == BKPC_BOR_VOL_3_1) || \ + ((x) == BKPC_BOR_VOL_3_3) || \ + ((x) == BKPC_BOR_VOL_3_6) || \ + ((x) == BKPC_BOR_VOL_3_7) || \ + ((x) == BKPC_BOR_VOL_4_0) || \ + ((x) == BKPC_BOR_VOL_4_3)) +#define IS_BKPC_RAM_IDX(x) ((x) < 32) +/** + * @} + */ + +/** @addtogroup BKPC_Public_Functions + * @{ + */ +/** @addtogroup BKPC_Public_Functions_Group1 + * @{ + */ +/* control functions */ +extern void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state); +extern void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state); +/** + * @} + */ +/** @addtogroup BKPC_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +extern void ald_bkpc_write_ram(uint8_t idx, uint32_t value); +extern uint32_t ald_bkpc_read_ram(uint8_t idx); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_BKPC_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h similarity index 73% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h index 896522b8613f863d8d31f2d169d7f594985c307a..283417d843bc0dcbb880716abf445c20b9b8749e 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h @@ -35,10 +35,10 @@ extern "C" { /** @addtogroup CALC_Public_Functions * @{ */ -extern uint32_t calc_sqrt(uint32_t data); -extern uint32_t calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder); -extern int32_t calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder); -extern flag_status_t calc_get_dz_status(void); +extern uint32_t ald_calc_sqrt(uint32_t data); +extern uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder); +extern int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder); +extern flag_status_t ald_calc_get_dz_status(void); /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h new file mode 100644 index 0000000000000000000000000000000000000000..471c20e6acd2067da9b0fe9159c6fb904a8f6690 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h @@ -0,0 +1,491 @@ +/** + ****************************************************************************** + * @file ald_can.h + * @brief Header file of CAN Module driver. + * + * @version V1.0 + * @date 16 Apr 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ****************************************************************************** + */ + +#ifndef __ALD_CAN_H +#define __ALD_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Public_Types CAN Public Types + * @{ + */ +/** + * @brief ALD State structures definition + */ +typedef enum +{ + CAN_STATE_RESET = 0x00, /**< CAN not yet initialized or disabled */ + CAN_STATE_READY = 0x01, /**< CAN initialized and ready for use */ + CAN_STATE_BUSY = 0x02, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX = 0x11, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX = 0x21, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX = 0x31, /**< CAN process is ongoing */ + CAN_STATE_TIMEOUT = 0x03, /**< CAN in Timeout state */ + CAN_STATE_ERROR = 0x04, /**< CAN error state */ +} can_state_t; + +/** + * @brief CAN Error Code + */ +typedef enum +{ + CAN_ERROR_NONE = 0x00, /**< No error */ + CAN_ERROR_EWG = 0x01, /**< EWG error */ + CAN_ERROR_EPV = 0x02, /**< EPV error */ + CAN_ERROR_BOF = 0x04, /**< BOF error */ + CAN_ERROR_STF = 0x08, /**< Stuff error */ + CAN_ERROR_FOR = 0x10, /**< Form error */ + CAN_ERROR_ACK = 0x20, /**< Acknowledgment error */ + CAN_ERROR_BR = 0x40, /**< Bit recessive */ + CAN_ERROR_BD = 0x80, /**< LEC dominant */ + CAN_ERROR_CRC = 0x100, /**< LEC transfer error */ + CAN_ERROR_UNK = 0x200, /**< Unknown error */ +} can_error_t; + +/** + * @brief CAN Operating Mode + */ +typedef enum +{ + CAN_MODE_NORMAL = 0x00, /**< Normal mode */ + CAN_MODE_LOOPBACK = 0x01, /**< Loopback mode */ + CAN_MODE_SILENT = 0x02, /**< Silent mode */ + CAN_MODE_SILENT_LOOPBACK = 0x03, /**< Loopback combined with silent mode */ +} can_operate_mode_t; + +/** + * @brief CAN Synchronization Jump Width + */ +typedef enum +{ + CAN_SJW_1 = 0x0, /**< 1 time quantum */ + CAN_SJW_2 = 0x1, /**< 2 time quantum */ + CAN_SJW_3 = 0x2, /**< 3 time quantum */ + CAN_SJW_4 = 0x3, /**< 4 time quantum */ +} can_sjw_t; + +/** + * @brief CAN Time Quantum in Bit Segment 1 + */ +typedef enum +{ + CAN_SEG1_1 = 0x0, /**< 1 time quantum */ + CAN_SEG1_2 = 0x1, /**< 2 time quantum */ + CAN_SEG1_3 = 0x2, /**< 3 time quantum */ + CAN_SEG1_4 = 0x3, /**< 4 time quantum */ + CAN_SEG1_5 = 0x4, /**< 5 time quantum */ + CAN_SEG1_6 = 0x5, /**< 6 time quantum */ + CAN_SEG1_7 = 0x6, /**< 7 time quantum */ + CAN_SEG1_8 = 0x7, /**< 8 time quantum */ + CAN_SEG1_9 = 0x8, /**< 9 time quantum */ + CAN_SEG1_10 = 0x9, /**< 10 time quantum */ + CAN_SEG1_11 = 0xA, /**< 11 time quantum */ + CAN_SEG1_12 = 0xB, /**< 12 time quantum */ + CAN_SEG1_13 = 0xC, /**< 13 time quantum */ + CAN_SEG1_14 = 0xD, /**< 14 time quantum */ + CAN_SEG1_15 = 0xE, /**< 15 time quantum */ + CAN_SEG1_16 = 0xF, /**< 16 time quantum */ +} can_seg1_t; + +/** + * @brief CAN Time Quantum in Bit Segment 2 + */ +typedef enum +{ + CAN_SEG2_1 = 0x0, /**< 1 time quantum */ + CAN_SEG2_2 = 0x1, /**< 2 time quantum */ + CAN_SEG2_3 = 0x2, /**< 3 time quantum */ + CAN_SEG2_4 = 0x3, /**< 4 time quantum */ + CAN_SEG2_5 = 0x4, /**< 5 time quantum */ + CAN_SEG2_6 = 0x5, /**< 6 time quantum */ + CAN_SEG2_7 = 0x6, /**< 7 time quantum */ + CAN_SEG2_8 = 0x7, /**< 8 time quantum */ +} can_seg2_t; + +/** + * @brief CAN Filter Mode + */ +typedef enum +{ + CAN_FILTER_MODE_MASK = 0x0, /**< Identifier mask mode */ + CAN_FILTER_MODE_LIST = 0x1, /**< Identifier list mode */ +} can_filter_mode_t; + +/** + * @brief CAN Filter Scale + */ +typedef enum +{ + CAN_FILTER_SCALE_16 = 0x0, /**< Two 16-bit filters */ + CAN_FILTER_SCALE_32 = 0x1, /**< One 32-bit filter */ +} can_filter_scale_t; + +/** + * @brief CAN Filter fifo + */ +typedef enum +{ + CAN_FILTER_FIFO0 = 0x0, /**< FIFO 0 assignment for filter */ + CAN_FILTER_FIFO1 = 0x1, /**< FIFO 1 assignment for filter */ +} can_filter_fifo_t; + +/** + * @brief CAN Identifier Type + */ +typedef enum +{ + CAN_ID_STD = 0x0, /**< Standard Id */ + CAN_ID_EXT = 0x1, /**< Extended Id */ +} can_id_type_t; + +/** + * @brief CAN Remote Transmission Request + */ +typedef enum +{ + CAN_RTR_DATA = 0x0, /**< Data frame */ + CAN_RTR_REMOTE = 0x1, /**< Remote frame */ +} can_remote_req_t; + +/** + * @brief CAN Transmit Constants + */ +typedef enum +{ + CAN_TX_MAILBOX_0 = 0x0, /**< TX mailbox index 0 */ + CAN_TX_MAILBOX_1 = 0x1, /**< TX mailbox index 1 */ + CAN_TX_MAILBOX_2 = 0x2, /**< TX mailbox index 2 */ + CAN_TX_MAILBOX_NONE = 0x3, /**< MailBox can't be used */ +} can_tx_mailbox_t; + +/** + * @brief CAN Receive fifo Number + */ +typedef enum +{ + CAN_RX_FIFO0 = 0x0, /**< CAN fifo 0 used to receive */ + CAN_RX_FIFO1 = 0x1, /**< CAN fifo 1 used to receive */ +} can_rx_fifo_t; + +/** + * @brief CAN Flags + */ +typedef enum +{ + CAN_FLAG_SLPS = (1U << 1), /**< Sleep acknowledge flag */ + CAN_FLAG_ERR = (1U << 2), /**< Error flag*/ + CAN_FLAG_WK = (1U << 3), /**< Wake up flag */ + CAN_FLAG_SLP = (1U << 4), /**< Sleep acknowledge flag */ + CAN_FLAG_M0REQC = (1U << 20) | (1U << 0), /**< Request MailBox0 flag */ + CAN_FLAG_M0TXC = (1U << 20) | (1U << 1), /**< Transmission OK MailBox0 flag */ + CAN_FLAG_M1REQC = (1U << 20) | (1U << 8), /**< Request MailBox1 flag */ + CAN_FLAG_M1TXC = (1U << 20) | (1U << 9), /**< Transmission OK MailBox1 flag */ + CAN_FLAG_M2REQC = (1U << 20) | (1U << 16), /**< Request MailBox2 flag */ + CAN_FLAG_M2TXC = (1U << 20) | (1U << 17), /**< Transmission OK MailBox2 flag */ + CAN_FLAG_TXM0 = (1U << 20) | (1U << 26), /**< Transmit mailbox 0 empty flag */ + CAN_FLAG_TXM1 = (1U << 20) | (1U << 27), /**< Transmit mailbox 1 empty flag */ + CAN_FLAG_TXM2 = (1U << 20) | (1U << 28), /**< Transmit mailbox 2 empty flag */ + CAN_FLAG_FF0 = (2U << 20) | (1U << 3), /**< FIFO 0 Full flag */ + CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), /**< FIFO 0 Overrun flag */ + CAN_FLAG_FF1 = (3U << 20) | (1U << 3), /**< FIFO 1 Full flag */ + CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), /**< FIFO 1 Overrun flag */ + CAN_FLAG_WARN = (4U << 20) | (1U << 0), /**< Error warning flag */ + CAN_FLAG_PERR = (4U << 20) | (1U << 1), /**< Error passive flag */ + CAN_FLAG_BOF = (4U << 20) | (1U << 2), /**< Bus-Off flag */ +} can_flag_t; + +/** + * @brief CAN Interrupts + */ +typedef enum +{ + CAN_IT_TXM = (1U << 0), /**< Transmit mailbox empty interrupt bit */ + CAN_IT_FP0 = (1U << 1), /**< FIFO0 message pending interrupt bit */ + CAN_IT_FF0 = (1U << 2), /**< FIFO0 full interrupt bit */ + CAN_IT_FOV0 = (1U << 3), /**< FIFO0 overrun interrupt bit */ + CAN_IT_FP1 = (1U << 4), /**< FIFO1 message pending interrupt bit */ + CAN_IT_FF1 = (1U << 5), /**< FIFO1 full interrupt bit */ + CAN_IT_FOV1 = (1U << 6), /**< FIFO1 overrun interrupt bit */ + CAN_IT_WARN = (1U << 8), /**< Error warning interrupt bit */ + CAN_IT_PERR = (1U << 9), /**< Error passive interrupt bit */ + CAN_IT_BOF = (1U << 10), /**< Bus-off interrupt bit */ + CAN_IT_PRERR = (1U << 11), /**< Last error code interrupt bit */ + CAN_IT_ERR = (1U << 15), /**< Error interrupt bit */ + CAN_IT_WK = (1U << 16), /**< wake-up interrupt bit */ + CAN_IT_SLP = (1U << 17), /**< sleep interrupt bit */ +} can_it_t; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t id_high; /**< Specifies the filter identification number */ + uint32_t id_low; /**< Specifies the filter identification number */ + uint32_t mask_id_high; /**< Specifies the filter mask number or identification number */ + uint32_t mask_id_low; /**< Specifies the filter mask number or identification number */ + can_filter_fifo_t fifo; /**< Specifies the fifo (0 or 1) which will be assigned to the filter. */ + uint32_t number; /**< Specifies the filter which will be initialized. */ + can_filter_mode_t mode; /**< Specifies the filter mode to be initialized. */ + can_filter_scale_t scale; /**< Specifies the filter scale. */ + type_func_t active; /**< Enable or disable the filter. */ + uint32_t bank_number; /**< Select the start slave bank filter. */ +} can_filter_t; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t psc; /**< Specifies the length of a time quantum. */ + can_operate_mode_t mode; /**< Specifies the CAN operating mode. */ + can_sjw_t sjw; /**< Specifies the maximum number of time quanta the CAN hardware is + allowed to lengthen or shorten a bit to perform resynchronization. */ + can_seg1_t seg1; /**< Specifies the number of time quanta in Bit Segment 1. */ + can_seg2_t seg2; /**< Specifies the number of time quanta in Bit Segment 2. */ + type_func_t ttcm; /**< Enable or disable the time triggered communication mode. */ + type_func_t abom; /**< Enable or disable the automatic bus-off management. */ + type_func_t awk; /**< Enable or disable the automatic wake-up mode. */ + type_func_t artx; /**< Enable or disable the non-automatic retransmission mode. */ + type_func_t rfom; /**< Enable or disable the Receive fifo Locked mode. */ + type_func_t txmp; /**< Enable or disable the transmit fifo priority. */ +} can_init_t; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be transmitted. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the message that will be transmitted. */ + uint32_t len; /**< Specifies the length of the frame that will be transmitted. */ + uint8_t data[8]; /**< Contains the data to be transmitted. */ +} can_tx_msg_t; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be received. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the received message. */ + uint32_t len; /**< Specifies the length of the frame that will be received. */ + uint8_t data[8]; /**< Contains the data to be received. */ + uint32_t fmi; /**< Specifies the index of the filter the message stored in the mailbox passes through. */ + can_rx_fifo_t num; /**< Specifies the receive fifo number. */ +} can_rx_msg_t; + +/** + * @brief CAN handle Structure definition + */ +typedef struct can_handle_s +{ + CAN_TypeDef *perh; /**< Register base address */ + can_init_t init; /**< CAN required parameters */ + can_rx_msg_t *rx_msg; /**< Pointer to receive message */ + lock_state_t lock; /**< CAN locking object */ + can_state_t state; /**< CAN communication state */ + can_error_t err; /**< CAN Error code */ + + void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct can_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct can_handle_s *arg); /**< error callback */ +} can_handle_t; +/** + * @} + */ + +/** @defgroup CAN_Public_Macro CAN Public Macros + * @{ + */ +#define CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET) +#define CAN_RX_MSG_PENDING(x, y) (((y) == CAN_RX_FIFO0) ? \ + (READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK))) +#define CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS)) +#define CAN_TX_STAMP_ENABLE(x) (SET_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +#define CAN_TX_STAMP_DISABLE(x) (CLEAR_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define IS_CAN_ALL(x) ((x) == CAN0) +#define IS_CAN_FILTER_NUMBER(x) ((x) <= 13) +#define IS_CAN_MODE(x) (((x) == CAN_MODE_NORMAL) || \ + ((x) == CAN_MODE_LOOPBACK) || \ + ((x) == CAN_MODE_SILENT) || \ + ((x) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(x) (((x) == CAN_SJW_1) || \ + ((x) == CAN_SJW_2) || \ + ((x) == CAN_SJW_3) || \ + ((x) == CAN_SJW_4)) +#define IS_CAN_BS1(x) ((x) <= CAN_SEG1_16) +#define IS_CAN_BS2(x) ((x) <= CAN_SEG2_8) +#define IS_CAN_FILTER_MODE(x) (((x) == CAN_FILTER_MODE_MASK) || \ + ((x) == CAN_FILTER_MODE_LIST)) +#define IS_CAN_FILTER_SCALE(x) (((x) == CAN_FILTER_SCALE_16) || \ + ((x) == CAN_FILTER_SCALE_32)) +#define IS_CAN_FILTER_FIFO(x) (((x) == CAN_FILTER_FIFO0) || \ + ((x) == CAN_FILTER_FIFO1)) +#define IS_CAN_IDTYPE(x) (((x) == CAN_ID_STD) || \ + ((x) == CAN_ID_EXT)) +#define IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE)) +#define IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1)) +#define IS_CAN_BANKNUMBER(x) ((x) <= 28) +#define IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE) +#define IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08)) +#define IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024)) +#define IS_CAN_GET_FLAG(x) (((x) == CAN_FLAG_SLPS) || \ + ((x) == CAN_FLAG_ERR) || \ + ((x) == CAN_FLAG_WK) || \ + ((x) == CAN_FLAG_SLP) || \ + ((x) == CAN_FLAG_M0REQC) || \ + ((x) == CAN_FLAG_M0TXC) || \ + ((x) == CAN_FLAG_M1REQC) || \ + ((x) == CAN_FLAG_M1TXC) || \ + ((x) == CAN_FLAG_M2REQC) || \ + ((x) == CAN_FLAG_M2TXC) || \ + ((x) == CAN_FLAG_TXM0) || \ + ((x) == CAN_FLAG_TXM1) || \ + ((x) == CAN_FLAG_TXM2) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1) || \ + ((x) == CAN_FLAG_WARN) || \ + ((x) == CAN_FLAG_PERR) || \ + ((x) == CAN_FLAG_BOF)) +#define IS_CAN_CLEAR_FLAG(x) (((x) == CAN_FLAG_ERR) || \ + ((x) == CAN_FLAG_WK) || \ + ((x) == CAN_FLAG_SLP) || \ + ((x) == CAN_FLAG_M0REQC) || \ + ((x) == CAN_FLAG_M1REQC) || \ + ((x) == CAN_FLAG_M2REQC) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1)) +#define IS_CAN_IT(x) (((x) == CAN_IT_TXM) || \ + ((x) == CAN_IT_FP0) || \ + ((x) == CAN_IT_FF0) || \ + ((x) == CAN_IT_FOV0) || \ + ((x) == CAN_IT_FP1) || \ + ((x) == CAN_IT_FF1) || \ + ((x) == CAN_IT_FOV1) || \ + ((x) == CAN_IT_WARN) || \ + ((x) == CAN_IT_PERR) || \ + ((x) == CAN_IT_BOF) || \ + ((x) == CAN_IT_PRERR) || \ + ((x) == CAN_IT_ERR) || \ + ((x) == CAN_IT_WK) || \ + ((x) == CAN_IT_SLP)) +#define CAN_TIMEOUT_VALUE 100 +#define CAN_STATE_TX_MASK (1U << 4) +#define CAN_STATE_RX_MASK (1U << 5) +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions + * @{ + */ + +/** @addtogroup CAN_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_can_reset(can_handle_t *hperh); +ald_status_t ald_can_init(can_handle_t *hperh); +ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout); +ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg); +ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout); +ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group3 + * @{ + */ +/* Control function */ +ald_status_t ald_can_sleep(can_handle_t *hperh); +ald_status_t ald_can_wake_up(can_handle_t *hperh); +void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box); +void ald_can_irq_handler(can_handle_t *hperh); +type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box); +void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state); +it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it); +flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag); +void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group4 + * @{ + */ +/* State and Error functions */ +can_state_t ald_can_get_state(can_handle_t *hperh); +can_error_t ald_can_get_error(can_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CAN_H */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h new file mode 100644 index 0000000000000000000000000000000000000000..5bcae0bd075aa20383264f2e98295db69d5770b0 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -0,0 +1,653 @@ +/** + ********************************************************************************* + * + * @file ald_cmu.h + * @brief Header file of CMU module driver. + * + * @version V1.0 + * @date 22 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_CMU_H__ +#define __ALD_CMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_syscfg.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CMU + * @{ + */ + +/** @defgroup CMU_Public_Macros CMU Public Macros + * @{ + */ +#define CMU_LOSC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LOSC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LRC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LRC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_ULRC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_ULRC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) + +/* Low power mode control */ +#define CMU_LP_LRC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_LRC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_LOSC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_LOSC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_HRC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_HRC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_HOSC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_HOSC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +/** + * @} + */ + + +/** @defgroup CMU_Public_Types CMU Public Types + * @{ + */ +/** + * @brief CMU state structure definition + */ +typedef enum +{ + CMU_CLOCK_HRC = 0x1, /**< HRC */ + CMU_CLOCK_LRC = 0x2, /**< LRC */ + CMU_CLOCK_LOSC = 0x3, /**< LOSC */ + CMU_CLOCK_PLL1 = 0x4, /**< PLL1 */ + CMU_CLOCK_HOSC = 0x5, /**< HOSC */ +} cmu_clock_t; + +/** + * @brief PLL1 output clock + */ +typedef enum +{ + CMU_PLL1_OUTPUT_32M = 0x0, /**< x8 (32MHz) */ + CMU_PLL1_OUTPUT_48M = 0x1, /**< x12 (48MHz) */ +} cmu_pll1_output_t; + +/** + * @brief PLL1 referance clock + */ +typedef enum +{ + CMU_PLL1_INPUT_HRC_6 = 0x0, /**< HRC / 6 */ + CMU_PLL1_INPUT_PLL2 = 0x1, /**< PLL2 */ + CMU_PLL1_INPUT_HOSC = 0x2, /**< HOSC / 1 */ + CMU_PLL1_INPUT_HOSC_2 = 0x3, /**< HOSC / 2 */ + CMU_PLL1_INPUT_HOSC_3 = 0x4, /**< HOSC / 3 */ + CMU_PLL1_INPUT_HOSC_4 = 0x5, /**< HOSC / 4 */ + CMU_PLL1_INPUT_HOSC_5 = 0x6, /**< HOSC / 5 */ + CMU_PLL1_INPUT_HOSC_6 = 0x7, /**< HOSC / 6 */ +} cmu_pll1_input_t; + +/** + * @brief HOSC range + */ +typedef enum +{ + CMU_HOSC_2M = 0x0, + CMU_HOSC_4M = 0x1, + CMU_HOSC_8M = 0x2, + CMU_HOSC_16M = 0x3, + CMU_HOSC_24M = 0x4, +} cmu_hosc_range_t; + +/** + * @brief Auto-calibrate input + */ +typedef enum +{ + CMU_AUTO_CALIB_INPUT_LOSE = 0x0, + CMU_AUTO_CALIB_INPUT_HOSE = 0x1, +} cmu_auto_calib_input_t; + +/** + * @brief Auto-calibrate output + */ +typedef enum +{ + CMU_AUTO_CALIB_OUTPUT_24M = 0x0, + CMU_AUTO_CALIB_OUTPUT_2M = 0x1, +} cmu_auto_calib_output_t; + +/** + * @brief Frequency division select bit + */ +typedef enum +{ + CMU_DIV_1 = 0x0, /**< Division by 1 */ + CMU_DIV_2 = 0x1, /**< Division by 2 */ + CMU_DIV_4 = 0x2, /**< Division by 4 */ + CMU_DIV_8 = 0x3, /**< Division by 8 */ + CMU_DIV_16 = 0x4, /**< Division by 16 */ + CMU_DIV_32 = 0x5, /**< Division by 32 */ + CMU_DIV_64 = 0x6, /**< Division by 64 */ + CMU_DIV_128 = 0x7, /**< Division by 128 */ + CMU_DIV_256 = 0x8, /**< Division by 256 */ + CMU_DIV_512 = 0x9, /**< Division by 512 */ + CMU_DIV_1024 = 0xA, /**< Division by 1024 */ + CMU_DIV_2048 = 0xB, /**< Division by 2048 */ + CMU_DIV_4096 = 0xC, /**< Division by 4096 */ +} cmu_div_t; + +/** + * @brief Bus type + */ +typedef enum +{ + CMU_HCLK_1 = 0x0, /**< AHB1 bus */ + CMU_SYS = 0x1, /**< SYS bus */ + CMU_PCLK_1 = 0x2, /**< APB1 bus */ + CMU_PCLK_2 = 0x3, /**< APB2 bus */ +} cmu_bus_t; + +/** + * @brief Output high clock select + */ +typedef enum +{ + CMU_OUTPUT_HIGH_SEL_HOSC = 0x0, /**< Select HOSC */ + CMU_OUTPUT_HIGH_SEL_LOSC = 0x1, /**< Select LOSC */ + CMU_OUTPUT_HIGH_SEL_HRC = 0x2, /**< Select HRC */ + CMU_OUTPUT_HIGH_SEL_LRC = 0x3, /**< Select LRC */ + CMU_OUTPUT_HIGH_SEL_HOSM = 0x4, /**< Select HOSM */ + CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5, /**< Select PLL1 */ + CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6, /**< Select PLL2 */ + CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7, /**< Select SYSCLK */ +} cmu_output_high_sel_t; + +/** + * @brief Output frequency division + */ +typedef enum +{ + CMU_OUTPUT_DIV_1 = 0x0, /**< Division by 1 */ + CMU_OUTPUT_DIV_2 = 0x1, /**< Division by 2 */ + CMU_OUTPUT_DIV_4 = 0x2, /**< Division by 4 */ + CMU_OUTPUT_DIV_8 = 0x3, /**< Division by 8 */ + CMU_OUTPUT_DIV_16 = 0x4, /**< Division by 16 */ + CMU_OUTPUT_DIV_32 = 0x5, /**< Division by 32 */ + CMU_OUTPUT_DIV_64 = 0x6, /**< Division by 64 */ + CMU_OUTPUT_DIV_128 = 0x7, /**< Division by 128 */ +} cmu_output_high_div_t; + +/** + * @brief Output low clock select + */ +typedef enum +{ + CMU_OUTPUT_LOW_SEL_LOSC = 0x0, /**< Select LOSC */ + CMU_OUTPUT_LOW_SEL_LRC = 0x1, /**< Select LRC */ + CMU_OUTPUT_LOW_SEL_LOSM = 0x2, /**< Select LOSM */ + CMU_OUTPUT_LOW_SEL_BUZZ = 0x3, /**< Select BUZZ */ + CMU_OUTPUT_LOW_SEL_ULRC = 0x4, /**< Select ULRC */ +} cmu_output_low_sel_t; + +/** + * @brief BUZZ frequency division + */ +typedef enum +{ + CMU_BUZZ_DIV_2 = 0x0, /**< Division by 2 */ + CMU_BUZZ_DIV_4 = 0x1, /**< Division by 4 */ + CMU_BUZZ_DIV_8 = 0x2, /**< Division by 8 */ + CMU_BUZZ_DIV_16 = 0x3, /**< Division by 16 */ + CMU_BUZZ_DIV_32 = 0x4, /**< Division by 32 */ + CMU_BUZZ_DIV_64 = 0x5, /**< Division by 64 */ + CMU_BUZZ_DIV_128 = 0x6, /**< Division by 128 */ + CMU_BUZZ_DIV_256 = 0x7, /**< Division by 256 */ +} cmu_buzz_div_t; + +/** + * @brief Low power peripheral clock select + */ +typedef enum +{ + CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0, /**< Select PCLK2 */ + CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1, /**< Select PLL1 */ + CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2, /**< Select PLL2 */ + CMU_LP_PERH_CLOCK_SEL_HRC = 0x3, /**< Select HRC */ + CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4, /**< Select HOSC */ + CMU_LP_PERH_CLOCK_SEL_LRC = 0x5, /**< Select LRC */ + CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6, /**< Select LOSC */ + CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7, /**< Select ULRC */ + CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8, /**< Select HRC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9, /**< Select HOSC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_LOSM = 0xA, /**< Select LOSM */ + CMU_LP_PERH_CLOCK_SEL_HOSM = 0xB, /**< Select HOSM */ +} cmu_lp_perh_clock_sel_t; + +/** + * @brief LCD clock select + */ +typedef enum +{ + CMU_LCD_SEL_LOSM = 0x0, /**< Select LOSM */ + CMU_LCD_SEL_LOSC = 0x1, /**< Select LOSC */ + CMU_LCD_SEL_LRC = 0x2, /**< Select LRC */ + CMU_LCD_SEL_ULRC = 0x3, /**< Select ULRC */ + CMU_LCD_SEL_HRC_1M = 0x4, /**< Select HRC down to 1MHz */ + CMU_LCD_SEL_HOSC_1M = 0x5, /**< Select HOSC down to 1MHz */ +} cmu_lcd_clock_sel_t; + +/** + * @brief Peripheral clock enable/disable + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + CMU_PERH_GPIO = (1U << 0), /**< GPIO */ + CMU_PERH_CRC = (1U << 1), /**< CRC */ + CMU_PERH_CALC = (1U << 2), /**< CALC */ + CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ + CMU_PERH_TRNG = (1U << 4), /**< TRNG */ + CMU_PERH_PIS = (1U << 5), /**< PIS */ + CMU_PERH_TIMER0 = (1U << 0) | (1U << 27), /**< TIMER0 */ + CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), /**< TIMER1 */ + CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), /**< TIMER2 */ + CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), /**< TIMER3 */ + CMU_PERH_TIMER4 = (1U << 4) | (1U << 27), /**< TIMER4 */ + CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), /**< TIMER5 */ + CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), /**< TIMER6 */ + CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), /**< TIMER7 */ + CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ + CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ + CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ + CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ + CMU_PERH_USART0 = (1U << 12) | (1U << 27), /**< USART0 */ + CMU_PERH_USART1 = (1U << 13) | (1U << 27), /**< USART1 */ + CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ + CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ + CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ + CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ + CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ + CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ + CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ + CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ + CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ + CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ + CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ + CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ + CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ + CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ + CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ + CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ + CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ + CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ + CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */ + CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ + CMU_PERH_BKRPAM = (1U << 18) | (1U << 28), /**< BKPRAM */ + CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ + CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ +} cmu_perh_t; + +/** + * @brief CMU interrupt type + */ +typedef enum +{ + CMU_LOSC_STOP = 0x0, /**< LOSC STOP INTERRUPT */ + CMU_HOSC_STOP = 0x1, /**< HOSC STOP INTERRUPT */ + CMU_PLL1_UNLOCK = 0x2, /**< PLL1 UNLOCK INTERRUPT */ + CMU_LOSC_START = 0x3, /**< LOSC START INTERRUPT */ + CMU_HOSC_START = 0x4, /**< HOSC START INTERRUPT */ +} cmu_security_t; + +/** + * @brief CMU clock state type + */ +typedef enum +{ + CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ + CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ + CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ + CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ + CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ + CMU_CLOCK_STATE_PLLACT = (1U << 8), /**< PLL active */ + CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ + CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ + CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ + CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ + CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ +} cmu_clock_state_t; +/** + * @} + */ + +/** + * @defgroup CMU_Private_Macros CMU Private Macros + * @{ + */ +#define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \ + ((x) == CMU_CLOCK_LRC) || \ + ((x) == CMU_CLOCK_LOSC) || \ + ((x) == CMU_CLOCK_PLL1) || \ + ((x) == CMU_CLOCK_HOSC)) +#define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_32M) || \ + ((x) == CMU_PLL1_OUTPUT_48M)) +#define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ + ((x) == CMU_PLL1_INPUT_PLL2) || \ + ((x) == CMU_PLL1_INPUT_HOSC) || \ + ((x) == CMU_PLL1_INPUT_HOSC_2) || \ + ((x) == CMU_PLL1_INPUT_HOSC_3) || \ + ((x) == CMU_PLL1_INPUT_HOSC_4) || \ + ((x) == CMU_PLL1_INPUT_HOSC_5) || \ + ((x) == CMU_PLL1_INPUT_HOSC_6)) +#define IS_CMU_HOSC_RANGE(x) (((x) == CMU_HOSC_2M) || \ + ((x) == CMU_HOSC_4M) || \ + ((x) == CMU_HOSC_8M) || \ + ((x) == CMU_HOSC_16M) || \ + ((x) == CMU_HOSC_24M)) +#define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \ + ((x) == CMU_DIV_2) || \ + ((x) == CMU_DIV_4) || \ + ((x) == CMU_DIV_8) || \ + ((x) == CMU_DIV_16) || \ + ((x) == CMU_DIV_32) || \ + ((x) == CMU_DIV_64) || \ + ((x) == CMU_DIV_128) || \ + ((x) == CMU_DIV_256) || \ + ((x) == CMU_DIV_512) || \ + ((x) == CMU_DIV_1024) || \ + ((x) == CMU_DIV_2048) || \ + ((x) == CMU_DIV_4096)) +#define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \ + ((x) == CMU_SYS) || \ + ((x) == CMU_PCLK_1) || \ + ((x) == CMU_PCLK_2)) +#define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) +#define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \ + ((x) == CMU_OUTPUT_DIV_2) || \ + ((x) == CMU_OUTPUT_DIV_4) || \ + ((x) == CMU_OUTPUT_DIV_8) || \ + ((x) == CMU_OUTPUT_DIV_16) || \ + ((x) == CMU_OUTPUT_DIV_32) || \ + ((x) == CMU_OUTPUT_DIV_64) || \ + ((x) == CMU_OUTPUT_DIV_128)) +#define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \ + ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ + ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) +#define IS_CMU_AUTO_CALIB_INPUT(x) (((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \ + ((x) == CMU_AUTO_CALIB_INPUT_HOSE)) +#define IS_CMU_AUTO_CALIB_OUTPUT(x) (((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \ + ((x) == CMU_AUTO_CALIB_OUTPUT_2M)) +#define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ + ((x) == CMU_BUZZ_DIV_4) || \ + ((x) == CMU_BUZZ_DIV_8) || \ + ((x) == CMU_BUZZ_DIV_16) || \ + ((x) == CMU_BUZZ_DIV_32) || \ + ((x) == CMU_BUZZ_DIV_64) || \ + ((x) == CMU_BUZZ_DIV_128) || \ + ((x) == CMU_BUZZ_DIV_256)) +#define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) +#define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \ + ((x) == CMU_LCD_SEL_LOSC) || \ + ((x) == CMU_LCD_SEL_LRC) || \ + ((x) == CMU_LCD_SEL_ULRC) || \ + ((x) == CMU_LCD_SEL_HRC_1M) || \ + ((x) == CMU_LCD_SEL_HOSC_1M)) +#define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \ + ((x) == CMU_PERH_CRC) || \ + ((x) == CMU_PERH_CALC) || \ + ((x) == CMU_PERH_CRYPT) || \ + ((x) == CMU_PERH_TRNG) || \ + ((x) == CMU_PERH_PIS) || \ + ((x) == CMU_PERH_TIMER0) || \ + ((x) == CMU_PERH_TIMER1) || \ + ((x) == CMU_PERH_TIMER2) || \ + ((x) == CMU_PERH_TIMER3) || \ + ((x) == CMU_PERH_TIMER4) || \ + ((x) == CMU_PERH_TIMER5) || \ + ((x) == CMU_PERH_TIMER6) || \ + ((x) == CMU_PERH_TIMER7) || \ + ((x) == CMU_PERH_UART0) || \ + ((x) == CMU_PERH_UART1) || \ + ((x) == CMU_PERH_UART2) || \ + ((x) == CMU_PERH_UART3) || \ + ((x) == CMU_PERH_USART0) || \ + ((x) == CMU_PERH_USART1) || \ + ((x) == CMU_PERH_SPI0) || \ + ((x) == CMU_PERH_SPI1) || \ + ((x) == CMU_PERH_SPI2) || \ + ((x) == CMU_PERH_I2C0) || \ + ((x) == CMU_PERH_I2C1) || \ + ((x) == CMU_PERH_CAN) || \ + ((x) == CMU_PERH_LPTIM0) || \ + ((x) == CMU_PERH_LPUART0) || \ + ((x) == CMU_PERH_ADC0) || \ + ((x) == CMU_PERH_ADC1) || \ + ((x) == CMU_PERH_ACMP0) || \ + ((x) == CMU_PERH_ACMP1) || \ + ((x) == CMU_PERH_OPAMP) || \ + ((x) == CMU_PERH_DAC0) || \ + ((x) == CMU_PERH_WWDT) || \ + ((x) == CMU_PERH_LCD) || \ + ((x) == CMU_PERH_IWDT) || \ + ((x) == CMU_PERH_RTC) || \ + ((x) == CMU_PERH_TSENSE) || \ + ((x) == CMU_PERH_BKPC) || \ + ((x) == CMU_PERH_BKRPAM ) || \ + ((x) == CMU_PERH_DBGC) || \ + ((x) == CMU_PERH_ALL)) +#define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ + ((x) == CMU_CLOCK_STATE_LOSCACT) || \ + ((x) == CMU_CLOCK_STATE_HRCACT) || \ + ((x) == CMU_CLOCK_STATE_LRCACT) || \ + ((x) == CMU_CLOCK_STATE_ULRCACT) || \ + ((x) == CMU_CLOCK_STATE_PLLACT) || \ + ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_HRCRDY) || \ + ((x) == CMU_CLOCK_STATE_LRCRDY) || \ + ((x) == CMU_CLOCK_STATE_PLLRDY)) +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions + * @{ + */ +/** @addtogroup CMU_Public_Functions_Group1 + * @{ + */ +/* System clock configure */ +ald_status_t ald_cmu_clock_config_default(void); +ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock); +void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output); +uint32_t ald_cmu_get_clock(void); +int32_t ald_cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group2 + * @{ + */ +/* BUS division control */ +void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div); +uint32_t ald_cmu_get_hclk1_clock(void); +uint32_t ald_cmu_get_sys_clock(void); +uint32_t ald_cmu_get_pclk1_clock(void); +uint32_t ald_cmu_get_pclk2_clock(void); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group3 + * @{ + */ +/* Clock safe configure */ +void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); +void ald_cmu_losc_safe_config(type_func_t status); +void ald_cmu_pll_safe_config(type_func_t status); +flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr); +void ald_cmu_irq_handler(void); +void ald_cmu_irq_cbk(cmu_security_t se); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group4 + * @{ + */ +/* Clock output configure */ +void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, + cmu_output_high_div_t div, type_func_t status); +void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group5 + * @{ + */ +/* Peripheral Clock configure */ +void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status); +void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock); +void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock); +void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock); +void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CMU_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h similarity index 100% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..e3281dc166891a72aae047822aacfed3f1568c26 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -0,0 +1,202 @@ +/** + ********************************************************************************* + * + * @file ald_crc.h + * @brief Header file of CRC module driver. + * + * @version V1.0 + * @date 6 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_CRC_H__ +#define __ALD_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Public_Types CRC Public Types + * @{ + */ + +/** + * @brief CRC mode + */ +typedef enum +{ + CRC_MODE_CCITT = 0, /**< Ccitt */ + CRC_MODE_8 = 1, /**< Crc8 */ + CRC_MODE_16 = 2, /**< Crc16 */ + CRC_MODE_32 = 3, /**< Crc32 */ +} crc_mode_t; + +/** + * @brief CRC input length + */ +typedef enum +{ + CRC_LEN_AUTO = 0, /**< Auto */ + CRC_DATASIZE_8 = 1, /**< Byte */ + CRC_DATASIZE_16 = 2, /**< Half word */ + CRC_DATASIZE_32 = 3, /**< Word */ +} crc_datasize_t; + +/** + * @brief CRC whether write error or no + */ +typedef enum +{ + CRC_WERR_NO = 0, /**< No error */ + CRC_WERR_ERR = 1, /**< Error */ +} crc_werr_t; + +/** + * @brief CRC state structures definition + */ +typedef enum +{ + CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */ + CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + CRC_STATE_ERROR = 0x4, /**< Error */ +} crc_state_t; + +/** + * @brief CRC init structure definition + */ +typedef struct +{ + crc_mode_t mode; /**< CRC mode */ + type_func_t data_rev; /**< CRC data reverse or no */ + type_func_t data_inv; /**< CRC data inverse or no */ + type_func_t chs_rev; /**< CRC check sum reverse or no */ + type_func_t chs_inv; /**< CRC check sum inverse or no */ + uint32_t seed; /**< CRC seed */ +} crc_init_t; + +/** + * @brief CRC Handle Structure definition + */ +typedef struct crc_handle_s +{ + CRC_TypeDef *perh; /**< Register base address */ + crc_init_t init; /**< CRC required parameters */ + uint8_t *cal_buf; /**< The pointer of preparing buffer */ + uint32_t *cal_res; /**< The pointer of result */ +#ifdef ALD_DMA + dma_handle_t hdma; /**< CRC DMA handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + crc_state_t state; /**< CRC operation state */ + + void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ + void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ +} crc_handle_t; +/** + * @} + */ + +/** @defgroup CRC_Public_Macros CRC Public Macros + * @{ + */ +#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK)) +#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK)) +/** + * @} + */ + +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ +#define IS_CRC(x) ((x) == CRC) +#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \ + ((x) == CRC_MODE_8) || \ + ((x) == CRC_MODE_16) || \ + ((x) == CRC_MODE_32)) +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions + * @{ + */ + +/** @addtogroup CRC_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_crc_init(crc_handle_t *hperh); +void ald_crc_reset(crc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions_Group2 + * @{ + */ +uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size); +uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size); +uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size); +/** + * @} + */ + +#ifdef ALD_DMA +/** @addtogroup CRC_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_dma_pause(crc_handle_t *hperh); +ald_status_t ald_crc_dma_resume(crc_handle_t *hperh); +ald_status_t ald_crc_dma_stop(crc_handle_t *hperh); +/** + * @} + */ +#endif +/** @addtogroup CRC_Public_Functions_Group4 + * @{ + */ +crc_state_t ald_crc_get_state(crc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CRC_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h new file mode 100644 index 0000000000000000000000000000000000000000..18340558a2d5e6b2c805d2b2035025bcec1b3e6a --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -0,0 +1,264 @@ +/** + ********************************************************************************* + * + * @file ald_crypt.h + * @brief Header file of CRYPT module driver. + * + * @version V1.0 + * @date 7 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_CRYPT_H__ +#define __ALD_CRYPT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CRYPT + * @{ + */ + +/** @defgroup CRYPT_Public_Types CRYPT Public Types + * @{ + */ + +/** + * @brief CRYPT encrypt or decrypt select + */ +typedef enum +{ + CRYPT_DECRYPT = 0, /**< Decrypt */ + CRYPT_ENCRYPT = 1, /**< Encrypt */ +} crypt_encs_t; + +/** + * @brief CRYPT mode select + */ +typedef enum +{ + CRYPT_MODE_ECB = 0, /**< ECB */ + CRYPT_MODE_CBC = 1, /**< CBC */ + CRYPT_MODE_CTR = 2, /**< CTR */ +} crypt_mode_t; + +/** + * @brief CRYPT data type + */ +typedef enum +{ + CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */ + CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */ + CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */ + CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */ +} crypt_datatype_t; + +/** + * @brief CRYPT interrupt + */ +typedef enum +{ + CRYPT_IT_IT = 0x80, /**< Interrupt */ +} crypt_it_t; + +/** + * @brief CRYPT interrupt flag + */ +typedef enum +{ + CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */ + CRYPT_FLAG_DONE = 0x100, /**< Complete flag */ +} crypt_flag_t; + +/** + * @brief CRYPT state structures definition + */ +typedef enum +{ + CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */ + CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + CRYPT_STATE_ERROR = 0x4, /**< Error */ +} crypt_state_t; + +/** + * @brief CRYPT data type + */ +typedef enum +{ + DATA_32_BIT = 0, /**< 32 bit data,don't swap */ + DATA_16_BIT = 1, /**< 16 bit data,swap */ + DATA_8_BIT = 2, /**< 8 bit data,swap */ + DATA_1_BIT = 3, /**< 1 bit data, swap */ +} crypt_data_t; + +/** + * @brief CRYPT init structure definition + */ +typedef struct +{ + crypt_mode_t mode; /**< Crypt mode */ + crypt_data_t type; /**< Data type select */ +} crypt_init_t; + +/** + * @brief CRYPT Handle Structure definition + */ +typedef struct crypt_handle_s +{ + CRYPT_TypeDef *perh; /**< Register base address */ + crypt_init_t init; /**< CRYPT required parameters */ +#ifdef ALD_DMA + dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ + dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ +#endif + uint8_t *plain_text; /**< Pointer to plain text */ + uint8_t *cipher_text; /**< Pointer to cipher text */ + uint32_t size; /**< The size of crypt data buf */ + uint32_t count; /**< The count of crypt data buf */ + uint32_t step; /**< The step of once crypt 4(aes) */ + uint32_t dir; /**< ENCRYPT or DECRYPT */ + uint32_t iv[4]; /**< The iv of crypt */ + uint32_t key[4]; /**< The key of crypt */ + lock_state_t lock; /**< Locking object */ + crypt_state_t state; /**< CRYPT operation state */ + + void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ + void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ +} crypt_handle_t; +/** + * @} + */ + +/** @defgroup CRYPT_Public_Macros CRYPT Public Macros + * @{ + */ +#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK)) +#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) +#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) +#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) +#define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) +#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) +#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) +#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \ + (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) +#define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data)) +#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO) +/** + * @} + */ + +/** @defgroup CRYPT_Private_Macros CRYPT Private Macros + * @{ + */ +#define IS_CRYPT(x) ((x) == CRYPT) +#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \ + ((x) == CRYPT_MODE_CBC) || \ + ((x) == CRYPT_MODE_CTR)) +#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT) +#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \ + ((x) == CRYPT_FLAG_DONE)) +#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \ + ((x) == IV_4_LEN)) +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions + * @{ + */ + +/** @addtogroup CRYPT_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_crypt_init(crypt_handle_t *hperh); +ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key); +ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key); +ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv); +ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); +ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); +ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag); +ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); +ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); +#ifdef ALD_DMA +ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); +ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); +#endif +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group3 + * @{ + */ +#ifdef ALD_DMA +ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh); +ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh); +ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh); +#endif +void ald_crypt_irq_handler(crypt_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group4 + * @{ + */ +void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state); +flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); +void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); +it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group5 + * @{ + */ +crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h similarity index 58% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h index 293997c04e6e72ad50409ff599ee9d6859719394..31b8dc6ca40a811eca70ef4dd86608feec96534b 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -43,10 +43,10 @@ extern "C" { */ typedef enum { - DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */ - DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */ - DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */ - DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */ + DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */ + DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */ + DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */ + DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */ } dbgc_mode_t; /** @@ -54,21 +54,21 @@ typedef enum */ typedef enum { - DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */ - DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */ - DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */ - DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */ - DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */ - DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */ - DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */ - DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */ - DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */ - DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */ - DEBC_PERH_CAN = (1u << 12), /**< CAN */ - DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */ - DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */ - DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */ - DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */ + DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */ + DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */ + DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */ + DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */ + DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */ + DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */ + DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */ + DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */ + DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */ + DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */ + DEBC_PERH_CAN = (1u << 12), /**< CAN */ + DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */ + DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */ + DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */ + DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */ } dbgc_perh_t; /** * @} @@ -81,7 +81,7 @@ typedef enum * @brief Gets version. * @retval Version */ -__INLINE uint32_t dbgc_get_rev_id(void) +__INLINE uint32_t ald_dbgc_get_rev_id(void) { return (DBGC->IDCODE >> 16); } @@ -90,7 +90,7 @@ __INLINE uint32_t dbgc_get_rev_id(void) * @brief Gets core id. * @retval Core id */ -__INLINE uint32_t dbgc_get_core_id(void) +__INLINE uint32_t ald_dbgc_get_core_id(void) { return (DBGC->IDCODE >> 12) & 0xF; } @@ -99,7 +99,7 @@ __INLINE uint32_t dbgc_get_core_id(void) * @brief Gets device id * @retval device id */ -__INLINE uint32_t dbgc_get_device_id(void) +__INLINE uint32_t ald_dbgc_get_device_id(void) { return DBGC->IDCODE & 0xFFF; } @@ -110,7 +110,7 @@ __INLINE uint32_t dbgc_get_device_id(void) * @param state: ENABLE/DISABLE * @retval None */ -__INLINE void dbgc_mode_config(dbgc_mode_t mode, type_func_t state) +__INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state) { if (state) SET_BIT(DBGC->CR, mode); @@ -124,7 +124,7 @@ __INLINE void dbgc_mode_config(dbgc_mode_t mode, type_func_t state) * @param state: ENABLE/DISABLE * @retval None */ -__INLINE void dbgc_perh_config(dbgc_perh_t perh, type_func_t state) +__INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state) { if ((perh >> 16) & 0x1) { diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..364f9e16cb40498c8e85e6deeb80c3b4a1afd769 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -0,0 +1,409 @@ +/** + ********************************************************************************* + * + * @file ald_dma.h + * @brief DMA module Library. + * + * @version V1.0 + * @date 09 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_DMA_H__ +#define __ALD_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** + * @defgroup DMA_Public_Macros DMA Public Macros + * @{ + */ +#define DMA_CH_COUNT 6 +#define DMA_ERR 31 +/** + * @} + */ + +/** + * @defgroup DMA_Public_Types DMA Public Types + * @{ + */ + +/** + * @brief Input source to DMA channel + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + DMA_MSEL_NONE = 0x0, /**< NONE */ + DMA_MSEL_GPIO = 0x1, /**< GPIO */ + DMA_MSEL_CRYPT = 0x2, /**< CRYPT */ + DMA_MSEL_ACMP = 0x3, /**< ACMP */ + DMA_MSEL_DAC0 = 0x4, /**< DAC0 */ + DMA_MSEL_ADC0 = 0x6, /**< ADC0 */ + DMA_MSEL_CRC = 0x7, /**< CRC */ + DMA_MSEL_UART0 = 0x8, /**< UART0 */ + DMA_MSEL_UART1 = 0x9, /**< UART1 */ + DMA_MSEL_UART2 = 0xA, /**< UART2 */ + DMA_MSEL_UART3 = 0xB, /**< UART3 */ + DMA_MSEL_USART0 = 0xC, /**< USART0 */ + DMA_MSEL_USART1 = 0xD, /**< USART1 */ + DMA_MSEL_SPI0 = 0xE, /**< SPI0 */ + DMA_MSEL_SPI1 = 0xF, /**< SPI1 */ + DMA_MSEL_I2C0 = 0x10, /**< I2C0 */ + DMA_MSEL_I2C1 = 0x11, /**< I2C1 */ + DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */ + DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */ + DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */ + DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */ + DMA_MSEL_RTC = 0x16, /**< RTC */ + DMA_MSEL_LPTIM0 = 0x17, /**< LPTIM0 */ + DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */ + DMA_MSEL_DMA = 0x19, /**< DMA */ + DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */ + DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */ + DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */ + DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */ + DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */ + DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */ + DMA_MSEL_PIS = 0x20, /**< PIS */ + DMA_MSEL_TRNG = 0x21, /**< TRNG */ +} dma_msel_t; + +/** + * @brief Input signal to DMA channel + */ +typedef enum +{ + DMA_MSIGSEL_NONE = 0x0, /**< NONE */ + DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */ + DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */ + DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */ + DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */ + DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */ + DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */ + DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */ + DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */ + DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */ + DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */ + DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */ + DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */ + DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */ + DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */ + DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */ + DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */ + DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */ + DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */ + DMA_MSIGSEL_CALC_WRITE = 0x0, /**< CALC write mode */ + DMA_MSIGSEL_CALC_READ = 0x1, /**< CALC read mode */ + DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */ + DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */ + DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */ + DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART transmit */ + DMA_MSIGSEL_UART_RNR = 0x1, /**< UART receive */ + DMA_MSIGSEL_USART_RNR = 0x0, /**< USART reveive */ + DMA_MSIGSEL_USART_TXEMPTY = 0x1, /**< USART transmit */ + DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */ + DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */ + DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */ + DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */ + DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */ + DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */ + DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */ + DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */ + DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */ + DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */ + DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */ + DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */ + DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */ + DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */ + DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */ + DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */ + DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */ + DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */ + DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */ + DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */ + DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */ + DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */ + DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */ + DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */ + DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */ + DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */ + DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */ + DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */ + DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */ +} dma_msigsel_t; + +/** + * @brief DMA Descriptor control type + */ +typedef union +{ + struct + { + uint32_t cycle_ctrl : 3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ + uint32_t next_useburst : 1; /**< Uses the alternate data structure when complete a DMA cycle */ + uint32_t n_minus_1 : 10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ + uint32_t R_power : 4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + uint32_t src_prot_ctrl : 3; /**< Control the state of HPROT when reads the source data. */ + uint32_t dst_prot_ctrl : 3; /**< Control the state of HPROT when writes the destination data */ + uint32_t src_size : 2; /**< Source data size @ref dma_data_size_t */ + uint32_t src_inc : 2; /**< Control the source address increment. @ref dma_data_inc_t */ + uint32_t dst_size : 2; /**< Destination data size. @ref dma_data_size_t */ + uint32_t dst_inc : 2; /**< Destination address increment. @ref dma_data_inc_t */ + }; + uint32_t word; +} dma_ctrl_t; + +/** + * @brief Channel control data structure + */ +typedef struct +{ + void *src; /**< Source data end pointer */ + void *dst; /**< Destination data end pointer */ + dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ + uint32_t use; /**< Reserve for user */ +} dma_descriptor_t; + +/** + * @brief data increment + */ +typedef enum +{ + DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */ + DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */ + DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */ + DMA_DATA_INC_NONE = 0x3, /**< No increment */ +} dma_data_inc_t; + +/** + * @brief Data size + */ +typedef enum +{ + DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */ + DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */ + DMA_DATA_SIZE_WORD = 0x2, /**< Word */ +} dma_data_size_t; + +/** + * @brief The operating mode of the DMA cycle + */ +typedef enum +{ + DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */ + DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */ + DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */ + DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */ + DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */ + DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */ +} dma_cycle_ctrl_t; + +/** + * @brief Control how many DMA transfers can occur + * before the controller re-arbitrates + */ +typedef enum +{ + DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */ + DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */ + DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */ + DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */ + DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */ + DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */ + DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */ + DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */ + DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */ + DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */ + DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */ +} dma_arbiter_config_t; + +/** + * @brief Callback function pointer and param + */ +typedef struct +{ + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void *arg); /**< DMA occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ +} dma_call_back_t; + +/** + * @brief DMA channal configure structure + */ +typedef struct +{ + void *src; /**< Source data begin pointer */ + void *dst; /**< Destination data begin pointer */ + uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ + dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ + dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ + dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ + dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + type_func_t primary; /**< Use primary descriptor or alternate descriptor */ + type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */ + type_func_t high_prio; /**< High priority or default priority */ + type_func_t iterrupt; /**< Enable/disable interrupt */ + dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ + dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ + uint8_t channel; /**< Channel index */ +} dma_config_t; + +/** + * @brief DMA handle structure definition + */ +typedef struct +{ + DMA_TypeDef *perh; /**< DMA registers base address */ + dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ +} dma_handle_t; +/** + * @} + */ + +/** + * @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ +#define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_TRNG) +#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF) +#define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \ + ((x) == DMA_DATA_INC_HALFWORD) || \ + ((x) == DMA_DATA_INC_WORD) || \ + ((x) == DMA_DATA_INC_NONE)) +#define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ + ((x) == DMA_DATA_SIZE_HALFWORD) || \ + ((x) == DMA_DATA_SIZE_WORD)) +#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ + ((x) == DMA_CYCLE_CTRL_BASIC) || \ + ((x) == DMA_CYCLE_CTRL_AUTO) || \ + ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \ + ((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER)) +#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ + ((x) == DMA_R_POWER_2) || \ + ((x) == DMA_R_POWER_4) || \ + ((x) == DMA_R_POWER_8) || \ + ((x) == DMA_R_POWER_16) || \ + ((x) == DMA_R_POWER_32) || \ + ((x) == DMA_R_POWER_64) || \ + ((x) == DMA_R_POWER_128) || \ + ((x) == DMA_R_POWER_256) || \ + ((x) == DMA_R_POWER_512) || \ + ((x) == DMA_R_POWER_1024)) +#define IS_DMA(x) ((x) == DMA0) +#define IS_DMA_CHANNEL(x) ((x) <= 5) +#define IS_DMA_DATA_SIZE(x) ((x) <= 1024) +#define IS_DMA_IT_TYPE(x) (((x) <= 5) || ((x) == 31)) +/** + * @} + */ + +/** + * @addtogroup DMA_Public_Functions + * @{ + */ + +/** @addtogroup DMA_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void ald_dma_reset(DMA_TypeDef *DMAx); +extern void ald_dma_init(DMA_TypeDef *DMAx); +extern void ald_dma_config_struct(dma_config_t *p); +/** + * @} + */ + + +/** @addtogroup DMA_Public_Functions_Group2 + * @{ + */ +/* Configure DMA channel functions */ +extern void ald_dma_config_auto(dma_handle_t *hperh); +extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size); +extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, + uint16_t size, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_basic(dma_handle_t *hperh); +extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); +extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); +/** + * @} + */ + +/** @addtogroup DMA_Public_Functions_Group3 + * @{ + */ +/* DMA control functions */ +extern void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); +extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); +extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); +extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); +extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); +void ald_dma_irq_handler(void); +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__ALD_DMA_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..9a4a66b0686fcf6dd519a503252441dc25053be6 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -0,0 +1,129 @@ +/** + ********************************************************************************* + * + * @file ald_flash.h + * @brief Header file of FLASH driver + * + * @version V1.0 + * @date 20 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_FLASH_H__ +#define __ALD_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** + * @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#define FLASH_REG_UNLOCK() \ + do { \ + if (op_cmd == OP_FLASH) { \ + WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \ + WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \ + } \ + else { \ + WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \ + WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \ + } \ + } while (0) +#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) +#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) +#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) +#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) +#define FLASH_BASE_ADDR 0x00000000 +#define FLASH_PAGE_SIZE 1024UL +#define FLASH_WORD_SIZE 8UL +#define FLASH_TOTAL_SIZE 256UL +#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) +#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1) +#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE)) +#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0) +#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK)) +#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK) +#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK)) +#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK) +#define INFO_PAGE_SIZE 1024UL +#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1) +#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK)) + +#ifdef USE_FLASH_FIFO +#define FLASH_FIFO 1 +#else +#define FLASH_FIFO 0 +#endif +/** + * @} + */ + +/** @defgroup FLASH_Private_Types FLASH Private Types + * @{ + */ +typedef enum +{ + FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */ + FLASH_CMD_PE = 0x00005EA1, /**< Page erase */ + FLASH_CMD_WP = 0x00005DA2, /**< Word program */ + FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */ + FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */ +} flash_cmd_type; + +typedef enum +{ + OP_FLASH = 0, /**< Operate Pragram area */ + OP_INFO = 1, /**< Operate info area */ +} op_cmd_type; + +/** + * @} + */ +/** @addtogroup Flash_Private_Functions + * @{ + */ +ald_status_t flash_page_erase(uint32_t addr); +ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo); +/** + * @} + */ + +/** @addtogroup Flash_Public_Functions + * @{ + */ +ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len); +ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len); +ald_status_t ald_flash_erase(uint32_t addr, uint16_t len); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_FLASH_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..a8a2e9ebe0571b01ebf85abc75c43957e3f85381 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -0,0 +1,288 @@ +/** + ********************************************************************************* + * + * @file ald_gpio.h + * @brief Header file of GPIO module driver + * + * @version V1.0 + * @date 07 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_GPIO_H__ +#define __ALD_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** + * @defgroup GPIO_Public_Macros GPIO Public Macros + * @{ + */ +#define GPIO_PIN_0 (1U << 0) +#define GPIO_PIN_1 (1U << 1) +#define GPIO_PIN_2 (1U << 2) +#define GPIO_PIN_3 (1U << 3) +#define GPIO_PIN_4 (1U << 4) +#define GPIO_PIN_5 (1U << 5) +#define GPIO_PIN_6 (1U << 6) +#define GPIO_PIN_7 (1U << 7) +#define GPIO_PIN_8 (1U << 8) +#define GPIO_PIN_9 (1U << 9) +#define GPIO_PIN_10 (1U << 10) +#define GPIO_PIN_11 (1U << 11) +#define GPIO_PIN_12 (1U << 12) +#define GPIO_PIN_13 (1U << 13) +#define GPIO_PIN_14 (1U << 14) +#define GPIO_PIN_15 (1U << 15) +#define GPIO_PIN_ALL (0xFFFF) +/** + * @} + */ + +/** + * @defgroup GPIO_Public_Types GPIO Public Types + * @{ + */ + +/** + * @brief GPIO mode + */ +typedef enum +{ + GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */ + GPIO_MODE_INPUT = 0x1, /**< Input */ + GPIO_MODE_OUTPUT = 0x2, /**< Output */ +} gpio_mode_t; + +/** + * @brief GPIO open-drain or push-pull + */ +typedef enum +{ + GPIO_PUSH_PULL = 0x0, /**< Push-Pull */ + GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */ + GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */ +} gpio_odos_t; + +/** + * @brief GPIO push-up or push-down + */ +typedef enum +{ + GPIO_FLOATING = 0x0,/**< Floating */ + GPIO_PUSH_UP = 0x1,/**< Push-Up */ + GPIO_PUSH_DOWN = 0x2,/**< Push-Down */ + GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */ +} gpio_push_t; + +/** + * @brief GPIO output drive + */ +typedef enum +{ + GPIO_OUT_DRIVE_NORMAL = 0x0, /**< Normal current flow */ + GPIO_OUT_DRIVE_STRONG = 0x1, /**< Strong current flow */ +} gpio_out_drive_t; + +/** + * @brief GPIO filter + */ +typedef enum +{ + GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */ + GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */ +} gpio_filter_t; + +/** + * @brief GPIO type + */ +typedef enum +{ + GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */ + GPIO_TYPE_TTL = 0x1, /**< TTL Type */ +} gpio_type_t; + +/** + * @brief GPIO functions + */ +typedef enum +{ + GPIO_FUNC_0 = 0, /**< function #0 */ + GPIO_FUNC_1 = 1, /**< function #1 */ + GPIO_FUNC_2 = 2, /**< function #2 */ + GPIO_FUNC_3 = 3, /**< function #3 */ + GPIO_FUNC_4 = 4, /**< function #4 */ + GPIO_FUNC_5 = 5, /**< function #5 */ + GPIO_FUNC_6 = 6, /**< function #6 */ + GPIO_FUNC_7 = 7, /**< function #7 */ +} gpio_func_t; + + +/** + * @brief GPIO Init Structure definition + */ +typedef struct +{ + gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. + This parameter can be any value of @ref gpio_mode_t */ + gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. + This parameter can be a value of @ref gpio_odos_t */ + gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. + This parameter can be a value of @ref gpio_push_t */ + gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins. + This parameter can be a value of @ref gpio_out_drive_t */ + gpio_filter_t flt; /**< Specifies the input filter for the selected pins. + This parameter can be a value of @ref gpio_filter_t */ + gpio_type_t type; /**< Specifies the type for the selected pins. + This parameter can be a value of @ref gpio_type_t */ + gpio_func_t func; /**< Specifies the function for the selected pins. + This parameter can be a value of @ref gpio_func_t */ +} gpio_init_t; + +/** + * @brief EXTI trigger style + */ +typedef enum +{ + EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */ + EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */ + EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */ +} exti_trigger_style_t; + +/** + * @brief EXTI filter clock select + */ +typedef enum +{ + EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */ + EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */ +} exti_filter_clock_t; + +/** + * @brief EXTI Init Structure definition + */ +typedef struct +{ + type_func_t filter; /**< Enable filter. */ + exti_filter_clock_t cks; /**< Filter clock select. */ + uint8_t filter_time; /**< Filter duration */ +} exti_init_t; +/** + * @} + */ + +/** + * @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define PIN_MASK 0xFFFF +#define UNLOCK_KEY 0x55AA + +#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) +#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ + (GPIOx == GPIOB) || \ + (GPIOx == GPIOC) || \ + (GPIOx == GPIOD) || \ + (GPIOx == GPIOE) || \ + (GPIOx == GPIOF) || \ + (GPIOx == GPIOG) || \ + (GPIOx == GPIOH)) +#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \ + ((x) == GPIO_MODE_INPUT) || \ + ((x) == GPIO_MODE_OUTPUT)) +#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \ + ((x) == GPIO_OPEN_DRAIN) || \ + ((x) == GPIO_OPEN_SOURCE)) +#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \ + ((x) == GPIO_PUSH_UP) || \ + ((x) == GPIO_PUSH_DOWN) || \ + ((x) == GPIO_PUSH_UP_DOWN)) +#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \ + ((x) == GPIO_OUT_DRIVE_STRONG)) +#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \ + ((x) == GPIO_FILTER_ENABLE)) +#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \ + ((x) == GPIO_TYPE_CMOS)) +#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \ + ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \ + ((x) == EXTI_TRIGGER_BOTH_EDGE)) +#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \ + ((x) == EXTI_FILTER_CLOCK_32K)) +#define IS_GPIO_FUNC(x) ((x) <= 7) +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions + * @{ + */ + +/** @addtogroup GPIO_Public_Functions_Group1 + * @{ + */ +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init); +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_func_default(GPIO_TypeDef *GPIOx); +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group2 + * @{ + */ +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val); +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx); +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group3 + * @{ + */ +void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status); +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin); +void ald_gpio_exti_clear_flag_status(uint16_t pin); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_GPIO_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..a05aaf0ebb357a68831fa28efc094a41bef9601c --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -0,0 +1,534 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.h + * @brief Header file of I2C driver + * + * @version V1.0 + * @date 15 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_I2C_H__ +#define __ALD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_cmu.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Public_Types I2C Public Types + * @{ + */ +/** + * @brief I2C Error Code + */ +typedef enum +{ + I2C_ERROR_NONE = 0x0, /**< No error */ + I2C_ERROR_BERR = 0x1, /**< Berr error */ + I2C_ERROR_ARLO = 0x2, /**< Arlo error */ + I2C_ERROR_AF = 0x4, /**< Af error */ + I2C_ERROR_OVR = 0x8, /**< Ovr error */ + I2C_ERROR_DMA = 0x10, /**< Dma error */ + I2C_ERROR_TIMEOUT = 0x20, /**< Timeout error */ +} i2c_error_t; + +/** + * @brief I2C state structure definition + */ +typedef enum +{ + I2C_STATE_RESET = 0x0, /**< Peripheral is not yet Initialized */ + I2C_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + I2C_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + I2C_STATE_BUSY_TX = 0x3, /**< Data Transmission process is ongoing */ + I2C_STATE_BUSY_RX = 0x4, /**< Data Reception process is ongoing */ + I2C_STATE_TIMEOUT = 0x5, /**< timeout state */ + I2C_STATE_ERROR = 0x6, /**< Error */ +} i2c_state_t; + +/** + * @brief I2C Duty Cycle + */ +typedef enum +{ + I2C_DUTYCYCLE_2 = 0x0, /**< duty cycle is 2 */ + I2C_DUTYCYCLE_16_9 = 0x4000, /**< duty cycle is 16/9 */ +} i2c_duty_t; + +/** + * @brief I2C Addressing Mode + */ +typedef enum +{ + I2C_ADDR_7BIT = 0x1, /**< 7 bit address */ + I2C_ADDR_10BIT = 0x2, /**< 10 bit address */ +} i2c_addr_t; + +/** + * @brief I2C Dual Addressing Mode + */ +typedef enum +{ + I2C_DUALADDR_DISABLE = 0x0, /**< dual address is disable */ + I2C_DUALADDR_ENABLE = 0x1, /**< dual address is enable */ +} i2c_dual_addr_t; + +/** + * @brief I2C General Call Addressing mode + */ +typedef enum +{ + I2C_GENERALCALL_DISABLE = 0x0, /**< feneral call address is disable */ + I2C_GENERALCALL_ENABLE = 0x40, /**< feneral call address is enable */ +} i2c_general_addr_t; + +/** + * @brief I2C Nostretch Mode + */ +typedef enum +{ + I2C_NOSTRETCH_DISABLE = 0x0, /**< Nostretch disable */ + I2C_NOSTRETCH_ENABLE = 0x80, /**< Nostretch enable */ +} i2c_nostretch_t; + +/** + * @brief I2C Memory Address Size + */ +typedef enum +{ + I2C_MEMADD_SIZE_8BIT = 0x1, /**< 8 bit memory address size */ + I2C_MEMADD_SIZE_16BIT = 0x10 /**< 10 bit memory address size */ +} i2c_addr_size_t; + +/** + * @brief I2C Flag Definition + */ +typedef enum +{ + I2C_FLAG_SB = (1U << 0), + I2C_FLAG_ADDR = (1U << 1), + I2C_FLAG_BTF = (1U << 2), + I2C_FLAG_ADD10 = (1U << 3), + I2C_FLAG_STOPF = (1U << 4), + I2C_FLAG_RXNE = (1U << 6), + I2C_FLAG_TXE = (1U << 7), + I2C_FLAG_BERR = (1U << 8), + I2C_FLAG_ARLO = (1U << 9), + I2C_FLAG_AF = (1U << 10), + I2C_FLAG_OVR = (1U << 11), + I2C_FLAG_PECERR = (1U << 12), + I2C_FLAG_TIMEOUT = (1U << 14), + I2C_FLAG_SMBALERT = (1U << 15), + I2C_FLAG_MSL = (1U << 16), + I2C_FLAG_BUSY = (1U << 17), + I2C_FLAG_TRA = (1U << 18), + I2C_FLAG_GENCALL = (1U << 20), + I2C_FLAG_SMBDEFAULT = (1U << 21), + I2C_FLAG_SMBHOST = (1U << 22), + I2C_FLAG_DUALF = (1U << 23), +} i2c_flag_t; + +/** + * @brief I2C mode structure definition + */ +typedef enum +{ + I2C_MODE_NONE = 0x0, /**< No I2C communication on going */ + I2C_MODE_MASTER = 0x10, /**< I2C communication is in Master mode */ + I2C_MODE_SLAVE = 0x20, /**< I2C communication is in Slave mode */ + I2C_MODE_MEM = 0x40, /**< I2C communication is in Memory mode */ +} i2c_mode_t; + +/** + * @brief I2C Clock + */ +typedef enum +{ + I2C_STANDARD_MODE_MAX_CLK = 100000, /**< Standard mode clock */ + I2C_FAST_MODE_MAX_CLK = 400000, /**< Fast mode clock */ +} i2c_clock_t; + +/** + * @brief Interrupt Configuration Definition + */ +typedef enum +{ + I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */ + I2C_IT_EVT = (1U << 9), /**< Event interrupt */ + I2C_IT_ERR = (1U << 8), /**< Error interrupt */ +} i2c_interrupt_t; + +/** + * @brief I2C CON1 Register + */ +typedef enum +{ + I2C_CON1_PEN = (1U << 0), /**< PEN BIT */ + I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */ + I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */ + I2C_CON1_ARPEN = (1U << 4), /**< ARPEN BIT */ + I2C_CON1_PECEN = (1U << 5), /**< PECEN BIT */ + I2C_CON1_GCEN = (1U << 6), /**< GCEN BIT */ + I2C_CON1_DISCS = (1U << 7), /**< DISCS BIT */ + I2C_CON1_START = (1U << 8), /**< START BIT */ + I2C_CON1_STOP = (1U << 9), /**< STOP BIT */ + I2C_CON1_ACKEN = (1U << 10), /**< ACKEN BIT */ + I2C_CON1_POSAP = (1U << 11), /**< POSAP BIT */ + I2C_CON1_TRPEC = (1U << 12), /**< TRPEC BIT */ + I2C_CON1_ALARM = (1U << 13), /**< ALARM BIT */ + I2C_CON1_SRST = (1U << 15), /**< SRST BIT */ +} i2c_con1_t; + +/** + * @brief I2C CON2 Register + */ +typedef enum +{ + I2C_CON2_CLKF = 0x3F, /**< CLKF BITS */ + I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */ + I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */ + I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */ + I2C_CON2_CLKF_3 = (1U << 3), /**< CLKF_3 BIT */ + I2C_CON2_CLKF_4 = (1U << 4), /**< CLKF_4 BIT */ + I2C_CON2_CLKF_5 = (1U << 5), /**< CLKF_5 BIT */ + I2C_CON2_ERRIE = (1U << 8), /**< ERRIE BIT */ + I2C_CON2_EVTIE = (1U << 9), /**< EVTIE BIT */ + I2C_CON2_BUFIE = (1U << 10), /**< BUFIE BIT */ + I2C_CON2_DMAEN = (1U << 11), /**< DMAEN BIT */ + I2C_CON2_LDMA = (1U << 12), /**< LDMA BIT */ +} i2c_con2_t; + +/** + * @brief I2C ADDR1 Register + */ +typedef enum +{ + I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */ + I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */ + I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */ + I2C_ADDR1_ADDH3 = (1U << 3), /**< ADDH3 BIT */ + I2C_ADDR1_ADDH4 = (1U << 4), /**< ADDH4 BIT */ + I2C_ADDR1_ADDH5 = (1U << 5), /**< ADDH5 BIT */ + I2C_ADDR1_ADDH6 = (1U << 6), /**< ADDH6 BIT */ + I2C_ADDR1_ADDH7 = (1U << 7), /**< ADDH7 BIT */ + I2C_ADDR1_ADDH8 = (1U << 8), /**< ADDH8 BIT */ + I2C_ADDR1_ADDH9 = (1U << 9), /**< ADDH9 BIT */ + I2C_ADDR1_ADDTYPE = (1U << 15), /**< ADDTYPE BIT */ +} i2c_addr1_t; + +/** + * @brief I2C ADDR2 Register + */ +typedef enum +{ + I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */ + I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */ +} i2c_addr2_t; + +/** + * @brief I2C STAT1 Register + */ +typedef enum +{ + I2C_STAT1_SB = (1U << 0), /**< SB BIT */ + I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */ + I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */ + I2C_STAT1_SENDADD10 = (1U << 3), /**< SENDADD10 BIT */ + I2C_STAT1_DETSTP = (1U << 4), /**< DETSTP BIT */ + I2C_STAT1_RXBNE = (1U << 6), /**< RXBNE BIT */ + I2C_STAT1_TXBE = (1U << 7), /**< TXBE BIT */ + I2C_STAT1_BUSERR = (1U << 8), /**< BUSERR BIT */ + I2C_STAT1_LARB = (1U << 9), /**< LARB BIT */ + I2C_STAT1_ACKERR = (1U << 10), /**< ACKERR BIT */ + I2C_STAT1_ROUERR = (1U << 11), /**< ROUERR BIT */ + I2C_STAT1_PECERR = (1U << 12), /**< PECERR BIT */ + I2C_STAT1_SMBTO = (1U << 14), /**< SMBTO BIT */ + I2C_STAT1_SMBALARM = (1U << 15), /**< SMBALARM BIT */ +} i2c_stat1_t; + +/** + * @brief I2C STAT2 Register + */ +typedef enum +{ + I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */ + I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */ + I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */ + I2C_STAT2_RXGCF = (1U << 4), /**< RXGCF BIT */ + I2C_STAT2_SMBDEF = (1U << 5), /**< SMBDEF BIT */ + I2C_STAT2_SMBHH = (1U << 6), /**< SMBHH BIT */ + I2C_STAT2_DUALF = (1U << 7), /**< DMF BIT */ + I2C_STAT2_PECV = (1U << 8), /**< PECV BIT */ +} i2c_stat2_t; + +/** + * @brief I2C CKCFG Register + */ +typedef enum +{ + I2C_CKCFG_CLKSET = 0xFFF, /**< CLKSET BITS */ + I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */ + I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */ +} i2c_ckcfg_t; + +/** + * @brief I2C RT Register + */ +typedef enum +{ + I2C_RT_RISET = 0x3F, /**< RISET BITS */ +} i2c_trise_t; + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct +{ + uint32_t clk_speed; /**< Specifies the clock frequency */ + i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */ + uint32_t own_addr1; /**< Specifies the first device own address */ + i2c_addr_t addr_mode; /**< Specifies addressing mode */ + i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ + uint32_t own_addr2; /**< Specifies the second device own address */ + i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ + i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ +} i2c_init_t; + +/** + * @brief I2C handle Structure definition + */ +typedef struct i2c_handle_s +{ + I2C_TypeDef *perh; /**< I2C registers base address */ + i2c_init_t init; /**< I2C communication parameters */ + uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ + uint16_t xfer_size; /**< I2C transfer size */ + __IO uint16_t xfer_count; /**< I2C transfer counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ +#endif + lock_state_t lock; /**< I2C locking object */ + __IO i2c_state_t state; /**< I2C communication state */ + __IO i2c_mode_t mode; /**< I2C communication mode */ + __IO uint32_t error_code; /**< I2C Error code */ + + void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ + void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ + void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ + void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ + void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ + void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ + void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ +} i2c_handle_t; + +/** + * @} + */ + +/** @defgroup I2C_Public_Macro I2C Public Macros + * @{ + */ +#define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) +#define I2C_CLEAR_ADDRFLAG(x) \ + do { \ + __IO uint32_t tmpreg; \ + tmpreg = (x)->perh->STAT1; \ + tmpreg = (x)->perh->STAT2; \ + UNUSED(tmpreg); \ + } while (0) +#define __I2C_CLEAR_STOPFLAG(x) \ + do { \ + __IO uint32_t tmpreg; \ + tmpreg = (x)->perh->STAT1; \ + tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \ + UNUSED(tmpreg); \ + } while (0) +#define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) +#define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) +/** + * @} + */ + +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_I2C_TYPE(x) (((x) == I2C0) || \ + ((x) == I2C1)) +#define IS_I2C_ADDRESSING_MODE(x) (((x) == I2C_ADDR_7BIT) || \ + ((x) == I2C_ADDR_10BIT)) +#define IS_I2C_DUAL_ADDRESS(x) (((x) == I2C_DUALADDR_DISABLE) || \ + ((x) == I2C_DUALADDR_ENABLE)) +#define IS_I2C_GENERAL_CALL(x) (((x) == I2C_GENERALCALL_DISABLE) || \ + ((x) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_MEMADD_size(x) (((x) == I2C_MEMADD_SIZE_8BIT) || \ + ((x) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_NO_STRETCH(x) (((x) == I2C_NOSTRETCH_DISABLE) || \ + ((x) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_OWN_ADDRESS1(x) (((x) & (uint32_t)(0xFFFFFC00)) == 0) +#define IS_I2C_OWN_ADDRESS2(x) (((x) & (uint32_t)(0xFFFFFF01)) == 0) +#define IS_I2C_CLOCK_SPEED(x) (((x) > 0) && ((x) <= I2C_FAST_MODE_MAX_CLK)) +#define IS_I2C_DUTY_CYCLE(x) (((x) == I2C_DUTYCYCLE_2) || \ + ((x) == I2C_DUTYCYCLE_16_9)) +#define IS_I2C_IT_TYPE(x) (((x) == I2C_IT_BUF) || \ + ((x) == I2C_IT_EVT) || \ + ((x) == I2C_IT_ERR)) +#define IS_I2C_FLAG(x) (((x) == I2C_FLAG_SB) || \ + ((x) == I2C_FLAG_ADDR) || \ + ((x) == I2C_FLAG_BTF) || \ + ((x) == I2C_FLAG_ADD10) || \ + ((x) == I2C_FLAG_STOPF) || \ + ((x) == I2C_FLAG_RXNE) || \ + ((x) == I2C_FLAG_TXE) || \ + ((x) == I2C_FLAG_BERR) || \ + ((x) == I2C_FLAG_ARLO) || \ + ((x) == I2C_FLAG_AF) || \ + ((x) == I2C_FLAG_OVR) || \ + ((x) == I2C_FLAG_PECERR) || \ + ((x) == I2C_FLAG_TIMEOUT) || \ + ((x) == I2C_FLAG_SMBALERT) || \ + ((x) == I2C_FLAG_MSL) || \ + ((x) == I2C_FLAG_BUSY) || \ + ((x) == I2C_FLAG_TRA) || \ + ((x) == I2C_FLAG_GENCALL) || \ + ((x) == I2C_FLAG_SMBDEFAULT) || \ + ((x) == I2C_FLAG_SMBHOST) || \ + ((x) == I2C_FLAG_DUALF)) + +#define I2C_FREQ_RANGE(x) ((x) / 1000000) +#define I2C_RISE_TIME(x, u) (((u) <= I2C_STANDARD_MODE_MAX_CLK) ? ((x) + 1) :\ + ((((x) * 300) / 1000) + 1)) +#define I2C_SPEED_STANDARD(x, y) (((((x) / ((y) << 1)) & I2C_CKCFG_CLKSET) < 4) ? 4:\ + ((x) / ((y) << 1))) +#define I2C_SPEED_FAST(x, y, z) (((z) == I2C_DUTYCYCLE_2) ? ((x) / ((y) * 3)) :\ + (((x) / ((y) * 25)) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(x, y, z) (((y) <= 100000) ? (I2C_SPEED_STANDARD((x), (y))) :\ + ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \ + ((I2C_SPEED_FAST((x), (y), (z))) | I2C_CKCFG_CLKMOD)) +#define I2C_MEM_ADD_MSB(x) ((uint8_t)((uint16_t)(((uint16_t)((x) &\ + (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) +#define I2C_7BIT_ADD_WRITE(x) ((uint8_t)((x) & (~I2C_ADDR1_ADDH0))) +#define I2C_7BIT_ADD_READ(x) ((uint8_t)((x) | I2C_ADDR1_ADDH0)) +#define I2C_10BIT_ADDRESS(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) +#define I2C_10BIT_HEADER_WRITE(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ + (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) +#define I2C_10BIT_HEADER_READ(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ + (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions + * @{ + */ + +/** @addtogroup I2C_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_i2c_init(i2c_handle_t *hperh); +ald_status_t ald_i2c_reset(i2c_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group2 + * @{ + */ +/** Blocking mode: Polling */ +ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout); + +/** Non-Blocking mode: Interrupt */ +ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); +ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); +ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); +ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); + +#ifdef ALD_DMA +/** Non-Blocking mode: DMA */ +ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); +#endif +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group3 + * @{ + */ +i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh); +uint32_t ald_i2c_get_error(i2c_handle_t *hperh); +flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); +flag_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it); +void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group4 + * @{ + */ +void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state); +void ald_i2c_ev_irq_handler(i2c_handle_t *hperh); +void ald_i2c_er_irq_handler(i2c_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_I2C_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h similarity index 74% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h index 4109bed4b15b907d536d1d3790995f5927fc6b88..7a841e7c2a32601e2bc3445920576765863ed8dd 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -36,10 +36,10 @@ extern "C" { * @defgroup IAP_Private_Macros IAP Private Macros * @{ */ -#define IAP_WSP_ADDR 0x10000000 -#define IAP_PE_ADDR 0x10000004 -#define IAP_WP_ADDR 0x10000008 -#define IAP_DWP_ADDR 0x1000000c +#define IAP_WSP_ADDR 0x10000000 +#define IAP_PE_ADDR 0x10000004 +#define IAP_WP_ADDR 0x10000008 +#define IAP_DWP_ADDR 0x1000000c /** * @} */ @@ -58,10 +58,10 @@ typedef uint32_t (*IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t /** @addtogroup IAP_Public_Functions * @{ */ -uint32_t iap_erase_page(uint32_t addr); -uint32_t iap_program_word(uint32_t addr, uint32_t data); -uint32_t iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h); -uint32_t iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); +uint32_t ald_iap_erase_page(uint32_t addr); +uint32_t ald_iap_program_word(uint32_t addr, uint32_t data); +uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h); +uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h new file mode 100644 index 0000000000000000000000000000000000000000..a40bc998d119597634ffde2fca08300e5164b7f6 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -0,0 +1,692 @@ +/** + ********************************************************************************* + * + * @file ald_pis.h + * @brief Header file of PIS driver. + * + * @version V1.0 + * @date 27 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_PIS_H__ +#define __ALD_PIS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup PIS + * @{ + */ + +/** @defgroup PIS_Public_Types PIS Public Types + * @{ + */ +/** + * @brief Producer entry + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + PIS_NON = 0x0, /**< No async */ + PIS_GPIO_PIN0 = 0x10, /**< Pin0, level,support async */ + PIS_GPIO_PIN1 = 0x11, /**< Pin1, level,support async */ + PIS_GPIO_PIN2 = 0x12, /**< Pin2, level,support async */ + PIS_GPIO_PIN3 = 0x13, /**< Pin3, level,support async */ + PIS_GPIO_PIN4 = 0x14, /**< Pin4, level,support async */ + PIS_GPIO_PIN5 = 0x15, /**< Pin5, level,support async */ + PIS_GPIO_PIN6 = 0x16, /**< Pin6, level,support async */ + PIS_GPIO_PIN7 = 0x17, /**< Pin7, level,support async */ + PIS_GPIO_PIN8 = 0x18, /**< Pin8, level,support async */ + PIS_GPIO_PIN9 = 0x19, /**< Pin9, level,support async */ + PIS_GPIO_PIN10 = 0x1a, /**< Pin10, level,support async */ + PIS_GPIO_PIN11 = 0x1b, /**< Pin11, level,support async */ + PIS_GPIO_PIN12 = 0x1c, /**< Pin12, level,support async */ + PIS_GPIO_PIN13 = 0x1d, /**< Pin13, level,support async */ + PIS_GPIO_PIN14 = 0x1e, /**< Pin14, level,support async */ + PIS_GPIO_PIN15 = 0x1f, /**< Pin15, level,support async */ + PIS_ACMP_OUT0 = 0x30, /**< Acmp0 output, level,support async */ + PIS_ACMP_OUT1 = 0x31, /**< Acmp1 output, level,support async */ + PIS_DAC0_CH0 = 0x40, /**< Dac0 channel 0, pclk2 pulse,support async */ + PIS_DAC0_CH1 = 0x41, /**< Dac0 channel 1, pclk2 pulse,support async */ + PIS_ADC0_INJECT = 0x60, /**< Adc0 inject, pclk2 pulse,support async */ + PIS_ADC0_REGULAT = 0x61, /**< Adc0 regulat, pclk2 pulse,support async */ + PIS_ADC0_WINDOW = 0x62, /**< Adc0 window, no have */ + PIS_LVD = 0x70, /**< Lvd, level,support async */ + PIS_UART0_ASY_SEND = 0x80, /**< Uart0 asy send, pulse,support async */ + PIS_UART0_ASY_RECV = 0x81, /**< Uart0 asy recv, pulse,support async */ + PIS_UART0_IRDAOUT = 0x82, /**< Uart0 irdaout, level,support async */ + PIS_UART0_RTSOUT = 0x83, /**< Uart0 rtsout, level,support async */ + PIS_UART0_TXOUT = 0x84, /**< Uart0 txout, level,support async */ + PIS_UART0_SYN_SEND = 0x85, /**< Uart0 syn send, pulse,support async */ + PIS_UART0_SYN_RECV = 0x86, /**< Uart0 syn recv, pulse,support async */ + PIS_UART1_ASY_SEND = 0x90, /**< Uart1 asy send, pulse,support async */ + PIS_UART1_ASY_RECV = 0x91, /**< Uart1 asy recv, pulse,support async */ + PIS_UART1_IRDA = 0x92, /**< Uart1 irdaout, level,support async */ + PIS_UART1_RTS = 0x93, /**< Uart1 rtsout, level,support async */ + PIS_UART1_TXOUT = 0x94, /**< Uart1 txout, level,support async */ + PIS_UART1_SYN_SEND = 0x95, /**< Uart1 syn send, pulse,support async */ + PIS_UART1_SYN_RECV = 0x96, /**< Uart1 syn recv, pulse,support async */ + PIS_UART2_ASY_SEND = 0xa0, /**< Uart2 asy send, pulse,support async */ + PIS_UART2_ASY_RECV = 0xa1, /**< Uart2 asy recv, pulse,support async */ + PIS_UART2_IRDA = 0xa2, /**< Uart2 irdaout, level,support async */ + PIS_UART2_RTS = 0xa3, /**< Uart2 rtsout, level,support async */ + PIS_UART2_TXOUT = 0xa4, /**< Uart2 txout, level,support async */ + PIS_UART2_SYN_SEND = 0xa5, /**< Uart2 syn send, pulse,support async */ + PIS_UART2_SYN_RECV = 0xa6, /**< Uart2 syn recv, pulse,support async */ + PIS_UART3_ASY_SEND = 0xb1, /**< Uart3 asy send, pulse,support async */ + PIS_UART3_ASY_RECV = 0xb2, /**< Uart3 asy recv, pulse,support async */ + PIS_UART3_IRDA = 0xb3, /**< Uart3 irdaout, level,support async */ + PIS_UART3_RTS = 0xb4, /**< Uart3 rtsout, level,support async */ + PIS_UART3_TXOUT = 0xb5, /**< Uart3 txout, level,support async */ + PIS_UART3_SYN_SEND = 0xb6, /**< Uart3 syn send, pulse,support async */ + PIS_UART3_SYN_RECV = 0xb7, /**< Uart3 syn recv, pulse,support async */ + PIS_EUART0_RECV = 0xc0, /**< Euart0 recv, plck1 pulse */ + PIS_EUART0_SEND = 0xc1, /**< Euart0 send, plck1 pulse */ + PIS_EUART0_TXOUT = 0xc2, /**< Euart0 txout, plck1 level */ + PIS_EUART1_RECV = 0xd0, /**< Euart1 recv, plck1 pulse */ + PIS_EUART1_SEND = 0xd1, /**< Euart1 send, plck1 pulse */ + PIS_EUART1_TXOUT = 0xd2, /**< Euart1 txout, plck1 level */ + PIS_SPI0_RECV = 0xe0, /**< Spi0 recv, plck1 pulse */ + PIS_SPI0_SEND = 0xe1, /**< Spi0 send, plck1 pulse */ + PIS_SPI0_NE = 0xe2, /**< Spi0 ne, plck1 level */ + PIS_SPI1_RECV = 0xf0, /**< Spi1 recv, plck1 pulse */ + PIS_SPI1_SEND = 0xf1, /**< Spi1 send, plck1 pulse */ + PIS_SPI1_NE = 0xf2, /**< Spi1 ne, plck1 level */ + PIS_I2C0_RECV = 0x100, /**< I2c0 recv, plck1 level */ + PIS_I2C0_SEND = 0x101, /**< I2c0 send, plck1 level */ + PIS_I2C1_RECV = 0x110, /**< I2c1 recv, plck1 level */ + PIS_I2C1_SEND = 0x111, /**< I2c1 send, plck1 level */ + PIS_TIMER0_UPDATA = 0x120, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER0_TRIG = 0x121, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER0_INPUT = 0x122, /**< Timer0 input, plck1 pulse */ + PIS_TIMER0_OUTPUT = 0x123, /**< Timer0 output, plck1 pulse */ + PIS_TIMER1_UPDATA = 0x130, /**< Timer1 updata, plck1 pulse */ + PIS_TIMER1_TRIG = 0x131, /**< Timer1 trig, plck1 pulse */ + PIS_TIMER1_INPUT = 0x132, /**< Timer1 input, plck1 pulse */ + PIS_TIMER1_OUTPUT = 0x133, /**< Timer1 output, plck1 pulse */ + PIS_TIMER2_UPDATA = 0x140, /**< Timer2 updata, plck1 pulse */ + PIS_TIMER2_TRIG = 0x141, /**< Timer2 trig, plck1 pulse */ + PIS_TIMER2_INPUT = 0x142, /**< Timer2 input, plck1 pulse */ + PIS_TIMER2_OUTPUT = 0x143, /**< Timer2 output, plck1 pulse */ + PIS_TIMER3_UPDATA = 0x150, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER3_TRIG = 0x151, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER3_INPUT = 0x152, /**< Timer0 input, plck1 pulse */ + PIS_TIMER3_OUTPUT = 0x153, /**< Timer0 output, plck1 pulse */ + PIS_RTC_CLOCK = 0x160, /**< Rtc clock, pulse,support async */ + PIS_RTC_ALARM = 0x161, /**< Rtc alarm, pulse,support async */ + PIS_LPTIM0_SYN_UPDATA = 0x170, /**< Lptimer0 syn updata, pulse,support async */ + PIS_LPTIM0_ASY_UPDATA = 0x171, /**< Lptimer0 asy updata, pulse,support async */ + PIS_LPUART0_ASY_RECV = 0x180, /**< Lpuart0 asy recv, pulse,support async */ + PIS_LPUART0_ASY_SEND = 0x181, /**< Lpuart0 asy send, pulse,support async */ + PIS_LPUART0_SYN_RECV = 0x182, /**< Lpuart0 syn recv, pulse,support async */ + PIS_LPUART0_SYN_SEND = 0x183, /**< Lpuart0 syn recv, pulse,support async */ + PIS_DMA = 0x190, /**< Dma, pulse,support async */ + PIS_ADC1_INJECT = 0x1a0, /**< Adc1 inject, pclk2 pulse,support async */ + PIS_ADC1_REGULAT = 0x1a1, /**< Adc1 regulat, pclk2 pulse,support async */ + PIS_ADC1_WINDOW = 0x1a2, /**< Adc1 window, no have */ +} pis_src_t; + +/** + * @brief Consumer entry + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + PIS_CH0_TIMER0_BRKIN = 0x0400, /**< Timer0 brkin */ + PIS_CH0_SPI1_CLK = 0x0F10, /**< Spi1 clk */ + PIS_CH0_LPTIM0_EXT0 = 0x0030, /**< Lptimer0 ext0 */ + PIS_CH0_ADC1_NORMAL = 0x0030, /**< Adc1 normal */ + PIS_CH1_TIMER0_CH1IN = 0x0001, /**< Timer0 ch1in */ + PIS_CH1_TIMER2_CH1IN = 0x1001, /**< Timer2 ch1in */ + PIS_CH1_TIMER3_CH1IN = 0x1801, /**< Timer3 ch1in */ + PIS_CH1_LPTIM0_EXT1 = 0x0031, /**< Lptime0 ext1 */ + PIS_CH1_UART0_RX_IRDA = 0x0011, /**< Uart0 rx irda */ + PIS_CH1_ADC1_INSERT = 0x0031, /**< Adc1 insert */ + PIS_CH2_TIMER0_CH2IN = 0x0102, /**< Timer0 ch2in */ + PIS_CH2_TIMER2_CH2IN = 0x1102, /**< Timer2 ch2in */ + PIS_CH2_TIMER3_CH2IN = 0x1902, /**< Timer3 ch2in */ + PIS_CH2_LPTIM0_EXT2 = 0x0032, /**< Lptime0 ext2 */ + PIS_CH2_UART1_RX_IRDA = 0x0112, /**< Uart1 rx irda */ + PIS_CH3_TIMER0_CH3IN = 0x0203, /**< Timer0 ch3in */ + PIS_CH3_LPTIM0_EXT3 = 0x0033, /**< Lptime0 ext3 */ + PIS_CH3_UART2_RX_IRDA = 0x0213, /**< Uart2 rx irda */ + PIS_CH4_TIMER0_CH4IN = 0x0004, /**< Timer0 ch4in */ + PIS_CH4_TIMER0_ITR0 = 0x0034, /**< Timer0 itr0 */ + PIS_CH4_TIMER2_ITR0 = 0x0034, /**< Timer2 itr0 */ + PIS_CH4_TIMER3_ITR0 = 0x0034, /**< Timer3 itr0 */ + PIS_CH4_LPTIM0_EXT4 = 0x0434, /**< Lptime0 ext4 */ + PIS_CH4_UART3_RX_IRDA = 0x0314, /**< Uart3 rx irda */ + PIS_CH5_SPI0_RX = 0x0C15, /**< Spi0 rx */ + PIS_CH5_LPTIM0_EXT5 = 0x0035, /**< Lptime0 ext5 */ + PIS_CH5_EUART0_RX = 0x0615, /**< Euart0 rx */ + PIS_CH5_TIMER0_ITR1 = 0x0035, /**< Timer0 itr1 */ + PIS_CH5_TIMER2_ITR1 = 0x0035, /**< Timer2 itr1 */ + PIS_CH5_TIMER3_ITR1 = 0x0035, /**< Timer3 itr1 */ + PIS_CH6_SPI0_CLK = 0x0D16, /**< Spi0 clk */ + PIS_CH6_ADC0_NORMAL = 0x0036, /**< Adc0 normal */ + PIS_CH6_LPTIM0_EXT6 = 0x0036, /**< Lptime0 ext6 */ + PIS_CH6_EUART1_RX = 0x0716, /**< Euart1 rx */ + PIS_CH6_TIMER0_ITR2 = 0x0036, /**< Timer0 itr2 */ + PIS_CH6_TIMER2_ITR2 = 0x0036, /**< Timer2 itr2 */ + PIS_CH6_TIMER3_ITR2 = 0x0036, /**< Timer3 itr2 */ + PIS_CH6_DAC_CH1 = 0x0036, /**< Dac channel 1 */ + PIS_CH7_SPI1_RX = 0x0E17, /**< Spi1 rx */ + PIS_CH7_ADC0_INSERT = 0x0037, /**< Adc0 insert */ + PIS_CH7_LPTIM0_EXT7 = 0x0037, /**< Lptime0 ext7 */ + PIS_CH7_DMA = 0x0037, /**< Dma */ + PIS_CH7_TIMER0_ITR3 = 0x0037, /**< Timer0 itr3 */ + PIS_CH7_TIMER2_ITR3 = 0x0037, /**< Timer2 itr3 */ + PIS_CH7_TIMER3_ITR3 = 0x0037, /**< Timer3 itr3 */ + PIS_CH7_LPUART_RX = 0x0817, /**< Lpuart rx */ + PIS_CH7_DAC_CH0 = 0x0037, /**< Dac channel 0 */ +} pis_trig_t; + +/** + * @brief Clock select + */ +typedef enum +{ + PIS_CLK_PCLK1 = 0, /**< Pclock1 */ + PIS_CLK_PCLK2 = 1, /**< Pclock2 */ + PIS_CLK_SYS = 2, /**< Sys clock */ + PIS_CLK_LP = 3, /**< Low power clock */ +} pis_clock_t; + +/** + * @brief Level select + */ +typedef enum +{ + PIS_EDGE_NONE = 0, /**< None edge */ + PIS_EDGE_UP = 1, /**< Up edge */ + PIS_EDGE_DOWN = 2, /**< Down edge */ + PIS_EDGE_UP_DOWN = 3, /**< Up and down edge */ +} pis_edge_t; + +/** + * @brief Output style + */ +typedef enum +{ + PIS_OUT_LEVEL = 0, /**< Level */ + PIS_OUT_PULSE = 1, /**< Pulse */ +} pis_output_t; +/** + * @brief Sync select + */ +typedef enum +{ + PIS_SYN_DIRECT = 0, /**< Direct */ + PIS_SYN_ASY_PCLK1 = 1, /**< Asy pclk1 */ + PIS_SYN_ASY_PCLK2 = 2, /**< Asy pclk2 */ + PIS_SYN_ASY_PCLK = 3, /**< Asy pclk */ + PIS_SYN_PCLK2_PCLK1 = 4, /**< Pclk2 to pclk1 */ + PIS_SYN_PCLK1_PCLK2 = 5, /**< Pclk1 to pclk2 */ + PIS_SYN_PCLK12_SYS = 6, /**< Pclk1 or pclk2 to sysclk */ +} pis_syncsel_t; + +/** + * @brief Pis channel + */ +typedef enum +{ + PIS_CH_0 = 0, /**< Channel 0 */ + PIS_CH_1 = 1, /**< Channel 1 */ + PIS_CH_2 = 2, /**< Channel 2 */ + PIS_CH_3 = 3, /**< Channel 3 */ + PIS_CH_4 = 4, /**< Channel 4 */ + PIS_CH_5 = 5, /**< Channel 5 */ + PIS_CH_6 = 6, /**< Channel 6 */ + PIS_CH_7 = 7, /**< Channel 7 */ +} pis_ch_t; + +/** + * @brief Pis output channel + */ +typedef enum +{ + PIS_OUT_CH_0 = 0, /**< Channel 0 */ + PIS_OUT_CH_1 = 1, /**< Channel 1 */ + PIS_OUT_CH_2 = 2, /**< Channel 2 */ + PIS_OUT_CH_3 = 3, /**< Channel 3 */ +} pis_out_ch_t; + +/** + * @brief Indirect value,no care of it. + */ +typedef enum +{ + PIS_CON_0 = 0, /**< Con 0 */ + PIS_CON_1 = 1, /**< Con 1 */ + PIS_CON_NONE = 2, /**< None */ +} pis_con_t; + +/** + * @brief Indirect value,no care of it. + */ +typedef union +{ + struct + { + uint8_t ch : 4; /**< Channel */ + uint8_t con : 4; /**< Contorl */ + uint8_t shift : 8; /**< Shift */ + }; + uint16_t HalfWord; +} pis_divide_t; + +/** + * @brief PIS state structures definition + */ +typedef enum +{ + PIS_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + PIS_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + PIS_STATE_BUSY = 0x02, /**< An internal process is ongoing */ + PIS_STATE_TIMEOUT = 0x03, /**< Timeout state */ + PIS_STATE_ERROR = 0x04, /**< Error */ +} pis_state_t; + +/** + * @brief PIS modulate target + */ +typedef enum +{ + PIS_UART0_TX = 0, /**< Modulate uart0 tx */ + PIS_UART1_TX = 1, /**< Modulate uart1 tx */ + PIS_UART2_TX = 2, /**< Modulate uart2 tx */ + PIS_UART3_TX = 3, /**< Modulate uart3 tx */ + PIS_LPUART0_TX = 4, /**< Modulate lpuart0 tx */ +} pis_modu_targ_t; + +/** + * @brief PIS modulate level + */ +typedef enum +{ + PIS_LOW_LEVEL = 0, /**< Modulate low level */ + PIS_HIGH_LEVEL = 1, /**< Modulate high level */ +} pis_modu_level_t; + +/** + * @brief PIS modulate source + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + PIS_SRC_NONE = 0, /**< Stop modulate */ + PIS_SRC_TIMER0 = 1, /**< Modulate source is TIMER0 */ + PIS_SRC_TIMER1 = 2, /**< Modulate source is TIMER1 */ + PIS_SRC_TIMER2 = 3, /**< Modulate source is TIMER2 */ + PIS_SRC_TIMER3 = 4, /**< Modulate source is TIMER3 */ + PIS_SRC_TIMER6 = 5, /**< Modulate source is TIMER6 */ + PIS_SRC_TIMER7 = 6, /**< Modulate source is TIMER7 */ + PIS_SRC_LPTIM0 = 7, /**< Modulate source is LPTIM0 */ + PIS_SRC_BUZ = 8, /**< Modulate source is buz */ +} pis_modu_src_t; + +/** + * @brief PIS modulate channel + */ +typedef enum +{ + PIS_TIMER_CH1 = 0, /**< Src is TIMERx and choose channel 1 */ + PIS_TIMER_CH2 = 1, /**< Src is TIMERx and choose channel 2 */ + PIS_TIMER_CH3 = 2, /**< Src is TIMERx and choose channel 3 */ + PIS_TIMER_CH4 = 3, /**< Src is TIMERx and choose channel 4 */ +} pis_modu_channel_t; + +/** + * @brief PIS init structure definition + */ +typedef struct +{ + pis_src_t producer_src; /**< Producer entry */ + pis_clock_t producer_clk; /**< Producer module clock */ + pis_edge_t producer_edge; /**< Producer module pin output edge */ + pis_trig_t consumer_trig; /**< Consumer entry */ + pis_clock_t consumer_clk; /**< Consumer clock */ +} pis_init_t; + +/** + * @brief PIS modulate config structure definition + */ +typedef struct +{ + pis_modu_targ_t target; /**< Modulate target */ + pis_modu_level_t level; /**< Modulate level */ + pis_modu_src_t src; /**< Modulate src */ + pis_modu_channel_t channel; /**< Modulate channel */ +} pis_modulate_config_t; + +/** + * @brief PIS Handle Structure definition + */ +typedef struct pis_handle_s +{ + PIS_TypeDef *perh; /**< Register base address */ + pis_init_t init; /**< PIS required parameters */ + pis_ch_t consumer_ch; /**< Indirect value, no care of it */ + pis_con_t consumer_con; /**< Indirect value, no care of it */ + uint8_t consumer_pos; /**< Indirect value, no care of it */ + uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ + lock_state_t lock; /**< Locking object */ + pis_state_t state; /**< PIS operation state */ +} pis_handle_t; +/** + * @} + */ + + +/** @defgroup PIS_Private_Macros PIS Private Macros + * @{ + */ +#define IS_PIS(x) (((x) == PIS)) +#define IS_PIS_SRC(x) (((x) == PIS_NON) || \ + ((x) == PIS_GPIO_PIN0) || \ + ((x) == PIS_GPIO_PIN1) || \ + ((x) == PIS_GPIO_PIN2) || \ + ((x) == PIS_GPIO_PIN3) || \ + ((x) == PIS_GPIO_PIN4) || \ + ((x) == PIS_GPIO_PIN5) || \ + ((x) == PIS_GPIO_PIN6) || \ + ((x) == PIS_GPIO_PIN7) || \ + ((x) == PIS_GPIO_PIN8) || \ + ((x) == PIS_GPIO_PIN9) || \ + ((x) == PIS_GPIO_PIN10) || \ + ((x) == PIS_GPIO_PIN11) || \ + ((x) == PIS_GPIO_PIN12) || \ + ((x) == PIS_GPIO_PIN13) || \ + ((x) == PIS_GPIO_PIN14) || \ + ((x) == PIS_GPIO_PIN15) || \ + ((x) == PIS_ACMP_OUT0) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_DAC0_CH1) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_ADC0_INJECT) || \ + ((x) == PIS_ADC0_REGULAT) || \ + ((x) == PIS_ADC0_WINDOW) || \ + ((x) == PIS_LVD) || \ + ((x) == PIS_UART0_ASY_SEND) || \ + ((x) == PIS_UART0_ASY_RECV) || \ + ((x) == PIS_UART0_IRDAOUT) || \ + ((x) == PIS_UART0_RTSOUT) || \ + ((x) == PIS_UART0_TXOUT) || \ + ((x) == PIS_UART0_SYN_SEND) || \ + ((x) == PIS_UART0_SYN_RECV) || \ + ((x) == PIS_UART1_ASY_SEND) || \ + ((x) == PIS_UART1_ASY_RECV) || \ + ((x) == PIS_UART1_IRDA) || \ + ((x) == PIS_UART1_RTS) || \ + ((x) == PIS_UART1_TXOUT) || \ + ((x) == PIS_UART1_SYN_SEND) || \ + ((x) == PIS_UART1_SYN_RECV) || \ + ((x) == PIS_UART2_ASY_SEND) || \ + ((x) == PIS_UART2_ASY_RECV) || \ + ((x) == PIS_UART2_IRDA) || \ + ((x) == PIS_UART2_RTS) || \ + ((x) == PIS_UART2_TXOUT) || \ + ((x) == PIS_UART2_SYN_SEND) || \ + ((x) == PIS_UART2_SYN_RECV) || \ + ((x) == PIS_UART3_ASY_SEND) || \ + ((x) == PIS_UART3_ASY_RECV) || \ + ((x) == PIS_UART3_IRDA) || \ + ((x) == PIS_UART3_RTS) || \ + ((x) == PIS_UART3_TXOUT) || \ + ((x) == PIS_UART3_SYN_SEND) || \ + ((x) == PIS_UART3_SYN_RECV) || \ + ((x) == PIS_EUART0_RECV) || \ + ((x) == PIS_EUART0_SEND) || \ + ((x) == PIS_EUART0_TXOUT) || \ + ((x) == PIS_EUART1_RECV) || \ + ((x) == PIS_EUART1_SEND) || \ + ((x) == PIS_EUART1_TXOUT) || \ + ((x) == PIS_SPI0_RECV) || \ + ((x) == PIS_SPI0_SEND) || \ + ((x) == PIS_SPI0_NE) || \ + ((x) == PIS_SPI1_RECV) || \ + ((x) == PIS_SPI1_SEND) || \ + ((x) == PIS_SPI1_NE) || \ + ((x) == PIS_I2C0_RECV) || \ + ((x) == PIS_I2C0_SEND) || \ + ((x) == PIS_I2C1_RECV) || \ + ((x) == PIS_I2C1_SEND) || \ + ((x) == PIS_TIMER0_UPDATA) || \ + ((x) == PIS_TIMER0_TRIG) || \ + ((x) == PIS_TIMER0_INPUT) || \ + ((x) == PIS_TIMER0_OUTPUT) || \ + ((x) == PIS_TIMER1_UPDATA) || \ + ((x) == PIS_TIMER1_TRIG) || \ + ((x) == PIS_TIMER1_INPUT) || \ + ((x) == PIS_TIMER1_OUTPUT) || \ + ((x) == PIS_TIMER2_UPDATA) || \ + ((x) == PIS_TIMER2_TRIG) || \ + ((x) == PIS_TIMER2_INPUT) || \ + ((x) == PIS_TIMER2_OUTPUT) || \ + ((x) == PIS_TIMER3_UPDATA) || \ + ((x) == PIS_TIMER3_TRIG) || \ + ((x) == PIS_TIMER3_INPUT) || \ + ((x) == PIS_TIMER3_OUTPUT) || \ + ((x) == PIS_RTC_CLOCK) || \ + ((x) == PIS_RTC_ALARM) || \ + ((x) == PIS_LPTIM0_SYN_UPDATA) || \ + ((x) == PIS_LPTIM0_ASY_UPDATA) || \ + ((x) == PIS_LPUART0_ASY_RECV) || \ + ((x) == PIS_LPUART0_ASY_SEND) || \ + ((x) == PIS_LPUART0_SYN_RECV) || \ + ((x) == PIS_LPUART0_SYN_SEND) || \ + ((x) == PIS_DMA) || \ + ((x) == PIS_ADC1_INJECT) || \ + ((x) == PIS_ADC1_REGULAT) || \ + ((x) == PIS_ADC1_WINDOW)) +#define IS_PIS_TRIG(x) (((x) == PIS_CH0_TIMER0_BRKIN) || \ + ((x) == PIS_CH0_SPI1_CLK) || \ + ((x) == PIS_CH0_LPTIM0_EXT0) || \ + ((x) == PIS_CH0_ADC1_NORMAL) || \ + ((x) == PIS_CH1_TIMER0_CH1IN) || \ + ((x) == PIS_CH1_TIMER2_CH1IN) || \ + ((x) == PIS_CH1_TIMER3_CH1IN) || \ + ((x) == PIS_CH1_UART0_RX_IRDA) || \ + ((x) == PIS_CH1_LPTIM0_EXT1) || \ + ((x) == PIS_CH1_ADC1_INSERT) || \ + ((x) == PIS_CH2_TIMER0_CH2IN) || \ + ((x) == PIS_CH2_TIMER2_CH2IN) || \ + ((x) == PIS_CH2_TIMER3_CH2IN) || \ + ((x) == PIS_CH2_LPTIM0_EXT2) || \ + ((x) == PIS_CH2_UART1_RX_IRDA) || \ + ((x) == PIS_CH3_TIMER0_CH3IN) || \ + ((x) == PIS_CH3_LPTIM0_EXT3) || \ + ((x) == PIS_CH3_UART2_RX_IRDA) || \ + ((x) == PIS_CH4_TIMER0_CH4IN) || \ + ((x) == PIS_CH4_TIMER0_ITR0) || \ + ((x) == PIS_CH4_TIMER2_ITR0) || \ + ((x) == PIS_CH4_TIMER3_ITR0) || \ + ((x) == PIS_CH4_LPTIM0_EXT4) || \ + ((x) == PIS_CH4_UART3_RX_IRDA) || \ + ((x) == PIS_CH5_SPI0_RX) || \ + ((x) == PIS_CH5_LPTIM0_EXT5) || \ + ((x) == PIS_CH5_EUART0_RX) || \ + ((x) == PIS_CH5_TIMER0_ITR1) || \ + ((x) == PIS_CH5_TIMER2_ITR1) || \ + ((x) == PIS_CH5_TIMER3_ITR1) || \ + ((x) == PIS_CH6_SPI0_CLK) || \ + ((x) == PIS_CH6_ADC0_NORMAL) || \ + ((x) == PIS_CH6_LPTIM0_EXT6) || \ + ((x) == PIS_CH6_EUART1_RX) || \ + ((x) == PIS_CH6_TIMER0_ITR2) || \ + ((x) == PIS_CH6_TIMER2_ITR2) || \ + ((x) == PIS_CH6_TIMER3_ITR2) || \ + ((x) == PIS_CH6_DAC_CH1) || \ + ((x) == PIS_CH7_SPI1_RX) || \ + ((x) == PIS_CH7_ADC0_INSERT) || \ + ((x) == PIS_CH7_LPTIM0_EXT7) || \ + ((x) == PIS_CH7_DMA) || \ + ((x) == PIS_CH7_TIMER0_ITR3) || \ + ((x) == PIS_CH7_TIMER2_ITR3) || \ + ((x) == PIS_CH7_TIMER3_ITR3) || \ + ((x) == PIS_CH7_DAC_CH0) || \ + ((x) == PIS_CH7_LPUART_RX)) +#define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \ + ((x) == PIS_CLK_PCLK2) || \ + ((x) == PIS_CLK_SYS) || \ + ((x) == PIS_CLK_LP)) +#define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \ + ((x) == PIS_EDGE_UP) || \ + ((x) == PIS_EDGE_DOWN) || \ + ((x) == PIS_EDGE_UP_DOWN)) +#define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \ + ((x) == PIS_OUT_PULSE)) +#define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \ + ((x) == PIS_OUT_CH_1) || \ + ((x) == PIS_OUT_CH_2) || \ + ((x) == PIS_OUT_CH_3)) +#define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \ + ((x) == PIS_UART1_TX) || \ + ((x) == PIS_UART2_TX) || \ + ((x) == PIS_UART3_TX) || \ + ((x) == PIS_LPUART0_TX)) +#define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \ + ((x) == PIS_HIGH_LEVEL)) +#define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \ + ((x) == PIS_SRC_TIMER0) || \ + ((x) == PIS_SRC_TIMER1) || \ + ((x) == PIS_SRC_TIMER2) || \ + ((x) == PIS_SRC_TIMER3) || \ + ((x) == PIS_SRC_TIMER6) || \ + ((x) == PIS_SRC_TIMER7) || \ + ((x) == PIS_SRC_LPTIM0) || \ + ((x) == PIS_SRC_BUZ)) +#define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \ + ((x) == PIS_TIMER_CH2) || \ + ((x) == PIS_TIMER_CH3) || \ + ((x) == PIS_TIMER_CH4)) +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions + * @{ + */ + +/** @addtogroup PIS_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_pis_create(pis_handle_t *hperh); +ald_status_t ald_pis_destroy(pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch); +ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group3 + * @{ + */ +pis_state_t ald_pis_get_state(pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group4 + * @{ + */ +ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_PIS_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h new file mode 100644 index 0000000000000000000000000000000000000000..85c962657879017c50feae5ab7b9380af454b5c7 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -0,0 +1,211 @@ +/** + ********************************************************************************* + * + * @file ald_pmu.h + * @brief Header file of PMU module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_PMU_H__ +#define __ALD_PMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_syscfg.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup PMU + * @{ + */ + +/** @defgroup PMU_Public_Macros PMU Public Macros + * @{ + */ +#define PMU_SRAM0_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \ + SYSCFG_LOCK(); \ + } while (0) +#define PMU_SRAM0_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\ + SYSCFG_LOCK(); \ + } while (0) +#define PMU_SRAM1_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \ + SYSCFG_LOCK(); \ + } while (0) +#define PMU_SRAM1_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\ + SYSCFG_LOCK(); \ + } while (0) +#define PMU_BXCAN_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define PMU_BXCAN_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) + +#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) +/** + * @} + */ + + +/** @defgroup PMU_Public_Types PMU Public Types + * @{ + */ +/** + * @brief Low power mode + */ +typedef enum +{ + PMU_LP_STOP1 = 0x0, /**< Stop1 */ + PMU_LP_STOP2 = 0x1, /**< Stop2 */ +} pmu_lp_mode_t; + +typedef enum +{ + PMU_SR_WUF = (1U << 0), +} pmu_status_t; + +/** + * @brief LVD voltage select + */ +typedef enum +{ + PMU_LVD_VOL_SEL_2_0 = 0x0, /**< 2.0V ~ 2.05V */ + PMU_LVD_VOL_SEL_2_1 = 0x1, /**< 2.1V ~ 2.15V */ + PMU_LVD_VOL_SEL_2_2 = 0x2, /**< 2.2V ~ 2.25V */ + PMU_LVD_VOL_SEL_2_4 = 0x3, /**< 2.4V ~ 2.45V */ + PMU_LVD_VOL_SEL_2_6 = 0x4, /**< 2.6V ~ 2.65V */ + PMU_LVD_VOL_SEL_2_8 = 0x5, /**< 2.8V ~ 2.85V */ + PMU_LVD_VOL_SEL_3_0 = 0x6, /**< 3.0V ~ 3.05V */ + PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */ + PMU_LVD_VOL_SEL_4_0 = 0x8, /**< 4.0V ~ 4.05V */ + PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */ + PMU_LVD_VOL_SEL_2_3 = 0xA, /**< 2.3V ~ 2.35V */ + PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */ +} pmu_lvd_voltage_sel_t; + +/** + * @brief LVD trigger mode + */ +typedef enum +{ + PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */ + PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */ + PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */ + PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */ + PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */ +} pmu_lvd_trigger_mode_t; + +/** + * @} + */ + +/** + * @defgroup PMU_Private_Macros PMU Private Macros + * @{ + */ +#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \ + ((x) == PMU_LP_STOP2)) +#define IS_PMU_STATUS(x) ((x) == PMU_SR_WUF) +#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \ + ((x) == PMU_LVD_VOL_SEL_2_1) || \ + ((x) == PMU_LVD_VOL_SEL_2_2) || \ + ((x) == PMU_LVD_VOL_SEL_2_4) || \ + ((x) == PMU_LVD_VOL_SEL_2_6) || \ + ((x) == PMU_LVD_VOL_SEL_2_8) || \ + ((x) == PMU_LVD_VOL_SEL_3_0) || \ + ((x) == PMU_LVD_VOL_SEL_3_6) || \ + ((x) == PMU_LVD_VOL_SEL_4_0) || \ + ((x) == PMU_LVD_VOL_SEL_4_6) || \ + ((x) == PMU_LVD_VOL_SEL_2_3) || \ + ((x) == PMU_LVD_VOL_SEL_EXT)) +#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \ + ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \ + ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_RISING_FALLING)) +/** + * @} + */ + +/** @addtogroup PMU_Public_Functions + * @{ + */ +/** @addtogroup PMU_Public_Functions_Group1 + * @{ + */ +/* Low power mode select */ +__STATIC_INLINE__ void ald_pmu_sleep() +{ + __WFI(); +} + +__STATIC_INLINE__ void ald_pmu_sleep_deep() +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); +} + +void ald_pmu_stop1_enter(void); +void ald_pmu_stop2_enter(void); +flag_status_t ald_pmu_get_status(pmu_status_t sr); +void ald_pmu_clear_status(pmu_status_t sr); +/** + * @} + */ +/** @addtogroup PMU_Public_Functions_Group2 + * @{ + */ +/* LVD configure */ +void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state); +void ald_lvd_irq_handler(void); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_PMU_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h new file mode 100644 index 0000000000000000000000000000000000000000..b6a7060e4e0ee60c584355ce62d266ab40cce573 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -0,0 +1,285 @@ +/** + ********************************************************************************* + * + * @file ald_rmu.h + * @brief Header file of RMU module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_RMU_H__ +#define __ALD_RMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup RMU + * @{ + */ + +/** @defgroup RMU_Public_Types RMU Public Types + * @{ + */ +/** + * @brief RMU BOR fliter + */ +typedef enum +{ + RMU_BORFLT_1 = 0x1, /**< 1 cycle */ + RMU_BORFLT_2 = 0x2, /**< 2 cycles */ + RMU_BORFLT_3 = 0x3, /**< 3 cycles */ + RMU_BORFLT_4 = 0x4, /**< 4 cycles */ + RMU_BORFLT_5 = 0x5, /**< 5 cycles */ + RMU_BORFLT_6 = 0x6, /**< 6 cycles */ + RMU_BORFLT_7 = 0x7, /**< 7 cycles */ +} rmu_bor_filter_t; + +/** + * @brief RMU BOR voltage + */ +typedef enum +{ + RMU_VOL_1_7 = 0x0, /**< 1.7V */ + RMU_VOL_2_0 = 0x1, /**< 2.0V */ + RMU_VOL_2_1 = 0x2, /**< 2.1V */ + RMU_VOL_2_2 = 0x3, /**< 2.2V */ + RMU_VOL_2_3 = 0x4, /**< 2.3V */ + RMU_VOL_2_4 = 0x5, /**< 2.4V */ + RMU_VOL_2_5 = 0x6, /**< 2.5V */ + RMU_VOL_2_6 = 0x7, /**< 2.6V */ + RMU_VOL_2_8 = 0x8, /**< 2.8V */ + RMU_VOL_3_0 = 0x9, /**< 3.0V */ + RMU_VOL_3_1 = 0xA, /**< 3.1V */ + RMU_VOL_3_3 = 0xB, /**< 3.3V */ + RMU_VOL_3_6 = 0xC, /**< 3.6V */ + RMU_VOL_3_7 = 0xD, /**< 3.7V */ + RMU_VOL_4_0 = 0xE, /**< 4.0V */ + RMU_VOL_4_3 = 0xF, /**< 4.3V */ +} rmu_bor_vol_t; + +/** + * @brief RMU reset status + */ +typedef enum +{ + RMU_RST_POR = (1U << 0), /**< POR */ + RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ + RMU_RST_BOR = (1U << 2), /**< BOR */ + RMU_RST_NMRST = (1U << 3), /**< NMRST */ + RMU_RST_IWDT = (1U << 4), /**< IWDT */ + RMU_RST_WWDT = (1U << 5), /**< WWDT */ + RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ + RMU_RST_CHIP = (1U << 7), /**< CHIP */ + RMU_RST_MCU = (1U << 8), /**< MCU */ + RMU_RST_CPU = (1U << 9), /**< CPU */ + RMU_RST_CFG = (1U << 10), /**< CFG */ + RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ +} rmu_state_t; + +/** + * @brief RMU periperal select bit + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ + RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ + RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ + RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ + RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ + RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ + RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ + RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ + RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */ + RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */ + RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */ + RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */ + RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */ + RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */ + RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */ + RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */ + RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ + RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ + RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ + RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ + RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */ + RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */ + RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ + RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ + RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ + RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ + RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ + RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ + RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ + RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ + RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ + RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ + RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ + RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ + RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ + RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ + RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ + RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ + RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ + RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ + RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */ + RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ + RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ +} rmu_peripheral_t; +/** + * @} + */ + +/** + * @defgroup RMU_Private_Macros RMU Private Macros + * @{ + */ +#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \ + ((x) == RMU_BORFLT_2) || \ + ((x) == RMU_BORFLT_3) || \ + ((x) == RMU_BORFLT_4) || \ + ((x) == RMU_BORFLT_5) || \ + ((x) == RMU_BORFLT_6) || \ + ((x) == RMU_BORFLT_7)) +#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_7) || \ + ((x) == RMU_VOL_2_0) || \ + ((x) == RMU_VOL_2_1) || \ + ((x) == RMU_VOL_2_2) || \ + ((x) == RMU_VOL_2_3) || \ + ((x) == RMU_VOL_2_4) || \ + ((x) == RMU_VOL_2_5) || \ + ((x) == RMU_VOL_2_6) || \ + ((x) == RMU_VOL_2_8) || \ + ((x) == RMU_VOL_3_0) || \ + ((x) == RMU_VOL_3_1) || \ + ((x) == RMU_VOL_3_3) || \ + ((x) == RMU_VOL_3_6) || \ + ((x) == RMU_VOL_3_7) || \ + ((x) == RMU_VOL_4_0) || \ + ((x) == RMU_VOL_4_3)) +#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \ + ((x) == RMU_RST_WAKEUP) || \ + ((x) == RMU_RST_BOR) || \ + ((x) == RMU_RST_NMRST) || \ + ((x) == RMU_RST_IWDT) || \ + ((x) == RMU_RST_WWDT) || \ + ((x) == RMU_RST_LOCKUP) || \ + ((x) == RMU_RST_CHIP) || \ + ((x) == RMU_RST_MCU) || \ + ((x) == RMU_RST_CPU) || \ + ((x) == RMU_RST_CFG) || \ + ((x) == RMU_RST_CFGERR)) +#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \ + ((x) == RMU_RST_WAKEUP) || \ + ((x) == RMU_RST_BOR) || \ + ((x) == RMU_RST_NMRST) || \ + ((x) == RMU_RST_IWDT) || \ + ((x) == RMU_RST_WWDT) || \ + ((x) == RMU_RST_LOCKUP) || \ + ((x) == RMU_RST_CHIP) || \ + ((x) == RMU_RST_MCU) || \ + ((x) == RMU_RST_CPU) || \ + ((x) == RMU_RST_CFG)) +#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \ + ((x) == RMU_PERH_CRC) || \ + ((x) == RMU_PERH_CALC) || \ + ((x) == RMU_PERH_CRYPT) || \ + ((x) == RMU_PERH_TRNG) || \ + ((x) == RMU_PERH_PIS) || \ + ((x) == RMU_PERH_CHIP) || \ + ((x) == RMU_PERH_CPU) || \ + ((x) == RMU_PERH_TIMER0) || \ + ((x) == RMU_PERH_TIMER1) || \ + ((x) == RMU_PERH_TIMER2) || \ + ((x) == RMU_PERH_TIMER3) || \ + ((x) == RMU_PERH_TIMER4) || \ + ((x) == RMU_PERH_TIMER5) || \ + ((x) == RMU_PERH_TIMER6) || \ + ((x) == RMU_PERH_TIMER7) || \ + ((x) == RMU_PERH_UART0) || \ + ((x) == RMU_PERH_UART1) || \ + ((x) == RMU_PERH_UART2) || \ + ((x) == RMU_PERH_UART3) || \ + ((x) == RMU_PERH_USART0) || \ + ((x) == RMU_PERH_USART1) || \ + ((x) == RMU_PERH_SPI0) || \ + ((x) == RMU_PERH_SPI1) || \ + ((x) == RMU_PERH_SPI2) || \ + ((x) == RMU_PERH_I2C0) || \ + ((x) == RMU_PERH_I2C1) || \ + ((x) == RMU_PERH_CAN0) || \ + ((x) == RMU_PERH_LPTIM0) || \ + ((x) == RMU_PERH_LPUART0) || \ + ((x) == RMU_PERH_ADC0) || \ + ((x) == RMU_PERH_ADC1) || \ + ((x) == RMU_PERH_ACMP0) || \ + ((x) == RMU_PERH_ACMP1) || \ + ((x) == RMU_PERH_OPAMP) || \ + ((x) == RMU_PERH_DAC0) || \ + ((x) == RMU_PERH_WWDT) || \ + ((x) == RMU_PERH_LCD) || \ + ((x) == RMU_PERH_IWDT) || \ + ((x) == RMU_PERH_RTC) || \ + ((x) == RMU_PERH_TSENSE) || \ + ((x) == RMU_PERH_BKPC) || \ + ((x) == RMU_PERH_BKPRAM)) +/** + * @} + */ + +/** @addtogroup RMU_Public_Functions + * @{ + */ +void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state); +flag_status_t ald_rmu_get_reset_status(rmu_state_t state); +void ald_rmu_clear_reset_status(rmu_state_t state); +void ald_rmu_reset_periperal(rmu_peripheral_t perh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_RMU_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..e14f542363707152db84d1ace5f3a59c874c31b5 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -0,0 +1,699 @@ +/** + ****************************************************************************** + * @file ald_rtc.h + * @brief Header file of RTC Module driver. + * + * @version V1.0 + * @date 16 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************* + */ + +#ifndef __ALD_RTC_H__ +#define __ALD_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Public_Types RTC Public Types + * @{ + */ + +/** + * @brief Hours format + */ +typedef enum +{ + RTC_HOUR_FORMAT_24 = 0x0, /**< 24-hours format */ + RTC_HOUR_FORMAT_12 = 0x1, /**< 12-hours format */ +} rtc_hour_format_t; + +/** + * @brief Output mode + */ +typedef enum +{ + RTC_OUTPUT_DISABLE = 0x0, /**< Disable output */ + RTC_OUTPUT_ALARM_A = 0x1, /**< Output alarm_a signal */ + RTC_OUTPUT_ALARM_B = 0x2, /**< Output alarm_b signal */ + RTC_OUTPUT_WAKEUP = 0x3, /**< Output wakeup signal */ +} rtc_output_select_t; + +/** + * @brief Output polarity + */ +typedef enum +{ + RTC_OUTPUT_POLARITY_HIGH = 0x0, /**< Polarity is high */ + RTC_OUTPUT_POLARITY_LOW = 0x0, /**< Polarity is low */ +} rtc_output_polarity_t; + +/** + * @brief Initialization structure + */ +typedef struct +{ + rtc_hour_format_t hour_format; /**< Hours format */ + uint32_t asynch_pre_div; /**< Asynchronous predivider value */ + uint32_t synch_pre_div; /**< Synchronous predivider value */ + rtc_output_select_t output; /**< Output signal type */ + rtc_output_polarity_t output_polarity; /**< Output polarity */ +} rtc_init_t; + +/** + * @brief Source select + */ +typedef enum +{ + RTC_SOURCE_LOSC = 0x0, /**< LOSC */ + RTC_SOURCE_LRC = 0x1, /**< LRC */ + RTC_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ + RTC_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ +} rtc_source_sel_t; + +/** + * @brief Time structure + */ +typedef struct +{ + uint8_t hour; /**< Hours */ + uint8_t minute; /**< Minutes */ + uint8_t second; /**< Seconds */ + uint16_t sub_sec; /**< Sub-seconds */ +} rtc_time_t; + +/** + * @brief Date structure + */ +typedef struct +{ + uint8_t week; /**< Weeks */ + uint8_t day; /**< days */ + uint8_t month; /**< months */ + uint8_t year; /**< years */ +} rtc_date_t; + +/** + * @brief Data format + */ +typedef enum +{ + RTC_FORMAT_DEC = 0, + RTC_FORMAT_BCD = 1, +} rtc_format_t; + +/** + * @brief Index of alarm + */ +typedef enum +{ + RTC_ALARM_A = 0x0, /**< Alarm-A */ + RTC_ALARM_B = 0x1, /**< Alarm-B */ +} rtc_alarm_idx_t; + +/** + * @brief Alarm mask + */ +typedef enum +{ + RTC_ALARM_MASK_NONE = 0x0, /**< Mask is disable */ + RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ + RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ + RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ + RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ + RTC_ALARM_MASK_ALL = 0x40808080, /**< Mask all */ +} rtc_alarm_mask_t; + +/** + * @brief Alarm sub-second mask + */ +typedef enum +{ + RTC_ALARM_SS_MASK_NONE = 0xF, /**< Mask is disable */ + RTC_ALARM_SS_MASK_14_1 = 0x1, /**< Mask bit(1-14) */ + RTC_ALARM_SS_MASK_14_2 = 0x2, /**< Mask bit(2-14) */ + RTC_ALARM_SS_MASK_14_3 = 0x3, /**< Mask bit(3-14) */ + RTC_ALARM_SS_MASK_14_4 = 0x4, /**< Mask bit(4-14) */ + RTC_ALARM_SS_MASK_14_5 = 0x5, /**< Mask bit(5-14) */ + RTC_ALARM_SS_MASK_14_6 = 0x6, /**< Mask bit(6-14) */ + RTC_ALARM_SS_MASK_14_7 = 0x7, /**< Mask bit(7-14) */ + RTC_ALARM_SS_MASK_14_8 = 0x8, /**< Mask bit(8-14) */ + RTC_ALARM_SS_MASK_14_9 = 0x9, /**< Mask bit(9-14) */ + RTC_ALARM_SS_MASK_14_10 = 0xA, /**< Mask bit(10-14) */ + RTC_ALARM_SS_MASK_14_11 = 0xB, /**< Mask bit(11-14) */ + RTC_ALARM_SS_MASK_14_12 = 0xC, /**< Mask bit(12-14) */ + RTC_ALARM_SS_MASK_14_13 = 0xD, /**< Mask bit(13-14) */ + RTC_ALARM_SS_MASK_14 = 0xE, /**< Mask bit14 */ + RTC_ALARM_SS_MASK_ALL = 0x0, /**< Mask bit(0-14) */ +} rtc_sub_second_mask_t; + +/** + * @brief Alarm select week or day */ +typedef enum +{ + RTC_SELECT_DAY = 0x0, /**< Alarm select day */ + RTC_SELECT_WEEK = 0x1, /**< Alarm select week */ +} rtc_week_day_sel_t; + +/** + * @brief Alarm structure + */ +typedef struct +{ + rtc_alarm_idx_t idx; /**< Index of alarm */ + rtc_time_t time; /**< Time structure */ + uint32_t mask; /**< Alarm mask */ + rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ + rtc_week_day_sel_t sel; /**< Select week or day */ + + union + { + uint8_t week; /**< Alarm select week */ + uint8_t day; /**< Alarm select day */ + }; +} rtc_alarm_t; + +/** + * @brief Time stamp signel select + */ +typedef enum +{ + RTC_TS_SIGNAL_SEL_TAMPER0 = 0, /**< Select tamper0 */ + RTC_TS_SIGNAL_SEL_TAMPER1 = 1, /**< Select tamper1 */ +} rtc_ts_signal_sel_t; + +/** + * @brief Time stamp trigger style + */ +typedef enum +{ + RTC_TS_RISING_EDGE = 0, /**< Rising edge */ + RTC_TS_FALLING_EDGE = 1, /**< Falling edge */ +} rtc_ts_trigger_style_t; + +/** + * @brief Index of tamper + */ +typedef enum +{ + RTC_TAMPER_0 = 0, /**< Tamper0 */ + RTC_TAMPER_1 = 1, /**< Tamper1 */ +} rtc_tamper_idx_t; + +/** + * @brief Tamper trigger type + */ +typedef enum +{ + RTC_TAMPER_TRIGGER_LOW = 0, /**< High trigger */ + RTC_TAMPER_TRIGGER_HIGH = 1, /**< Low trigger */ +} rtc_tamper_trigger_t; + +/** + * @brief Tamper sampling frequency + */ +typedef enum +{ + RTC_TAMPER_SAMPLING_FREQ_32768 = 0, /**< RTCCLK / 32768 */ + RTC_TAMPER_SAMPLING_FREQ_16384 = 1, /**< RTCCLK / 16384 */ + RTC_TAMPER_SAMPLING_FREQ_8192 = 2, /**< RTCCLK / 8192 */ + RTC_TAMPER_SAMPLING_FREQ_4096 = 3, /**< RTCCLK / 4096 */ + RTC_TAMPER_SAMPLING_FREQ_2048 = 4, /**< RTCCLK / 2048 */ + RTC_TAMPER_SAMPLING_FREQ_1024 = 5, /**< RTCCLK / 1024 */ + RTC_TAMPER_SAMPLING_FREQ_512 = 6, /**< RTCCLK / 512 */ + RTC_TAMPER_SAMPLING_FREQ_256 = 7, /**< RTCCLK / 256 */ +} rtc_tamper_sampling_freq_t; + +/** + * @brief Tamper filter time + */ +typedef enum +{ + RTC_TAMPER_DURATION_1 = 0, /**< Duration 1 sampling */ + RTC_TAMPER_DURATION_2 = 1, /**< Duration 2 sampling */ + RTC_TAMPER_DURATION_4 = 2, /**< Duration 4 sampling */ + RTC_TAMPER_DURATION_8 = 3, /**< Duration 8 sampling */ +} rtc_tamper_duration_t; + +/** + * @brief Tamper structure + */ +typedef struct +{ + rtc_tamper_idx_t idx; /**< Index of tamper */ + rtc_tamper_trigger_t trig; /**< Trigger type */ + rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ + rtc_tamper_duration_t dur; /**< Filter time */ + type_func_t ts; /**< Enable/Disable trigger time stamp event */ +} rtc_tamper_t; + +/** + * @brief Wake-up clock + */ +typedef enum +{ + RTC_WAKEUP_CLOCK_DIV_16 = 0, /**< RTCCLK / 16 */ + RTC_WAKEUP_CLOCK_DIV_8 = 1, /**< RTCCLK / 8 */ + RTC_WAKEUP_CLOCK_DIV_4 = 2, /**< RTCCLK / 4 */ + RTC_WAKEUP_CLOCK_DIV_2 = 3, /**< RTCCLK / 2 */ + RTC_WAKEUP_CLOCK_1HZ = 4, /**< 1Hz */ + RTC_WAKEUP_CLOCK_1HZ_PULS = 6, /**< 1Hz and WUT + 65536 */ +} rtc_wakeup_clock_t; + +/** + * @brief RTC clock output type + */ +typedef enum +{ + RTC_CLOCK_OUTPUT_32768 = 0, /**< 32768Hz */ + RTC_CLOCK_OUTPUT_1024 = 1, /**< 1024Hz */ + RTC_CLOCK_OUTPUT_32 = 2, /**< 32Hz */ + RTC_CLOCK_OUTPUT_1 = 3, /**< 1Hz */ + RTC_CLOCK_OUTPUT_CAL_1 = 4, /**< 1Hz after calibration */ + RTC_CLOCK_OUTPUT_EXA_1 = 5, /**< Exact 1Hz */ +} rtc_clock_output_t; + +/** + * @ Calibration frequency + */ +typedef enum +{ + RTC_CALI_FREQ_10_SEC = 0, /**< Calibrate every 10 seconds */ + RTC_CALI_FREQ_20_SEC = 1, /**< Calibrate every 20 seconds */ + RTC_CALI_FREQ_1_MIN = 2, /**< Calibrate every 1 minute */ + RTC_CALI_FREQ_2_MIN = 3, /**< Calibrate every 2 minutes */ + RTC_CALI_FREQ_5_MIN = 4, /**< Calibrate every 5 minutes */ + RTC_CALI_FREQ_10_MIN = 5, /**< Calibrate every 10 minutes */ + RTC_CALI_FREQ_20_MIN = 6, /**< Calibrate every 20 minutes */ + RTC_CALI_FREQ_1_SEC = 7, /**< Calibrate every 1 second */ +} rtc_cali_freq_t; + +/** + * @brief Temperature compensate type + */ +typedef enum +{ + RTC_CALI_TC_NONE = 0, /**< Temperature compensate disable */ + RTC_CALI_TC_AUTO_BY_HW = 1, /**< Temperature compensate by hardware */ + RTC_CALI_TC_AUTO_BY_SF = 2, /**< Temperature compensate by software */ + RTC_CALI_TC_AUTO_BY_HW_SF = 3, /**< Temperature compensate by hardware, trigger by software */ +} rtc_cali_tc_t; + +/** + * @ Calculate frequency + */ +typedef enum +{ + RTC_CALI_CALC_FREQ_10_SEC = 0, /**< Calculate every 10 seconds */ + RTC_CALI_CALC_FREQ_20_SEC = 1, /**< Calculate every 20 seconds */ + RTC_CALI_CALC_FREQ_1_MIN = 2, /**< Calculate every 1 minute */ + RTC_CALI_CALC_FREQ_2_MIN = 3, /**< Calculate every 2 minutes */ + RTC_CALI_CALC_FREQ_5_MIN = 4, /**< Calculate every 5 minutes */ + RTC_CALI_CALC_FREQ_10_MIN = 5, /**< Calculate every 10 minutes */ + RTC_CALI_CALC_FREQ_20_MIN = 6, /**< Calculate every 20 minutes */ + RTC_CALI_CALC_FREQ_1_HOUR = 7, /**< Calculate every 1 hour */ +} rtc_cali_calc_freq_t; + +/** + * @brief Calibration algorithm + */ +typedef enum +{ + RTC_CALI_CALC_4 = 0, /**< 4-polynomial */ + RTC_CALI_CALC_2 = 1, /**< 2-parabola */ +} rtc_cali_calc_t; + +/** + * @brief Calibration structure + */ +typedef struct +{ + rtc_cali_freq_t cali_freq; /**< calibrate frequency */ + rtc_cali_tc_t tc; /**< Temperature compensate type */ + rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ + rtc_cali_calc_t calc; /**< algorithm */ + type_func_t acc; /**< Enable/Disable decimal accumulate */ +} rtc_cali_t; + +/** + * @brief Interrupt type + */ +typedef enum +{ + RTC_IT_SEC = (1U << 0), /**< Second */ + RTC_IT_MIN = (1U << 1), /**< Minute */ + RTC_IT_HR = (1U << 2), /**< Hour */ + RTC_IT_DAY = (1U << 3), /**< Day */ + RTC_IT_MON = (1U << 4), /**< Month */ + RTC_IT_YR = (1U << 5), /**< Year */ + RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IT_TS = (1U << 10), /**< Time stamp */ + RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IT_SFC = (1U << 17), /**< Shift complete */ + RTC_IT_WU = (1U << 18), /**< Wake-up */ + RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ +} rtc_it_t; + +/** + * @brief Interrupt flag + */ +typedef enum +{ + RTC_IF_SEC = (1U << 0), /**< Second */ + RTC_IF_MIN = (1U << 1), /**< Minute */ + RTC_IF_HR = (1U << 2), /**< Hour */ + RTC_IF_DAY = (1U << 3), /**< Day */ + RTC_IF_MON = (1U << 4), /**< Month */ + RTC_IF_YR = (1U << 5), /**< Year */ + RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IF_TS = (1U << 10), /**< Time stamp */ + RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IF_SFC = (1U << 17), /**< Shift complete */ + RTC_IF_WU = (1U << 18), /**< Wake-up */ + RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ +} rtc_flag_t; +/** + * @} + */ + +/** @defgroup RTC_Public_Macro RTC Public Macros + * @{ + */ +#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55)) +#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0)) +#define RTC_BY_PASS_ENABLE() \ + do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ + } while (0) +#define RTC_BY_PASS_DISABLE() \ + do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ + } while (0) +#define RTC_SUMMER_TIME_ENABLE() \ + do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ + } while (0) +#define RTC_SUMMER_TIME_DISABLE() \ + do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ + } while (0) +#define RTC_WINTER_TIME_ENABLE() \ + do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ + } while (0) +#define RTC_WINTER_TIME_DISABLE() \ + do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ + } while (0) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AA)) +#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0)) +#define ALARM_MASK_ALL 0x40808080 +#define RTC_TIMEOUT_VALUE 100 + +#define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15)) +#define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \ + ((x) == RTC_HOUR_FORMAT_12)) +#define IS_RTC_OUTPUT_SEL(x) (((x) == RTC_OUTPUT_DISABLE) || \ + ((x) == RTC_OUTPUT_ALARM_A) || \ + ((x) == RTC_OUTPUT_ALARM_B) || \ + ((x) == RTC_OUTPUT_WAKEUP)) +#define IS_RTC_OUTPUT_POLARITY(x) (((x) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((x) == RTC_OUTPUT_POLARITY_LOW)) +#define IS_RTC_SOURCE_SEL(x) (((x) == RTC_SOURCE_LOSC) || \ + ((x) == RTC_SOURCE_LRC) || \ + ((x) == RTC_SOURCE_HRC_DIV_1M ) || \ + ((x) == RTC_SOURCE_HOSC_DIV_1M)) +#define IS_RTC_ALARM(x) (((x) == RTC_ALARM_A) || \ + ((x) == RTC_ALARM_B)) +#define IS_RTC_ALARM_SEL(x) (((x) == RTC_SELECT_DAY) || \ + ((x) == RTC_SELECT_WEEK)) +#define IS_RTC_ALARM_MASK(x) (((x) == RTC_ALARM_MASK_NONE) || \ + ((x) == RTC_ALARM_MASK_WEEK_DAY) || \ + ((x) == RTC_ALARM_MASK_HOUR) || \ + ((x) == RTC_ALARM_MASK_MINUTE) || \ + ((x) == RTC_ALARM_MASK_SECOND) || \ + ((x) == RTC_ALARM_MASK_ALL)) +#define IS_RTC_ALARM_SS_MASK(x) (((x) == RTC_ALARM_SS_MASK_NONE) || \ + ((x) == RTC_ALARM_SS_MASK_14_1) || \ + ((x) == RTC_ALARM_SS_MASK_14_2) || \ + ((x) == RTC_ALARM_SS_MASK_14_3) || \ + ((x) == RTC_ALARM_SS_MASK_14_4) || \ + ((x) == RTC_ALARM_SS_MASK_14_5) || \ + ((x) == RTC_ALARM_SS_MASK_14_6) || \ + ((x) == RTC_ALARM_SS_MASK_14_7) || \ + ((x) == RTC_ALARM_SS_MASK_14_8) || \ + ((x) == RTC_ALARM_SS_MASK_14_9) || \ + ((x) == RTC_ALARM_SS_MASK_14_10) || \ + ((x) == RTC_ALARM_SS_MASK_14_11) || \ + ((x) == RTC_ALARM_SS_MASK_14_12) || \ + ((x) == RTC_ALARM_SS_MASK_14_13) || \ + ((x) == RTC_ALARM_SS_MASK_14) || \ + ((x) == RTC_ALARM_SS_MASK_ALL)) +#define IS_RTC_TS_SIGNAL(x) (((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \ + ((x) == RTC_TS_SIGNAL_SEL_TAMPER1)) +#define IS_RTC_TS_STYLE(x) (((x) == RTC_TS_RISING_EDGE) || \ + ((x) == RTC_TS_FALLING_EDGE)) +#define IS_RTC_FORMAT(x) (((x) == RTC_FORMAT_DEC) || \ + ((x) == RTC_FORMAT_BCD)) +#define IS_RTC_TAMPER(x) (((x) == RTC_TAMPER_0) || \ + ((x) == RTC_TAMPER_1)) +#define IS_RTC_TAMPER_TRIGGER(x) (((x) == RTC_TAMPER_TRIGGER_LOW) || \ + ((x) == RTC_TAMPER_TRIGGER_HIGH)) +#define IS_RTC_TAMPER_SAMPLING_FREQ(x) (((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_256)) +#define IS_RTC_TAMPER_DURATION(x) (((x) == RTC_TAMPER_DURATION_1) || \ + ((x) == RTC_TAMPER_DURATION_2) || \ + ((x) == RTC_TAMPER_DURATION_4) || \ + ((x) == RTC_TAMPER_DURATION_8)) +#define IS_RTC_WAKEUP_CLOCK(x) (((x) == RTC_WAKEUP_CLOCK_DIV_16) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_8) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_4) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_2) || \ + ((x) == RTC_WAKEUP_CLOCK_1HZ) || \ + ((x) == RTC_WAKEUP_CLOCK_1HZ_PULS)) +#define IS_RTC_CLOCK_OUTPUT(x) (((x) == RTC_CLOCK_OUTPUT_32768) || \ + ((x) == RTC_CLOCK_OUTPUT_1024) || \ + ((x) == RTC_CLOCK_OUTPUT_32) || \ + ((x) == RTC_CLOCK_OUTPUT_1) || \ + ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \ + ((x) == RTC_CLOCK_OUTPUT_EXA_1)) +#define IS_RTC_CALI_FREQ(x) (((x) == RTC_CALI_FREQ_10_SEC) || \ + ((x) == RTC_CALI_FREQ_20_SEC) || \ + ((x) == RTC_CALI_FREQ_1_MIN) || \ + ((x) == RTC_CALI_FREQ_2_MIN) || \ + ((x) == RTC_CALI_FREQ_5_MIN) || \ + ((x) == RTC_CALI_FREQ_10_MIN) || \ + ((x) == RTC_CALI_FREQ_20_MIN) || \ + ((x) == RTC_CALI_FREQ_1_SEC)) +#define IS_RTC_CALI_TC(x) (((x) == RTC_CALI_TC_NONE) || \ + ((x) == RTC_CALI_TC_AUTO_BY_HW) || \ + ((x) == RTC_CALI_TC_AUTO_BY_SF) || \ + ((x) == RTC_CALI_TC_AUTO_BY_HW_SF)) +#define IS_RTC_CALC_FREQ(x) (((x) == RTC_CALI_CALC_FREQ_10_SEC) || \ + ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \ + ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_5_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_1_HOUR)) +#define IS_RTC_CALI_CALC(x) (((x) == RTC_CALI_CALC_4) || \ + ((x) == RTC_CALI_CALC_2)) +#define IS_RTC_IT(x) (((x) == RTC_IT_SEC) || \ + ((x) == RTC_IT_MIN) || \ + ((x) == RTC_IT_HR) || \ + ((x) == RTC_IT_DAY) || \ + ((x) == RTC_IT_MON) || \ + ((x) == RTC_IT_YR) || \ + ((x) == RTC_IT_ALMA) || \ + ((x) == RTC_IT_ALMB) || \ + ((x) == RTC_IT_TS) || \ + ((x) == RTC_IT_TSOV) || \ + ((x) == RTC_IT_TP0) || \ + ((x) == RTC_IT_TP1) || \ + ((x) == RTC_IT_RSC) || \ + ((x) == RTC_IT_SFC) || \ + ((x) == RTC_IT_WU) || \ + ((x) == RTC_IT_TCC) || \ + ((x) == RTC_IT_TCE)) +#define IS_RTC_IF(x) (((x) == RTC_IF_SEC) || \ + ((x) == RTC_IF_MIN) || \ + ((x) == RTC_IF_HR) || \ + ((x) == RTC_IF_DAY) || \ + ((x) == RTC_IF_MON) || \ + ((x) == RTC_IF_YR) || \ + ((x) == RTC_IF_ALMA) || \ + ((x) == RTC_IF_ALMB) || \ + ((x) == RTC_IF_TS) || \ + ((x) == RTC_IF_TSOV) || \ + ((x) == RTC_IF_TP0) || \ + ((x) == RTC_IF_TP1) || \ + ((x) == RTC_IF_RSC) || \ + ((x) == RTC_IF_SFC) || \ + ((x) == RTC_IF_WU) || \ + ((x) == RTC_IF_TCC) || \ + ((x) == RTC_IF_TCE)) +#define IS_RTC_SECOND(x) ((x) < 60) +#define IS_RTC_MINUTE(x) ((x) < 60) +#define IS_RTC_HOUR(x) ((x) < 24) +#define IS_RTC_DAY(x) (((x) > 0) && ((x) < 32)) +#define IS_RTC_MONTH(x) (((x) > 0) && ((x) < 13)) +#define IS_RTC_YEAR(x) ((x) < 100) +/** + * @} + */ + +/** @addtogroup RTC_Public_Functions + * @{ + */ + +/** @addtogroup RTC_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_rtc_reset(void); +void ald_rtc_init(rtc_init_t *init); +void ald_rtc_source_select(rtc_source_sel_t sel); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group2 + * @{ + */ +/* Time and date operation functions */ +ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format); +ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format); +void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format); +void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format); +int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group3 + * @{ + */ +/* Alarm functions */ +void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format); +void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group4 + * @{ + */ +/* Time stamp functions */ +void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style); +void ald_rtc_cancel_time_stamp(void); +void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group5 + * @{ + */ +/* Tamper functions */ +void ald_rtc_set_tamper(rtc_tamper_t *tamper); +void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group6 + * @{ + */ +/* Wakeup functions */ +void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value); +void ald_rtc_cancel_wakeup(void); +uint16_t ald_rtc_get_wakeup_timer_value(void); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group7 + * @{ + */ +/* Clock output functions */ +ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock); +void ald_rtc_cancel_clock_output(void); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group8 + * @{ + */ +/* Control functions */ +void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state); +void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state); +ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss); +void ald_rtc_set_cali(rtc_cali_t *config); +void ald_rtc_cancel_cali(void); +ald_status_t ald_rtc_get_cali_status(void); +void ald_rtc_write_temp(uint16_t temp); +it_status_t ald_rtc_get_it_status(rtc_it_t it); +flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag); +void ald_rtc_clear_flag_status(rtc_flag_t flag); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h new file mode 100644 index 0000000000000000000000000000000000000000..b04380ee6d0973f1fc31238a247a07616adce0c3 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h @@ -0,0 +1,279 @@ +/** + ********************************************************************************* + * + * @file ald_usart.h + * @brief Header file of SMARTCARD driver module. + * + * @version V1.0 + * @date 25 Apr 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_SMARTCARD_H__ +#define __ALD_SMARTCARD_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_usart.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup SMARTCARD + * @{ + */ + +/** @defgroup SMARTCARD_Public_Constants SMARTCARD Public constants + * @{ + */ + +/** + * @brief SMARTCARD error codes + */ +typedef enum +{ + SMARTCARD_ERROR_NONE = ((uint32_t)0x00), /**< No error */ + SMARTCARD_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ + SMARTCARD_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ + SMARTCARD_ERROR_FE = ((uint32_t)0x04), /**< frame error */ + SMARTCARD_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ + SMARTCARD_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +} smartcard_error_t; + +/** + * @brief SMARTCARD Prescaler + */ +typedef enum +{ + SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1), /**< SYSCLK divided by 2 */ + SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2), /**< SYSCLK divided by 4 */ + SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3), /**< SYSCLK divided by 6 */ + SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4), /**< SYSCLK divided by 8 */ + SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5), /**< SYSCLK divided by 10 */ + SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6), /**< SYSCLK divided by 12 */ + SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7), /**< SYSCLK divided by 14 */ + SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8), /**< SYSCLK divided by 16 */ + SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9), /**< SYSCLK divided by 18 */ + SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA), /**< SYSCLK divided by 20 */ + SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB), /**< SYSCLK divided by 22 */ + SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC), /**< SYSCLK divided by 24 */ + SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD), /**< SYSCLK divided by 26 */ + SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE), /**< SYSCLK divided by 28 */ + SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF), /**< SYSCLK divided by 30 */ + SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10), /**< SYSCLK divided by 32 */ + SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11), /**< SYSCLK divided by 34 */ + SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12), /**< SYSCLK divided by 36 */ + SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13), /**< SYSCLK divided by 38 */ + SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14), /**< SYSCLK divided by 40 */ + SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15), /**< SYSCLK divided by 42 */ + SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16), /**< SYSCLK divided by 44 */ + SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17), /**< SYSCLK divided by 46 */ + SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18), /**< SYSCLK divided by 48 */ + SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19), /**< SYSCLK divided by 50 */ + SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A), /**< SYSCLK divided by 52 */ + SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B), /**< SYSCLK divided by 54 */ + SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C), /**< SYSCLK divided by 56 */ + SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D), /**< SYSCLK divided by 58 */ + SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E), /**< SYSCLK divided by 60 */ + SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F), /**< SYSCLK divided by 62 */ +} smartcard_prescaler_t; + +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Types SMARTCARD Public Types + * @{ + */ + +/** + * @brief SMARTCARD Init Structure definition + */ +typedef struct +{ + uint32_t baud; /**< This member configures the SmartCard communication baud rate. */ + usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ + usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ + usart_parity_t parity; /**< Specifies the parity mode. + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits).*/ + usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */ + usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ + usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/ + usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref usart_last_bit_t */ + smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock + to provide the smartcard clock. The value given in the register (5 significant bits) + is multiplied by 2 to give the division factor of the source clock frequency. */ + uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ + type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */ +} smartcard_init_t; + +/** + * @brief ALD state structures definition + */ +typedef enum +{ + SMARTCARD_STATE_RESET = 0x00, /**< Peripheral is not yet Initialized */ + SMARTCARD_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + SMARTCARD_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + SMARTCARD_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ + SMARTCARD_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ + SMARTCARD_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission and Reception process is ongoing */ + SMARTCARD_STATE_TIMEOUT = 0x03, /**< Timeout state */ + SMARTCARD_STATE_ERROR = 0x04 /**< Error */ +} smartcard_state_t; + + +/** + * @brief SMARTCARD handle structure definition + */ +typedef struct smartcard_handle_s +{ + USART_TypeDef *perh; /**< USART registers base address */ + smartcard_init_t init; /**< SmartCard communication parameters */ + uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */ + uint16_t tx_size; /**< SmartCard Tx Transfer size */ + uint16_t tx_count; /**< SmartCard Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */ + uint16_t rx_size; /**< SmartCard Rx Transfer size */ + uint16_t rx_count; /**< SmartCard Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + smartcard_state_t state; /**< SmartCard communication state */ + uint32_t err_code; /**< SmartCard Error code */ + + void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */ +} smartcard_handle_t; + +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Macros SMARTCARD Public Macros + * @{ + */ + +/** @defgroup SMARTCARD_Public_Macros_1 SMARTCARD handle reset + * @{ + */ +#define SMARTCARD_RESET_HANDLE_STATE(handle) ((handle)->state = SMARTCARD_STATE_RESET) +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Macros_2 SMARTCARD flush data + * @{ + */ +#define SMARTCARD_FLUSH_DRREGISTER(handle) ((handle)->perh->DATA) +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Macros_3 SMARTCARD enable + * @{ + */ +#define SMARTCARD_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Macros_4 SMARTCARD disable + * @{ + */ +#define SMARTCARD_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros + * @{ + */ + +#define IS_SMARTCARD_PRESCALER(x) (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \ + ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62)) +/** + * @} + */ + +/** @addtogroup SMARTCARD_Public_Functions + * @{ + */ + +/** @addtogroup SMARTCARD_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +ald_status_t ald_smartcard_init(smartcard_handle_t *hperh); +ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup SMARTCARD_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +#endif +void ald_smartcard_irq_handler(smartcard_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup SMARTCARD_Public_Functions_Group3 + * @{ + */ +/* Peripheral State and Errors functions functions */ +smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh); +uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_SMARTCARD_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..d92aefb219bd36f88c6b54c2f17eb07cdb7d180a --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -0,0 +1,398 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief Header file of SPI module driver. + * + * @version V1.0 + * @date 13 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_SPI_H__ +#define __ALD_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Public_Types SPI Public Types + * @{ + */ + +/** + * @brief clock phase + */ +typedef enum +{ + SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */ + SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */ +} spi_cpha_t; + +/** + * @brief clock polarity + */ +typedef enum +{ + SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */ + SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */ +} spi_cpol_t; + +/** + * @brief master selection + */ +typedef enum +{ + SPI_MODE_SLAVER = 0, /**< Slave mode */ + SPI_MODE_MASTER = 1, /**< Master mode */ +} spi_mode_t; + +/** + * @brief baud rate control + */ +typedef enum +{ + SPI_BAUD_2 = 0, /**< fpclk/2 */ + SPI_BAUD_4 = 1, /**< fpclk/4 */ + SPI_BAUD_8 = 2, /**< fpclk/8 */ + SPI_BAUD_16 = 3, /**< fpclk/16 */ + SPI_BAUD_32 = 4, /**< fpclk/32 */ + SPI_BAUD_64 = 5, /**< fpclk/64 */ + SPI_BAUD_128 = 6, /**< fpclk/128 */ + SPI_BAUD_256 = 7, /**< fpclk/256 */ +} spi_baud_t; + +/** + * @brief frame format + */ +typedef enum +{ + SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */ + SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */ +} spi_firstbit_t; + +/** + * @brief data frame format + */ +typedef enum +{ + SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */ + SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */ +} spi_datasize_t; + +/** + * @brief interrupt control + */ +typedef enum +{ + SPI_IT_ERR = (1U << 5), /**< error interrupt */ + SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */ + SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */ +} spi_it_t; + +/** + * @brief interrupt flag + */ +typedef enum +{ + SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */ + SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */ + SPI_IF_CRCERR = (1U << 4), /**< crc error flag */ + SPI_IF_MODF = (1U << 5), /**< mode fault */ + SPI_IF_OVE = (1U << 6), /**< overrun flag */ + SPI_IF_BUSY = (1U << 7), /**< busy flag */ +} spi_flag_t; + +/** + * @brief SPI error status + */ +typedef enum +{ + SPI_ERROR_NONE = 0, /**< none */ + SPI_ERROR_MODF = 1, /**< mode fault */ + SPI_ERROR_CRC = 2, /**< crc error */ + SPI_ERROR_OVE = 4, /**< overrun error */ + SPI_ERROR_DMA = 8, /**< dma error */ + SPI_ERROR_FLAG = 0x10, /**< interrupt flag error */ +} spi_error_t; + + + +/** + * @brief SPI state structures definition + */ +typedef enum +{ + SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */ + SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */ + SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */ + SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */ + SPI_STATE_ERROR = 0x04, /**< Error */ +} spi_state_t; + +/** + * @brief SPI status definition + */ +typedef enum +{ + SPI_STATUS_RXBNE = (1U << 0), /**< Receive not empty status */ + SPI_STATUS_TXBE = (1U << 1), /**< Transmit empty status */ + SPI_STATUS_CRCERR = (1U << 4), /**< CRC error status */ + SPI_STATUS_MODEERR = (1U << 5), /**< Mode error status */ + SPI_STATUS_OVERR = (1U << 6), /**< Overflow status */ + SPI_STATUS_BUSY = (1U << 7), /**< Busy status */ + +} spi_status_t; + +/** + * @brief SPI direction definition + */ +typedef enum +{ + SPI_DIRECTION_2LINES = 0, /**< 2 lines */ + SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */ + SPI_DIRECTION_1LINE = 2, /**< 1 line */ + SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */ +} spi_direction_t; + +/** + * @brief SPI dma request definition + */ +typedef enum +{ + SPI_DMA_REQ_TX = 0, /**< TX dma request */ + SPI_DMA_REQ_RX = 1, /**< RX dma request */ +} spi_dma_req_t; + +/** + * @brief SPI TXE/RXNE status definition + */ +typedef enum +{ + SPI_SR_TXBE = 0, /**< SR.TXE set */ + SPI_SR_RXBNE = 1, /**< SR.RXNE set */ + SPI_SR_TXBE_RXBNE = 2, /**< SR.TXE and SR.RXNE set */ +} spi_sr_status_t; + +/** + * @brief SPI init structure definition + */ +typedef struct +{ + spi_mode_t mode; /**< SPI mode */ + spi_direction_t dir; /**< SPI direction */ + spi_datasize_t data_size; /**< SPI data size */ + spi_baud_t baud; /**< SPI baudrate prescaler */ + spi_cpha_t phase; /**< SPI clock phase */ + spi_cpol_t polarity; /**< SPI clock polarity */ + spi_firstbit_t first_bit; /**< SPI first bit */ + type_func_t ss_en; /**< SPI ssm enable or disable */ + type_func_t crc_calc; /**< SPI crc calculation */ + uint16_t crc_poly; /**< SPI crc polynomial */ +} spi_init_t; + +/** + * @brief SPI handle structure definition + */ +typedef struct spi_handle_s +{ + SPI_TypeDef *perh; /**< SPI registers base address */ + spi_init_t init; /**< SPI communication parameters */ + uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ + uint16_t tx_size; /**< SPI Tx transfer size */ + uint16_t tx_count; /**< SPI Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ + uint16_t rx_size; /**< SPI Rx Transfer size */ + uint16_t rx_count; /**< SPI Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + spi_state_t state; /**< SPI communication state */ + uint32_t err_code; /**< SPI error code */ + + void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ + void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ +} spi_handle_t; +/** + * @} + */ + +/** @defgroup SPI_Public_Macros SPI Public Macros + * @{ + */ +#define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET) +#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) +#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) +#define SPI_CRC_RESET(x) \ + do { \ + CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + } while (0) +#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +#define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +/** + * @} + */ + +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ +#define IS_SPI(x) (((x) == SPI0) || \ + ((x) == SPI1) || \ + ((x) == SPI2)) +#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \ + ((x) == SPI_CPHA_SECOND)) +#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \ + ((x) == SPI_CPOL_HIGH)) +#define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \ + ((x) == SPI_MODE_MASTER)) +#define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \ + ((x) == SPI_BAUD_4) || \ + ((x) == SPI_BAUD_8) || \ + ((x) == SPI_BAUD_16) || \ + ((x) == SPI_BAUD_32) || \ + ((x) == SPI_BAUD_64) || \ + ((x) == SPI_BAUD_128) || \ + ((x) == SPI_BAUD_256)) +#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \ + ((x) == SPI_DATA_SIZE_16)) +#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \ + ((x) == SPI_BID_TX)) +#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \ + ((x) == SPI_BIDMODE_SOLE)) +#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \ + ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((x) == SPI_DIRECTION_1LINE) || \ + ((x) == SPI_DIRECTION_1LINE_RX)) +#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \ + ((x) == SPI_DMA_REQ_RX)) +#define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \ + ((x) == SPI_SR_RXBNE) || \ + ((x) == SPI_SR_TXBE_RXBNE)) +#define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \ + ((x) == SPI_IT_RXBNE) || \ + ((x) == SPI_IT_TXBE)) +#define IS_SPI_IF(x) (((x) == SPI_IF_RXBNE) || \ + ((x) == SPI_IF_TXBE) || \ + ((x) == SPI_IF_CRCERR) || \ + ((x) == SPI_IF_MODF) || \ + ((x) == SPI_IF_OVE) || \ + ((x) == SPI_IF_BUSY)) +#define IS_SPI_STATUS(x) (((x) == SPI_STATUS_RXBNE) || \ + ((x) == SPI_STATUS_TXBE) || \ + ((x) == SPI_STATUS_CRCERR) || \ + ((x) == SPI_STATUS_MODEERR) || \ + ((x) == SPI_STATUS_OVERR) || \ + ((x) == SPI_STATUS_BUSY)) +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions + * @{ + */ + +/** @addtogroup SPI_Public_Functions_Group1 + * @{ + */ + +ald_status_t ald_spi_init(spi_handle_t *hperh); +void ald_spi_reset(spi_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group2 + * @{ + */ +int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data); +int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data); +uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh); +ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +ald_status_t ald_spi_dma_pause(spi_handle_t *hperh); +ald_status_t ald_spi_dma_resume(spi_handle_t *hperh); +ald_status_t ald_spi_dma_stop(spi_handle_t *hperh); +#endif +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group3 + * @{ + */ +void ald_spi_irq_handler(spi_handle_t *hperh); +void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state); +void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed); +void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state); +it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it); +flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status); +flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag); +void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag); +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group4 + * @{ + */ +spi_state_t ald_spi_get_state(spi_handle_t *hperh); +uint32_t ald_spi_get_error(spi_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h similarity index 50% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h index 22ef750f702191fe78d6be39165fc42d910d0d32..d173be011f324fc1bfbb603fbef600f7f14bdebe 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -36,33 +36,33 @@ extern "C" { /** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros * @{ */ -#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0) -#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996) -#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) - -#define BOOT_FROM_BOOT_ROM() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -#define BOOT_FROM_BOOT_FLASH() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -#define BOOT_FROM_FLASH() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) +#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0) +#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996) +#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) + +#define BOOT_FROM_BOOT_ROM() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) + +#define BOOT_FROM_BOOT_FLASH() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) + +#define BOOT_FROM_FLASH() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) /** * @} */ @@ -71,7 +71,7 @@ do { \ /** @defgroup SYSCFG_Public_Functions SYSCFG Public Functions * @{ */ -__STATIC_INLINE__ void vtor_config(uint32_t offset, type_func_t status) +__STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status) { SYSCFG_UNLOCK(); diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..9fe5ee6d6445ab35e2f8e49becf616b63f24c3c9 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -0,0 +1,1193 @@ +/** + ********************************************************************************* + * + * @file ald_timer.h + * @brief TIMER module driver. + * This is the common part of the TIMER initialization + * + * @version V1.0 + * @date 06 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_TIMER_H__ +#define __ALD_TIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_Public_Types TIMER Public Types + * @{ + */ + +/** + * @brief TIMER counter mode + */ +typedef enum +{ + TIMER_CNT_MODE_UP = 0, /**< Counter mode up */ + TIMER_CNT_MODE_DOWN = 1, /**< Counter mode down */ + TIMER_CNT_MODE_CENTER1 = 2, /**< Counter mode center1 */ + TIMER_CNT_MODE_CENTER2 = 3, /**< Counter mode center2 */ + TIMER_CNT_MODE_CENTER3 = 4, /**< Counter mode center3 */ +} timer_cnt_mode_t; + +/** + * @brief TIMER clock division + */ +typedef enum +{ + TIMER_CLOCK_DIV1 = 0, /**< No prescaler is used */ + TIMER_CLOCK_DIV2 = 1, /** Clock is divided by 2 */ + TIMER_CLOCK_DIV4 = 2, /** Clock is divided by 4 */ +} timer_clock_division_t; + +/** + * @brief TIMER output compare and PWM modes + */ +typedef enum +{ + TIMER_OC_MODE_TIMERING = 0, /**< Output compare mode is timering */ + TIMER_OC_MODE_ACTIVE = 1, /**< Output compare mode is active */ + TIMER_OC_MODE_INACTIVE = 2, /**< Output compare mode is inactive */ + TIMER_OC_MODE_TOGGLE = 3, /**< Output compare mode is toggle */ + TIMER_OC_MODE_FORCE_INACTIVE = 4, /**< Output compare mode is force inactive */ + TIMER_OC_MODE_FORCE_ACTIVE = 5, /**< Output compare mode is force active */ + TIMER_OC_MODE_PWM1 = 6, /**< Output compare mode is pwm1 */ + TIMER_OC_MODE_PWM2 = 7, /**< Output compare mode is pwm2 */ +} timer_oc_mode_t; + +/** + * @brief TIMER output compare polarity + */ +typedef enum +{ + TIMER_OC_POLARITY_HIGH = 0, /**< Output compare polarity is high */ + TIMER_OC_POLARITY_LOW = 1, /**< Output compare polarity is low */ +} timer_oc_polarity_t; + +/** + * @brief TIMER complementary output compare polarity + */ +typedef enum +{ + TIMER_OCN_POLARITY_HIGH = 0, /**< Complementary output compare polarity is high */ + TIMER_OCN_POLARITY_LOW = 1, /**< Complementary output compare polarity is low */ +} timer_ocn_polarity_t; + +/** + * @brief TIMER output compare idle state + */ +typedef enum +{ + TIMER_OC_IDLE_RESET = 0, /**< Output compare idle state is reset */ + TIMER_OC_IDLE_SET = 1, /**< Output compare idle state is set */ +} timer_oc_idle_t; + +/** + * @brief TIMER complementary output compare idle state + */ +typedef enum +{ + TIMER_OCN_IDLE_RESET = 0, /**< Complementary output compare idle state is reset */ + TIMER_OCN_IDLE_SET = 1, /**< Complementary output compare idle state is set */ +} timer_ocn_idle_t; + +/** + * @brief TIMER channel + */ +typedef enum +{ + TIMER_CHANNEL_1 = 0, /**< Channel 1 */ + TIMER_CHANNEL_2 = 1, /**< Channel 2 */ + TIMER_CHANNEL_3 = 2, /**< Channel 3 */ + TIMER_CHANNEL_4 = 4, /**< Channel 4 */ + TIMER_CHANNEL_ALL = 0xF, /**< All channel */ +} timer_channel_t; + +/** + * @brief TIMER one pulse mode + */ +typedef enum +{ + TIMER_OP_MODE_REPEAT = 0, /**< Repetitive */ + TIMER_OP_MODE_SINGLE = 1, /**< single */ +} timer_op_mode_t; + +/** + * @brief TIMER one pulse output channel + */ +typedef enum +{ + TIMER_OP_OUTPUT_CHANNEL_1 = 0, /**< One pulse output channal 1 */ + TIMER_OP_OUTPUT_CHANNEL_2 = 1, /**< One pulse output channal 2 */ +} timer_op_output_channel_t; + +/** + * @brief TIMER time base configuration structure definition + */ +typedef struct +{ + uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ + timer_cnt_mode_t mode; /**< Specifies the counter mode. */ + uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ + timer_clock_division_t clk_div; /**< Specifies the clock division.*/ + uint32_t re_cnt; /**< Specifies the repetition counter value. */ +} timer_base_init_t; + +/** + * @brief TIMER output compare configuration structure definition + */ +typedef struct +{ + timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ + uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ + type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ +} timer_oc_init_t; + +/** + * @brief State structures definition + */ +typedef enum +{ + TIMER_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */ + TIMER_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + TIMER_STATE_BUSY = 0x02, /**< An internal process is ongoing */ + TIMER_STATE_TIMEREOUT = 0x03, /**< Timeout state */ + TIMER_STATE_ERROR = 0x04, /**< Reception process is ongoing */ +} timer_state_t; + +/** + * @brief Active channel structures definition + */ +typedef enum +{ + TIMER_ACTIVE_CHANNEL_1 = 0x01, /**< The active channel is 1 */ + TIMER_ACTIVE_CHANNEL_2 = 0x02, /**< The active channel is 2 */ + TIMER_ACTIVE_CHANNEL_3 = 0x04, /**< The active channel is 3 */ + TIMER_ACTIVE_CHANNEL_4 = 0x08, /**< The active channel is 4 */ + TIMER_ACTIVE_CHANNEL_CLEARED = 0x00, /**< All active channels cleared */ +} timer_active_channel_t; + +/** + * @brief TIMER time base handle structure definition + */ +typedef struct timer_handle_s +{ + TIMER_TypeDef *perh; /**< Register base address */ + timer_base_init_t init; /**< TIMER Time Base required parameters */ + timer_active_channel_t ch; /**< Active channel */ + lock_state_t lock; /**< Locking object */ + timer_state_t state; /**< TIMER operation state */ + + void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ + void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ + void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ + void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ + void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ + void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ + void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ + void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ +} timer_handle_t; + + +/** + * @brief TIMER encoder mode + */ +typedef enum +{ + TIMER_ENC_MODE_TI1 = 1, /**< encoder mode 1 */ + TIMER_ENC_MODE_TI2 = 2, /**< encoder mode 2 */ + TIMER_ENC_MODE_TI12 = 3, /**< encoder mode 3 */ +} timer_encoder_mode_t; + +/** + * @brief TIMER input capture polarity + */ +typedef enum +{ + TIMER_IC_POLARITY_RISE = 0, /**< Input capture polarity rising */ + TIMER_IC_POLARITY_FALL = 1, /**< Input capture polarity falling */ +} timer_ic_polarity_t; + +/** + *@brief TIMER input capture selection + */ +typedef enum +{ + TIMER_IC_SEL_DIRECT = 1, /**< IC1 -- TI1 */ + TIMER_IC_SEL_INDIRECT = 2, /**< IC1 -- TI2 */ + TIMER_IC_SEL_TRC = 3, /**< IC1 -- TRC */ +} timer_ic_select_t; + +/** + * @brief TIMER input capture prescaler + */ +typedef enum +{ + TIMER_IC_PSC_DIV1 = 0, /**< Capture performed once every 1 events */ + TIMER_IC_PSC_DIV2 = 1, /**< Capture performed once every 2 events */ + TIMER_IC_PSC_DIV4 = 2, /**< Capture performed once every 4 events */ + TIMER_IC_PSC_DIV8 = 3, /**< Capture performed once every 4 events */ +} timer_ic_prescaler_t; + +/** + * @brief TIMER encoder configuration structure definition + */ +typedef struct +{ + timer_encoder_mode_t mode; /**< Specifies the encoder mode */ + timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic1_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic1_filter; /**< Specifies the input capture filter */ + timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic2_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic2_filter; /**< Specifies the input capture filter */ +} timer_encoder_init_t; + +/** + * @brief TIMER input capture configuration structure definition + */ +typedef struct +{ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter */ +} timer_ic_init_t; + +/** + * @brief TIMER one pulse mode configuration structure definition + */ +typedef struct +{ + timer_oc_mode_t mode; /**< Specifies the TIMER mode */ + uint16_t pulse; /**< Specifies the pulse value */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + uint32_t filter; /**< Specifies the input capture filter */ +} timer_one_pulse_init_t; + +/** @brief TIMER clear input source + */ +typedef enum +{ + TIMER_INPUT_NONE = 0, /**< Clear input none */ + TIMER_INPUT_ETR = 1, /**< Clear input etr */ +} timer_clear_input_source_t; + +/** @brief TIMER clear input polarity + */ +typedef enum +{ + TIMER_POLARITY_NO_INV = 0, /**< Polarity for ETRx pin */ + TIMER_POLARITY_INV = 1, /**< Polarity for ETRx pin */ +} timer_clear_input_polarity_t; + +/** @brief TIMER clear input polarity + */ +typedef enum +{ + TIMER_ETR_PSC_DIV1 = 0, /**< No prescaler is used */ + TIMER_ETR_PSC_DIV2 = 1, /**< ETR input source is divided by 2 */ + TIMER_ETR_PSC_DIV4 = 2, /**< ETR input source is divided by 4 */ + TIMER_ETR_PSC_DIV8 = 3, /**< ETR input source is divided by 8 */ +} timer_etr_psc_t; + +/** + * @brief TIMER clear input configuration handle structure definition + */ +typedef struct +{ + type_func_t state; /**< TIMER clear Input state */ + timer_clear_input_source_t source; /**< TIMER clear Input sources */ + timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ + timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ + uint32_t filter; /**< TIMER Clear Input filter */ +} timer_clear_input_config_t; + +/** @brief TIMER clock source + */ +typedef enum +{ + TIMER_SRC_ETRMODE2 = 0, /**< Clock source is etr mode2 */ + TIMER_SRC_INTER = 1, /**< Clock source is etr internal */ + TIMER_SRC_ITR0 = 2, /**< Clock source is etr itr0 */ + TIMER_SRC_ITR1 = 3, /**< Clock source is etr itr1 */ + TIMER_SRC_ITR2 = 4, /**< Clock source is etr itr2 */ + TIMER_SRC_ITR3 = 5, /**< Clock source is etr itr3 */ + TIMER_SRC_TI1ED = 6, /**< Clock source is etr ti1ed */ + TIMER_SRC_TI1 = 7, /**< Clock source is etr ti1 */ + TIMER_SRC_TI2 = 8, /**< Clock source is etr ti2 */ + TIMER_SRC_ETRMODE1 = 9, /**< Clock source is etr mode1 */ +} timer_clock_source_t; + +/** @brief TIMER clock polarity + */ +typedef enum +{ + TIMER_CLK_POLARITY_INV = 1, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_NO_INV = 0, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_RISE = 0, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_FALL = 1, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_BOTH = 3, /**< Polarity for TIx clock sources */ +} timer_clock_polarity_t; + +/** + * @brief TIMER clock config structure definition + */ +typedef struct +{ + timer_clock_source_t source; /**< TIMER clock sources */ + timer_clock_polarity_t polarity; /**< TIMER clock polarity */ + timer_etr_psc_t psc; /**< TIMER clock prescaler */ + uint32_t filter; /**< TIMER clock filter */ +} timer_clock_config_t; + +/** + * @brief TIMER slave mode + */ +typedef enum +{ + TIMER_MODE_DISABLE = 0, /**< Slave mode is disable */ + TIMER_MODE_ENC1 = 1, /**< Slave mode is encoder1 */ + TIMER_MODE_ENC2 = 2, /**< Slave mode is encoder2 */ + TIMER_MODE_ENC3 = 3, /**< Slave mode is encoder3 */ + TIMER_MODE_RESET = 4, /**< Slave mode is reset */ + TIMER_MODE_GATED = 5, /**< Slave mode is gated */ + TIMER_MODE_TRIG = 6, /**< Slave mode is trigger */ + TIMER_MODE_EXTERNAL1 = 7, /**< Slave mode is external1 */ +} timer_slave_mode_t; + +/** + * @brief TIMER ts definition + */ +typedef enum +{ + TIMER_TS_ITR0 = 0, /**< ITR0 */ + TIMER_TS_ITR1 = 1, /**< ITR1 */ + TIMER_TS_ITR2 = 2, /**< ITR2 */ + TIMER_TS_ITR3 = 3, /**< ITR3 */ + TIMER_TS_TI1F_ED = 4, /**< TI1F_ED */ + TIMER_TS_TI1FP1 = 5, /**< TI1FP1 */ + TIMER_TS_TI2FP2 = 6, /**< TI2FP2 */ + TIMER_TS_ETRF = 7, /**< ETRF */ +} timer_ts_t; + +/** + * @brief TIMER slave configuration structure definition + */ +typedef struct +{ + timer_slave_mode_t mode; /**< Slave mode selection */ + timer_ts_t input; /**< Input Trigger source */ + timer_clock_polarity_t polarity; /**< Input Trigger polarity */ + timer_etr_psc_t psc; /**< Input trigger prescaler */ + uint32_t filter; /**< Input trigger filter */ +} timer_slave_config_t; + +/** + * @brief TIMER hall sensor configuretion structure definition + */ +typedef struct +{ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */ + uint32_t delay; /**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */ +} timer_hall_sensor_init_t; + +/** + * @brief TIMER lock level + */ +typedef enum +{ + TIMER_LOCK_LEVEL_OFF = 0, /**< Lock off */ + TIMER_LOCK_LEVEL_1 = 1, /**< Lock level 1 */ + TIMER_LOCK_LEVEL_2 = 2, /**< Lock level 2 */ + TIMER_LOCK_LEVEL_3 = 3, /**< Lock level 3 */ +} timer_lock_level_t; + +/** + * @brief TIMER break polarity + */ +typedef enum +{ + TIMER_BREAK_POLARITY_LOW = 0, /**< LOW */ + TIMER_BREAK_POLARITY_HIGH = 1, /**< HIGH */ +} timer_break_polarity_t; + +/** + * @brief TIMER break and dead time configuretion structure definition + */ +typedef struct +{ + type_func_t off_run; /**< Enalbe/Disable off state in run mode */ + type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */ + timer_lock_level_t lock_level; /**< Lock level */ + uint32_t dead_time; /**< Dead time, [0x0, 0xFF] */ + type_func_t break_state; /**< Break state */ + timer_break_polarity_t polarity; /**< Break input polarity */ + type_func_t auto_out; /**< Enalbe/Disable automatic output */ +} timer_break_dead_time_t; + +/** + * @brief TIMER commutation event channel configuretion structure definition + */ +typedef struct +{ + type_func_t en; /**< Enalbe/Disable the channel */ + type_func_t n_en; /**< Enalbe/Disable the complementary channel */ + timer_oc_mode_t mode; /**< Mode of the channel */ +} timer_channel_config_t; + +/** + * @brief TIMER commutation event configuretion structure definition + */ +typedef struct +{ + timer_channel_config_t ch[3]; /**< Configure of channel */ +} timer_com_channel_config_t; + +/** + * @brief TIMER master mode selection + */ +typedef enum +{ + TIMER_TRGO_RESET = 0, /**< RESET */ + TIMER_TRGO_ENABLE = 1, /**< ENABLE */ + TIMER_TRGO_UPDATE = 2, /**< UPDATE */ + TIMER_TRGO_OC1 = 3, /**< OC1 */ + TIMER_TRGO_OC1REF = 4, /**< OC1REF */ + TIMER_TRGO_OC2REF = 5, /**< OC2REF */ + TIMER_TRGO_OC3REF = 6, /**< OC3REF */ + TIMER_TRGO_OC4REF = 7, /**< OC4REF */ +} timer_master_mode_sel_t; + +/** + * @brief TIMER master configuretion structure definition + */ +typedef struct +{ + timer_master_mode_sel_t sel; /**< Specifies the active edge of the input signal */ + type_func_t master_en; /**< Master/Slave mode selection */ +} timer_master_config_t; + +/** + * @brief Specifies the event source + */ +typedef enum +{ + TIMER_SRC_UPDATE = (1U << 0), /**< Event source is update */ + TIMER_SRC_CC1 = (1U << 1), /**< Event source is channel1 */ + TIMER_SRC_CC2 = (1U << 2), /**< Event source is channel2 */ + TIMER_SRC_CC3 = (1U << 3), /**< Event source is channel3 */ + TIMER_SRC_CC4 = (1U << 4), /**< Event source is channel4 */ + TIMER_SRC_COM = (1U << 5), /**< Event source is compare */ + TIMER_SRC_TRIG = (1U << 6), /**< Event source is trigger */ + TIMER_SRC_BREAK = (1U << 7), /**< Event source is break */ +} timer_event_source_t; + +/** + * @brief TIMER interrupt definition + */ +typedef enum +{ + TIMER_IT_UPDATE = (1U << 0), /**< Update interrupt bit */ + TIMER_IT_CC1 = (1U << 1), /**< Channel1 interrupt bit */ + TIMER_IT_CC2 = (1U << 2), /**< Channel2 interrupt bit */ + TIMER_IT_CC3 = (1U << 3), /**< Channel3 interrupt bit */ + TIMER_IT_CC4 = (1U << 4), /**< Channel4 interrupt bit */ + TIMER_IT_COM = (1U << 5), /**< compare interrupt bit */ + TIMER_IT_TRIGGER = (1U << 6), /**< Trigger interrupt bit */ + TIMER_IT_BREAK = (1U << 7), /**< Break interrupt bit */ +} timer_it_t; + +/** + * @brief TIMER DMA request + */ +typedef enum +{ + TIMER_DMA_UPDATE = (1U << 8), /**< DMA request from update */ + TIMER_DMA_CC1 = (1U << 9), /**< DMA request from channel1 */ + TIMER_DMA_CC2 = (1U << 10), /**< DMA request from channel2 */ + TIMER_DMA_CC3 = (1U << 11), /**< DMA request from channel3 */ + TIMER_DMA_CC4 = (1U << 12), /**< DMA request from channel4 */ + TIMER_DMA_COM = (1U << 13), /**< DMA request from compare */ + TIMER_DMA_TRIGGER = (1U << 14), /**< DMA request from trigger */ +} timer_dma_req_t; + +/** + * @brief TIMER flag definition + */ +typedef enum +{ + TIMER_FLAG_UPDATE = (1U << 0), /**< Update interrupt flag */ + TIMER_FLAG_CC1 = (1U << 1), /**< Channel1 interrupt flag */ + TIMER_FLAG_CC2 = (1U << 2), /**< Channel2 interrupt flag */ + TIMER_FLAG_CC3 = (1U << 3), /**< Channel3 interrupt flag */ + TIMER_FLAG_CC4 = (1U << 4), /**< Channel4 interrupt flag */ + TIMER_FLAG_COM = (1U << 5), /**< Compare interrupt flag */ + TIMER_FLAG_TRIGGER = (1U << 6), /**< Trigger interrupt flag */ + TIMER_FLAG_BREAK = (1U << 7), /**< Break interrupt flag */ + TIMER_FLAG_CC1OF = (1U << 9), /**< Channel1 override state flag */ + TIMER_FLAG_CC2OF = (1U << 10), /**< Channel2 override state flag */ + TIMER_FLAG_CC3OF = (1U << 11), /**< Channel3 override state flag */ + TIMER_FLAG_CC4OF = (1U << 12), /**< Channel4 override state flag */ +} timer_flag_t; +/** + * @} + */ + +/** @defgroup TIMER_Public_Macros TIMER Public Macros + * @{ + */ +#define CCER_CCxE_MASK ((1U << 0) | (1U << 4) | (1U << 8) | (1U << 12)) +#define CCER_CCxNE_MASK ((1U << 2) | (1U << 6) | (1U << 10)) + +/** + * @brief Reset TIMER handle state + */ +#define TIMER_RESET_HANDLE_STATE(hperh) ((hperh)->state = TIMER_STATE_RESET) + +/** + * @brief Enable the TIMER peripheral. + */ +#define TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK)) + +/** + * @brief Enable the TIMER main output. + */ +#define TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK)) + +/** + * @brief Disable the TIMER peripheral. + */ +#define TIMER_DISABLE(hperh) \ + do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ + } while (0) + +/** + * @brief Disable the TIMER main output. + * @note The Main Output Enable of a timer instance is disabled only if + * all the CCx and CCxN channels have been disabled + */ +#define TIMER_MOE_DISABLE(hperh) \ + do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ + } while (0) + +/** + * @brief Sets the TIMER autoreload register value on runtime without calling + * another time any Init function. + */ +#define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ + do { \ + (handle)->perh->AR = (AUTORELOAD); \ + (handle)->init.period = (AUTORELOAD); \ + } while (0) + +/** + * @brief Gets the TIMER autoreload register value on runtime + */ +#define TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR) + +/** + * @brief Gets the TIMER count register value on runtime + */ +#define TIMER_GET_CNT(handle) ((handle)->perh->COUNT) + +/** + * @brief Gets the TIMER count direction value on runtime + */ +#define TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS)) + +/** + * @brief CCx DMA request sent when CCx event occurs + */ +#define TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief CCx DMA request sent when update event occurs + */ +#define TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief Enable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ + (SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) + +/** + * @brief Disable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ + (CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) + +/** + * @brief Enable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) + +/** + * @brief Disable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) +/** + * @} + */ + +/** @defgroup TIMER_Private_Macros TIMER Private Macros + * @{ + */ +#if defined (ES32F065x) +#define IS_TIMER_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1) || \ + ((x) == BS16T0) || \ + ((x) == BS16T1) || \ + ((x) == BS16T2) || \ + ((x) == BS16T3)) +#define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T0) +#define IS_TIMER_XOR_INSTANCE(x) (((x) == AD16C4T0) || ((x) == GP16C4T0)) +#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_CC4_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C4T0)) +#define IS_TIMER_BREAK_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) +#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) +#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == AD16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) + +#elif defined (ES32F033x) || defined (ES32F093x) + +#define IS_TIMER_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == BS16T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1) || \ + ((x) == BS16T1) || \ + ((x) == BS16T2) || \ + ((x) == GP16C4T1) || \ + ((x) == BS16T3)) +#define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T0) +#define IS_TIMER_XOR_INSTANCE(x) (((x) == GP16C4T0) || ((x) == GP16C4T1)) +#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_CC2_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1) || \ + ((x) == GP16C4T1)) +#define IS_TIMER_CC4_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C4T1)) +#define IS_TIMER_BREAK_INSTANCE(x) (((x) == GP16C4T0)) +#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) +#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) +#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) +#endif + +#define IS_TIMER_COUNTER_MODE(x) (((x) == TIMER_CNT_MODE_UP) || \ + ((x) == TIMER_CNT_MODE_DOWN) || \ + ((x) == TIMER_CNT_MODE_CENTER1) || \ + ((x) == TIMER_CNT_MODE_CENTER2) || \ + ((x) == TIMER_CNT_MODE_CENTER3)) +#define IS_TIMER_CLOCK_DIVISION(x) (((x) == TIMER_CLOCK_DIV1) || \ + ((x) == TIMER_CLOCK_DIV2) || \ + ((x) == TIMER_CLOCK_DIV4)) +#define IS_TIMER_PWM_MODE(x) (((x) == TIMER_OC_MODE_PWM1) || \ + ((x) == TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_MODE(x) (((x) == TIMER_OC_MODE_TIMERING) || \ + ((x) == TIMER_OC_MODE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_TOGGLE) || \ + ((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_PWM1) || \ + ((x) == TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_POLARITY(x) (((x) == TIMER_OC_POLARITY_HIGH) || \ + ((x) == TIMER_OC_POLARITY_LOW)) +#define IS_TIMER_OCN_POLARITY(x) (((x) == TIMER_OCN_POLARITY_HIGH) || \ + ((x) == TIMER_OCN_POLARITY_LOW)) +#define IS_TIMER_OCIDLE_STATE(x) (((x) == TIMER_OC_IDLE_RESET) || \ + ((x) == TIMER_OC_IDLE_SET)) +#define IS_TIMER_OCNIDLE_STATE(x) (((x) == TIMER_OCN_IDLE_RESET) || \ + ((x) == TIMER_OCN_IDLE_SET)) +#define IS_TIMER_CHANNELS(x) (((x) == TIMER_CHANNEL_1) || \ + ((x) == TIMER_CHANNEL_2) || \ + ((x) == TIMER_CHANNEL_3) || \ + ((x) == TIMER_CHANNEL_4) || \ + ((x) == TIMER_CHANNEL_ALL)) +#define IS_TIMER_OP_MODE(x) (((x) == TIMER_OP_MODE_REPEAT) || \ + ((x) == TIMER_OP_MODE_SINGLE)) +#define IS_TIMER_OP_OUTPUT_CH(x) (((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \ + ((x) == TIMER_OP_OUTPUT_CHANNEL_2)) +#define IS_TIMER_ENCODER_MODE(x) (((x) == TIMER_ENC_MODE_TI1) || \ + ((x) == TIMER_ENC_MODE_TI2) || \ + ((x) == TIMER_ENC_MODE_TI12)) +#define IS_TIMER_IC_POLARITY(x) (((x) == TIMER_IC_POLARITY_RISE) || \ + ((x) == TIMER_IC_POLARITY_FALL)) +#define IS_TIMER_IC_SELECT(x) (((x) == TIMER_IC_SEL_DIRECT) || \ + ((x) == TIMER_IC_SEL_INDIRECT) || \ + ((x) == TIMER_IC_SEL_TRC)) +#define IS_TIMER_IC_PSC(x) (((x) == TIMER_IC_PSC_DIV1) || \ + ((x) == TIMER_IC_PSC_DIV2) || \ + ((x) == TIMER_IC_PSC_DIV4) || \ + ((x) == TIMER_IC_PSC_DIV8)) +#define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) +#define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) +#define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == TIMER_INPUT_NONE) || \ + ((x) == TIMER_INPUT_ETR)) +#define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == TIMER_POLARITY_NO_INV) || \ + ((x) == TIMER_POLARITY_INV)) +#define IS_TIMER_ETR_PSC(x) (((x) == TIMER_ETR_PSC_DIV1) || \ + ((x) == TIMER_ETR_PSC_DIV2) || \ + ((x) == TIMER_ETR_PSC_DIV4) || \ + ((x) == TIMER_ETR_PSC_DIV8)) +#define IS_TIMER_CLOCK_SOURCE(x) (((x) == TIMER_SRC_ETRMODE2) || \ + ((x) == TIMER_SRC_INTER) || \ + ((x) == TIMER_SRC_ITR0) || \ + ((x) == TIMER_SRC_ITR1) || \ + ((x) == TIMER_SRC_ITR2) || \ + ((x) == TIMER_SRC_ITR3) || \ + ((x) == TIMER_SRC_TI1ED) || \ + ((x) == TIMER_SRC_TI1) || \ + ((x) == TIMER_SRC_TI2) || \ + ((x) == TIMER_SRC_ETRMODE1)) +#define IS_TIMER_CLOCK_POLARITY(x) (((x) == TIMER_CLK_POLARITY_INV) || \ + ((x) == TIMER_CLK_POLARITY_NO_INV) || \ + ((x) == TIMER_CLK_POLARITY_RISE) || \ + ((x) == TIMER_CLK_POLARITY_FALL) || \ + ((x) == TIMER_CLK_POLARITY_BOTH)) +#define IS_TIMER_SLAVE_MODE(x) (((x) == TIMER_MODE_DISABLE) || \ + ((x) == TIMER_MODE_ENC1) || \ + ((x) == TIMER_MODE_ENC2) || \ + ((x) == TIMER_MODE_ENC3) || \ + ((x) == TIMER_MODE_RESET) || \ + ((x) == TIMER_MODE_GATED) || \ + ((x) == TIMER_MODE_TRIG) || \ + ((x) == TIMER_MODE_EXTERNAL1)) +#define IS_TIMER_EVENT_SOURCE(x) (((x) == TIMER_SRC_UPDATE) || \ + ((x) == TIMER_SRC_CC1) || \ + ((x) == TIMER_SRC_CC2) || \ + ((x) == TIMER_SRC_CC3) || \ + ((x) == TIMER_SRC_CC4) || \ + ((x) == TIMER_SRC_COM) || \ + ((x) == TIMER_SRC_TRIG) || \ + ((x) == TIMER_SRC_BREAK)) +#define IS_TIMER_TS(x) (((x) == TIMER_TS_ITR0) || \ + ((x) == TIMER_TS_ITR1) || \ + ((x) == TIMER_TS_ITR2) || \ + ((x) == TIMER_TS_ITR3) || \ + ((x) == TIMER_TS_TI1F_ED) || \ + ((x) == TIMER_TS_TI1FP1) || \ + ((x) == TIMER_TS_TI2FP2) || \ + ((x) == TIMER_TS_ETRF)) +#define IS_TIMER_CLOCK_LEVEL(x) (((x) == TIMER_LOCK_LEVEL_OFF) || \ + ((x) == TIMER_LOCK_LEVEL_1) || \ + ((x) == TIMER_LOCK_LEVEL_2) || \ + ((x) == TIMER_LOCK_LEVEL_3)) +#define IS_TIMER_BREAK_POLARITY(x) (((x) == TIMER_BREAK_POLARITY_LOW) || \ + ((x) == TIMER_BREAK_POLARITY_HIGH)) +#define IS_TIMER_MASTER_MODE_SEL(x) (((x) == TIMER_TRGO_RESET) || \ + ((x) == TIMER_TRGO_ENABLE) || \ + ((x) == TIMER_TRGO_UPDATE) || \ + ((x) == TIMER_TRGO_OC1) || \ + ((x) == TIMER_TRGO_OC1REF) || \ + ((x) == TIMER_TRGO_OC2REF) || \ + ((x) == TIMER_TRGO_OC3REF) || \ + ((x) == TIMER_TRGO_OC4REF)) +#define IS_TIMER_IT(x) (((x) == TIMER_IT_UPDATE) || \ + ((x) == TIMER_IT_CC1) || \ + ((x) == TIMER_IT_CC2) || \ + ((x) == TIMER_IT_CC3) || \ + ((x) == TIMER_IT_CC4) || \ + ((x) == TIMER_IT_COM) || \ + ((x) == TIMER_IT_TRIGGER) || \ + ((x) == TIMER_IT_BREAK)) +#define IS_TIMER_DMA_REQ(x) (((x) == TIMER_DMA_UPDATE) || \ + ((x) == TIMER_DMA_CC1) || \ + ((x) == TIMER_DMA_CC2) || \ + ((x) == TIMER_DMA_CC3) || \ + ((x) == TIMER_DMA_CC4) || \ + ((x) == TIMER_DMA_COM) || \ + ((x) == TIMER_DMA_TRIGGER)) +#define IS_TIMER_FLAG(x) (((x) == TIMER_FLAG_UPDATE) || \ + ((x) == TIMER_FLAG_CC1) || \ + ((x) == TIMER_FLAG_CC2) || \ + ((x) == TIMER_FLAG_CC3) || \ + ((x) == TIMER_FLAG_CC4) || \ + ((x) == TIMER_FLAG_COM) || \ + ((x) == TIMER_FLAG_TRIGGER) || \ + ((x) == TIMER_FLAG_BREAK) || \ + ((x) == TIMER_FLAG_CC1OF) || \ + ((x) == TIMER_FLAG_CC2OF) || \ + ((x) == TIMER_FLAG_CC3OF) || \ + ((x) == TIMER_FLAG_CC4OF)) +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions + * @{ + */ +/** @addtogroup TIMER_Public_Functions_Group1 + * @{ + */ +/* Time Base functions */ +ald_status_t ald_timer_base_init(timer_handle_t *hperh); +void ald_timer_base_reset(timer_handle_t *hperh); +void ald_timer_base_start(timer_handle_t *hperh); +void ald_timer_base_stop(timer_handle_t *hperh); +void ald_timer_base_start_by_it(timer_handle_t *hperh); +void ald_timer_base_stop_by_it(timer_handle_t *hperh); +#ifdef ALD_DMA +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_base_stop_by_dma(timer_handle_t *hperh); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group2 + * @{ + */ +/* Timer Output Compare functions */ +ald_status_t ald_timer_oc_init(timer_handle_t *hperh); +void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group3 + * @{ + */ +/* Timer PWM functions */ +ald_status_t ald_timer_pwm_init(timer_handle_t *hperh); +void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq); +void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty); +void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group4 + * @{ + */ +/* Timer Input Capture functions */ +ald_status_t ald_timer_ic_init(timer_handle_t *hperh); +void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group5 + * @{ + */ +/* Timer One Pulse functions */ +ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode); +void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group6 + * @{ + */ +/* Timer encoder functions */ +ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config); +void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, + uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2); +void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group7 + * @{ + */ +/* Timer hall sensor functions */ +ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config); +void ald_timer_hall_sensor_start(timer_handle_t *hperh); +void ald_timer_hall_sensor_stop(timer_handle_t *hperh); +void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh); +void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh); +#ifdef ALD_DMA +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group8 + * @{ + */ +/* Timer complementary output compare functions */ +void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group9 + * @{ + */ +/* Timer complementary PWM functions */ +void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group10 + * @{ + */ +/* Timer complementary one pulse functions */ +void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group11 + * @{ + */ +/* Control functions */ +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch); +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch); +ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, + timer_channel_t ch_out, timer_channel_t ch_in); +ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch); +ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config); +ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select); +ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config); +ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config); +ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event); +uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch); +void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config); +void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); +void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); +void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config); +void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config); +void ald_timer_irq_handler(timer_handle_t *hperh); +void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state); +void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state); +it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it); +flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag); +void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group12 + * @{ + */ +/* State functions */ +timer_state_t ald_timer_get_state(timer_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TIMER_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h new file mode 100644 index 0000000000000000000000000000000000000000..a1142838eb5fe1e247e0e5fea1e0fc93381d77ae --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -0,0 +1,210 @@ +/** + ********************************************************************************* + * + * @file ald_trng.h + * @brief Header file of TRNG module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_TRNG_H__ +#define __ALD_TRNG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TRNG + * @{ + */ + +/** @defgroup TRNG_Public_Types TRNG Public Types + * @{ + */ +/** + * @brief Data width + */ +typedef enum +{ + TRNG_DSEL_1B = 0x0, /**< 1-bit */ + TRNG_DSEL_8B = 0x1, /**< 8-bit */ + TRNG_DSEL_16B = 0x2, /**< 16-bit */ + TRNG_DSEL_32B = 0x3, /**< 32-bit */ +} trng_data_width_t; + +/** + * @brief seed type + */ +typedef enum +{ + TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */ + TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */ + TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */ + TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */ +} trng_seed_type_t; + +/** + * @brief TRNG init structure definition + */ +typedef struct +{ + trng_data_width_t data_width; /**< The width of data */ + trng_seed_type_t seed_type; /**< The seed type */ + uint32_t seed; /**< The value of seed */ + uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */ + uint8_t adjc; /**< Adjust parameter */ + type_func_t posten; /**< Data back handle function */ +} trng_init_t; + +/** + * @brief TRNG state structures definition + */ +typedef enum +{ + TRNG_STATE_RESET = 0x0, /**< Peripheral is not initialized */ + TRNG_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + TRNG_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + TRNG_STATE_ERROR = 0x4, /**< Error */ +} trng_state_t; + +/** + * @brief State type + */ +typedef enum +{ + TRNG_STATUS_START = (1U << 0), /**< Start state */ + TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ + TRNG_STATUS_SERR = (1U << 2), /**< Error state */ +} trng_status_t; + +/** + * @brief Interrupt type + */ +typedef enum +{ + TRNG_IT_START = (1U << 0), /**< Start */ + TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IT_SERR = (1U << 2), /**< Error */ +} trng_it_t; + +/** + * @brief Interrupt flag type + */ +typedef enum +{ + TRNG_IF_START = (1U << 0), /**< Start */ + TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IF_SERR = (1U << 2), /**< Error */ +} trng_flag_t; + +/** + * @brief TRNG Handle Structure definition + */ +typedef struct trng_handle_s +{ + TRNG_TypeDef *perh; /**< Register base address */ + trng_init_t init; /**< TRNG required parameters */ + uint32_t data; /**< result data */ + lock_state_t lock; /**< Locking object */ + trng_state_t state; /**< TRNG operation state */ + + void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */ + void (*err_cplt_cbk)(struct trng_handle_s *arg); /**< Trng error callback */ + void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */ +} trng_handle_t; +/** + * @} + */ + +/** @defgroup TRNG_Public_Macros TRNG Public Macros + * @{ + */ +#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) +#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) +#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) +#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) +/** + * @} + */ + +/** + * @defgroup TRNG_Private_Macros TRNG Private Macros + * @{ + */ +#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \ + ((x) == TRNG_DSEL_8B) || \ + ((x) == TRNG_DSEL_16B) || \ + ((x) == TRNG_DSEL_32B)) +#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \ + ((x) == TRNG_SEED_TYPE_1) || \ + ((x) == TRNG_SEED_TYPE_LAST) || \ + ((x) == TRNG_SEED_TYPE_SEED)) +#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \ + ((x) == TRNG_STATUS_DAVLD) || \ + ((x) == TRNG_STATUS_SERR)) +#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ + ((x) == TRNG_IT_DAVLD) || \ + ((x) == TRNG_IT_SERR)) +#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ + ((x) == TRNG_IF_DAVLD) || \ + ((x) == TRNG_IF_SERR)) +#define IS_TRNG_ADJC(x) ((x) < 4) +/** + * @} + */ + +/** @addtogroup TRNG_Public_Functions + * @{ + */ +/** @addtogroup TRNG_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern ald_status_t ald_trng_init(trng_handle_t *hperh); +/** + * @} + */ +/** @addtogroup TRNG_Public_Functions_Group2 + * @{ + */ +/* Control functions */ +extern uint32_t ald_trng_get_result(trng_handle_t *hperh); +extern void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state); +extern flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status); +extern it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it); +extern flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag); +extern void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag); +extern void ald_trng_irq_handler(trng_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TRNG_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h new file mode 100644 index 0000000000000000000000000000000000000000..0f55db2a2981f546e323e3ff1d7417558b01ed50 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h @@ -0,0 +1,227 @@ +/** + ********************************************************************************* + * + * @file ald_tsense.h + * @brief Header file of TSENSE module driver. + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_TSENSE_H__ +#define __ALD_TSENSE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TSENSE + * @{ + */ + +/** @defgroup TSENSE_Public_Macros TSENSE Public Macros + * @{ + */ +#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0)) +#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669)) +#define TSENSE_ENABLE() \ + do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_DISABLE() \ + do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_REQ_ENABLE() \ + do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_REQ_DISABLE() \ + do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_CTN_ENABLE() \ + do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_CTN_DISABLE() \ + do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_RESET() \ + do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_LTGR_WR(data) \ + do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->LTGR, (data)); \ + TSENSE_LOCK(); \ + } while(0) +#define TSENSE_HTGR_WR(data) \ + do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->HTGR, (data)); \ + TSENSE_LOCK(); \ + } while(0) +#define TSENSE_TBDR_WR(data) \ + do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TBDR, (data)); \ + TSENSE_LOCK(); \ + } while(0) +#define TSENSE_TCALBDR_WR(data) \ + do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TCALBDR, (data)); \ + TSENSE_LOCK(); \ + } while(0) +/** + * @} + */ + +/** @defgroup TSENSE_Public_Types TSENSE Public Types + * @{ + */ +/** + * @brief Temperature update time + */ +typedef enum +{ + TSENSE_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */ + TSENSE_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */ + TSENSE_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */ + TSENSE_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */ + TSENSE_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */ +} tsense_update_cycle_t; + +/** + * @brief Temperature output mode + */ +typedef enum +{ + TSENSE_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */ + TSENSE_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */ + TSENSE_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */ + TSENSE_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */ + TSENSE_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */ +} tsense_output_mode_t; + +/** + * @brief Source select + */ +typedef enum +{ + TSENSE_SOURCE_LOSC = 0x0, /**< LOSC */ + TSENSE_SOURCE_LRC = 0x1, /**< LRC */ + TSENSE_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ + TSENSE_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ +} tsense_source_sel_t; + + +/** + * @brief TSENSE init structure definition + */ +typedef struct +{ + tsense_update_cycle_t cycle; /**< Temperature update time */ + tsense_output_mode_t mode; /**< Temperature output mode */ + type_func_t ctn; /**< Continue mode */ + uint8_t psc; /**< Perscaler */ +} tsense_init_t; + +/** + * @brief Define callback function type + */ +typedef void (*tsense_cbk)(uint16_t value, ald_status_t status); +/** + * @} + */ + +/** + * @defgroup TSENSE_Private_Macros TSENSE Private Macros + * @{ + */ +#define IS_TSENSE_UPDATE_CYCLE(x) (((x) == TSENSE_UPDATE_CYCLE_3) || \ + ((x) == TSENSE_UPDATE_CYCLE_4) || \ + ((x) == TSENSE_UPDATE_CYCLE_5) || \ + ((x) == TSENSE_UPDATE_CYCLE_6) || \ + ((x) == TSENSE_UPDATE_CYCLE_7)) +#define IS_TSENSE_OUTPUT_MODE(x) (((x) == TSENSE_OUTPUT_MODE_200) || \ + ((x) == TSENSE_OUTPUT_MODE_400) || \ + ((x) == TSENSE_OUTPUT_MODE_800) || \ + ((x) == TSENSE_OUTPUT_MODE_1600) || \ + ((x) == TSENSE_OUTPUT_MODE_3200)) +#define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \ + ((x) == TSENSE_SOURCE_LRC) || \ + ((x) == TSENSE_SOURCE_HRC_DIV_1M ) || \ + ((x) == TSENSE_SOURCE_HOSC_DIV_1M)) +/** + * @} + */ + +/** @addtogroup TSENSE_Public_Functions + * @{ + */ +/** @addtogroup TSENSE_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void ald_tsense_init(tsense_init_t *init); +extern void ald_tsense_source_select(tsense_source_sel_t sel); +/** + * @} + */ +/** @addtogroup TSENSE_Public_Functions_Group2 + * @{ + */ +/* Control functions */ +extern ald_status_t ald_tsense_get_value(uint16_t *tsense); +extern void ald_tsense_get_value_by_it(tsense_cbk cbk); +extern void ald_tsense_irq_handler(void); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TSENSE_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..49cc24d9efb9d72fa7ce911da99613ccd353f702 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -0,0 +1,478 @@ +/** + ********************************************************************************* + * + * @file ald_uart.h + * @brief Header file of UART module library. + * + * @version V1.0 + * @date 21 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_UART_H__ +#define __ALD_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** + * @defgroup UART_Public_Macros UART Public Macros + * @{ + */ +#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) +#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) +#define UART_BRR_WRITE_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) +#define UART_BRR_WRITE_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) +#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) +#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) +#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) +#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) +#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) +#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) +#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) +#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) +#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) +#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) +#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) +#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) +#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) +#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) +#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_TFRST_MSK)) +#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_RFRST_MSK)) +#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) +#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) +#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) +#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) +#define UART_AUTOBR_RESTART(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABRRS_MSK)) +#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR)) +#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS)) +/** + * @} + */ + +/** @defgroup UART_Public_Types UART Public Types + * @{ + */ +/** + * @brief UART word length + */ +typedef enum +{ + UART_WORD_LENGTH_5B = 0x0, /**< 5-bits */ + UART_WORD_LENGTH_6B = 0x1, /**< 6-bits */ + UART_WORD_LENGTH_7B = 0x2, /**< 7-bits */ + UART_WORD_LENGTH_8B = 0x3, /**< 8-bits */ +} uart_word_length_t; + +/** + * @brief UART stop bits + */ +typedef enum +{ + UART_STOP_BITS_1 = 0x0, /**< 1-bits */ + UART_STOP_BITS_2 = 0x1, /**< 2-bits */ + UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */ + UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */ +} uart_stop_bits_t; + +/** + * @brief UART parity + */ +typedef enum +{ + UART_PARITY_NONE = 0x0, /**< Not parity */ + UART_PARITY_ODD = 0x1, /**< Odd parity */ + UART_PARITY_EVEN = 0x3, /**< Even parity */ +} uart_parity_t; + +/** + * @brief UART mode + */ +typedef enum +{ + UART_MODE_UART = 0x0, /**< UART */ + UART_MODE_LIN = 0x1, /**< LIN */ + UART_MODE_IrDA = 0x2, /**< IrDA */ + UART_MODE_RS485 = 0x3, /**< RS485 */ + UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */ +} uart_mode_t; + +/** + * @brief UART hardware flow control + */ +typedef enum +{ + UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */ + UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */ +} uart_hw_flow_ctl_t; + +/** + * @brief ALD UART state + */ +typedef enum +{ + UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ + UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ + UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ + UART_STATE_TIMEOUT = 0x03, /**< Timeout state */ + UART_STATE_ERROR = 0x04, /**< Error */ +} uart_state_t; + +/** + * @brief UART error codes + */ +typedef enum +{ + UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ + UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ + UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ + UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ + UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ + UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +} uart_error_t; + +/** + * @brief UART init structure definition + */ +typedef struct +{ + uint32_t baud; /**< Specifies the uart communication baud rate */ + uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ + uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ + uart_parity_t parity; /**< Specifies the parity mode */ + uart_mode_t mode; /**< Specifies uart mode */ + uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ +} uart_init_t; + +/** + * @brief UART handle structure definition + */ +typedef struct uart_handle_s +{ + UART_TypeDef *perh; /**< UART registers base address */ + uart_init_t init; /**< UART communication parameters */ + uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ + uint16_t tx_size; /**< UART Tx Transfer size */ + uint16_t tx_count; /**< UART Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ + uint16_t rx_size; /**< UART Rx Transfer size */ + uint16_t rx_count; /**< UART Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + uart_state_t state; /**< UART communication state */ + uart_error_t err_code; /**< UART Error code */ + + void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ +} uart_handle_t; + +/** + * @brief UART RS485 configure structure definition + */ +typedef struct +{ + type_func_t normal; /**< Normal mode */ + type_func_t dir; /**< Auto-direction mode */ + type_func_t invert; /**< Address detection invert */ + uint8_t addr; /**< Address for compare */ +} uart_rs485_config_t; + +/** + * @brief LIN detection break length + */ +typedef enum +{ + LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */ + LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */ +} uart_lin_break_len_t; + +/** + * @brief UART TXFIFO size + */ +typedef enum +{ + UART_TXFIFO_EMPTY = 0x0, /**< Empty */ + UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */ + UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */ + UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */ +} uart_txfifo_t; + +/** + * @brief UART RXFIFO size + */ +typedef enum +{ + UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */ + UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */ + UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */ + UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */ +} uart_rxfifo_t; + +/** + * @brief UART auto-baud mode + */ +typedef enum +{ + UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */ + UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */ + UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */ +} uart_auto_baud_mode_t; + +/** + * @brief UART status types + */ +typedef enum +{ + UART_STATUS_DR = (1U << 0), /**< Data ready */ + UART_STATUS_OE = (1U << 1), /**< Overrun error */ + UART_STATUS_PE = (1U << 2), /**< Parity error */ + UART_STATUS_FE = (1U << 3), /**< Framing error */ + UART_STATUS_BI = (1U << 4), /**< Break interrupt */ + UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */ + UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */ + UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */ + UART_STATUS_BUSY = (1U << 8), /**< UART busy */ + UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */ + UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */ + UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */ + UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */ + UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */ + UART_STATUS_CTS = (1U << 15), /**< Clear to send */ +} uart_status_t; + +/** + * @brief UART interrupt types + */ +typedef enum +{ + UART_IT_RXRD = (1U << 0), /**< Receive data available */ + UART_IT_TXS = (1U << 1), /**< Tx empty status */ + UART_IT_RXS = (1U << 2), /**< Rx line status */ + UART_IT_MDS = (1U << 3), /**< Modem status */ + UART_IT_RTO = (1U << 4), /**< Receiver timeout */ + UART_IT_BZ = (1U << 5), /**< Busy status */ + UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */ + UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ + UART_IT_LINBK = (1U << 8), /**< Lin break detection */ + UART_IT_TC = (1U << 9), /**< Transmission complete */ + UART_IT_EOB = (1U << 10), /**< End of block */ + UART_IT_CM = (1U << 11), /**< Character match */ +} uart_it_t; + +/** + * @brief UART flags types + */ +typedef enum +{ + UART_IF_RXRD = (1U << 0), /**< Receive data available */ + UART_IF_TXS = (1U << 1), /**< Tx empty status */ + UART_IF_RXS = (1U << 2), /**< Rx line status */ + UART_IF_MDS = (1U << 3), /**< Modem status */ + UART_IF_RTO = (1U << 4), /**< Receiver timeout */ + UART_IF_BZ = (1U << 5), /**< Busy status */ + UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */ + UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ + UART_IF_LINBK = (1U << 8), /**< Lin break detection */ + UART_IF_TC = (1U << 9), /**< Transmission complete */ + UART_IF_EOB = (1U << 10), /**< End of block */ + UART_IF_CM = (1U << 11), /**< Character match */ +} uart_flag_t; +/** + * @} + */ + +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_ALL(x) (((x) == UART0) || \ + ((x) == UART1) || \ + ((x) == UART2) || \ + ((x) == UART3)) +#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \ + ((x) == UART_WORD_LENGTH_6B) || \ + ((x) == UART_WORD_LENGTH_7B) || \ + ((x) == UART_WORD_LENGTH_8B)) +#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \ + ((x) == UART_STOP_BITS_2) || \ + ((x) == UART_STOP_BITS_0_5) || \ + ((x) == UART_STOP_BITS_1_5)) +#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \ + ((x) == UART_PARITY_ODD) || \ + ((x) == UART_PARITY_EVEN)) +#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \ + ((x) == UART_MODE_LIN) || \ + ((x) == UART_MODE_IrDA) || \ + ((x) == UART_MODE_RS485) || \ + ((x) == UART_MODE_HDSEL)) +#define IS_UART_HARDWARE_FLOW_CONTROL(x) \ + (((x) == UART_HW_FLOW_CTL_DISABLE) || \ + ((x) == UART_HW_FLOW_CTL_ENABLE)) +#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \ + ((x) == LIN_BREAK_LEN_11B)) +#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \ + ((x) == UART_TXFIFO_2BYTE) || \ + ((x) == UART_TXFIFO_4BYTE) || \ + ((x) == UART_TXFIFO_8BYTE)) +#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \ + ((x) == UART_RXFIFO_4BYTE) || \ + ((x) == UART_RXFIFO_8BYTE) || \ + ((x) == UART_RXFIFO_14BYTE)) +#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \ + ((x) == UART_ABRMOD_1) || \ + ((x) == UART_ABRMOD_0_TO_1)) +#define IS_UART_STATUS(x) (((x) == UART_STATUS_DR) || \ + ((x) == UART_STATUS_OE) || \ + ((x) == UART_STATUS_PE) || \ + ((x) == UART_STATUS_FE) || \ + ((x) == UART_STATUS_BI) || \ + ((x) == UART_STATUS_TBEM) || \ + ((x) == UART_STATUS_TEM) || \ + ((x) == UART_STATUS_RFE) || \ + ((x) == UART_STATUS_BUSY) || \ + ((x) == UART_STATUS_TFNF) || \ + ((x) == UART_STATUS_TFEM) || \ + ((x) == UART_STATUS_RFNE) || \ + ((x) == UART_STATUS_RFF) || \ + ((x) == UART_STATUS_DCTS) || \ + ((x) == UART_STATUS_CTS)) +#define IS_UART_IT(x) (((x) == UART_IT_RXRD) || \ + ((x) == UART_IT_TXS) || \ + ((x) == UART_IT_RXS) || \ + ((x) == UART_IT_MDS) || \ + ((x) == UART_IT_RTO) || \ + ((x) == UART_IT_BZ) || \ + ((x) == UART_IT_ABE) || \ + ((x) == UART_IT_ABTO) || \ + ((x) == UART_IT_LINBK) || \ + ((x) == UART_IT_TC) || \ + ((x) == UART_IT_EOB) || \ + ((x) == UART_IT_CM)) +#define IS_UART_IF(x) (((x) == UART_IF_RXRD) || \ + ((x) == UART_IF_TXS) || \ + ((x) == UART_IF_RXS) || \ + ((x) == UART_IF_MDS) || \ + ((x) == UART_IF_RTO) || \ + ((x) == UART_IF_BZ) || \ + ((x) == UART_IF_ABE) || \ + ((x) == UART_IF_ABTO) || \ + ((x) == UART_IF_LINBK) || \ + ((x) == UART_IF_TC) || \ + ((x) == UART_IF_EOB) || \ + ((x) == UART_IF_CM)) +#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) +#define IS_UART_DATA(x) ((x) <= 0x1FF) + +#define UART_STATE_TX_MASK (1U << 4) +#define UART_STATE_RX_MASK (1U << 5) +/** + * @} + */ + +/** @addtogroup UART_Public_Functions + * @{ + */ + +/** @addtogroup UART_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_uart_init(uart_handle_t *hperh); +void ald_uart_reset(uart_handle_t *hperh); +void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_dma_pause(uart_handle_t *hperh); +ald_status_t ald_uart_dma_resume(uart_handle_t *hperh); +ald_status_t ald_uart_dma_stop(uart_handle_t *hperh); +#endif +void ald_uart_irq_handler(uart_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group3 + * @{ + */ +/* Peripheral Control functions */ +void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state); +void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state); +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); +void ald_uart_lin_send_break(uart_handle_t *hperh); +void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len); +void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode); +ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout); +it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it); +flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status); +flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag); +flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag); +void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group4 + * @{ + */ +/* Peripheral State and Errors functions */ +uart_state_t ald_uart_get_state(uart_handle_t *hperh); +uint32_t ald_uart_get_error(uart_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_UART_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h new file mode 100644 index 0000000000000000000000000000000000000000..62214b2a089d43a973487d3bb104619895f7ce4d --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h @@ -0,0 +1,580 @@ +/** + ********************************************************************************* + * + * @file ald_usart.h + * @brief Header file of USART module library. + * + * @version V1.0 + * @date 16 Apr 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_USART_H__ +#define __ALD_USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/** @defgroup USART_Public_Types USART Public Types + * @{ + */ + +/** + * @brief usart_word_length + */ +typedef enum +{ + USART_WORD_LENGTH_8B = 0x0, /**< Word length is 8-bits */ + USART_WORD_LENGTH_9B = 0x1, /**< Word length is 9-bits */ +} usart_word_length_t; + +/** + * @brief usart_stop_bits + */ +typedef enum +{ + USART_STOP_BITS_1 = 0x0, /**< Stop bits is 1-bits */ + USART_STOP_BITS_0_5 = 0x1, /**< Stop bits is 0.5-bits */ + USART_STOP_BITS_2 = 0x2, /**< Stop bits is 2-bits */ + USART_STOP_BITS_1_5 = 0x3, /**< Stop bits is 1.5-bits */ +} usart_stop_bits_t; + +/** + * @brief usart_parity + */ +typedef enum +{ + USART_PARITY_NONE = 0x0, /**< Not parity */ + USART_PARITY_EVEN = 0x2, /**< Even parity */ + USART_PARITY_ODD = 0x3, /**< Odd parity */ +} usart_parity_t; + +/** + * @brief usart_mode + */ +typedef enum +{ + USART_MODE_RX = 0x1, /**< TX mode */ + USART_MODE_TX = 0x2, /**< RX mode */ + USART_MODE_TX_RX = 0x3, /**< TX & RX mode */ +} usart_mode_t; + +/** + * @brief usart_hardware_flow_control + */ +typedef enum +{ + USART_HW_FLOW_CTL_NONE = 0x0, /**< Not flow control */ + USART_HW_FLOW_CTL_RTS = 0x1, /**< RTS flow control */ + USART_HW_FLOW_CTL_CTS = 0x2, /**< CTS flow control */ + USART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS flow control */ +} usart_hw_flow_ctl_t; + +/** + * @brief usart_clock + */ +typedef enum +{ + USART_CLOCK_DISABLE = 0x0, /**< Disable clock output */ + USART_CLOCK_ENABLE = 0x1, /**< Enable clock output */ +} usart_clock_t; + +/** + * @brief usart_clock_polarity + */ +typedef enum +{ + USART_CPOL_LOW = 0x0, /**< Clock polarity low */ + USART_CPOL_HIGH = 0x1, /**< Clock polarity high */ +} usart_cpol_t; + +/** + * @brief usart_clock_phase + */ +typedef enum +{ + USART_CPHA_1EDGE = 0x0, /**< Clock phase first edge */ + USART_CPHA_2EDGE = 0x1, /**< Clock phase second edge */ +} usart_cpha_t; + +/** + * @brief usart_last_bit + */ +typedef enum +{ + USART_LAST_BIT_DISABLE = 0x0, /**< Disable last bit clock output */ + USART_LAST_BIT_ENABLE = 0x1, /**< Enable last bit clock output */ +} usart_last_bit_t; + +/** + * @brief usart state structures definition + */ +typedef enum +{ + USART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + USART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + USART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + USART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ + USART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ + USART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ + USART_STATE_TIMEOUT = 0x03, /**< Timeout state */ + USART_STATE_ERROR = 0x04, /**< Error */ +} usart_state_t; + +/** + * @brief usart error codes + */ +typedef enum +{ + USART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ + USART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ + USART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ + USART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ + USART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ + USART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +} usart_error_t; + + +/** + * @brief usart init structure definition + */ +typedef struct +{ + uint32_t baud; /**< This member configures the Usart communication baud rate. */ + usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ + usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ + usart_parity_t parity; /**< Specifies the parity mode. + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + usart_mode_t mode; /**< Specifies wether the Receive or Transmit mode is enabled or disabled. */ + usart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled. */ + type_func_t over_sampling; /**< Specifies whether the Over sampling 8 is enabled or disabled. */ +} usart_init_t; + +/** + * @brief USART handle structure definition + */ +typedef struct usart_handle_s +{ + USART_TypeDef *perh; /**< USART registers base address */ + usart_init_t init; /**< USART communication parameters */ + uint8_t *tx_buf; /**< Pointer to USART Tx transfer buffer */ + uint16_t tx_size; /**< USART Tx transfer size */ + uint16_t tx_count; /**< USART Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to USART Rx transfer buffer */ + uint16_t rx_size; /**< USART Rx Transfer size */ + uint16_t rx_count; /**< USART Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< USART Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< USART Rx DMA handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + usart_state_t state; /**< USART communication state */ + uint32_t err_code; /**< USART error code */ + + void (*tx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct usart_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx & Rx completed callback */ + void (*error_cbk)(struct usart_handle_s *arg); /**< error callback */ +} usart_handle_t; + + +/** + * @brief USART clock init structure definition + */ +typedef struct +{ + usart_clock_t clk; /**< Pecifies whether the USART clock is enable or disable. */ + usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ + usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made. */ + usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. */ +} usart_clock_init_t; + + +/** + * @brief usart_dma_request + */ +typedef enum +{ + USART_DMA_REQ_TX = (1U << 7), /**< TX dma bit */ + USART_DMA_REQ_RX = (1U << 6), /**< RX dma bit */ +} usart_dma_req_t; + +/** + * @brief usart_wakeup_methods + */ +typedef enum +{ + USART_WAKEUP_IDLE = 0x0, /**< Wake up the machine when bus-line is idle */ + USART_WAKEUP_ADDR = 0x1, /**< Wake up the machine when match the address */ +} usart_wakeup_t; + +/** + * @brief usart_IrDA_low_power + */ +typedef enum +{ + USART_IrDA_MODE_NORMAL = 0x0, /**< Normal IrDA mode */ + USART_IrDA_MODE_LOW_POWER = 0x1, /**< Low-power IrDA mode */ +} usart_IrDA_mode_t; + +/** + * @brief USART interrupts definition + */ +typedef enum +{ + USART_IT_PE = ((1U << 8) | (1U << 16)), /**< Parity error */ + USART_IT_TXE = ((1U << 7) | (1U << 16)), /**< Tx empty */ + USART_IT_TC = ((1U << 6) | (1U << 16)), /**< Tx complete */ + USART_IT_RXNE = ((1U << 5) | (1U << 16)), /**< Rx not empty */ + USART_IT_IDLE = ((1U << 4) | (1U << 16)), /**< Idle */ + USART_IT_CTS = ((1U << 10) | (1U << 18)), /**< CTS */ + USART_IT_ERR = ((1U << 0) | (1U << 18)), /**< Error */ + USART_IT_ORE = (1U << 3), /**< Overrun error */ + USART_IT_NE = (1U << 2), /**< Noise error */ + USART_IT_FE = (1U << 0), /**< Frame error */ +} usart_it_t; + +/** + * @brief USART flags + */ +typedef enum +{ + USART_FLAG_CTS = (1U << 9), /**< CTS */ + USART_FLAG_TXE = (1U << 7), /**< Tx empty */ + USART_FLAG_TC = (1U << 6), /**< Tx complete */ + USART_FLAG_RXNE = (1U << 5), /**< Rx not empty */ + USART_FLAG_IDLE = (1U << 4), /**< Idle */ + USART_FLAG_ORE = (1U << 3), /**< Overrun error */ + USART_FLAG_NE = (1U << 2), /**< Noise error */ + USART_FLAG_FE = (1U << 1), /**< Frame error */ + USART_FLAG_PE = (1U << 0), /**< Parity error */ +} usart_flag_t; + +/** + * @} + */ + + +/** @defgroup USART_Public_Macros USART Public Macros + * @{ + */ + +/** @defgroup USART_Public_Macros_1 USART handle reset + * @{ + */ +#define USART_RESET_HANDLE_STATE(handle) ((handle)->state = USART_STATE_RESET) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_2 USART clear PE flag + * @{ + */ +#define USART_CLEAR_PEFLAG(handle) \ + do { \ + __IO uint32_t tmpreg; \ + tmpreg = (handle)->perh->STAT; \ + tmpreg = (handle)->perh->DATA; \ + UNUSED(tmpreg); \ + } while (0) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_3 USART clear FE flag + * @{ + */ +#define USART_CLEAR_FEFLAG(handle) USART_CLEAR_PEFLAG(handle) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_4 USART clear NE flag + * @{ + */ +#define USART_CLEAR_NEFLAG(handle) USART_CLEAR_PEFLAG(handle) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_5 USART clear ORE flag + * @{ + */ +#define USART_CLEAR_OREFLAG(handle) USART_CLEAR_PEFLAG(handle) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_6 USART clear IDLE flag + * @{ + */ +#define USART_CLEAR_IDLEFLAG(handle) USART_CLEAR_PEFLAG(handle) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_7 USART enable CTS flow control + * @{ + */ +#define USART_HWCONTROL_CTS_ENABLE(handle) \ + (SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_8 USART disable CTS flow control + * @{ + */ +#define USART_HWCONTROL_CTS_DISABLE(handle) \ + (CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_9 USART enable RTS flow control + * @{ + */ +#define USART_HWCONTROL_RTS_ENABLE(handle) \ + (SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_10 USART disable RTS flow control + * @{ + */ +#define USART_HWCONTROL_RTS_DISABLE(handle) \ + (CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_11 USART enable + * @{ + */ +#define USART_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_12 USART disable + * @{ + */ +#define USART_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Macros USART Private Macros + * @{ + */ + +#define IS_USART(x) (((x) == USART0) || ((x) == USART1)) +#define IS_USART_WORD_LENGTH(x) (((x) == USART_WORD_LENGTH_8B) || \ + ((x) == USART_WORD_LENGTH_9B)) +#define IS_USART_STOPBITS(x) (((x) == USART_STOP_BITS_1) || \ + ((x) == USART_STOP_BITS_0_5) || \ + ((x) == USART_STOP_BITS_2) || \ + ((x) == USART_STOP_BITS_1_5)) +#define IS_USART_PARITY(x) (((x) == USART_PARITY_NONE) || \ + ((x) == USART_PARITY_EVEN) || \ + ((x) == USART_PARITY_ODD)) +#define IS_USART_MODE(x) (((x) == USART_MODE_RX) || \ + ((x) == USART_MODE_TX) || \ + ((x) == USART_MODE_TX_RX)) +#define IS_USART_HARDWARE_FLOW_CONTROL(x)\ + (((x) == USART_HW_FLOW_CTL_NONE) || \ + ((x) == USART_HW_FLOW_CTL_RTS) || \ + ((x) == USART_HW_FLOW_CTL_CTS) || \ + ((x) == USART_HW_FLOW_CTL_RTS_CTS)) +#define IS_USART_CLOCK(x) (((x) == USART_CLOCK_DISABLE) || \ + ((x) == USART_CLOCK_ENABLE)) +#define IS_USART_CPOL(x) (((x) == USART_CPOL_LOW) || ((x) == USART_CPOL_HIGH)) +#define IS_USART_CPHA(x) (((x) == USART_CPHA_1EDGE) || ((x) == USART_CPHA_2EDGE)) +#define IS_USART_LASTBIT(x) (((x) == USART_LAST_BIT_DISABLE) || \ + ((x) == USART_LAST_BIT_ENABLE)) +#define IS_USART_DMAREQ(x) (((x) == USART_DMA_REQ_TX) || \ + ((x) == USART_DMA_REQ_RX)) +#define IS_USART_WAKEUP(x) (((x) == USART_WAKEUP_IDLE) || \ + ((x) == USART_WAKEUP_ADDR)) +#define IS_USART_IRDA_MODE(x) (((x) == USART_IrDA_MODE_NORMAL) || \ + ((x) == USART_IrDA_MODE_LOW_POWER)) +#define IS_USART_CONFIG_IT(x) (((x) == USART_IT_PE) || ((x) == USART_IT_TXE) || \ + ((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ + ((x) == USART_IT_IDLE) || \ + ((x) == USART_IT_CTS) || ((x) == USART_IT_ERR)) +#define IS_USART_GET_IT(x) (((x) == USART_IT_PE) || ((x) == USART_IT_TXE) || \ + ((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ + ((x) == USART_IT_IDLE) || \ + ((x) == USART_IT_CTS) || ((x) == USART_IT_ORE) || \ + ((x) == USART_IT_NE) || ((x) == USART_IT_FE) || \ + ((x) == USART_IT_ERR)) +#define IS_USART_CLEAR_IT(x) (((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ + ((x) == USART_IT_CTS)) + +#define IS_USART_FLAG(x) (((x) == USART_FLAG_PE) || ((x) == USART_FLAG_TXE) || \ + ((x) == USART_FLAG_TC) || ((x) == USART_FLAG_RXNE) || \ + ((x) == USART_FLAG_IDLE) || \ + ((x) == USART_FLAG_CTS) || ((x) == USART_FLAG_ORE) || \ + ((x) == USART_FLAG_NE) || ((x) == USART_FLAG_FE)) +#define IS_USART_CLEAR_FLAG(x) (((x) == USART_FLAG_CTS) || \ + ((x) == USART_FLAG_TC) || \ + ((x) == USART_FLAG_RXNE)) +#define IS_USART_BAUDRATE(x) (((x) > 0) && ((x) < 0x0044AA21)) +#define IS_USART_ADDRESS(x) ((x) <= 0xF) +#define IS_USART_DATA(x) ((x) <= 0x1FF) +#define DUMMY_DATA 0xFFFF +#define USART_STATE_TX_MASK (1 << 4) +#define USART_STATE_RX_MASK (1 << 5) + +/** + * @} + */ + +/** @addtogroup USART_Public_Functions + * @{ + */ + +/** @addtogroup USART_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_usart_reset(usart_handle_t *hperh); +ald_status_t ald_usart_init(usart_handle_t *hperh); +ald_status_t ald_usart_half_duplex_init(usart_handle_t *hperh); +ald_status_t ald_usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup); +ald_status_t ald_usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init); +/** + * @} + */ + +/** @addtogroup USART_Public_Functions_Group2 + * @{ + */ + +/** @addtogroup USART_Public_Functions_Group2_1 + * @{ + */ +/* Asynchronization IO operation functions */ +ald_status_t ald_usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +#endif +/** + * @} + */ + +/** @addtogroup USART_Public_Functions_Group2_2 + * @{ + */ +/* Synchronization IO operation functions */ +ald_status_t ald_usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); +ald_status_t ald_usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, + uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +#endif +/** + * @} + */ + +/** @addtogroup USART_Public_Functions_Group2_3 + * @{ + */ +/* Utilities functions */ +#ifdef ALD_DMA +ald_status_t ald_usart_dma_pause(usart_handle_t *hperh); +ald_status_t ald_usart_dma_resume(usart_handle_t *hperh); +ald_status_t ald_usart_dma_stop(usart_handle_t *hperh); +#endif +void ald_usart_irq_handler(usart_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USART_Public_Functions_Group3 + * @{ + */ +/* Peripheral control functions */ +ald_status_t ald_usart_multi_processor_enter_mute_mode(usart_handle_t *hperh); +ald_status_t ald_usart_multi_processor_exit_mute_mode(usart_handle_t *hperh); +ald_status_t ald_usart_half_duplex_enable_send(usart_handle_t *hperh); +ald_status_t ald_usart_half_duplex_enable_recv(usart_handle_t *hperh); +void ald_usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state); +void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state); +flag_status_t ald_usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag); +void ald_usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag); +it_status_t ald_usart_get_it_status(usart_handle_t *hperh, usart_it_t it); +/** + * @} + */ + +/** @addtogroup USART_Public_Functions_Group4 + * @{ + */ + +/* Peripheral state and error functions */ +usart_state_t ald_usart_get_state(usart_handle_t *hperh); +uint32_t ald_usart_get_error(usart_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_USART_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h similarity index 66% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h index ee181e3da75d04a882e1a4647c3dd4344df0425a..b2b0e2203ab5cbb3b988f6e8926a3ce60798090f 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -40,10 +40,10 @@ extern "C" { */ typedef enum { - WWDT_WIN_25 = 0x0, /**< No dog window size: 25% */ - WWDT_WIN_50 = 0x1, /**< No dog window size: 50% */ - WWDT_WIN_75 = 0x2, /**< No dog window size: 75% */ - WWDT_WIN_00 = 0x3, /**< No dog window size: 0% */ + WWDT_WIN_25 = 0x0, /**< No dog window size: 25% */ + WWDT_WIN_50 = 0x1, /**< No dog window size: 50% */ + WWDT_WIN_75 = 0x2, /**< No dog window size: 75% */ + WWDT_WIN_00 = 0x3, /**< No dog window size: 0% */ } wwdt_win_t; /** @@ -71,8 +71,8 @@ typedef enum (x == WWDT_WIN_50) || \ (x == WWDT_WIN_75) || \ (x == WWDT_WIN_00)) -#define IS_FUNC_STATE(x) (((x) == DISABLE) || \ - ((x) == ENABLE)) +#define IS_FUNC_STATE(x) (((x) == DISABLE) || \ + ((x) == ENABLE)) /** * @} */ @@ -80,12 +80,12 @@ typedef enum /** @addtogroup WWDT_Public_Functions * @{ */ -void wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt); -void wwdt_start(void); -uint32_t wwdt_get_value(void); -it_status_t wwdt_get_flag_status(void); -void wwdt_clear_flag_status(void); -void wwdt_feed_dog(void); +void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt); +void ald_wwdt_start(void); +uint32_t ald_wwdt_get_value(void); +it_status_t ald_wwdt_get_flag_status(void); +void ald_wwdt_clear_flag_status(void); +void ald_wwdt_feed_dog(void); /** * @} */ @@ -93,12 +93,12 @@ void wwdt_feed_dog(void); /** @addtogroup IWDT_Public_Functions * @{ */ -void iwdt_init(uint32_t load, type_func_t interrupt); -void iwdt_start(void); -uint32_t iwdt_get_value(void); -it_status_t iwdt_get_flag_status(void); -void iwdt_clear_flag_status(void); -void iwdt_feed_dog(void); +void ald_iwdt_init(uint32_t load, type_func_t interrupt); +void ald_iwdt_start(void); +uint32_t ald_iwdt_get_value(void); +it_status_t ald_iwdt_get_flag_status(void); +void ald_iwdt_clear_flag_status(void); +void ald_iwdt_feed_dog(void); /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h similarity index 55% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h index 34303037d93014cbc75655f2914783d4f9547a60..7bf1c1e543558d14b5db019e1cbc96bfef772173 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h @@ -25,11 +25,11 @@ extern "C" { #if defined (__CC_ARM) -#define __INLINE__ __inline -#define __STATIC_INLINE__ static __inline +#define __INLINE__ __inline +#define __STATIC_INLINE__ static __inline #else -#define __INLINE__ inline -#define __STATIC_INLINE__ static inline +#define __INLINE__ inline +#define __STATIC_INLINE__ static inline #endif #define __isr__ @@ -51,7 +51,7 @@ typedef enum DISABLE = 0x0, ENABLE = 0x1, } type_func_t; -#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) +#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) typedef enum { @@ -64,40 +64,40 @@ typedef enum UNLOCK = 0x0, LOCK = 0x1, } lock_state_t; -#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) - - -#define BIT(x) ((1U << (x))) -#define BITS(s, e) ((0xffffffff << (s)) & (0xffffffff >> (31 - (e)))) -#define SET_BIT(reg, bit) ((reg) |= (bit)) -#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) -#define READ_BIT(reg, bit) ((reg) & (bit)) -#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s)) -#define CLEAR_REG(reg) ((reg) = (0x0)) -#define WRITE_REG(reg, val) ((reg) = (val)) -#define READ_REG(reg) ((reg)) -#define MODIFY_REG(reg, clearmask, setmask) \ +#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) + + +#define BIT(x) ((1U << (x))) +#define BITS(s, e) ((0xffffffff << (s)) & (0xffffffff >> (31 - (e)))) +#define SET_BIT(reg, bit) ((reg) |= (bit)) +#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) +#define READ_BIT(reg, bit) ((reg) & (bit)) +#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s)) +#define CLEAR_REG(reg) ((reg) = (0x0)) +#define WRITE_REG(reg, val) ((reg) = (val)) +#define READ_REG(reg) ((reg)) +#define MODIFY_REG(reg, clearmask, setmask) \ WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) -#define UNUSED(x) ((void)(x)) +#define UNUSED(x) ((void)(x)) #ifdef USE_ASSERT -#define assert_param(x) \ -do { \ - if (!(x)) { \ - __disable_irq(); \ - while (1) \ - ; \ - } \ -} while (0) +#define assert_param(x) \ + do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ + } while (0) #else #define assert_param(x) #endif -#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ -#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ -#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ -#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ __STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) { @@ -114,10 +114,10 @@ __STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) #if defined ( __GNUC__ ) #ifndef __weak #define __weak __attribute__((weak)) -#endif /* __weak */ +#endif /* __weak */ #ifndef __packed #define __packed __attribute__((__packed__)) -#endif /* __packed */ +#endif /* __packed */ #endif /* __GNUC__ */ #ifdef __cplusplus diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h similarity index 56% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h index b80d15579004feb1aa1bf356695cb45d19945570..b9041cb62a6ef1903032be1ba0edd4325fd1efa4 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h @@ -59,10 +59,10 @@ typedef enum */ typedef enum { - SYSTICK_INTERVAL_1MS = 1000, /**< Interval is 1ms */ - SYSTICK_INTERVAL_10MS = 100, /**< Interval is 10ms */ - SYSTICK_INTERVAL_100MS = 10, /**< Interval is 100ms */ - SYSTICK_INTERVAL_1000MS = 1, /**< Interval is 1s */ + SYSTICK_INTERVAL_1MS = 1000, /**< Interval is 1ms */ + SYSTICK_INTERVAL_10MS = 100, /**< Interval is 10ms */ + SYSTICK_INTERVAL_100MS = 10, /**< Interval is 100ms */ + SYSTICK_INTERVAL_1000MS = 1, /**< Interval is 1s */ } systick_interval_t; /** * @} @@ -71,24 +71,24 @@ typedef enum /** @defgroup ALD_Public_Macros Public Macros * @{ */ -#define ALD_MAX_DELAY 0xFFFFFFFF - -#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) -#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) -#define RESET_HANDLE_STATE(x) ((x)->state = 0) -#define __LOCK(x) \ - do { \ - if ((x)->lock == LOCK) { \ - return BUSY; \ - } \ - else { \ - (x)->lock = LOCK; \ - } \ +#define ALD_MAX_DELAY 0xFFFFFFFF + +#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) +#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) +#define RESET_HANDLE_STATE(x) ((x)->state = 0) +#define __LOCK(x) \ + do { \ + if ((x)->lock == LOCK) { \ + return BUSY; \ + } \ + else { \ + (x)->lock = LOCK; \ + } \ } while (0) -#define __UNLOCK(x) \ - do { \ - (x)->lock = UNLOCK; \ +#define __UNLOCK(x) \ + do { \ + (x)->lock = UNLOCK; \ } while (0) /** @@ -98,8 +98,8 @@ typedef enum /** @defgroup ALD_Private_Macros Private Macros * @{ */ -#define IS_PRIO(x) ((x) < 4) -#define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ +#define IS_PRIO(x) ((x) < 4) +#define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ ((x) == SYSTICK_INTERVAL_10MS) || \ ((x) == SYSTICK_INTERVAL_100MS) || \ ((x) == SYSTICK_INTERVAL_1000MS)) @@ -116,9 +116,9 @@ typedef enum */ /* Initialization functions */ -void mcu_ald_init(void); -void __init_tick(uint32_t prio); -void systick_interval_select(systick_interval_t value); +void ald_cmu_init(void); +void ald_tick_init(uint32_t prio); +void ald_systick_interval_select(systick_interval_t value); /** * @} @@ -128,17 +128,18 @@ void systick_interval_select(systick_interval_t value); * @{ */ /* Peripheral Control functions */ -void __inc_tick(void); -void __delay_ms(__IO uint32_t delay); -uint32_t __get_tick(void); -void __suspend_tick(void); -void __resume_tick(void); -void systick_irq_cbk(void); -uint32_t get_ald_version(void); -ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout); -void mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status); -uint32_t mcu_get_tick(void); -uint32_t mcu_get_cpu_id(void); +void ald_inc_tick_weak(void); +void ald_delay_ms(__IO uint32_t delay); +uint32_t ald_get_tick(void); +void ald_suspend_tick(void); +void ald_resume_tick(void); +void ald_systick_irq_cbk(void); +void ald_inc_tick(void); +uint32_t ald_get_ald_version(void); +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout); +void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status); +uint32_t ald_mcu_get_tick(void); +uint32_t ald_mcu_get_cpu_id(void); /** * @} diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c similarity index 74% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c index 0ea7a7c0ebbf5cba3b9472230cc6276ecfbef85e..3057d7d2463cd952b6bc0ea6331f4a7d3341b2ef 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c @@ -42,7 +42,7 @@ * the configuration information for the specified ACMP module. * @retval Status, see @ref ald_status_t. */ -ald_status_t acmp_init(acmp_handle_t *hperh) +ald_status_t ald_acmp_init(acmp_handle_t *hperh) { uint32_t tmp = 0; @@ -67,7 +67,7 @@ ald_status_t acmp_init(acmp_handle_t *hperh) tmp = hperh->perh->CON; tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) | - (hperh->init.inactval << ACMP_CON_INACTV_POS)); + (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS)); hperh->perh->CON = tmp; @@ -85,33 +85,42 @@ ald_status_t acmp_init(acmp_handle_t *hperh) switch (hperh->init.edge) { - case ACMP_EDGE_NONE: - CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - case ACMP_EDGE_FALL: - SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - case ACMP_EDGE_RISE: - CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - case ACMP_EDGE_ALL: - SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - default: - break; + case ACMP_EDGE_NONE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_FALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_RISE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_ALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + default: + break; } SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK); - while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0); + tmp = 0; + + while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) + { + if (tmp++ >= 600000) + { + __UNLOCK(hperh); + return ERROR; + } + } __UNLOCK(hperh); return OK; @@ -136,7 +145,7 @@ ald_status_t acmp_init(acmp_handle_t *hperh) * - DISABLE * @retval Status, see @ref ald_status_t. */ -ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state) +ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state) { assert_param(IS_ACMP_TYPE(hperh->perh)); assert_param(IS_ACMP_IT_TYPE(it)); @@ -154,6 +163,27 @@ ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func return OK; } +/** + * @brief Checks whether the specified ACMP interrupt has set or not. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param it: Specifies the ACMP interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref acmp_it_t. + * @retval it_status_t + * - SET + * - RESET + */ +it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); + + if (hperh->perh->IEV & it) + return SET; + else + return RESET; +} + /** * @brief Checks whether the specified ACMP interrupt has occurred or not. * @param hperh: Pointer to a acmp_handle_t structure that contains @@ -164,7 +194,7 @@ ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func * - SET * - RESET */ -it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) { assert_param(IS_ACMP_TYPE(hperh->perh)); assert_param(IS_ACMP_FLAG_TYPE(flag)); @@ -185,7 +215,7 @@ it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) * This parameter can be one of the @ref acmp_it_t. * @retval Status, see @ref ald_status_t. */ -ald_status_t acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) { assert_param(IS_ACMP_TYPE(hperh->perh)); assert_param(IS_ACMP_FLAG_TYPE(flag)); @@ -225,7 +255,7 @@ ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it) * - SET * - RESET */ -flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) +flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) { assert_param(IS_ACMP_TYPE(hperh->perh)); assert_param(IS_ACMP_STATUS_TYPE(status)); @@ -253,20 +283,22 @@ flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) * the configuration information for the specified ACMP module. * @retval None */ -void acmp_irq_handle(acmp_handle_t *hperh) +void ald_acmp_irq_handler(acmp_handle_t *hperh) { - if (acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) + if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_WARMUP) == SET)) { if (hperh->acmp_warmup_cplt_cbk) hperh->acmp_warmup_cplt_cbk(hperh); - acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); + + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); } - if (acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) + if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_EDGE) == SET)) { if (hperh->acmp_edge_cplt_cbk) hperh->acmp_edge_cplt_cbk(hperh); - acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); + + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); } return; @@ -280,7 +312,7 @@ void acmp_irq_handle(acmp_handle_t *hperh) * the configutation information for acmp output. * @retval Status, see @ref ald_status_t. */ -ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) +ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) { if (hperh == NULL) return ERROR; @@ -290,11 +322,9 @@ ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) assert_param(IS_ACMP_TYPE(hperh->perh)); assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv)); - assert_param(IS_ACMP_LOCATION_TYPE(config->location)); assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func)); __LOCK(hperh); - hperh->perh->PORT = config->location; hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS); hperh->perh->PORT = config->out_func; __UNLOCK(hperh); @@ -308,7 +338,7 @@ ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) * the configuration information for the specified ACMP module. * @retval output value. */ -uint8_t acmp_out_result(acmp_handle_t *hperh) +uint8_t ald_acmp_out_result(acmp_handle_t *hperh) { assert_param(IS_ACMP_TYPE(hperh->perh)); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c similarity index 69% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c index 95d707dfdaf61b51adb056e86a4707f45e1e4386..2019e5a948a337a2a9e99769f0f66514bff45faa 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -71,7 +71,7 @@ * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_init(adc_handle_t *hperh) +ald_status_t ald_adc_init(adc_handle_t *hperh) { ald_status_t tmp_status = OK; @@ -85,20 +85,49 @@ ald_status_t adc_init(adc_handle_t *hperh) assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.neg_ref)); assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.pos_ref)); assert_param(IS_ADC_CONV_RES_TYPE(hperh->init.conv_res)); - assert_param(IS_ADC_NBR_OF_NM_TYPE(hperh->init.conv_nbr)); + assert_param(IS_ADC_NCH_LEN_TYPE(hperh->init.nch_len)); + assert_param(IS_ADC_DISC_MODE_TYPE(hperh->init.disc_mode)); assert_param(IS_ADC_DISC_NBR_TYPE(hperh->init.disc_nbr)); assert_param(IS_FUNC_STATE(hperh->init.cont_mode)); - assert_param(IS_FUNC_STATE(hperh->init.disc_mode)); - assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_mode)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); + assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); if (hperh->state == ADC_STATE_RESET) { hperh->error_code = ADC_ERROR_NONE; - hperh->lock = UNLOCK; + hperh->lock = UNLOCK; + } + + if ((hperh->init.pos_ref == ADC_POS_REF_VDD) && (hperh->init.neg_ref == ADC_NEG_REF_VSS)) + { + ADC_ENABLE(hperh); + + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, 1 << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, 1 << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, 6 << ADC_CCR_CKDIV_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_RES_12 << ADC_CON0_RSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); + + hperh->perh->SMPT2 = 0x30; + + /* Start adc normal convert */ + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + /* Wait convert finish */ + while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); + + hperh->vdd_value = (hperh->perh->NCHDR & 0xfff); + + /* Get calibration VDD value */ + hperh->vdd_value = 2000 * 4096 / hperh->vdd_value; } ADC_DISABLE(hperh); + ald_adc_reset(hperh); hperh->state = ADC_STATE_BUSY_INTERNAL; MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.data_align << ADC_CON1_ALIGN_POS); MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont_mode << ADC_CON1_CM_POS); @@ -106,32 +135,28 @@ ald_status_t adc_init(adc_handle_t *hperh) MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.conv_res << ADC_CON0_RSEL_POSS); /* Enable discontinuous mode only if continuous mode is enabled */ - if (hperh->init.disc_mode == ENABLE) + if (hperh->init.disc_mode == ADC_NCH_DISC_EN) { - if (hperh->init.cont_mode == ENABLE) - { - SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS); - } - else - { - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - tmp_status = ERROR; - } + hperh->init.scan_mode = ENABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); + } + else if (hperh->init.disc_mode == ADC_ICH_DISC_EN) + { + hperh->init.scan_mode = ENABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); } else { CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); } - if (hperh->init.scan_mode == ADC_SCAN_ENABLE) - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS); - - if (hperh->init.cont_mode == ENABLE) - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS); + if ((hperh->init.scan_mode == ENABLE) || (hperh->init.disc_mode == ADC_NCH_DISC_EN)) + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_len << ADC_CHSL_NSL_POSS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan_mode << ADC_CON0_SCANEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); @@ -144,20 +169,17 @@ ald_status_t adc_init(adc_handle_t *hperh) MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.clk_div << ADC_CCR_CKDIV_POSS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_mode << ADC_CON1_NCHESEL_POS); - - if (hperh->nm_trig_mode != ADC_TRIG_SOFT) - pis_create(&hperh->reg_pis_handle); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); if (tmp_status == OK) { hperh->error_code = ADC_ERROR_NONE; - hperh->state |= ADC_STATE_READY; - hperh->state &= ~(ADC_STATE_ERROR | ADC_STATE_NM_BUSY + hperh->state |= ADC_STATE_READY; + hperh->state &= ~(ADC_STATE_ERROR | ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY | ADC_STATE_BUSY_INTERNAL); } - adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); + ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); return tmp_status; } @@ -168,7 +190,7 @@ ald_status_t adc_init(adc_handle_t *hperh) * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_reset(adc_handle_t *hperh) +ald_status_t ald_adc_reset(adc_handle_t *hperh) { if (hperh == NULL) return ERROR; @@ -177,12 +199,12 @@ ald_status_t adc_reset(adc_handle_t *hperh) ADC_DISABLE(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_AWD); - adc_clear_flag_status(hperh, ADC_FLAG_NH); - adc_clear_flag_status(hperh, ADC_FLAG_IH); - adc_clear_flag_status(hperh, ADC_FLAG_OVR); - adc_clear_flag_status(hperh, ADC_FLAG_NHS); - adc_clear_flag_status(hperh, ADC_FLAG_IHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); WRITE_REG(hperh->perh->CON0, 0x0); WRITE_REG(hperh->perh->CON1, 0x0); @@ -202,12 +224,6 @@ ald_status_t adc_reset(adc_handle_t *hperh) WRITE_REG(hperh->perh->SMPT2, 0x0); WRITE_REG(hperh->perh->CHSL, 0x0); - if (hperh->nm_trig_mode != ADC_TRIG_SOFT) - pis_destroy(&hperh->reg_pis_handle); - - if (hperh->ist_trig_mode != ADC_TRIG_SOFT) - pis_destroy(&hperh->inj_pis_handle); - hperh->state = ADC_STATE_RESET; hperh->error_code = ADC_ERROR_NONE; return OK; @@ -227,12 +243,11 @@ ald_status_t adc_reset(adc_handle_t *hperh) * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_start(adc_handle_t *hperh) +ald_status_t ald_adc_normal_start(adc_handle_t *hperh) { if (hperh == NULL) return ERROR; - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); assert_param(IS_ADC_TYPE(hperh->perh)); __LOCK(hperh); @@ -240,10 +255,9 @@ ald_status_t adc_normal_start(adc_handle_t *hperh) hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); hperh->state |= ADC_STATE_NM_BUSY; __UNLOCK(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_NH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - if (hperh->nm_trig_mode == ADC_TRIG_SOFT) - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); return OK; } @@ -253,14 +267,13 @@ ald_status_t adc_normal_start(adc_handle_t *hperh) * case of auto_injection mode), disable ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on insert group. If insert group is under use, it - * should be preliminarily stopped using adc_insert_stop function. + * should be preliminarily stopped using ald_adc_insert_stop function. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_stop(adc_handle_t *hperh) +ald_status_t ald_adc_normal_stop(adc_handle_t *hperh) { - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); assert_param(IS_ADC_TYPE(hperh->perh)); __LOCK(hperh); @@ -285,18 +298,19 @@ ald_status_t adc_normal_stop(adc_handle_t *hperh) * @param timeout: Timeout value in millisecond. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) +ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) { uint32_t tickstart = 0; assert_param(IS_ADC_TYPE(hperh->perh)); - tickstart = __get_tick(); + tickstart = ald_get_tick(); + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) { if (timeout != ALD_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state |= ADC_STATE_TIMEOUT; __UNLOCK(hperh); @@ -305,20 +319,19 @@ ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeou } } - adc_clear_flag_status(hperh, ADC_FLAG_NHS); - adc_clear_flag_status(hperh, ADC_FLAG_NH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); hperh->state |= ADC_STATE_NM_EOC; - if ((hperh->nm_trig_mode == ADC_TRIG_SOFT) - && (hperh->init.cont_mode == DISABLE) - && (hperh->init.scan_mode == ADC_SCAN_DISABLE)) + if ((hperh->init.cont_mode == DISABLE) && (hperh->init.scan_mode == DISABLE)) { hperh->state &= ~ADC_STATE_NM_BUSY; if ((hperh->state & ADC_STATE_IST_BUSY) == 0) hperh->state |= ADC_STATE_READY; } + return OK; } @@ -332,20 +345,20 @@ ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeou * @param timeout: Timeout value in millisecond. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout) +ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout) { uint32_t tickstart = 0; assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_EVENT_TYPE(event_type)); - tickstart = __get_tick(); + tickstart = ald_get_tick(); - while (adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) + while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) { if (timeout != ALD_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state |= ADC_STATE_TIMEOUT; __UNLOCK(hperh); @@ -367,14 +380,14 @@ ald_status_t adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_start_by_it(adc_handle_t *hperh) +ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); __LOCK(hperh); ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_NM_BUSY; + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); + hperh->state |= ADC_STATE_NM_BUSY; hperh->error_code = ADC_ERROR_NONE; if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) @@ -384,11 +397,10 @@ ald_status_t adc_normal_start_by_it(adc_handle_t *hperh) } __UNLOCK(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_NH); - adc_interrupt_config(hperh, ADC_IT_NH, ENABLE); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE); - if (hperh->nm_trig_mode == ADC_TRIG_SOFT) - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); return OK; } @@ -401,13 +413,13 @@ ald_status_t adc_normal_start_by_it(adc_handle_t *hperh) * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_stop_by_it(adc_handle_t *hperh) +ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); __LOCK(hperh); ADC_DISABLE(hperh); - adc_interrupt_config(hperh, ADC_IT_NH, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); hperh->state |= ADC_STATE_READY; hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); @@ -426,7 +438,7 @@ ald_status_t adc_normal_stop_by_it(adc_handle_t *hperh) * @param channel: The DMA channel * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) { if ((hperh == NULL) || (buf == NULL) || (size == 0) || (channel > 5)) return ERROR; @@ -454,6 +466,7 @@ ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, hperh->state &= ~(ADC_STATE_ERROR); hperh->error_code = ADC_ERROR_NONE; } + __UNLOCK(hperh); if (hperh->hdma.perh == NULL) @@ -464,7 +477,7 @@ ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, hperh->hdma.err_cbk = adc_dma_error; hperh->hdma.err_arg = hperh; - dma_config_struct(&hperh->hdma.config); + ald_dma_config_struct(&hperh->hdma.config); hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; hperh->hdma.config.dst = (void *)buf; hperh->hdma.config.size = size; @@ -474,17 +487,9 @@ ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, hperh->hdma.config.msel = DMA_MSEL_ADC0; hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC; hperh->hdma.config.channel = channel; - dma_config_basic(&hperh->hdma); - - hperh->hpis.init.producer_src = PIS_ADC1_REGULAT; - hperh->hpis.init.producer_clk = PIS_CLK_PCLK2; - hperh->hpis.init.producer_edge = PIS_EDGE_NONE; - hperh->hpis.init.consumer_trig = PIS_CH7_DAC_CH0; - hperh->hpis.init.consumer_clk = PIS_CLK_PCLK1; - pis_create(&hperh->hpis); + ald_dma_config_basic(&hperh->hdma); - if (hperh->nm_trig_mode == ADC_TRIG_SOFT) - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); return OK; } @@ -503,7 +508,7 @@ ald_status_t adc_stop_dma(adc_handle_t *hperh) __LOCK(hperh); ADC_DISABLE(hperh); - pis_destroy(&hperh->hpis); + ald_pis_destroy(&hperh->hpis); hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); hperh->state |= ADC_STATE_READY; @@ -521,9 +526,10 @@ static void adc_dma_timer_trigger_cplt(void *arg) adc_timer_config_t *hperh = (adc_timer_config_t *)arg; ADC_DISABLE(&hperh->lh_adc); - timer_base_stop(&hperh->lh_timer); + ald_timer_base_stop(&hperh->lh_timer); __UNLOCK(hperh); + if (hperh->lh_adc.adc_reg_cplt_cbk != NULL) hperh->lh_adc.adc_reg_cplt_cbk(&hperh->lh_adc); @@ -536,22 +542,32 @@ static void adc_dma_timer_trigger_cplt(void *arg) * contains the configuration information for the specified function. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) +ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) { __LOCK(config); config->lh_pis.perh = PIS; config->lh_pis.init.producer_clk = PIS_CLK_PCLK1; config->lh_pis.init.producer_edge = PIS_EDGE_NONE; - config->lh_pis.init.consumer_clk = PIS_CLK_PCLK1; + config->lh_pis.init.consumer_clk = PIS_CLK_PCLK2; + +#if defined (ES32F065x) - if (config->p_timer == TIMER0) + if (config->p_timer == AD16C4T0) config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; - else if (config->p_timer == TIMER1) + +#elif defined(ES32F033x) || defined (ES32F093x) + + if (config->p_timer == GP16C4T0) + config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; + +#endif + + else if (config->p_timer == BS16T0) config->lh_pis.init.producer_src = PIS_TIMER1_UPDATA; - else if (config->p_timer == TIMER2) + else if (config->p_timer == GP16C2T0) config->lh_pis.init.producer_src = PIS_TIMER2_UPDATA; - else if (config->p_timer == TIMER3) + else if (config->p_timer == GP16C2T1) config->lh_pis.init.producer_src = PIS_TIMER3_UPDATA; else return ERROR; @@ -563,27 +579,27 @@ ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) else return ERROR; - pis_create(&config->lh_pis); + ald_pis_create(&config->lh_pis); /* Initialize TIMER0 */ config->lh_timer.perh = config->p_timer; config->lh_timer.init.prescaler = 0; config->lh_timer.init.mode = TIMER_CNT_MODE_UP; - config->lh_timer.init.period = ((cmu_get_pclk1_clock() / 1000000) * config->time); + config->lh_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); config->lh_timer.init.clk_div = TIMER_CLOCK_DIV1; config->lh_timer.init.re_cnt = 0; - timer_base_init(&config->lh_timer); + ald_timer_base_init(&config->lh_timer); config->lh_adc.perh = config->p_adc; config->lh_adc.init.data_align = ADC_DATAALIGN_RIGHT; - config->lh_adc.init.scan_mode = ADC_SCAN_DISABLE; + config->lh_adc.init.scan_mode = DISABLE; config->lh_adc.init.cont_mode = DISABLE; - config->lh_adc.init.conv_nbr = ADC_NM_NBR_1; - config->lh_adc.init.disc_mode = DISABLE; + config->lh_adc.init.nch_len = ADC_NCH_LEN_1; + config->lh_adc.init.disc_mode = ADC_ALL_DISABLE; config->lh_adc.init.disc_nbr = ADC_DISC_NBR_1; config->lh_adc.init.conv_res = ADC_CONV_RES_12; config->lh_adc.init.clk_div = ADC_CKDIV_16; - config->lh_adc.init.nche_mode = ADC_NCHESEL_MODE_ONE; + config->lh_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; config->lh_adc.init.neg_ref = config->n_ref; config->lh_adc.init.pos_ref = config->p_ref; config->lh_adc.adc_reg_cplt_cbk = config->adc_cplt_cbk; @@ -591,19 +607,19 @@ ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) config->lh_adc.adc_out_of_win_cbk = NULL; config->lh_adc.adc_error_cbk = NULL; config->lh_adc.adc_ovr_cbk = NULL; - adc_init(&config->lh_adc); + ald_adc_init(&config->lh_adc); config->lnm_config.channel = config->adc_ch; - config->lnm_config.rank = ADC_NC_RANK_1; - config->lnm_config.sampling_time = ADC_SAMPLETIME_1; - adc_normal_channel_config(&config->lh_adc, &config->lnm_config); + config->lnm_config.rank = ADC_NCH_RANK_1; + config->lnm_config.samp_time = ADC_SAMPLETIME_1; + ald_adc_normal_channel_config(&config->lh_adc, &config->lnm_config); config->lh_dma.cplt_cbk = adc_dma_timer_trigger_cplt; config->lh_dma.cplt_arg = config; config->lh_dma.err_cbk = adc_dma_error; config->lh_dma.err_arg = &config->lh_adc; - dma_config_struct(&config->lh_dma.config); + ald_dma_config_struct(&config->lh_dma.config); config->lh_dma.perh = DMA0; config->lh_dma.config.src = (void *)&config->lh_adc.perh->NCHDR; config->lh_dma.config.dst = (void *)config->buf; @@ -614,10 +630,10 @@ ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) config->lh_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; config->lh_dma.config.msigsel = DMA_MSIGSEL_ADC; config->lh_dma.config.channel = config->dma_ch; - dma_config_basic(&config->lh_dma); + ald_dma_config_basic(&config->lh_dma); ADC_ENABLE(&config->lh_adc); - timer_base_start(&config->lh_timer); + ald_timer_base_start(&config->lh_timer); return OK; } @@ -629,7 +645,7 @@ ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) * the configuration information for the specified ADC module. * @retval ADC group normal conversion data */ -uint32_t adc_normal_get_value(adc_handle_t *hperh) +uint32_t ald_adc_normal_get_value(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); @@ -637,6 +653,54 @@ uint32_t adc_normal_get_value(adc_handle_t *hperh) return hperh->perh->NCHDR; } +/** + * @brief The pos reference is VDD and neg reference is VSS, + * get adc normal group result and convert voltage value. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC group normal voltage value,the unit is mV. + */ +uint32_t ald_adc_get_vdd_value(adc_handle_t *hperh) +{ + uint32_t value = 0; + + if ((hperh->init.pos_ref != ADC_POS_REF_VDD) || (hperh->init.neg_ref != ADC_NEG_REF_VSS)) + return 0; + + __LOCK(hperh); + ADC_ENABLE(hperh); + + /* Set adc and measure 2V */ + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, DISABLE << ADC_CCR_VRBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFOEN_MSK, DISABLE << ADC_CCR_VREFOEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, ENABLE << ADC_CCR_PWRMODSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, 6 << ADC_CCR_CKDIV_POSS); + MODIFY_REG(hperh->perh->CON0, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_RES_12 << ADC_CON0_RSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); + + hperh->perh->SMPT2 = 0x30; + /* Start adc normal convert */ + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + /* Wait convert finish */ + while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); + + value = (hperh->perh->NCHDR & 0xfff); + /* Get calibration VDD value */ + value = 2000 * 4096 / value; + hperh->vdd_value = value; + + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); + __UNLOCK(hperh); + + return value; +} + /** * @brief Enables ADC, starts conversion of insert group. * Interruptions enabled in this function: None. @@ -644,10 +708,9 @@ uint32_t adc_normal_get_value(adc_handle_t *hperh) * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_insert_start(adc_handle_t *hperh) +ald_status_t ald_adc_insert_start(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); __LOCK(hperh); ADC_ENABLE(hperh); @@ -658,12 +721,11 @@ ald_status_t adc_insert_start(adc_handle_t *hperh) hperh->error_code = ADC_ERROR_NONE; __UNLOCK(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_IH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) { - if (hperh->ist_trig_mode == ADC_TRIG_SOFT) - SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); } return OK; @@ -673,18 +735,17 @@ ald_status_t adc_insert_start(adc_handle_t *hperh) * @brief Stop conversion of insert channels. Disable ADC peripheral if * no normal conversion is on going. * @note If ADC must be disabled and if conversion is on going on - * normal group, function adc_normal_stop must be used to stop both + * normal group, function ald_adc_normal_stop must be used to stop both * insert and normal groups, and disable the ADC. * @note If insert group mode auto-injection is enabled, - * function adc_normal_stop must be used. + * function ald_adc_normal_stop must be used. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_insert_stop(adc_handle_t *hperh) +ald_status_t ald_adc_insert_stop(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); __LOCK(hperh); @@ -713,20 +774,19 @@ ald_status_t adc_insert_stop(adc_handle_t *hperh) * @param timeout: Timeout value in millisecond. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) +ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) { uint32_t tickstart; assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); - tickstart = __get_tick(); + tickstart = ald_get_tick(); while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) { if (timeout != ALD_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state |= ADC_STATE_TIMEOUT; __UNLOCK(hperh); @@ -735,18 +795,16 @@ ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeou } } - adc_clear_flag_status(hperh, ADC_FLAG_IHS); - adc_clear_flag_status(hperh, ADC_FLAG_IH); - adc_clear_flag_status(hperh, ADC_FLAG_NH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); hperh->state |= ADC_STATE_IST_EOC; - if (hperh->ist_trig_mode == ADC_TRIG_SOFT) - { - hperh->state &= ~(ADC_STATE_IST_BUSY); - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - } + hperh->state &= ~(ADC_STATE_IST_BUSY); + + if ((hperh->state & ADC_STATE_NM_BUSY) == 0) + hperh->state |= ADC_STATE_READY; hperh->state &= ~(ADC_STATE_TIMEOUT); __UNLOCK(hperh); @@ -761,10 +819,9 @@ ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeou * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t.. */ -ald_status_t adc_insert_start_by_it(adc_handle_t *hperh) +ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); __LOCK(hperh); ADC_ENABLE(hperh); @@ -775,14 +832,12 @@ ald_status_t adc_insert_start_by_it(adc_handle_t *hperh) hperh->error_code = ADC_ERROR_NONE; __UNLOCK(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_IH); - adc_interrupt_config(hperh, ADC_IT_IH, ENABLE); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE); if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - { - if (hperh->ist_trig_mode == ADC_TRIG_SOFT) - SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - } + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + return OK; } @@ -791,18 +846,17 @@ ald_status_t adc_insert_start_by_it(adc_handle_t *hperh) * end-of-conversion. Disable ADC peripheral if no normal conversion * is on going. * @note If ADC must be disabled and if conversion is on going on - * normal group, function adc_normal_stop must be used to stop both + * normal group, function ald_adc_normal_stop must be used to stop both * insert and normal groups, and disable the ADC. * @note If insert group mode auto-injection is enabled, - * function adc_normal_stop must be used. + * function ald_adc_normal_stop must be used. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. * @retval None */ -ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh) +ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); __LOCK(hperh); @@ -810,13 +864,13 @@ ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh) && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) { ADC_DISABLE(hperh); - adc_interrupt_config(hperh, ADC_IT_IH, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); hperh->state |= ADC_STATE_READY; } else { - adc_interrupt_config(hperh, ADC_IT_IH, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); hperh->state |= ADC_STATE_ERROR; __UNLOCK(hperh); return ERROR; @@ -838,29 +892,33 @@ ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh) * @arg ADC_INJ_RANK_4: insert Channel4 selected * @retval ADC group insert conversion data */ -uint32_t adc_insert_get_value(adc_handle_t *hperh, adc_ih_rank_t ih_rank) +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank) { uint32_t tmp; assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_IH_RANK_TYPE(ih_rank)); + assert_param(IS_ADC_ICH_RANK_TYPE(ih_rank)); switch (ih_rank) { - case ADC_IH_RANK_1: - tmp = hperh->perh->ICHDR[0]; - break; - case ADC_IH_RANK_2: - tmp = hperh->perh->ICHDR[1]; - break; - case ADC_IH_RANK_3: - tmp = hperh->perh->ICHDR[2]; - break; - case ADC_IH_RANK_4: - tmp = hperh->perh->ICHDR[3]; - break; - default: - break; + case ADC_ICH_RANK_1: + tmp = hperh->perh->ICHDR[0]; + break; + + case ADC_ICH_RANK_2: + tmp = hperh->perh->ICHDR[1]; + break; + + case ADC_ICH_RANK_3: + tmp = hperh->perh->ICHDR[2]; + break; + + case ADC_ICH_RANK_4: + tmp = hperh->perh->ICHDR[3]; + break; + + default: + break; } return tmp; @@ -872,21 +930,18 @@ uint32_t adc_insert_get_value(adc_handle_t *hperh, adc_ih_rank_t ih_rank) * the configuration information for the specified ADC module. * @retval None */ -void adc_irq_handler(adc_handle_t *hperh) +void ald_adc_irq_handler(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); - if (adc_get_it_status(hperh, ADC_IT_NH) && adc_get_flag_status(hperh, ADC_FLAG_NH)) + if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) { if ((hperh->state & ADC_STATE_ERROR) == 0) hperh->state |= ADC_STATE_NM_EOC; - if ((hperh->nm_trig_mode == ADC_TRIG_SOFT) - && (hperh->init.cont_mode == DISABLE)) + if (hperh->init.cont_mode == DISABLE) { - adc_interrupt_config(hperh, ADC_IT_NH, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); hperh->state &= ~(ADC_STATE_NM_BUSY); if ((hperh->state & ADC_STATE_IST_BUSY) == 0) @@ -896,46 +951,45 @@ void adc_irq_handler(adc_handle_t *hperh) if (hperh->adc_reg_cplt_cbk != NULL) hperh->adc_reg_cplt_cbk(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_NHS); - adc_clear_flag_status(hperh, ADC_FLAG_NH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); } - if (adc_get_it_status(hperh, ADC_IT_IH) && adc_get_flag_status(hperh, ADC_FLAG_IH)) + if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) { if ((hperh->state & ADC_STATE_ERROR) == 0) hperh->state |= ADC_STATE_IST_EOC; - if ((hperh->ist_trig_mode == ADC_TRIG_SOFT) - || ((!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - && (hperh->nm_trig_mode == ADC_TRIG_SOFT) - && (hperh->init.cont_mode == DISABLE))) + if ((!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + && (hperh->init.cont_mode == DISABLE)) { - adc_interrupt_config(hperh, ADC_IT_IH, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); hperh->state &= ~(ADC_STATE_IST_BUSY); if ((hperh->state & ADC_STATE_NM_BUSY) == 0) hperh->state |= ADC_STATE_READY; } + if (hperh->adc_inj_cplt_cbk != NULL) hperh->adc_inj_cplt_cbk(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_IHS); - adc_clear_flag_status(hperh, ADC_FLAG_IH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); } - if (adc_get_it_status(hperh, ADC_IT_AWD) && adc_get_flag_status(hperh, ADC_FLAG_AWD)) + if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) { hperh->state |= ADC_STATE_AWD; if (hperh->adc_out_of_win_cbk != NULL) hperh->adc_out_of_win_cbk(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_AWD); + ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); } - if (adc_get_it_status(hperh, ADC_IT_OVR) && adc_get_flag_status(hperh, ADC_FLAG_OVR)) + if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) { - adc_clear_flag_status(hperh, ADC_FLAG_OVR); + ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); hperh->error_code |= ADC_ERROR_OVR; hperh->state |= ADC_STATE_ERROR; @@ -961,26 +1015,26 @@ void adc_irq_handler(adc_handle_t *hperh) * @param config: Structure of ADC channel for normal group. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t *config) +ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config) { assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - assert_param(IS_ADC_NC_RANK_TYPE(config->rank)); - assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->sampling_time)); + assert_param(IS_ADC_NCH_RANK_TYPE(config->rank)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); __LOCK(hperh); - if (config->rank <= ADC_NC_RANK_4) + if (config->rank <= ADC_NCH_RANK_4) { hperh->perh->NCHS1 &= ~(0x1f << ((config->rank - 1) << 3)); hperh->perh->NCHS1 |= (config->channel << ((config->rank - 1) << 3)); } - else if (config->rank <= ADC_NC_RANK_8) + else if (config->rank <= ADC_NCH_RANK_8) { hperh->perh->NCHS2 &= ~(0x1f << ((config->rank - 5) << 3)); hperh->perh->NCHS2 |= (config->channel << ((config->rank - 5) << 3)); } - else if (config->rank <= ADC_NC_RANK_12) + else if (config->rank <= ADC_NCH_RANK_12) { hperh->perh->NCHS3 &= ~(0x1f << ((config->rank - 9) << 3)); hperh->perh->NCHS3 |= (config->channel << ((config->rank - 9) << 3)); @@ -994,12 +1048,12 @@ ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t * if (config->channel <= 15) { hperh->perh->SMPT1 &= ~(0x03 << (config->channel << 1)); - hperh->perh->SMPT1 |= config->sampling_time << (config->channel << 1); + hperh->perh->SMPT1 |= config->samp_time << (config->channel << 1); } else { hperh->perh->SMPT2 &= ~(0x03 << ((config->channel - 16) << 1)); - hperh->perh->SMPT2 |= config->sampling_time << ((config->channel - 16) << 1); + hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 16) << 1); } __UNLOCK(hperh); @@ -1014,51 +1068,53 @@ ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t * * @param config: Structure of ADC channel for insert group. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *config) +ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config) { uint8_t tmp1, tmp2; ald_status_t tmp_status = OK; assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - assert_param(IS_ADC_IH_RANK_TYPE(config->rank)); + assert_param(IS_ADC_ICH_RANK_TYPE(config->rank)); assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); - assert_param(IS_ADC_NBR_OF_IST_TYPE(config->nbr)); - assert_param(IS_FUNC_STATE(config->disc_mode)); + assert_param(IS_ADC_NBR_OF_IST_TYPE(config->ich_len)); assert_param(IS_FUNC_STATE(config->auto_inj)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); __LOCK(hperh); - if (hperh->init.scan_mode == ADC_SCAN_DISABLE) + if (hperh->init.scan_mode == DISABLE) { switch (config->rank) { - case ADC_IH_RANK_1: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS1_MSK, config->channel << ADC_ICHS_IS1_POSS); - break; - case ADC_IH_RANK_2: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS2_MSK, config->channel << ADC_ICHS_IS1_POSS); - break; - case ADC_IH_RANK_3: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS3_MSK, config->channel << ADC_ICHS_IS1_POSS); - break; - case ADC_IH_RANK_4: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS4_MSK, config->channel << ADC_ICHS_IS1_POSS); - break; - default: - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - tmp_status = ERROR; - break; + case ADC_ICH_RANK_1: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS1_MSK, config->channel << ADC_ICHS_IS1_POSS); + break; + + case ADC_ICH_RANK_2: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS2_MSK, config->channel << ADC_ICHS_IS2_POSS); + break; + + case ADC_ICH_RANK_3: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS3_MSK, config->channel << ADC_ICHS_IS3_POSS); + break; + + case ADC_ICH_RANK_4: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS4_MSK, config->channel << ADC_ICHS_IS4_POSS); + break; + + default: + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_INTERNAL; + tmp_status = ERROR; + break; } } else { - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nbr << ADC_CHSL_ISL_POSS); + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); tmp1 = config->rank ; - tmp2 = config->nbr; + tmp2 = config->ich_len; if (tmp1 <= tmp2) { @@ -1069,28 +1125,21 @@ ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *confi else { hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); + hperh->perh->ICHS |= config->channel + << ((tmp1 - 1) << 3); } } if (config->auto_inj == ENABLE) { - if (hperh->ist_trig_mode == ADC_TRIG_SOFT) - { - SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); - } - else - { - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - tmp_status = ERROR; - } + SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); } - if (config->disc_mode == ENABLE) + if (hperh->init.disc_mode == ADC_ICH_DISC_EN) { if (config->auto_inj == DISABLE) { - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nbr << ADC_CHSL_ISL_POSS); + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); } else @@ -1114,24 +1163,25 @@ ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *confi switch (config->rank) { - case ADC_IH_RANK_1: - hperh->perh->ICHOFF[0] = config->offset; - break; - case ADC_IH_RANK_2: - hperh->perh->ICHOFF[1] = config->offset; - break; - case ADC_IH_RANK_3: - hperh->perh->ICHOFF[2] = config->offset; - break; - case ADC_IH_RANK_4: - hperh->perh->ICHOFF[3] = config->offset; - break; - default: - break; - } + case ADC_ICH_RANK_1: + hperh->perh->ICHOFF[0] = config->offset; + break; - if (hperh->ist_trig_mode != ADC_TRIG_SOFT) - pis_create(&hperh->inj_pis_handle); + case ADC_ICH_RANK_2: + hperh->perh->ICHOFF[1] = config->offset; + break; + + case ADC_ICH_RANK_3: + hperh->perh->ICHOFF[2] = config->offset; + break; + + case ADC_ICH_RANK_4: + hperh->perh->ICHOFF[3] = config->offset; + break; + + default: + break; + } __UNLOCK(hperh); return tmp_status; @@ -1144,7 +1194,7 @@ ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *confi * @param config: Structure of ADC analog watchdog configuration * @retval ALD status */ -ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config) +ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config) { assert_param(IS_ADC_TYPE(hperh->perh)); @@ -1161,9 +1211,9 @@ ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *c assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); if (config->it_mode == DISABLE) - adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); else - adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); + ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); @@ -1190,7 +1240,7 @@ ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *c * - DISABLE * @retval None */ -void adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) +void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) { assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_IT_TYPE(it)); @@ -1213,7 +1263,7 @@ void adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) * - SET * - RESET */ -it_status_t adc_get_it_status(adc_handle_t *hperh, adc_it_t it) +it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it) { assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_IT_TYPE(it)); @@ -1232,7 +1282,7 @@ it_status_t adc_get_it_status(adc_handle_t *hperh, adc_it_t it) * - SET * - RESET */ -flag_status_t adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) +flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) { assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_FLAGS_TYPE(flag)); @@ -1249,7 +1299,7 @@ flag_status_t adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) * This parameter can be one of the @ref adc_flag_t. * @retval None */ -void adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) +void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) { assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_FLAGS_TYPE(flag)); @@ -1272,7 +1322,7 @@ void adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) * the configuration information for the specified ADC module. * @retval state */ -uint32_t adc_get_state(adc_handle_t *hperh) +uint32_t ald_adc_get_state(adc_handle_t *hperh) { return hperh->state; } @@ -1283,7 +1333,7 @@ uint32_t adc_get_state(adc_handle_t *hperh) * the configuration information for the specified ADC module. * @retval ADC Error Code */ -uint32_t adc_get_error(adc_handle_t *hperh) +uint32_t ald_adc_get_error(adc_handle_t *hperh) { return hperh->error_code; } diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c similarity index 85% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c index 0a6e766b6aae190bf832b9d59e6574f67d5611b3..7035bc506719ee6d2087ea7f769ff69bc515c95b 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -40,8 +40,8 @@ ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) bkpc_ldo_config() API can configure LDO in backup field. - (+) bkpc_bor_config() API can configure BOR in backup field. + (+) ald_bkpc_ldo_config() API can configure LDO in backup field. + (+) ald_bkpc_bor_config() API can configure BOR in backup field. @endverbatim * @{ @@ -53,7 +53,7 @@ * @param state: DISABLE/ENABLE. * @retval None */ -void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state) +void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state) { assert_param(IS_BKPC_LDO_OUTPUT(output)); assert_param(IS_FUNC_STATE(state)); @@ -74,7 +74,7 @@ void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state) * @param state: DISABLE/ENABLE. * @retval None */ -void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) +void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) { assert_param(IS_BKPC_BOR_VOL(vol)); assert_param(IS_FUNC_STATE(state)); @@ -102,8 +102,8 @@ void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) ##### IO operation functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) bkpc_write_ram() API can write data in backup ram. - (+) bkpc_read_ram() API can read data from backup ram. + (+) ald_bkpc_write_ram() API can write data in backup ram. + (+) ald_bkpc_read_ram() API can read data from backup ram. @endverbatim * @{ @@ -115,7 +115,7 @@ void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) * @param value: Value which will be written to backup ram. * @retval None */ -void bkpc_write_ram(uint8_t idx, uint32_t value) +void ald_bkpc_write_ram(uint8_t idx, uint32_t value) { assert_param(IS_BKPC_RAM_IDX(idx)); @@ -131,7 +131,7 @@ void bkpc_write_ram(uint8_t idx, uint32_t value) * @param idx: Index of backup word. * @retval The data. */ -uint32_t bkpc_read_ram(uint8_t idx) +uint32_t ald_bkpc_read_ram(uint8_t idx) { assert_param(IS_BKPC_RAM_IDX(idx)); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c similarity index 91% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c index 4ddc9901f9a7ea03496fd00d946f2f5f08e7bc00..26a67f249377d3d27d137bacd4a0af09dd0f10f2 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -48,9 +48,10 @@ * @param data: The data; * @retval The value of square root. */ -uint32_t calc_sqrt(uint32_t data) +uint32_t ald_calc_sqrt(uint32_t data) { WRITE_REG(CALC->RDCND, data); + while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK)); return READ_REG(CALC->SQRTRES); @@ -63,7 +64,7 @@ uint32_t calc_sqrt(uint32_t data) * @param remainder: The value of the remainder. * @retval The result of division. */ -uint32_t calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) +uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) { CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); @@ -83,7 +84,7 @@ uint32_t calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) * @param remainder: The value of the remainder. * @retval The result of division. */ -int32_t calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) +int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) { SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); @@ -100,7 +101,7 @@ int32_t calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) * @brief Get the flag of divisor is zero. * @retval The status, SET/RESET. */ -flag_status_t calc_get_dz_status(void) +flag_status_t ald_calc_get_dz_status(void) { if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK)) return SET; diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c similarity index 73% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c index cb01604b872918cf9587e7dc2e07dff927bdc65c..cc55f867c5e465bd8c115412c034661e073cde16 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c @@ -24,27 +24,27 @@ (#) CAN pins configuration (++) Enable the clock for the CAN GPIOs; (++) Connect and configure the involved CAN pins using the - following function gpio_init(); - (#) Initialise and configure the CAN using can_init() function. - (#) Transmit the CAN frame using can_send()/can_send_by_it() function. - (#) Receive a CAN frame using can_recv()/can_recv_by_it function. + following function ald_gpio_init(); + (#) Initialise and configure the CAN using ald_can_init() function. + (#) Transmit the CAN frame using ald_can_send()/ald_can_send_by_it() function. + (#) Receive a CAN frame using ald_can_recv()/ald_can_recv_by_it function. *** Polling mode IO operation *** ================================= [..] (+) Start the CAN peripheral transmission and wait the end of this operation - using can_send(), at this stage user can specify the value of timeout + using ald_can_send(), at this stage user can specify the value of timeout according to his end application. (+) Start the CAN peripheral reception and wait the end of this operation - using can_recv(), at this stage user can specify the value of timeout + using ald_can_recv(), at this stage user can specify the value of timeout according to his end application *** Interrupt mode IO operation *** =================================== [..] - (+) Start the CAN peripheral transmission using can_send_by_it() - (+) Start the CAN peripheral reception using can_recv_by_it() - (+) Use can_irq_handler() called under the used CAN Interrupt subroutine + (+) Start the CAN peripheral transmission using ald_can_send_by_it() + (+) Start the CAN peripheral reception using ald_can_recv_by_it() + (+) Use ald_can_irq_handler() called under the used CAN Interrupt subroutine (+) At CAN end of transmission pherh->tx_cplt_cbk() function is executed and user can add his own code by customization of function pointer pherh->tx_cplt_cbk() (+) In case of CAN Error, pherh->rx_cplt_cbk() function is executed and user can @@ -83,7 +83,7 @@ * @{ */ static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num); -static ald_status_t __can_send_by_it(can_handle_t *hperh); +static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err); static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num); /** * @} @@ -116,7 +116,7 @@ static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num); * the configuration information for the specified CAN. * @retval Status, see ald_status_t. */ -ald_status_t can_init(can_handle_t *hperh) +ald_status_t ald_can_init(can_handle_t *hperh) { uint32_t tickstart = 0; @@ -137,14 +137,14 @@ ald_status_t can_init(can_handle_t *hperh) hperh->lock = UNLOCK; hperh->state = CAN_STATE_BUSY; - tickstart = __get_tick(); + tickstart = ald_get_tick(); CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); SET_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); while (!READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { - if ((__get_tick() - tickstart) > CAN_TIMEOUT_VALUE) + if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -167,11 +167,11 @@ ald_status_t can_init(can_handle_t *hperh) MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_BPSC_MSK, (hperh->init.psc - 1) << CAN_BTIME_BPSC_POSS); CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); - tickstart = __get_tick(); + tickstart = ald_get_tick(); while (READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { - if ((__get_tick() - tickstart) > CAN_TIMEOUT_VALUE) + if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -194,7 +194,7 @@ ald_status_t can_init(can_handle_t *hperh) * contains the filter configuration information. * @retval Status, see ald_status_t. */ -ald_status_t can_filter_config(can_handle_t *hperh, can_filter_t *config) +ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config) { uint32_t pos; @@ -247,7 +247,7 @@ ald_status_t can_filter_config(can_handle_t *hperh, can_filter_t *config) * @param hperh: pointer to a can_handle_t structure. * @retval None */ -void can_reset(can_handle_t *hperh) +void ald_can_reset(can_handle_t *hperh) { assert_param(IS_CAN_ALL(hperh->perh)); @@ -281,11 +281,11 @@ void can_reset(can_handle_t *hperh) /** * @brief Send a CAN frame message. * @param hperh: pointer to a can_handle_t structure. - * @param msg: message which will be snet. + * @param msg: message which will be sent. * @param timeout: specify Timeout value * @retval Status, see ald_status_t. */ -ald_status_t can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) +ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) { uint32_t tick; can_tx_mailbox_t idx; @@ -330,15 +330,16 @@ ald_status_t can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); } + MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); - tick = __get_tick(); + tick = ald_get_tick(); - while (!(can_get_tx_status(hperh, idx))) + while (!(ald_can_get_tx_status(hperh, idx))) { - if ((timeout == 0) || ((__get_tick() - tick) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -354,10 +355,10 @@ ald_status_t can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) /** * @brief Send a CAN frame message using interrupt. * @param hperh: pointer to a can_handle_t structure. - * @param msg: message which will be snet. + * @param msg: message which will be sent. * @retval Status, see ald_status_t. */ -ald_status_t can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) +ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) { uint8_t idx = CAN_TX_MAILBOX_NONE; @@ -404,12 +405,12 @@ ald_status_t can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) SET_BIT(hperh->state, CAN_STATE_TX_MASK); - can_interrupt_config(hperh, CAN_IT_EWG, ENABLE); - can_interrupt_config(hperh, CAN_IT_EPV, ENABLE); - can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); - can_interrupt_config(hperh, CAN_IT_LEC, ENABLE); - can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); - can_interrupt_config(hperh, CAN_IT_TME, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_TXM, ENABLE); SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); return OK; @@ -423,7 +424,7 @@ ald_status_t can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) * @param timeout: Specify timeout value * @retval Status, see ald_status_t. */ -ald_status_t can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout) +ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout) { uint32_t tick, stid, exid; @@ -432,11 +433,11 @@ ald_status_t can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, __LOCK(hperh); SET_BIT(hperh->state, CAN_STATE_RX_MASK); - tick = __get_tick(); + tick = ald_get_tick(); while (CAN_RX_MSG_PENDING(hperh, num) == 0) { - if ((timeout == 0) || ((__get_tick() - tick) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -479,7 +480,7 @@ ald_status_t can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, * @param msg: Storing message. * @retval Status, see ald_status_t. */ -ald_status_t can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg) +ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg) { assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_FIFO(num)); @@ -490,16 +491,16 @@ ald_status_t can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t SET_BIT(hperh->state, CAN_STATE_RX_MASK); hperh->rx_msg = msg; - can_interrupt_config(hperh, CAN_IT_EWG, ENABLE); - can_interrupt_config(hperh, CAN_IT_EPV, ENABLE); - can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); - can_interrupt_config(hperh, CAN_IT_LEC, ENABLE); - can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); if (num == CAN_RX_FIFO0) - can_interrupt_config(hperh, CAN_IT_FMP0, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_FP0, ENABLE); else - can_interrupt_config(hperh, CAN_IT_FMP1, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_FP1, ENABLE); return OK; } @@ -535,7 +536,7 @@ ald_status_t can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t * @param hperh: pointer to a can_handle_t. * @retval Status, see ald_status_t. */ -ald_status_t can_sleep(can_handle_t *hperh) +ald_status_t ald_can_sleep(can_handle_t *hperh) { uint32_t tick; @@ -546,11 +547,11 @@ ald_status_t can_sleep(can_handle_t *hperh) CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); SET_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); - tick = __get_tick(); + tick = ald_get_tick(); while ((!(READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK))) || READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { - if ((__get_tick() - tick) > CAN_TIMEOUT_VALUE) + if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -570,7 +571,7 @@ ald_status_t can_sleep(can_handle_t *hperh) * @param hperh: pointer to a can_handle_t structure. * @retval Status, see ald_status_t. */ -ald_status_t can_wake_up(can_handle_t *hperh) +ald_status_t ald_can_wake_up(can_handle_t *hperh) { uint32_t tick; @@ -580,11 +581,11 @@ ald_status_t can_wake_up(can_handle_t *hperh) hperh->state = CAN_STATE_BUSY; CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); - tick = __get_tick(); + tick = ald_get_tick(); while (READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK)) { - if ((__get_tick() - tick) > CAN_TIMEOUT_VALUE) + if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -603,71 +604,107 @@ ald_status_t can_wake_up(can_handle_t *hperh) * @param hperh: pointer to a can_handle_t structure. * @retval None */ -void can_irq_handler(can_handle_t *hperh) +void ald_can_irq_handler(can_handle_t *hperh) { - if (can_get_it_status(hperh, CAN_IT_TME)) + if (ald_can_get_it_status(hperh, CAN_IT_TXM)) { - if ((can_get_tx_status(hperh, CAN_TX_MAILBOX_0)) - || (can_get_tx_status(hperh, CAN_TX_MAILBOX_1)) - || (can_get_tx_status(hperh, CAN_TX_MAILBOX_2))) - __can_send_by_it(hperh); + if ((ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_0)) + || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_1)) + || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_2))) + __can_send_by_it(hperh, 0); + + if (hperh->perh->TXSTAT & CAN_TXSTAT_M0TXERR_MSK) + { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M0REQC_MSK); + __can_send_by_it(hperh, 1); + } + + if (hperh->perh->TXSTAT & CAN_TXSTAT_M1TXERR_MSK) + { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M1REQC_MSK); + __can_send_by_it(hperh, 1); + } + + if (hperh->perh->TXSTAT & CAN_TXSTAT_M2TXERR_MSK) + { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M2REQC_MSK); + __can_send_by_it(hperh, 1); + } } - if ((can_get_it_status(hperh, CAN_IT_FMP0)) + if ((ald_can_get_it_status(hperh, CAN_IT_FP0)) && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO0) != 0)) __can_recv_by_it(hperh, CAN_RX_FIFO0); - if ((can_get_it_status(hperh, CAN_IT_FMP1)) + if ((ald_can_get_it_status(hperh, CAN_IT_FP1)) && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO1) != 0)) __can_recv_by_it(hperh, CAN_RX_FIFO1); - if ((can_get_flag_status(hperh, CAN_FLAG_EWG)) - && (can_get_it_status(hperh, CAN_IT_EWG)) - && (can_get_it_status(hperh, CAN_IT_ERR))) + if ((ald_can_get_flag_status(hperh, CAN_FLAG_WARN)) + && (ald_can_get_it_status(hperh, CAN_IT_WARN)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) hperh->err |= CAN_ERROR_EWG; - if ((can_get_flag_status(hperh, CAN_FLAG_EPV)) - && (can_get_it_status(hperh, CAN_IT_EPV)) - && (can_get_it_status(hperh, CAN_IT_ERR))) + if ((ald_can_get_flag_status(hperh, CAN_FLAG_PERR)) + && (ald_can_get_it_status(hperh, CAN_IT_PERR)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) hperh->err |= CAN_ERROR_EPV; - if ((can_get_flag_status(hperh, CAN_FLAG_BOF)) - && (can_get_it_status(hperh, CAN_IT_BOF)) - && (can_get_it_status(hperh, CAN_IT_ERR))) + if ((ald_can_get_flag_status(hperh, CAN_FLAG_BOF)) + && (ald_can_get_it_status(hperh, CAN_IT_BOF)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) hperh->err |= CAN_ERROR_BOF; if (READ_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK) - && (can_get_it_status(hperh, CAN_IT_LEC)) - && (can_get_it_status(hperh, CAN_IT_ERR))) + && (ald_can_get_it_status(hperh, CAN_IT_PRERR)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) { switch (READ_BITS(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK, CAN_ERRSTAT_PRERRF_POSS)) { - case (1): - hperh->err |= CAN_ERROR_STF; - break; - case (2): - hperh->err |= CAN_ERROR_FOR; - break; - case (3): - hperh->err |= CAN_ERROR_ACK; - break; - case (4): - hperh->err |= CAN_ERROR_BR; - break; - case (5): - hperh->err |= CAN_ERROR_BD; - break; - case (6): - hperh->err |= CAN_ERROR_CRC; - break; - default: - break; + case (1): + hperh->err |= CAN_ERROR_STF; + break; + + case (2): + hperh->err |= CAN_ERROR_FOR; + break; + + case (3): + hperh->err |= CAN_ERROR_ACK; + break; + + case (4): + hperh->err |= CAN_ERROR_BR; + break; + + case (5): + hperh->err |= CAN_ERROR_BD; + break; + + case (6): + hperh->err |= CAN_ERROR_CRC; + break; + + default: + break; } CLEAR_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK); + + if (READ_BIT(hperh->perh->IE, CAN_IE_TXMEIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); + + if (READ_BIT(hperh->perh->IE, CAN_IE_F0PIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); + + if (READ_BIT(hperh->perh->IE, CAN_IE_F1PIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); } + if ((ald_can_get_flag_status(hperh, CAN_FLAG_ERR)) && (hperh->err == CAN_ERROR_NONE)) + hperh->err = CAN_ERROR_UNK; + if (hperh->err != CAN_ERROR_NONE) { SET_BIT(hperh->perh->IFC, CAN_IFC_ERRIFC_MSK); @@ -684,45 +721,51 @@ void can_irq_handler(can_handle_t *hperh) * @param box: the index of the mailbox that is used for transmission. * @retval The new status of transmission(TRUE or FALSE). */ -type_bool_t can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box) +type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box) { assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_TX_MAILBOX(box)); switch (box) { - case CAN_TX_MAILBOX_0: - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0REQC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0TXC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) - return FALSE; - - return TRUE; - - case CAN_TX_MAILBOX_1: - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1REQC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1TXC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) - return FALSE; - - return TRUE; - - case CAN_TX_MAILBOX_2: - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2REQC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2TXC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) - return FALSE; - - return TRUE; - - default: - break; + case CAN_TX_MAILBOX_0: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0REQC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0TXC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_1: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1REQC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1TXC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_2: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2REQC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2TXC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + return FALSE; + + return TRUE; + + default: + break; } return FALSE; @@ -734,24 +777,27 @@ type_bool_t can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box) * @param box: the index of the mailbox that is used for transmission. * @retval None */ -void can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box) +void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box) { assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_TX_MAILBOX(box)); switch (box) { - case CAN_TX_MAILBOX_0: - SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0STPREQ_MSK); - break; - case CAN_TX_MAILBOX_1: - SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1STPREQ_MSK); - break; - case CAN_TX_MAILBOX_2: - SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2STPREQ_MSK); - break; - default: - break; + case CAN_TX_MAILBOX_0: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0STPREQ_MSK); + break; + + case CAN_TX_MAILBOX_1: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1STPREQ_MSK); + break; + + case CAN_TX_MAILBOX_2: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2STPREQ_MSK); + break; + + default: + break; } return; @@ -768,7 +814,7 @@ void can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box) * @arg DISABLE * @retval None */ -void can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state) +void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state) { assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_IT(it)); @@ -791,7 +837,7 @@ void can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state) * - 0: RESET * - 1: SET */ -it_status_t can_get_it_status(can_handle_t *hperh, can_it_t it) +it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it) { assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_IT(it)); @@ -811,7 +857,7 @@ it_status_t can_get_it_status(can_handle_t *hperh, can_it_t it) * - 0: RESET * - 1: SET */ -flag_status_t can_get_flag_status(can_handle_t *hperh, can_flag_t flag) +flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag) { uint32_t idx = (flag >> 20) & 0x7; uint32_t _flag = flag & 0xFF8FFFFF; @@ -820,33 +866,38 @@ flag_status_t can_get_flag_status(can_handle_t *hperh, can_flag_t flag) switch (idx) { - case 0: - if (READ_BIT(hperh->perh->STAT, _flag)) - return SET; - - break; - case 1: - if (READ_BIT(hperh->perh->TXSTAT, _flag)) - return SET; - - break; - case 2: - if (READ_BIT(hperh->perh->RXF0, _flag)) - return SET; - - break; - case 3: - if (READ_BIT(hperh->perh->RXF1, _flag)) - return SET; - - break; - case 4: - if (READ_BIT(hperh->perh->ERRSTAT, _flag)) - return SET; - - break; - default: - break; + case 0: + if (READ_BIT(hperh->perh->STAT, _flag)) + return SET; + + break; + + case 1: + if (READ_BIT(hperh->perh->TXSTAT, _flag)) + return SET; + + break; + + case 2: + if (READ_BIT(hperh->perh->RXF0, _flag)) + return SET; + + break; + + case 3: + if (READ_BIT(hperh->perh->RXF1, _flag)) + return SET; + + break; + + case 4: + if (READ_BIT(hperh->perh->ERRSTAT, _flag)) + return SET; + + break; + + default: + break; } return RESET; @@ -857,7 +908,7 @@ flag_status_t can_get_flag_status(can_handle_t *hperh, can_flag_t flag) * @param flag: specifies the flag to check. * @retval None. */ -void can_clear_flag(can_handle_t *hperh, can_flag_t flag) +void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag) { uint32_t idx = (flag >> 20) & 0x7; uint32_t _flag = flag & 0xFF8FFFFF; @@ -866,20 +917,24 @@ void can_clear_flag(can_handle_t *hperh, can_flag_t flag) switch (idx) { - case 0: - WRITE_REG(hperh->perh->IFC, _flag); - break; - case 1: - WRITE_REG(hperh->perh->TXSTATC, _flag); - break; - case 2: - WRITE_REG(hperh->perh->RXF0C, _flag); - break; - case 3: - WRITE_REG(hperh->perh->RXF1C, _flag); - break; - default: - break; + case 0: + WRITE_REG(hperh->perh->IFC, _flag); + break; + + case 1: + WRITE_REG(hperh->perh->TXSTATC, _flag); + break; + + case 2: + WRITE_REG(hperh->perh->RXF0C, _flag); + break; + + case 3: + WRITE_REG(hperh->perh->RXF1C, _flag); + break; + + default: + break; } return; @@ -908,7 +963,7 @@ void can_clear_flag(can_handle_t *hperh, can_flag_t flag) * @param hperh: pointer to a can_handle_t structure. * @retval Status, see can_state_t. */ -can_state_t can_get_state(can_handle_t *hperh) +can_state_t ald_can_get_state(can_handle_t *hperh) { return hperh->state; } @@ -918,7 +973,7 @@ can_state_t can_get_state(can_handle_t *hperh) * @param hperh: pointer to a can_handle_t structure. * @retval CAN Error Code */ -can_error_t can_get_error(can_handle_t *hperh) +can_error_t ald_can_get_error(can_handle_t *hperh) { return hperh->err; } @@ -953,26 +1008,33 @@ static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num) /** * @brief transmits a CAN frame message using interrupt. * @param hperh: pointer to a can_handle_t structure. + * @param err: Error code, 0 - success, 1 - error. * @retval Status, see ald_status_t. */ -static ald_status_t __can_send_by_it(can_handle_t *hperh) +static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err) { - can_interrupt_config(hperh, CAN_IT_TME, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); if (hperh->state == CAN_STATE_BUSY_TX) { - can_interrupt_config(hperh, CAN_IT_EWG, DISABLE); - can_interrupt_config(hperh, CAN_IT_EPV, DISABLE); - can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); - can_interrupt_config(hperh, CAN_IT_LEC, DISABLE); - can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); } CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); - if (hperh->tx_cplt_cbk) + if ((err == 0) && (hperh->tx_cplt_cbk)) hperh->tx_cplt_cbk(hperh); + if ((err) && (hperh->error_cbk != NULL)) + { + hperh->err = CAN_ERROR_UNK; + hperh->error_cbk(hperh); + } + return OK; } @@ -1010,21 +1072,21 @@ static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num) if (num == CAN_RX_FIFO0) { can_rx_fifo_release(hperh, CAN_RX_FIFO0); - can_interrupt_config(hperh, CAN_IT_FMP0, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); } else { can_rx_fifo_release(hperh, CAN_RX_FIFO1); - can_interrupt_config(hperh, CAN_IT_FMP1, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); } if (hperh->state == CAN_STATE_BUSY_RX) { - can_interrupt_config(hperh, CAN_IT_EWG, DISABLE); - can_interrupt_config(hperh, CAN_IT_EPV, DISABLE); - can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); - can_interrupt_config(hperh, CAN_IT_LEC, DISABLE); - can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); } CLEAR_BIT(hperh->state, CAN_STATE_RX_MASK); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c similarity index 71% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c index 88fc71952a31cf7bded0ea0da0aba6efc6387e24..f5a6016d23ce682b856404f17ac3b7f605913c55 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -20,9 +20,9 @@ *** System clock configure *** ================================= [..] - (+) If you don't change system clock, you can using cmu_clock_config_default() API. + (+) If you don't change system clock, you can using ald_cmu_clock_config_default() API. It will select HRC as system clock. The system clock is 24MHz. - (+) If you want to change system clock, you can using cmu_clock_config() API. + (+) If you want to change system clock, you can using ald_cmu_clock_config() API. You can select one of the following as system clock: @ref CMU_CLOCK_HRC 2MHz or 24MHz @ref CMU_CLOCK_LRC 32768Hz @@ -30,13 +30,13 @@ @ref CMU_CLOCK_PLL1 32MHz, 48MHz or (32768*1024)Hz @ref CMU_CLOCK_HOSC 1MHz -- 24MHz (+) If you select CMU_CLOCK_PLL1 as system clock, it must config the PLL1 - using cmu_pll1_config() API. The input of clock must be 4MHz or PLL2. - (+) If you get current clock, you can using cmu_get_clock() API. + using ald_cmu_pll1_config() API. The input of clock must be 4MHz or PLL2. + (+) If you get system clock, you can using ald_cmu_get_sys_clock() API. *** BUS division control *** =================================== - PLCK sys_clk hclk1 + MCLK sys_clk hclk1 -------DIV_SYS-----------+------DIV_AHB1------------Peripheral(GPIO, CRC, ... etc.) | | pclk1 @@ -46,41 +46,41 @@ +------DIV_APB2------------Peripheral(ADC, WWDT, ... etc.) [..] - (+) Configure the division using cmu_div_config() API. - (+) Get sys_clk using cmu_get_sys_clock() API. - (+) Get hclk1 using cmu_get_hclk1_clock() API. - (+) Get pclk1 using cmu_get_pclk1_clock() API. - (+) Get pclk2 using cmu_get_pclk2_clock() API. + (+) Configure the division using ald_cmu_div_config() API. + (+) Get sys_clk using ald_cmu_get_sys_clock() API. + (+) Get hclk1 using ald_cmu_get_hclk1_clock() API. + (+) Get pclk1 using ald_cmu_get_pclk1_clock() API. + (+) Get pclk2 using ald_cmu_get_pclk2_clock() API. *** Clock safe configure *** =================================== [..] (+) If you select CMU_CLOCK_HOSC as system clock, you need enable - clock safe using cmu_hosc_safe_config() API. It will change + clock safe using ald_cmu_hosc_safe_config() API. It will change CMU_CLOCK_HRC as system clock, when the outer crystal stoped. (+) If you select CMU_CLOCK_LOSC as system clock, you need enable - clock safe using cmu_losc_safe_config() API. It will change + clock safe using ald_cmu_losc_safe_config() API. It will change CMU_CLOCK_LRC as system clock, when the outer crystal stoped. (+) If you select CMU_CLOCK_PLL1 as system clock, you need enable - clock safe using cmu_pll_safe_config() API. It will change + clock safe using ald_cmu_pll_safe_config() API. It will change CMU_CLOCK_HRC as system clock, when the pll1 is lose. - (+) The cmu_irq_cbk() will be invoked, when CMU interrupt has + (+) The ald_cmu_irq_cbk() will be invoked, when CMU interrupt has been occurred. You can overwrite this function in application. *** Clock output configure *** =================================== [..] - (+) Output high-speed clock using cmu_output_high_clock_config() API. - (+) Output low-speed clock using cmu_output_low_clock_config() API. + (+) Output high-speed clock using ald_cmu_output_high_clock_config() API. + (+) Output low-speed clock using ald_cmu_output_low_clock_config() API. *** Peripheral clock configure *** =================================== [..] - (+) Configure buzz clock using cmu_buzz_config() API. - (+) Selected lptim0 clock using cmu_lptim0_clock_select() API. - (+) Selected lpuart clock using cmu_lpuart0_clock_select() API. - (+) Selected lcd clock using cmu_lcd_clock_select() API. - (+) Enable/Disable peripheral clock using cmu_perh_clock_config() API. + (+) Configure buzz clock using ald_cmu_buzz_config() API. + (+) Selected lptim0 clock using ald_cmu_lptim0_clock_select() API. + (+) Selected lpuart clock using ald_cmu_lpuart0_clock_select() API. + (+) Selected lcd clock using ald_cmu_lcd_clock_select() API. + (+) Enable/Disable peripheral clock using ald_cmu_perh_clock_config() API. *** CMU ALD driver macros list *** ============================================= @@ -146,7 +146,7 @@ static void cmu_clock_update(uint32_t clock) __system_clock = clock; if (clock > 1000000) - __init_tick(TICK_INT_PRIORITY); + ald_tick_init(TICK_INT_PRIORITY); return; } @@ -155,7 +155,7 @@ static void cmu_clock_update(uint32_t clock) * @brief CMU module interrupt handler * @retval None */ -void CMU_Handler(void) +void ald_cmu_irq_handler(void) { /* HOSC stop */ if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) @@ -168,7 +168,8 @@ void CMU_Handler(void) && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); - cmu_irq_cbk(CMU_HOSC_STOP); + + ald_cmu_irq_cbk(CMU_HOSC_STOP); } /* HOSC start */ @@ -181,7 +182,8 @@ void CMU_Handler(void) if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000); - cmu_irq_cbk(CMU_HOSC_START); + + ald_cmu_irq_cbk(CMU_HOSC_START); } /* LOSC stop */ @@ -190,7 +192,7 @@ void CMU_Handler(void) SYSCFG_UNLOCK(); SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); SYSCFG_LOCK(); - cmu_irq_cbk(CMU_LOSC_STOP); + ald_cmu_irq_cbk(CMU_LOSC_STOP); } /* LOSC start */ @@ -199,7 +201,7 @@ void CMU_Handler(void) SYSCFG_UNLOCK(); SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK); SYSCFG_LOCK(); - cmu_irq_cbk(CMU_LOSC_START); + ald_cmu_irq_cbk(CMU_LOSC_START); } /* PLL1 lose */ @@ -213,7 +215,8 @@ void CMU_Handler(void) && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); - cmu_irq_cbk(CMU_PLL1_UNLOCK); + + ald_cmu_irq_cbk(CMU_PLL1_UNLOCK); } return; @@ -249,7 +252,7 @@ void CMU_Handler(void) * enable CMU_CLOCK_LRC(32768Hz). * @retval The status of ALD. */ -ald_status_t cmu_clock_config_default(void) +ald_status_t ald_cmu_clock_config_default(void) { uint32_t cnt = 4000, tmp; @@ -257,6 +260,7 @@ ald_status_t cmu_clock_config_default(void) /* Select HRC */ MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) @@ -265,7 +269,7 @@ ald_status_t cmu_clock_config_default(void) return ERROR; } - CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); /* Select 24Mhz */ + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); /* Select 24Mhz */ tmp = READ_REG(CMU->CLKENR); /* Enable HRC/LRC/LOSC */ @@ -288,7 +292,7 @@ ald_status_t cmu_clock_config_default(void) * on the parameter of clk. * @retval The status of ALD. */ -ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock) +ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock) { uint32_t cnt = 4000; @@ -297,127 +301,150 @@ ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock) switch (clk) { - case CMU_CLOCK_HRC: - assert_param(clock == 24000000 || clock == 2000000); + case CMU_CLOCK_HRC: + assert_param(clock == 24000000 || clock == 2000000); - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) - { - SYSCFG_LOCK(); - return ERROR; - } + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - if (clock == 24000000) - CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - else - SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) + { + SYSCFG_LOCK(); + return ERROR; + } - SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); + if (clock == 24000000) + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + else + SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - for (cnt = 4000; cnt; --cnt); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); - cmu_clock_update(clock); - break; + for (cnt = 4000; cnt; --cnt); - case CMU_CLOCK_LRC: - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + cnt = 4000; - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) - { - SYSCFG_LOCK(); - return ERROR; - } + cnt = 4000; - SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); + cmu_clock_update(clock); + break; - cmu_clock_update(32768); - break; + case CMU_CLOCK_LRC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - case CMU_CLOCK_LOSC: - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) - { - SYSCFG_LOCK(); - return ERROR; - } + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) + { + SYSCFG_LOCK(); + return ERROR; + } - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); + cnt = 4000; - cmu_clock_update(32768); - break; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); - case CMU_CLOCK_PLL1: - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + cnt = 4000; - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) - { - SYSCFG_LOCK(); - return ERROR; - } + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + cmu_clock_update(32768); + break; - for (cnt = 4000; cnt; --cnt); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + case CMU_CLOCK_LOSC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - cmu_clock_update(clock); - break; + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); - case CMU_CLOCK_HOSC: - assert_param(clock <= 24000000); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) + { + SYSCFG_LOCK(); + return ERROR; + } - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) - { - SYSCFG_LOCK(); - return ERROR; - } + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); - SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); - MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); + + cmu_clock_update(32768); + break; + + case CMU_CLOCK_PLL1: + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) + { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + + cmu_clock_update(clock); + break; - for (cnt = 4000; cnt; --cnt); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + case CMU_CLOCK_HOSC: + assert_param(clock <= 24000000); - cmu_clock_update(clock); - break; + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); - default: - break; + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) + { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + + cmu_clock_update(clock); + break; + + default: + break; } SYSCFG_LOCK(); @@ -434,7 +461,7 @@ ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock) * CMU_PLL1_OUTPUT_32M, and then the real clock is (32768x1024)Hz. * @retval None */ -void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) +void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) { uint32_t cnt = 4000; @@ -463,7 +490,9 @@ void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); SYSCFG_LOCK(); @@ -471,10 +500,10 @@ void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) } /** - * @brief Gets current system clock. - * @retval The value of system clock. + * @brief Gets MCLK clock. + * @retval The value of MCLK clock. */ -uint32_t cmu_get_clock(void) +uint32_t ald_cmu_get_clock(void) { return __system_clock; } @@ -487,7 +516,7 @@ uint32_t cmu_get_clock(void) * - 0 Success * - -1 Failed */ -int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq) +int32_t ald_cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq) { uint32_t cnt = 5000, tmp; @@ -505,7 +534,9 @@ int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output WRITE_REG(CMU->HRCACR, tmp); while (cnt--); + cnt = 30000; + while ((READ_BIT(CMU->HRCACR, CMU_HRCACR_BUSY_MSK)) && (--cnt)); if (READ_BITS(CMU->HRCACR, CMU_HRCACR_STA_MSK, CMU_HRCACR_STA_POSS) != 1) @@ -534,10 +565,10 @@ int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output ============================================================================== [..] This section provides functions allowing to: (+) Configure the bus division. - (+) Get ahb1 clock. - (+) Get sys bus clock. - (+) Get apb1 clock. - (+) Get apb2 clock. + (+) Get AHB1 clock. + (+) Get system clock. + (+) Get APB1 clock. + (+) Get APB2 clock. @endverbatim * @{ @@ -553,7 +584,7 @@ int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output * @param div: The value of divider. * @retval None */ -void cmu_div_config(cmu_bus_t bus, cmu_div_t div) +void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div) { assert_param(IS_CMU_BUS(bus)); assert_param(IS_CMU_DIV(div)); @@ -562,24 +593,35 @@ void cmu_div_config(cmu_bus_t bus, cmu_div_t div) switch (bus) { - case CMU_HCLK_1: - MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); - break; + case CMU_HCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); + break; - case CMU_SYS: - MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); - break; + case CMU_SYS: + MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); - case CMU_PCLK_1: - MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); - break; + if ((__system_clock >> div) <= 1000000) + { + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + } + else + { + ald_tick_init(TICK_INT_PRIORITY); + } - case CMU_PCLK_2: - MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); - break; + break; + + case CMU_PCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); + break; + + case CMU_PCLK_2: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); + break; - default: - break; + default: + break; } SYSCFG_LOCK(); @@ -590,7 +632,7 @@ void cmu_div_config(cmu_bus_t bus, cmu_div_t div) * @brief Get AHB1 clock. * @retval The value of AHB1 clock. */ -uint32_t cmu_get_hclk1_clock(void) +uint32_t ald_cmu_get_hclk1_clock(void) { uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS); @@ -599,10 +641,10 @@ uint32_t cmu_get_hclk1_clock(void) } /** - * @brief Get SYS clock - * @retval The value of SYS clock + * @brief Get system clock + * @retval The value of system clock */ -uint32_t cmu_get_sys_clock(void) +uint32_t ald_cmu_get_sys_clock(void) { uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); @@ -613,7 +655,7 @@ uint32_t cmu_get_sys_clock(void) * @brief Get APB1 clock. * @retval The value of APB1 clock. */ -uint32_t cmu_get_pclk1_clock(void) +uint32_t ald_cmu_get_pclk1_clock(void) { uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS); @@ -625,7 +667,7 @@ uint32_t cmu_get_pclk1_clock(void) * @brief Get APB2 clock. * @retval The value of APB2 clock. */ -uint32_t cmu_get_pclk2_clock(void) +uint32_t ald_cmu_get_pclk2_clock(void) { uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS); @@ -659,7 +701,7 @@ uint32_t cmu_get_pclk2_clock(void) * @param status: The new status. * @retval None */ -void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) +void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) { assert_param(IS_CMU_HOSC_RANGE(clock)); assert_param(IS_FUNC_STATE(status)); @@ -673,7 +715,7 @@ void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); - mcu_irq_config(CMU_IRQn, 3, ENABLE); + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); } else { @@ -681,7 +723,7 @@ void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) - mcu_irq_config(CMU_IRQn, 3, DISABLE); + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); } SYSCFG_LOCK(); @@ -693,7 +735,7 @@ void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) * @param status: The new status. * @retval None */ -void cmu_losc_safe_config(type_func_t status) +void ald_cmu_losc_safe_config(type_func_t status) { assert_param(IS_FUNC_STATE(status)); SYSCFG_UNLOCK(); @@ -704,7 +746,7 @@ void cmu_losc_safe_config(type_func_t status) SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); - mcu_irq_config(CMU_IRQn, 3, ENABLE); + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); } else { @@ -712,7 +754,7 @@ void cmu_losc_safe_config(type_func_t status) CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) - mcu_irq_config(CMU_IRQn, 3, DISABLE); + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); } SYSCFG_LOCK(); @@ -724,7 +766,7 @@ void cmu_losc_safe_config(type_func_t status) * @param status: The new status. * @retval None */ -void cmu_pll_safe_config(type_func_t status) +void ald_cmu_pll_safe_config(type_func_t status) { assert_param(IS_FUNC_STATE(status)); SYSCFG_UNLOCK(); @@ -736,7 +778,7 @@ void cmu_pll_safe_config(type_func_t status) SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); - mcu_irq_config(CMU_IRQn, 3, ENABLE); + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); } else { @@ -744,7 +786,7 @@ void cmu_pll_safe_config(type_func_t status) CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0) - mcu_irq_config(CMU_IRQn, 3, DISABLE); + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); } SYSCFG_LOCK(); @@ -756,7 +798,7 @@ void cmu_pll_safe_config(type_func_t status) * @param sr: The state type, see @ref cmu_clock_state_t. * @retval SET/RESET */ -flag_status_t cmu_get_clock_state(cmu_clock_state_t sr) +flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr) { assert_param(IS_CMU_CLOCK_STATE(sr)); @@ -772,7 +814,7 @@ flag_status_t cmu_get_clock_state(cmu_clock_state_t sr) * implementations in user file. * @retval None */ -__weak void cmu_irq_cbk(cmu_security_t se) +__weak void ald_cmu_irq_cbk(cmu_security_t se) { return; } @@ -818,8 +860,8 @@ __weak void cmu_irq_cbk(cmu_security_t se) * @param status: The new status. * @retval None */ -void cmu_output_high_clock_config(cmu_output_high_sel_t sel, - cmu_output_high_div_t div, type_func_t status) +void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, + cmu_output_high_div_t div, type_func_t status) { assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); assert_param(IS_CMU_OUTPUT_HIGH_DIV(div)); @@ -853,7 +895,7 @@ void cmu_output_high_clock_config(cmu_output_high_sel_t sel, * @param status: The new status. * @retval None */ -void cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) +void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) { assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); assert_param(IS_FUNC_STATE(status)); @@ -903,7 +945,7 @@ void cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) * @param status: The new status. * @retval None */ -void cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) +void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) { assert_param(IS_CMU_BUZZ_DIV(div)); assert_param(IS_FUNC_STATE(status)); @@ -942,7 +984,7 @@ void cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) * @arg CMU_LP_PERH_CLOCK_SEL_HOSM * @retval None */ -void cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) +void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) { assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); @@ -970,7 +1012,7 @@ void cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) * @arg CMU_LP_PERH_CLOCK_SEL_HOSM * @retval None */ -void cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) +void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) { assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); @@ -992,7 +1034,7 @@ void cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) * @arg CMU_LCD_SEL_HOSC_1M * @retval None */ -void cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) +void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) { assert_param(IS_CMU_LCD_CLOCK_SEL(clock)); @@ -1009,7 +1051,7 @@ void cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) * @param status: The new status. * @retval None */ -void cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) +void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) { uint32_t idx, pos; @@ -1044,40 +1086,40 @@ void cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) { switch (idx) { - case 0: - SET_BIT(CMU->AHB1ENR, pos); - break; + case 0: + SET_BIT(CMU->AHB1ENR, pos); + break; - case 1: - SET_BIT(CMU->APB1ENR, pos); - break; + case 1: + SET_BIT(CMU->APB1ENR, pos); + break; - case 2: - SET_BIT(CMU->APB2ENR, pos); - break; + case 2: + SET_BIT(CMU->APB2ENR, pos); + break; - default: - break; + default: + break; } } else { switch (idx) { - case 0: - CLEAR_BIT(CMU->AHB1ENR, pos); - break; + case 0: + CLEAR_BIT(CMU->AHB1ENR, pos); + break; - case 1: - CLEAR_BIT(CMU->APB1ENR, pos); - break; + case 1: + CLEAR_BIT(CMU->APB1ENR, pos); + break; - case 2: - CLEAR_BIT(CMU->APB2ENR, pos); - break; + case 2: + CLEAR_BIT(CMU->APB2ENR, pos); + break; - default: - break; + default: + break; } } diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c similarity index 54% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c index d03a935835fdaedf4b46670023a8771aff2b5fa1..d49b39fe564f2522393158e2de1dbe9be88a49c3 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c @@ -29,7 +29,7 @@ /** @addtogroup CRC_Private_Functions CRC Private Functions * @{ */ -void crc_reset(crc_handle_t *hperh); +void ald_crc_reset(crc_handle_t *hperh); #ifdef ALD_DMA static void crc_dma_calculate_cplt(void *arg); static void crc_dma_error(void *arg); @@ -55,7 +55,7 @@ void crc_reset(crc_handle_t *hperh); * the configuration information for the specified CRC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crc_init(crc_handle_t *hperh) +ald_status_t ald_crc_init(crc_handle_t *hperh) { uint32_t tmp = 0; @@ -69,7 +69,7 @@ ald_status_t crc_init(crc_handle_t *hperh) assert_param(IS_FUNC_STATE(hperh->init.data_rev)); assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); - crc_reset(hperh); + ald_crc_reset(hperh); __LOCK(hperh); CRC_ENABLE(hperh); @@ -79,7 +79,7 @@ ald_status_t crc_init(crc_handle_t *hperh) tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) | (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | - (1 << CRC_CR_BYTORD_POS)); + (0 << CRC_CR_BYTORD_POS)); hperh->perh->CR = tmp; hperh->perh->SEED = hperh->init.seed; @@ -101,14 +101,14 @@ ald_status_t crc_init(crc_handle_t *hperh) */ /** - * @brief Calculate the crc value of data. + * @brief Calculate the crc value of data by byte. * @param hperh: Pointer to a crc_handle_t structure that contains * the configuration information for the specified CRC module. * @param buf: Pointer to data buffer * @param size: The size of data to be calculate * @retval result, the result of a amount data */ -uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) +uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) { uint32_t i; uint32_t ret; @@ -119,6 +119,71 @@ uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) return 0; __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint8_t *) & (hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by halfword. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 2 bytes. + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint16_t *) & (hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 4 bytes + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); hperh->state = CRC_STATE_BUSY; for (i = 0; i < size; i++) @@ -130,6 +195,7 @@ uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) return ret; } + /** * @} */ @@ -150,7 +216,7 @@ uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) * @param channel: DMA channel as CRC transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) { if (hperh->state != CRC_STATE_READY) return BUSY; @@ -159,6 +225,7 @@ ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *r return ERROR; __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); hperh->state = CRC_STATE_BUSY; @@ -173,7 +240,7 @@ ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *r hperh->hdma.err_arg = (void *)hperh; hperh->hdma.err_cbk = &crc_dma_error; - dma_config_struct(&(hperh->hdma.config)); + ald_dma_config_struct(&(hperh->hdma.config)); hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE; hperh->hdma.config.src = (void *)buf; hperh->hdma.config.dst = (void *)&hperh->perh->DATA; @@ -183,7 +250,59 @@ ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *r hperh->hdma.config.msel = DMA_MSEL_CRC; hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; hperh->hdma.config.channel = channel; - dma_config_basic(&(hperh->hdma)); + ald_dma_config_basic(&(hperh->hdma)); + + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); + + return OK; +} + +/** + * @brief Calculate an amount of data used dma channel,data width is half-word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to half_word data buffer + * @param res: Pointer to result + * @param size: Amount of half_word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != CRC_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + + hperh->state = CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); __UNLOCK(hperh); CRC_DMA_ENABLE(hperh); @@ -191,13 +310,66 @@ ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *r return OK; } +/** + * @brief Calculate an amount of data used dma channel,data width is word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to word data buffer + * @param res: Pointer to result + * @param size: Amount of word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != CRC_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + + hperh->state = CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); + + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); + + return OK; +} + + /** * @brief Pauses the DMA Transfer. * @param hperh: Pointer to a crc_handle_t structure that contains * the configuration information for the specified CRC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crc_dma_pause(crc_handle_t *hperh) +ald_status_t ald_crc_dma_pause(crc_handle_t *hperh) { __LOCK(hperh); CRC_DMA_DISABLE(hperh); @@ -212,7 +384,7 @@ ald_status_t crc_dma_pause(crc_handle_t *hperh) * the configuration information for the specified CRC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crc_dma_resume(crc_handle_t *hperh) +ald_status_t ald_crc_dma_resume(crc_handle_t *hperh) { __LOCK(hperh); CRC_DMA_ENABLE(hperh); @@ -227,7 +399,7 @@ ald_status_t crc_dma_resume(crc_handle_t *hperh) * the configuration information for the specified CRC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crc_dma_stop(crc_handle_t *hperh) +ald_status_t ald_crc_dma_stop(crc_handle_t *hperh) { __LOCK(hperh); CRC_DMA_DISABLE(hperh); @@ -253,7 +425,7 @@ ald_status_t crc_dma_stop(crc_handle_t *hperh) * the configuration information for the specified CRC module. * @retval CRC state */ -crc_state_t crc_get_state(crc_handle_t *hperh) +crc_state_t ald_crc_get_state(crc_handle_t *hperh) { assert_param(IS_CRC(hperh->perh)); @@ -278,7 +450,7 @@ crc_state_t crc_get_state(crc_handle_t *hperh) * the configuration information for the specified CRC module. * @retval None */ -void crc_reset(crc_handle_t *hperh) +void ald_crc_reset(crc_handle_t *hperh) { hperh->perh->DATA = 0x0; hperh->perh->CR = 0x2; @@ -331,11 +503,11 @@ static void crc_dma_error(void *arg) /** * @} */ +#endif /* ALD_CRC */ /** * @} */ -#endif /* ALD_CRC */ /** * @} diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c similarity index 88% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c index 4cf2f6e5a9f135b041be20d4486dc90cb2814303..30d7f1e3ef8e6d1aed5f9e25f2ed997384684955 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -3,7 +3,7 @@ * * @file ald_crypt.c * @brief CRYPT module driver. - * This is the common part of the CRYPT initialization + * This is the common part of the CRYPT initialization * * @version V1.0 * @date 7 Dec 2017 @@ -58,7 +58,7 @@ void crypt_reset(crypt_handle_t *hperh); * the configuration information for the specified CRYPT module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_init(crypt_handle_t *hperh) +ald_status_t ald_crypt_init(crypt_handle_t *hperh) { uint32_t tmp = 0; @@ -92,7 +92,7 @@ ald_status_t crypt_init(crypt_handle_t *hperh) * @param key: Pointer to key data buffer * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key) +ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key) { uint32_t *temp = key; uint32_t i; @@ -123,7 +123,7 @@ ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key) * @param key: The pointer to the key * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key) +ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key) { uint32_t *temp = key; @@ -150,10 +150,11 @@ ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key) * @param iv: Pointer to iv data buffer * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) +ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) { uint32_t *temp = iv; uint32_t i; + if (hperh->state == CRYPT_STATE_BUSY) return BUSY; @@ -181,7 +182,7 @@ ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) * @param iv: Pointer to iv data buffer * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) +ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) { uint32_t *temp = iv; @@ -220,7 +221,7 @@ ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) +ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) { uint32_t count = 0; uint32_t i; @@ -248,7 +249,7 @@ ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t * plain_buf++; } - while (crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); for (i = 0; i < hperh->step; i++) { @@ -273,7 +274,7 @@ ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t * * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) +ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) { uint32_t count = 0; uint32_t i; @@ -282,7 +283,7 @@ ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t if (hperh->init.mode == CRYPT_MODE_CTR) { - return crypt_encrypt(hperh, cipher_text, plain_text, size); + return ald_crypt_encrypt(hperh, cipher_text, plain_text, size); } if (hperh->state != CRYPT_STATE_READY) @@ -306,7 +307,7 @@ ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t cipher_buf++; } - while (crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); for (i = 0; i < hperh->step; i++) { @@ -357,7 +358,7 @@ void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv) * @param tag: Pointer to authentication tag buffer * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag) +ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag) { uint8_t GCM_HASH_in[0x60] = {0}; uint8_t ecb[16] = {0}; @@ -376,53 +377,65 @@ ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint3 { GCM_HASH_in [i] = * (aadata + i); } + len += alen; + for (i = 0; i < v / 8; i++) { GCM_HASH_in[i + len] = 0; } + len += v / 8; + for (i = 0; i < size; i++) { GCM_HASH_in[i + len] = * (cipher_text + i); } + len += size; + for (i = 0; i < u / 8; i++) { GCM_HASH_in[i + len] = 0; } + len += u / 8; for (i = 0; i < 4; i++) { GCM_HASH_in[i + len] = 0; } + len += 4; for (i = 0; i < 4; i++) { GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF; } + len += 4; for (i = 0; i < 4; i++) { GCM_HASH_in[i + len] = 0; } + len += 4; for (i = 0; i < 4; i++) { GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF; } + len += 4; CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS); - crypt_encrypt(hperh, ecb, ecb, 16); + ald_crypt_encrypt(hperh, ecb, ecb, 16); k = len / 16; + for (i = 0; i < 16; i++) { tag[i] = 0; @@ -430,6 +443,7 @@ ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint3 cipher_text_temp = (uint32_t *)GCM_HASH_in; tag_temp = (uint32_t *)tag; + for (i = 0; i < k; i++) { for (j = 0; j < 4; j++) @@ -445,13 +459,13 @@ ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint3 * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode */ tag_temp = (uint32_t *)tag; - crypt_init(hperh); + ald_crypt_init(hperh); CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS); - crypt_write_key(hperh, hperh->key); + ald_crypt_write_key(hperh, hperh->key); hperh->iv[3] = 1; - crypt_write_ivr(hperh, hperh->iv); - crypt_encrypt(hperh, tag, tag, 16); + ald_crypt_write_ivr(hperh, hperh->iv); + ald_crypt_encrypt(hperh, tag, tag, 16); return OK; } @@ -466,7 +480,7 @@ ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint3 * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) +ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) { uint32_t i; uint32_t *plain_buf = (uint32_t *)plain_text; @@ -486,7 +500,7 @@ ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uin hperh->plain_text = plain_text; hperh->cipher_text = cipher_text; hperh->size = size; - crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); for (i = 0; i < hperh->step; i++) { @@ -508,14 +522,14 @@ ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uin * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) +ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) { uint32_t i; uint32_t *cipher_buf = (uint32_t *)cipher_text; if (hperh->init.mode == CRYPT_MODE_CTR) { - return crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); + return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); } if (hperh->state != CRYPT_STATE_READY) @@ -533,7 +547,7 @@ ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, ui hperh->plain_text = plain_text; hperh->cipher_text = cipher_text; hperh->size = size; - crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); for (i = 0; i < hperh->step; i++) { @@ -558,8 +572,8 @@ ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, ui * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, - uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) { if (hperh->state != CRYPT_STATE_READY) return ERROR; @@ -579,6 +593,7 @@ ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, if (hperh->hdma_m2p.perh == NULL) hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) hperh->hdma_p2m.perh = DMA0; @@ -594,7 +609,7 @@ ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); - dma_config_struct(&hperh->hdma_m2p.config); + ald_dma_config_struct(&hperh->hdma_m2p.config); hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; hperh->hdma_m2p.config.src = (void *)hperh->plain_text; hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; @@ -604,9 +619,9 @@ ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; hperh->hdma_m2p.config.channel = channel_m2p; - dma_config_basic(&(hperh->hdma_m2p)); + ald_dma_config_basic(&(hperh->hdma_m2p)); - dma_config_struct(&hperh->hdma_p2m.config); + ald_dma_config_struct(&hperh->hdma_p2m.config); hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text; @@ -616,7 +631,7 @@ ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; hperh->hdma_p2m.config.channel = channel_p2m; - dma_config_basic(&(hperh->hdma_p2m)); + ald_dma_config_basic(&(hperh->hdma_p2m)); CRYPT_DMA_ENABLE(hperh); __UNLOCK(hperh); @@ -636,14 +651,15 @@ ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, - uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) { if (hperh->init.mode == CRYPT_MODE_CTR) - return crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); + return ald_crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); if (hperh->state != CRYPT_STATE_READY) return ERROR; + if (plain_text == NULL || cipher_text == NULL || size == 0) return ERROR; @@ -657,6 +673,7 @@ ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, if (hperh->hdma_m2p.perh == NULL) hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) hperh->hdma_p2m.perh = DMA0; @@ -673,7 +690,7 @@ ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, CRYPT_SETDIR(hperh, CRYPT_DECRYPT); - dma_config_struct(&hperh->hdma_m2p.config); + ald_dma_config_struct(&hperh->hdma_m2p.config); hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; hperh->hdma_m2p.config.src = (void *)hperh->cipher_text; hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; @@ -683,9 +700,9 @@ ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; hperh->hdma_m2p.config.channel = channel_m2p; - dma_config_basic(&(hperh->hdma_m2p)); + ald_dma_config_basic(&(hperh->hdma_m2p)); - dma_config_struct(&hperh->hdma_p2m.config); + ald_dma_config_struct(&hperh->hdma_p2m.config); hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; hperh->hdma_p2m.config.dst = (void *)hperh->plain_text; @@ -695,7 +712,7 @@ ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; hperh->hdma_p2m.config.channel = channel_p2m; - dma_config_basic(&(hperh->hdma_p2m)); + ald_dma_config_basic(&(hperh->hdma_p2m)); CRYPT_DMA_ENABLE(hperh); __UNLOCK(hperh); @@ -718,7 +735,7 @@ ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, * the configuration information for the specified CRYPT module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_dma_pause(crypt_handle_t *hperh) +ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh) { __LOCK(hperh); CRYPT_DMA_DISABLE(hperh); @@ -734,7 +751,7 @@ ald_status_t crypt_dma_pause(crypt_handle_t *hperh) * the configuration information for the specified CRYPT module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_dma_resume(crypt_handle_t *hperh) +ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh) { __LOCK(hperh); CRYPT_DMA_ENABLE(hperh); @@ -749,7 +766,7 @@ ald_status_t crypt_dma_resume(crypt_handle_t *hperh) * the configuration information for the specified CRYPT module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_dma_stop(crypt_handle_t *hperh) +ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh) { __LOCK(hperh); CRYPT_DMA_DISABLE(hperh); @@ -766,7 +783,7 @@ ald_status_t crypt_dma_stop(crypt_handle_t *hperh) * the configuration information for the specified CRYPT module. * @retval None */ -void crypt_irq_handle(crypt_handle_t *hperh) +void ald_crypt_irq_handler(crypt_handle_t *hperh) { uint32_t i; uint32_t *in_buf; @@ -783,15 +800,16 @@ void crypt_irq_handle(crypt_handle_t *hperh) out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step; } - if (crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) + if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) { - crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); + ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); } for (i = 0; i < hperh->step; i++) *out_buf++ = CRYPT_READ_FIFO(hperh); hperh->count += hperh->step; + if (hperh->count > (hperh->size / 4)) { hperh->count = 0; @@ -829,7 +847,7 @@ void crypt_irq_handle(crypt_handle_t *hperh) * - DISABLE * @retval None */ -void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state) +void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state) { assert_param(IS_CRYPT(hperh->perh)); @@ -851,7 +869,7 @@ void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t st * - SET * - RESET */ -flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) +flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) { assert_param(IS_CRYPT(hperh->perh)); assert_param(IS_CRYPT_FLAG(flag)); @@ -871,7 +889,7 @@ flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) * @arg CRYPT_FLAG_DONE: encrypt or decrypt Complete flag. * @retval None */ -void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) +void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) { assert_param(IS_CRYPT(hperh->perh)); assert_param(IS_CRYPT_FLAG(flag)); @@ -885,13 +903,13 @@ void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) * @param hperh: Pointer to a crypt_handle_t structure that contains * the configuration information for the specified CRYPT module. * @param it: Specifies the CRYPT interrupt source to check. - * This parameter can be one of the following values: - * @arg crypt_it_t: CRYPT interrupt + * This parameter can be one of the following values: + * @arg crypt_it_t: CRYPT interrupt * @retval Status * - SET * - RESET */ -it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) +it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) { assert_param(IS_CRYPT_IT(it)); @@ -917,7 +935,7 @@ it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) * the configuration information for the specified CRYPT module. * @retval CRYPT state */ -crypt_state_t crypt_get_state(crypt_handle_t *hperh) +crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh) { assert_param(IS_CRYPT(hperh->perh)); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c similarity index 79% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c index 9a7d04c392bd00d7e312d180d02f157cec59c63b..5847fa627dd02189c59ee19a0fd597cd703c20f6 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -19,38 +19,38 @@ [..] The DMA driver can be used as follows: - (#) System initialization invokes dma_init(), mcu_ald_init() --> dma_init(). + (#) System initialization invokes ald_dma_init(), ald_cmu_init() --> ald_dma_init(). (#) Declare a dma_handle_t handle structure. (#) Configure the dma_handle_t structure, you can configure the - dma_config_t structure with the help of dma_config_struct(). + dma_config_t structure with the help of ald_dma_config_struct(). (#) Enable the DMA Configure: - (##) Memory -- memory: call dma_config_auto(). - (##) Peripheral -- memory: call dma_config_basic(). - (##) If you want use the dma easily, you can do this: - (+++) Memory -- memory: call dma_config_auto_easy(). - (+++) Peripheral -- memory: call dma_config_basic_easy(). + (##) Memory -- memory: call ald_dma_config_auto(). + (##) Peripheral -- memory: call ald_dma_config_basic(). + (##) If you want use the dma easily, you can do this: + (+++) Memory -- memory: call ald_dma_config_auto_easy(). + (+++) Peripheral -- memory: call ald_dma_config_basic_easy(). (#) Enable the DMA request signal: (##) Memory -- memory: the DMA request signal is request automatic. - (##) Peripheral -- memory: you need enable peripheral request signal. + (##) Peripheral -- memory: you need enable peripheral request signal. (#) If you enable DMA interrupt, the callback will be invoked: (##) When DMA transfer is completed, the cplt_cbk() will be invoked. - (##) When DMA bus occurs error, the err_cbk() will be invoked. + (##) When DMA bus occurs error, the err_cbk() will be invoked. (#) If you don't enable the DMA interrupt, you need do this: - (##) Polling the dma_get_flag_status(), this function's parameter is channel - or DMA_ERR. - (+++) When the function's Parameter is channel, if retval is SET, it means - the DMA transfer is completed. at this moment, you can do something, - and then, you need invoke dma_clear_flag_status() to clear flag. + (##) Polling the ald_dma_get_flag_status(), this function's parameter is channel + or DMA_ERR. + (+++) When the function's Parameter is channel, if retval is SET, it means + the DMA transfer is completed. at this moment, you can do something, + and then, you need invoke ald_dma_clear_flag_status() to clear flag. - (+++) When the function's Parameter is DMA_ERR, if retval is SET, it means - the DMA bus occurs error. at this moment, you can do something, - and then, you need invoke dma_clear_flag_status() to clear flag. + (+++) When the function's Parameter is DMA_ERR, if retval is SET, it means + the DMA bus occurs error. at this moment, you can do something, + and then, you need invoke ald_dma_clear_flag_status() to clear flag. @endverbatim */ @@ -167,7 +167,7 @@ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config * @brief Handle DMA interrupt * @retval None */ -void DMA_Handler(void) +void ald_dma_irq_handler(void) { uint32_t i, reg = DMA0->IFLAG; @@ -178,13 +178,13 @@ void DMA_Handler(void) if (dma0_cbk[i].cplt_cbk != NULL) dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg); - dma_clear_flag_status(DMA0, i); + ald_dma_clear_flag_status(DMA0, i); } } if (READ_BIT(reg, (1U << DMA_ERR))) { - dma_clear_flag_status(DMA0, DMA_ERR); + ald_dma_clear_flag_status(DMA0, DMA_ERR); for (i = 0; i < DMA_CH_COUNT; ++i) { @@ -193,7 +193,6 @@ void DMA_Handler(void) } } - dma0_irq_cbk(); return; } /** @@ -215,20 +214,20 @@ void DMA_Handler(void) =================================================================== [..] This subsection provides two functions to Initilizate DMA: - (+) dma_reset(): Reset the DMA register. - - (+) dma_init(): Initializate the DMA module. this function is - invoked by mcu_ald_init(). - this function do this: - (++) Initializte private variable dma_ctrl_base and dma_cbk. - (++) Reset DMA register. - (++) Set DMA interrupt priority: preempt_prio=1, sub_priority=1 - (++) Enable DMA interrupt. - (++) Enable DMA bus error interrupt. - (++) Configure CTRLBASE resigter. - (++) Enable DMA module. - - (+) dma_config_struct(): Configure dma_config_t + (+) ald_dma_reset(): Reset the DMA register. + + (+) ald_dma_init(): Initializate the DMA module. this function is + invoked by ald_cmu_init(). + this function do this: + (++) Initializte private variable dma_ctrl_base and dma_cbk. + (++) Reset DMA register. + (++) Set DMA interrupt priority: preempt_prio=1, sub_priority=1 + (++) Enable DMA interrupt. + (++) Enable DMA bus error interrupt. + (++) Configure CTRLBASE resigter. + (++) Enable DMA module. + + (+) ald_dma_config_struct(): Configure dma_config_t structure using default parameter. @endverbatim @@ -240,7 +239,7 @@ void DMA_Handler(void) * @param DMAx: Pointer to DMA peripheral * @retval None */ -void dma_reset(DMA_TypeDef *DMAx) +void ald_dma_reset(DMA_TypeDef *DMAx) { uint32_t i; @@ -264,18 +263,18 @@ void dma_reset(DMA_TypeDef *DMAx) /** * @brief DMA module initialization, this function - * is invoked by mcu_ald_init(). + * is invoked by ald_cmu_init(). * @param DMAx: Pointer to DMA peripheral * @retval None */ -void dma_init(DMA_TypeDef *DMAx) +void ald_dma_init(DMA_TypeDef *DMAx) { assert_param(IS_DMA(DMAx)); memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base)); memset(dma0_cbk, 0x0, sizeof(dma0_cbk)); - dma_reset(DMAx); + ald_dma_reset(DMAx); NVIC_SetPriority(DMA_IRQn, 2); NVIC_EnableIRQ(DMA_IRQn); SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK); @@ -292,7 +291,7 @@ void dma_init(DMA_TypeDef *DMAx) * @param p: Pointer to dma_config_t structure, see @ref dma_config_t * @retval None */ -void dma_config_struct(dma_config_t *p) +void ald_dma_config_struct(dma_config_t *p) { p->data_width = DMA_DATA_SIZE_BYTE; p->src_inc = DMA_DATA_INC_BYTE; @@ -323,19 +322,19 @@ void dma_config_struct(dma_config_t *p) This subsection provides some functions allowing to configure DMA channel. Include two type DMA transfer: (+) Carry data from memory to memory, this mode APIs are: - (++) dma_config_auto(): Configure DMA channel according to - the specified parameter in the dma_handle_t structure. - (++) dma_restart_auto(): Restart DMA transmitted. - (++) dma_config_auto_easy(): Configure DMA channel according - to the specified parameter. If you want use the dma easily, + (++) ald_dma_config_auto(): Configure DMA channel according to + the specified parameter in the dma_handle_t structure. + (++) ald_dma_restart_auto(): Restart DMA transmitted. + (++) ald_dma_config_auto_easy(): Configure DMA channel according + to the specified parameter. If you want use the dma easily, you can invoke this function. (+) Carry data from peripheral to memory or from memory to peripheral, this mode APIs are: - (++) dma_config_basic(): Configure DMA channel according to - the specified parameter in the dma_handle_t structure. - (++) dma_restart_basic(): Restart DMA transmitted. - (++) dma_config_basic_easy(): Configure DMA channel according - to the specified parameter. If you want use the dma easily, + (++) ald_dma_config_basic(): Configure DMA channel according to + the specified parameter in the dma_handle_t structure. + (++) ald_dma_restart_basic(): Restart DMA transmitted. + (++) ald_dma_config_basic_easy(): Configure DMA channel according + to the specified parameter. If you want use the dma easily, you can invoke this function. @endverbatim @@ -350,7 +349,7 @@ void dma_config_struct(dma_config_t *p) * configuration information for specified DMA channel. * @retval None */ -void dma_config_auto(dma_handle_t *hperh) +void ald_dma_config_auto(dma_handle_t *hperh) { dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; @@ -358,7 +357,7 @@ void dma_config_auto(dma_handle_t *hperh) dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config); - dma_clear_flag_status(hperh->perh, hperh->config.channel); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); @@ -375,7 +374,7 @@ void dma_config_auto(dma_handle_t *hperh) * @param size: Size. * @retval None */ -void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) +void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) { dma_descriptor_t *descr; @@ -400,7 +399,7 @@ void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); } - dma_clear_flag_status(hperh->perh, hperh->config.channel); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; descr->ctrl.n_minus_1 = size - 1; WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); @@ -419,19 +418,19 @@ void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) * @param src: Source data begin pointer * @param dst: Destination data begin pointer * @param size: The total number of DMA transfers that DMA cycle contains - * @param channel: Channel index which well be used. + * @param channel: Channel index which will be used. * @param cbk: DMA complete callback function * * @retval None */ -void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, - uint16_t size, uint8_t channel, void (*cbk)(void *arg)) +void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, + uint16_t size, uint8_t channel, void (*cbk)(void *arg)) { dma_handle_t hperh; assert_param(IS_DMA(DMAx)); - dma_config_struct(&hperh.config); + ald_dma_config_struct(&hperh.config); hperh.config.src = src; hperh.config.dst = dst; hperh.config.size = size; @@ -444,8 +443,8 @@ void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, hperh.cplt_arg = NULL; hperh.err_cbk = NULL; - dma_clear_flag_status(DMAx, channel); - dma_config_auto(&hperh); + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_auto(&hperh); return; } @@ -459,14 +458,14 @@ void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, * configuration information for specified DMA channel. * @retval None */ -void dma_config_basic(dma_handle_t *hperh) +void ald_dma_config_basic(dma_handle_t *hperh) { dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; - dma_clear_flag_status(hperh->perh, hperh->config.channel); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config); WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); @@ -483,7 +482,7 @@ void dma_config_basic(dma_handle_t *hperh) * @param size: Size. * @retval None */ -void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) +void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) { dma_descriptor_t *descr; @@ -508,7 +507,7 @@ void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); } - dma_clear_flag_status(hperh->perh, hperh->config.channel); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; descr->ctrl.n_minus_1 = size - 1; WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); @@ -527,19 +526,19 @@ void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) * @param size: The total number of DMA transfers that DMA cycle contains * @param msel: Input source to DMA channel @ref dma_msel_t * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t - * @param channel: Channel index which well be used + * @param channel: Channel index which will be used * @param cbk: DMA complete callback function * * @retval None * */ -void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, - dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) +void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) { dma_handle_t hperh; assert_param(IS_DMA(DMAx)); - dma_config_struct(&hperh.config); + ald_dma_config_struct(&hperh.config); if (((uint32_t)src) >= 0x40000000) hperh.config.src_inc = DMA_DATA_INC_NONE; @@ -559,8 +558,8 @@ void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t siz hperh.cplt_arg = NULL; hperh.err_cbk = NULL; - dma_clear_flag_status(DMAx, channel); - dma_config_basic(&hperh); + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_basic(&hperh); return; } @@ -580,14 +579,14 @@ void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t siz =================================================================== [..] This subsection provides some functions allowing to control DMA: - (+) dma_channel_config(): Control DMA channel ENABLE/DISABLE. - (+) dma_interrupt_config(): Control DMA channel interrupt ENABLE or + (+) ald_dma_channel_config(): Control DMA channel ENABLE/DISABLE. + (+) ald_dma_interrupt_config(): Control DMA channel interrupt ENABLE or DISABLE. - (+) dma_get_it_status(): Check whether the specified channel + (+) ald_dma_get_it_status(): Check whether the specified channel interrupt is SET or RESET. - (+) dma_get_flag_status(): Check whether the specified channel + (+) ald_dma_get_flag_status(): Check whether the specified channel flag is SET or RESET. - (+) dma_clear_flag_status(): Clear the specified channel + (+) ald_dma_clear_flag_status(): Clear the specified channel pending flag @endverbatim @@ -604,7 +603,7 @@ void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t siz * @arg DISABLE: Disable the channel * @retval None */ -void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) +void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) { dma_descriptor_t *descr, *alt_descr; @@ -642,7 +641,7 @@ void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) * * @retval None */ -void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) +void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) { assert_param(IS_DMA(DMAx)); assert_param(IS_DMA_IT_TYPE(channel)); @@ -667,7 +666,7 @@ void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) * - SET: Channel interrupt is set * - RESET: Channel interrupt is reset */ -it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) +it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) { assert_param(IS_DMA(DMAx)); assert_param(IS_DMA_IT_TYPE(channel)); @@ -689,7 +688,7 @@ it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) * - SET: Channel flag is set * - RESET: Channel flag is reset */ -flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) +flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) { assert_param(IS_DMA(DMAx)); assert_param(IS_DMA_IT_TYPE(channel)); @@ -708,7 +707,7 @@ flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) * @arg DMA_ERR: DMA bus error * @retval None */ -void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) +void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) { assert_param(IS_DMA(DMAx)); assert_param(IS_DMA_IT_TYPE(channel)); @@ -716,17 +715,6 @@ void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) WRITE_REG(DMAx->ICFR, (1 << channel)); return; } - -/** - * @brief Interrupt callback function. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void dma0_irq_cbk(void) -{ - return; -} /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..b7a3e128c93200e3a8dc5c710403900aefbe5be8 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -0,0 +1,222 @@ +/** + ********************************************************************************* + * + * @file ald_flash.c + * @brief FLASH module driver. + * + * @version V1.0 + * @date 20 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + */ + +#include "ald_flash.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH module driver + * @{ + */ + +#ifdef ALD_FLASH + +#if defined ( __ICCARM__ ) + #define __RAMFUNC __ramfunc +#else + #define __RAMFUNC +#endif + +/** @defgroup Flash_Private_Variables Flash Private Variables + * @{ + */ +/* global variable*/ +static op_cmd_type OP_CMD = OP_FLASH; +/** + * @} + */ + +/** @defgroup Flash_Private_Functions Flash Private Functions + * @brief Flash Private functions + * @{ + */ +/** + * @brief Unlock the flash. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_unlock(void) +{ + uint16_t i; + uint16_t op_cmd = OP_CMD; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + return ERROR; + + FLASH_REG_UNLOCK(); + FLASH_IAP_ENABLE(); + FLASH_REQ(); + + for (i = 0; i < 0xFFFF; i++) + { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) + break; + } + + return i == 0xFFFF ? ERROR : OK; +} + +/** + * @brief Lock the flash. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_lock(void) +{ + uint16_t i; + uint16_t op_cmd = OP_CMD; + + FLASH_REG_UNLOCK(); + WRITE_REG(MSC->FLASHCR, 0x0); + + for (i = 0; i < 0xFFFF; i++) + { + if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) + break; + } + + return i == 0xFFFF ? ERROR : OK; +} + +/** + * @brief Erase one page. + * @param addr: The erased page's address + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC ald_status_t flash_page_erase(uint32_t addr) +{ + uint32_t i; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) + { + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + else + { + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); + + for (i = 0; i < 0xFFFF; i++) + { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) + goto end; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) + goto end; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) + break; + } + + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; +end: + flash_lock(); + return ERROR; +} + +/** + * @brief Programme a word. + * @param addr: The word's address, it is must word align. + * @param data: The 8 bytes data be write. + * @param len: The number of data be write. + * @param fifo: Choose if use fifo. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo) +{ + uint16_t i; + uint16_t prog_len; + uint32_t *p_data = data; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + else + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); + MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); + + for (prog_len = 0; prog_len < len; prog_len++) + { + if (fifo) + { + WRITE_REG(MSC->FLASHFIFO, p_data[0]); + WRITE_REG(MSC->FLASHFIFO, p_data[1]); + } + else + { + WRITE_REG(MSC->FLASHDL, p_data[0]); + WRITE_REG(MSC->FLASHDH, p_data[1]); + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); + } + + p_data += 2; + + for (i = 0; i < 0xFFFF; i++) + { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) + break; + } + } + + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; +end: + flash_lock(); + return ERROR; +} +/** + * @} + */ + +#endif + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c similarity index 60% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c index 0b15ad7ca832e9dff8fe51026ca1d94e9c5a8bd6..87595d3ce9af2c9d59bd519618a354a849c231a2 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c @@ -1,11 +1,11 @@ /** ********************************************************************************* * - * @file ald_flash.c + * @file ald_flash_ext.c * @brief FLASH module driver. * * @version V1.0 - * @date 20 Nov 2017 + * @date 15 May 2019 * @author AE Team * @note * @@ -29,22 +29,23 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) programme flash using flash_write(uint32_t addr, uint8_t *buf, uint16_t len) + (#) programme flash using ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) (++) call the function and supply all the three paraments is needs, addr means the first address to write in this operation, buf is a pointer to the data which - need writing to flash. + need writing to flash. - (#) erase flash using flash_erase(uint32_t addr, uint16_t len) + (#) erase flash using ald_flash_erase(uint32_t addr, uint16_t len) (++) call the function and supply two paraments, addr is the first address to erase, len is the length to erase - (#) read flash using flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) + (#) read flash using ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) (++) read the flash and save to a buffer, ram_addr is the buffer's first address, addr is the start reading address in flash, len is the length need read @endverbatim */ + #include "ald_flash.h" @@ -52,227 +53,25 @@ * @{ */ -/** @defgroup FLASH FLASH - * @brief FLASH module driver +/** @addtogroup FLASH * @{ */ #ifdef ALD_FLASH -/** @addtogroup FLASH_Private_Types +/** @addtogroup Flash_Private_Variables * @{ */ - -/* opration buffer, global variable*/ +/* opration buffer*/ static uint8_t write_buf[FLASH_PAGE_SIZE]; -static op_cmd_type OP_CMD = OP_FLASH; - -#if defined ( __ICCARM__ ) - #define __RAMFUNC __ramfunc -#else - #define __RAMFUNC -#endif - /** * @} */ -/** @defgroup Flash_Private_Functions Flash Private Functions - * @brief Flash Private functions +/** @addtogroup Flash_Private_Functions * @{ */ -/** - * @brief Unlock the flash. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t flash_unlock(void) -{ - uint16_t i; - uint16_t op_cmd = OP_CMD; - - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - return ERROR; - - FLASH_REG_UNLOCK(); - FLASH_IAP_ENABLE(); - FLASH_REQ(); - - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) - break; - } - - return i == 0xFFFF ? ERROR : OK; -} - -/** - * @brief Lock the flash. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t flash_lock(void) -{ - uint16_t i; - uint16_t op_cmd = OP_CMD; - - FLASH_REG_UNLOCK(); - WRITE_REG(MSC->FLASHCR, 0x0); - - for (i = 0; i < 0xFFFF; i++) - { - if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) - break; - } - - return i == 0xFFFF ? ERROR : OK; -} - -/** - * @brief Erase one page. - * @param addr: The erased page's address - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t flash_page_erase(uint32_t addr) -{ - uint32_t i; - uint16_t op_cmd = OP_CMD; - - __disable_irq(); - if (flash_unlock() != OK) - goto end; - - if (op_cmd == OP_FLASH) - { - CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); - } - else - { - SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); - } - - WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); - - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - continue; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) - goto end; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) - goto end; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) - break; - } - - if (i == 0xFFFF) - goto end; - - if (flash_lock() == ERROR) - goto end; - - __enable_irq(); - return OK; -end: - - if (flash_lock() == ERROR) - while (1); - - __enable_irq(); - return ERROR; -} - -/** - * @brief Programme a word. - * @param addr: The word's address, it is must word align. - * @param data: The 8 bytes data be write. - * @param len: The number of data be write. - * @param fifo: Choose if use fifo. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t flash_word_program(uint32_t addr, uint32_t data[], uint32_t len, uint32_t fifo) -{ - uint16_t i; - uint16_t prog_len; - uint32_t *p_data = data; - uint16_t op_cmd = OP_CMD; - - __disable_irq(); - if (flash_unlock() != OK) - goto end; - - if (op_cmd == OP_FLASH) - CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - else - SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); - MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); - - for (prog_len = 0; prog_len < len; prog_len++) - { - if (fifo) - { - WRITE_REG(MSC->FLASHFIFO, p_data[0]); - WRITE_REG(MSC->FLASHFIFO, p_data[1]); - } - else - { - WRITE_REG(MSC->FLASHDL, p_data[0]); - WRITE_REG(MSC->FLASHDH, p_data[1]); - WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); - } - - p_data += 2; - - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - continue; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) - break; - } - } - if (i == 0xFFFF) - goto end; - - if (flash_lock() == ERROR) - goto end; - - __enable_irq(); - return OK; -end: - if (flash_lock() == ERROR) - while (1); - - __enable_irq(); - return ERROR; -} - -/** - * @brief Read data from flash, and store in buffer. - * @param ram_addr: The stored buffer's address. - * @param addr: The start address in flash to read. - * @param len: The length of byte to read. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t __flash_read(uint32_t ram_addr[], uint32_t addr, uint32_t len) -{ - uint32_t i; - - if (!len) - return ERROR; - - for (i = 0; i < len; i++) - { - ram_addr[i] = ((uint32_t *)addr)[i]; - } - - return OK; -} - /** * @brief Check whether the flash between the given address section * have been writen, if it have been writen, return TRUE, else @@ -283,7 +82,7 @@ __RAMFUNC static ald_status_t __flash_read(uint32_t ram_addr[], uint32_t addr, u * - TRUE * - FALSE */ -__RAMFUNC static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) +static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) { uint8_t *addr_to_read; uint8_t value; @@ -310,15 +109,14 @@ __RAMFUNC static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_ return value == 0xFF ? FALSE : TRUE; } - /** * @} */ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions +/** @defgroup Flash_Public_Functions Flash Public Functions * @verbatim =============================================================================== - ##### Flash oprate functions ##### + ##### Flash operation functions ##### =============================================================================== [..] This section provides functions allowing to operate flash, such as read and write. @@ -327,6 +125,35 @@ __RAMFUNC static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_ * @{ */ +/** + * @brief read the specified length bytes from flash, and store to the specified area. + * @param ram_addr: the specified area to store the reading bytes. + * @param addr: the start address. + * @param len: the length to read. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) +{ + uint32_t i; + uint32_t temp; + + assert_param(IS_4BYTES_ALIGN(ram_addr)); + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + temp = (uint32_t)ram_addr; + + if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) + return ERROR; + + for (i = 0; i < len; i++) + { + ram_addr[i] = ((uint32_t *)addr)[i]; + } + + return OK; +} + /** * @brief Write the give bytes to the given address section. * @param addr: The start address to write. @@ -335,7 +162,7 @@ __RAMFUNC static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_ * @retval Status, see @ref ald_status_t. */ -__RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len) +ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) { uint32_t index = 0; uint32_t para = 0; @@ -353,6 +180,8 @@ __RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len) len_to_write = len; + __disable_irq(); + while (len_to_write > 0) { need_erase_page = FALSE; @@ -369,12 +198,18 @@ __RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len) if (need_erase_page) { - if (ERROR == __flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), - FLASH_PAGE_SIZE >> 2)) + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), + FLASH_PAGE_SIZE >> 2)) + { + __enable_irq(); return ERROR; + } if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) + { + __enable_irq(); return ERROR; + } para = end_write_addr & (FLASH_PAGE_SIZE - 1); index = start_write_addr & (FLASH_PAGE_SIZE - 1); @@ -405,11 +240,15 @@ __RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len) } if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) + { + __enable_irq(); return ERROR; + } len_to_write = len_to_write - (end_write_addr - start_write_addr + 1); } + __enable_irq(); return OK; } @@ -419,9 +258,9 @@ __RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len) * @param len: The length to erase. * @retval Status, see @ref ald_status_t. */ -__RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len) +ald_status_t ald_flash_erase(uint32_t addr, uint16_t len) { - int32_t index; + int32_t index; int32_t para; int32_t start_erase_addr; int32_t end_erase_addr; @@ -434,6 +273,8 @@ __RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len) len_not_erase = len; + __disable_irq(); + while (len_not_erase > 0) { page_need_save = FALSE; @@ -448,6 +289,7 @@ __RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len) if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1))) page_need_save = TRUE; } + if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) { if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr))) @@ -456,8 +298,8 @@ __RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len) if (page_need_save) { - if (ERROR == __flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), - FLASH_PAGE_SIZE >> 2)) + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), + FLASH_PAGE_SIZE >> 2)) { __enable_irq(); return ERROR; @@ -480,45 +322,25 @@ __RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len) index = FLASH_PAGE_ADDR(start_erase_addr); len_index = FLASH_PAGE_SIZE; + if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) { __enable_irq(); return ERROR; } } + len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1); } + __enable_irq(); return OK; } - -/** - * @brief read the specified length bytes from flash, and store to the specified area. - * @param ram_addr: the specified area to store the reading bytes. - * @param addr: the start address. - * @param len: the length to read. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC ald_status_t flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) -{ - uint32_t temp; - - assert_param(IS_4BYTES_ALIGN(ram_addr)); - assert_param(IS_FLASH_ADDRESS(addr)); - assert_param(IS_FLASH_ADDRESS(addr + len - 1)); - - temp = (uint32_t)ram_addr; - - if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) - return ERROR; - - return __flash_read(ram_addr, addr, len) == ERROR ? ERROR : OK; -} - /** * @} */ + #endif /** diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c similarity index 91% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c index e1d95dca31ef0da890e22931b7bc5d89234cfb46..17b4464ac161953b72512091f191abb41915731f 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -72,7 +72,7 @@ [..] (#) Enable the GPIO clock. - (#) Configure the GPIO pin(s) using gpio_init(). + (#) Configure the GPIO pin(s) using ald_gpio_init(). (++) Configure the IO mode using "mode" member from gpio_init_t structure (++) Activate Pull-up, Pull-down resistor using "pupd" member from gpio_init_t structure. @@ -87,7 +87,7 @@ (++) Analog mode is required when a pin is to be used as ADC channel or DAC output. - (#) Configure the GPIO pin(s) using gpio_init_default(). + (#) Configure the GPIO pin(s) using ald_gpio_init_default(). (++) Configure GPIO pin using default param: init.mode = GPIO_MODE_OUTPUT; init.odos = GPIO_PUSH_PULL; @@ -98,8 +98,8 @@ init.func = GPIO_FUNC_1; (#) In case of external interrupt/event mode selection, user need invoke - gpio_exti_init() to configure some param. And then invoke - gpio_exti_interrupt_config() to enable/disable external interrupt/event. + ald_gpio_exti_init() to configure some param. And then invoke + ald_gpio_exti_interrupt_config() to enable/disable external interrupt/event. (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using NVIC_SetPriority() and enable it using @@ -108,17 +108,17 @@ (#) To get the level of a pin configured in input mode use GPIO_read_pin(). (#) To set/reset the level of a pin configured in output mode use - gpio_write_pin()/gpio_toggle_pin(). + ald_gpio_write_pin()/ald_gpio_toggle_pin(). - (#) To lock pin configuration until next reset use gpio_lock_pin(). + (#) To lock pin configuration until next reset use ald_gpio_lock_pin(). (#) Configure external interrupt mode and enable/disable using - gpio_exti_interrupt_config(). + ald_gpio_exti_interrupt_config(). - (#) Get external interrupt flag status using gpio_exti_get_flag_status(). + (#) Get external interrupt flag status using ald_gpio_exti_get_flag_status(). (#) Clear pending external interrupt flag status using - gpio_exti_clear_flag_status(). + ald_gpio_exti_clear_flag_status(). @endverbatim */ @@ -166,7 +166,7 @@ * the configuration information for the specified parameters. * @retval None */ -void gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) { uint32_t i, pos, mask, tmp; @@ -247,7 +247,7 @@ void gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) * @param pin: The pin which need to initialize. * @retval None */ -void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) { gpio_init_t init; @@ -260,7 +260,7 @@ void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) init.type = GPIO_TYPE_CMOS; init.func = GPIO_FUNC_1; - gpio_init(GPIOx, pin, &init); + ald_gpio_init(GPIOx, pin, &init); return; } @@ -269,7 +269,7 @@ void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. * @retval None */ -void gpio_func_default(GPIO_TypeDef *GPIOx) +void ald_gpio_func_default(GPIO_TypeDef *GPIOx) { WRITE_REG(GPIOx->FUNC0, 0x00); WRITE_REG(GPIOx->FUNC1, 0x00); @@ -286,7 +286,7 @@ void gpio_func_default(GPIO_TypeDef *GPIOx) * the configuration information for the specified parameters. * @retval None */ -void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) { uint8_t i; uint8_t port; @@ -376,7 +376,7 @@ void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) * - BIT_SET * - BIT_RESET */ -uint8_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { assert_param(IS_GPIO_PORT(GPIOx)); assert_param(IS_GPIO_PIN(pin)); @@ -395,7 +395,7 @@ uint8_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) * @param val: The specifies value to be written. * @retval None */ -void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) { assert_param(IS_GPIO_PORT(GPIOx)); assert_param(IS_GPIO_PIN(pin)); @@ -414,7 +414,7 @@ void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) * @param pin: Specifies the pin to turn over. * @retval None */ -void gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { assert_param(IS_GPIO_PORT(GPIOx)); assert_param(IS_GPIO_PIN(pin)); @@ -429,7 +429,7 @@ void gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) * @param pin: Specifies the pin to turn over. * @retval None */ -void gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) { uint32_t i, pos, mask, tmp, value; @@ -477,7 +477,7 @@ void gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) * @param pin: The specified Pin to be written. * @retval None */ -void gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { assert_param(IS_GPIO_PORT(GPIOx)); assert_param(IS_GPIO_PIN(pin)); @@ -493,7 +493,7 @@ void gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. * @retval The value; */ -uint16_t gpio_read_port(GPIO_TypeDef *GPIOx) +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx) { assert_param(IS_GPIO_PORT(GPIOx)); @@ -506,7 +506,7 @@ uint16_t gpio_read_port(GPIO_TypeDef *GPIOx) * @param val: The specifies value to be written. * @retval None */ -void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) { assert_param(IS_GPIO_PORT(GPIOx)); @@ -543,7 +543,7 @@ void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) * @arg DISABLE * @retval None */ -void gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status) +void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status) { assert_param(IS_GPIO_PIN(pin)); assert_param(IS_TRIGGER_STYLE(style)); @@ -605,7 +605,7 @@ void gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_f * - SET * - RESET */ -flag_status_t gpio_exti_get_flag_status(uint16_t pin) +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin) { assert_param(IS_GPIO_PIN(pin)); @@ -620,7 +620,7 @@ flag_status_t gpio_exti_get_flag_status(uint16_t pin) * @param pin: The pin which belong to external interrupt. * @retval None */ -void gpio_exti_clear_flag_status(uint16_t pin) +void ald_gpio_exti_clear_flag_status(uint16_t pin) { assert_param(IS_GPIO_PIN(pin)); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c similarity index 85% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c index e285872cf23ffc9a842faadcb67ecbd98c9e646d..1e5f32cde1248511f4c36ffcf1eb78c308aaac10 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -24,24 +24,24 @@ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, Dual Addressing mode, Own Address2, General call and Nostretch mode in the hperh init structure. - (#) Initialize the I2C registers by calling the i2c_init(). - (#) To check if target device is ready for communication, use the function i2c_is_device_ready() + (#) Initialize the I2C registers by calling the ald_i2c_init(). + (#) To check if target device is ready for communication, use the function ald_i2c_is_device_ready() (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using i2c_master_send() - (+) Receive in master mode an amount of data in blocking mode using i2c_master_recv() - (+) Transmit in slave mode an amount of data in blocking mode using i2c_slave_send() - (+) Receive in slave mode an amount of data in blocking mode using i2c_slave_recv() + (+) Transmit in master mode an amount of data in blocking mode using ald_i2c_master_send() + (+) Receive in master mode an amount of data in blocking mode using ald_i2c_master_recv() + (+) Transmit in slave mode an amount of data in blocking mode using ald_i2c_slave_send() + (+) Receive in slave mode an amount of data in blocking mode using ald_i2c_slave_recv() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using i2c_mem_write() - (+) Read an amount of data in blocking mode from a specific memory address using i2c_mem_read() + (+) Write an amount of data in blocking mode to a specific memory address using ald_i2c_mem_write() + (+) Read an amount of data in blocking mode from a specific memory address using ald_i2c_mem_read() *** Interrupt mode IO operation *** @@ -49,16 +49,16 @@ [..] (+) The I2C interrupts should have the highest priority in the application in order to make them uninterruptible. - (+) Transmit in master mode an amount of data in non-blocking mode using i2c_master_send_by_it() + (+) Transmit in master mode an amount of data in non-blocking mode using ald_i2c_master_send_by_it() (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->master_tx_cplt_cbk() - (+) Receive in master mode an amount of data in non-blocking mode using i2c_master_recv_by_it() + (+) Receive in master mode an amount of data in non-blocking mode using ald_i2c_master_recv_by_it() (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->master_rx_cplt_cbk() - (+) Transmit in slave mode an amount of data in non-blocking mode using i2c_slave_send_by_it() + (+) Transmit in slave mode an amount of data in non-blocking mode using ald_i2c_slave_send_by_it() (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() - (+) Receive in slave mode an amount of data in non-blocking mode using i2c_slave_recv_by_it() + (+) Receive in slave mode an amount of data in non-blocking mode using ald_i2c_slave_recv_by_it() (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() (+) In case of transfer Error, hperh->error_callback() function is executed and user can @@ -70,11 +70,11 @@ (+) The I2C interrupts should have the highest priority in the application in order to make them uninterruptible. (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - i2c_mem_write_by_it() + ald_i2c_mem_write_by_it() (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - i2c_mem_read_by_it() + ald_i2c_mem_read_by_it() (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() (+) In case of transfer Error, hperh->error_callback() function is executed and user can @@ -84,19 +84,19 @@ ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - i2c_master_send_by_dma() + ald_i2c_master_send_by_dma() (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->master_tx_cplt_cbk() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - i2c_master_recv_by_dma() + ald_i2c_master_recv_by_dma() (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->master_rx_cplt_cbk() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - i2c_slave_send_by_dma() + ald_i2c_slave_send_by_dma() (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - i2c_slave_recv_by_dma() + ald_i2c_slave_recv_by_dma() (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() (+) In case of transfer Error, hperh->error_callback() function is executed and user can @@ -106,11 +106,11 @@ ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - i2c_mem_write_by_dma() + ald_i2c_mem_write_by_dma() (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - i2c_mem_read_by_dma() + ald_i2c_mem_read_by_dma() (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() (+) In case of transfer Error, hperh->error_callback() function is executed and user can @@ -144,7 +144,7 @@ supported by the slave. (##) Data valid time (tVD;DAT) violated without the OVR flag being set: Workaround: If the slave device allows it, use the clock stretching mechanism - by programming no_stretch = I2C_NOSTRETCH_DISABLE in i2c_init. + by programming no_stretch = I2C_NOSTRETCH_DISABLE in ald_i2c_init. @endverbatim ********************************************************************************* @@ -229,7 +229,7 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk); [..] This subsection provides a set of functions allowing to initialize and de-initialiaze the I2Cx peripheral: - (+) Call the function i2c_init() to configure the selected device with + (+) Call the function ald_i2c_init() to configure the selected device with the selected configuration: (++) Communication Speed (++) Duty cycle @@ -240,7 +240,7 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk); (++) General call mode (++) Nostretch mode - (+) Call the function i2c_reset() to restore the default configuration + (+) Call the function ald_i2c_reset() to restore the default configuration of the selected I2Cx periperal. @endverbatim @@ -254,7 +254,7 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk); * the configuration information for the specified I2C. * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_init(i2c_handle_t *hperh) +ald_status_t ald_i2c_init(i2c_handle_t *hperh) { uint32_t freqrange = 0; uint32_t pclk1 = 0; @@ -278,7 +278,7 @@ ald_status_t i2c_init(i2c_handle_t *hperh) hperh->lock = UNLOCK; hperh->state = I2C_STATE_BUSY; - pclk1 = cmu_get_pclk1_clock(); + pclk1 = ald_cmu_get_pclk1_clock(); I2C_DISABLE(hperh); freqrange = I2C_FREQ_RANGE(pclk1); @@ -305,7 +305,7 @@ ald_status_t i2c_init(i2c_handle_t *hperh) * the configuration information for the specified I2C. * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_reset(i2c_handle_t *hperh) +ald_status_t ald_i2c_reset(i2c_handle_t *hperh) { if (hperh == NULL) return ERROR; @@ -349,29 +349,29 @@ ald_status_t i2c_reset(i2c_handle_t *hperh) using DMA mode. (#) Blocking mode functions are : - (++) i2c_master_send() - (++) i2c_master_recv() - (++) i2c_slave_send() - (++) i2c_slave_recv() - (++) i2c_mem_write() - (++) i2c_mem_read() - (++) i2c_is_device_ready() + (++) ald_i2c_master_send() + (++) ald_i2c_master_recv() + (++) ald_i2c_slave_send() + (++) ald_i2c_slave_recv() + (++) ald_i2c_mem_write() + (++) ald_i2c_mem_read() + (++) ald_i2c_is_device_ready() (#) No-Blocking mode functions with Interrupt are : - (++) i2c_master_send_by_it() - (++) i2c_master_recv_by_it() - (++) i2c_slave_send_by_it() - (++) i2c_slave_recv_by_it() - (++) i2c_mem_write_by_it() - (++) i2c_mem_read_by_it() + (++) ald_i2c_master_send_by_it() + (++) ald_i2c_master_recv_by_it() + (++) ald_i2c_slave_send_by_it() + (++) ald_i2c_slave_recv_by_it() + (++) ald_i2c_mem_write_by_it() + (++) ald_i2c_mem_read_by_it() (#) No-Blocking mode functions with DMA are : - (++) i2c_master_send_by_dma() - (++) i2c_master_recv_by_dma() - (++) i2c_slave_send_by_dma() - (++) i2c_slave_recv_by_dma() - (++) i2c_mem_write_by_dma() - (++) i2c_mem_read_by_dma() + (++) ald_i2c_master_send_by_dma() + (++) ald_i2c_master_recv_by_dma() + (++) ald_i2c_slave_send_by_dma() + (++) ald_i2c_slave_recv_by_dma() + (++) ald_i2c_mem_write_by_dma() + (++) ald_i2c_mem_read_by_dma() (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) hperh->mem_tx_cplt_cbk() @@ -396,8 +396,8 @@ ald_status_t i2c_reset(i2c_handle_t *hperh) * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -453,7 +453,7 @@ ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *bu hperh->perh->DATA = (*buf++); --size; - if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { hperh->perh->DATA = (*buf++); --size; @@ -492,8 +492,8 @@ ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *bu * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -568,7 +568,7 @@ ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *bu (*buf++) = hperh->perh->DATA; --size; - if (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { (*buf++) = hperh->perh->DATA; --size; @@ -577,64 +577,64 @@ ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *bu switch (size) { - case 1: - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) + case 1: + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; + if (hperh->error_code == I2C_ERROR_TIMEOUT) + { + __UNLOCK(hperh); + return TIMEOUT; + } + else + { + __UNLOCK(hperh); + return ERROR; + } } - else + + (*buf++) = hperh->perh->DATA; + break; + + case 2: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { __UNLOCK(hperh); - return ERROR; + return TIMEOUT; } - } - - (*buf++) = hperh->perh->DATA; - break; - case 2: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } + __disable_irq(); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; - __disable_irq(); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; + case 3: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } - case 3: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + (*buf++) = hperh->perh->DATA; - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - (*buf++) = hperh->perh->DATA; + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + __enable_irq(); + return TIMEOUT; + } - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; __enable_irq(); - return TIMEOUT; - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; + (*buf++) = hperh->perh->DATA; + break; - default : - break; + default : + break; } hperh->state = I2C_STATE_READY; @@ -652,7 +652,7 @@ ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *bu * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -713,7 +713,7 @@ ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui hperh->perh->DATA = (*buf++); --size; - if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { hperh->perh->DATA = (*buf++); --size; @@ -726,7 +726,7 @@ ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui return TIMEOUT; } - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); hperh->state = I2C_STATE_READY; @@ -744,7 +744,7 @@ ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -794,7 +794,7 @@ ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui (*buf++) = hperh->perh->DATA; --size; - if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { (*buf++) = hperh->perh->DATA; --size; @@ -804,6 +804,7 @@ ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) { CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + if (hperh->error_code == I2C_ERROR_AF) { __UNLOCK(hperh); @@ -833,7 +834,7 @@ ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -877,9 +878,9 @@ ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8 /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -892,7 +893,7 @@ ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8 * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -952,9 +953,9 @@ ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8 /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -966,7 +967,7 @@ ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8 * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -994,9 +995,9 @@ ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t si /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -1009,7 +1010,7 @@ ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t si * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1037,9 +1038,9 @@ ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t si /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -1055,8 +1056,8 @@ ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t si * @param channel: DMA channel as I2C transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint8_t channel) +ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1087,7 +1088,7 @@ ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint hperh->hdmatx.err_cbk = i2c_dma_error; hperh->hdmatx.err_arg = hperh; - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -1097,7 +1098,7 @@ ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; hperh->hdmatx.config.channel = channel; - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { @@ -1129,8 +1130,8 @@ ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint * @param channel: DMA channel as I2C receive * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint8_t channel) +ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1161,7 +1162,7 @@ ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint hperh->hdmarx.err_cbk = i2c_dma_error; hperh->hdmarx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -1171,7 +1172,7 @@ ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; hperh->hdmarx.config.channel = channel; - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { @@ -1207,7 +1208,7 @@ ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint * @param channel: DMA channel as I2C Transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1238,7 +1239,7 @@ ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s hperh->hdmatx.err_cbk = i2c_dma_error; hperh->hdmatx.err_arg = hperh; - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -1248,7 +1249,7 @@ ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; hperh->hdmatx.config.channel = channel; - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); @@ -1290,7 +1291,7 @@ ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s * @param channel: DMA channel as I2C receive * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1321,7 +1322,7 @@ ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s hperh->hdmarx.err_cbk = i2c_dma_error; hperh->hdmarx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -1331,7 +1332,7 @@ ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; hperh->hdmarx.config.channel = channel; - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); @@ -1360,8 +1361,8 @@ ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1416,7 +1417,7 @@ ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_ hperh->perh->DATA = (*buf++); --size; - if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { hperh->perh->DATA = (*buf++); --size; @@ -1441,7 +1442,7 @@ ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_ SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); hperh->state = I2C_STATE_READY; hperh->mode = I2C_MODE_NONE; - __delay_ms(10); + ald_delay_ms(10); __UNLOCK(hperh); return OK; } @@ -1458,8 +1459,8 @@ ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_ * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1535,7 +1536,7 @@ ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_a (*buf++) = hperh->perh->DATA; --size; - if (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { (*buf++) = hperh->perh->DATA; --size; @@ -1544,64 +1545,64 @@ ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_a switch (size) { - case 1: - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) + case 1: + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; + if (hperh->error_code == I2C_ERROR_TIMEOUT) + { + __UNLOCK(hperh); + return TIMEOUT; + } + else + { + __UNLOCK(hperh); + return ERROR; + } } - else + + (*buf++) = hperh->perh->DATA; + break; + + case 2: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { __UNLOCK(hperh); - return ERROR; + return TIMEOUT; } - } - - (*buf++) = hperh->perh->DATA; - break; - case 2: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } + __disable_irq(); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; - __disable_irq(); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; + case 3: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } - case 3: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + (*buf++) = hperh->perh->DATA; - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - (*buf++) = hperh->perh->DATA; + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + __enable_irq(); + return TIMEOUT; + } - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; __enable_irq(); - return TIMEOUT; - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; + (*buf++) = hperh->perh->DATA; + break; - default: - break; + default: + break; } hperh->state = I2C_STATE_READY; @@ -1621,8 +1622,8 @@ ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_a * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1665,9 +1666,9 @@ ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_ /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -1683,8 +1684,8 @@ ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_ * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1745,9 +1746,9 @@ ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -1765,8 +1766,8 @@ ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t * @param channel: DMA channel * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1797,7 +1798,7 @@ ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16 hperh->hdmatx.cplt_arg = hperh; hperh->hdmatx.err_cbk = i2c_dma_error; hperh->hdmatx.err_arg = hperh; - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; @@ -1808,7 +1809,7 @@ ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16 hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; hperh->hdmatx.config.channel = channel; - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { @@ -1841,8 +1842,8 @@ ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16 * @param channel: DMA channel * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1873,7 +1874,7 @@ ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_ hperh->hdmarx.cplt_arg = (void *)hperh; hperh->hdmarx.err_cbk = i2c_dma_error; hperh->hdmarx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; @@ -1884,7 +1885,7 @@ ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_ hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; hperh->hdmarx.config.channel = channel; - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { @@ -1922,7 +1923,7 @@ ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_ * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout) +ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout) { uint32_t tickstart = 0; uint32_t tmp1 = 0; @@ -1955,23 +1956,24 @@ ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_ } hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - tickstart = __get_tick(); - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = i2c_get_flag_status(hperh, I2C_FLAG_AF); + tickstart = ald_get_tick(); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); tmp3 = hperh->state; while ((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != I2C_STATE_TIMEOUT)) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) hperh->state = I2C_STATE_TIMEOUT; - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); tmp3 = hperh->state; } + hperh->state = I2C_STATE_READY; - if (i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) { SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); I2C_CLEAR_ADDRFLAG(hperh); @@ -1990,7 +1992,7 @@ ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_ else { SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) @@ -2036,7 +2038,7 @@ ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_ * @arg DISABLE * @retval None */ -void i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state) +void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state) { assert_param(IS_I2C_TYPE(hperh->perh)); assert_param(IS_I2C_IT_TYPE(it)); @@ -2059,7 +2061,7 @@ void i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t s * - 0: RESET * - 1: SET */ -flag_status_t i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) +flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) { flag_status_t state = RESET; @@ -2089,7 +2091,7 @@ flag_status_t i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) * - 0: RESET * - 1: SET */ -flag_status_t i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) +flag_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) { assert_param(IS_I2C_TYPE(hperh->perh)); assert_param(IS_I2C_IT_TYPE(it)); @@ -2107,7 +2109,7 @@ flag_status_t i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) * This parameter can be one of the @ref uart_flag_t. * @retval None */ -void i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) +void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) { assert_param(IS_I2C_TYPE(hperh->perh)); assert_param(IS_I2C_FLAG(flag)); @@ -2127,7 +2129,7 @@ void i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) * the configuration information for the specified I2C. * @retval ald_status_t state */ -i2c_state_t i2c_get_state(i2c_handle_t *hperh) +i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh) { return hperh->state; } @@ -2138,7 +2140,7 @@ i2c_state_t i2c_get_state(i2c_handle_t *hperh) * the configuration information for the specified I2C. * @retval I2C Error Code */ -uint32_t i2c_get_error(i2c_handle_t *hperh) +uint32_t ald_i2c_get_error(i2c_handle_t *hperh) { return hperh->error_code; } @@ -2156,7 +2158,7 @@ uint32_t i2c_get_error(i2c_handle_t *hperh) * the configuration information for the specified I2C. * @retval None */ -void i2c_ev_irq_handler(i2c_handle_t *hperh) +void ald_i2c_ev_irq_handler(i2c_handle_t *hperh) { uint32_t tmp1 = 0; uint32_t tmp2 = 0; @@ -2165,12 +2167,12 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) { - if (i2c_get_flag_status(hperh, I2C_FLAG_TRA) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_TRA) == SET) { - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_TXE); - tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) i2c_master_send_txe(hperh); @@ -2181,10 +2183,10 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) /* I2C in mode Receiver */ else { - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_RXNE); - tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) i2c_master_recv_rxne(hperh); @@ -2196,10 +2198,10 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) /* Slave mode selected */ else { - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = i2c_get_it_status(hperh, (I2C_IT_EVT)); - tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_STOPF); - tmp4 = i2c_get_flag_status(hperh, I2C_FLAG_TRA); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = ald_i2c_get_it_status(hperh, (I2C_IT_EVT)); + tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF); + tmp4 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TRA); if ((tmp1 == SET) && (tmp2 == SET)) { @@ -2213,10 +2215,10 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) /* I2C in mode Transmitter */ else if (tmp4 == SET) { - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_TXE); - tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) i2c_slave_send_txe(hperh); @@ -2227,10 +2229,10 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) /* I2C in mode Receiver */ else { - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_RXNE); - tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) i2c_slave_recv_rxne(hperh); @@ -2246,35 +2248,35 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) * the configuration information for I2C module * @retval NONE */ -void i2c_er_irq_handler(i2c_handle_t *hperh) +void ald_i2c_er_irq_handler(i2c_handle_t *hperh) { uint32_t tmp1 = 0; uint32_t tmp2 = 0; uint32_t tmp3 = 0; - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_BERR); - tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BERR); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); /* I2C Bus error interrupt occurred */ if ((tmp1 == SET) && (tmp2 == SET)) { hperh->error_code |= I2C_ERROR_BERR; - i2c_clear_flag_status(hperh, I2C_FLAG_BERR); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_BERR); SET_BIT(hperh->perh->CON1, I2C_CON1_SRST); } - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ARLO); - tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ARLO); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); /* I2C Arbitration Loss error interrupt occurred */ if ((tmp1 == SET) && (tmp2 == SET)) { hperh->error_code |= I2C_ERROR_ARLO; - i2c_clear_flag_status(hperh, I2C_FLAG_ARLO); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_ARLO); } - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_AF); - tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); /* I2C Acknowledge failure error interrupt occurred */ if ((tmp1 == SET) && (tmp2 == SET)) @@ -2282,6 +2284,7 @@ void i2c_er_irq_handler(i2c_handle_t *hperh) tmp1 = hperh->mode; tmp2 = hperh->xfer_count; tmp3 = hperh->state; + if ((tmp1 == I2C_MODE_SLAVE) && (tmp2 == 0) && \ (tmp3 == I2C_STATE_BUSY_TX)) { @@ -2291,24 +2294,25 @@ void i2c_er_irq_handler(i2c_handle_t *hperh) { hperh->error_code |= I2C_ERROR_AF; SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); } } - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_OVR); - tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_OVR); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); /* I2C Over-Run/Under-Run interrupt occurred */ if ((tmp1 == SET) && (tmp2 == SET)) { hperh->error_code |= I2C_ERROR_OVR; - i2c_clear_flag_status(hperh, I2C_FLAG_OVR); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_OVR); } if (hperh->error_code != I2C_ERROR_NONE) { hperh->state = I2C_STATE_READY; CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + if (hperh->error_callback) hperh->error_callback(hperh); } @@ -2335,7 +2339,7 @@ static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh) { if (hperh->xfer_count == 0) { - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); } else { @@ -2361,23 +2365,27 @@ static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh) } else { - i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + if (hperh->mode == I2C_MODE_MEM) { hperh->state = I2C_STATE_READY; + if (hperh->mem_tx_cplt_cbk) hperh->mem_tx_cplt_cbk(hperh); } else { hperh->state = I2C_STATE_READY; + if (hperh->master_tx_cplt_cbk) hperh->master_tx_cplt_cbk(hperh); } } + return OK; } @@ -2392,6 +2400,7 @@ static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) uint32_t tmp = 0; tmp = hperh->xfer_count; + if (tmp > 3) { (*hperh->p_buff++) = hperh->perh->DATA; @@ -2399,29 +2408,32 @@ static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) } else if ((tmp == 2) || (tmp == 3)) { - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); } else { - i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); (*hperh->p_buff++) = hperh->perh->DATA; hperh->xfer_count--; if (hperh->mode == I2C_MODE_MEM) { hperh->state = I2C_STATE_READY; + if (hperh->mem_rx_cplt_cbk) hperh->mem_rx_cplt_cbk(hperh); } else { hperh->state = I2C_STATE_READY; + if (hperh->master_rx_cplt_cbk) hperh->master_rx_cplt_cbk(hperh); } } + return OK; } @@ -2441,8 +2453,8 @@ static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) } else if (hperh->xfer_count == 2) { - i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); (*hperh->p_buff++) = hperh->perh->DATA; --hperh->xfer_count; @@ -2453,12 +2465,14 @@ static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) if (hperh->mode == I2C_MODE_MEM) { hperh->state = I2C_STATE_READY; + if (hperh->mem_rx_cplt_cbk) hperh->mem_rx_cplt_cbk(hperh); } else { hperh->state = I2C_STATE_READY; + if (hperh->master_rx_cplt_cbk) hperh->master_rx_cplt_cbk(hperh); } @@ -2468,6 +2482,7 @@ static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) (*hperh->p_buff++) = hperh->perh->DATA; --hperh->xfer_count; } + return OK; } @@ -2484,6 +2499,7 @@ static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) hperh->perh->DATA = (*hperh->p_buff++); --hperh->xfer_count; } + return OK; } @@ -2500,6 +2516,7 @@ static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh) hperh->perh->DATA = (*hperh->p_buff++); --hperh->xfer_count; } + return OK; } @@ -2516,6 +2533,7 @@ static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh) (*hperh->p_buff++) = hperh->perh->DATA; --hperh->xfer_count; } + return OK; } @@ -2532,6 +2550,7 @@ static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh) (*hperh->p_buff++) = hperh->perh->DATA; --hperh->xfer_count; } + return OK; } @@ -2562,9 +2581,9 @@ static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) --hperh->xfer_count; } - i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); __I2C_CLEAR_STOPFLAG(hperh); CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); @@ -2584,10 +2603,10 @@ static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_af(i2c_handle_t *hperh) { - i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); hperh->state = I2C_STATE_READY; @@ -2643,6 +2662,7 @@ static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, else return TIMEOUT; } + return OK; } @@ -2669,6 +2689,7 @@ static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, else { hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) { if (hperh->error_code == I2C_ERROR_AF) @@ -2759,6 +2780,7 @@ static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, ui else { hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { if (hperh->error_code == I2C_ERROR_AF) @@ -2771,6 +2793,7 @@ static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, ui return TIMEOUT; } } + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); } @@ -2840,6 +2863,7 @@ static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uin return TIMEOUT; } } + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); } @@ -2918,7 +2942,7 @@ static void i2c_dma_slave_send_cplt(void *argv) if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != OK) hperh->error_code |= I2C_ERROR_TIMEOUT; - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); @@ -3083,6 +3107,7 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk) if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) { tmp1 = (i2c_clk / (hperh->init.clk_speed << 1)); + if ((tmp1 & I2C_CKCFG_CLKSET) < 4) return 4; else @@ -3139,13 +3164,13 @@ static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t fla { uint32_t tickstart = 0; - tickstart = __get_tick(); + tickstart = ald_get_tick(); if (status == RESET) { - while (i2c_get_flag_status(hperh, flag) == RESET) + while (ald_i2c_get_flag_status(hperh, flag) == RESET) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state = I2C_STATE_READY; __UNLOCK(hperh); @@ -3155,9 +3180,9 @@ static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t fla } else { - while (i2c_get_flag_status(hperh, flag) != RESET) + while (ald_i2c_get_flag_status(hperh, flag) != RESET) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state = I2C_STATE_READY; __UNLOCK(hperh); @@ -3165,6 +3190,7 @@ static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t fla } } } + return OK; } @@ -3180,13 +3206,14 @@ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_fla { uint32_t tickstart = 0; - tickstart = __get_tick(); - while (i2c_get_flag_status(hperh, flag) == RESET) + tickstart = ald_get_tick(); + + while (ald_i2c_get_flag_status(hperh, flag) == RESET) { - if (i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) { SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); hperh->error_code = I2C_ERROR_AF; hperh->state = I2C_STATE_READY; @@ -3196,7 +3223,7 @@ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_fla if (timeout != I2C_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state = I2C_STATE_READY; __UNLOCK(hperh); @@ -3204,6 +3231,7 @@ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_fla } } } + return OK; } @@ -3216,16 +3244,16 @@ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_fla */ static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = __get_tick(); + uint32_t tickstart = ald_get_tick(); - while (i2c_get_flag_status(hperh, I2C_FLAG_TXE) == RESET) + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE) == RESET) { if (i2c_is_ack_failed(hperh) != OK) return ERROR; if (timeout != I2C_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->error_code |= I2C_ERROR_TIMEOUT; hperh->state = I2C_STATE_READY; @@ -3234,6 +3262,7 @@ static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeou } } } + return OK; } @@ -3246,9 +3275,9 @@ static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeou */ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = __get_tick(); + uint32_t tickstart = ald_get_tick(); - while (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == RESET) + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == RESET) { if (i2c_is_ack_failed(hperh) != OK) { @@ -3257,7 +3286,7 @@ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeou if (timeout != I2C_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->error_code |= I2C_ERROR_TIMEOUT; hperh->state = I2C_STATE_READY; @@ -3266,6 +3295,7 @@ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeou } } } + return OK; } @@ -3279,14 +3309,14 @@ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeou static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { uint32_t tickstart = 0x00; - tickstart = __get_tick(); + tickstart = ald_get_tick(); - while (i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == RESET) + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == RESET) { if (i2c_is_ack_failed(hperh) != OK) return ERROR; - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->error_code |= I2C_ERROR_TIMEOUT; hperh->state = I2C_STATE_READY; @@ -3294,6 +3324,7 @@ static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeo return TIMEOUT; } } + return OK; } @@ -3307,20 +3338,20 @@ static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeo static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { uint32_t tickstart = 0x00; - tickstart = __get_tick(); + tickstart = ald_get_tick(); - while (i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == RESET) + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == RESET) { - if (i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET) { - i2c_clear_flag_status(hperh, I2C_FLAG_STOPF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_STOPF); hperh->error_code = I2C_ERROR_NONE; hperh->state = I2C_STATE_READY; __UNLOCK(hperh); return ERROR; } - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->error_code |= I2C_ERROR_TIMEOUT; hperh->state = I2C_STATE_READY; @@ -3328,6 +3359,7 @@ static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeo return TIMEOUT; } } + return OK; } @@ -3339,9 +3371,9 @@ static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeo */ static ald_status_t i2c_is_ack_failed(i2c_handle_t *hperh) { - if (i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) { - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); hperh->error_code = I2C_ERROR_AF; hperh->state = I2C_STATE_READY; __UNLOCK(hperh); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c similarity index 92% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c index 842e40938f624201d9a3f11dd7602f4042c4e6de..81b933d6c78acd5a98fc6d6f5a7369c7540c3250 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -49,7 +49,7 @@ * - 0: SUCCESS * - 1: ERROR */ -uint32_t iap_erase_page(uint32_t addr) +uint32_t ald_iap_erase_page(uint32_t addr) { uint32_t status; IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR); @@ -70,7 +70,7 @@ uint32_t iap_erase_page(uint32_t addr) * - 0: SUCCESS * - 1: ERROR */ -uint32_t iap_program_word(uint32_t addr, uint32_t data) +uint32_t ald_iap_program_word(uint32_t addr, uint32_t data) { uint32_t status; IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR); @@ -95,7 +95,7 @@ uint32_t iap_program_word(uint32_t addr, uint32_t data) * - 0: SUCCESS * - 1: ERROR */ -uint32_t iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) +uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) { uint32_t status; IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR); @@ -122,7 +122,7 @@ uint32_t iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) * - 0: SUCCESS * - 1: ERROR */ -uint32_t iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) +uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) { uint32_t status; IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c similarity index 58% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c index f15053cd6d8d90bba44fe3f961edeb32cc087031..0966ea26a28a0794cb8a096e00b92e8ac9dd8cd7 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -42,7 +42,7 @@ * the configuration information for the specified PIS module. * @retval Status, see @ref ald_status_t. */ -ald_status_t pis_create(pis_handle_t *hperh) +ald_status_t ald_pis_create(pis_handle_t *hperh) { pis_divide_t temp; uint8_t clock_menu = 0; @@ -81,32 +81,39 @@ ald_status_t pis_create(pis_handle_t *hperh) /* configure sync clock, judging by producer clock with consumer clock */ switch (clock_menu) { - case 0x00: - case 0x11: - case 0x22: - case 0x33: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x01: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x02: - case 0x12: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x21: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x30: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x31: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x32: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS); - default: - break; + case 0x00: + case 0x11: + case 0x22: + case 0x33: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x01: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x02: + case 0x12: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x21: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x30: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x31: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x32: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS); + + default: + break; } MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS); @@ -116,14 +123,16 @@ ald_status_t pis_create(pis_handle_t *hperh) /* enable consumer bit, switch pin of consumer */ switch (hperh->consumer_con) { - case PIS_CON_0: - PIS->TAR_CON0 |= hperh->consumer_pos; - break; - case PIS_CON_1: - PIS->TAR_CON1 |= hperh->consumer_pos; - break; - default: - break; + case PIS_CON_0: + PIS->TAR_CON0 |= hperh->consumer_pos; + break; + + case PIS_CON_1: + PIS->TAR_CON1 |= hperh->consumer_pos; + break; + + default: + break; } __UNLOCK(hperh); @@ -137,7 +146,7 @@ ald_status_t pis_create(pis_handle_t *hperh) * the configuration information for the specified PIS module. * @retval Status, see @ref ald_status_t. */ -ald_status_t pis_destroy(pis_handle_t *hperh) +ald_status_t ald_pis_destroy(pis_handle_t *hperh) { assert_param(IS_PIS(hperh->perh)); @@ -151,14 +160,16 @@ ald_status_t pis_destroy(pis_handle_t *hperh) switch (hperh->consumer_con) { - case PIS_CON_0: - PIS->TAR_CON0 &= ~(hperh->consumer_pos); - break; - case PIS_CON_1: - PIS->TAR_CON1 &= ~(hperh->consumer_pos); - break; - default: - break; + case PIS_CON_0: + PIS->TAR_CON0 &= ~(hperh->consumer_pos); + break; + + case PIS_CON_1: + PIS->TAR_CON1 &= ~(hperh->consumer_pos); + break; + + default: + break; } hperh->state = PIS_STATE_RESET; @@ -180,14 +191,14 @@ ald_status_t pis_destroy(pis_handle_t *hperh) * @param hperh: Pointer to a pis_handle_t structure that contains * the configuration information for the specified PIS module. * @param ch: The PIS channel enable output - * This parameter can be one of the following values: - * @arg PIS_OUT_CH_0 - * @arg PIS_OUT_CH_1 - * @arg PIS_OUT_CH_2 - * @arg PIS_OUT_CH_3 + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 * @retval Status, see @ref ald_status_t. */ -ald_status_t pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) +ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) { assert_param(IS_PIS(hperh->perh)); assert_param(IS_PIS_OUPUT_CH(ch)); @@ -203,14 +214,14 @@ ald_status_t pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) * @param hperh: Pointer to a pis_handle_t structure that contains * the configuration information for the specified PIS module. * @param ch: The PIS channel disable output - * This parameter can be one of the following values: - * @arg PIS_OUT_CH_0 - * @arg PIS_OUT_CH_1 - * @arg PIS_OUT_CH_2 - * @arg PIS_OUT_CH_3 + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 * @retval Status, see @ref ald_status_t. */ -ald_status_t pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) +ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) { assert_param(IS_PIS(hperh->perh)); assert_param(IS_PIS_OUPUT_CH(ch)); @@ -235,7 +246,7 @@ ald_status_t pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) * the configuration information for the specified PIS module. * @retval ALD state */ -pis_state_t pis_get_state(pis_handle_t *hperh) +pis_state_t ald_pis_get_state(pis_handle_t *hperh) { assert_param(IS_PIS(hperh->perh)); return hperh->state; @@ -259,7 +270,7 @@ pis_state_t pis_get_state(pis_handle_t *hperh) * LPUART0) how to modulate the target output signal. * @retval Status, see @ref ald_status_t. */ -ald_status_t pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) +ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) { assert_param(IS_PIS(hperh->perh)); assert_param(IS_PIS_MODU_TARGET(config->target)); @@ -270,38 +281,38 @@ ald_status_t pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) switch (config->target) { - case PIS_UART0_TX: - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART1_TX: - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART2_TX: - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART3_TX: - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_LPUART0_TX: - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - default: - break; + case PIS_UART0_TX: + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART1_TX: + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART2_TX: + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART3_TX: + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_LPUART0_TX: + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + default: + break; } __UNLOCK(hperh); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c similarity index 75% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c index f959aa300143c6fd108515fcbec6e2a25f0d1ac3..0c488304a17925b8c25566eb42dcc9fc240126eb 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -37,13 +37,12 @@ * @brief PMU module interrupt handler * @retval None */ -void LVD_Handler(void) +void ald_lvd_irq_handler(void) { SYSCFG_UNLOCK(); SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); SYSCFG_LOCK(); - lvd_irq_cbk(); return; } /** @@ -64,7 +63,6 @@ void LVD_Handler(void) [..] This section provides functions allowing to: (+) Enter stop1 mode. (+) Enter stop2 mode. - (+) Enter standby mode. (+) Get wakeup status. (+) Clear wakeup status. @@ -76,7 +74,7 @@ void LVD_Handler(void) * @brief Enter stop1 mode * @retval None */ -void pmu_stop1_enter(void) +void ald_pmu_stop1_enter(void) { SYSCFG_UNLOCK(); MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS); @@ -94,9 +92,10 @@ void pmu_stop1_enter(void) * @brief Enter stop2 mode * @retval None */ -void pmu_stop2_enter(void) +void ald_pmu_stop2_enter(void) { SYSCFG_UNLOCK(); + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS); SYSCFG_LOCK(); @@ -105,38 +104,6 @@ void pmu_stop2_enter(void) __WFI(); SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - return; - -} - -/** - * @brief Enter standby mode - * @param port: The port whick wake up the standby mode. - * @retval None - */ -void pmu_standby_enter(pmu_standby_wakeup_sel_t port) -{ - assert_param(IS_PMU_STANDBY_PORT_SEL(port)); - - if (port != PMU_STANDBY_PORT_NONE) - { - BKPC_UNLOCK(); - MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS); - SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); - BKPC_LOCK(); - - SYSCFG_UNLOCK(); - MODIFY_REG(PMU->CR, PMU_CR_WKPS_MSK, port << PMU_CR_WKPS_POSS); - SET_BIT(PMU->CR, PMU_CR_WKPEN_MSK); - MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STANDBY << PMU_CR_LPM_POSS); - SYSCFG_LOCK(); - } - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - return; } @@ -145,7 +112,7 @@ void pmu_standby_enter(pmu_standby_wakeup_sel_t port) * @param sr: Status bit. * @retval Status. */ -flag_status_t pmu_get_status(pmu_status_t sr) +flag_status_t ald_pmu_get_status(pmu_status_t sr) { assert_param(IS_PMU_STATUS(sr)); @@ -160,7 +127,7 @@ flag_status_t pmu_get_status(pmu_status_t sr) * @param sr: Status bit. * @retval None */ -void pmu_clear_status(pmu_status_t sr) +void ald_pmu_clear_status(pmu_status_t sr) { assert_param(IS_PMU_STATUS(sr)); SYSCFG_UNLOCK(); @@ -201,7 +168,7 @@ void pmu_clear_status(pmu_status_t sr) * @param state: New state, ENABLE/DISABLE; * @retval None */ -void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state) +void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state) { assert_param(IS_FUNC_STATE(state)); SYSCFG_UNLOCK(); @@ -228,17 +195,6 @@ void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type SYSCFG_LOCK(); return; } - -/** - * @brief Interrupt callback function. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void lvd_irq_cbk(void) -{ - return; -} /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c similarity index 78% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c index 5b8efcad02ae03ccc754c98f289e1a43b6d971bf..b896bcf104e7325a1d30f190a0669391a39c40dd 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -38,7 +38,7 @@ * @param state: The new status: ENABLE/DISABLE. * @retval None */ -void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) +void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) { assert_param(IS_FUNC_STATE(state)); @@ -67,7 +67,7 @@ void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) * @param state: Speicifies the type of the reset, * @retval The status: SET/RESET. */ -flag_status_t rmu_get_reset_status(rmu_state_t state) +flag_status_t ald_rmu_get_reset_status(rmu_state_t state) { assert_param(IS_RMU_STATE(state)); @@ -82,7 +82,7 @@ flag_status_t rmu_get_reset_status(rmu_state_t state) * @param state: Specifies the type of the reset, * @retval None */ -void rmu_clear_reset_status(rmu_state_t state) +void ald_rmu_clear_reset_status(rmu_state_t state) { assert_param(IS_RMU_STATE_CLEAR(state)); @@ -97,7 +97,7 @@ void rmu_clear_reset_status(rmu_state_t state) * @param perh: The peripheral device, * @retval None */ -void rmu_reset_periperal(rmu_peripheral_t perh) +void ald_rmu_reset_periperal(rmu_peripheral_t perh) { uint32_t idx, pos; @@ -109,24 +109,24 @@ void rmu_reset_periperal(rmu_peripheral_t perh) switch (idx) { - case 0: - WRITE_REG(RMU->AHB1RSTR, pos); - break; + case 0: + WRITE_REG(RMU->AHB1RSTR, pos); + break; - case 1: - WRITE_REG(RMU->AHB2RSTR, pos); - break; + case 1: + WRITE_REG(RMU->AHB2RSTR, pos); + break; - case 2: - WRITE_REG(RMU->APB1RSTR, pos); - break; + case 2: + WRITE_REG(RMU->APB1RSTR, pos); + break; - case 4: - WRITE_REG(RMU->APB2RSTR, pos); - break; + case 4: + WRITE_REG(RMU->APB2RSTR, pos); + break; - default: - break; + default: + break; } SYSCFG_LOCK(); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c similarity index 84% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c index 913a095bd2b065148ff53917b7642553dfcfde09..c8294d3ab7d4472daa7ab7e6949501d4757ed4a1 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -27,48 +27,48 @@ (+) Enable the RTC controller interface clock. (+) Select the RTC source clock(default LOSC). (+) Configure the RTC asynchronous prescaler, synchronous prescaler and hour - format using the rtc_init() function. + format using the ald_rtc_init() function. *** Time and date operation *** ================================= [..] - (+) To configure the time use the rtc_set_time() function. - (+) To configure the date use the rtc_set_date() function. - (+) To read the time use the rtc_get_time() function. - (+) To read the date use the rtc_get_date() function. + (+) To configure the time use the ald_rtc_set_time() function. + (+) To configure the date use the ald_rtc_set_date() function. + (+) To read the time use the ald_rtc_get_time() function. + (+) To read the date use the ald_rtc_get_date() function. *** Alarm operation *** =================================== [..] - (+) To configure the alarm use rtc_set_alarm() function - (+) To read the alarm use rtc_get_alarm() function - (+) To cancel the alarm use rtc_alarm_cmd() function + (+) To configure the alarm use ald_rtc_set_alarm() function + (+) To read the alarm use ald_rtc_get_alarm() function + (+) To cancel the alarm use ald_rtc_alarm_cmd() function *** Time stamp operation *** =================================== [..] - (+) To configure the time stamp use rtc_set_time_stamp() function - (+) To read the time stamp use rtc_get_time_stamp() function - (+) To cancel the time stamp use rtc_cancel_time_stamp() function + (+) To configure the time stamp use ald_rtc_set_time_stamp() function + (+) To read the time stamp use ald_rtc_get_time_stamp() function + (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function *** Tamper operation *** =================================== [..] - (+) To configure the tamper use rtc_set_tamper() function - (+) To cancel the tamper use rtc_alarm_cmd() function + (+) To configure the tamper use ald_rtc_set_tamper() function + (+) To cancel the tamper use ald_rtc_alarm_cmd() function *** Wake-up operation *** =================================== [..] - (+) To configure the wake-up parameters use rtc_set_wakeup() function - (+) To read the re-load register value use rtc_get_wakeup_timer_value() function - (+) To cancel the wake-up use rtc_cancel_wakeup() function + (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function + (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function + (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function *** Output clock operation *** =================================== [..] - (+) To configure the clock output type use rtc_set_clock_output() function - (+) To cancel the clock output use rtc_cancel_clock_output() function + (+) To configure the clock output type use ald_rtc_set_clock_output() function + (+) To cancel the clock output use ald_rtc_cancel_clock_output() function *** Control functions *** =================================== @@ -118,7 +118,7 @@ #include "ald_rtc.h" #include "ald_bkpc.h" -#include "ald_temp.h" +#include "ald_tsense.h" #include "ald_syscfg.h" @@ -170,14 +170,19 @@ static int32_t rtc_consistency_check(rtc_time_t *t_last, { if (t_last->second != time->second) return 0; + if (t_last->minute != time->minute) return 0; + if (t_last->hour != time->hour) return 0; + if (d_last->day != date->day) return 0; + if (d_last->month != date->month) return 0; + if (d_last->year != date->year) return 0; @@ -217,7 +222,7 @@ static int32_t rtc_consistency_check(rtc_time_t *t_last, * @brief Reset RTC register. * @retval None */ -void rtc_reset(void) +void ald_rtc_reset(void) { RTC_UNLOCK(); @@ -237,13 +242,13 @@ void rtc_reset(void) * the configuration parameters. * @retval None */ -void rtc_init(rtc_init_t *init) +void ald_rtc_init(rtc_init_t *init) { assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); assert_param(IS_RTC_OUTPUT_SEL(init->output)); assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); - rtc_reset(); + ald_rtc_reset(); RTC_UNLOCK(); MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); @@ -262,7 +267,7 @@ void rtc_init(rtc_init_t *init) * @param sel: RTC source type. * @retval None */ -void rtc_source_selcet(rtc_source_sel_t sel) +void ald_rtc_source_select(rtc_source_sel_t sel) { assert_param(IS_RTC_SOURCE_SEL(sel)); @@ -299,10 +304,10 @@ void rtc_source_selcet(rtc_source_sel_t sel) [..] This section provides functions allowing: [#] - (+) To configure the time use the rtc_set_time() function. - (+) To configure the date use the rtc_set_date() function. - (+) To read the time use the rtc_get_time() function. - (+) To read the date use the rtc_get_date() function. + (+) To configure the time use the ald_rtc_set_time() function. + (+) To configure the date use the ald_rtc_set_date() function. + (+) To read the time use the ald_rtc_get_time() function. + (+) To read the date use the ald_rtc_get_date() function. @endverbatim * @{ @@ -314,7 +319,7 @@ void rtc_source_selcet(rtc_source_sel_t sel) * @param format: Data format. * @retval ALD status. */ -ald_status_t rtc_set_time(rtc_time_t *time, rtc_format_t format) +ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) { uint32_t tmp; @@ -344,11 +349,11 @@ ald_status_t rtc_set_time(rtc_time_t *time, rtc_format_t format) WRITE_REG(RTC->SSEC, time->sub_sec); RTC_LOCK(); - tmp = __get_tick(); + tmp = ald_get_tick(); while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { - if ((__get_tick() - tmp) > RTC_TIMEOUT_VALUE) + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) return TIMEOUT; } @@ -361,7 +366,7 @@ ald_status_t rtc_set_time(rtc_time_t *time, rtc_format_t format) * @param format: Data format. * @retval ALD status. */ -ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format) +ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format) { uint32_t tmp; @@ -392,11 +397,11 @@ ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format) WRITE_REG(RTC->DATE, tmp); RTC_LOCK(); - tmp = __get_tick(); + tmp = ald_get_tick(); while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { - if ((__get_tick() - tmp) > RTC_TIMEOUT_VALUE) + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) return TIMEOUT; } @@ -409,7 +414,7 @@ ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format) * @param format: Data format. * @retval None */ -void rtc_get_time(rtc_time_t *time, rtc_format_t format) +void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format) { uint32_t tmp; @@ -441,7 +446,7 @@ void rtc_get_time(rtc_time_t *time, rtc_format_t format) * @param format: Data format. * @retval None */ -void rtc_get_date(rtc_date_t *date, rtc_format_t format) +void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format) { uint32_t tmp = RTC->DATE; @@ -475,7 +480,7 @@ void rtc_get_date(rtc_date_t *date, rtc_format_t format) * 0 - Consistency * -1 - Not consistency */ -int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format) +int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format) { int32_t nr = 3; rtc_date_t d_last; @@ -483,10 +488,10 @@ int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t forma while (nr--) { - rtc_get_time(&t_last, format); - rtc_get_date(&d_last, format); - rtc_get_time(time, format); - rtc_get_date(date, format); + ald_rtc_get_time(&t_last, format); + ald_rtc_get_date(&d_last, format); + ald_rtc_get_time(time, format); + ald_rtc_get_date(date, format); if (rtc_consistency_check(&t_last, &d_last, time, date)) return 0; @@ -508,8 +513,8 @@ int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t forma [..] This section provides functions allowing: [#] - (+) To configure the alarm use rtc_set_alarm() function - (+) To read the alarm use rtc_get_alarm() function + (+) To configure the alarm use ald_rtc_set_alarm() function + (+) To read the alarm use ald_rtc_get_alarm() function @endverbatim * @{ @@ -521,7 +526,7 @@ int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t forma * @param format: Data format. * @retval None */ -void rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) +void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) { unsigned int tmp, ss_tmp; @@ -607,7 +612,7 @@ void rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) * @param format: Data format. * @retval None */ -void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) +void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) { uint8_t week; uint32_t tmp, ss_tmp; @@ -633,29 +638,36 @@ void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) switch (week) { - case 1: - alarm->week = 0; - break; - case 2: - alarm->week = 1; - break; - case 4: - alarm->week = 2; - break; - case 8: - alarm->week = 3; - break; - case 16: - alarm->week = 4; - break; - case 32: - alarm->week = 5; - break; - case 64: - alarm->week = 6; - break; - default: - break; + case 1: + alarm->week = 0; + break; + + case 2: + alarm->week = 1; + break; + + case 4: + alarm->week = 2; + break; + + case 8: + alarm->week = 3; + break; + + case 16: + alarm->week = 4; + break; + + case 32: + alarm->week = 5; + break; + + case 64: + alarm->week = 6; + break; + + default: + break; } } else @@ -701,9 +713,9 @@ void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) [..] This section provides functions allowing: [#] - (+) To configure the time stamp use rtc_set_time_stamp() function - (+) To read the time stamp use rtc_get_time_stamp() function - (+) To cancel the time stamp use rtc_cancel_time_stamp() function + (+) To configure the time stamp use ald_rtc_set_time_stamp() function + (+) To read the time stamp use ald_rtc_get_time_stamp() function + (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function @endverbatim * @{ @@ -719,7 +731,7 @@ void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) * @arg RTC_TS_FALLING_EDGE * @retval None */ -void rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) +void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) { assert_param(IS_RTC_TS_SIGNAL(sel)); assert_param(IS_RTC_TS_STYLE(style)); @@ -739,7 +751,7 @@ void rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) * @brief Cancel time stamp. * @retval None */ -void rtc_cancel_time_stamp(void) +void ald_rtc_cancel_time_stamp(void) { RTC_UNLOCK(); CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); @@ -755,7 +767,7 @@ void rtc_cancel_time_stamp(void) * @param format: Data format. * @retval None */ -void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format) +void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format) { uint32_t tmp0, tmp1; @@ -804,8 +816,8 @@ void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t f [..] This section provides functions allowing: [#] - (+) To configure the tamper use rtc_set_tamper() function - (+) To cancel the tamper use rtc_alarm_cmd() function + (+) To configure the tamper use ald_rtc_set_tamper() function + (+) To cancel the tamper use ald_rtc_alarm_cmd() function @endverbatim * @{ @@ -815,7 +827,7 @@ void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t f * @param tamper: pointer to rtc_tamper_t structure. * @retval None */ -void rtc_set_tamper(rtc_tamper_t *tamper) +void ald_rtc_set_tamper(rtc_tamper_t *tamper) { assert_param(IS_RTC_TAMPER(tamper->idx)); assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig)); @@ -850,7 +862,7 @@ void rtc_set_tamper(rtc_tamper_t *tamper) * @arg RTC_TAMPER_1 * @retval None */ -void rtc_cancel_tamper(rtc_tamper_idx_t idx) +void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx) { assert_param(IS_RTC_TAMPER(idx)); @@ -878,9 +890,9 @@ void rtc_cancel_tamper(rtc_tamper_idx_t idx) [..] This section provides functions allowing: [#] - (+) To configure the wake-up parameters use rtc_set_wakeup() function - (+) To read the re-load register value use rtc_get_wakeup_timer_value() function - (+) To cancel the wake-up use rtc_cancel_wakeup() function + (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function + (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function + (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function @endverbatim * @{ @@ -891,7 +903,7 @@ void rtc_cancel_tamper(rtc_tamper_idx_t idx) * @param value: re-load value. * @retval None */ -void rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) +void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) { assert_param(IS_RTC_WAKEUP_CLOCK(clock)); @@ -908,7 +920,7 @@ void rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) * @brief Cancel wake-up. * @retval None */ -void rtc_cancel_wakeup(void) +void ald_rtc_cancel_wakeup(void) { RTC_UNLOCK(); CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK); @@ -921,7 +933,7 @@ void rtc_cancel_wakeup(void) * @brief Get wake-up re-load register value. * @retval Value of re-load register. */ -uint16_t rtc_get_wakeup_timer_value(void) +uint16_t ald_rtc_get_wakeup_timer_value(void) { return RTC->WUMAT & 0xFFFF; } @@ -939,8 +951,8 @@ uint16_t rtc_get_wakeup_timer_value(void) [..] This section provides functions allowing: [#] - (+) To configure the clock output type use rtc_set_clock_output() function - (+) To cancel the clock output use rtc_cancel_clock_output() function + (+) To configure the clock output type use ald_rtc_set_clock_output() function + (+) To cancel the clock output use ald_rtc_cancel_clock_output() function @endverbatim * @{ @@ -950,7 +962,7 @@ uint16_t rtc_get_wakeup_timer_value(void) * @param clock: pointer to rtc_clock_output_t structure. * @retval ALD status. */ -ald_status_t rtc_set_clock_output(rtc_clock_output_t clock) +ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock) { uint32_t cnt = 4000; assert_param(IS_RTC_CLOCK_OUTPUT(clock)); @@ -960,8 +972,11 @@ ald_status_t rtc_set_clock_output(rtc_clock_output_t clock) if (clock == RTC_CLOCK_OUTPUT_EXA_1) { SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt)); } else @@ -982,7 +997,7 @@ ald_status_t rtc_set_clock_output(rtc_clock_output_t clock) * @brief Cancel clock output. * @retval None */ -void rtc_cancel_clock_output(void) +void ald_rtc_cancel_clock_output(void) { RTC_UNLOCK(); CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK); @@ -1025,7 +1040,7 @@ void rtc_cancel_clock_output(void) * @arg DISABLE * @retval None */ -void rtc_interrupt_config(rtc_it_t it, type_func_t state) +void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state) { assert_param(IS_RTC_IT(it)); assert_param(IS_FUNC_STATE(state)); @@ -1051,7 +1066,7 @@ void rtc_interrupt_config(rtc_it_t it, type_func_t state) * @arg DISABLE * @retval None */ -void rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) +void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) { assert_param(IS_RTC_ALARM(idx)); assert_param(IS_FUNC_STATE(state)); @@ -1073,7 +1088,7 @@ void rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) * @param sub_ss: value of sub-sconde. * @retval ALD status. */ -ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) +ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) { uint32_t tick; @@ -1085,11 +1100,11 @@ ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); RTC_LOCK(); - tick = __get_tick(); + tick = ald_get_tick(); while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) { - if ((__get_tick() - tick) > RTC_TIMEOUT_VALUE) + if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE) return TIMEOUT; } @@ -1101,7 +1116,7 @@ ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) * @param config: pointer to rtc_cali_t structure. * @retval None */ -void rtc_set_cali(rtc_cali_t *config) +void ald_rtc_set_cali(rtc_cali_t *config) { assert_param(IS_RTC_CALI_FREQ(config->cali_freq)); assert_param(IS_RTC_CALI_TC(config->tc)); @@ -1129,7 +1144,7 @@ void rtc_set_cali(rtc_cali_t *config) * @brief Cancel calibration * @retval None */ -void rtc_cancel_cali(void) +void ald_rtc_cancel_cali(void) { RTC_CALI_UNLOCK(); CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); @@ -1142,7 +1157,7 @@ void rtc_cancel_cali(void) * @brief Get calibration status. * @retval ALD status. */ -ald_status_t rtc_get_cali_status(void) +ald_status_t ald_rtc_get_cali_status(void) { if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK)) return ERROR; @@ -1155,7 +1170,7 @@ ald_status_t rtc_get_cali_status(void) * @param temp: the value of temperature. * @retval None */ -void rtc_write_temp(uint16_t temp) +void ald_rtc_write_temp(uint16_t temp) { RTC_CALI_UNLOCK(); MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS); @@ -1172,7 +1187,7 @@ void rtc_write_temp(uint16_t temp) * - 0: RESET * - 1: SET */ -it_status_t rtc_get_it_status(rtc_it_t it) +it_status_t ald_rtc_get_it_status(rtc_it_t it) { assert_param(IS_RTC_IT(it)); @@ -1190,7 +1205,7 @@ it_status_t rtc_get_it_status(rtc_it_t it) * - 0: RESET * - 1: SET */ -flag_status_t rtc_get_flag_status(rtc_flag_t flag) +flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag) { assert_param(IS_RTC_IF(flag)); @@ -1204,7 +1219,7 @@ flag_status_t rtc_get_flag_status(rtc_flag_t flag) * @param flag: specifies the flag to check. * @retval None. */ -void rtc_clear_flag_status(rtc_flag_t flag) +void ald_rtc_clear_flag_status(rtc_flag_t flag) { assert_param(IS_RTC_IF(flag)); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c similarity index 83% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c index 79f2af9ac702c03a43db332593e04d64eb6143dd..e7d1f466223fe4b7e4cbd7414e8d89912ede3827 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c @@ -29,12 +29,12 @@ (##) SMARTCARD pins configuration: (+++) Enable the clock for the SMARTCARD GPIOs. (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). - (##) NVIC configuration if you need to use interrupt process (smartcard_send_by_it() - and smartcard_recv_by_it() APIs): + (##) NVIC configuration if you need to use interrupt process (ald_smartcard_send_by_it() + and ald_smartcard_recv_by_it() APIs): (+++) Configure the USARTx interrupt priority. (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (smartcard_send_by_dma() - and smartcard_recv_by_dma() APIs): + (##) DMA Configuration if you need to use DMA process (ald_smartcard_send_by_dma() + and ald_smartcard_recv_by_dma() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. (+++) Enable the DMAx interface clock. (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. @@ -47,23 +47,23 @@ (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure. - (#) Initialize the SMARTCARD registers by calling the smartcard_init() API. + (#) Initialize the SMARTCARD registers by calling the ald_smartcard_init() API. (#) Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Send an amount of data in blocking mode using smartcard_send() - (+) Receive an amount of data in blocking mode using smartcard_recv() + (+) Send an amount of data in blocking mode using ald_smartcard_send() + (+) Receive an amount of data in blocking mode using ald_smartcard_recv() *** Interrupt mode IO operation *** =================================== [..] - (+) Send an amount of data in non blocking mode using smartcard_send_by_it() + (+) Send an amount of data in non blocking mode using ald_smartcard_send_by_it() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode using smartcard_recv_by_it() + (+) Receive an amount of data in non blocking mode using ald_smartcard_recv_by_it() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk() function is executed and user can @@ -72,10 +72,10 @@ *** DMA mode IO operation *** ============================== [..] - (+) Send an amount of data in non blocking mode (DMA) using smartcard_send_by_dma() + (+) Send an amount of data in non blocking mode (DMA) using ald_smartcard_send_by_dma() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using smartcard_recv_by_dma() + (+) Receive an amount of data in non blocking mode (DMA) using ald_smartcard_recv_by_dma() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can @@ -180,7 +180,7 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t to use 1.5 stop bits for both transmitting and receiving to avoid switching between the two configurations. [..] - The smartcard_init() function follows the USART SmartCard configuration procedure. + The ald_smartcard_init() function follows the USART SmartCard configuration procedure. @endverbatim * @{ @@ -202,7 +202,7 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t * the configuration information for the specified SMARTCARD module. * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_init(smartcard_handle_t *hperh) +ald_status_t ald_smartcard_init(smartcard_handle_t *hperh) { assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); @@ -239,7 +239,7 @@ ald_status_t smartcard_init(smartcard_handle_t *hperh) * the configuration information for the specified SMARTCARD module. * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_reset(smartcard_handle_t *hperh) +ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); @@ -295,17 +295,17 @@ ald_status_t smartcard_reset(smartcard_handle_t *hperh) error is detected. (#) Blocking mode APIs are : - (++) smartcard_send() - (++) smartcard_recv() + (++) ald_smartcard_send() + (++) ald_smartcard_recv() (#) Non Blocking mode APIs with Interrupt are : - (++) smartcard_send_by_it() - (++) smartcard_recv_by_it() - (++) smartcard_irq_handle() + (++) ald_smartcard_send_by_it() + (++) ald_smartcard_recv_by_it() + (++) ald_smartcard_irq_handler() (#) Non Blocking mode functions with DMA are : - (++) smartcard_send_by_dma() - (++) smartcard_recv_by_dma() + (++) ald_smartcard_send_by_dma() + (++) ald_smartcard_recv_by_dma() * @endverbatim * @{ @@ -320,10 +320,11 @@ ald_status_t smartcard_reset(smartcard_handle_t *hperh) * @param timeout: Specify timeout value * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -368,10 +369,11 @@ ald_status_t smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t si * @param timeout: Specify timeout value * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -408,10 +410,11 @@ ald_status_t smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t si * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -424,8 +427,8 @@ ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint1 hperh->err_code = SMARTCARD_ERROR_NONE; __UNLOCK(hperh); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE); return OK; } @@ -438,10 +441,11 @@ ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint1 * @param size: Amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -454,9 +458,9 @@ ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint1 hperh->err_code = SMARTCARD_ERROR_NONE; __UNLOCK(hperh); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); return OK; } @@ -471,10 +475,11 @@ ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint1 * @param channel: DMA channel as USART transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -494,7 +499,7 @@ ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint hperh->hdmatx.err_cbk = smartcard_dma_error; hperh->hdmatx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -503,11 +508,11 @@ ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; hperh->hdmatx.config.channel = channel; - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); - usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); + ald_usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); __UNLOCK(hperh); - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE); return OK; } @@ -522,10 +527,11 @@ ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit. * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -545,7 +551,7 @@ ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint hperh->hdmarx.err_cbk = smartcard_dma_error; hperh->hdmarx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -554,10 +560,10 @@ ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; hperh->hdmarx.config.channel = channel; - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); __UNLOCK(hperh); - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE); return OK; } @@ -569,48 +575,55 @@ ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint * the configuration information for the specified SMARTCARD module. * @retval None */ -void smartcard_irq_handle(smartcard_handle_t *hperh) +void ald_smartcard_irq_handler(smartcard_handle_t *hperh) { uint32_t flag; uint32_t source; /* Handle parity error */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE); - source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= SMARTCARD_ERROR_PE; /* Handle frame error */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE); - source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= SMARTCARD_ERROR_FE; /* Handle noise error */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= SMARTCARD_ERROR_NE; /* Handle overrun error */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= SMARTCARD_ERROR_ORE; /* Handle receive */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE); - source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) __smartcard_recv_by_it(hperh); /* Handle transmit */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE); - source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) __smartcard_send_by_it(hperh); /* Handle transmit complete */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); - source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC); + if ((flag != RESET) && (source != RESET)) __smartcard_end_send_by_it(hperh); @@ -638,9 +651,9 @@ void smartcard_irq_handle(smartcard_handle_t *hperh) [..] This subsection provides a set of functions allowing to return the State of SmartCard communication process and also return Peripheral Errors occurred during communication process - (+) smartcard_get_state() API can be helpful to check in run-time the state + (+) ald_smartcard_get_state() API can be helpful to check in run-time the state of the SMARTCARD peripheral. - (+) smartcard_get_error() check in run-time errors that could be occurred during + (+) ald_smartcard_get_error() check in run-time errors that could be occurred during communication. @endverbatim @@ -653,7 +666,7 @@ void smartcard_irq_handle(smartcard_handle_t *hperh) * the configuration information for the specified SMARTCARD module. * @retval ALD state */ -smartcard_state_t smartcard_get_state(smartcard_handle_t *hperh) +smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh) { return hperh->state; } @@ -664,7 +677,7 @@ smartcard_state_t smartcard_get_state(smartcard_handle_t *hperh) * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD Error Code */ -uint32_t smartcard_get_error(smartcard_handle_t *hperh) +uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh) { return hperh->err_code; } @@ -694,8 +707,8 @@ static void smartcard_dma_send_cplt(void *arg) smartcard_handle_t *hperh = (smartcard_handle_t *)arg; hperh->tx_count = 0; - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); return; } @@ -711,7 +724,7 @@ static void smartcard_dma_recv_cplt(void *arg) smartcard_handle_t *hperh = (smartcard_handle_t *)arg; hperh->rx_count = 0; - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); if (hperh->rx_cplt_cbk) @@ -735,8 +748,8 @@ static void smartcard_dma_error(void *arg) hperh->err_code = SMARTCARD_ERROR_DMA; hperh->state = SMARTCARD_STATE_READY; - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); if (hperh->error_cbk) hperh->error_cbk(hperh); @@ -761,16 +774,16 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t if (timeout == 0) return OK; - tick = __get_tick(); + tick = ald_get_tick(); - while ((usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) + while ((ald_usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) { - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); return TIMEOUT; } @@ -784,7 +797,7 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t * @param hperh: Pointer to a smartcard_handle_t structure that contains * the configuration information for the specified SMARTCARD module. * Function called under interruption only, once - * interruptions have been enabled by smartcard_send_by_it() + * interruptions have been enabled by ald_smartcard_send_by_it() * @retval Status, see @ref ald_status_t. */ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) @@ -796,8 +809,8 @@ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) if (--hperh->tx_count == 0) { - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); } return OK; @@ -812,11 +825,11 @@ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) */ static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hperh) { - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); if (hperh->state == SMARTCARD_STATE_READY) - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); if (hperh->tx_cplt_cbk) hperh->tx_cplt_cbk(hperh); @@ -840,9 +853,9 @@ static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh) if (--hperh->rx_count == 0) { - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); if (hperh->rx_cplt_cbk) @@ -901,13 +914,14 @@ static void smartcard_set_config(smartcard_handle_t *hperh) if (READ_BIT(hperh->perh->CON0, (1 << 15))) { /* Integer part computing in case Oversampling mode is 8 Samples */ - integer = ((25 * cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); + integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); } else { /* Integer part computing in case Oversampling mode is 16 Samples */ - integer = ((25 * cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); + integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); } + tmp = (integer / 100) << 4; /* Determine the fractional part */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c similarity index 83% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c index 45e24960f8e15802b4dc128d575664c15403315b..9ab99c71a543b0a0d5c353ce8e1850b5d80c29d2 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -34,16 +34,16 @@ (+++) Enable the clock for the SPI GPIOs (+++) Configure these SPI pins as push-pull (##) NVIC configuration if you need to use interrupt process - by implementing the mcu_irq_config() API. - Invoked spi_irq_handle() function in SPI-IRQ function + by implementing the ald_mcu_irq_config() API. + Invoked ald_spi_irq_handler() function in SPI-IRQ function (##) DMA Configuration if you need to use DMA process (+++) Define ALD_DMA in ald_conf.h - (+++) Enable the DMAx clock + (+++) Enable the DMAx clock (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. - (#) Initialize the SPI module by invoking the spi_init() API. + (#) Initialize the SPI module by invoking the ald_spi_init() API. [..] Circular mode restriction: @@ -51,7 +51,7 @@ (##) Master 2Lines RxOnly (##) Master 1Line Rx (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs - the spi_dma_pause()/ spi_dma_stop(). + the ald_spi_dma_pause()/ ald_spi_dma_stop(). * @endverbatim */ @@ -104,7 +104,7 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); (+) User must configure all related peripherals resources (CLOCK, GPIO, DMA, NVIC). - (+) Call the function spi_init() to configure the selected device with + (+) Call the function ald_spi_init() to configure the selected device with the selected configuration: (++) Mode (++) Direction @@ -117,7 +117,7 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); (++) CRC Calculation (++) CRC Polynomial if CRC enabled - (+) Call the function spi_reset() to reset the selected SPIx periperal. + (+) Call the function ald_spi_reset() to reset the selected SPIx periperal. @endverbatim * @{ @@ -129,7 +129,7 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); * the configuration information for the specified SPI module. * @retval None */ -void spi_reset(spi_handle_t *hperh) +void ald_spi_reset(spi_handle_t *hperh) { hperh->perh->CON1 = 0x0; hperh->perh->CON2 = 0x0; @@ -148,7 +148,7 @@ void spi_reset(spi_handle_t *hperh) * the configuration information for the specified SPI module. * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_init(spi_handle_t *hperh) +ald_status_t ald_spi_init(spi_handle_t *hperh) { uint32_t tmp = 0; @@ -166,7 +166,7 @@ ald_status_t spi_init(spi_handle_t *hperh) if (hperh == NULL) return ERROR; - spi_reset(hperh); + ald_spi_reset(hperh); tmp = hperh->perh->CON1; @@ -251,37 +251,63 @@ ald_status_t spi_init(spi_handle_t *hperh) * - 0 Success * - -1 Failed */ -int32_t spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) +int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) { uint16_t cnt = 2000, temp; hperh->perh->DATA = data; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0); + cnt = 2000; + + while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0 && (--cnt)); + temp = hperh->perh->DATA; UNUSED(temp); return cnt == 0 ? -1 : 0; } +/** + * @brief transmit one byte fast in blocking mode(1line). + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data) +{ + uint16_t cnt = 2000; + + hperh->perh->DATA = data; + + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); + + return cnt == 0 ? -1 : 0; +} + /** * @brief Receive one byte fast in blocking mode. * @param hperh: Pointer to a spi_handle_t structure. * @retval Data. */ -uint8_t spi_recv_byte_fast(spi_handle_t *hperh) +uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh) { uint16_t cnt = 2000; if (hperh->init.mode == SPI_MODE_MASTER) { hperh->perh->DATA = 0xFF; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); } cnt = 2000; + while (((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0) && (--cnt)); + return (uint8_t)hperh->perh->DATA; } @@ -293,12 +319,13 @@ uint8_t spi_recv_byte_fast(spi_handle_t *hperh) * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; @@ -316,8 +343,10 @@ ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE) SPI_1LINE_TX(hperh); + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) SPI_ENABLE(hperh); @@ -378,7 +407,7 @@ ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t } if (hperh->init.dir == SPI_DIRECTION_2LINES) - spi_clear_flag_status(hperh, SPI_IF_OVE); + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); hperh->state = SPI_STATE_READY; __UNLOCK(hperh); @@ -394,13 +423,14 @@ ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { uint16_t temp; assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; @@ -417,6 +447,7 @@ ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) SPI_1LINE_RX(hperh); @@ -424,7 +455,7 @@ ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t { __UNLOCK(hperh); hperh->state = SPI_STATE_READY; - return spi_send_recv(hperh, buf, buf, size, timeout); + return ald_spi_send_recv(hperh, buf, buf, size, timeout); } if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) @@ -498,11 +529,11 @@ ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t UNUSED(temp); } - if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { hperh->err_code |= SPI_ERROR_CRC; SPI_CRC_RESET(hperh); - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); hperh->state = SPI_STATE_READY; __UNLOCK(hperh); return ERROR; @@ -523,7 +554,7 @@ ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) +ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) { uint16_t temp; @@ -531,8 +562,10 @@ ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf if (hperh->state != SPI_STATE_READY) return BUSY; + if (hperh->init.dir != SPI_DIRECTION_2LINES) return ERROR; + if (tx_buf == NULL || rx_buf == NULL || size == 0) return ERROR; @@ -701,11 +734,11 @@ ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf return TIMEOUT; } - if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { hperh->err_code |= SPI_ERROR_CRC; SPI_CRC_RESET(hperh); - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); hperh->state = SPI_STATE_READY; __UNLOCK(hperh); @@ -725,12 +758,13 @@ ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; @@ -754,12 +788,12 @@ ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) if (hperh->init.dir == SPI_DIRECTION_2LINES) { - spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); } else { - spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); } if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) @@ -775,16 +809,18 @@ ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) - return ERROR; /* Please call spi_send_recv_by_it() */ + return ERROR; /* Please call ald_spi_send_recv_by_it() */ __LOCK(hperh); hperh->state = SPI_STATE_BUSY_RX; @@ -804,8 +840,8 @@ ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) if (hperh->init.crc_calc == ENABLE) SPI_CRC_RESET(hperh); - spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) SPI_ENABLE(hperh); @@ -822,12 +858,13 @@ ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) +ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) return ERROR; @@ -846,9 +883,9 @@ ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t * if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); - spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); - spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); return OK; } @@ -862,12 +899,13 @@ ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t * * @param channel: DMA channel as SPI transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; @@ -884,6 +922,7 @@ ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u if (hperh->init.dir == SPI_DIRECTION_1LINE) SPI_1LINE_TX(hperh); + if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); @@ -896,7 +935,7 @@ ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u hperh->hdmatx.err_cbk = spi_dma_error; /* Configure SPI DMA transmit */ - dma_config_struct(&(hperh->hdmatx.config)); + ald_dma_config_struct(&(hperh->hdmatx.config)); hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; @@ -906,10 +945,10 @@ ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; hperh->hdmatx.config.channel = channel; - dma_config_basic(&(hperh->hdmatx)); + ald_dma_config_basic(&(hperh->hdmatx)); __UNLOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) SPI_ENABLE(hperh); @@ -925,12 +964,13 @@ ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u * @param channel: DMA channel as SPI transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; @@ -947,11 +987,13 @@ ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) SPI_1LINE_RX(hperh); + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) { __UNLOCK(hperh); - return ERROR; /* Please use spi_send_recv_by_dma() */ + return ERROR; /* Please use ald_spi_send_recv_by_dma() */ } + if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); @@ -964,7 +1006,7 @@ ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u hperh->hdmarx.err_cbk = spi_dma_error; /* Configure DMA Receive */ - dma_config_struct(&(hperh->hdmarx.config)); + ald_dma_config_struct(&(hperh->hdmarx.config)); hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; @@ -974,10 +1016,10 @@ ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; hperh->hdmarx.config.channel = channel; - dma_config_basic(&(hperh->hdmarx)); + ald_dma_config_basic(&(hperh->hdmarx)); __UNLOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) SPI_ENABLE(hperh); @@ -995,12 +1037,13 @@ ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u * @param rx_channel: DMA channel as SPI receive * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) +ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX) return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) return ERROR; @@ -1017,6 +1060,7 @@ ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t if (hperh->hdmatx.perh == NULL) hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) hperh->hdmarx.perh = DMA0; @@ -1033,7 +1077,7 @@ ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t SPI_CRC_RESET(hperh); /* Configure SPI DMA transmit */ - dma_config_struct(&(hperh->hdmatx.config)); + ald_dma_config_struct(&(hperh->hdmatx.config)); hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; hperh->hdmatx.config.src = (void *)tx_buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; @@ -1043,10 +1087,10 @@ ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; hperh->hdmatx.config.channel = tx_channel; - dma_config_basic(&(hperh->hdmatx)); + ald_dma_config_basic(&(hperh->hdmatx)); /* Configure DMA Receive */ - dma_config_struct(&(hperh->hdmarx.config)); + ald_dma_config_struct(&(hperh->hdmarx.config)); hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)rx_buf; @@ -1056,11 +1100,11 @@ ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; hperh->hdmarx.config.channel = rx_channel; - dma_config_basic(&(hperh->hdmarx)); + ald_dma_config_basic(&(hperh->hdmarx)); __UNLOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); return OK; } @@ -1070,13 +1114,13 @@ ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t * @param hperh: Pointer to a spi_handle_t structure. * @retval Status */ -ald_status_t spi_dma_pause(spi_handle_t *hperh) +ald_status_t ald_spi_dma_pause(spi_handle_t *hperh) { assert_param(IS_SPI(hperh->perh)); __LOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); __UNLOCK(hperh); return OK; @@ -1087,13 +1131,13 @@ ald_status_t spi_dma_pause(spi_handle_t *hperh) * @param hperh: Pointer to a spi_handle_t structure. * @retval Status */ -ald_status_t spi_dma_resume(spi_handle_t *hperh) +ald_status_t ald_spi_dma_resume(spi_handle_t *hperh) { assert_param(IS_SPI(hperh->perh)); __LOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); __UNLOCK(hperh); return OK; @@ -1104,13 +1148,13 @@ ald_status_t spi_dma_resume(spi_handle_t *hperh) * @param hperh: Pointer to a spi_handle_t structure. * @retval Status */ -ald_status_t spi_dma_stop(spi_handle_t *hperh) +ald_status_t ald_spi_dma_stop(spi_handle_t *hperh) { assert_param(IS_SPI(hperh->perh)); __LOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); __UNLOCK(hperh); hperh->state = SPI_STATE_READY; @@ -1130,7 +1174,7 @@ ald_status_t spi_dma_stop(spi_handle_t *hperh) =============================================================================== [..] This subsection provides a set of functions allowing to control the SPI. - (+) Handle interrupt about SPI module. The spi_irq_handle() function must + (+) Handle interrupt about SPI module. The ald_spi_irq_handler() function must be invoked by SPI-IRQ function. (+) Configure the interrupt DISABLE/ENABLE. (+) Configure the DMA request. @@ -1147,14 +1191,14 @@ ald_status_t spi_dma_stop(spi_handle_t *hperh) * @param hperh: Pointer to a spi_handle_t structure. * @retval None */ -void spi_irq_handle(spi_handle_t *hperh) +void ald_spi_irq_handler(spi_handle_t *hperh) { if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) { - if ((spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) __spi_recv_by_it(hperh); - if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) __spi_send_by_it(hperh); } @@ -1162,43 +1206,45 @@ void spi_irq_handle(spi_handle_t *hperh) { if (hperh->tx_size == hperh->tx_count) { - if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) __spi_send_recv_by_it(hperh, SPI_SR_TXBE); } else { - if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET) - && (spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET) + && (ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) __spi_send_recv_by_it(hperh, SPI_SR_TXBE_RXBNE); } } - if ((spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) + if ((ald_spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) { - if (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) { hperh->err_code |= SPI_ERROR_CRC; - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); } - if (spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) + + if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) { hperh->err_code |= SPI_ERROR_MODF; - spi_clear_flag_status(hperh, SPI_IF_MODF); + ald_spi_clear_flag_status(hperh, SPI_IF_MODF); } - if (spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) + + if (ald_spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) { if (hperh->state != SPI_STATE_BUSY_TX) { hperh->err_code |= SPI_ERROR_OVE; - spi_clear_flag_status(hperh, SPI_IF_OVE); + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); } } if (hperh->err_code != SPI_ERROR_NONE) { - spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); hperh->state = SPI_STATE_READY; if (hperh->err_cbk) @@ -1219,7 +1265,7 @@ void spi_irq_handle(spi_handle_t *hperh) * - DISABLE * @retval None */ -void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) +void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) { assert_param(IS_SPI(hperh->perh)); assert_param(IS_SPI_IT(it)); @@ -1240,7 +1286,7 @@ void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) * This parameter can be one of the @ref spi_baud_t. * @retval None */ -void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) +void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) { uint32_t tmp = 0; assert_param(IS_SPI(hperh->perh)); @@ -1263,7 +1309,7 @@ void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) * - DISABLE * @retval None */ -void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state) +void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state) { assert_param(IS_SPI(hperh->perh)); assert_param(IS_SPI_DMA_REQ(req)); @@ -1287,6 +1333,25 @@ void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t stat return; } +/** @brief Check whether the specified SPI state flag is set or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: specifies the flag to check. + * This parameter can be one of the @ref spi_status_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + /** * @brief Checks whether the specified SPI interrupt has occurred or not. * @param hperh: Pointer to a spi_handle_t structure. @@ -1296,7 +1361,7 @@ void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t stat * - SET * - RESET */ -it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it) +it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it) { assert_param(IS_SPI(hperh->perh)); assert_param(IS_SPI_IT(it)); @@ -1315,7 +1380,7 @@ it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it) * - SET * - RESET */ -flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) +flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) { assert_param(IS_SPI(hperh->perh)); assert_param(IS_SPI_IF(flag)); @@ -1332,7 +1397,7 @@ flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) * This parameter can be one of the @ref spi_flag_t. * @retval None */ -void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) +void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) { uint32_t temp; @@ -1344,6 +1409,7 @@ void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) SET_BIT(hperh->perh->STAT, SPI_STAT_CRCERR_MSK); return; } + if (flag == SPI_IF_OVE) { temp = hperh->perh->DATA; @@ -1351,6 +1417,7 @@ void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) UNUSED(temp); return; } + if (flag == SPI_IF_MODF) { temp = hperh->perh->STAT; @@ -1372,17 +1439,17 @@ void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) */ static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tick = __get_tick(); + uint32_t tick = ald_get_tick(); assert_param(timeout > 0); - while ((spi_get_flag_status(hperh, flag)) != status) + while ((ald_spi_get_flag_status(hperh, flag)) != status) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) { - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); return TIMEOUT; } } @@ -1402,14 +1469,14 @@ static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag { assert_param(timeout > 0); - while (((spi_get_flag_status(hperh, flag)) != status) && (--timeout)); + while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout)); if (timeout) return OK; - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); return TIMEOUT; } @@ -1427,8 +1494,8 @@ static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag =============================================================================== [..] This subsection provides a set of functions allowing to control the SPI. - (+) spi_get_state() API can check in run-time the state of the SPI peripheral - (+) spi_get_error() check in run-time Errors occurring during communication + (+) ald_spi_get_state() API can check in run-time the state of the SPI peripheral + (+) ald_spi_get_error() check in run-time Errors occurring during communication @endverbatim * @{ @@ -1439,7 +1506,7 @@ static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag * @param hperh: Pointer to a spi_handle_t structure. * @retval ALD state */ -spi_state_t spi_get_state(spi_handle_t *hperh) +spi_state_t ald_spi_get_state(spi_handle_t *hperh) { assert_param(IS_SPI(hperh->perh)); return hperh->state; @@ -1450,7 +1517,7 @@ spi_state_t spi_get_state(spi_handle_t *hperh) * @param hperh: Pointer to a spi_handle_t structure. * @retval SPI Error Code */ -uint32_t spi_get_error(spi_handle_t *hperh) +uint32_t ald_spi_get_error(spi_handle_t *hperh) { assert_param(IS_SPI(hperh->perh)); return hperh->err_code; @@ -1477,11 +1544,11 @@ static void __spi_send_by_it(spi_handle_t *hperh) { if (hperh->tx_count == 0) { - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); hperh->state = SPI_STATE_READY; if (hperh->init.dir == SPI_DIRECTION_2LINES) - spi_clear_flag_status(hperh, SPI_IF_OVE); + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) { @@ -1507,6 +1574,7 @@ static void __spi_send_by_it(spi_handle_t *hperh) hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; hperh->tx_buf += 2; } + --hperh->tx_count; if (hperh->tx_count == 0) @@ -1526,6 +1594,7 @@ static void __spi_send_by_it(spi_handle_t *hperh) static void __spi_recv_by_it(spi_handle_t *hperh) { uint16_t temp; + if (hperh->init.data_size == SPI_DATA_SIZE_8) { *hperh->rx_buf = hperh->perh->DATA; @@ -1536,6 +1605,7 @@ static void __spi_recv_by_it(spi_handle_t *hperh) *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; hperh->rx_buf += 2; } + --hperh->rx_count; if ((hperh->rx_count == 1) && (hperh->init.crc_calc)) @@ -1543,13 +1613,13 @@ static void __spi_recv_by_it(spi_handle_t *hperh) if (hperh->rx_count == 0) { - spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); hperh->state = SPI_STATE_READY; - if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { hperh->err_code |= SPI_ERROR_CRC; - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); if (hperh->err_cbk) hperh->err_cbk(hperh); @@ -1638,7 +1708,8 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) { if (hperh->init.crc_calc) SPI_CRCNEXT_ENABLE(hperh); - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); } } } @@ -1646,15 +1717,15 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) if (hperh->rx_count == 0) { - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); hperh->state = SPI_STATE_READY; - if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { hperh->err_code |= SPI_ERROR_CRC; - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); if (hperh->err_cbk) hperh->err_cbk(hperh); @@ -1682,11 +1753,11 @@ static void spi_dma_send_cplt(void *arg) spi_handle_t *hperh = (spi_handle_t *)arg; hperh->tx_count = 0; - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); hperh->state = SPI_STATE_READY; if (hperh->init.dir == SPI_DIRECTION_2LINES) - spi_clear_flag_status(hperh, SPI_IF_OVE); + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) hperh->err_code |= SPI_ERROR_FLAG; @@ -1718,8 +1789,8 @@ static void spi_dma_recv_cplt(void *arg) spi_handle_t *hperh = (spi_handle_t *)arg; hperh->rx_count = 0; - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); hperh->state = SPI_STATE_READY; if (hperh->init.crc_calc) @@ -1730,11 +1801,11 @@ static void spi_dma_recv_cplt(void *arg) tmp = hperh->perh->DATA; UNUSED(tmp); - if (spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { SET_BIT(hperh->err_code, SPI_ERROR_CRC); SPI_CRC_RESET(hperh); - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); } } @@ -1771,10 +1842,10 @@ static void spi_dma_send_recv_cplt(void *arg) tmp = hperh->perh->DATA; UNUSED(tmp); - if (spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { SET_BIT(hperh->err_code, SPI_ERROR_CRC); - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); } } @@ -1783,8 +1854,8 @@ static void spi_dma_send_recv_cplt(void *arg) for (delay = 0; delay < 3000; delay++); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); hperh->tx_count = 0; hperh->rx_count = 0; hperh->state = SPI_STATE_READY; @@ -1813,8 +1884,8 @@ static void spi_dma_error(void *arg) { spi_handle_t *hperh = (spi_handle_t *)arg; - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); SET_BIT(hperh->err_code, SPI_ERROR_DMA); hperh->tx_count = 0; diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c similarity index 66% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c index d4419ebdec171548e971864828de07f3afeca44f..677bbdcf86eabab4b48eed0542015e6234580949 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -3,7 +3,7 @@ * * @file ald_timer.c * @brief TIMER module driver. - * This is the common part of the TIMER initialization + * This is the common part of the TIMER initialization * * @version V1.0 * @date 06 Nov 2017 @@ -57,6 +57,7 @@ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t * static void timer_dma_capture_cplt(void *arg); static void timer_dma_period_elapse_cplt(void *arg); static void timer_dma_error(void *arg); + static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config); #endif /** * @} @@ -93,7 +94,7 @@ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t * * @param hperh: TIMER base handle * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_base_init(timer_handle_t *hperh) +ald_status_t ald_timer_base_init(timer_handle_t *hperh) { if (hperh == NULL) return ERROR; @@ -117,7 +118,7 @@ ald_status_t timer_base_init(timer_handle_t *hperh) * @param hperh: TIMER base handle * @retval Status, see @ref ald_status_t. */ -void timer_base_reset(timer_handle_t *hperh) +void ald_timer_base_reset(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); @@ -134,7 +135,7 @@ void timer_base_reset(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_base_start(timer_handle_t *hperh) +void ald_timer_base_start(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); @@ -150,7 +151,7 @@ void timer_base_start(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_base_stop(timer_handle_t *hperh) +void ald_timer_base_stop(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); @@ -166,11 +167,11 @@ void timer_base_stop(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_base_start_by_it(timer_handle_t *hperh) +void ald_timer_base_start_by_it(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); - timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); TIMER_ENABLE(hperh); return; @@ -181,11 +182,11 @@ void timer_base_start_by_it(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_base_stop_by_it(timer_handle_t *hperh) +void ald_timer_base_stop_by_it(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); - timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); TIMER_DISABLE(hperh); return; @@ -201,13 +202,14 @@ void timer_base_stop_by_it(timer_handle_t *hperh) * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf == 0) || (len == 0)) @@ -224,7 +226,7 @@ ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, hdma->err_cbk = timer_dma_error; hdma->err_arg = (void *)hperh; - dma_config_struct(&hdma->config); + ald_dma_config_struct(&hdma->config); hdma->config.src = (void *)buf; hdma->config.dst = (void *)&hperh->perh->AR; hdma->config.size = len; @@ -234,27 +236,9 @@ ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, hdma->config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; hdma->config.channel = dma_ch; - if (hperh->perh == TIMER0) - hdma->config.msel = DMA_MSEL_TIMER0; - else if (hperh->perh == TIMER1) - hdma->config.msel = DMA_MSEL_TIMER1; - else if (hperh->perh == TIMER2) - hdma->config.msel = DMA_MSEL_TIMER2; - else if (hperh->perh == TIMER3) - hdma->config.msel = DMA_MSEL_TIMER3; - else if (hperh->perh == TIMER4) - hdma->config.msel = DMA_MSEL_TIMER4; - else if (hperh->perh == TIMER5) - hdma->config.msel = DMA_MSEL_TIMER5; - else if (hperh->perh == TIMER6) - hdma->config.msel = DMA_MSEL_TIMER6; - else if (hperh->perh == TIMER7) - hdma->config.msel = DMA_MSEL_TIMER7; - else - ; - - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); + timer_dma_msel(hperh->perh, &hdma->config); + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); TIMER_ENABLE(hperh); return OK; @@ -265,11 +249,11 @@ ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, * @param hperh: TIMER handle * @retval None */ -void timer_base_stop_by_dma(timer_handle_t *hperh) +void ald_timer_base_stop_by_dma(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); - timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); TIMER_DISABLE(hperh); hperh->state = TIMER_STATE_READY; @@ -306,9 +290,9 @@ void timer_base_stop_by_dma(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_oc_init(timer_handle_t *hperh) +ald_status_t ald_timer_oc_init(timer_handle_t *hperh) { - return timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** @@ -322,7 +306,7 @@ ald_status_t timer_oc_init(timer_handle_t *hperh) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); @@ -346,7 +330,7 @@ void timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); @@ -371,30 +355,30 @@ void timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; - case TIMER_CHANNEL_4: - timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; - default: - break; + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); @@ -417,30 +401,30 @@ void timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; - case TIMER_CHANNEL_4: - timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; - default: - break; + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); @@ -453,29 +437,34 @@ void timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) return; } + + + + #ifdef ALD_DMA /** * @brief Starts the TIMER Output Compare signal generation in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf == 0) || (len == 0)) @@ -492,7 +481,7 @@ ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, hdma->err_cbk = timer_dma_error; hdma->err_arg = (void *)hperh; - dma_config_struct(&hdma->config); + ald_dma_config_struct(&hdma->config); hdma->config.src = (void *)buf; hdma->config.size = len; hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; @@ -500,61 +489,45 @@ ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, hdma->config.dst_inc = DMA_DATA_INC_NONE; hdma->config.channel = dma_ch; - if (hperh->perh == TIMER0) - hdma->config.msel = DMA_MSEL_TIMER0; - else if (hperh->perh == TIMER1) - hdma->config.msel = DMA_MSEL_TIMER1; - else if (hperh->perh == TIMER2) - hdma->config.msel = DMA_MSEL_TIMER2; - else if (hperh->perh == TIMER3) - hdma->config.msel = DMA_MSEL_TIMER3; - else if (hperh->perh == TIMER4) - hdma->config.msel = DMA_MSEL_TIMER4; - else if (hperh->perh == TIMER5) - hdma->config.msel = DMA_MSEL_TIMER5; - else if (hperh->perh == TIMER6) - hdma->config.msel = DMA_MSEL_TIMER6; - else if (hperh->perh == TIMER7) - hdma->config.msel = DMA_MSEL_TIMER7; - else - ;//do nothing + + timer_dma_msel(hperh->perh, &hdma->config); switch (ch) { - case TIMER_CHANNEL_1: - hdma->config.dst = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; - - case TIMER_CHANNEL_2: - hdma->config.dst = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; - - case TIMER_CHANNEL_3: - hdma->config.dst = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; - - case TIMER_CHANNEL_4: - hdma->config.dst = (void *)&hperh->perh->CCVAL4; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - break; - - default: - break; + case TIMER_CHANNEL_1: + hdma->config.dst = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.dst = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.dst = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hdma->config.dst = (void *)&hperh->perh->CCVAL4; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); @@ -570,37 +543,37 @@ ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, * @brief Stops the TIMER Output Compare signal generation in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; - case TIMER_CHANNEL_2: - timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; - case TIMER_CHANNEL_3: - timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; - case TIMER_CHANNEL_4: - timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; - default: - break; + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); @@ -621,18 +594,18 @@ void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @brief TIMER PWM functions * * @verbatim - ============================================================================== - ##### Time PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER PWM. - (+) Start the Time PWM. - (+) Stop the Time PWM. - (+) Start the Time PWM and enable interrupt. - (+) Stop the Time PWM and disable interrupt. - (+) Start the Time PWM and enable DMA transfer. - (+) Stop the Time PWM and disable DMA transfer. + ============================================================================== + ##### Time PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER PWM. + (+) Start the Time PWM. + (+) Stop the Time PWM. + (+) Start the Time PWM and enable interrupt. + (+) Stop the Time PWM and disable interrupt. + (+) Start the Time PWM and enable DMA transfer. + (+) Stop the Time PWM and disable DMA transfer. @endverbatim * @{ @@ -643,25 +616,25 @@ void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @param hperh: TIMER handle * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_pwm_init(timer_handle_t *hperh) +ald_status_t ald_timer_pwm_init(timer_handle_t *hperh) { - return timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** * @brief Starts the PWM signal generation. * @param hperh: TIMER handle * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) { - timer_oc_start(hperh, ch); + ald_timer_oc_start(hperh, ch); return; } @@ -669,16 +642,16 @@ void timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) * @brief Stops the PWM signal generation. * @param hperh: TIMER handle * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) { - timer_oc_stop(hperh, ch); + ald_timer_oc_stop(hperh, ch); return; } @@ -686,16 +659,16 @@ void timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) * @brief Starts the PWM signal generation in interrupt mode. * @param hperh: TIMER handle * @param ch: TIMER Channel to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_oc_start_by_it(hperh, ch); + ald_timer_oc_start_by_it(hperh, ch); return; } @@ -703,16 +676,16 @@ void timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @brief Stops the PWM signal generation in interrupt mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_oc_stop_by_it(hperh, ch); + ald_timer_oc_stop_by_it(hperh, ch); return; } @@ -721,37 +694,37 @@ void timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @brief Starts the TIMER PWM signal generation in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) { - return timer_oc_start_by_dma(hperh, ch, hdma, buf, len, dma_ch); + return ald_timer_oc_start_by_dma(hperh, ch, hdma, buf, len, dma_ch); } /** * @brief Stops the TIMER PWM signal generation in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - timer_oc_stop_by_dma(hperh, ch); + ald_timer_oc_stop_by_dma(hperh, ch); return; } #endif @@ -761,9 +734,9 @@ void timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @param freq: PWM freq to set * @retval None */ -void timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) +void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) { - uint32_t _arr = cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; + uint32_t _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; WRITE_REG(hperh->perh->AR, _arr); hperh->init.period = _arr; @@ -773,15 +746,15 @@ void timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) * @brief Set the PWM duty. * @param hperh: TIMER handle * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @param duty: PWM duty to set * @retval None */ -void timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty) +void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty) { uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1; @@ -803,40 +776,43 @@ void timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty * @brief Set capture the PWM. * @param hperh: TIMER handle * @param ch: TIMER Channels to be captured the PWM - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - break; - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - break; - default: - break; + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + + default: + break; } SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); @@ -874,9 +850,9 @@ void timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) * @param hperh: TIMER handle * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_ic_init(timer_handle_t *hperh) +ald_status_t ald_timer_ic_init(timer_handle_t *hperh) { - return timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** @@ -890,7 +866,7 @@ ald_status_t timer_ic_init(timer_handle_t *hperh) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); @@ -910,7 +886,7 @@ void timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); @@ -930,26 +906,30 @@ void timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; - case TIMER_CHANNEL_4: - timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); @@ -968,26 +948,30 @@ void timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; - case TIMER_CHANNEL_4: - timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); @@ -1000,24 +984,25 @@ void timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @brief Starts the TIMER Input Capture measurement in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf == 0) || (len == 0)) @@ -1034,7 +1019,7 @@ ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, hdma->err_cbk = timer_dma_error; hdma->err_arg = (void *)hperh; - dma_config_struct(&hdma->config); + ald_dma_config_struct(&hdma->config); hdma->config.dst = (void *)buf; hdma->config.size = len; hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; @@ -1042,61 +1027,44 @@ ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; hdma->config.channel = dma_ch; - if (hperh->perh == TIMER0) - hdma->config.msel = DMA_MSEL_TIMER0; - else if (hperh->perh == TIMER1) - hdma->config.msel = DMA_MSEL_TIMER1; - else if (hperh->perh == TIMER2) - hdma->config.msel = DMA_MSEL_TIMER2; - else if (hperh->perh == TIMER3) - hdma->config.msel = DMA_MSEL_TIMER3; - else if (hperh->perh == TIMER4) - hdma->config.msel = DMA_MSEL_TIMER4; - else if (hperh->perh == TIMER5) - hdma->config.msel = DMA_MSEL_TIMER5; - else if (hperh->perh == TIMER6) - hdma->config.msel = DMA_MSEL_TIMER6; - else if (hperh->perh == TIMER7) - hdma->config.msel = DMA_MSEL_TIMER7; - else - ;/* do nothing */ + timer_dma_msel(hperh->perh, &hdma->config); switch (ch) { - case TIMER_CHANNEL_1: - hdma->config.src = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; - - case TIMER_CHANNEL_2: - hdma->config.src = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; - - case TIMER_CHANNEL_3: - hdma->config.src = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; - - case TIMER_CHANNEL_4: - hdma->config.src = (void *)&hperh->perh->CCVAL4; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - break; - - default: - break; + case TIMER_CHANNEL_1: + hdma->config.src = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.src = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.src = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hdma->config.src = (void *)&hperh->perh->CCVAL4; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); @@ -1108,33 +1076,37 @@ ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, * @brief Stops the TIMER Input Capture measurement in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - case TIMER_CHANNEL_3: - timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; - case TIMER_CHANNEL_4: - timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); @@ -1177,7 +1149,7 @@ void timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_OP_MODE_REPEAT: Repetitive pulses wil be generated. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) +ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) { if (hperh == NULL) return ERROR; @@ -1207,7 +1179,7 @@ ald_status_t timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) +void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) { /* Enable the Capture compare and the Input Capture channels * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) @@ -1233,7 +1205,7 @@ void timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) +void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) { timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); @@ -1254,7 +1226,7 @@ void timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) +void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) { /* Enable the Capture compare and the Input Capture channels * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) @@ -1262,8 +1234,8 @@ void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_ * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together */ - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); @@ -1282,10 +1254,10 @@ void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_ * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) +void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) { - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); @@ -1303,18 +1275,18 @@ void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t * @brief TIMER Encoder functions * * @verbatim - ============================================================================== - ##### Time Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER Encoder. - (+) Start the Time Encoder. - (+) Stop the Time Encoder. - (+) Start the Time Encoder and enable interrupt. - (+) Stop the Time Encoder and disable interrupt. - (+) Start the Time Encoder and enable DMA transfer. - (+) Stop the Time Encoder and disable DMA transfer. + ============================================================================== + ##### Time Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Encoder. + (+) Start the Time Encoder. + (+) Stop the Time Encoder. + (+) Start the Time Encoder and enable interrupt. + (+) Stop the Time Encoder and disable interrupt. + (+) Start the Time Encoder and enable DMA transfer. + (+) Stop the Time Encoder and disable DMA transfer. * @endverbatim * @{ @@ -1325,7 +1297,7 @@ void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t * @param config: TIMER Encoder Interface configuration structure * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config) +ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config) { if (hperh == NULL) return ERROR; @@ -1374,22 +1346,24 @@ ald_status_t timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *co * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected * @retval None */ -void timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - break; + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + break; + + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; } TIMER_ENABLE(hperh); @@ -1406,22 +1380,24 @@ void timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected * @retval None */ -void timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - break; + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + break; + + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; } TIMER_DISABLE(hperh); @@ -1438,26 +1414,28 @@ void timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected * @retval None */ -void timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; } TIMER_ENABLE(hperh); @@ -1474,26 +1452,28 @@ void timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected * @retval None */ -void timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; } TIMER_DISABLE(hperh); @@ -1519,14 +1499,15 @@ void timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @param dma_ch2: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, - uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2) +ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, + uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) @@ -1535,6 +1516,7 @@ ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t c if (hdma1->perh == NULL) hdma1->perh = DMA0; + if (hdma2->perh == NULL) hdma2->perh = DMA0; @@ -1544,80 +1526,63 @@ ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t c hdma1->err_cbk = timer_dma_error; hdma1->err_arg = (void *)hperh; - dma_config_struct(&hdma1->config); + ald_dma_config_struct(&hdma1->config); hdma1->config.size = len; hdma1->config.data_width = DMA_DATA_SIZE_HALFWORD; hdma1->config.src_inc = DMA_DATA_INC_NONE; hdma1->config.dst_inc = DMA_DATA_INC_HALFWORD; - if (hperh->perh == TIMER0) - hdma1->config.msel = DMA_MSEL_TIMER0; - else if (hperh->perh == TIMER1) - hdma1->config.msel = DMA_MSEL_TIMER1; - else if (hperh->perh == TIMER2) - hdma1->config.msel = DMA_MSEL_TIMER2; - else if (hperh->perh == TIMER3) - hdma1->config.msel = DMA_MSEL_TIMER3; - else if (hperh->perh == TIMER4) - hdma1->config.msel = DMA_MSEL_TIMER4; - else if (hperh->perh == TIMER5) - hdma1->config.msel = DMA_MSEL_TIMER5; - else if (hperh->perh == TIMER6) - hdma1->config.msel = DMA_MSEL_TIMER6; - else if (hperh->perh == TIMER7) - hdma1->config.msel = DMA_MSEL_TIMER7; - else - ;/* do nothing */ + timer_dma_msel(hperh->perh, &hdma1->config); switch (ch) { - case TIMER_CHANNEL_1: - hdma1->config.src = (void *)&hperh->perh->CCVAL1; - hdma1->config.dst = (void *)buf1; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma1->config.channel = dma_ch1; - dma_config_basic(hdma1); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); - break; - - case TIMER_CHANNEL_2: - hdma1->config.src = (void *)&hperh->perh->CCVAL2; - hdma1->config.dst = (void *)buf2; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hdma1->config.channel = dma_ch2; - dma_config_basic(hdma1); - timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - TIMER_ENABLE(hperh); - break; - - default: - hdma2->cplt_cbk = timer_dma_capture_cplt; - hdma2->cplt_arg = (void *)hperh; - hdma2->err_cbk = timer_dma_error; - hdma2->err_arg = (void *)hperh; - memcpy(&hdma2->config, &hdma1->config, sizeof(dma_config_t)); - - hdma1->config.src = (void *)&hperh->perh->CCVAL1; - hdma1->config.dst = (void *)buf1; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma1->config.channel = dma_ch1; - dma_config_basic(hdma1); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - - hdma2->config.src = (void *)&hperh->perh->CCVAL2; - hdma2->config.dst = (void *)buf2; - hdma2->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hdma2->config.channel = dma_ch2; - dma_config_basic(hdma2); - timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - TIMER_ENABLE(hperh); - break; + case TIMER_CHANNEL_1: + hdma1->config.src = (void *)&hperh->perh->CCVAL1; + hdma1->config.dst = (void *)buf1; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hdma1->config.channel = dma_ch1; + ald_dma_config_basic(hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + break; + + case TIMER_CHANNEL_2: + hdma1->config.src = (void *)&hperh->perh->CCVAL2; + hdma1->config.dst = (void *)buf2; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hdma1->config.channel = dma_ch2; + ald_dma_config_basic(hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + + default: + hdma2->cplt_cbk = timer_dma_capture_cplt; + hdma2->cplt_arg = (void *)hperh; + hdma2->err_cbk = timer_dma_error; + hdma2->err_arg = (void *)hperh; + memcpy(&hdma2->config, &hdma1->config, sizeof(dma_config_t)); + + hdma1->config.src = (void *)&hperh->perh->CCVAL1; + hdma1->config.dst = (void *)buf1; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hdma1->config.channel = dma_ch1; + ald_dma_config_basic(hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + + hdma2->config.src = (void *)&hperh->perh->CCVAL2; + hdma2->config.dst = (void *)buf2; + hdma2->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hdma2->config.channel = dma_ch2; + ald_dma_config_basic(hdma2); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; } return OK; @@ -1633,26 +1598,28 @@ ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t c * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected * @retval None */ -void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; } TIMER_DISABLE(hperh); @@ -1668,18 +1635,18 @@ void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @brief TIMER Hall Sensor functions * * @verbatim - ============================================================================== - ##### Time Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER hall sensor. - (+) Start the hall sensor. - (+) Stop the hall sensor. - (+) Start the hall sensor and enable interrupt. - (+) Stop the hall sensor and disable interrupt. - (+) Start the hall sensor and enable DMA transfer. - (+) Stop the hal sensor and disable DMA transfer. + ============================================================================== + ##### Time Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER hall sensor. + (+) Start the hall sensor. + (+) Stop the hall sensor. + (+) Start the hall sensor and enable interrupt. + (+) Stop the hall sensor and disable interrupt. + (+) Start the hall sensor and enable DMA transfer. + (+) Stop the hal sensor and disable DMA transfer. * @endverbatim * @{ @@ -1690,7 +1657,7 @@ void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @param config: TIMER Encoder Interface configuration structure * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config) +ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config) { timer_oc_init_t oc; @@ -1730,7 +1697,7 @@ ald_status_t timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_in * @param hperh: TIMER handle * @retval None */ -void timer_hall_sensor_start(timer_handle_t *hperh) +void ald_timer_hall_sensor_start(timer_handle_t *hperh) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); @@ -1745,7 +1712,7 @@ void timer_hall_sensor_start(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_hall_sensor_stop(timer_handle_t *hperh) +void ald_timer_hall_sensor_stop(timer_handle_t *hperh) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); @@ -1760,11 +1727,11 @@ void timer_hall_sensor_stop(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_hall_sensor_start_by_it(timer_handle_t *hperh) +void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); TIMER_ENABLE(hperh); @@ -1776,12 +1743,12 @@ void timer_hall_sensor_start_by_it(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_hall_sensor_stop_by_it(timer_handle_t *hperh) +void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); TIMER_DISABLE(hperh); return; @@ -1797,13 +1764,14 @@ void timer_hall_sensor_stop_by_it(timer_handle_t *hperh) * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf == 0) || (len == 0)) @@ -1819,25 +1787,20 @@ ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t hdma->err_cbk = timer_dma_error; hdma->err_arg = (void *)hperh; - dma_config_struct(&hdma->config); + ald_dma_config_struct(&hdma->config); hdma->config.size = len; hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; hdma->config.src_inc = DMA_DATA_INC_NONE; hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; - if (hperh->perh == TIMER0) - hdma->config.msel = DMA_MSEL_TIMER0; - else if (hperh->perh == TIMER6) - hdma->config.msel = DMA_MSEL_TIMER6; - else - ;/* do nothing */ + timer_dma_msel(hperh->perh, &hdma->config); hdma->config.src = (void *)&hperh->perh->CCVAL1; hdma->config.dst = (void *)buf; hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; hdma->config.channel = dma_ch; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); TIMER_ENABLE(hperh); @@ -1848,11 +1811,11 @@ ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t * @param hperh: TIMER handle * @retval None */ -void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) +void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); TIMER_DISABLE(hperh); @@ -1867,17 +1830,17 @@ void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) * @brief TIMER complementary output compare functions * * @verbatim - ============================================================================== - ##### Time complementary output compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Time complementary output compare. - (+) Stop the Time complementary output compare. - (+) Start the Time complementary output compare and enable interrupt. - (+) Stop the Time complementary output compare and disable interrupt. - (+) Start the Time complementary output compare and enable DMA transfer. - (+) Stop the Time complementary output compare and disable DMA transfer. + ============================================================================== + ##### Time complementary output compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary output compare. + (+) Stop the Time complementary output compare. + (+) Start the Time complementary output compare and enable interrupt. + (+) Stop the Time complementary output compare and disable interrupt. + (+) Start the Time complementary output compare and enable DMA transfer. + (+) Stop the Time complementary output compare and disable DMA transfer. * @endverbatim * @{ @@ -1893,7 +1856,7 @@ void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); @@ -1914,7 +1877,7 @@ void timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); @@ -1936,28 +1899,29 @@ void timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + + default: + break; } - timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); TIMER_MOE_ENABLE(hperh); TIMER_ENABLE(hperh); @@ -1976,32 +1940,33 @@ void timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + + default: + break; } if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK))) && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK))) && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) { - timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); } timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); @@ -2027,13 +1992,14 @@ void timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @param dma_ch: Channel of DMA. * @retval None */ -ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf == 0) || (len == 0)) @@ -2050,7 +2016,7 @@ ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, hdma->err_cbk = timer_dma_error; hdma->err_arg = (void *)hperh; - dma_config_struct(&hdma->config); + ald_dma_config_struct(&hdma->config); hdma->config.src = (void *)buf; hdma->config.size = len; hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; @@ -2061,32 +2027,32 @@ ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, switch (ch) { - case TIMER_CHANNEL_1: - hdma->config.dst = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; - - case TIMER_CHANNEL_2: - hdma->config.dst = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; - - case TIMER_CHANNEL_3: - hdma->config.dst = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; - - default: - break; + case TIMER_CHANNEL_1: + hdma->config.dst = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.dst = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.dst = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); @@ -2107,25 +2073,26 @@ ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + + default: + break; } timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); @@ -2143,17 +2110,17 @@ void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @brief TIMER complementary PWM functions * * @verbatim - ============================================================================== - ##### Time complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Time complementary PWM. - (+) Stop the Time complementary PWM. - (+) Start the Time complementary PWM and enable interrupt. - (+) Stop the Time complementary PWM and disable interrupt. - (+) Start the Time complementary PWM and enable DMA transfer. - (+) Stop the Time complementary PWM and disable DMA transfer. + ============================================================================== + ##### Time complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary PWM. + (+) Stop the Time complementary PWM. + (+) Start the Time complementary PWM and enable interrupt. + (+) Stop the Time complementary PWM and disable interrupt. + (+) Start the Time complementary PWM and enable DMA transfer. + (+) Stop the Time complementary PWM and disable DMA transfer. * @endverbatim * @{ @@ -2169,9 +2136,9 @@ void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_start(hperh, ch); + ald_timer_ocn_start(hperh, ch); } /** @@ -2184,9 +2151,9 @@ void timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_stop(hperh, ch); + ald_timer_ocn_stop(hperh, ch); } /** @@ -2200,9 +2167,9 @@ void timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_start_by_it(hperh, ch); + ald_timer_ocn_start_by_it(hperh, ch); } /** @@ -2216,9 +2183,9 @@ void timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_stop_by_it(hperh, ch); + ald_timer_ocn_stop_by_it(hperh, ch); } #ifdef ALD_DMA @@ -2237,10 +2204,10 @@ void timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @param dma_ch: Channel of DMA. * @retval None */ -ald_status_t timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) { - return timer_ocn_start_by_dma(hperh, hdma, ch, buf, len, dma_ch); + return ald_timer_ocn_start_by_dma(hperh, hdma, ch, buf, len, dma_ch); } /** @@ -2254,9 +2221,9 @@ ald_status_t timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_stop_by_dma(hperh, ch); + ald_timer_ocn_stop_by_dma(hperh, ch); } #endif /** @@ -2267,15 +2234,15 @@ void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @brief TIMER complementary one pulse functions * * @verbatim - ============================================================================== - ##### Time complementary one pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Time complementary one pulse. - (+) Stop the Time complementary one pulse. - (+) Start the Time complementary one pulse and enable interrupt. - (+) Stop the Time complementary one pulse and disable interrupt. + ============================================================================== + ##### Time complementary one pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary one pulse. + (+) Stop the Time complementary one pulse. + (+) Start the Time complementary one pulse and enable interrupt. + (+) Stop the Time complementary one pulse and disable interrupt. * @endverbatim * @{ @@ -2290,9 +2257,9 @@ void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_start(hperh, ch); + ald_timer_ocn_start(hperh, ch); } /** @@ -2304,9 +2271,9 @@ void timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_stop(hperh, ch); + ald_timer_ocn_stop(hperh, ch); } /** @@ -2319,9 +2286,9 @@ void timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_start_by_it(hperh, ch); + ald_timer_ocn_start_by_it(hperh, ch); } /** @@ -2334,9 +2301,9 @@ void timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_stop_by_it(hperh, ch); + ald_timer_ocn_stop_by_it(hperh, ch); } /** * @} @@ -2371,14 +2338,14 @@ void timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @param hperh: TIMER handle * @param config: TIMER Output Compare configuration structure * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch) +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); assert_param(IS_TIMER_OC_MODE(config->oc_mode)); @@ -2389,24 +2356,24 @@ ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *con switch (ch) { - case TIMER_CHANNEL_1: - timer_oc1_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_2: - timer_oc2_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_3: - timer_oc3_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_3: + timer_oc3_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_4: - timer_oc4_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_4: + timer_oc4_set_config(hperh->perh, config); + break; - default: - break; + default: + break; } hperh->state = TIMER_STATE_READY; @@ -2427,7 +2394,7 @@ ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *con * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch) +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); assert_param(IS_TIMER_IC_POLARITY(config->polarity)); @@ -2440,28 +2407,28 @@ ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *con switch (ch) { - case TIMER_CHANNEL_1: - timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); - break; - - case TIMER_CHANNEL_2: - timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); - break; - - case TIMER_CHANNEL_3: - timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); - break; - - case TIMER_CHANNEL_4: - timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); - break; - - default: - break; + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); + break; + + case TIMER_CHANNEL_3: + timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); + break; + + case TIMER_CHANNEL_4: + timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); + break; + + default: + break; } hperh->state = TIMER_STATE_READY; @@ -2484,7 +2451,7 @@ ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *con * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, +ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, timer_channel_t ch_out, timer_channel_t ch_in) { timer_oc_init_t tmp; @@ -2514,33 +2481,36 @@ ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pul switch (ch_out) { - case TIMER_CHANNEL_1: - timer_oc1_set_config(hperh->perh, &tmp); - break; - case TIMER_CHANNEL_2: - timer_oc2_set_config(hperh->perh, &tmp); - break; - default: - break; + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, &tmp); + break; + + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, &tmp); + break; + + default: + break; } switch (ch_in) { - case TIMER_CHANNEL_1: - timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); - CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_CHANNEL_2: - timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); - CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); - break; - default: - break; + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + default: + break; } hperh->state = TIMER_STATE_READY; @@ -2561,7 +2531,7 @@ ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pul * @arg TIMER_CHANNEL_4: TIMER Channel 4 * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch) +ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); assert_param(IS_FUNC_STATE(config->state)); @@ -2582,26 +2552,26 @@ ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_ switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); - break; - - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); - break; - - case TIMER_CHANNEL_3: - assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); - break; - - case TIMER_CHANNEL_4: - assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); - break; - - default: - break; + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); + break; + + case TIMER_CHANNEL_3: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); + break; + + case TIMER_CHANNEL_4: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); + break; + + default: + break; } return OK; @@ -2614,7 +2584,7 @@ ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_ * contains the clock source information for the TIMER peripheral. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config) +ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); @@ -2628,60 +2598,61 @@ ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config switch (config->source) { - case TIMER_SRC_INTER: - CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); - break; - - case TIMER_SRC_ETRMODE1: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ETRMODE2: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); - break; - - case TIMER_SRC_TI1: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_TI2: - timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_TI1ED: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR0: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR1: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR2: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR3: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - default: - break; + case TIMER_SRC_INTER: + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + break; + + case TIMER_SRC_ETRMODE1: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ETRMODE2: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); + break; + + case TIMER_SRC_TI1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI1ED: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR0: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR1: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR2: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR3: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + default: + break; } hperh->state = TIMER_STATE_READY; @@ -2701,7 +2672,7 @@ ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config * pins are connected to the TI1 input (XOR combination) * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) +ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); @@ -2718,7 +2689,7 @@ ald_status_t timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config) +ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_SLAVE_MODE(config->mode)); @@ -2731,8 +2702,8 @@ ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t hperh->state = TIMER_STATE_BUSY; timer_slave_set_config(hperh, config); - timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); - timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); hperh->state = TIMER_STATE_READY; __UNLOCK(hperh); @@ -2748,7 +2719,7 @@ ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config) +ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_SLAVE_MODE(config->mode)); @@ -2761,8 +2732,8 @@ ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_co hperh->state = TIMER_STATE_BUSY; timer_slave_set_config(hperh, config); - timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); - timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); hperh->state = TIMER_STATE_READY; __UNLOCK(hperh); @@ -2775,7 +2746,7 @@ ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_co * @param event: specifies the event source. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_generate_event(timer_handle_t *hperh, timer_event_source_t event) +ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_EVENT_SOURCE(event)); @@ -2800,7 +2771,7 @@ ald_status_t timer_generate_event(timer_handle_t *hperh, timer_event_source_t ev * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected * @retval Captured value */ -uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) +uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) { uint32_t tmp; @@ -2809,20 +2780,24 @@ uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) switch (ch) { - case TIMER_CHANNEL_1: - tmp = hperh->perh->CCVAL1; - break; - case TIMER_CHANNEL_2: - tmp = hperh->perh->CCVAL2; - break; - case TIMER_CHANNEL_3: - tmp = hperh->perh->CCVAL3; - break; - case TIMER_CHANNEL_4: - tmp = hperh->perh->CCVAL4; - break; - default: - break; + case TIMER_CHANNEL_1: + tmp = hperh->perh->CCVAL1; + break; + + case TIMER_CHANNEL_2: + tmp = hperh->perh->CCVAL2; + break; + + case TIMER_CHANNEL_3: + tmp = hperh->perh->CCVAL3; + break; + + case TIMER_CHANNEL_4: + tmp = hperh->perh->CCVAL4; + break; + + default: + break; } hperh->state = TIMER_STATE_READY; @@ -2842,7 +2817,7 @@ uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected * @retval None */ -void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch) +void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); assert_param(IS_TIMER_OC_MODE(mode)); @@ -2850,20 +2825,24 @@ void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_ch switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); - break; - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); - break; - case TIMER_CHANNEL_3: - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); - break; - case TIMER_CHANNEL_4: - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); - break; - default: - break; + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); + break; + + case TIMER_CHANNEL_3: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); + break; + + case TIMER_CHANNEL_4: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); + break; + + default: + break; } return; @@ -2875,7 +2854,7 @@ void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_ch * @param config: Parameters of the channel. * @retval None */ -void timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config) +void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config) { uint32_t cm1, cm2, cce; @@ -2932,7 +2911,7 @@ void timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t * * @arg DISABLE: Commutation event source is set by software using the COMG bit * @retval None */ -void timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) +void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) { assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); assert_param(IS_TIMER_TS(ts)); @@ -2961,10 +2940,10 @@ void timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t tr * @arg DISABLE: Commutation event source is set by software using the COMG bit * @retval None */ -void timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) +void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) { - timer_com_event_config(hperh, ts, trgi); - timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); + ald_timer_com_event_config(hperh, ts, trgi); + ald_timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); } /** @@ -2973,7 +2952,7 @@ void timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t * @param config: Pointer to the timer_break_dead_timere_t structure. * @retval None */ -void timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config) +void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config) { uint32_t tmp; @@ -3006,7 +2985,7 @@ void timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t * @param config: Pointer to the timer_master_config_t structure. * @retval None */ -void timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config) +void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); @@ -3025,14 +3004,14 @@ void timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *conf * @param hperh: TIMER handle * @retval None */ -void timer_irq_handle(timer_handle_t *hperh) +void ald_timer_irq_handler(timer_handle_t *hperh) { uint32_t reg = hperh->perh->IFM; /* Capture or compare 1 event */ if (READ_BIT(reg, TIMER_FLAG_CC1)) { - timer_clear_flag_status(hperh, TIMER_FLAG_CC1); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC1); hperh->ch = TIMER_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3041,20 +3020,22 @@ void timer_irq_handle(timer_handle_t *hperh) if (hperh->capture_cbk) hperh->capture_cbk(hperh); } - else /* Output compare event */ + else /* Output compare event */ { if (hperh->delay_elapse_cbk) hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) hperh->pwm_pulse_finish_cbk(hperh); } hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; } + /* Capture or compare 2 event */ if (READ_BIT(reg, TIMER_FLAG_CC2)) { - timer_clear_flag_status(hperh, TIMER_FLAG_CC2); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC2); hperh->ch = TIMER_ACTIVE_CHANNEL_2; /* Input capture event */ @@ -3063,20 +3044,22 @@ void timer_irq_handle(timer_handle_t *hperh) if (hperh->capture_cbk) hperh->capture_cbk(hperh); } - else /* Output compare event */ + else /* Output compare event */ { if (hperh->delay_elapse_cbk) hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) hperh->pwm_pulse_finish_cbk(hperh); } hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; } + /* Capture or compare 3 event */ if (READ_BIT(reg, TIMER_FLAG_CC3)) { - timer_clear_flag_status(hperh, TIMER_FLAG_CC3); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC3); hperh->ch = TIMER_ACTIVE_CHANNEL_3; /* Input capture event */ @@ -3085,20 +3068,22 @@ void timer_irq_handle(timer_handle_t *hperh) if (hperh->capture_cbk) hperh->capture_cbk(hperh); } - else /* Output compare event */ + else /* Output compare event */ { if (hperh->delay_elapse_cbk) hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) hperh->pwm_pulse_finish_cbk(hperh); } hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; } + /* Capture or compare 4 event */ if (READ_BIT(reg, TIMER_FLAG_CC4)) { - timer_clear_flag_status(hperh, TIMER_FLAG_CC4); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC4); hperh->ch = TIMER_ACTIVE_CHANNEL_4; /* Input capture event */ @@ -3107,10 +3092,11 @@ void timer_irq_handle(timer_handle_t *hperh) if (hperh->capture_cbk) hperh->capture_cbk(hperh); } - else /* Output compare event */ + else /* Output compare event */ { if (hperh->delay_elapse_cbk) hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) hperh->pwm_pulse_finish_cbk(hperh); } @@ -3121,7 +3107,7 @@ void timer_irq_handle(timer_handle_t *hperh) /* TIMER Update event */ if (READ_BIT(reg, TIMER_FLAG_UPDATE)) { - timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); if (hperh->period_elapse_cbk) hperh->period_elapse_cbk(hperh); @@ -3130,7 +3116,7 @@ void timer_irq_handle(timer_handle_t *hperh) /* TIMER Break input event */ if (READ_BIT(reg, TIMER_FLAG_BREAK)) { - timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); if (hperh->break_cbk) hperh->break_cbk(hperh); @@ -3139,7 +3125,7 @@ void timer_irq_handle(timer_handle_t *hperh) /* TIMER Trigger detection event */ if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) { - timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); if (hperh->trigger_cbk) hperh->trigger_cbk(hperh); @@ -3148,7 +3134,7 @@ void timer_irq_handle(timer_handle_t *hperh) /* TIMER commutation event */ if (READ_BIT(reg, TIMER_FLAG_COM)) { - timer_clear_flag_status(hperh, TIMER_FLAG_COM); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_COM); if (hperh->com_cbk) hperh->com_cbk(hperh); @@ -3164,7 +3150,7 @@ void timer_irq_handle(timer_handle_t *hperh) * @param state: New state of the specified DMA request. * @retval None */ -void timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state) +void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_DMA_REQ(req)); @@ -3189,7 +3175,7 @@ void timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_ * @arg DISABLE * @retval None */ -void timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state) +void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_IT(it)); @@ -3212,7 +3198,7 @@ void timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t st * - 0: RESET * - 1: SET */ -it_status_t timer_get_it_status(timer_handle_t *hperh, timer_it_t it) +it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_IT(it)); @@ -3232,7 +3218,7 @@ it_status_t timer_get_it_status(timer_handle_t *hperh, timer_it_t it) * - 0: RESET * - 1: SET */ -flag_status_t timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) +flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_FLAG(flag)); @@ -3250,7 +3236,7 @@ flag_status_t timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) * This parameter can be one of the @ref timer_flag_t. * @retval None */ -void timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) +void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_FLAG(flag)); @@ -3282,7 +3268,7 @@ void timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) * @param hperh: TIMER handle * @retval TIMER peripheral state */ -timer_state_t timer_get_state(timer_handle_t *hperh) +timer_state_t ald_timer_get_state(timer_handle_t *hperh) { return hperh->state; } @@ -3359,6 +3345,7 @@ void timer_dma_error(void *arg) timer_handle_t *hperh = (timer_handle_t *)arg; hperh->state = TIMER_STATE_READY; + if (hperh->error_cbk) hperh->error_cbk(hperh); @@ -3525,11 +3512,11 @@ static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf * @brief Enables or disables the TIMER Capture Compare Channel x. * @param TIMERx: Select the TIMER peripheral * @param ch: specifies the TIMER Channel - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 - * @arg TIMER_CHANNEL_2: TIMER Channel 2 - * @arg TIMER_CHANNEL_3: TIMER Channel 3 - * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 * @param state: specifies the TIMER Channel CCxE bit new state. * @retval None */ @@ -3540,34 +3527,34 @@ static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, typ switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); - break; + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); + break; - case TIMER_CHANNEL_2: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); - break; + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); + break; - case TIMER_CHANNEL_3: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); - break; + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); + break; - case TIMER_CHANNEL_4: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); - break; + case TIMER_CHANNEL_4: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); + break; - default: - break; + default: + break; } } /** * @brief Enables or disables the TIMER Capture Compare Channel xN. * @param TIMERx: Select the TIMER peripheral * @param ch: specifies the TIMER Channel - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 - * @arg TIMER_CHANNEL_2: TIMER Channel 2 - * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 * @param state: specifies the TIMER Channel CCxNE bit new state. * @retval None */ @@ -3575,20 +3562,20 @@ static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, ty { switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); - break; + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); + break; - case TIMER_CHANNEL_2: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); - break; + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); + break; - case TIMER_CHANNEL_3: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); - break; + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); + break; - default: - break; + default: + break; } } @@ -3608,8 +3595,7 @@ static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); return; } @@ -3625,8 +3611,8 @@ static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) { MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + return; } @@ -3646,8 +3632,8 @@ static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + return; } @@ -3663,8 +3649,7 @@ static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) { MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); return; } @@ -3683,8 +3668,7 @@ static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC3POL_POS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC3NPOL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS); return; } @@ -3704,8 +3688,7 @@ static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC4POL_POS); - + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS); return; } @@ -3741,27 +3724,78 @@ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t * switch (config->input) { - case TIMER_TS_ETRF: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - break; + case TIMER_TS_ETRF: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + break; - case TIMER_TS_TI1F_ED: - CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); - break; + case TIMER_TS_TI1F_ED: + CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); + break; - case TIMER_TS_TI1FP1: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - break; + case TIMER_TS_TI1FP1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; - case TIMER_TS_TI2FP2: - timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - break; + case TIMER_TS_TI2FP2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; - default: - break; + default: + break; } } + +#ifdef ALD_DMA + +/** + * @brief Timer DMA msel signal configuration + * @param hperh: pointer to a timer_handle_t structure that contains + * the configuration information for TIMER module. + * @param config: DMA configuration structure + * @retval None + */ +static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config) +{ +#if defined (ES32F065x) + + if (hperh == AD16C4T0) + config->msel = DMA_MSEL_TIMER0; + + if (hperh == GP16C4T0) + config->msel = DMA_MSEL_TIMER6; + +#elif defined (ES32F033x) || defined (ES32F093x) + + if (hperh == GP16C4T0) + config->msel = DMA_MSEL_TIMER0; + + if (hperh == GP16C4T1) + config->msel = DMA_MSEL_TIMER6; + +#endif + + if (hperh == GP16C2T0) + config->msel = DMA_MSEL_TIMER2; + + if (hperh == GP16C2T1) + config->msel = DMA_MSEL_TIMER3; + + if (hperh == BS16T0) + config->msel = DMA_MSEL_TIMER1; + + if (hperh == BS16T1) + config->msel = DMA_MSEL_TIMER4; + + if (hperh == BS16T2) + config->msel = DMA_MSEL_TIMER5; + + if (hperh == BS16T3) + config->msel = DMA_MSEL_TIMER7; +} + +#endif + /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c new file mode 100644 index 0000000000000000000000000000000000000000..85539e815a0131bfe4fc4ace236de042e51dbc2b --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -0,0 +1,314 @@ +/** + ********************************************************************************* + * + * @file ald_trng.c + * @brief TRNG module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_trng.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup TRNG TRNG + * @brief TRNG module driver + * @{ + */ +#ifdef ALD_TRNG + +/** @addtogroup CRYPT_Private_Functions CRYPT Private Functions + * @{ + */ +void trng_reset(trng_handle_t *hperh); +/** + * @} + */ + +/** @defgroup TRNG_Public_Functions TRNG Public Functions + * @{ + */ + +/** @addtogroup TRNG_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + ============================================================================== + ##### Initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize the TRNG: + (+) This parameters can be configured: + (++) Word Width + (++) Seed Type + (++) Seed + (++) Start Time + (++) Adjust parameter + + @endverbatim + * @{ + */ + + +/** + * @brief Initializes the TRNG according to the specified + * parameters in the trng_init_t. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_trng_init(trng_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width)); + assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type)); + assert_param(IS_TRNG_ADJC(hperh->init.adjc)); + + __LOCK(hperh); + trng_reset(hperh); + + if (hperh->state == TRNG_STATE_RESET) + __UNLOCK(hperh); + + tmp = TRNG->CR; + + if (hperh->init.adjc == 0) + tmp = (0 << TRNG_CR_ADJM_POS); + else + tmp = (1 << TRNG_CR_ADJM_POS); + + tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) | + (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) | + (hperh->init.posten << TRNG_CR_POSTEN_MSK)); + + TRNG->CR = tmp; + + WRITE_REG(TRNG->SEED, hperh->init.seed); + MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS); + + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return OK; +} +/** + * @} + */ + +/** @addtogroup TRNG_Public_Functions_Group2 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) ald_trng_get_result() API can Get the result. + (+) ald_trng_interrupt_config() API can be helpful to configure TRNG interrupt source. + (+) ald_trng_get_it_status() API can get the status of interrupt source. + (+) ald_trng_get_status() API can get the status of SR register. + (+) ald_trng_get_flag_status() API can get the status of interrupt flag. + (+) ald_trng_clear_flag_status() API can clear interrupt flag. + + @endverbatim + * @{ + */ + +/** + * @brief Get the result. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval The resultl + */ +uint32_t ald_trng_get_result(trng_handle_t *hperh) +{ + hperh->state = TRNG_STATE_READY; + hperh->data = hperh->perh->DR; + return (uint32_t)hperh->perh->DR; +} + +/** + * @brief Enable/disable the specified interrupts. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param it: Specifies the interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref trng_it_t. + * @param state: New state of the specified interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state) +{ + assert_param(IS_TRNG_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + SET_BIT(hperh->perh->IER, it); + else + CLEAR_BIT(hperh->perh->IER, it); + + return; +} + +/** + * @brief Get the status of SR register. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param status: Specifies the TRNG status type. + * This parameter can be one of the @ref trng_status_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status) +{ + assert_param(IS_TRNG_STATUS(status)); + + if (READ_BIT(hperh->perh->SR, status)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt source. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param it: Specifies the interrupt source. + * This parameter can be one of the @ref trng_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it) +{ + assert_param(IS_TRNG_IT(it)); + + if (READ_BIT(hperh->perh->IER, it)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt flag. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param flag: Specifies the interrupt flag. + * This parameter can be one of the @ref trng_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag) +{ + assert_param(IS_TRNG_FLAG(flag)); + + if (READ_BIT(hperh->perh->IFR, flag)) + return SET; + + return RESET; +} + +/** + * @brief Clear the interrupt flag. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param flag: Specifies the interrupt flag. + * This parameter can be one of the @ref trng_flag_t. + * @retval None + */ +void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag) +{ + assert_param(IS_TRNG_FLAG(flag)); + WRITE_REG(hperh->perh->IFCR, flag); + + return; +} + +/** + * @brief Reset the TRNG peripheral. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval None + */ +void trng_reset(trng_handle_t *hperh) +{ + TRNG->CR = 0; + TRNG->SEED = 0; + TRNG->CFGR = 0x1FF0707; + TRNG->IER = 0; + TRNG->IFCR = 0xFFFFFFFF; + + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return; +} + +/** + * @brief This function handles TRNG interrupt request. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval None + */ +void ald_trng_irq_handler(trng_handle_t *hperh) +{ + if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) + { + hperh->state = TRNG_STATE_ERROR; + ald_trng_clear_flag_status(hperh, TRNG_IF_SERR); + + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); + + return; + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) + { + hperh->data = hperh->perh->DR; + hperh->state = TRNG_STATE_READY; + ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD); + + if (hperh->trng_cplt_cbk) + hperh->trng_cplt_cbk(hperh); + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) + { + hperh->state = TRNG_STATE_BUSY; + ald_trng_clear_flag_status(hperh, TRNG_IF_START); + + if (hperh->init_cplt_cbk) + hperh->init_cplt_cbk(hperh); + } +} + +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_TRNG */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c new file mode 100644 index 0000000000000000000000000000000000000000..b31d5084cb5e0a7b114a0553bfdadcb7667c9de5 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c @@ -0,0 +1,223 @@ +/** + ********************************************************************************* + * + * @file ald_tsense.c + * @brief TSENSE module driver. + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_tsense.h" +#include "ald_bkpc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup TSENSE TSENSE + * @brief TSENSE module driver + * @{ + */ +#ifdef ALD_TSENSE + + +/** @defgroup TSENSE_Private_Variables TSENSE Private Variables + * @{ + */ +tsense_cbk __tsense_cbk; +/** + * @} + */ + +/** @defgroup TSENSE_Public_Functions TSENSE Public Functions + * @{ + */ + +/** @addtogroup TSENSE_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + ============================================================================== + ##### Initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize the TSENSE: + (+) This parameters can be configured: + (++) Update Cycle + (++) Output Mode + (++) Perscaler + (+) Select TSENSE source clock(default LOSC) + + @endverbatim + * @{ + */ + +/** + * @brief Initializes the TSENSE according to the specified + * parameters in the tsense_init_t. + * @param init: Pointer to a tsense_init_t structure that contains + * the configuration information. + * @retval None + */ +void ald_tsense_init(tsense_init_t *init) +{ + assert_param(IS_TSENSE_UPDATE_CYCLE(init->cycle)); + assert_param(IS_TSENSE_OUTPUT_MODE(init->mode)); + + TSENSE_UNLOCK(); + TSENSE->CR = 0; + + MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, init->cycle << TSENSE_CR_TSU_POSS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, init->mode << TSENSE_CR_TOM_POSS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_CTN_MSK, init->ctn << TSENSE_CR_CTN_POS); + MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, init->psc << TSENSE_PSR_PRS_POSS); + TSENSE_LOCK(); + + return; +} + +/** + * @brief Configure the TSENSE source. + * @param sel: TSENSE source type. + * @retval None + */ +void ald_tsense_source_select(tsense_source_sel_t sel) +{ + assert_param(IS_TSENSE_SOURCE_SEL(sel)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS); + + if (sel == TSENSE_SOURCE_LOSC) + { + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); + } + else if (sel == TSENSE_SOURCE_LRC) + { + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); + } + else + { + ; /* do nothing */ + } + + BKPC_LOCK(); + return; +} +/** + * @} + */ + +/** @addtogroup TSENSE_Public_Functions_Group2 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) ald_tsense_get_value() API can get the current temperature. + (+) ald_tsense_get_value_by_it() API can get the current temperature by interrupt. + (+) ald_tsense_irq_handler() API can handle the interrupt request. + + @endverbatim + * @{ + */ + +/** + * @brief Get the current temperature + * @param tsense: The value of current temperature. + * @retval ALD status: + * @arg @ref OK The value is valid + * @arg @ref ERROR The value is invalid + */ +ald_status_t ald_tsense_get_value(uint16_t *tsense) +{ + uint32_t tmp = 0; + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000)); + + if (tmp >= 1000000) + return TIMEOUT; + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); + + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) + return ERROR; + + *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS); + return OK; +} + +/** + * @brief Get the current temperature by interrupt + * @param cbk: The callback function + * @retval None + */ +void ald_tsense_get_value_by_it(tsense_cbk cbk) +{ + __tsense_cbk = cbk; + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + return; +} + +/** + * @brief This function handles TSENSE interrupt request. + * @retval None + */ +void ald_tsense_irq_handler(void) +{ + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); + + if (__tsense_cbk == NULL) + return; + + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) + { + __tsense_cbk(0, ERROR); + return; + } + + __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK); + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); + return; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_TSENSE */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c similarity index 82% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c index 32cdbe143fd1c0b0903441cc9df439428ab10a61..ee0751ad8d07847a8406b11a7f8f0036fae5036a 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -32,19 +32,19 @@ (##) UART pins configuration: (+++) Enable the clock for the UART GPIOs. (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input). - (##) NVIC configuration if you need to use interrupt process (uart_send_by_it() - and uart_recv_by_it() APIs): + (##) NVIC configuration if you need to use interrupt process (ald_uart_send_by_it() + and ald_uart_recv_by_it() APIs): (+++) Configure the uart interrupt priority. (+++) Enable the NVIC UART IRQ handle. - (##) DMA Configuration if you need to use DMA process (uart_send_by_dma() - and uart_recv_by_dma() APIs): + (##) DMA Configuration if you need to use DMA process (ald_uart_send_by_dma() + and ald_uart_recv_by_dma() APIs): (+++) Select the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware flow control and Mode(Receiver/Transmitter) in the hperh Init structure. - (#) Initialize the UART registers by calling the uart_init() API. + (#) Initialize the UART registers by calling the ald_uart_init() API. [..] Three operation modes are available within this driver: @@ -52,16 +52,16 @@ *** Polling mode IO operation *** ================================= [..] - (+) Send an amount of data in blocking mode using uart_send() - (+) Receive an amount of data in blocking mode using uart_recv() + (+) Send an amount of data in blocking mode using ald_uart_send() + (+) Receive an amount of data in blocking mode using ald_uart_recv() *** Interrupt mode IO operation *** =================================== [..] - (+) Send an amount of data in non blocking mode using uart_send_by_it() + (+) Send an amount of data in non blocking mode using ald_uart_send_by_it() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode using uart_recv_by_it() + (+) Receive an amount of data in non blocking mode using ald_uart_recv_by_it() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk() function is executed and user can @@ -70,17 +70,17 @@ *** DMA mode IO operation *** ============================== [..] - (+) Send an amount of data in non blocking mode (DMA) using uart_send_by_dma() + (+) Send an amount of data in non blocking mode (DMA) using ald_uart_send_by_dma() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using uart_recv_by_dma() + (+) Receive an amount of data in non blocking mode (DMA) using ald_uart_recv_by_dma() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk() function is executed and user can add his own code by customization of function pointer hperh->error_cbk() - (+) Pause the DMA Transfer using uart_dma_pause() - (+) Resume the DMA Transfer using uart_dma_resume() - (+) Stop the DMA Transfer using uart_dma_stop() + (+) Pause the DMA Transfer using ald_uart_dma_pause() + (+) Resume the DMA Transfer using ald_uart_dma_resume() + (+) Stop the DMA Transfer using ald_uart_dma_stop() @endverbatim ****************************************************************************** @@ -115,10 +115,10 @@ static void uart_dma_send_cplt(void *arg) uart_handle_t *hperh = (uart_handle_t *)arg; if (hperh->state == UART_STATE_BUSY_TX) - uart_dma_req_config(hperh, DISABLE); + ald_uart_dma_req_config(hperh, DISABLE); hperh->tx_count = 0; - uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); return; } @@ -132,7 +132,7 @@ static void uart_dma_recv_cplt(void *arg) uart_handle_t *hperh = (uart_handle_t *)arg; if (hperh->state == UART_STATE_BUSY_RX) - uart_dma_req_config(hperh, DISABLE); + ald_uart_dma_req_config(hperh, DISABLE); hperh->rx_count = 0; CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); @@ -156,7 +156,7 @@ static void uart_dma_error(void *arg) hperh->tx_count = 0; hperh->state = UART_STATE_READY; hperh->err_code |= UART_ERROR_DMA; - uart_dma_req_config(hperh, DISABLE); + ald_uart_dma_req_config(hperh, DISABLE); if (hperh->error_cbk) hperh->error_cbk(hperh); @@ -180,12 +180,12 @@ static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, fla if (timeout == 0) return ERROR; - tick = __get_tick(); + tick = ald_get_tick(); /* Waiting for flag */ - while ((uart_get_status(hperh, flag)) != status) + while ((ald_uart_get_status(hperh, flag)) != status) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) return TIMEOUT; } @@ -206,9 +206,9 @@ static ald_status_t __uart_send_by_it(uart_handle_t *hperh) if (--hperh->tx_count == 0) { - uart_clear_flag_status(hperh, UART_IF_TC); - uart_interrupt_config(hperh, UART_IT_TXS, DISABLE); - uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + ald_uart_clear_flag_status(hperh, UART_IF_TC); + ald_uart_interrupt_config(hperh, UART_IT_TXS, DISABLE); + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); } return OK; @@ -224,8 +224,9 @@ static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh) if (!(READ_BIT(hperh->perh->SR, UART_SR_TEM_MSK))) return OK; - uart_interrupt_config(hperh, UART_IT_TC, DISABLE); + ald_uart_interrupt_config(hperh, UART_IT_TC, DISABLE); CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + if (hperh->tx_cplt_cbk) hperh->tx_cplt_cbk(hperh); @@ -246,7 +247,7 @@ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) if (--hperh->rx_count == 0) { - uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE); + ald_uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE); CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); if (hperh->rx_cplt_cbk) @@ -280,11 +281,11 @@ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) (++) Parity (++) Hardware flow control (+) For RS485 mode, user also need configure some parameters by - uart_rs485_config(): + ald_uart_rs485_config(): (++) Enable/disable normal point mode - (++) Enable/disable auto-direction - (++) Enable/disable address detection invert - (++) Enable/disable address for compare + (++) Enable/disable auto-direction + (++) Enable/disable address detection invert + (++) Enable/disable address for compare @endverbatim * @{ @@ -296,7 +297,7 @@ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) * the configuration information for the specified uart module. * @retval None */ -void uart_reset(uart_handle_t *hperh) +void ald_uart_reset(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); @@ -322,7 +323,7 @@ void uart_reset(uart_handle_t *hperh) * the configuration information for the specified UART module. * @retval None */ -void uart_init(uart_handle_t *hperh) +void ald_uart_init(uart_handle_t *hperh) { uint32_t tmp; @@ -334,7 +335,7 @@ void uart_init(uart_handle_t *hperh) assert_param(IS_UART_MODE(hperh->init.mode)); assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - uart_reset(hperh); + ald_uart_reset(hperh); tmp = READ_REG(hperh->perh->LCR); MODIFY_REG(tmp, UART_LCR_DLS_MSK, hperh->init.word_length << UART_LCR_DLS_POSS); @@ -344,7 +345,7 @@ void uart_init(uart_handle_t *hperh) WRITE_REG(hperh->perh->LCR, tmp); MODIFY_REG(hperh->perh->MCR, UART_MCR_AFCEN_MSK, hperh->init.fctl << UART_MCR_AFCEN_POS); SET_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); - WRITE_REG(hperh->perh->BRR, cmu_get_pclk1_clock() / hperh->init.baud); + WRITE_REG(hperh->perh->BRR, ald_cmu_get_pclk1_clock() / hperh->init.baud); CLEAR_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); @@ -366,6 +367,7 @@ void uart_init(uart_handle_t *hperh) if (hperh->init.fctl) SET_BIT(hperh->perh->MCR, UART_MCR_RTSCTRL_MSK); + if (hperh->init.mode == UART_MODE_IrDA) SET_BIT(hperh->perh->LCR, UART_LCR_RXINV_MSK); @@ -382,7 +384,7 @@ void uart_init(uart_handle_t *hperh) * @param config: Specifies the RS485 parameters. * @retval None */ -void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) +void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_FUNC_STATE(config->normal)); @@ -424,20 +426,20 @@ void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) a communication error is detected. (#) Blocking mode APIs are: - (++) uart_send() - (++) uart_recv() + (++) ald_uart_send() + (++) ald_uart_recv() (#) Non Blocking mode APIs with Interrupt are: - (++) uart_send_by_it() - (++) uart_recv_by_it() - (++) uart_irq_handle() + (++) ald_uart_send_by_it() + (++) ald_uart_recv_by_it() + (++) ald_uart_irq_handler() (#) Non Blocking mode functions with DMA are: - (++) uart_send_by_dma() - (++) uart_recv_by_dma() - (++) uart_dma_pause() - (++) uart_dma_resume() - (++) uart_dma_stop() + (++) ald_uart_send_by_dma() + (++) ald_uart_recv_by_dma() + (++) ald_uart_dma_pause() + (++) ald_uart_dma_resume() + (++) ald_uart_dma_stop() (#) A set of transfer complete callbacks are provided in non blocking mode: (++) hperh->tx_cplt_cbk() @@ -456,7 +458,7 @@ void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { assert_param(IS_UART_ALL(hperh->perh)); @@ -506,7 +508,7 @@ ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32 * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { assert_param(IS_UART_ALL(hperh->perh)); @@ -549,7 +551,7 @@ ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32 * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) { assert_param(IS_UART_ALL(hperh->perh)); @@ -568,8 +570,8 @@ ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) SET_BIT(hperh->state, UART_STATE_TX_MASK); __UNLOCK(hperh); - if (((uart_get_status(hperh, UART_STATUS_TBEM)) == SET) - && ((uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) + if (((ald_uart_get_status(hperh, UART_STATUS_TBEM)) == SET) + && ((ald_uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) { WRITE_REG(hperh->perh->TBR, (*hperh->tx_buf++ & 0xFF)); --hperh->tx_count; @@ -577,11 +579,11 @@ ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) if (hperh->tx_count == 0) { - uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); return OK; } - uart_interrupt_config(hperh, UART_IT_TXS, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_TXS, ENABLE); return OK; } @@ -592,7 +594,7 @@ ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) * @param size: Amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) { assert_param(IS_UART_ALL(hperh->perh)); @@ -610,7 +612,7 @@ ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) SET_BIT(hperh->state, UART_STATE_RX_MASK); __UNLOCK(hperh); - uart_interrupt_config(hperh, UART_IT_RXRD, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_RXRD, ENABLE); return OK; } #ifdef ALD_DMA @@ -622,7 +624,7 @@ ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) * @param channel: DMA channel as UART transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { assert_param(IS_UART_ALL(hperh->perh)); @@ -648,7 +650,7 @@ ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, hperh->hdmatx.err_cbk = uart_dma_error; hperh->hdmatx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->TBR; hperh->hdmatx.config.size = size; @@ -673,13 +675,13 @@ ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, else if (hperh->perh == UART3) hperh->hdmatx.config.msel = DMA_MSEL_UART3; else - ; /* do nothing */ + ; /* do nothing */ - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); __UNLOCK(hperh); - uart_clear_flag_status(hperh, UART_IF_TC); - uart_dma_req_config(hperh, ENABLE); + ald_uart_clear_flag_status(hperh, UART_IF_TC); + ald_uart_dma_req_config(hperh, ENABLE); return OK; } @@ -692,7 +694,7 @@ ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, * @param channel: DMA channel as UART receive * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { assert_param(IS_UART_ALL(hperh->perh)); @@ -717,7 +719,7 @@ ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, hperh->hdmarx.err_cbk = uart_dma_error; hperh->hdmarx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->RBR; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -744,9 +746,9 @@ ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, else ; - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); __UNLOCK(hperh); - uart_dma_req_config(hperh, ENABLE); + ald_uart_dma_req_config(hperh, ENABLE); return OK; } @@ -756,11 +758,11 @@ ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, * @param hperh: Pointer to a uart_handle_t structure. * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_dma_pause(uart_handle_t *hperh) +ald_status_t ald_uart_dma_pause(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); - uart_dma_req_config(hperh, DISABLE); + ald_uart_dma_req_config(hperh, DISABLE); return OK; } @@ -769,11 +771,11 @@ ald_status_t uart_dma_pause(uart_handle_t *hperh) * @param hperh: Pointer to a uart_handle_t structure. * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_dma_resume(uart_handle_t *hperh) +ald_status_t ald_uart_dma_resume(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); - uart_dma_req_config(hperh, ENABLE); + ald_uart_dma_req_config(hperh, ENABLE); return OK; } @@ -782,11 +784,11 @@ ald_status_t uart_dma_resume(uart_handle_t *hperh) * @param hperh: Pointer to a uart_handle_t structure. * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_dma_stop(uart_handle_t *hperh) +ald_status_t ald_uart_dma_stop(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); - uart_dma_req_config(hperh, DISABLE); + ald_uart_dma_req_config(hperh, DISABLE); hperh->state = UART_STATE_READY; return OK; } @@ -797,40 +799,40 @@ ald_status_t uart_dma_stop(uart_handle_t *hperh) * @param hperh: Pointer to a uart_handle_t structure. * @retval None */ -void uart_irq_handle(uart_handle_t *hperh) +void ald_uart_irq_handler(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); /* Handle parity error */ - if ((uart_get_status(hperh, UART_STATUS_PE)) != RESET) + if ((ald_uart_get_status(hperh, UART_STATUS_PE)) != RESET) hperh->err_code |= UART_ERROR_PE; /* Handle frame error */ - if ((uart_get_status(hperh, UART_STATUS_FE)) != RESET) + if ((ald_uart_get_status(hperh, UART_STATUS_FE)) != RESET) hperh->err_code |= UART_ERROR_FE; /* Handle overflow error */ - if ((uart_get_status(hperh, UART_STATUS_OE)) != RESET) + if ((ald_uart_get_status(hperh, UART_STATUS_OE)) != RESET) hperh->err_code |= UART_ERROR_ORE; /* Receive */ - if ((uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) { - uart_clear_flag_status(hperh, UART_IF_RXRD); + ald_uart_clear_flag_status(hperh, UART_IF_RXRD); __uart_recv_by_it(hperh); } - /* Transmite */ - if ((uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) + /* Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) { - uart_clear_flag_status(hperh, UART_IF_TXS); + ald_uart_clear_flag_status(hperh, UART_IF_TXS); __uart_send_by_it(hperh); } - /* End Transmite */ - if ((uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) + /* End Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) { - uart_clear_flag_status(hperh, UART_IF_TC); + ald_uart_clear_flag_status(hperh, UART_IF_TC); __uart_end_send_by_it(hperh); } @@ -856,18 +858,18 @@ void uart_irq_handle(uart_handle_t *hperh) ============================================================================== [..] This subsection provides a set of functions allowing to control the UART: - (+) uart_interrupt_config() API can be helpful to configure UART interrupt source. - (+) uart_dma_req_config() API can be helpful to configure UART DMA request. - (+) uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters. - (+) uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters. - (+) uart_lin_send_break() API can send a frame of break in LIN mode. - (+) uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame. - (+) uart_auto_baud_config() API can be helpful to configure detection data mode. - (+) uart_get_it_status() API can get the status of interrupt source. - (+) uart_get_status() API can get the status of UART_SR register. - (+) uart_get_flag_status() API can get the status of UART flag. - (+) uart_get_mask_flag_status() API can get status os flag and interrupt source. - (+) uart_clear_flag_status() API can clear UART flag. + (+) ald_uart_interrupt_config() API can be helpful to configure UART interrupt source. + (+) ald_uart_dma_req_config() API can be helpful to configure UART DMA request. + (+) ald_uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters. + (+) ald_uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters. + (+) ald_uart_lin_send_break() API can send a frame of break in LIN mode. + (+) ald_uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame. + (+) ald_uart_auto_baud_config() API can be helpful to configure detection data mode. + (+) ald_uart_get_it_status() API can get the status of interrupt source. + (+) ald_uart_get_status() API can get the status of UART_SR register. + (+) ald_uart_get_flag_status() API can get the status of UART flag. + (+) ald_uart_get_mask_flag_status() API can get status os flag and interrupt source. + (+) ald_uart_clear_flag_status() API can clear UART flag. @endverbatim * @{ @@ -884,7 +886,7 @@ void uart_irq_handle(uart_handle_t *hperh) * @arg DISABLE * @retval None */ -void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state) +void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_IT(it)); @@ -907,7 +909,7 @@ void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state * @arg DISABLE * @retval None */ -void uart_dma_req_config(uart_handle_t *hperh, type_func_t state) +void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_FUNC_STATE(state)); @@ -927,7 +929,7 @@ void uart_dma_req_config(uart_handle_t *hperh, type_func_t state) * @param level: Transmit fifo level. * @retval None */ -void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_TXFIFO_TYPE(config)); @@ -947,7 +949,7 @@ void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t lev * @param level: Receive fifo level. * @retval None */ -void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_RXFIFO_TYPE(config)); @@ -965,7 +967,7 @@ void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t lev * @param hperh: Pointer to a uart_handle_t structure. * @retval None */ -void uart_lin_send_break(uart_handle_t *hperh) +void ald_uart_lin_send_break(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); @@ -981,7 +983,7 @@ void uart_lin_send_break(uart_handle_t *hperh) * @arg LIN_BREAK_LEN_11B * @retval None */ -void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len) +void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_LIN_BREAK_LEN(len)); @@ -999,7 +1001,7 @@ void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t * @arg UART_ABRMOD_0_TO_1 * @retval None */ -void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) +void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_AUTO_BAUD_MODE(mode)); @@ -1016,7 +1018,7 @@ void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) * @param timeout: Timeout duration * @retval The ALD status. */ -ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout) +ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout) { assert_param(IS_UART_ALL(hperh->perh)); @@ -1053,7 +1055,7 @@ ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t * - 0: RESET * - 1: SET */ -it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it) +it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_IT(it)); @@ -1073,7 +1075,7 @@ it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it) * - 0: RESET * - 1: SET */ -flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status) +flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_STATUS(status)); @@ -1094,7 +1096,7 @@ flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status) * - 0: RESET * - 1: SET */ -flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) +flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_IF(flag)); @@ -1114,7 +1116,7 @@ flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) * - 0: RESET * - 1: SET */ -flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) +flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_IF(flag)); @@ -1132,7 +1134,7 @@ flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) * This parameter can be one of the @ref uart_flag_t. * @retval None */ -void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) +void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_IF(flag)); @@ -1155,8 +1157,8 @@ void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) This subsection provides a set of functions allowing to return the State of UART communication process, return Peripheral Errors occurred during communication process - (+) uart_get_state() API can be helpful to check in run-time the state of the UART peripheral. - (+) uart_get_error() check in run-time errors that could be occurred during communication. + (+) ald_uart_get_state() API can be helpful to check in run-time the state of the UART peripheral. + (+) ald_uart_get_error() check in run-time errors that could be occurred during communication. @endverbatim * @{ @@ -1167,7 +1169,7 @@ void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) * @param hperh: Pointer to a uart_handle_t structure. * @retval ALD state */ -uart_state_t uart_get_state(uart_handle_t *hperh) +uart_state_t ald_uart_get_state(uart_handle_t *hperh) { return hperh->state; } @@ -1177,7 +1179,7 @@ uart_state_t uart_get_state(uart_handle_t *hperh) * @param hperh: Pointer to a uart_handle_t structure. * @retval UART Error Code */ -uint32_t uart_get_error(uart_handle_t *hperh) +uint32_t ald_uart_get_error(uart_handle_t *hperh) { return hperh->err_code; } diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c similarity index 85% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c index 69641cb0600130cfcf36c4a9445bf553b346df72..18672dd07e84908f68354d78175bd40443cc26e1 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c @@ -32,12 +32,12 @@ (##) USART pins configuration: (+++) Enable the clock for the USART GPIOs. (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). - (##) NVIC configuration if you need to use interrupt process (usart_send_by_it() - and usart_recv_by_it() APIs): + (##) NVIC configuration if you need to use interrupt process (ald_usart_send_by_it() + and ald_usart_recv_by_it() APIs): (+++) Configure the USARTx interrupt priority. (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (usart_send_by_dma() - and usart_recv_by_dma() APIs): + (##) DMA Configuration if you need to use DMA process (ald_usart_send_by_dma() + and ald_usart_recv_by_dma() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. (+++) Enable the DMAx interface clock. (+++) Configure the declared DMA handle structure with the required @@ -49,20 +49,20 @@ flow control and mode(Receiver/Transmitter) in the hperh Init structure. (#) For the USART asynchronous mode, initialize the USART registers by calling - the usart_init() API. + the ald_usart_init() API. (#) For the USART Half duplex mode, initialize the USART registers by calling - the usart_half_duplex_init() API. + the ald_usart_half_duplex_init() API. (#) For the LIN mode, initialize the USART registers by calling the usart_lin_init() API. (#) For the Multi-Processor mode, initialize the USART registers by calling - the usart_multi_processor_init() API. + the ald_usart_multi_processor_init() API. [..] (@) The specific USART interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the function - usart_interrupt_config inside the transmit and receive process. + ald_usart_interrupt_config inside the transmit and receive process. [..] Three operation modes are available within this driver : @@ -70,17 +70,17 @@ *** Polling mode IO operation *** ================================= [..] Asynchronous: - (+) Send an amount of data in blocking mode using usart_send() - (+) Receive an amount of data in blocking mode using usart_recv() + (+) Send an amount of data in blocking mode using ald_usart_send() + (+) Receive an amount of data in blocking mode using ald_usart_recv() [..] Synchronous: - (+) Send an amount of data in blocking mode using usart_send_sync() - (+) Receive an amount of data in blocking mode using usart_recv_sync() + (+) Send an amount of data in blocking mode using ald_usart_send_sync() + (+) Receive an amount of data in blocking mode using ald_usart_recv_sync() *** Interrupt mode IO operation *** =================================== [..] Asynchronous: - (+) Send an amount of data in non blocking mode using usart_send_by_it() + (+) Send an amount of data in non blocking mode using ald_usart_send_by_it() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() (+) Receive an amount of data in non blocking mode using USART_recv_by_it() @@ -89,7 +89,7 @@ (+) In case of transfer Error, hperh->error_cbk() function is executed and user can add his own code by customization of function pointer hperh->error_cbk() [..] Synchronous: - (+) Send an amount of data in non blocking mode using usart_send_by_it_sync() + (+) Send an amount of data in non blocking mode using ald_usart_send_by_it_sync() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() (+) Receive an amount of data in non blocking mode using USART_recv_by_it_sync() @@ -101,27 +101,27 @@ *** DMA mode IO operation *** ============================== [..] Asynchronous: - (+) Send an amount of data in non blocking mode (DMA) using usart_send_by_dma() + (+) Send an amount of data in non blocking mode (DMA) using ald_usart_send_by_dma() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using usart_recv_by_dma() + (+) Receive an amount of data in non blocking mode (DMA) using ald_usart_recv_by_dma() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can add his own code by customization of function pointer hperh->error_cbk() [..] Synchronous: - (+) Send an amount of data in non blocking mode (DMA) using usart_send_by_dma_sync() + (+) Send an amount of data in non blocking mode (DMA) using ald_usart_send_by_dma_sync() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using usart_recv_by_dma_sync() + (+) Receive an amount of data in non blocking mode (DMA) using ald_usart_recv_by_dma_sync() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can add his own code by customization of function pointer hperh->error_cbk() [..] Utilities: - (+) Pause the DMA Transfer using usart_dma_pause() - (+) Resume the DMA Transfer using usart_dma_resume() - (+) Stop the DMA Transfer using usart_dma_stop() + (+) Pause the DMA Transfer using ald_usart_dma_pause() + (+) Resume the DMA Transfer using ald_usart_dma_resume() + (+) Stop the DMA Transfer using ald_usart_dma_stop() *** USART ALD driver macros list *** ============================================= @@ -212,8 +212,8 @@ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, fl (++) Hardware flow control (++) Receiver/transmitter modes [..] - The usart_init(), usart_half_duplex_init(), usart_lin_init(), usart_multi_processor_init() - and usart_clock_init() APIs follow respectively the USART asynchronous, USART Half duplex, + The ald_usart_init(), ald_usart_half_duplex_init(), usart_lin_init(), ald_usart_multi_processor_init() + and ald_usart_clock_init() APIs follow respectively the USART asynchronous, USART Half duplex, LIN, Multi-Processor and synchronous configuration procedures. @endverbatim @@ -245,7 +245,7 @@ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, fl * the configuration information for the specified USART module. * @retval None */ -void usart_reset(usart_handle_t *hperh) +void ald_usart_reset(usart_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); @@ -270,14 +270,14 @@ void usart_reset(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_init(usart_handle_t *hperh) +ald_status_t ald_usart_init(usart_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - usart_reset(hperh); + ald_usart_reset(hperh); hperh->state = USART_STATE_BUSY; USART_DISABLE(hperh); usart_set_config(hperh); @@ -305,13 +305,13 @@ ald_status_t usart_init(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_half_duplex_init(usart_handle_t *hperh) +ald_status_t ald_usart_half_duplex_init(usart_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - usart_reset(hperh); + ald_usart_reset(hperh); hperh->state = USART_STATE_BUSY; USART_DISABLE(hperh); usart_set_config(hperh); @@ -343,7 +343,7 @@ ald_status_t usart_half_duplex_init(usart_handle_t *hperh) * @arg USART_WAKEUP_ADDR: Wakeup by an address mark * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup) +ald_status_t ald_usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_WAKEUP(wakeup)); @@ -351,7 +351,7 @@ ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usa assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - usart_reset(hperh); + ald_usart_reset(hperh); hperh->state = USART_STATE_BUSY; USART_DISABLE(hperh); usart_set_config(hperh); @@ -381,13 +381,13 @@ ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usa * @param init: USART Clock Init Structure. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) +ald_status_t ald_usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - usart_reset(hperh); + ald_usart_reset(hperh); hperh->state = USART_STATE_BUSY; USART_DISABLE(hperh); usart_set_config(hperh); @@ -445,20 +445,20 @@ ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) a communication error is detected. (#) Blocking mode APIs are: - (++) usart_send() - (++) usart_recv() + (++) ald_usart_send() + (++) ald_usart_recv() (#) Non Blocking mode APIs with Interrupt are: - (++) usart_send_by_it() - (++) usart_recv_by_it() + (++) ald_usart_send_by_it() + (++) ald_usart_recv_by_it() (++) urart_irq_handle() (#) Non Blocking mode functions with DMA are: - (++) usart_send_by_dma() - (++) usart_recv_by_dma() - (++) usart_dma_pause() - (++) usart_dma_resume() - (++) usart_dma_stop() + (++) ald_usart_send_by_dma() + (++) ald_usart_recv_by_dma() + (++) ald_usart_dma_pause() + (++) ald_usart_dma_resume() + (++) ald_usart_dma_stop() (#) A set of Transfer Complete Callbacks are provided in non blocking mode: (++) hperh->tx_cplt_cbk() @@ -483,7 +483,7 @@ ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) return BUSY; @@ -547,7 +547,7 @@ ald_status_t usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) return BUSY; @@ -607,7 +607,7 @@ ald_status_t usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) return BUSY; @@ -624,7 +624,7 @@ ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size hperh->err_code = USART_ERROR_NONE; __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); return OK; } @@ -637,7 +637,7 @@ ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size * @param size: Amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) return BUSY; @@ -654,9 +654,9 @@ ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size hperh->err_code = USART_ERROR_NONE; __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); return OK; } @@ -669,7 +669,7 @@ ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size * @param size: Maximum amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) return BUSY; @@ -686,9 +686,9 @@ ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->err_code = USART_ERROR_NONE; __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); __frame_mode = 1; return OK; @@ -704,7 +704,7 @@ ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_ * @param channel: DMA channel as USART transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) return BUSY; @@ -730,7 +730,7 @@ ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz hperh->hdmatx.err_arg = (void *)hperh; /* Configure USART DMA transmit */ - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -747,10 +747,10 @@ ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); __UNLOCK(hperh); - usart_clear_flag_status(hperh, USART_FLAG_TC); + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); return OK; @@ -767,7 +767,7 @@ ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz * the parity bit (MSB position) * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) return BUSY; @@ -792,7 +792,7 @@ ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz hperh->hdmarx.err_arg = (void *)hperh; /* Configure DMA Receive */ - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -809,7 +809,7 @@ ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); __UNLOCK(hperh); SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); @@ -847,27 +847,27 @@ ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz using DMA mode. The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks will be executed respectively at the end of the transmit - or Receive process. The hperh->error_cbk() user callback will be - executed when a communication error is detected + or Receive process. The hperh->error_cbk() user callback will be + executed when a communication error is detected (#) Blocking mode APIs are : - (++) usart_send_sync() in simplex mode - (++) usart_recv_sync() in full duplex receive only - (++) usart_send_recv_sync() in full duplex mode + (++) ald_usart_send_sync() in simplex mode + (++) ald_usart_recv_sync() in full duplex receive only + (++) ald_usart_send_recv_sync() in full duplex mode (#) Non Blocking mode APIs with Interrupt are : - (++) usart_send_by_it_sync()in simplex mode - (++) usart_recv_by_it_sync() in full duplex receive only - (++) usart_send_recv_by_it_sync() in full duplex mode - (++) usart_irq_handle() + (++) ald_usart_send_by_it_sync()in simplex mode + (++) ald_usart_recv_by_it_sync() in full duplex receive only + (++) ald_usart_send_recv_by_it_sync() in full duplex mode + (++) ald_usart_irq_handler() (#) Non Blocking mode functions with DMA are : - (++) usart_send_by_dma_sync()in simplex mode - (++) usart_recv_by_dma_sync() in full duplex receive only + (++) ald_usart_send_by_dma_sync()in simplex mode + (++) ald_usart_recv_by_dma_sync() in full duplex receive only (++) usart_send_recv_by_dma_symc() in full duplex mode - (++) usart_dma_pause() - (++) usart_dma_resume() - (++) usart_dma_stop() + (++) ald_usart_dma_pause() + (++) ald_usart_dma_resume() + (++) ald_usart_dma_stop() (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) hperh->tx_cplt_cbk() @@ -888,7 +888,7 @@ ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -945,7 +945,7 @@ ald_status_t usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1024,7 +1024,7 @@ ald_status_t usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) +ald_status_t ald_usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1114,7 +1114,7 @@ ald_status_t usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_ * @retval Status, see @ref ald_status_t. * @note The USART errors are not managed to avoid the overrun error. */ -ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1140,7 +1140,7 @@ ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t */ __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); return OK; } @@ -1153,7 +1153,7 @@ ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t * @param size: Amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1170,9 +1170,9 @@ ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t hperh->state = USART_STATE_BUSY_RX; __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & (uint16_t)0x01FF)); return OK; @@ -1187,7 +1187,7 @@ ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t * @param size: Amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) +ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1207,10 +1207,10 @@ ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, hperh->state = USART_STATE_BUSY_TX_RX; __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); return OK; } @@ -1225,7 +1225,7 @@ ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, * @param channel: DMA channel as USART transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1251,7 +1251,7 @@ ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->hdmatx.err_arg = (void *)hperh; /* Configure DMA transmit */ - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -1268,10 +1268,10 @@ ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); __UNLOCK(hperh); - usart_clear_flag_status(hperh, USART_FLAG_TC); + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); return OK; @@ -1289,7 +1289,7 @@ ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. */ -ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) +ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1308,6 +1308,7 @@ ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ if (hperh->hdmatx.perh == NULL) hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) hperh->hdmarx.perh = DMA0; @@ -1318,7 +1319,7 @@ ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->hdmarx.err_arg = (void *)hperh; /* Configure DMA receive*/ - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -1335,13 +1336,13 @@ ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); /* Enable the USART transmit DMA channel: the transmit channel is used in order * to generate in the non-blocking mode the clock to the slave device, * this mode isn't a simplex receive mode but a full-duplex receive one */ - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -1358,7 +1359,7 @@ ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); USART_CLEAR_OREFLAG(hperh); __UNLOCK(hperh); @@ -1380,7 +1381,7 @@ ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, +ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { if (hperh->state != USART_STATE_READY) @@ -1400,6 +1401,7 @@ ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, if (hperh->hdmatx.perh == NULL) hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) hperh->hdmarx.perh = DMA0; @@ -1414,7 +1416,7 @@ ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, hperh->hdmarx.err_arg = (void *)hperh; /* Configure DMA receive */ - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)rx_buf; hperh->hdmarx.config.size = size; @@ -1431,10 +1433,10 @@ ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); /* Configure DMA transmit*/ - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)tx_buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -1451,9 +1453,9 @@ ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); - usart_clear_flag_status(hperh, USART_FLAG_TC); + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); USART_CLEAR_OREFLAG(hperh); __UNLOCK(hperh); SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); @@ -1477,7 +1479,7 @@ ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_dma_pause(usart_handle_t *hperh) +ald_status_t ald_usart_dma_pause(usart_handle_t *hperh) { __LOCK(hperh); @@ -1510,7 +1512,7 @@ ald_status_t usart_dma_pause(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_dma_resume(usart_handle_t *hperh) +ald_status_t ald_usart_dma_resume(usart_handle_t *hperh) { __LOCK(hperh); @@ -1545,7 +1547,7 @@ ald_status_t usart_dma_resume(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_dma_stop(usart_handle_t *hperh) +ald_status_t ald_usart_dma_stop(usart_handle_t *hperh) { CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); @@ -1560,36 +1562,41 @@ ald_status_t usart_dma_stop(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval None */ -void usart_irq_handle(usart_handle_t *hperh) +void ald_usart_irq_handler(usart_handle_t *hperh) { uint32_t flag; uint32_t source; /* Handle parity error */ - flag = usart_get_flag_status(hperh, USART_FLAG_PE); - source = usart_get_it_status(hperh, USART_IT_PE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_PE); + source = ald_usart_get_it_status(hperh, USART_IT_PE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= USART_ERROR_PE; /* Handle frame error */ - flag = usart_get_flag_status(hperh, USART_FLAG_FE); - source = usart_get_it_status(hperh, USART_IT_ERR); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_FE); + source = ald_usart_get_it_status(hperh, USART_IT_ERR); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= USART_ERROR_FE; /* Handle noise error */ - flag = usart_get_flag_status(hperh, USART_FLAG_NE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_NE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= USART_ERROR_NE; /* Handle overrun error */ - flag = usart_get_flag_status(hperh, USART_FLAG_ORE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_ORE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= USART_ERROR_ORE; /* Handle idle error */ - flag = usart_get_flag_status(hperh, USART_FLAG_IDLE); - source = usart_get_it_status(hperh, USART_IT_IDLE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_IDLE); + source = ald_usart_get_it_status(hperh, USART_IT_IDLE); + if ((flag != RESET) && (source != RESET)) __usart_recv_frame_cplt(hperh); @@ -1597,22 +1604,25 @@ void usart_irq_handle(usart_handle_t *hperh) if (READ_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK) == 0) { /* Receiver */ - flag = usart_get_flag_status(hperh, USART_FLAG_RXNE); - source = usart_get_it_status(hperh, USART_IT_RXNE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status(hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) __usart_recv_by_it(hperh); /* Transmitter */ - flag = usart_get_flag_status(hperh, USART_FLAG_TXE); - source = usart_get_it_status(hperh, USART_IT_TXE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status(hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) __usart_send_by_it(hperh); } - else /* Handle synchronous */ + else /* Handle synchronous */ { /* Receiver */ - flag = usart_get_flag_status(hperh, USART_FLAG_RXNE); - source = usart_get_it_status(hperh, USART_IT_RXNE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status(hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) { if (hperh->state == USART_STATE_BUSY_RX) @@ -1622,8 +1632,9 @@ void usart_irq_handle(usart_handle_t *hperh) } /* Transmitter */ - flag = usart_get_flag_status(hperh, USART_FLAG_TXE); - source = usart_get_it_status(hperh, USART_IT_TXE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status(hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) { if (hperh->state == USART_STATE_BUSY_TX) @@ -1634,8 +1645,9 @@ void usart_irq_handle(usart_handle_t *hperh) } /* Handle transmitter end */ - flag = usart_get_flag_status(hperh, USART_FLAG_TC); - source = usart_get_it_status(hperh, USART_IT_TC); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TC); + source = ald_usart_get_it_status(hperh, USART_IT_TC); + if ((flag != RESET) && (source != RESET)) __usart_end_send_by_it(hperh); @@ -1668,14 +1680,14 @@ void usart_irq_handle(usart_handle_t *hperh) [..] This subsection provides a set of functions allowing to control the USART: (+) usart_lin_send_break() API can be helpful to transmit the break character. - (+) usart_multi_processor_enter_mute_mode() API can be helpful to enter the USART in mute mode. - (+) usart_multi_processor_exit_mute_mode() API can be helpful to exit the USART mute mode by software. - (+) usart_half_duplex_enable_send() API to enable the USART transmitter and disables the USART receiver in Half Duplex mode - (+) usart_half_duplex_enable_recv() API to enable the USART receiver and disables the USART transmitter in Half Duplex mode - (+) usart_interrupt_config() API to Enables/Disables the specified USART interrupts - (+) usart_get_flag_status() API to get USART flag status - (+) usart_clear_flag_status() API to clear USART flag status - (+) usart_get_it_status() API to Checks whether the specified USART interrupt has occurred or not + (+) ald_usart_multi_processor_enter_mute_mode() API can be helpful to enter the USART in mute mode. + (+) ald_usart_multi_processor_exit_mute_mode() API can be helpful to exit the USART mute mode by software. + (+) ald_usart_half_duplex_enable_send() API to enable the USART transmitter and disables the USART receiver in Half Duplex mode + (+) ald_usart_half_duplex_enable_recv() API to enable the USART receiver and disables the USART transmitter in Half Duplex mode + (+) ald_usart_interrupt_config() API to Enables/Disables the specified USART interrupts + (+) ald_usart_get_flag_status() API to get USART flag status + (+) ald_usart_clear_flag_status() API to clear USART flag status + (+) ald_usart_get_it_status() API to Checks whether the specified USART interrupt has occurred or not @endverbatim * @{ @@ -1687,7 +1699,7 @@ void usart_irq_handle(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) +ald_status_t ald_usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); @@ -1707,7 +1719,7 @@ ald_status_t usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) +ald_status_t ald_usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); @@ -1727,7 +1739,7 @@ ald_status_t usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_half_duplex_enable_send(usart_handle_t *hperh) +ald_status_t ald_usart_half_duplex_enable_send(usart_handle_t *hperh) { __LOCK(hperh); @@ -1746,7 +1758,7 @@ ald_status_t usart_half_duplex_enable_send(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_half_duplex_enable_recv(usart_handle_t *hperh) +ald_status_t ald_usart_half_duplex_enable_recv(usart_handle_t *hperh) { __LOCK(hperh); @@ -1764,14 +1776,14 @@ ald_status_t usart_half_duplex_enable_recv(usart_handle_t *hperh) * @param hperh: Pointer to a usart_handle_t structure that contains * the configuration information for the specified USART module. * @param req: specifies the DMA request. - * @arg USART_dma_req_tx: USART DMA transmit request - * @arg USART_dma_req_rx: USART DMA receive request + * @arg USART_dma_req_tx: USART DMA transmit request + * @arg USART_dma_req_rx: USART DMA receive request * @param state: New state of the DMA Request sources. - * @arg ENABLE + * @arg ENABLE * @arg DISABLE * @return: None */ -void usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state) +void ald_usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_DMAREQ(req)); @@ -1804,7 +1816,7 @@ void usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_ * - DISABLE * @retval None */ -void usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state) +void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state) { uint8_t idx; @@ -1850,7 +1862,7 @@ void usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t st * - SET * - RESET */ -flag_status_t usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag) +flag_status_t ald_usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag) { flag_status_t status = RESET; @@ -1880,7 +1892,7 @@ flag_status_t usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag) * @note TXE flag is cleared only by a write to the USART_DR register. * @retval None */ -void usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) +void ald_usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_CLEAR_FLAG(flag)); @@ -1893,22 +1905,22 @@ void usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) * @param hperh: Pointer to a usart_handle_t structure that contains * the configuration information for the specified USART module. * @param it: Specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE: OverRun Error interrupt - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE: OverRun Error interrupt + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt * @retval Status * - SET * - RESET */ -it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it) +it_status_t ald_usart_get_it_status(usart_handle_t *hperh, usart_it_t it) { uint8_t idx; it_status_t status = RESET; @@ -1963,8 +1975,8 @@ it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it) This subsection provides a set of functions allowing to return the State of USART communication process, return Peripheral Errors occurred during communication process - (+) usart_get_state() API can be helpful to check in run-time the state of the USART peripheral. - (+) usart_get_error() check in run-time errors that could be occurred during communication. + (+) ald_usart_get_state() API can be helpful to check in run-time the state of the USART peripheral. + (+) ald_usart_get_error() check in run-time errors that could be occurred during communication. @endverbatim * @{ @@ -1976,7 +1988,7 @@ it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it) * the configuration information for the specified USART module. * @retval USART state */ -usart_state_t usart_get_state(usart_handle_t *hperh) +usart_state_t ald_usart_get_state(usart_handle_t *hperh) { return hperh->state; } @@ -1987,7 +1999,7 @@ usart_state_t usart_get_state(usart_handle_t *hperh) * the configuration information for the specified USART. * @retval USART Error Code */ -uint32_t usart_get_error(usart_handle_t *hperh) +uint32_t ald_usart_get_error(usart_handle_t *hperh) { return hperh->err_code; } @@ -2017,7 +2029,7 @@ static void usart_dma_send_cplt(void *arg) hperh->tx_count = 0; CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - usart_interrupt_config(hperh, USART_IT_TC, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); } /** @@ -2076,16 +2088,16 @@ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, fl if (timeout == 0) return OK; - tick = __get_tick(); + tick = ald_get_tick(); - while ((usart_get_flag_status(hperh, flag)) != status) + while ((ald_usart_get_flag_status(hperh, flag)) != status) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) { - usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); return TIMEOUT; } @@ -2117,8 +2129,8 @@ static ald_status_t __usart_send_by_it(usart_handle_t *hperh) if (--hperh->tx_count == 0) { - usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - usart_interrupt_config(hperh, USART_IT_TC, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); } return OK; @@ -2133,7 +2145,7 @@ static ald_status_t __usart_send_by_it(usart_handle_t *hperh) */ static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh) { - usart_interrupt_config(hperh, USART_IT_TC, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_TC, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); if (hperh->tx_cplt_cbk != NULL) @@ -2173,19 +2185,19 @@ static ald_status_t __usart_recv_by_it(usart_handle_t *hperh) *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); } - if (__frame_mode && ((usart_get_it_status(hperh, USART_IT_IDLE)) == RESET)) - usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE); + if (__frame_mode && ((ald_usart_get_it_status(hperh, USART_IT_IDLE)) == RESET)) + ald_usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE); if (--hperh->rx_count == 0) { - usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); __frame_mode = 0; if (hperh->state == USART_STATE_READY) { - usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); } if (hperh->rx_cplt_cbk != NULL) @@ -2206,8 +2218,8 @@ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh) if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) return BUSY; - usart_interrupt_config(hperh, USART_IT_IDLE, DISABLE); - usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_IDLE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); __frame_mode = 0; @@ -2215,8 +2227,8 @@ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh) if (hperh->state == USART_STATE_READY) { - usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); } if (hperh->rx_cplt_cbk != NULL) @@ -2267,9 +2279,9 @@ static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh) if (hperh->rx_count == 0) { - usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); hperh->state = USART_STATE_READY; if (hperh->rx_cplt_cbk != NULL) @@ -2292,7 +2304,7 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) if (hperh->tx_count != 0) { - if (usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) + if (ald_usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) { if (hperh->init.word_length == USART_WORD_LENGTH_9B) { @@ -2312,13 +2324,13 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) } if (--hperh->tx_count == 0) - usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); } } if (hperh->rx_count != 0) { - if (usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) + if (ald_usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) { if (hperh->init.word_length == USART_WORD_LENGTH_9B) { @@ -2346,9 +2358,9 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) if (hperh->rx_count == 0) { - usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); hperh->state = USART_STATE_READY; @@ -2407,13 +2419,14 @@ static void usart_set_config(usart_handle_t *hperh) if (READ_BIT(hperh->perh->CON0, (1 << 15))) { /* Integer part computing in case Oversampling mode is 8 Samples */ - integer = ((25 * cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); + integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); } else { /* Integer part computing in case Oversampling mode is 16 Samples */ - integer = ((25 * cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); + integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); } + tmp = (integer / 100) << 4; /* Determine the fractional part */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c similarity index 88% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c index cbe2921ee939947cf972ed3c48a6172138e76e66..acf092a2788b3ff79ca0e9ede781eeb8985f1077 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c @@ -44,7 +44,7 @@ * @param interrupt: Enable or disable interrupt. * @retval None */ -void wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) +void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) { assert_param(IS_WWDT_WIN_TYPE(win)); assert_param(IS_FUNC_STATE(interrupt)); @@ -64,7 +64,7 @@ void wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) * @brief Start the WWDT * @retval None */ -void wwdt_start(void) +void ald_wwdt_start(void) { WWDT_UNLOCK(); SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); @@ -77,7 +77,7 @@ void wwdt_start(void) * @brief Get the free-running downcounter value * @retval Value */ -uint32_t wwdt_get_value(void) +uint32_t ald_wwdt_get_value(void) { return WWDT->VALUE; } @@ -86,7 +86,7 @@ uint32_t wwdt_get_value(void) * @brief Get interrupt state * @retval Value */ -it_status_t wwdt_get_flag_status(void) +it_status_t ald_wwdt_get_flag_status(void) { if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) return SET; @@ -98,7 +98,7 @@ it_status_t wwdt_get_flag_status(void) * @brief Clear interrupt state * @retval None */ -void wwdt_clear_flag_status(void) +void ald_wwdt_clear_flag_status(void) { WRITE_REG(WWDT->INTCLR, 1); return; @@ -108,7 +108,7 @@ void wwdt_clear_flag_status(void) * @brief Refreshes the WWDT * @retval None */ -void wwdt_feed_dog(void) +void ald_wwdt_feed_dog(void) { WWDT_UNLOCK(); WRITE_REG(WWDT->INTCLR, 0x1); @@ -130,7 +130,7 @@ void wwdt_feed_dog(void) * @param interrupt: Enable or disable interrupt. * @retval None */ -void iwdt_init(uint32_t load, type_func_t interrupt) +void ald_iwdt_init(uint32_t load, type_func_t interrupt) { assert_param(IS_FUNC_STATE(interrupt)); @@ -148,7 +148,7 @@ void iwdt_init(uint32_t load, type_func_t interrupt) * @brief Start the IWDT * @retval None */ -void iwdt_start(void) +void ald_iwdt_start(void) { IWDT_UNLOCK(); SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); @@ -161,7 +161,7 @@ void iwdt_start(void) * @brief Get the free-running downcounter value * @retval Value */ -uint32_t iwdt_get_value(void) +uint32_t ald_iwdt_get_value(void) { return IWDT->VALUE; } @@ -170,7 +170,7 @@ uint32_t iwdt_get_value(void) * @brief Get interrupt state * @retval Value */ -it_status_t iwdt_get_flag_status(void) +it_status_t ald_iwdt_get_flag_status(void) { if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) return SET; @@ -182,7 +182,7 @@ it_status_t iwdt_get_flag_status(void) * @brief Clear interrupt state * @retval None */ -void iwdt_clear_flag_status(void) +void ald_iwdt_clear_flag_status(void) { WRITE_REG(IWDT->INTCLR, 1); return; @@ -192,7 +192,7 @@ void iwdt_clear_flag_status(void) * @brief Refreshes the WWDT * @retval None */ -void iwdt_feed_dog(void) +void ald_iwdt_feed_dog(void) { IWDT_UNLOCK(); WRITE_REG(IWDT->INTCLR, 1); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c similarity index 78% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c index 24c6bfdf45b724b9dbc87c6dc178b4d758266ee8..596bc38fbf686078a559693810e977ca37da7955 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c @@ -37,14 +37,14 @@ /** * @brief ALD version number */ -#define __ALD_VERSION_MAIN (0x01) /**< [31:24] main version */ -#define __ALD_VERSION_SUB1 (0x00) /**< [23:16] sub1 version */ -#define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ -#define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ -#define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ - (__ALD_VERSION_SUB1 << 16) | \ - (__ALD_VERSION_SUB2 << 8 ) | \ - (__ALD_VERSION_RC)) +#define __ALD_VERSION_MAIN (0x01) /**< [31:24] main version */ +#define __ALD_VERSION_SUB1 (0x00) /**< [23:16] sub1 version */ +#define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ +#define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ +#define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ + (__ALD_VERSION_SUB1 << 16) | \ + (__ALD_VERSION_SUB2 << 8 ) | \ + (__ALD_VERSION_RC)) /** * @} */ @@ -82,11 +82,11 @@ uint32_t __systick_interval = SYSTICK_INTERVAL_1MS; can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms. - (++) Time base configuration function (__init_tick()) is called automatically - at the beginning of the program after reset by mcu_ald_init() or at - any time when clock is configured. + (++) Time base configuration function (ald_tick_init()) is called automatically + at the beginning of the program after reset by ald_cmu_init() or at + any time when clock is configured. (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if __delay_ms() is called from a + time intervals. Care must be taken if ald_delay_ms() is called from a peripheral ISR process, the Tick interrupt line must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. @@ -108,12 +108,12 @@ uint32_t __systick_interval = SYSTICK_INTERVAL_1MS; * The tick variable is incremented each 1ms in its ISR. * @retval None */ -void mcu_ald_init(void) +void ald_cmu_init(void) { - cmu_clock_config_default(); - __init_tick(TICK_INT_PRIORITY); + ald_cmu_clock_config_default(); + ald_tick_init(TICK_INT_PRIORITY); #ifdef ALD_DMA - dma_init(DMA0); + ald_dma_init(DMA0); #endif return; } @@ -124,7 +124,7 @@ void mcu_ald_init(void) * Tick interrupt priority. * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. - * Care must be taken if __delay_ms() is called from a peripheral ISR process, + * Care must be taken if ald_delay_ms() is called from a peripheral ISR process, * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other @@ -132,10 +132,10 @@ void mcu_ald_init(void) * @param prio: Tick interrupt priority. * @retval None */ -__weak void __init_tick(uint32_t prio) +__weak void ald_tick_init(uint32_t prio) { /* Configure the SysTick IRQ */ - SysTick_Config(cmu_get_clock() / SYSTICK_INTERVAL_1MS); + SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS); if (prio != 3) NVIC_SetPriority(SysTick_IRQn, prio); @@ -152,11 +152,11 @@ __weak void __init_tick(uint32_t prio) * @arg @ref SYSTICK_INTERVAL_1000MS 1 second * @retval None */ -void systick_interval_select(systick_interval_t value) +void ald_systick_interval_select(systick_interval_t value) { assert_param(IS_SYSTICK_INTERVAL(value)); - SysTick_Config(cmu_get_clock() / value); + SysTick_Config(ald_cmu_get_sys_clock() / value); __systick_interval = value; if (TICK_INT_PRIORITY != 3) @@ -198,7 +198,7 @@ void systick_interval_select(systick_interval_t value) * implementations in user file. * @retval None */ -__weak void __inc_tick(void) +__weak void ald_inc_tick_weak(void) { ++lib_tick; } @@ -209,7 +209,7 @@ __weak void __inc_tick(void) * other implementations in user file. * @retval None */ -__weak void systick_irq_cbk(void) +__weak void ald_systick_irq_cbk(void) { /* do nothing */ return; @@ -219,10 +219,10 @@ __weak void systick_irq_cbk(void) * @brief This function invoked by Systick ISR each 1ms. * @retval None */ -__isr__ void SysTick_Handler(void) +__isr__ void ald_inc_tick(void) { - __inc_tick(); - systick_irq_cbk(); + ald_inc_tick_weak(); + ald_systick_irq_cbk(); return; } @@ -233,7 +233,7 @@ __isr__ void SysTick_Handler(void) * implementations in user file. * @retval tick value */ -__weak uint32_t __get_tick(void) +__weak uint32_t ald_get_tick(void) { return lib_tick; } @@ -249,37 +249,37 @@ __weak uint32_t __get_tick(void) * @param delay: specifies the delay time length, in milliseconds. * @retval None */ -__weak void __delay_ms(__IO uint32_t delay) +__weak void ald_delay_ms(__IO uint32_t delay) { uint32_t tick, __delay; switch (__systick_interval) { - case SYSTICK_INTERVAL_1MS: - __delay = delay; - break; + case SYSTICK_INTERVAL_1MS: + __delay = delay; + break; - case SYSTICK_INTERVAL_10MS: - __delay = delay / 10; - break; + case SYSTICK_INTERVAL_10MS: + __delay = delay / 10; + break; - case SYSTICK_INTERVAL_100MS: - __delay = delay / 100; - break; + case SYSTICK_INTERVAL_100MS: + __delay = delay / 100; + break; - case SYSTICK_INTERVAL_1000MS: - __delay = delay / 1000; - break; + case SYSTICK_INTERVAL_1000MS: + __delay = delay / 1000; + break; - default: - __delay = delay; - break; + default: + __delay = delay; + break; } - tick = __get_tick(); + tick = ald_get_tick(); __delay = __delay == 0 ? 1 : __delay; - while ((__get_tick() - tick) < __delay) + while ((ald_get_tick() - tick) < __delay) ; } @@ -287,13 +287,13 @@ __weak void __delay_ms(__IO uint32_t delay) * @brief Suspend Tick increment. * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. - * Once __suspend_tick() is called, the the SysTick interrupt + * Once ald_suspend_tick() is called, the the SysTick interrupt * will be disabled and so Tick increment is suspended. * @note This function is declared as __weak to be overwritten * in case of other implementations in user file. * @retval None */ -__weak void __suspend_tick(void) +__weak void ald_suspend_tick(void) { CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } @@ -302,13 +302,13 @@ __weak void __suspend_tick(void) * @brief Resume Tick increment. * @note In the default implementation, SysTick timer is the source of * time base. It is used to generate interrupts at regular time - * intervals. Once __resume_tick() is called, the the SysTick + * intervals. Once ald_resume_tick() is called, the the SysTick * interrupt will be enabled and so Tick increment is resumed. * @note This function is declared as __weak to be overwritten * in case of other implementations in user file. * @retval None */ -__weak void __resume_tick(void) +__weak void ald_resume_tick(void) { SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } @@ -317,7 +317,7 @@ __weak void __resume_tick(void) * @brief This method returns the ALD revision * @retval version: 0xXYZR (8bits for each decimal, R for RC) */ -uint32_t get_ald_version(void) +uint32_t ald_get_ald_version(void) { return __ALD_VERSION; } @@ -330,9 +330,9 @@ uint32_t get_ald_version(void) * @param timeout: Timeout duration. * @retval Status, see @ref ald_status_t. */ -ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) { - uint32_t tick = __get_tick(); + uint32_t tick = ald_get_tick(); assert_param(timeout > 0); @@ -340,7 +340,7 @@ ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint { while (!(IS_BIT_SET(*reg, bit))) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) return TIMEOUT; } } @@ -348,7 +348,7 @@ ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint { while ((IS_BIT_SET(*reg, bit))) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) return TIMEOUT; } } @@ -365,7 +365,7 @@ ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint * @arg DISABLE * @retval None */ -void mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) +void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) { assert_param(IS_FUNC_STATE(status)); assert_param(IS_PRIO(prio)); @@ -387,7 +387,7 @@ void mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) * @brief Get the system tick. * @retval The value of current tick. */ -uint32_t mcu_get_tick(void) +uint32_t ald_mcu_get_tick(void) { uint32_t load = SysTick->LOAD; uint32_t val = SysTick->VAL; @@ -399,7 +399,7 @@ uint32_t mcu_get_tick(void) * @brief Get the CPU ID. * @retval CPU ID. */ -uint32_t mcu_get_cpu_id(void) +uint32_t ald_mcu_get_cpu_id(void) { return SCB->CPUID; } diff --git a/bsp/es32f0654/libraries/SConscript b/bsp/essemi/es32f0654/libraries/SConscript similarity index 96% rename from bsp/es32f0654/libraries/SConscript rename to bsp/essemi/es32f0654/libraries/SConscript index 6da75a02629767c304c912112f550f5771f0bfd9..04d2eae28bb8174139ab3648b61ab67275534d0b 100644 --- a/bsp/es32f0654/libraries/SConscript +++ b/bsp/essemi/es32f0654/libraries/SConscript @@ -22,6 +22,6 @@ path = [cwd + '/CMSIS/Device/EastSoft/ES32F065x/Include', cwd + '/CMSIS/Include', cwd + '/ES32F065x_ALD_StdPeriph_Driver/Include'] -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = ['ES32F065x']) Return('group') diff --git a/bsp/es32f0654/project.uvoptx b/bsp/essemi/es32f0654/project.uvoptx similarity index 100% rename from bsp/es32f0654/project.uvoptx rename to bsp/essemi/es32f0654/project.uvoptx diff --git a/bsp/es32f0654/project.uvprojx b/bsp/essemi/es32f0654/project.uvprojx similarity index 90% rename from bsp/es32f0654/project.uvprojx rename to bsp/essemi/es32f0654/project.uvprojx index e51102987c94bb8681c99b7cfd05d1b09d715ff2..724ef242af1bedcc7be2d89e261205f5ba19420a 100644 --- a/bsp/es32f0654/project.uvprojx +++ b/bsp/essemi/es32f0654/project.uvprojx @@ -330,9 +330,9 @@ 0 - + ES32F065x - .;..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F065x\Include;libraries\CMSIS\Include;libraries\ES32F065x_ALD_StdPeriph_Driver\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\common + .;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F065x\Include;libraries\CMSIS\Include;libraries\ES32F065x_ALD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common @@ -379,105 +379,98 @@ clock.c 1 - ..\..\src\clock.c + ..\..\..\src\clock.c components.c 1 - ..\..\src\components.c - - - - - cpu.c - 1 - ..\..\src\cpu.c + ..\..\..\src\components.c device.c 1 - ..\..\src\device.c + ..\..\..\src\device.c idle.c 1 - ..\..\src\idle.c + ..\..\..\src\idle.c ipc.c 1 - ..\..\src\ipc.c + ..\..\..\src\ipc.c irq.c 1 - ..\..\src\irq.c + ..\..\..\src\irq.c kservice.c 1 - ..\..\src\kservice.c + ..\..\..\src\kservice.c mem.c 1 - ..\..\src\mem.c + ..\..\..\src\mem.c mempool.c 1 - ..\..\src\mempool.c + ..\..\..\src\mempool.c object.c 1 - ..\..\src\object.c + ..\..\..\src\object.c scheduler.c 1 - ..\..\src\scheduler.c + ..\..\..\src\scheduler.c signal.c 1 - ..\..\src\signal.c + ..\..\..\src\signal.c thread.c 1 - ..\..\src\thread.c + ..\..\..\src\thread.c timer.c 1 - ..\..\src\timer.c + ..\..\..\src\timer.c @@ -587,6 +580,13 @@ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c + + + ald_flash_ext.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + + ald_gpio.c @@ -652,23 +652,23 @@ - ald_temp.c + ald_timer.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_temp.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c - ald_timer.c + ald_trng.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c - ald_trng.c + ald_tsense.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c @@ -713,35 +713,35 @@ backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ..\..\..\libcpu\arm\common\backtrace.c div0.c 1 - ..\..\libcpu\arm\common\div0.c + ..\..\..\libcpu\arm\common\div0.c showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ..\..\..\libcpu\arm\common\showmem.c cpuport.c 1 - ..\..\libcpu\arm\cortex-m0\cpuport.c + ..\..\..\libcpu\arm\cortex-m0\cpuport.c context_rvds.S 2 - ..\..\libcpu\arm\cortex-m0\context_rvds.S + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S @@ -751,63 +751,63 @@ pin.c 1 - ..\..\components\drivers\misc\pin.c + ..\..\..\components\drivers\misc\pin.c serial.c 1 - ..\..\components\drivers\serial\serial.c + ..\..\..\components\drivers\serial\serial.c completion.c 1 - ..\..\components\drivers\src\completion.c + ..\..\..\components\drivers\src\completion.c dataqueue.c 1 - ..\..\components\drivers\src\dataqueue.c + ..\..\..\components\drivers\src\dataqueue.c pipe.c 1 - ..\..\components\drivers\src\pipe.c + ..\..\..\components\drivers\src\pipe.c ringblk_buf.c 1 - ..\..\components\drivers\src\ringblk_buf.c + ..\..\..\components\drivers\src\ringblk_buf.c ringbuffer.c 1 - ..\..\components\drivers\src\ringbuffer.c + ..\..\..\components\drivers\src\ringbuffer.c waitqueue.c 1 - ..\..\components\drivers\src\waitqueue.c + ..\..\..\components\drivers\src\waitqueue.c workqueue.c 1 - ..\..\components\drivers\src\workqueue.c + ..\..\..\components\drivers\src\workqueue.c @@ -817,21 +817,21 @@ shell.c 1 - ..\..\components\finsh\shell.c + ..\..\..\components\finsh\shell.c cmd.c 1 - ..\..\components\finsh\cmd.c + ..\..\..\components\finsh\cmd.c msh.c 1 - ..\..\components\finsh\msh.c + ..\..\..\components\finsh\msh.c diff --git a/bsp/es32f0654/rtconfig.h b/bsp/essemi/es32f0654/rtconfig.h similarity index 95% rename from bsp/es32f0654/rtconfig.h rename to bsp/essemi/es32f0654/rtconfig.h index 61cd5f891d7dff921be4cbcce1685f2f1768a515..ab25a2d01bb306cf3e2e58e9be2d2783045171c4 100644 --- a/bsp/es32f0654/rtconfig.h +++ b/bsp/essemi/es32f0654/rtconfig.h @@ -39,7 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart2" -#define RT_VER_NUM 0x40001 +#define RT_VER_NUM 0x40002 /* RT-Thread Components */ @@ -78,9 +78,6 @@ #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN -/* Using WiFi */ - - /* Using USB */ @@ -92,10 +89,10 @@ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -144,13 +141,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_ES32F0654LT /* Hardware Drivers Config */ diff --git a/bsp/es32f0654/rtconfig.py b/bsp/essemi/es32f0654/rtconfig.py similarity index 100% rename from bsp/es32f0654/rtconfig.py rename to bsp/essemi/es32f0654/rtconfig.py diff --git a/bsp/es32f0654/template.uvoptx b/bsp/essemi/es32f0654/template.uvoptx similarity index 100% rename from bsp/es32f0654/template.uvoptx rename to bsp/essemi/es32f0654/template.uvoptx diff --git a/bsp/es32f0654/template.uvprojx b/bsp/essemi/es32f0654/template.uvprojx similarity index 100% rename from bsp/es32f0654/template.uvprojx rename to bsp/essemi/es32f0654/template.uvprojx