/** ****************************************************************************** * @file stm32u575xx.h * @author MCD Application Team * @brief CMSIS STM32U575xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention * * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ #ifndef STM32U575xx_H #define STM32U575xx_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup ST * @{ */ /** @addtogroup STM32U575xx * @{ */ /** @addtogroup Configuration_of_CMSIS * @{ */ /* =========================================================================================================================== */ /* ================ Interrupt Number Definition ================ */ /* =========================================================================================================================== */ typedef enum { /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ SecureFault_IRQn = -9, /*!< -9 Secure Fault */ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ /* =========================================== STM32U575xx Specific Interrupt Numbers ================================= */ WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ RTC_IRQn = 2, /*!< RTC non-secure interrupt */ RTC_S_IRQn = 3, /*!< RTC secure interrupt */ TAMP_IRQn = 4, /*!< Tamper non-secure interrupt */ RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ RCC_IRQn = 9, /*!< RCC non secure global interrupt */ RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ IWDG_IRQn = 27, /*!< IWDG global interrupt */ GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ ADC1_IRQn = 37, /*!< ADC1 global interrupt */ DAC1_IRQn = 38, /*!< DAC1 global interrupt */ FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ TIM2_IRQn = 45, /*!< TIM2 global interrupt */ TIM3_IRQn = 46, /*!< TIM3 global interrupt */ TIM4_IRQn = 47, /*!< TIM4 global interrupt */ TIM5_IRQn = 48, /*!< TIM5 global interrupt */ TIM6_IRQn = 49, /*!< TIM6 global interrupt */ TIM7_IRQn = 50, /*!< TIM7 global interrupt */ TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ SPI1_IRQn = 59, /*!< SPI1 global interrupt */ SPI2_IRQn = 60, /*!< SPI2 global interrupt */ USART1_IRQn = 61, /*!< USART1 global interrupt */ USART2_IRQn = 62, /*!< USART2 global interrupt */ USART3_IRQn = 63, /*!< USART3 global interrupt */ UART4_IRQn = 64, /*!< UART4 global interrupt */ UART5_IRQn = 65, /*!< UART5 global interrupt */ LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ TIM15_IRQn = 69, /*!< TIM15 global interrupt */ TIM16_IRQn = 70, /*!< TIM16 global interrupt */ TIM17_IRQn = 71, /*!< TIM17 global interrupt */ COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ OTG_FS_IRQn = 73, /*!< USB OTG FS global interrupt */ CRS_IRQn = 74, /*!< CRS global interrupt */ FMC_IRQn = 75, /*!< FSMC global interrupt */ OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ SDMMC2_IRQn = 79, /*!< SDMMC2 global interrupt */ GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */ TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ RNG_IRQn = 94, /*!< RNG global interrupt */ FPU_IRQn = 95, /*!< FPU global interrupt */ HASH_IRQn = 96, /*!< HASH global interrupt */ LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ SPI3_IRQn = 99, /*!< SPI3 global interrupt */ I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ MDF1_FLT2_IRQn = 104, /*!< MDF1 Filter 2 global interrupt */ MDF1_FLT3_IRQn = 105, /*!< MDF1 Filter 3 global interrupt */ UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */ ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ ADF1_IRQn = 112, /*!< ADF interrupt */ ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ DMA2D_IRQn = 118, /*!< DMA2D global interrupt */ DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ OCTOSPI2_IRQn = 120, /*!< OCTOSPI2 global interrupt */ MDF1_FLT4_IRQn = 121, /*!< MDF1 Filter 4 global interrupt */ MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */ CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ FMAC_IRQn = 124, /*!< FMAC global interrupt */ } IRQn_Type; /* =========================================================================================================================== */ /* ================ Processor and Core Peripheral Section ================ */ /* =========================================================================================================================== */ /* ------- Start of section using anonymous unions and disabling warnings ------- */ #if defined (__CC_ARM) #pragma push #pragma anon_unions #elif defined (__ICCARM__) #pragma language=extended #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wc11-extensions" #pragma clang diagnostic ignored "-Wreserved-id-macro" #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ #define __CM33_REV 0x0000U /* Core revision r0p1 */ #define __SAUREGION_PRESENT 1U /* SAU regions present */ #define __MPU_PRESENT 1U /* MPU present */ #define __VTOR_PRESENT 1U /* VTOR present */ #define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1U /* FPU present */ #define __DSP_PRESENT 1U /* DSP extension present */ /** @} */ /* End of group Configuration_of_CMSIS */ #include /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Section ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32U5xx_peripherals * @{ */ /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ uint32_t RESERVED3[246]; /*!< Reserved, */ __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ } CRC_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ __IO uint32_t AUTOCR; } I2C_TypeDef; /** * @brief DAC */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ __IO uint32_t RESERVED[1]; __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ } DAC_TypeDef; /** * @brief Clock Recovery System */ typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ } CRS_TypeDef; /** * @brief HASH */ typedef struct { __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ } HASH_TypeDef; /** * @brief HASH_DIGEST */ typedef struct { __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ } HASH_DIGEST_TypeDef; /** * @brief RNG */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED; __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ uint32_t RESERVED2; /*!< Reserved, 0x24 */ __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ } DBGMCU_TypeDef; /** * @brief DCMI */ typedef struct { __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ } DMA_TypeDef; typedef struct { __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ } DMA_Channel_TypeDef; /** * @brief DMA2D Controller */ typedef struct { __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ } DMA2D_TypeDef; /** * @brief Asynch Interrupt/Event Controller (EXTI) */ typedef struct { __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ uint32_t RESERVED4[4]; /*!< Reserved4, Address offset: 0x90-0x9C */ __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ uint32_t RESERVED5[4]; /*!< Reserved5, Address offset: 0xB0-0xBC */ __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ uint32_t RESERVED7[4]; /*!< Reserved7, Address offset: 0xE0-0xEC */ __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ } FLASH_TypeDef; /** * @brief FMAC */ typedef struct { __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ } FMAC_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ } GPIO_TypeDef; /** * @brief Global TrustZone Controller */ typedef struct { __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ } GTZC_TZSC_TypeDef; typedef struct { __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */ uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */ __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ } GTZC_MPCBB_TypeDef; typedef struct { __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ } GTZC_TZIC_TypeDef; /** * @brief Instruction Cache */ typedef struct { __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */ __IO uint32_t HWCFGR; /*!< ICACHE HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< ICACHE version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ICACHE IP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ICACHE size identification register, Address offset: 0x3FC */ } ICACHE_TypeDef; /** * @brief Data Cache */ typedef struct { __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ } DCACHE_TypeDef; /** * @brief PSSI */ typedef struct { __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ } PSSI_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ } TIM_TypeDef; /** * @brief LPTIMER */ typedef struct { __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ } LPTIM_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */ } COMP_TypeDef; typedef struct { __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ } COMP_Common_TypeDef; /** * @brief Operational Amplifier (OPAMP) */ typedef struct { __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ } OPAMP_TypeDef; /*Aliases */ #define OPAMP_Common_TypeDef OPAMP_TypeDef /** * @brief MDF/ADF */ typedef struct { __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ }MDF_TypeDef; /** * @brief MDF/ADF filter */ typedef struct { __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ } MDF_Filter_TypeDef; /** * @brief OCTO Serial Peripheral Interface */ typedef struct { __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */ uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ } OCTOSPI_TypeDef; /** * @brief OCTO Serial Peripheral Interface IO Manager */ typedef struct { __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ } OCTOSPIM_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ __IO uint32_t VOSR; /*!< PWR voltage scaling register, Address offset: 0x0C */ __IO uint32_t SVMCR; /*!< PWR supply voltage monitoring control register, Address offset: 0x10 */ __IO uint32_t WUCR1; /*!< PWR wakeup control register 1, Address offset: 0x14 */ __IO uint32_t WUCR2; /*!< PWR wakeup control register 2, Address offset: 0x18 */ __IO uint32_t WUCR3; /*!< PWR wakeup control register 3, Address offset: 0x1C */ __IO uint32_t BDCR1; /*!< PWR backup domain control register 1, Address offset: 0x20 */ __IO uint32_t BDCR2; /*!< PWR backup domain control register 2, Address offset: 0x24 */ __IO uint32_t DBPR; /*!< PWR disable backup domain register, Address offset: 0x28 */ __IO uint32_t UCPDR; /*!< PWR USB Type-C and Power Delivery register, Address offset: 0x2C */ __IO uint32_t SECCFGR; /*!< PWR Security configuration register, Address offset: 0x30 */ __IO uint32_t PRIVCFGR; /*!< PWR privilege control register, Address offset: 0x34 */ __IO uint32_t SR; /*!< PWR status register, Address offset: 0x38 */ __IO uint32_t SVMSR; /*!< PWR supply voltage monitoring status register, Address offset: 0x3C */ __IO uint32_t BDSR; /*!< PWR backup domain status register, Address offset: 0x40 */ __IO uint32_t WUSR; /*!< PWR wakeup status register, Address offset: 0x44 */ __IO uint32_t WUSCR; /*!< PWR wakeup status clear register, Address offset: 0x48 */ __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x4C */ __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ } PWR_TypeDef; /** * @brief SRAMs configuration controller */ typedef struct { __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ }RAMCFG_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ } RCC_TypeDef; /* * @brief RTC Specific device feature definitions */ #define RTC_BKP_NB 32U #define RTC_TAMP_NB 8U /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ } RTC_TypeDef; /** * @brief Tamper and backup registers */ typedef struct { __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ } TAMP_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ } USART_TypeDef; /** * @brief Serial Audio Interface */ typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; typedef struct { __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; /** * @brief System configuration controller */ typedef struct { __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ uint32_t RESERVED2[16];/*!< RESERVED2, Address offset: 0x30 - 0x6C */ __IO uint32_t UCPD; /*!< SYSCFG USB Type C and Power delivery register Address offset: 0x70 */ } SYSCFG_TypeDef; /** * @brief Secure digital input/output Interface */ typedef struct { __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ } SDMMC_TypeDef; /** * @brief Delay Block DLYB */ typedef struct { __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ } DLYB_TypeDef; /** * @brief UCPD */ typedef struct { __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ } UCPD_TypeDef; /** * @brief USB_OTG_Core_register */ typedef struct { __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ } USB_OTG_GlobalTypeDef; /** * @brief USB_OTG_device_Registers */ typedef struct { __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ } USB_OTG_DeviceTypeDef; /** * @brief USB_OTG_IN_Endpoint-Specific_Register */ typedef struct { __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ } USB_OTG_INEndpointTypeDef; /** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ typedef struct { __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ } USB_OTG_OUTEndpointTypeDef; /** * @brief USB_OTG_Host_Mode_Register_Structures */ typedef struct { __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ } USB_OTG_HostTypeDef; /** * @brief USB_OTG_Host_Channel_Specific_Registers */ typedef struct { __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ } USB_OTG_HostChannelTypeDef; /** * @brief FD Controller Area Network */ typedef struct { __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ uint32_t RESERVED1; /*!< Reserved, 0x008 */ __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ uint32_t RESERVED3; /*!< Reserved, 0x04C */ __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ uint32_t RESERVED5; /*!< Reserved, 0x08C */ __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ } FDCAN_GlobalTypeDef; /** * @brief FD Controller Area Network Configuration */ typedef struct { __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ } FDCAN_Config_TypeDef; /** * @brief Flexible Memory Controller */ typedef struct { __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ } FMC_Bank1_TypeDef; /** * @brief Flexible Memory Controller Bank1E */ typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FMC_Bank1E_TypeDef; /** * @brief Flexible Memory Controller Bank3 */ typedef struct { __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ uint32_t RESERVED0; /*!< Reserved, 0x90 */ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ } FMC_Bank3_TypeDef; /** * @brief VREFBUF */ typedef struct { __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ } VREFBUF_TypeDef; /** * @brief ADC */ typedef struct { __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ __IO uint32_t PW; /*!< ADC power register, Address offset: 0x44 */ uint32_t RESERVED1; /*!< Reserved, 0x048 */ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ uint32_t RESERVED5; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ } ADC_TypeDef; typedef struct { __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ } ADC_Common_TypeDef; /** * @brief CORDIC */ typedef struct { __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ } CORDIC_TypeDef; /** * @brief IWDG */ typedef struct { __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ } IWDG_TypeDef; /** * @brief SPI */ typedef struct { __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ } SPI_TypeDef; /** * @brief Touch Sensing Controller (TSC) */ typedef struct { __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ } TSC_TypeDef; /** * @brief WWDG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /*@}*/ /* end of group STM32U5xx_peripherals */ /* -------- End of section using anonymous unions and disabling warnings -------- */ #if defined (__CC_ARM) #pragma pop #elif defined (__ICCARM__) /* leave anonymous unions enabled */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning restore #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Address Map ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32U5xx_Peripheral_peripheralAddr * @{ */ /* Internal SRAMs size */ #define SRAM1_SIZE (0x30000UL) /*!< SRAM1=192k */ #define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ #define SRAM3_SIZE (0x80000UL) /*!< SRAM3=512k */ #define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ /* External memories base addresses - Not aliased */ #define FMC_BASE (0x60000000UL) /*!< FMC base address */ #define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ #define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ #define FMC_BANK1 FMC_BASE #define FMC_BANK1_1 FMC_BANK1 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) #define FMC_BANK3 (FMC_BASE + 0x20000000UL) /* Flash, Peripheral and internal SRAMs base addresses - Non secure */ #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address */ #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */ #define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */ #define SRAM3_BASE_NS (0x20040000UL) /*!< SRAM3 (512 KB) non-secure base address */ #define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ #define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ /* Peripheral memory map - Non secure */ #define APB1PERIPH_BASE_NS PERIPH_BASE_NS #define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) #define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) #define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) #define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) #define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) /*!< APB1 Non secure peripherals */ #define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) #define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) #define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) #define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) #define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) #define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) #define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) #define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) #define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) #define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) #define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) #define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) #define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) #define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) #define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) #define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) #define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) #define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) #define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) #define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) #define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) #define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) /*!< APB2 Non secure peripherals */ #define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) #define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) #define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) #define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) #define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) #define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) #define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) #define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) #define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) #define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) #define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) #define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) #define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) /*!< APB3 Non secure peripherals */ #define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) #define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) #define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) #define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) #define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) #define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) #define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) #define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) #define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) #define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) #define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) #define COMP1_BASE_NS (COMP12_BASE_NS) #define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) #define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) #define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) #define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) /*!< AHB1 Non secure peripherals */ #define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) #define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) #define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) #define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) #define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) #define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) #define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) #define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) #define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) #define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) #define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) #define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) #define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) #define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) #define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) #define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) #define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) #define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) #define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) #define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) #define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) #define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) #define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) #define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) #define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) #define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) #define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) #define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) #define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) #define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) #define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) #define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) #define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) #define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) #define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) #define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) #define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) #define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) #define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) #define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) #define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) #define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) #define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) #define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) /*!< AHB2 Non secure peripherals */ #define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) #define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) #define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) #define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) #define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) #define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) #define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) #define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) #define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) #define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) #define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL) #define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) #define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) #define USB_OTG_FS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) #define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) #define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) #define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) #define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ #define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) #define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) #define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) #define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) #define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) #define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) #define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ #define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) #define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) #define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) #define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ #define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ /*!< AHB3 Non secure peripherals */ #define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) #define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) #define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) #define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) #define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1308UL) #define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) #define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) #define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) #define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) #define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) #define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) #define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) #define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) #define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) #define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) #define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) #define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) /* Flash, Peripheral and internal SRAMs base addresses - Secure */ #define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ #define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ #define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ #define SRAM3_BASE_S (0x30040000UL) /*!< SRAM3 (512 KB) secure base address */ #define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ #define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ /* Peripheral memory map - Secure */ #define APB1PERIPH_BASE_S PERIPH_BASE_S #define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) #define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) #define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) #define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) #define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) /*!< APB1 Secure peripherals */ #define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) #define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) #define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) #define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) #define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) #define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) #define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) #define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) #define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) #define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) #define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) #define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) #define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) #define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) #define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) #define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) #define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) #define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) #define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) #define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) #define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) #define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) /*!< APB2 Secure peripherals */ #define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) #define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) #define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) #define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) #define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) #define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) #define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) #define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) #define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) #define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) #define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) #define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) #define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) /*!< APB3 Secure peripherals */ #define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) #define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) #define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL) #define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) #define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) #define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) #define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4300UL) #define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) #define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) #define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) #define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) #define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) #define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) #define COMP1_BASE_S (COMP12_BASE_S) #define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) #define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) #define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) #define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) /*!< AHB1 Secure peripherals */ #define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) #define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) #define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) #define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) #define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) #define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) #define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) #define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) #define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) #define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) #define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) #define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) #define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) #define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) #define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) #define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) #define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) #define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) #define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) #define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) #define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) #define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) #define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) #define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) #define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) #define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) #define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) #define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) #define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) #define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) #define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) #define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) #define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) #define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) #define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) #define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) #define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) #define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) #define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) #define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) #define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) #define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) #define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) #define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) /*!< AHB2 Secure peripherals */ #define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) #define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) #define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) #define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) #define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) #define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) #define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) #define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) #define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) #define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) #define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL) #define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) #define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) #define USB_OTG_FS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) #define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) #define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) #define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) #define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ #define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) #define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) #define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) #define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) #define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) #define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) #define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ #define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) #define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) #define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) #define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ #define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ /*!< AHB3 Secure peripherals */ #define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) #define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) #define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) #define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) #define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) #define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) #define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) #define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) #define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) #define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) #define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) #define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) #define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) #define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) #define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) /* Debug MCU registers base address */ #define DBGMCU_BASE (0xE0044000UL) #define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ #define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ /* Internal Flash OTP Area */ #define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ #define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ /* USB OTG FS registers Base address */ #define USB_OTG_GLOBAL_BASE (0x0000UL) #define USB_OTG_DEVICE_BASE (0x0800UL) #define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) #define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) #define USB_OTG_EP_REG_SIZE (0x0020UL) #define USB_OTG_HOST_BASE (0x0400UL) #define USB_OTG_HOST_PORT_BASE (0x0440UL) #define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) #define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) #define USB_OTG_PCGCCTL_BASE (0x0E00UL) #define USB_OTG_FIFO_BASE (0x1000UL) #define USB_OTG_FIFO_SIZE (0x1000UL) /*!< Root Secure Service Library */ /************ RSSLIB SAU system Flash region definition constants *************/ #define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) #define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) /************ RSSLIB function return constants ********************************/ #define RSSLIB_ERROR (0xF5F5F5F5UL) #define RSSLIB_SUCCESS (0xEAEAEAEAUL) /*!< RSSLIB pointer function structure address definition */ #define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START #define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) /*!< HDP Area constant definition */ #define RSSLIB_HDP_AREA_Pos (0U) #define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) #define RSSLIB_HDP_AREA1_Pos (0U) #define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) #define RSSLIB_HDP_AREA2_Pos (1U) #define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) /** * @brief Prototype of RSSLIB Close and exit HDP Function * @detail This function close the requested hdp area passed in input * parameter and jump to the reset handler present within the * Vector table. The function does not return on successful execution. * @param HdpArea notifies which hdp area to close, can be a combination of * hdpa area 1 and hdp area 2 * @param pointer on the vector table containing the reset handler the function * jumps to. * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); /** * @brief RSSLib non-secure callable function pointer structure */ typedef struct { __IM uint32_t Reserved[8]; }NSC_pFuncTypeDef; /** * @brief RSSLib secure callable function pointer structure */ typedef struct { __IM uint32_t Reserved2[2]; __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ }S_pFuncTypeDef; /** * @brief RSSLib function pointer structure */ typedef struct { NSC_pFuncTypeDef NSC; S_pFuncTypeDef S; }RSSLIB_pFunc_TypeDef; /** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ /* =========================================================================================================================== */ /* ================ Peripheral declaration ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32U5xx_Peripheral_declaration * @{ */ /*!< APB1 Non secure peripherals */ #define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) #define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) #define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) #define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) #define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) #define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) #define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) #define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) #define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) #define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) #define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) #define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) #define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) #define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) #define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) #define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) #define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) #define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) #define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) #define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) #define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) /*!< APB2 Non secure peripherals */ #define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) #define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) #define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) #define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) #define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) #define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) #define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) #define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) #define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) #define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) #define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) #define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) #define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) /*!< APB3 Non secure peripherals */ #define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) #define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) #define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) #define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) #define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) #define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) #define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) #define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) #define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) #define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) #define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) #define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) #define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) #define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) #define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) #define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) #define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) /*!< AHB1 Non secure peripherals */ #define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) #define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) #define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) #define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) #define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) #define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) #define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) #define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) #define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) #define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) #define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) #define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) #define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) #define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) #define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) #define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) #define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) #define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) #define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) #define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) #define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) #define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) #define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) #define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) #define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) #define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) #define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) #define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) #define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) #define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) #define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) #define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) #define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) #define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) #define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) #define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) #define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) #define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) #define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) #define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) #define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) #define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) /*!< AHB2 Non secure peripherals */ #define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) #define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) #define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) #define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) #define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) #define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) #define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) #define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) #define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) #define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) #define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) #define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) #define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) #define USB_OTG_FS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_NS) #define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) #define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) #define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) #define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) #define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) #define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) #define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) #define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) #define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) #define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) #define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) #define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) #define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) #define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) #define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) /*!< AHB3 Non secure peripherals */ #define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) #define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) #define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) #define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) #define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) #define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) #define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) #define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) #define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) #define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) #define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) #define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) #define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) #define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) #define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) #define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) #define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) /*!< APB1 Secure peripherals */ #define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) #define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) #define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) #define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) #define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) #define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) #define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) #define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) #define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) #define USART2_S ((USART_TypeDef *) USART2_BASE_S) #define USART3_S ((USART_TypeDef *) USART3_BASE_S) #define UART4_S ((USART_TypeDef *) UART4_BASE_S) #define UART5_S ((USART_TypeDef *) UART5_BASE_S) #define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) #define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) #define CRS_S ((CRS_TypeDef *) CRS_BASE_S) #define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) #define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) #define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) #define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) #define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) /*!< APB2 Secure peripherals */ #define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) #define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) #define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) #define USART1_S ((USART_TypeDef *) USART1_BASE_S) #define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) #define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) #define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) #define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) #define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) #define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) #define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) #define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) #define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) /*!< APB3 secure peripherals */ #define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) #define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) #define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) #define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) #define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) #define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) #define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) #define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) #define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) #define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) #define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) #define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) #define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) #define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) #define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) #define RTC_S ((RTC_TypeDef *) RTC_BASE_S) #define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) /*!< AHB1 Secure peripherals */ #define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) #define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) #define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) #define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) #define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) #define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) #define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) #define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) #define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) #define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) #define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) #define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) #define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) #define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) #define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) #define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) #define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) #define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) #define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) #define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) #define CRC_S ((CRC_TypeDef *) CRC_BASE_S) #define TSC_S ((TSC_TypeDef *) TSC_BASE_S) #define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) #define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) #define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) #define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) #define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) #define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) #define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) #define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) #define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) #define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) #define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) #define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) #define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) #define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) #define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) #define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) #define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) #define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) #define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) #define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) /*!< AHB2 Secure peripherals */ #define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) #define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) #define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) #define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) #define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) #define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) #define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) #define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) #define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) #define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) #define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) #define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) #define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) #define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_S) #define HASH_S ((HASH_TypeDef *) HASH_BASE_S) #define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) #define RNG_S ((RNG_TypeDef *) RNG_BASE_S) #define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) #define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) #define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) #define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) #define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) #define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) #define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) #define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) #define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) #define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) #define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) #define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) /*!< AHB3 Secure peripherals */ #define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) #define PWR_S ((PWR_TypeDef *) PWR_BASE_S) #define RCC_S ((RCC_TypeDef *) RCC_BASE_S) #define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) #define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) #define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) #define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) #define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) #define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) #define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) #define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) #define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) #define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) #define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) #define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) #define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) #define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) /*!< DBGMCU peripheral */ #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /*!< Memory base addresses for Secure peripherals */ #define FLASH_BASE FLASH_BASE_S #define SRAM1_BASE SRAM1_BASE_S #define SRAM2_BASE SRAM2_BASE_S #define SRAM3_BASE SRAM3_BASE_S #define SRAM4_BASE SRAM4_BASE_S #define BKPSRAM_BASE BKPSRAM_BASE_S #define PERIPH_BASE PERIPH_BASE_S #define APB1PERIPH_BASE APB1PERIPH_BASE_S #define APB2PERIPH_BASE APB2PERIPH_BASE_S #define AHB1PERIPH_BASE AHB1PERIPH_BASE_S #define AHB2PERIPH_BASE AHB2PERIPH_BASE_S /*!< Instance aliases and base addresses for Secure peripherals */ #define CORDIC CORDIC_S #define CORDIC_BASE CORDIC_BASE_S #define RCC RCC_S #define RCC_BASE RCC_BASE_S #define DCMI DCMI_S #define DCMI_BASE DCMI_BASE_S #define PSSI PSSI_S #define PSSI_BASE PSSI_BASE_S #define FLASH FLASH_S #define FLASH_R_BASE FLASH_R_BASE_S #define FMAC FMAC_S #define FMAC_BASE FMAC_BASE_S #define GPDMA1 GPDMA1_S #define GPDMA1_BASE GPDMA1_BASE_S #define GPDMA1_Channel0 GPDMA1_Channel0_S #define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S #define GPDMA1_Channel1 GPDMA1_Channel1_S #define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S #define GPDMA1_Channel2 GPDMA1_Channel2_S #define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S #define GPDMA1_Channel3 GPDMA1_Channel3_S #define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S #define GPDMA1_Channel4 GPDMA1_Channel4_S #define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S #define GPDMA1_Channel5 GPDMA1_Channel5_S #define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S #define GPDMA1_Channel6 GPDMA1_Channel6_S #define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S #define GPDMA1_Channel7 GPDMA1_Channel7_S #define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S #define GPDMA1_Channel8 GPDMA1_Channel8_S #define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S #define GPDMA1_Channel9 GPDMA1_Channel9_S #define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S #define GPDMA1_Channel10 GPDMA1_Channel10_S #define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S #define GPDMA1_Channel11 GPDMA1_Channel11_S #define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S #define GPDMA1_Channel12 GPDMA1_Channel12_S #define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S #define GPDMA1_Channel13 GPDMA1_Channel13_S #define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S #define GPDMA1_Channel14 GPDMA1_Channel14_S #define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S #define GPDMA1_Channel15 GPDMA1_Channel15_S #define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S #define LPDMA1 LPDMA1_S #define LPDMA1_BASE LPDMA1_BASE_S #define LPDMA1_Channel0 LPDMA1_Channel0_S #define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S #define LPDMA1_Channel1 LPDMA1_Channel1_S #define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S #define LPDMA1_Channel2 LPDMA1_Channel2_S #define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S #define LPDMA1_Channel3 LPDMA1_Channel3_S #define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S #define GPIOA GPIOA_S #define GPIOA_BASE GPIOA_BASE_S #define GPIOB GPIOB_S #define GPIOB_BASE GPIOB_BASE_S #define GPIOC GPIOC_S #define GPIOC_BASE GPIOC_BASE_S #define GPIOD GPIOD_S #define GPIOD_BASE GPIOD_BASE_S #define GPIOE GPIOE_S #define GPIOE_BASE GPIOE_BASE_S #define GPIOF GPIOF_S #define GPIOF_BASE GPIOF_BASE_S #define GPIOG GPIOG_S #define GPIOG_BASE GPIOG_BASE_S #define GPIOH GPIOH_S #define GPIOH_BASE GPIOH_BASE_S #define GPIOI GPIOI_S #define GPIOI_BASE GPIOI_BASE_S #define LPGPIO1 LPGPIO1_S #define LPGPIO1_BASE LPGPIO1_BASE_S #define PWR PWR_S #define PWR_BASE PWR_BASE_S #define RAMCFG_SRAM1 RAMCFG_SRAM1_S #define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S #define RAMCFG_SRAM2 RAMCFG_SRAM2_S #define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S #define RAMCFG_SRAM3 RAMCFG_SRAM3_S #define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S #define RAMCFG_SRAM4 RAMCFG_SRAM4_S #define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S #define RAMCFG_BKPRAM RAMCFG_BKPRAM_S #define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S #define EXTI EXTI_S #define EXTI_BASE EXTI_BASE_S #define ICACHE ICACHE_S #define ICACHE_BASE ICACHE_BASE_S #define DCACHE1 DCACHE1_S #define DCACHE1_BASE DCACHE1_BASE_S #define GTZC_TZSC1 GTZC_TZSC1_S #define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S #define GTZC_TZSC2 GTZC_TZSC2_S #define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S #define GTZC_TZIC1 GTZC_TZIC1_S #define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S #define GTZC_TZIC2 GTZC_TZIC2_S #define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S #define GTZC_MPCBB1 GTZC_MPCBB1_S #define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S #define GTZC_MPCBB2 GTZC_MPCBB2_S #define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S #define GTZC_MPCBB3 GTZC_MPCBB3_S #define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S #define GTZC_MPCBB4 GTZC_MPCBB4_S #define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S #define RTC RTC_S #define RTC_BASE RTC_BASE_S #define TAMP TAMP_S #define TAMP_BASE TAMP_BASE_S #define TIM1 TIM1_S #define TIM1_BASE TIM1_BASE_S #define TIM2 TIM2_S #define TIM2_BASE TIM2_BASE_S #define TIM3 TIM3_S #define TIM3_BASE TIM3_BASE_S #define TIM4 TIM4_S #define TIM4_BASE TIM4_BASE_S #define TIM5 TIM5_S #define TIM5_BASE TIM5_BASE_S #define TIM6 TIM6_S #define TIM6_BASE TIM6_BASE_S #define TIM7 TIM7_S #define TIM7_BASE TIM7_BASE_S #define TIM8 TIM8_S #define TIM8_BASE TIM8_BASE_S #define TIM15 TIM15_S #define TIM15_BASE TIM15_BASE_S #define TIM16 TIM16_S #define TIM16_BASE TIM16_BASE_S #define TIM17 TIM17_S #define TIM17_BASE TIM17_BASE_S #define WWDG WWDG_S #define WWDG_BASE WWDG_BASE_S #define IWDG IWDG_S #define IWDG_BASE IWDG_BASE_S #define SPI1 SPI1_S #define SPI1_BASE SPI1_BASE_S #define SPI2 SPI2_S #define SPI2_BASE SPI2_BASE_S #define SPI3 SPI3_S #define SPI3_BASE SPI3_BASE_S #define USART1 USART1_S #define USART1_BASE USART1_BASE_S #define USART2 USART2_S #define USART2_BASE USART2_BASE_S #define USART3 USART3_S #define USART3_BASE USART3_BASE_S #define UART4 UART4_S #define UART4_BASE UART4_BASE_S #define UART5 UART5_S #define UART5_BASE UART5_BASE_S #define I2C1 I2C1_S #define I2C1_BASE I2C1_BASE_S #define I2C2 I2C2_S #define I2C2_BASE I2C2_BASE_S #define I2C3 I2C3_S #define I2C3_BASE I2C3_BASE_S #define I2C4 I2C4_S #define I2C4_BASE I2C4_BASE_S #define CRS CRS_S #define CRS_BASE CRS_BASE_S #define FDCAN1 FDCAN1_S #define FDCAN1_BASE FDCAN1_BASE_S #define FDCAN_CONFIG FDCAN_CONFIG_S #define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S #define SRAMCAN_BASE SRAMCAN_BASE_S #define DAC DAC_S #define DAC_BASE DAC_BASE_S #define DAC1 DAC1_S #define DAC1_BASE DAC1_BASE_S #define OPAMP OPAMP_S #define OPAMP_BASE OPAMP_BASE_S #define OPAMP1 OPAMP1_S #define OPAMP1_BASE OPAMP1_BASE_S #define OPAMP2 OPAMP2_S #define OPAMP2_BASE OPAMP2_BASE_S #define LPTIM1 LPTIM1_S #define LPTIM1_BASE LPTIM1_BASE_S #define LPTIM2 LPTIM2_S #define LPTIM2_BASE LPTIM2_BASE_S #define LPTIM3 LPTIM3_S #define LPTIM3_BASE LPTIM3_BASE_S #define LPTIM4 LPTIM4_S #define LPTIM4_BASE LPTIM4_BASE_S #define LPUART1 LPUART1_S #define LPUART1_BASE LPUART1_BASE_S #define UCPD1 UCPD1_S #define UCPD1_BASE UCPD1_BASE_S #define SYSCFG SYSCFG_S #define SYSCFG_BASE SYSCFG_BASE_S #define VREFBUF VREFBUF_S #define VREFBUF_BASE VREFBUF_BASE_S #define COMP12 COMP12_S #define COMP12_BASE COMP12_BASE_S #define COMP1 COMP1_S #define COMP1_BASE COMP1_BASE_S #define COMP2 COMP2_S #define COMP2_BASE COMP2_BASE_S #define COMP12_COMMON COMP12_COMMON_S #define COMP12_COMMON_BASE COMP1_BASE_S #define SAI1 SAI1_S #define SAI1_BASE SAI1_BASE_S #define SAI1_Block_A SAI1_Block_A_S #define SAI1_Block_A_BASE SAI1_Block_A_BASE_S #define SAI1_Block_B SAI1_Block_B_S #define SAI1_Block_B_BASE SAI1_Block_B_BASE_S #define SAI2 SAI2_S #define SAI2_BASE SAI2_BASE_S #define SAI2_Block_A SAI2_Block_A_S #define SAI2_Block_A_BASE SAI2_Block_A_BASE_S #define SAI2_Block_B SAI2_Block_B_S #define SAI2_Block_B_BASE SAI2_Block_B_BASE_S #define CRC CRC_S #define CRC_BASE CRC_BASE_S #define TSC TSC_S #define TSC_BASE TSC_BASE_S #define ADC1 ADC1_S #define ADC1_BASE ADC1_BASE_S #define ADC12_COMMON ADC12_COMMON_S #define ADC12_COMMON_BASE ADC12_COMMON_BASE_S #define ADC4 ADC4_S #define ADC4_BASE ADC4_BASE_S #define ADC4_COMMON ADC4_COMMON_S #define ADC4_COMMON_BASE ADC4_COMMON_BASE_S #define HASH HASH_S #define HASH_BASE HASH_BASE_S #define HASH_DIGEST HASH_DIGEST_S #define HASH_DIGEST_BASE HASH_DIGEST_BASE_S #define RNG RNG_S #define RNG_BASE RNG_BASE_S #define SDMMC1 SDMMC1_S #define SDMMC1_BASE SDMMC1_BASE_S #define SDMMC2 SDMMC2_S #define SDMMC2_BASE SDMMC2_BASE_S #define FMC_Bank1_R FMC_Bank1_R_S #define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S #define FMC_Bank1E_R FMC_Bank1E_R_S #define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S #define FMC_Bank3_R FMC_Bank3_R_S #define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S #define OCTOSPI1 OCTOSPI1_S #define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S #define OCTOSPI2 OCTOSPI2_S #define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S #define OCTOSPIM OCTOSPIM_S #define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S #define DLYB_SDMMC1 DLYB_SDMMC1_S #define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S #define DLYB_SDMMC2 DLYB_SDMMC2_S #define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S #define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S #define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S #define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S #define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S #define DMA2D DMA2D_S #define DMA2D_BASE DMA2D_BASE_S #define USB_OTG_FS USB_OTG_FS_S #define USB_OTG_FS_BASE USB_OTG_FS_BASE_S #define MDF1 MDF1_S #define MDF1_BASE MDF1_BASE_S #define MDF1_Filter0 MDF1_Filter0_S #define MDF1_Filter0_BASE MDF1_Filter0_BASE_S #define MDF1_Filter1 MDF1_Filter1_S #define MDF1_Filter1_BASE MDF1_Filter1_BASE_S #define MDF1_Filter2 MDF1_Filter2_S #define MDF1_Filter2_BASE MDF1_Filter2_BASE_S #define MDF1_Filter3 MDF1_Filter3_S #define MDF1_Filter3_BASE MDF1_Filter3_BASE_S #define MDF1_Filter4 MDF1_Filter4_S #define MDF1_Filter4_BASE MDF1_Filter4_BASE_S #define MDF1_Filter5 MDF1_Filter5_S #define MDF1_Filter5_BASE MDF1_Filter5_BASE_S #define ADF1 ADF1_S #define ADF1_BASE ADF1_BASE_S #define ADF1_Filter0 ADF1_Filter0_S #define ADF1_Filter0_BASE ADF1_Filter0_BASE_S #else /*!< Memory base addresses for Non secure peripherals */ #define FLASH_BASE FLASH_BASE_NS #define SRAM1_BASE SRAM1_BASE_NS #define SRAM2_BASE SRAM2_BASE_NS #define SRAM3_BASE SRAM3_BASE_NS #define SRAM4_BASE SRAM4_BASE_NS #define BKPSRAM_BASE BKPSRAM_BASE_NS #define PERIPH_BASE PERIPH_BASE_NS #define APB1PERIPH_BASE APB1PERIPH_BASE_NS #define APB2PERIPH_BASE APB2PERIPH_BASE_NS #define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS #define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS /*!< Instance aliases and base addresses for Non secure peripherals */ #define CORDIC CORDIC_NS #define CORDIC_BASE CORDIC_BASE_NS #define RCC RCC_NS #define RCC_BASE RCC_BASE_NS #define DMA2D DMA2D_NS #define DMA2D_BASE DMA2D_BASE_NS #define DCMI DCMI_NS #define DCMI_BASE DCMI_BASE_NS #define PSSI PSSI_NS #define PSSI_BASE PSSI_BASE_NS #define FLASH FLASH_NS #define FLASH_R_BASE FLASH_R_BASE_NS #define FMAC FMAC_NS #define FMAC_BASE FMAC_BASE_NS #define GPDMA1 GPDMA1_NS #define GPDMA1_BASE GPDMA1_BASE_NS #define GPDMA1_Channel0 GPDMA1_Channel0_NS #define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS #define GPDMA1_Channel1 GPDMA1_Channel1_NS #define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS #define GPDMA1_Channel2 GPDMA1_Channel2_NS #define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS #define GPDMA1_Channel3 GPDMA1_Channel3_NS #define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS #define GPDMA1_Channel4 GPDMA1_Channel4_NS #define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS #define GPDMA1_Channel5 GPDMA1_Channel5_NS #define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS #define GPDMA1_Channel6 GPDMA1_Channel6_NS #define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS #define GPDMA1_Channel7 GPDMA1_Channel7_NS #define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS #define GPDMA1_Channel8 GPDMA1_Channel8_NS #define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS #define GPDMA1_Channel9 GPDMA1_Channel9_NS #define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS #define GPDMA1_Channel10 GPDMA1_Channel10_NS #define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS #define GPDMA1_Channel11 GPDMA1_Channel11_NS #define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS #define GPDMA1_Channel12 GPDMA1_Channel12_NS #define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS #define GPDMA1_Channel13 GPDMA1_Channel13_NS #define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS #define GPDMA1_Channel14 GPDMA1_Channel14_NS #define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS #define GPDMA1_Channel15 GPDMA1_Channel15_NS #define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS #define LPDMA1 LPDMA1_NS #define LPDMA1_BASE LPDMA1_BASE_NS #define LPDMA1_Channel0 LPDMA1_Channel0_NS #define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS #define LPDMA1_Channel1 LPDMA1_Channel1_NS #define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS #define LPDMA1_Channel2 LPDMA1_Channel2_NS #define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS #define LPDMA1_Channel3 LPDMA1_Channel3_NS #define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS #define GPIOA GPIOA_NS #define GPIOA_BASE GPIOA_BASE_NS #define GPIOB GPIOB_NS #define GPIOB_BASE GPIOB_BASE_NS #define GPIOC GPIOC_NS #define GPIOC_BASE GPIOC_BASE_NS #define GPIOD GPIOD_NS #define GPIOD_BASE GPIOD_BASE_NS #define GPIOE GPIOE_NS #define GPIOE_BASE GPIOE_BASE_NS #define GPIOF GPIOF_NS #define GPIOF_BASE GPIOF_BASE_NS #define GPIOG GPIOG_NS #define GPIOG_BASE GPIOG_BASE_NS #define GPIOH GPIOH_NS #define GPIOH_BASE GPIOH_BASE_NS #define GPIOI GPIOI_NS #define GPIOI_BASE GPIOI_BASE_NS #define LPGPIO1 LPGPIO1_NS #define LPGPIO1_BASE LPGPIO1_BASE_NS #define PWR PWR_NS #define PWR_BASE PWR_BASE_NS #define RAMCFG_SRAM1 RAMCFG_SRAM1_NS #define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS #define RAMCFG_SRAM2 RAMCFG_SRAM2_NS #define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS #define RAMCFG_SRAM3 RAMCFG_SRAM3_NS #define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS #define RAMCFG_SRAM4 RAMCFG_SRAM4_NS #define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS #define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS #define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS #define EXTI EXTI_NS #define EXTI_BASE EXTI_BASE_NS #define ICACHE ICACHE_NS #define ICACHE_BASE ICACHE_BASE_NS #define DCACHE1 DCACHE1_NS #define DCACHE1_BASE DCACHE1_BASE_NS #define GTZC_TZSC1 GTZC_TZSC1_NS #define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS #define GTZC_TZSC2 GTZC_TZSC2_NS #define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS #define GTZC_TZIC1 GTZC_TZIC1_NS #define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS #define GTZC_TZIC2 GTZC_TZIC2_NS #define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS #define GTZC_MPCBB1 GTZC_MPCBB1_NS #define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS #define GTZC_MPCBB2 GTZC_MPCBB2_NS #define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS #define GTZC_MPCBB3 GTZC_MPCBB3_NS #define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS #define GTZC_MPCBB4 GTZC_MPCBB4_NS #define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS #define RTC RTC_NS #define RTC_BASE RTC_BASE_NS #define TAMP TAMP_NS #define TAMP_BASE TAMP_BASE_NS #define TIM1 TIM1_NS #define TIM1_BASE TIM1_BASE_NS #define TIM2 TIM2_NS #define TIM2_BASE TIM2_BASE_NS #define TIM3 TIM3_NS #define TIM3_BASE TIM3_BASE_NS #define TIM4 TIM4_NS #define TIM4_BASE TIM4_BASE_NS #define TIM5 TIM5_NS #define TIM5_BASE TIM5_BASE_NS #define TIM6 TIM6_NS #define TIM6_BASE TIM6_BASE_NS #define TIM7 TIM7_NS #define TIM7_BASE TIM7_BASE_NS #define TIM8 TIM8_NS #define TIM8_BASE TIM8_BASE_NS #define TIM15 TIM15_NS #define TIM15_BASE TIM15_BASE_NS #define TIM16 TIM16_NS #define TIM16_BASE TIM16_BASE_NS #define TIM17 TIM17_NS #define TIM17_BASE TIM17_BASE_NS #define WWDG WWDG_NS #define WWDG_BASE WWDG_BASE_NS #define IWDG IWDG_NS #define IWDG_BASE IWDG_BASE_NS #define SPI1 SPI1_NS #define SPI1_BASE SPI1_BASE_NS #define SPI2 SPI2_NS #define SPI2_BASE SPI2_BASE_NS #define SPI3 SPI3_NS #define SPI3_BASE SPI3_BASE_NS #define USART1 USART1_NS #define USART1_BASE USART1_BASE_NS #define USART2 USART2_NS #define USART2_BASE USART2_BASE_NS #define USART3 USART3_NS #define USART3_BASE USART3_BASE_NS #define UART4 UART4_NS #define UART4_BASE UART4_BASE_NS #define UART5 UART5_NS #define UART5_BASE UART5_BASE_NS #define I2C1 I2C1_NS #define I2C1_BASE I2C1_BASE_NS #define I2C2 I2C2_NS #define I2C2_BASE I2C2_BASE_NS #define I2C3 I2C3_NS #define I2C3_BASE I2C3_BASE_NS #define I2C4 I2C4_NS #define I2C4_BASE I2C4_BASE_NS #define CRS CRS_NS #define CRS_BASE CRS_BASE_NS #define FDCAN1 FDCAN1_NS #define FDCAN1_BASE FDCAN1_BASE_NS #define FDCAN_CONFIG FDCAN_CONFIG_NS #define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS #define SRAMCAN_BASE SRAMCAN_BASE_NS #define DAC1 DAC1_NS #define DAC1_BASE DAC1_BASE_NS #define OPAMP OPAMP_NS #define OPAMP_BASE OPAMP_BASE_NS #define OPAMP1 OPAMP1_NS #define OPAMP1_BASE OPAMP1_BASE_NS #define OPAMP2 OPAMP2_NS #define OPAMP2_BASE OPAMP2_BASE_NS #define LPTIM1 LPTIM1_NS #define LPTIM1_BASE LPTIM1_BASE_NS #define LPTIM2 LPTIM2_NS #define LPTIM2_BASE LPTIM2_BASE_NS #define LPTIM3 LPTIM3_NS #define LPTIM3_BASE LPTIM3_BASE_NS #define LPTIM4 LPTIM4_NS #define LPTIM4_BASE LPTIM4_BASE_NS #define LPUART1 LPUART1_NS #define LPUART1_BASE LPUART1_BASE_NS #define UCPD1 UCPD1_NS #define UCPD1_BASE UCPD1_BASE_NS #define SYSCFG SYSCFG_NS #define SYSCFG_BASE SYSCFG_BASE_NS #define VREFBUF VREFBUF_NS #define VREFBUF_BASE VREFBUF_BASE_NS #define COMP12 COMP12_NS #define COMP12_BASE COMP12_BASE_NS #define COMP1 COMP1_NS #define COMP1_BASE COMP1_BASE_NS #define COMP2 COMP2_NS #define COMP2_BASE COMP2_BASE_NS #define COMP12_COMMON COMP12_COMMON_NS #define COMP12_COMMON_BASE COMP1_BASE_NS #define SAI1 SAI1_NS #define SAI1_BASE SAI1_BASE_NS #define SAI1_Block_A SAI1_Block_A_NS #define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS #define SAI1_Block_B SAI1_Block_B_NS #define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS #define SAI2 SAI2_NS #define SAI2_BASE SAI2_BASE_NS #define SAI2_Block_A SAI2_Block_A_NS #define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS #define SAI2_Block_B SAI2_Block_B_NS #define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS #define CRC CRC_NS #define CRC_BASE CRC_BASE_NS #define TSC TSC_NS #define TSC_BASE TSC_BASE_NS #define ADC1 ADC1_NS #define ADC1_BASE ADC1_BASE_NS #define ADC12_COMMON ADC12_COMMON_NS #define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS #define ADC4 ADC4_NS #define ADC4_BASE ADC4_BASE_NS #define ADC4_COMMON ADC4_COMMON_NS #define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS #define HASH HASH_NS #define HASH_BASE HASH_BASE_NS #define HASH_DIGEST HASH_DIGEST_NS #define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS #define RNG RNG_NS #define RNG_BASE RNG_BASE_NS #define SDMMC1 SDMMC1_NS #define SDMMC1_BASE SDMMC1_BASE_NS #define SDMMC2 SDMMC2_NS #define SDMMC2_BASE SDMMC2_BASE_NS #define FMC_Bank1_R FMC_Bank1_R_NS #define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS #define FMC_Bank1E_R FMC_Bank1E_R_NS #define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS #define FMC_Bank3_R FMC_Bank3_R_NS #define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS #define OCTOSPI1 OCTOSPI1_NS #define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS #define OCTOSPI2 OCTOSPI2_NS #define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS #define OCTOSPIM OCTOSPIM_NS #define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS #define DLYB_SDMMC1 DLYB_SDMMC1_NS #define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS #define DLYB_SDMMC2 DLYB_SDMMC2_NS #define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS #define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS #define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS #define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS #define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS #define USB_OTG_FS USB_OTG_FS_NS #define USB_OTG_FS_BASE USB_OTG_FS_BASE_NS #define MDF1 MDF1_NS #define MDF1_BASE MDF1_BASE_NS #define MDF1_Filter0 MDF1_Filter0_NS #define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS #define MDF1_Filter1 MDF1_Filter1_NS #define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS #define MDF1_Filter2 MDF1_Filter2_NS #define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS #define MDF1_Filter3 MDF1_Filter3_NS #define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS #define MDF1_Filter4 MDF1_Filter4_NS #define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS #define MDF1_Filter5 MDF1_Filter5_NS #define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS #define ADF1 ADF1_NS #define ADF1_BASE ADF1_BASE_NS #define ADF1_Filter0 ADF1_Filter0_NS #define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS #endif /** @addtogroup Hardware_Constant_Definition * @{ */ #define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ /** * @} */ /******************************************************************************/ /* */ /* Analog to Digital Converter */ /* */ /******************************************************************************/ /******************************* ADC VERSION ********************************/ #define ADC_VER_V5_X /******************** Bit definition for ADC_ISR register ********************/ #define ADC_ISR_ADRDY_Pos (0U) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ #define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ #define ADC_ISR_EOS_Pos (3U) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ #define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ #define ADC_ISR_JEOC_Pos (5U) #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ #define ADC_ISR_JEOS_Pos (6U) #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ #define ADC_ISR_AWD1_Pos (7U) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ #define ADC_ISR_EOCAL_Pos (11U) #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ #define ADC_ISR_LDORDY_Pos (12U) #define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ #define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ #define ADC_IER_EOSMPIE_Pos (1U) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ #define ADC_IER_EOCIE_Pos (2U) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ #define ADC_IER_EOSIE_Pos (3U) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ #define ADC_IER_OVRIE_Pos (4U) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ #define ADC_IER_JEOCIE_Pos (5U) #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ #define ADC_IER_JEOSIE_Pos (6U) #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ #define ADC_IER_AWD1IE_Pos (7U) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ #define ADC_IER_AWD2IE_Pos (8U) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ #define ADC_IER_AWD3IE_Pos (9U) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ #define ADC_IER_JQOVFIE_Pos (10U) #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ #define ADC_IER_EOCALIE_Pos (11U) #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ #define ADC_IER_LDORDYIE_Pos (12U) #define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ #define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ #define ADC_CR_ADDIS_Pos (1U) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ #define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ #define ADC_CR_JADSTART_Pos (3U) #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ #define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ #define ADC_CR_JADSTP_Pos (5U) #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ #define ADC_CR_ADCALLIN_Pos (16U) #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ #define ADC_CR_CALINDEX0_Pos (24U) #define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ #define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC Linearity calibration ready Word 3 */ #define ADC_CR_CALINDEX1_Pos (25U) #define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ #define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC Linearity calibration ready Word 4 */ #define ADC_CR_CALINDEX2_Pos (26U) #define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ #define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC Linearity calibration ready Word 5 */ #define ADC_CR_CALINDEX3_Pos (27U) #define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ #define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC Linearity calibration ready Word 6 */ #define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ #define ADC_CR_DEEPPWD_Pos (29U) #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ #define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ /******************** Bit definition for ADC_CFGR register ********************/ #define ADC_CFGR1_DMNGT_Pos (0U) #define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ #define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ #define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ #define ADC_CFGR1_RES_Pos (2U) #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ #define ADC4_CFGR1_DMAEN_Pos (0U) #define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ #define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC4_CFGR1_DMACFG_Pos (1U) #define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ #define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC4_CFGR1_SCANDIR_Pos (4U) #define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ #define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ #define ADC4_CFGR1_ALIGN_Pos (5U) #define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ #define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (5U) #define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ #define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ #define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR1_EXTEN_Pos (10U) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR1_OVRMOD_Pos (12U) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ #define ADC_CFGR1_CONT_Pos (13U) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ #define ADC_CFGR1_AUTDLY_Pos (14U) #define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ #define ADC4_CFGR1_WAIT_Pos (14U) #define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ #define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ #define ADC_CFGR1_DISCEN_Pos (16U) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ #define ADC_CFGR1_DISCNUM_Pos (17U) #define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ #define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR1_JDISCEN_Pos (20U) #define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ #define ADC_CFGR1_AWD1SGL_Pos (22U) #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ #define ADC_CFGR1_AWD1EN_Pos (23U) #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ #define ADC_CFGR1_JAWD1EN_Pos (24U) #define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ #define ADC_CFGR1_JAUTO_Pos (25U) #define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6U) #define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ #define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ #define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21U) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ #define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ #define ADC_CFGR1_AWD1CH_Pos (26U) #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_CFGR2 register ********************/ #define ADC_CFGR2_ROVSE_Pos (0U) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ #define ADC_CFGR2_JOVSE_Pos (1U) #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ #define ADC_CFGR2_OVSR_Pos (16U) #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ #define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ #define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ #define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ #define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ #define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ #define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ #define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_BULB_Pos (13U) #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ #define ADC_CFGR2_SWTRIG_Pos (14U) #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ #define ADC_CFGR2_SMPTRIG_Pos (15U) #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ #define ADC_CFGR2_LFTRIG_Pos (27U) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ #define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ /* Specific ADC4 */ #define ADC4_CFGR2_OVSR_Pos (2U) #define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC4_CFGR2_LFTRIG_Pos (29U) #define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ #define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ #define ADC4_SMPR_SMP1_Pos (0U) #define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ #define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ #define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ #define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ #define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ #define ADC4_SMPR_SMP2_Pos (4U) #define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ #define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ #define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ #define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ #define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ #define ADC4_SMPR_SMPSEL_Pos (8U) #define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ #define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ #define ADC4_SMPR_SMPSEL0_Pos (8U) #define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ #define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ #define ADC4_SMPR_SMPSEL1_Pos (9U) #define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ #define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ #define ADC4_SMPR_SMPSEL2_Pos (10U) #define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ #define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ #define ADC4_SMPR_SMPSEL3_Pos (11U) #define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ #define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ #define ADC4_SMPR_SMPSEL4_Pos (12U) #define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ #define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ #define ADC4_SMPR_SMPSEL5_Pos (13U) #define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ #define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ #define ADC4_SMPR_SMPSEL6_Pos (14U) #define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ #define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ #define ADC4_SMPR_SMPSEL7_Pos (15U) #define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ #define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ #define ADC4_SMPR_SMPSEL8_Pos (16U) #define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ #define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ #define ADC4_SMPR_SMPSEL9_Pos (17U) #define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ #define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ #define ADC4_SMPR_SMPSEL10_Pos (18U) #define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ #define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ #define ADC4_SMPR_SMPSEL11_Pos (19U) #define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ #define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ #define ADC4_SMPR_SMPSEL12_Pos (20U) #define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ #define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ #define ADC4_SMPR_SMPSEL13_Pos (21U) #define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ #define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ #define ADC4_SMPR_SMPSEL14_Pos (22U) #define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ #define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ #define ADC4_SMPR_SMPSEL15_Pos (23U) #define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ #define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ #define ADC4_SMPR_SMPSEL16_Pos (24U) #define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ #define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ #define ADC4_SMPR_SMPSEL17_Pos (25U) #define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ #define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ #define ADC4_SMPR_SMPSEL18_Pos (26U) #define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ #define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ #define ADC4_SMPR_SMPSEL19_Pos (27U) #define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ #define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ #define ADC4_SMPR_SMPSEL20_Pos (26U) #define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ #define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ #define ADC4_SMPR_SMPSEL21_Pos (26U) #define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ #define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ #define ADC4_SMPR_SMPSEL22_Pos (30U) #define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ #define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ #define ADC4_SMPR_SMPSEL23_Pos (31U) #define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ #define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ /******************** Bit definition for ADC_SMPR2 register ********************/ #define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ #define ADC_SMPR2_SMP19_Pos (27U) #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_PCSEL register ********************/ #define ADC_PCSEL_PCSEL_Pos (0U) #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ #define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ #define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ #define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ #define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ #define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ #define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ #define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ #define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ #define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ #define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ #define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ #define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ #define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ #define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ #define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ #define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ #define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ #define ADC_LTR_LT_Pos (0U) #define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ /***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ #define ADC_HTR_HT_Pos (0U) #define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ #define ADC_HTR_AWDFILT_Pos (29U) #define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ #define ADC_HTR_AWDFILT ADC_HTR_HT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ #define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ #define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ #define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ********************/ #define ADC_SQR2_SQ5_Pos (0U) #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ********************/ #define ADC_SQR3_SQ10_Pos (0U) #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ********************/ #define ADC_SQR4_SQ15_Pos (0U) #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ /******************** Bit definition for ADC_PW register ********************/ #define ADC4_PW_AUTOFF_Pos (0U) #define ADC4_PW_AUTOFF_Msk (0x1UL << ADC4_PW_AUTOFF_Pos) /*!< 0x00000001 */ #define ADC4_PW_AUTOFF ADC4_PW_AUTOFF_Msk /*!< ADC Auto-Off mode */ #define ADC4_PW_DPD_Pos (1U) #define ADC4_PW_DPD_Msk (0x1UL << ADC4_PW_DPD_Pos) /*!< 0x00000002 */ #define ADC4_PW_DPD ADC4_PW_DPD_Msk /*!< ADC Deep Power mode */ #define ADC4_PW_VREFPROT_Pos (2U) #define ADC4_PW_VREFPROT_Msk (0x1UL << ADC4_PW_VREFPROT_Pos) /*!< 0x00000004 */ #define ADC4_PW_VREFPROT ADC4_PW_VREFPROT_Msk /*!< ADC Vref protection */ #define ADC4_PW_VREFSECSMP_Pos (3U) #define ADC4_PW_VREFSECSMP_Msk (0x1UL << ADC4_PW_VREFSECSMP_Pos) /*!< 0x00000008 */ #define ADC4_PW_VREFSECSMP ADC4_PW_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ /******************** Bit definition for ADC_JSQR register ********************/ #define ADC_JSQR_JL_Pos (0U) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ #define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JEXTEN_Pos (7U) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ1_Pos (9U) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ2_Pos (15U) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ #define ADC_JSQR_JSQ3_Pos (21U) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ #define ADC_JSQR_JSQ4_Pos (27U) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ********************/ #define ADC_OFR1_OFFSET1_Pos (0U) #define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ #define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ #define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ #define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ #define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ #define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ #define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ #define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ #define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ #define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ #define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ #define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ #define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ #define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ #define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ #define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ #define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ #define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ #define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ #define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ #define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ #define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ #define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ #define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ #define ADC_OFR1_OFFSETPOS_Pos (24U) #define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ #define ADC_OFR1_USAT_Pos (25U) #define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ #define ADC_OFR1_SSAT_Pos (26U) #define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ #define ADC_OFR1_OFFSET1_CH_Pos (27U) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR2 register ********************/ #define ADC_OFR2_OFFSET2_Pos (0U) #define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ #define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ #define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ #define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ #define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ #define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ #define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ #define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ #define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ #define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ #define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ #define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ #define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ #define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ #define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ #define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ #define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ #define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ #define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ #define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ #define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ #define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ #define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ #define ADC_OFR2_OFFSETPOS_Pos (24U) #define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ #define ADC_OFR2_USAT_Pos (25U) #define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ #define ADC_OFR2_SSAT_Pos (26U) #define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ #define ADC_OFR2_OFFSET2_CH_Pos (27U) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR3 register ********************/ #define ADC_OFR3_OFFSET3_Pos (0U) #define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ #define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ #define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ #define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ #define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ #define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ #define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ #define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ #define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ #define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ #define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ #define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ #define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ #define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ #define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ #define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ #define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ #define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ #define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ #define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ #define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ #define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ #define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ #define ADC_OFR3_OFFSETPOS_Pos (24U) #define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ #define ADC_OFR3_USAT_Pos (25U) #define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ #define ADC_OFR3_SSAT_Pos (26U) #define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ #define ADC_OFR3_OFFSET3_CH_Pos (27U) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR4 register ********************/ #define ADC_OFR4_OFFSET4_Pos (0U) #define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ #define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ #define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ #define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ #define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ #define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ #define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ #define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ #define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ #define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ #define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ #define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ #define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ #define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ #define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ #define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ #define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ #define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ #define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ #define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ #define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ #define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ #define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ #define ADC_OFR4_OFFSETPOS_Pos (24U) #define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ #define ADC_OFR4_USAT_Pos (25U) #define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ #define ADC_OFR4_SSAT_Pos (26U) #define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ #define ADC_OFR4_OFFSET4_CH_Pos (27U) #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_GCOMP register ********************/ #define ADC_GCOMP_GCOMPCOEFF_Pos (0U) #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ #define ADC_GCOMP_GCOMP_Pos (31U) #define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ #define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_AWD2CR register ********************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ #define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ #define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ #define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ #define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_AWD1TR register *******************/ #define ADC_AWD1TR_LT1_Pos (0U) #define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ #define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ #define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ #define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ #define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ #define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ #define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ #define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ #define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ #define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ #define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ #define ADC_AWD1TR_HT1_Pos (16U) #define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ #define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ #define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ #define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ #define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ #define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ #define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ #define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ #define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ #define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ #define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ #define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_AWDTR2 register *******************/ #define ADC_AWD2TR_LT2_Pos (0U) #define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ #define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ #define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ #define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ #define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ #define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ #define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ #define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ #define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ #define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ #define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ #define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ #define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ #define ADC_AWD2TR_HT2_Pos (16U) #define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ #define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ #define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ #define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ #define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ #define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ #define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ #define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ #define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ #define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ #define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ #define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_CHSELR register ****************/ #define ADC_CHSELR_CHSEL_Pos (0U) #define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL0_Pos (0U) #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL1_Pos (1U) #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL2_Pos (2U) #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL3_Pos (3U) #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL4_Pos (4U) #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL5_Pos (5U) #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL6_Pos (6U) #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL7_Pos (7U) #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL8_Pos (8U) #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL9_Pos (9U) #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL10_Pos (10U) #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL11_Pos (11U) #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL12_Pos (12U) #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL13_Pos (13U) #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL14_Pos (14U) #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL15_Pos (15U) #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL16_Pos (16U) #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL17_Pos (17U) #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL18_Pos (18U) #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL19_Pos (19U) #define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL20_Pos (20U) #define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL21_Pos (21U) #define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL22_Pos (22U) #define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL23_Pos (23U) #define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_SQ_ALL_Pos (0U) #define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ #define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ1_Pos (0U) #define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ #define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ #define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ #define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ #define ADC_CHSELR_SQ2_Pos (4U) #define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ #define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ #define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ #define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ #define ADC_CHSELR_SQ3_Pos (8U) #define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ #define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ #define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ #define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ #define ADC_CHSELR_SQ4_Pos (12U) #define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ #define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ #define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ #define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ #define ADC_CHSELR_SQ5_Pos (16U) #define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ #define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ #define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ #define ADC_CHSELR_SQ6_Pos (20U) #define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ #define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ #define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ #define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ #define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ #define ADC_CHSELR_SQ7_Pos (24U) #define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ #define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ #define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ #define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ #define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ #define ADC_CHSELR_SQ8_Pos (28U) #define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ #define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ #define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ #define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_AWD3TR register *******************/ #define ADC_AWD3TR_LT3_Pos (0U) #define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ #define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ #define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ #define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ #define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ #define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ #define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ #define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ #define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ #define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ #define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ #define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ #define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ #define ADC_AWD3TR_HT3_Pos (16U) #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ #define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ #define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ #define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_AWD3CR register ********************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ #define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ #define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ #define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ #define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_DIFSEL register ********************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_CALFACT register ********************/ #define ADC_CALFACT_I_APB_ADDR_Pos (0U) #define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ #define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ #define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ #define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ #define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ #define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ #define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ #define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ #define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ #define ADC_CALFACT_I_APB_DATA_Pos (08U) #define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ #define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ #define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ #define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ #define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ #define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ #define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ #define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ #define ADC_CALFACT_VALIDITY_Pos (16U) #define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ #define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ #define ADC_CALFACT_LATCH_COEF_Pos (24U) #define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ #define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ #define ADC_CALFACT_CAPTURE_COEF_Pos (25U) #define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ #define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ #define ADC4_CALFACT_CALFACT_Pos (0U) #define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ #define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ #define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ #define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ #define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ #define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ #define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ #define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ /******************** Bit definition for ADC_CALFACT2 register ********************/ #define ADC_CALFACT2_CALFACT_Pos (0U) #define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ #define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ #define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ #define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ #define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ #define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ #define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ #define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ #define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ #define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ #define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ #define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ #define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ #define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ #define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ #define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ #define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ #define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ #define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ #define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ #define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ #define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ #define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ #define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ #define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ #define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ #define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ #define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ #define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ #define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ #define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ #define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ #define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ #define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OR register ********************/ #define ADC_OR_CHN0SEL_Pos (0U) #define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ #define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_PRESC_Pos (18U) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ #define ADC_CCR_VSENSEEN_Pos (23U) #define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ #define ADC_CCR_LFMEN_Pos (25U) #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ #define ADC_CCR_VDDCOREN_Pos (26U) #define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ #define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ /******************************************************************************/ /* */ /* CORDIC calculation unit */ /* */ /******************************************************************************/ /******************* Bit definition for CORDIC_CSR register *****************/ #define CORDIC_CSR_FUNC_Pos (0U) #define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ #define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ #define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ #define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ #define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ #define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ #define CORDIC_CSR_PRECISION_Pos (4U) #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ #define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ #define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ #define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ #define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ #define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ #define CORDIC_CSR_SCALE_Pos (8U) #define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ #define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ #define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ #define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ #define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ #define CORDIC_CSR_IEN_Pos (16U) #define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ #define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ #define CORDIC_CSR_DMAREN_Pos (17U) #define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ #define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ #define CORDIC_CSR_DMAWEN_Pos (18U) #define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ #define CORDIC_CSR_NRES_Pos (19U) #define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ #define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ #define CORDIC_CSR_NARGS_Pos (20U) #define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ #define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ #define CORDIC_CSR_RESSIZE_Pos (21U) #define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ #define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ #define CORDIC_CSR_ARGSIZE_Pos (22U) #define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ #define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ #define CORDIC_CSR_RRDY_Pos (31U) #define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ #define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ /******************* Bit definition for CORDIC_WDATA register ***************/ #define CORDIC_WDATA_ARG_Pos (0U) #define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ /******************* Bit definition for CORDIC_RDATA register ***************/ #define CORDIC_RDATA_RES_Pos (0U) #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ /******************************************************************************/ /* */ /* CRC calculation unit */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ #define CRC_CR_POLYSIZE_Pos (3U) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ #define CRC_CR_REV_IN_Pos (5U) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ #define CRC_CR_REV_OUT_Pos (7U) #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ #define CRC_INIT_INIT_Pos (0U) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ #define CRC_POL_POL_Pos (0U) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ /* CRS Clock Recovery System */ /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ #define CRS_CR_SYNCOKIE_Pos (0U) #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ #define CRS_CR_SYNCWARNIE_Pos (1U) #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ #define CRS_CR_ERRIE_Pos (2U) #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ #define CRS_CR_ESYNCIE_Pos (3U) #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ #define CRS_CR_CEN_Pos (5U) #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ #define CRS_CR_AUTOTRIMEN_Pos (6U) #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ #define CRS_CR_SWSYNC_Pos (7U) #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ #define CRS_CFGR_RELOAD_Pos (0U) #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ #define CRS_CFGR_FELIM_Pos (16U) #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ #define CRS_CFGR_SYNCDIV_Pos (24U) #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ #define CRS_CFGR_SYNCSRC_Pos (28U) #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ #define CRS_CFGR_SYNCPOL_Pos (31U) #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ #define CRS_ISR_SYNCOKF_Pos (0U) #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ #define CRS_ISR_SYNCWARNF_Pos (1U) #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ #define CRS_ISR_ERRF_Pos (2U) #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ #define CRS_ISR_ESYNCF_Pos (3U) #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ #define CRS_ISR_SYNCERR_Pos (8U) #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ #define CRS_ISR_SYNCMISS_Pos (9U) #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ #define CRS_ISR_TRIMOVF_Pos (10U) #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ #define CRS_ISR_FEDIR_Pos (15U) #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ #define CRS_ISR_FECAP_Pos (16U) #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ #define CRS_ICR_SYNCOKC_Pos (0U) #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ #define CRS_ICR_SYNCWARNC_Pos (1U) #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ #define CRS_ICR_ERRC_Pos (2U) #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ #define CRS_ICR_ESYNCC_Pos (3U) #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ /******************************************************************************/ /* */ /* RNG */ /* */ /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk #define RNG_CR_IE_Pos (3U) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ #define RNG_CR_IE RNG_CR_IE_Msk #define RNG_CR_CED_Pos (5U) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ #define RNG_CR_CED RNG_CR_CED_Msk #define RNG_CR_ARDIS_Pos (7U) #define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) #define RNG_CR_ARDIS RNG_CR_ARDIS_Msk #define RNG_CR_RNG_CONFIG3_Pos (8U) #define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) #define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk #define RNG_CR_NISTC_Pos (12U) #define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) #define RNG_CR_NISTC RNG_CR_NISTC_Msk #define RNG_CR_RNG_CONFIG2_Pos (13U) #define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) #define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk #define RNG_CR_CONDRST_Pos (30U) #define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) #define RNG_CR_CONDRST RNG_CR_CONDRST_Msk #define RNG_CR_CONFIGLOCK_Pos (31U) #define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) #define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ #define RNG_SR_DRDY RNG_SR_DRDY_Msk #define RNG_SR_CECS_Pos (1U) #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ #define RNG_SR_CECS RNG_SR_CECS_Msk #define RNG_SR_SECS_Pos (2U) #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_CEIS_Pos (5U) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk #define RNG_SR_SEIS_Pos (6U) #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk /******************** Bits definition for RNG_HTCR register *******************/ #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************************************************************************/ /* */ /* Digital to Analog Converter */ /* */ /******************************************************************************/ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1_Pos (0U) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) #define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ #define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) /******************* Bits definition for FLASH_ACR register *****************/ #define FLASH_ACR_LATENCY_Pos (0U) #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000U) #define FLASH_ACR_LATENCY_1WS (0x00000001U) #define FLASH_ACR_LATENCY_2WS (0x00000002U) #define FLASH_ACR_LATENCY_3WS (0x00000003U) #define FLASH_ACR_LATENCY_4WS (0x00000004U) #define FLASH_ACR_LATENCY_5WS (0x00000005U) #define FLASH_ACR_LATENCY_6WS (0x00000006U) #define FLASH_ACR_LATENCY_7WS (0x00000007U) #define FLASH_ACR_LATENCY_8WS (0x00000008U) #define FLASH_ACR_LATENCY_9WS (0x00000009U) #define FLASH_ACR_LATENCY_10WS (0x0000000AU) #define FLASH_ACR_LATENCY_11WS (0x0000000BU) #define FLASH_ACR_LATENCY_12WS (0x0000000CU) #define FLASH_ACR_LATENCY_13WS (0x0000000DU) #define FLASH_ACR_LATENCY_14WS (0x0000000EU) #define FLASH_ACR_LATENCY_15WS (0x0000000FU) #define FLASH_ACR_PRFTEN_Pos (8U) #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ #define FLASH_ACR_LPM_Pos (11U) #define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ #define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ #define FLASH_ACR_PDREQ1_Pos (12U) #define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ #define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ #define FLASH_ACR_PDREQ2_Pos (13U) #define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ #define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ #define FLASH_ACR_SLEEP_PD_Pos (14U) #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ /****************** Bits definition for FLASH_NSSR register *****************/ #define FLASH_NSSR_EOP_Pos (0U) #define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ #define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ #define FLASH_NSSR_OPERR_Pos (1U) #define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ #define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ #define FLASH_NSSR_PROGERR_Pos (3U) #define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ #define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ #define FLASH_NSSR_WRPERR_Pos (4U) #define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ #define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ #define FLASH_NSSR_PGAERR_Pos (5U) #define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ #define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ #define FLASH_NSSR_SIZERR_Pos (6U) #define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ #define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ #define FLASH_NSSR_PGSERR_Pos (7U) #define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ #define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ #define FLASH_NSSR_OPTWERR_Pos (13U) #define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ #define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ #define FLASH_NSSR_BSY_Pos (16U) #define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ #define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ #define FLASH_NSSR_WDW_Pos (17U) #define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ #define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ #define FLASH_NSSR_OEM1LOCK_Pos (18U) #define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ #define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ #define FLASH_NSSR_OEM2LOCK_Pos (19U) #define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ #define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ #define FLASH_NSSR_PD1_Pos (20U) #define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ #define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ #define FLASH_NSSR_PD2_Pos (21U) #define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ #define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ /****************** Bits definition for FLASH_SECSR register ****************/ #define FLASH_SECSR_EOP_Pos (0U) #define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ #define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ #define FLASH_SECSR_OPERR_Pos (1U) #define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ #define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ #define FLASH_SECSR_PROGERR_Pos (3U) #define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ #define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ #define FLASH_SECSR_WRPERR_Pos (4U) #define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ #define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ #define FLASH_SECSR_PGAERR_Pos (5U) #define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ #define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ #define FLASH_SECSR_SIZERR_Pos (6U) #define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ #define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ #define FLASH_SECSR_PGSERR_Pos (7U) #define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ #define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ #define FLASH_SECSR_BSY_Pos (16U) #define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ #define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ #define FLASH_SECSR_WDW_Pos (17U) #define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ #define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ /****************** Bits definition for FLASH_NSCR register *****************/ #define FLASH_NSCR_PG_Pos (0U) #define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ #define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ #define FLASH_NSCR_PER_Pos (1U) #define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ #define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ #define FLASH_NSCR_MER1_Pos (2U) #define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ #define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ #define FLASH_NSCR_PNB_Pos (3U) #define FLASH_NSCR_PNB_Msk (0x7FUL << FLASH_NSCR_PNB_Pos) /*!< 0x000003F8 */ #define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ #define FLASH_NSCR_BKER_Pos (11U) #define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ #define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ #define FLASH_NSCR_BWR_Pos (14U) #define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ #define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ #define FLASH_NSCR_MER2_Pos (15U) #define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ #define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ #define FLASH_NSCR_STRT_Pos (16U) #define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ #define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ #define FLASH_NSCR_OPTSTRT_Pos (17U) #define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ #define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ #define FLASH_NSCR_EOPIE_Pos (24U) #define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ #define FLASH_NSCR_ERRIE_Pos (25U) #define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ #define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ #define FLASH_NSCR_OBL_LAUNCH_Pos (27U) #define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ #define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ #define FLASH_NSCR_OPTLOCK_Pos (30U) #define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ #define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ #define FLASH_NSCR_LOCK_Pos (31U) #define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ /****************** Bits definition for FLASH_SECCR register ****************/ #define FLASH_SECCR_PG_Pos (0U) #define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ #define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ #define FLASH_SECCR_PER_Pos (1U) #define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ #define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ #define FLASH_SECCR_MER1_Pos (2U) #define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ #define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ #define FLASH_SECCR_PNB_Pos (3U) #define FLASH_SECCR_PNB_Msk (0x7FUL << FLASH_SECCR_PNB_Pos) /*!< 0x000003F8 */ #define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ #define FLASH_SECCR_BKER_Pos (11U) #define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ #define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ #define FLASH_SECCR_BWR_Pos (14U) #define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ #define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ #define FLASH_SECCR_MER2_Pos (15U) #define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ #define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ #define FLASH_SECCR_STRT_Pos (16U) #define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ #define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ #define FLASH_SECCR_EOPIE_Pos (24U) #define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ #define FLASH_SECCR_ERRIE_Pos (25U) #define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ #define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ #define FLASH_SECCR_INV_Pos (29U) #define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ #define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ #define FLASH_SECCR_LOCK_Pos (31U) #define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ /******************* Bits definition for FLASH_ECCR register ***************/ #define FLASH_ECCR_ADDR_ECC_Pos (0U) #define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */ #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ #define FLASH_ECCR_BK_ECC_Pos (21U) #define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ #define FLASH_ECCR_SYSF_ECC_Pos (22U) #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ #define FLASH_ECCR_ECCIE_Pos (24U) #define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ #define FLASH_ECCR_ECCC_Pos (30U) #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ #define FLASH_ECCR_ECCD_Pos (31U) #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ /******************* Bits definition for FLASH_OPSR register ***************/ #define FLASH_OPSR_ADDR_OP_Pos (0U) #define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ #define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ #define FLASH_OPSR_BK_OP_Pos (21U) #define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ #define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ #define FLASH_OPSR_SYSF_OP_Pos (22U) #define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ #define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ #define FLASH_OPSR_CODE_OP_Pos (29U) #define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ #define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ #define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ #define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ #define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ /******************* Bits definition for FLASH_OPTR register ***************/ #define FLASH_OPTR_RDP_Pos (0U) #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ #define FLASH_OPTR_BOR_LEV_Pos (8U) #define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ #define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ #define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ #define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ #define FLASH_OPTR_nRST_STOP_Pos (12U) #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ #define FLASH_OPTR_nRST_STDBY_Pos (13U) #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ #define FLASH_OPTR_nRST_SHDW_Pos (14U) #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ #define FLASH_OPTR_SRAM134_RST_Pos (15U) #define FLASH_OPTR_SRAM134_RST_Msk (0x1UL << FLASH_OPTR_SRAM134_RST_Pos) /*!< 0x00008000 */ #define FLASH_OPTR_SRAM134_RST FLASH_OPTR_SRAM134_RST_Msk /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */ #define FLASH_OPTR_IWDG_SW_Pos (16U) #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ #define FLASH_OPTR_IWDG_STOP_Pos (17U) #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ #define FLASH_OPTR_IWDG_STDBY_Pos (18U) #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ #define FLASH_OPTR_WWDG_SW_Pos (19U) #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ #define FLASH_OPTR_SWAP_BANK_Pos (20U) #define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ #define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ #define FLASH_OPTR_DUALBANK_Pos (21U) #define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ #define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ #define FLASH_OPTR_BKPRAM_ECC_Pos (22U) #define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ #define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ #define FLASH_OPTR_SRAM3_ECC_Pos (23U) #define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ #define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ #define FLASH_OPTR_SRAM2_ECC_Pos (24U) #define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ #define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ #define FLASH_OPTR_SRAM2_RST_Pos (25U) #define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ #define FLASH_OPTR_nSWBOOT0_Pos (26U) #define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ #define FLASH_OPTR_nBOOT0_Pos (27U) #define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ #define FLASH_OPTR_PA15_PUPEN_Pos (28U) #define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ #define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ #define FLASH_OPTR_IO_VDD_HSLV_Pos (29U) #define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ #define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ #define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30U) #define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ #define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ #define FLASH_OPTR_TZEN_Pos (31U) #define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ #define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ /**************** Bits definition for FLASH_NSBOOTADD0R register ************/ #define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) #define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ #define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ /**************** Bits definition for FLASH_NSBOOTADD1R register ************/ #define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) #define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ #define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ /**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ #define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) #define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ #define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ #define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) #define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ #define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ /***************** Bits definition for FLASH_SECWM1R1 register **************/ #define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U) #define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000007F */ #define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ #define FLASH_SECWM1R1_SECWM1_PEND_Pos (16U) #define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x007F0000 */ #define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ /***************** Bits definition for FLASH_SECWM1R2 register **************/ #define FLASH_SECWM1R2_HDP1_PEND_Pos (16U) #define FLASH_SECWM1R2_HDP1_PEND_Msk (0x7FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x007F0000 */ #define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ #define FLASH_SECWM1R2_HDP1EN_Pos (31U) #define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ #define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ /****************** Bits definition for FLASH_WRP1AR register ***************/ #define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U) #define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000007F */ #define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ #define FLASH_WRP1AR_WRP1A_PEND_Pos (16U) #define FLASH_WRP1AR_WRP1A_PEND_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x007F0000 */ #define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ #define FLASH_WRP1AR_UNLOCK_Pos (31U) #define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ #define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ /****************** Bits definition for FLASH_WRP1BR register ***************/ #define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U) #define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000007F */ #define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ #define FLASH_WRP1BR_WRP1B_PEND_Pos (16U) #define FLASH_WRP1BR_WRP1B_PEND_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x007F0000 */ #define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ #define FLASH_WRP1BR_UNLOCK_Pos (31U) #define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ #define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ /***************** Bits definition for FLASH_SECWM2R1 register **************/ #define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U) #define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000007F */ #define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ #define FLASH_SECWM2R1_SECWM2_PEND_Pos (16U) #define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x007F0000 */ #define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ /***************** Bits definition for FLASH_SECWM2R2 register **************/ #define FLASH_SECWM2R2_HDP2_PEND_Pos (16U) #define FLASH_SECWM2R2_HDP2_PEND_Msk (0x7FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x007F0000 */ #define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ #define FLASH_SECWM2R2_HDP2EN_Pos (31U) #define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ #define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ /****************** Bits definition for FLASH_WRP2AR register ***************/ #define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U) #define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000007F */ #define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ #define FLASH_WRP2AR_WRP2A_PEND_Pos (16U) #define FLASH_WRP2AR_WRP2A_PEND_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x007F0000 */ #define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ #define FLASH_WRP2AR_UNLOCK_Pos (31U) #define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ #define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ /****************** Bits definition for FLASH_WRP2BR register ***************/ #define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U) #define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000007F */ #define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ #define FLASH_WRP2BR_WRP2B_PEND_Pos (16U) #define FLASH_WRP2BR_WRP2B_PEND_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x007F0000 */ #define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ #define FLASH_WRP2BR_UNLOCK_Pos (31U) #define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ #define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ /****************** Bits definition for FLASH_SECHDPCR register ***********/ #define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U) #define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ #define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ #define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U) #define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ #define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ /****************** Bits definition for FLASH_PRIVCFGR register ***********/ #define FLASH_PRIVCFGR_SPRIV_Pos (0U) #define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ #define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ #define FLASH_PRIVCFGR_NSPRIV_Pos (1U) #define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ #define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ /******************************************************************************/ /* */ /* Filter Mathematical ACcelerator unit (FMAC) */ /* */ /******************************************************************************/ /***************** Bit definition for FMAC_X1BUFCFG register ****************/ #define FMAC_X1BUFCFG_X1_BASE_Pos (0U) #define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ #define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ #define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ #define FMAC_X1BUFCFG_FULL_WM_Pos (24U) #define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ #define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ /***************** Bit definition for FMAC_X2BUFCFG register ****************/ #define FMAC_X2BUFCFG_X2_BASE_Pos (0U) #define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ #define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ #define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ /***************** Bit definition for FMAC_YBUFCFG register *****************/ #define FMAC_YBUFCFG_Y_BASE_Pos (0U) #define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ #define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ #define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ #define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) #define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ #define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ /****************** Bit definition for FMAC_PARAM register ******************/ #define FMAC_PARAM_P_Pos (0U) #define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ #define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ #define FMAC_PARAM_Q_Pos (8U) #define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ #define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ #define FMAC_PARAM_R_Pos (16U) #define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ #define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ #define FMAC_PARAM_FUNC_Pos (24U) #define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ #define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ #define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ #define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ #define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ #define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ #define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ #define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ #define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ #define FMAC_PARAM_START_Pos (31U) #define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ #define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ /******************** Bit definition for FMAC_CR register *******************/ #define FMAC_CR_RIEN_Pos (0U) #define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ #define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ #define FMAC_CR_WIEN_Pos (1U) #define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ #define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ #define FMAC_CR_OVFLIEN_Pos (2U) #define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ #define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ #define FMAC_CR_UNFLIEN_Pos (3U) #define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ #define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ #define FMAC_CR_SATIEN_Pos (4U) #define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ #define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ #define FMAC_CR_DMAREN_Pos (8U) #define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ #define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ #define FMAC_CR_DMAWEN_Pos (9U) #define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ #define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ #define FMAC_CR_CLIPEN_Pos (15U) #define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ #define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ #define FMAC_CR_RESET_Pos (16U) #define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ #define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ /******************* Bit definition for FMAC_SR register ********************/ #define FMAC_SR_YEMPTY_Pos (0U) #define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ #define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ #define FMAC_SR_X1FULL_Pos (1U) #define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ #define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ #define FMAC_SR_OVFL_Pos (8U) #define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ #define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ #define FMAC_SR_UNFL_Pos (9U) #define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ #define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ #define FMAC_SR_SAT_Pos (10U) #define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ #define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ /****************** Bit definition for FMAC_WDATA register ******************/ #define FMAC_WDATA_WDATA_Pos (0U) #define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ #define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ /****************** Bit definition for FMACX_RDATA register *****************/ #define FMAC_RDATA_RDATA_Pos (0U) #define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ #define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ /******************************************************************************/ /* */ /* Flexible Memory Controller */ /* */ /******************************************************************************/ /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!