diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g030xx.h b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g030xx.h index d28e05b13422e8472935df6a7fa1d703b08ca692..77c51d434b59867161eb27f2d63df1bb6c00fda7 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g030xx.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g030xx.h @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -22,7 +22,7 @@ * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * - ****************************************************************************** + ****************************************************************************** */ /** @addtogroup CMSIS_Device @@ -95,7 +95,7 @@ typedef enum TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */ SPI2_IRQn = 26, /*!< SPI2 Interrupt */ USART1_IRQn = 27, /*!< USART1 Interrupt */ USART2_IRQn = 28, /*!< USART2 Interrupt */ @@ -146,6 +146,7 @@ typedef struct + /** * @brief CRC calculation unit */ @@ -517,7 +518,6 @@ typedef struct #define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ #define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ - #define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */ /*!< Peripheral memory map */ @@ -577,7 +577,6 @@ typedef struct #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) -#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) /*!< IOPORT */ #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) @@ -618,7 +617,6 @@ typedef struct #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) - #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) @@ -637,7 +635,6 @@ typedef struct #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -652,7 +649,6 @@ typedef struct #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) -#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) #define DBG ((DBG_TypeDef *) DBG_BASE) @@ -1280,9 +1276,10 @@ typedef struct #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ +/* Legacy */ #define ADC_CCR_LFMEN_Pos (25U) #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ -#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */ /******************************************************************************/ @@ -1728,27 +1725,6 @@ typedef struct #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ -/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/ -#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U) -#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */ -#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */ - -/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/ -#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U) -#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */ -#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */ - -#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U) -#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */ -#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */ - -#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U) -#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */ -#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */ - -#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U) -#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */ -#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */ /******************************************************************************/ /* */ /* External Interrupt/Event Controller */ @@ -2264,7 +2240,6 @@ typedef struct #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ - /******************************************************************************/ /* */ /* FLASH */ @@ -3864,6 +3839,7 @@ typedef struct #define PWR_PUCRD_PU3_Pos (3U) #define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */ #define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */ + /******************** Bit definition for PWR_PDCRD register *****************/ #define PWR_PDCRD_PD0_Pos (0U) #define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */ @@ -4347,10 +4323,10 @@ typedef struct #define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ #define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk #define RCC_APBSMENR1_WWDGSMEN_Pos (11U) -#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ #define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk #define RCC_APBSMENR1_SPI2SMEN_Pos (14U) -#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ #define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk #define RCC_APBSMENR1_USART2SMEN_Pos (17U) #define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ @@ -5070,7 +5046,6 @@ typedef struct #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk - /******************************************************************************/ /* */ /* Tamper and backup register (TAMP) */ @@ -5242,7 +5217,6 @@ typedef struct #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk - /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ @@ -6934,7 +6908,6 @@ typedef struct #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ - /******************************************************************************/ /* */ /* Window WATCHDOG */ @@ -7074,7 +7047,6 @@ typedef struct ((INSTANCE) == GPIOC) || \ ((INSTANCE) == GPIOD) || \ ((INSTANCE) == GPIOF)) - /******************************* GPIO AF Instances ****************************/ #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) @@ -7100,6 +7072,7 @@ typedef struct /******************************** SPI Instances *******************************/ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ ((INSTANCE) == SPI2)) + /******************************** SPI Instances *******************************/ #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) @@ -7295,7 +7268,9 @@ typedef struct ((INSTANCE) == TIM3)) /******************* TIM Instances : Timer input selection ********************/ -#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM14) || \ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM14) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g031xx.h b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g031xx.h index 520691fbd6ce1a8718d7bbac671264149af23b6d..6c762a8fbb843e78e32a0811dbf642a476aad7e8 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g031xx.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g031xx.h @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -22,7 +22,7 @@ * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * - ****************************************************************************** + ****************************************************************************** */ /** @addtogroup CMSIS_Device @@ -99,7 +99,7 @@ typedef enum TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */ SPI2_IRQn = 26, /*!< SPI2 Interrupt */ USART1_IRQn = 27, /*!< USART1 Interrupt */ USART2_IRQn = 28, /*!< USART2 Interrupt */ @@ -151,6 +151,7 @@ typedef struct + /** * @brief CRC calculation unit */ @@ -550,7 +551,6 @@ typedef struct #define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ #define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ - #define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */ /*!< Peripheral memory map */ @@ -615,7 +615,6 @@ typedef struct #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) -#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) /*!< IOPORT */ #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) @@ -661,7 +660,6 @@ typedef struct #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) - #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) @@ -680,7 +678,6 @@ typedef struct #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -695,7 +692,6 @@ typedef struct #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) -#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) #define DBG ((DBG_TypeDef *) DBG_BASE) @@ -1323,9 +1319,10 @@ typedef struct #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ +/* Legacy */ #define ADC_CCR_LFMEN_Pos (25U) #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ -#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */ /******************************************************************************/ @@ -1771,27 +1768,6 @@ typedef struct #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ -/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/ -#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U) -#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */ -#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */ - -/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/ -#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U) -#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */ -#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */ - -#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U) -#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */ -#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */ - -#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U) -#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */ -#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */ - -#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U) -#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */ -#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */ /******************************************************************************/ /* */ /* External Interrupt/Event Controller */ @@ -2346,7 +2322,6 @@ typedef struct #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ - /******************************************************************************/ /* */ /* FLASH */ @@ -4041,6 +4016,7 @@ typedef struct #define PWR_PUCRD_PU3_Pos (3U) #define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */ #define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */ + /******************** Bit definition for PWR_PDCRD register *****************/ #define PWR_PDCRD_PD0_Pos (0U) #define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */ @@ -4562,10 +4538,10 @@ typedef struct #define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ #define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk #define RCC_APBSMENR1_WWDGSMEN_Pos (11U) -#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ #define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk #define RCC_APBSMENR1_SPI2SMEN_Pos (14U) -#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ #define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk #define RCC_APBSMENR1_USART2SMEN_Pos (17U) #define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ @@ -5314,7 +5290,6 @@ typedef struct #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk - /******************************************************************************/ /* */ /* Tamper and backup register (TAMP) */ @@ -5486,7 +5461,6 @@ typedef struct #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk - /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ @@ -7395,7 +7369,6 @@ typedef struct #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ - /******************************************************************************/ /* */ /* VREFBUF */ @@ -7568,7 +7541,6 @@ typedef struct ((INSTANCE) == GPIOC) || \ ((INSTANCE) == GPIOD) || \ ((INSTANCE) == GPIOF)) - /******************************* GPIO AF Instances ****************************/ #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) @@ -7594,6 +7566,7 @@ typedef struct /******************************** SPI Instances *******************************/ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ ((INSTANCE) == SPI2)) + /******************************** SPI Instances *******************************/ #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) @@ -7840,7 +7813,6 @@ typedef struct #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) - /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g041xx.h b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g041xx.h index 039f91185f93017d5dc5005590bdfe97b6d334f6..b8e003823afcda98ca43c655b70664cf474a834d 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g041xx.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g041xx.h @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -22,7 +22,7 @@ * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * - ****************************************************************************** + ****************************************************************************** */ /** @addtogroup CMSIS_Device @@ -99,7 +99,7 @@ typedef enum TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */ SPI2_IRQn = 26, /*!< SPI2 Interrupt */ USART1_IRQn = 27, /*!< USART1 Interrupt */ USART2_IRQn = 28, /*!< USART2 Interrupt */ @@ -152,6 +152,7 @@ typedef struct + /** * @brief CRC calculation unit */ @@ -592,7 +593,6 @@ typedef struct #define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ #define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ - #define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */ /*!< Peripheral memory map */ @@ -659,7 +659,6 @@ typedef struct #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) -#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) /*!< IOPORT */ #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) @@ -705,7 +704,6 @@ typedef struct #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) - #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) @@ -727,7 +725,6 @@ typedef struct #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -742,7 +739,6 @@ typedef struct #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) -#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) #define DBG ((DBG_TypeDef *) DBG_BASE) @@ -1370,9 +1366,10 @@ typedef struct #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ +/* Legacy */ #define ADC_CCR_LFMEN_Pos (25U) #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ -#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */ /******************************************************************************/ @@ -2007,27 +2004,6 @@ typedef struct #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ -/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/ -#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U) -#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */ -#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */ - -/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/ -#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U) -#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */ -#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */ - -#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U) -#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */ -#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */ - -#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U) -#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */ -#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */ - -#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U) -#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */ -#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */ /******************************************************************************/ /* */ /* External Interrupt/Event Controller */ @@ -2582,7 +2558,6 @@ typedef struct #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ - /******************************************************************************/ /* */ /* FLASH */ @@ -4277,6 +4252,7 @@ typedef struct #define PWR_PUCRD_PU3_Pos (3U) #define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */ #define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */ + /******************** Bit definition for PWR_PDCRD register *****************/ #define PWR_PDCRD_PD0_Pos (0U) #define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */ @@ -4816,10 +4792,10 @@ typedef struct #define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ #define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk #define RCC_APBSMENR1_WWDGSMEN_Pos (11U) -#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ #define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk #define RCC_APBSMENR1_SPI2SMEN_Pos (14U) -#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ #define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk #define RCC_APBSMENR1_USART2SMEN_Pos (17U) #define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ @@ -5612,7 +5588,6 @@ typedef struct #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk - /******************************************************************************/ /* */ /* Tamper and backup register (TAMP) */ @@ -5784,7 +5759,6 @@ typedef struct #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk - /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ @@ -7699,7 +7673,6 @@ typedef struct #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ - /******************************************************************************/ /* */ /* VREFBUF */ @@ -7874,7 +7847,6 @@ typedef struct ((INSTANCE) == GPIOC) || \ ((INSTANCE) == GPIOD) || \ ((INSTANCE) == GPIOF)) - /******************************* GPIO AF Instances ****************************/ #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) @@ -7902,6 +7874,7 @@ typedef struct /******************************** SPI Instances *******************************/ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ ((INSTANCE) == SPI2)) + /******************************** SPI Instances *******************************/ #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) @@ -8148,7 +8121,6 @@ typedef struct #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) - /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g070xx.h b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g070xx.h index 389e37ae47bcde14246c104d908c6afaf995e289..2c85cdc3a520c147067f912c47cdd225cc0f522c 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g070xx.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g070xx.h @@ -22,7 +22,7 @@ * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * - ****************************************************************************** + ****************************************************************************** */ /** @addtogroup CMSIS_Device @@ -98,7 +98,7 @@ typedef enum TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */ SPI2_IRQn = 26, /*!< SPI2 Interrupt */ USART1_IRQn = 27, /*!< USART1 Interrupt */ USART2_IRQn = 28, /*!< USART2 Interrupt */ @@ -150,6 +150,7 @@ typedef struct + /** * @brief CRC calculation unit */ @@ -521,7 +522,6 @@ typedef struct #define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ #define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ - #define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */ /*!< Peripheral memory map */ @@ -590,7 +590,6 @@ typedef struct #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) -#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) /*!< IOPORT */ #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) @@ -636,7 +635,6 @@ typedef struct #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) - #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) @@ -657,7 +655,6 @@ typedef struct #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -674,7 +671,6 @@ typedef struct #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) -#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) #define DBG ((DBG_TypeDef *) DBG_BASE) @@ -1302,9 +1298,10 @@ typedef struct #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ +/* Legacy */ #define ADC_CCR_LFMEN_Pos (25U) #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ -#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */ /******************************************************************************/ @@ -2265,7 +2262,6 @@ typedef struct #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ - /******************************************************************************/ /* */ /* FLASH */ @@ -4505,10 +4501,10 @@ typedef struct #define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ #define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk #define RCC_APBSMENR1_WWDGSMEN_Pos (11U) -#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ #define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk #define RCC_APBSMENR1_SPI2SMEN_Pos (14U) -#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ #define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk #define RCC_APBSMENR1_USART2SMEN_Pos (17U) #define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ @@ -5242,7 +5238,6 @@ typedef struct #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk - /******************************************************************************/ /* */ /* Tamper and backup register (TAMP) */ @@ -5414,7 +5409,6 @@ typedef struct #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk - /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ @@ -7128,7 +7122,6 @@ typedef struct #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ - /******************************************************************************/ /* */ /* Window WATCHDOG */ @@ -7280,7 +7273,6 @@ typedef struct ((INSTANCE) == GPIOC) || \ ((INSTANCE) == GPIOD) || \ ((INSTANCE) == GPIOF)) - /******************************* GPIO AF Instances ****************************/ #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) @@ -7306,6 +7298,7 @@ typedef struct /******************************** SPI Instances *******************************/ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ ((INSTANCE) == SPI2)) + /******************************** SPI Instances *******************************/ #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) @@ -7532,7 +7525,9 @@ typedef struct ((INSTANCE) == TIM15)) /******************* TIM Instances : Timer input selection ********************/ -#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM14) || \ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM14) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g071xx.h b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g071xx.h index 47c9238807ba3a096097ee6a19ddd415fd966712..b376dceb3f7059068017b5ffe91507cf7e4c9d49 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g071xx.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g071xx.h @@ -22,7 +22,7 @@ * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * - ****************************************************************************** + ****************************************************************************** */ /** @addtogroup CMSIS_Device @@ -101,7 +101,7 @@ typedef enum TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */ SPI2_IRQn = 26, /*!< SPI2 Interrupt */ USART1_IRQn = 27, /*!< USART1 Interrupt */ USART2_IRQn = 28, /*!< USART2 Interrupt */ @@ -152,6 +152,7 @@ typedef struct __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ } ADC_Common_TypeDef; + /** * @brief HDMI-CEC */ @@ -633,7 +634,6 @@ typedef struct #define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ #define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ - #define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */ /*!< Peripheral memory map */ @@ -714,7 +714,6 @@ typedef struct #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) -#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) /*!< IOPORT */ #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) @@ -771,7 +770,6 @@ typedef struct #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) - #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) @@ -794,7 +792,6 @@ typedef struct #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -811,7 +808,6 @@ typedef struct #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) -#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) #define DBG ((DBG_TypeDef *) DBG_BASE) @@ -1439,9 +1435,10 @@ typedef struct #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ +/* Legacy */ #define ADC_CCR_LFMEN_Pos (25U) #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ -#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */ /******************************************************************************/ /* */ @@ -2868,7 +2865,6 @@ typedef struct #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */ - /******************************************************************************/ /* */ /* FLASH */ @@ -5265,10 +5261,10 @@ typedef struct #define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ #define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk #define RCC_APBSMENR1_WWDGSMEN_Pos (11U) -#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ #define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk #define RCC_APBSMENR1_SPI2SMEN_Pos (14U) -#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ #define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk #define RCC_APBSMENR1_USART2SMEN_Pos (17U) #define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ @@ -6049,7 +6045,6 @@ typedef struct #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk - /******************************************************************************/ /* */ /* Tamper and backup register (TAMP) */ @@ -6221,7 +6216,6 @@ typedef struct #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk - /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ @@ -8233,7 +8227,6 @@ typedef struct #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ - /******************************************************************************/ /* */ /* VREFBUF */ @@ -8750,7 +8743,6 @@ typedef struct ((INSTANCE) == GPIOC) || \ ((INSTANCE) == GPIOD) || \ ((INSTANCE) == GPIOF)) - /******************************* GPIO AF Instances ****************************/ #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) @@ -8776,6 +8768,7 @@ typedef struct /******************************** SPI Instances *******************************/ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ ((INSTANCE) == SPI2)) + /******************************** SPI Instances *******************************/ #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) @@ -9055,7 +9048,6 @@ typedef struct ((INSTANCE) == USART3) || \ ((INSTANCE) == USART4)) - /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g081xx.h b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g081xx.h index 218dee4e034c282772b15c6f969cf755d1de02fc..1a97d5d8acf986c61e1391747538141dfb17b011 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g081xx.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g081xx.h @@ -22,7 +22,7 @@ * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * - ****************************************************************************** + ****************************************************************************** */ /** @addtogroup CMSIS_Device @@ -101,7 +101,7 @@ typedef enum TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */ SPI2_IRQn = 26, /*!< SPI2 Interrupt */ USART1_IRQn = 27, /*!< USART1 Interrupt */ USART2_IRQn = 28, /*!< USART2 Interrupt */ @@ -153,6 +153,7 @@ typedef struct __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ } ADC_Common_TypeDef; + /** * @brief HDMI-CEC */ @@ -675,7 +676,6 @@ typedef struct #define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ #define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ - #define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */ /*!< Peripheral memory map */ @@ -758,7 +758,6 @@ typedef struct #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) -#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) /*!< IOPORT */ #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) @@ -815,7 +814,6 @@ typedef struct #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) - #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) @@ -841,7 +839,6 @@ typedef struct #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -858,7 +855,6 @@ typedef struct #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) -#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) #define DBG ((DBG_TypeDef *) DBG_BASE) @@ -1486,9 +1482,10 @@ typedef struct #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ +/* Legacy */ #define ADC_CCR_LFMEN_Pos (25U) #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ -#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */ /******************************************************************************/ /* */ @@ -3104,7 +3101,6 @@ typedef struct #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */ - /******************************************************************************/ /* */ /* FLASH */ @@ -5519,10 +5515,10 @@ typedef struct #define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ #define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk #define RCC_APBSMENR1_WWDGSMEN_Pos (11U) -#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ #define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk #define RCC_APBSMENR1_SPI2SMEN_Pos (14U) -#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ #define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk #define RCC_APBSMENR1_USART2SMEN_Pos (17U) #define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ @@ -6347,7 +6343,6 @@ typedef struct #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk - /******************************************************************************/ /* */ /* Tamper and backup register (TAMP) */ @@ -6519,7 +6514,6 @@ typedef struct #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk - /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ @@ -8537,7 +8531,6 @@ typedef struct #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ - /******************************************************************************/ /* */ /* VREFBUF */ @@ -9056,7 +9049,6 @@ typedef struct ((INSTANCE) == GPIOC) || \ ((INSTANCE) == GPIOD) || \ ((INSTANCE) == GPIOF)) - /******************************* GPIO AF Instances ****************************/ #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) @@ -9084,6 +9076,7 @@ typedef struct /******************************** SPI Instances *******************************/ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ ((INSTANCE) == SPI2)) + /******************************** SPI Instances *******************************/ #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) @@ -9363,7 +9356,6 @@ typedef struct ((INSTANCE) == USART3) || \ ((INSTANCE) == USART4)) - /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g0xx.h b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g0xx.h index 71761294f30348a95431c6429802dfa99969105a..8af3dc3c14720f22b50afbbce66670d8a6f4042b 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g0xx.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g0xx.h @@ -57,10 +57,13 @@ application */ -#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) +#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) && !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) /* #define STM32G070xx */ /*!< STM32G070xx Devices */ /* #define STM32G071xx */ /*!< STM32G071xx Devices */ /* #define STM32G081xx */ /*!< STM32G081xx Devices */ + /* #define STM32G030xx */ /*!< STM32G030xx Devices */ + /* #define STM32G031xx */ /*!< STM32G031xx Devices */ + /* #define STM32G041xx */ /*!< STM32G041xx Devices */ #endif /* Tip: To avoid modifying this file each time you need to switch between these @@ -79,7 +82,7 @@ * @brief CMSIS Device version number $VERSION$ */ #define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32G0_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ +#define __STM32G0_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32G0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\ @@ -101,6 +104,12 @@ #include "stm32g081xx.h" #elif defined(STM32G070xx) #include "stm32g070xx.h" +#elif defined(STM32G031xx) + #include "stm32g031xx.h" +#elif defined(STM32G041xx) + #include "stm32g041xx.h" +#elif defined(STM32G030xx) + #include "stm32g030xx.h" #else #error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)" #endif diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g030xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g030xx.s index e374689641c0f517cca16224f94d91a497ee64b1..086e7b10cfb97b961faf3e95be1313abc6e7d28c 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g030xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g030xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2019 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g031xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g031xx.s index dab10357a0d8a626a88c6978a5f1ef9962f04995..3b6bba8fb5fc54bc10e3e08445d58d59d38ec500 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g031xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g031xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2019 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g041xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g041xx.s index fd3ab2df9b65ec27583af2e5e50b93326e731d78..5be2c45c17ada1f0dee2602d56316235bb296923 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g041xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g041xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2019 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g070xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g070xx.s index ae3eb87aa2ef37da0331472e08b273982b2c3894..34570df147a923a1ee5b9bb5df67cb5415ff6a44 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g070xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g070xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2018 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g071xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g071xx.s index 33446332e80b4b9672a2e233350a3010ecddf86f..5f75566907dfad03aa0763584077364e0caa4cf3 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g071xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g071xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2018 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g081xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g081xx.s index f3e58c5ac5b622ee5c9cd7918968d18f4fcfc5de..7787b81b27f7b3e282c89409861ceb36f58cf0dd 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g081xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g081xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2018 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s index 5234f0136ec2e1b77d2faba40f2ce22b5f729c97..efe76cccafe69172571143318090563f81d4cfde 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g030xx.s * @author MCD Application Team - * @brief STM32G030xx devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32G030xx devices vector table for SW4STM32 toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,8 +14,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -85,9 +84,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever @@ -218,8 +217,8 @@ g_pfnVectors: .weak DMA1_Channel2_3_IRQHandler .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler - .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler + .weak DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler,Default_Handler .weak ADC1_IRQHandler .thumb_set ADC1_IRQHandler,Default_Handler diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s index 0fd24ae600f0f88f809d8a91f04e899fd5ad8499..021b318b91345c5b6c0a5ab570a47a468f3a83f9 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g031xx.s * @author MCD Application Team - * @brief STM32G031xx devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32G031xx devices vector table for SW4STM32 toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,8 +14,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -85,9 +84,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever @@ -273,5 +272,8 @@ g_pfnVectors: .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s index 19ecd13e91623d03dd469e2ab138c349bac47dc3..29f8185c1f67c3f0726cdc60fc21a7cc8f4f12ec 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g041xx.s * @author MCD Application Team - * @brief STM32G041xx devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32G041xx devices vector table for SW4STM32 toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,8 +14,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -85,9 +84,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s index 24652d9680d78dc4a76e86e60e496745efb21e7f..61bce5dec444f96e9a404600ba1f4469a7506c44 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g070xx.s * @author MCD Application Team - * @brief STM32G070xx devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32G070xx devices vector table for SW4STM32 toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,8 +14,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018 STMicroelectronics. All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -85,9 +84,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s index f7654671e4c9db3a6e58fa0e9224901650626eec..72487cfbb66dcee5f1481afd490a4ecc22f5262c 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g071xx.s * @author MCD Application Team - * @brief STM32G071xx devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32G071xx devices vector table for SW4STM32 toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,8 +14,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018 STMicroelectronics. All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -85,7 +84,7 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ -/* bl __libc_init_array */ +/* bl __libc_init_array */ /* Call the application's entry point.*/ bl entry diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s index 5c434be0ecb512f0f2bc8c1510f4abc5a6a3ce8d..3f96e68a960f21fbe5554ee1b7fd9c7be0985a77 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g081xx.s * @author MCD Application Team - * @brief STM32G051xx devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32G081xx devices vector table for SW4STM32 toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,8 +14,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018 STMicroelectronics. All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -85,9 +84,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g030xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g030xx.s index 7fd552e47f62fbf05cd74a9c2d179efe09bc523c..294828382aca5df423db8efa4b340d64d4a3ad72 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g030xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g030xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2019 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g031xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g031xx.s index 95e501697b125bcdc91b4ff30473fd3976104b0a..ae5ed70053eb094796da331a9bb7b9be60d0c044 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g031xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g031xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2019 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g041xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g041xx.s index 521d50934260818b77567169420ae787898a112e..a10669b34500f80c6b378cb51419cd2efc08ef20 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g041xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g041xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2019 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g070xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g070xx.s index b873f0c3c5b701ee559bc2b22c05926ee1b13f5a..62b87024a7011d06b7e4054b22f8a19142205ae0 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g070xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g070xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2018 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g071xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g071xx.s index eef161cec83897b2ac1db60cb48b732f3beee9c8..cfe8d16ed3eb330d63c0f2307bef9768ad536c04 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g071xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g071xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2018 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g081xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g081xx.s index ce675e745ab7572ea0ffe560de35425df4906bb6..9991b2bcd9b77d6f1467162c5ca5f1e25ec37d49 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g081xx.s +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g081xx.s @@ -14,8 +14,7 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2018 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2018 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c index b8b2611797ac008fc32691cb0531016cbb7728f7..233ab30a47c217939c2e94531a21bc04367c25bc 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c @@ -79,19 +79,19 @@ #include "stm32g0xx.h" #if !defined (HSE_VALUE) -#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ #if !defined (LSI_VALUE) - #define LSI_VALUE 32000U /*!< Value of LSI in Hz*/ + #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ #endif /* LSI_VALUE */ #if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of LSE in Hz*/ + #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ #endif /* LSE_VALUE */ /** @@ -140,10 +140,10 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ - uint32_t SystemCoreClock = 16000000U; + uint32_t SystemCoreClock = 16000000UL; - const uint32_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; - const uint32_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL}; + const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; /** * @} @@ -241,25 +241,26 @@ void SystemCoreClockUpdate(void) break; case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ - { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; - switch (pllsource) - { - case 0x03: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm); - break; + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL; - case 0x02: /* HSI used as PLL clock source */ - default: + if(pllsource == 0x03UL) /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + else /* HSI used as PLL clock source */ + { pllvco = (HSI_VALUE / pllm); - break; } pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); + SystemCoreClock = pllvco/pllr; break; - } + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ default: /* HSI used as system clock */ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 4de90c7b0bd68a779a8fbba9cbb70b660a15a73e..887d64b4346a05e993415d785bfa63b08f7ee56d 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -236,6 +236,16 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE +#if defined(STM32G4) +#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) +#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + /** * @} */ @@ -486,6 +496,13 @@ #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ /** * @} */ @@ -494,7 +511,7 @@ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 @@ -553,12 +570,12 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -599,6 +616,125 @@ #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ /** * @} */ @@ -738,6 +874,12 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 +#if defined(STM32L1) || defined(STM32L4) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + + /** * @} */ @@ -753,7 +895,6 @@ #define I2S_FLAG_TXE I2S_FLAG_TXP #define I2S_FLAG_RXNE I2S_FLAG_RXP - #define I2S_FLAG_FRE I2S_FLAG_TIFRE #endif #if defined(STM32F7) @@ -970,6 +1111,25 @@ #if defined(STM32F3) #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE #endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + /** * @} */ @@ -1249,7 +1409,7 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32G0) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT @@ -1258,7 +1418,18 @@ #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32G0 */ +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ /** * @} */ @@ -1338,14 +1509,14 @@ #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 */ +#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ /** * @} */ @@ -2234,6 +2405,20 @@ #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE @@ -2450,12 +2635,28 @@ #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET @@ -2788,6 +2989,15 @@ #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + #if defined(STM32F4) #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET @@ -2904,7 +3114,7 @@ #if defined(STM32L4) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32G0) +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3032,7 +3242,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) +#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3148,7 +3358,7 @@ #define SDIO_IRQHandler SDMMC1_IRQHandler #endif -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef @@ -3395,7 +3605,7 @@ /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose * @{ */ -#if defined (STM32H7) || defined (STM32F3) +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart @@ -3407,6 +3617,16 @@ * @} */ +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif +/** + * @} + */ + /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h index 2f23fdbfb015e7ea754201cc5d21304a3ce1b73d..499a9d2c538e80459c7c4a9e2761f8b331c105bc 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h @@ -89,6 +89,23 @@ extern "C" { * @} */ +#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +/** @defgroup SYSCFG_ClampingDiode Clamping Diode + * @{ + */ +#define SYSCFG_CDEN_PA1 SYSCFG_CFGR2_PA1_CDEN /*!< Enables Clamping Diode on PA1 */ +#define SYSCFG_CDEN_PA3 SYSCFG_CFGR2_PA3_CDEN /*!< Enables Clamping Diode on PA3 */ +#define SYSCFG_CDEN_PA5 SYSCFG_CFGR2_PA5_CDEN /*!< Enables Clamping Diode on PA5 */ +#define SYSCFG_CDEN_PA6 SYSCFG_CFGR2_PA6_CDEN /*!< Enables Clamping Diode on PA6 */ +#define SYSCFG_CDEN_PA13 SYSCFG_CFGR2_PA13_CDEN /*!< Enables Clamping Diode on PA13 */ +#define SYSCFG_CDEN_PB0 SYSCFG_CFGR2_PB0_CDEN /*!< Enables Clamping Diode on PB0 */ +#define SYSCFG_CDEN_PB1 SYSCFG_CFGR2_PB1_CDEN /*!< Enables Clamping Diode on PB1 */ +#define SYSCFG_CDEN_PB2 SYSCFG_CFGR2_PB2_CDEN /*!< Enables Clamping Diode on PB2 */ + +/** + * @} + */ +#endif /** @defgroup HAL_Pin_remapping Pin remapping * @{ @@ -107,6 +124,8 @@ extern "C" { #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */ #if defined (STM32G081xx) || defined (STM32G071xx) || defined (STM32G070xx) #define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART4 is selected as IR Modulation envelope source */ +#elif defined (STM32G041xx) || defined (STM32G031xx) || defined (STM32G030xx) +#define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */ #endif /** @@ -495,6 +514,18 @@ extern "C" { CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ }while(0U) +#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +/** @brief Clamping Diode on specific pins enable/disable macros + * @param __PIN__ This parameter can be a combination of values @ref SYSCFG_ClampingDiode + */ +#define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\ + SET_BIT(SYSCFG->CFGR2, (__PIN__));\ + }while(0U) + +#define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\ + CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\ + }while(0U) +#endif /** @brief ISR wrapper check * @note Allow to determine interrupt source per line. @@ -561,11 +592,25 @@ extern "C" { ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) #endif +#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +#define IS_SYSCFG_CLAMPINGDIODE(__PIN__) ((((__PIN__) & SYSCFG_CDEN_PA1) == SYSCFG_CDEN_PA1) || \ + (((__PIN__) & SYSCFG_CDEN_PA3) == SYSCFG_CDEN_PA3) || \ + (((__PIN__) & SYSCFG_CDEN_PA5) == SYSCFG_CDEN_PA5) || \ + (((__PIN__) & SYSCFG_CDEN_PA6) == SYSCFG_CDEN_PA6) || \ + (((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \ + (((__PIN__) & SYSCFG_CDEN_PB0) == SYSCFG_CDEN_PB0) || \ + (((__PIN__) & SYSCFG_CDEN_PB1) == SYSCFG_CDEN_PB1) || \ + (((__PIN__) & SYSCFG_CDEN_PB2) == SYSCFG_CDEN_PB2)) +#endif #if defined (STM32G081xx) || defined (STM32G071xx) || defined (STM32G070xx) #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) +#elif defined (STM32G041xx) || defined (STM32G031xx) || defined (STM32G030xx) +#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2)) #endif #define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \ ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED)) @@ -696,6 +741,10 @@ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); void HAL_SYSCFG_EnableRemap(uint32_t PinRemap); void HAL_SYSCFG_DisableRemap(uint32_t PinRemap); +#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig); +void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig); +#endif #if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery); #endif diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h index 98d36dc95a7f662a8e8c727a47f262ab7d347909..2c54afaddd965d80a889a5d2ebc5b19c1b01418b 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h @@ -359,7 +359,11 @@ typedef struct /** * @brief ADC handle Structure definition */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) typedef struct __ADC_HandleTypeDef +#else +typedef struct +#endif { ADC_TypeDef *Instance; /*!< Register base address */ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ @@ -421,7 +425,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking, +#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, enable/disable, erroneous state, ...) */ #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ @@ -508,19 +512,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ /* ADC group regular trigger sources for all ADC instances */ #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ -#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #if defined(TIM2) -#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #endif -#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #if defined(TIM6) -#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #endif #if defined(TIM15) -#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #endif -#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ /** * @} */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cec.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cec.h index 4bb94e12c922f930ffea20b71615fd2a61596e53..03083cc735bc732b46e14b282236029c8e377f87 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cec.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cec.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -111,8 +111,8 @@ typedef struct } CEC_InitTypeDef; /** - * @brief HAL CEC State structures definition - * @note HAL CEC State value is a combination of 2 different substates: gState and RxState. + * @brief HAL CEC State definition + * @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition). * - gState contains CEC state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -121,14 +121,14 @@ typedef struct * b6 Error information * 0 : No Error * 1 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized. HAL CEC Init function already called) + * b5 CEC peripheral initilisation status + * 0 : Reset (peripheral not initialized) + * 1 : Init done (peripheral initialized. HAL CEC Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) + * 1 : Busy (peripheral busy with some configuration or internal operations) * b1 (not used) * x : Should be set to 0 * b0 Tx state @@ -138,9 +138,9 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized) + * b5 CEC peripheral initilisation status + * 0 : Reset (peripheral not initialized) + * 1 : Init done (peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -149,27 +149,16 @@ typedef struct * b0 (not used) * x : Should be set to 0. */ -typedef enum -{ - HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized - Value is allowed for gState and RxState */ - HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */ -} HAL_CEC_StateTypeDef; +typedef uint32_t HAL_CEC_StateTypeDef; /** * @brief CEC handle Structure definition */ +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) typedef struct __CEC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ { CEC_TypeDef *Instance; /*!< CEC registers base address */ @@ -194,8 +183,10 @@ typedef struct __CEC_HandleTypeDef in case error is reported */ #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) - void (* TxCpltCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Tx Transfer completed callback */ - void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ + void (* TxCpltCallback)(struct __CEC_HandleTypeDef + *hcec); /*!< CEC Tx Transfer completed callback */ + void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, + uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ @@ -221,7 +212,8 @@ typedef enum * @brief HAL CEC Callback pointer definition */ typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */ -typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */ +typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, + uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */ #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ /** * @} @@ -231,7 +223,25 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, uint32_t RxFram /** @defgroup CEC_Exported_Constants CEC Exported Constants * @{ */ - +/** @defgroup CEC_State_Definition CEC State Code Definition + * @{ + */ +#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ +#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */ +/** + * @} + */ /** @defgroup CEC_Error_Code CEC Error Code * @{ */ @@ -413,7 +423,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, uint32_t RxFram * @{ */ #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ - CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) + CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) /** * @} */ @@ -635,7 +645,8 @@ void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, + pCEC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback); @@ -649,7 +660,8 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, + uint8_t *pData, uint32_t Size); uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec); void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer); void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h index 3d197a36a523c5c4eae8ccc1f11353993b983718..1c6c7475e005058e31542c0407b40d0309f39e2e 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h @@ -38,13 +38,13 @@ extern "C" { * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup COMP_Exported_Types COMP Exported Types * @{ */ -/** - * @brief COMP Init structure definition +/** + * @brief COMP Init structure definition */ typedef struct { @@ -80,7 +80,7 @@ typedef struct uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI). This parameter can be a value of @ref COMP_EXTI_TriggerMode */ -}COMP_InitTypeDef; +} COMP_InitTypeDef; /** * @brief HAL COMP state machine: HAL COMP states definition @@ -94,9 +94,9 @@ typedef enum HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */ HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */ HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */ -}HAL_COMP_StateTypeDef; +} HAL_COMP_StateTypeDef; -/** +/** * @brief COMP Handle Structure definition */ #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) @@ -297,10 +297,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @retval None */ #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) -#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_COMP_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ +#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_COMP_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) @@ -311,7 +311,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __HANDLE__ COMP handle * @retval None */ -#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE) +#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE) /** * @brief Enable the specified comparator. @@ -389,7 +389,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ @@ -597,7 +597,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @{ */ -/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators +/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators * @{ */ /** @@ -605,8 +605,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __INSTANCE__ specifies the COMP instance. * @retval value of @ref COMP_ExtiLine */ -#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ - : COMP_EXTI_LINE_COMP2) +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ + : COMP_EXTI_LINE_COMP2) /** * @} */ @@ -694,13 +694,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); -HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, + pCOMP_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_conf_template.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_conf_template.h index 11af9627c1a492d1a2fd49159feae6252cf171c1..f1a7aba38be71295b2726c9433bafa6e0f3ee9e0 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_conf_template.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_conf_template.h @@ -61,7 +61,6 @@ extern "C" { #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED #define HAL_USART_MODULE_ENABLED -#define HAL_UCPD_MODULE_ENABLED #define HAL_WWDG_MODULE_ENABLED /* ########################## Register Callbacks selection ############################## */ @@ -109,6 +108,7 @@ extern "C" { #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ + /** * @brief Internal Low Speed oscillator (LSI) value. */ @@ -138,6 +138,7 @@ in voltage and temperature.*/ #define EXTERNAL_I2S1_CLOCK_VALUE (48000UL) /*!< Value of the I2S1 External clock source in Hz*/ #endif /* EXTERNAL_I2S1_CLOCK_VALUE */ + /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ @@ -282,10 +283,6 @@ in voltage and temperature.*/ #include "stm32g0xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ -#ifdef HAL_UCPD_MODULE_ENABLED -#include "stm32g0xx_ll_ucpd.h" -#endif /* HAL_UCPD_MODULE_ENABLED */ - #ifdef HAL_WWDG_MODULE_ENABLED #include "stm32g0xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp.h index 2f0b14e9c14fa04e8caa324cbb85b351f3f26a05..746cc1b6d272f7e3a5e429bf011624742247e603 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -64,9 +64,12 @@ typedef struct uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication, GCM : also known as Additional Authentication Data CCM : named B1 composed of the associated data length and Associated Data. */ - uint32_t HeaderSize; /*!< The size of header buffer in word */ - uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ + uint32_t HeaderSize; /*!< The size of header buffer in word */ + uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization + Vector only once and to skip configuration for consecutive processings. + This parameter can be a value of @ref CRYP_Configuration_Skip */ } CRYP_ConfigTypeDef; @@ -122,7 +125,7 @@ typedef struct __IO uint16_t CrypOutCount; /*!< Counter of output data */ - uint16_t Size; /*!< length of input data in word */ + uint16_t Size; /*!< length of input data in words */ uint32_t Phase; /*!< CRYP peripheral phase */ @@ -136,6 +139,13 @@ typedef struct __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ + uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when + configuration can be skipped */ + + uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored + for a single signature computation after several + messages processing */ + #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */ void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */ @@ -161,7 +171,7 @@ typedef struct uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing is suspended */ uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing is suspended */ - + __IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing is suspended */ uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */ @@ -247,7 +257,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point */ #define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */ -#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */ +#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */ /** * @} @@ -322,6 +332,18 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @} */ +/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode + * @{ + */ + +#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */ +#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */ + +/** + * @} + */ + + /** * @} */ @@ -540,6 +562,9 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); ((DATATYPE) == CRYP_DATATYPE_8B) || \ ((DATATYPE) == CRYP_DATATYPE_1B)) +#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ + ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) + /** * @} */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h index a386a717a5a5762c701f6d615c306e38c8cf541d..98961f4eace0470422d0672e3c04655117fbd40e 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -110,8 +110,7 @@ typedef struct uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ -} -DAC_SampleAndHoldConfTypeDef; +} DAC_SampleAndHoldConfTypeDef; /** * @brief DAC Configuration regular Channel structure definition @@ -156,8 +155,8 @@ typedef enum HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ - HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ - HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ + HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ + HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ } HAL_DAC_CallbackIDTypeDef; @@ -196,17 +195,18 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_trigger_selection DAC trigger selection * @{ */ -#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ -#define DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ -#define DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1_OUT selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2_OUT selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ +#define DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1_OUT selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2_OUT selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ + /** * @} */ @@ -272,16 +272,14 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); */ /** @defgroup DAC_UserTrimming DAC User Trimming -* @{ -*/ - + * @{ + */ #define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */ #define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */ /** * @} */ - /** @defgroup DAC_SampleAndHold DAC power mode * @{ */ @@ -291,7 +289,6 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** * @} */ - /** * @} */ @@ -322,7 +319,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @retval None */ #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ -((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) + ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) /** @brief Disable the DAC channel. * @param __HANDLE__ specifies the DAC handle @@ -330,7 +327,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @retval None */ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ -((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) + ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) /** @brief Set DHR12R1 alignment. * @param __ALIGNMENT__ specifies the DAC alignment @@ -450,12 +447,13 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); */ /** @addtogroup DAC_Exported_Functions_Group2 - * @{ - */ + * @{ + */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment); +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, + uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); @@ -469,7 +467,8 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* DAC callback registering/unregistering */ -HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, + pDAC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ @@ -503,6 +502,16 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); * @} */ +/** @defgroup DAC_Private_Functions DAC Private Functions + * @{ + */ +void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); +void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); +/** + * @} + */ + /** * @} */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h index 9c8490d4a13309b7af4f7f82f027132348165b79..5343ba5cdd3f63b1a62d8da7040989367ef2fbde 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -122,7 +122,7 @@ extern "C" { ((CONNECT) == DAC_CHIPCONNECT_ENABLE)) #define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \ - ((TRIMMING) == DAC_TRIMMING_USER)) + ((TRIMMING) == DAC_TRIMMING_USER)) #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ @@ -160,8 +160,8 @@ extern "C" { */ /** @addtogroup DACEx_Exported_Functions_Group2 - * @{ - */ + * @{ + */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); @@ -186,7 +186,8 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue); +HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, + uint32_t NewTrimmingValue); uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel); /** @@ -197,7 +198,6 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel); * @} */ - /** @addtogroup DACEx_Private_Functions * @{ */ @@ -209,8 +209,8 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); /** - * @} - */ + * @} + */ /** * @} diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h index 60758ff74654a0dd4a28be3a0aae06f3610494e9..b44f106c27b3aef2ba2f03efd7284ab901a32cdd 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h @@ -277,6 +277,7 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_UCPD2_RX 60U /*!< DMAMUX UCPD2 RX request */ #define DMA_REQUEST_UCPD2_TX 61U /*!< DMAMUX UCPD2 TX request */ #endif + /** * @} */ @@ -668,6 +669,8 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #if defined(STM32G081xx)||defined(STM32G071xx)||defined(STM32G070xx) #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD2_TX) +#elif defined(STM32G041xx)||defined(STM32G031xx)||defined(STM32G030xx) +#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_USART2_TX) #endif #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h index 71379999a654dde66c368b33dcde6498e054822c..3addf72eeb020fd67b135097cb7c850950e196f5 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -49,9 +49,9 @@ typedef struct uint32_t TypeErase; /*!< Mass erase or page erase. This parameter can be a value of @ref FLASH_Type_Erase */ uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled - This parameter must be a value between 0 and (max number of pages - 1) */ + This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */ uint32_t NbPages; /*!< Number of pages to be erased. - This parameter must be a value between 1 and (max number of pages - value of initial page)*/ + This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/ } FLASH_EraseInitTypeDef; /** @@ -65,9 +65,9 @@ typedef struct Only one WRP area could be programmed at the same time. This parameter can be value of @ref FLASH_OB_WRP_Area */ uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). - This parameter must be a value between [0] and [max number of pages - 1]*/ + This parameter must be a value between 0 and [FLASH_PAGE_NB - 1]*/ uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). - This parameter must be a value between WRPStartOffset and [max number of pages - 1] */ + This parameter must be a value between WRPStartOffset and [FLASH_PAGE_NB - 1] */ uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). This parameter can be a value of @ref FLASH_OB_Read_Protection */ uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). @@ -107,11 +107,24 @@ typedef struct #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) uint32_t BootEntryPoint; /*!< Allow to force a unique boot entry point to Flash or system Flash */ uint32_t SecSize; /*!< This parameter defines securable memory area width in number of pages starting from Flash base address. - This parameter must be a value between [0] and [max number of pages], + This parameter must be a value between [0] and [FLASH_PAGE_NB], [0] meaning no secure area defined, [1] meaning first page only protected, etc... */ #endif } FLASH_OBProgramInitTypeDef; +/** +* @brief FLASH handle Structure definition +*/ +typedef struct +{ + HAL_LockTypeDef Lock; /* FLASH locking object */ + uint32_t ErrorCode; /* FLASH error code */ + uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ + uint32_t Address; /* Internal variable to save address selected for program in IT context */ + uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ + uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ +} FLASH_ProcessTypeDef; + /** * @} */ @@ -123,11 +136,11 @@ typedef struct /** @defgroup FLASH_Keys FLASH Keys * @{ */ -#define FLASH_KEY1 0x45670123u /*!< Flash key1 */ -#define FLASH_KEY2 0xCDEF89ABu /*!< Flash key2: used with FLASH_KEY1 +#define FLASH_KEY1 0x45670123U /*!< Flash key1 */ +#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 to unlock the FLASH registers access */ -#define FLASH_OPTKEY1 0x08192A3Bu /*!< Flash option byte key1 */ -#define FLASH_OPTKEY2 0x4C5D6E7Fu /*!< Flash option byte key2: used with FLASH_OPTKEY1 +#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ +#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 to allow option bytes operations */ /** * @} @@ -136,7 +149,7 @@ typedef struct /** @defgroup FLASH_Latency FLASH Latency * @{ */ -#define FLASH_LATENCY_0 0x00000000u /*!< FLASH Zero wait state */ +#define FLASH_LATENCY_0 0x00000000UL /*!< FLASH Zero wait state */ #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */ #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ /** @@ -189,7 +202,7 @@ typedef struct #if defined(FLASH_PCROP_SUPPORT) #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/ #endif -#define FLASH_IT_ECCC (FLASH_ECCR_ECCCIE >> 24) /*!< ECC Correction Interrupt source */ +#define FLASH_IT_ECCC (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos) /*!< ECC Correction Interrupt source */ /** * @} */ @@ -197,7 +210,7 @@ typedef struct /** @defgroup FLASH_Error FLASH Error * @{ */ -#define HAL_FLASH_ERROR_NONE 0x00000000u +#define HAL_FLASH_ERROR_NONE 0x00000000U #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR @@ -227,9 +240,8 @@ typedef struct /** @defgroup FLASH_Type_Program FLASH Program Type * @{ */ -#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /*!< Program a double-word (64-bit) at a specified address.*/ -#define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /*!< Fast program a 32 row double-word (64-bit) at a specified address. - And another 32 row double-word (64-bit) will be programmed */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /*!< Program a double-word (64-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /*!< Fast program a 32 row double-word (64-bit) at a specified address */ /** * @} */ @@ -237,20 +249,20 @@ typedef struct /** @defgroup FLASH_OB_Type FLASH Option Bytes Type * @{ */ -#define OPTIONBYTE_WRP 0x01u /*!< WRP option byte configuration */ -#define OPTIONBYTE_RDP 0x02u /*!< RDP option byte configuration */ -#define OPTIONBYTE_USER 0x04u /*!< USER option byte configuration */ +#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ #if defined(FLASH_PCROP_SUPPORT) -#define OPTIONBYTE_PCROP 0x08u /*!< PCROP option byte configuration */ +#define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */ #endif #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) -#define OPTIONBYTE_SEC 0x10u /*!< SEC option byte configuration */ +#define OPTIONBYTE_SEC 0x00000010U /*!< SEC option byte configuration */ #endif -#if defined(STM32G071xx) || defined(STM32G081xx) +#if defined(STM32G071xx) || defined(STM32G081xx) || defined(STM32G031xx) || defined(STM32G041xx) #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ OPTIONBYTE_PCROP | OPTIONBYTE_SEC) /*!< All option byte configuration */ -#elif defined (STM32G070xx) +#elif defined (STM32G070xx) || defined (STM32G030xx) #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER) /*!< All option byte configuration */ #endif /** @@ -260,8 +272,8 @@ typedef struct /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area * @{ */ -#define OB_WRPAREA_ZONE_A 0x01u /*!< Flash Zone A */ -#define OB_WRPAREA_ZONE_B 0x02u /*!< Flash Zone B */ +#define OB_WRPAREA_ZONE_A 0x00000001U /*!< Flash Zone A */ +#define OB_WRPAREA_ZONE_B 0x00000002U /*!< Flash Zone B */ /** * @} */ @@ -269,10 +281,10 @@ typedef struct /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection * @{ */ -#define OB_RDP_LEVEL_0 0xAAu -#define OB_RDP_LEVEL_1 0xBBu -#define OB_RDP_LEVEL_2 0xCCu /*!< Warning: When enabling read protection level 2 - it is no more possible to go back to level 1 or 0 */ +#define OB_RDP_LEVEL_0 0x000000AAU +#define OB_RDP_LEVEL_1 0x000000BBU +#define OB_RDP_LEVEL_2 0x000000CCU /*!< Warning: When enabling read protection level 2 + it is no more possible to go back to level 1 or 0 */ /** * @} */ @@ -303,13 +315,13 @@ typedef struct #if defined(FLASH_OPTR_IRHEN) #define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */ #endif -#if defined(STM32G071xx) || defined(STM32G081xx) +#if defined(STM32G071xx) || defined(STM32G081xx) || defined(STM32G031xx) || defined(STM32G041xx) #define OB_USER_ALL (OB_USER_BOR_EN | OB_USER_BOR_LEV | OB_USER_nRST_STOP | \ OB_USER_nRST_STDBY | OB_USER_nRST_SHDW | OB_USER_IWDG_SW | \ OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ OB_USER_nBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */ -#elif defined (STM32G070xx) +#elif defined (STM32G070xx) || defined (STM32G030xx) #define OB_USER_ALL ( OB_USER_nRST_STOP | \ OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \ OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ @@ -324,7 +336,7 @@ typedef struct /** @defgroup FLASH_OB_USER_BOR_ENABLE FLASH Option Bytes User BOR enable * @{ */ -#define OB_BOR_DISABLE 0x00000000u /*!< BOR Reset set to default */ +#define OB_BOR_DISABLE 0x00000000U /*!< BOR Reset set to default */ #define OB_BOR_ENABLE FLASH_OPTR_BOR_EN /*!< Use option byte to define BOR thresholds */ /** * @} @@ -333,11 +345,11 @@ typedef struct /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level * @{ */ -#define OB_BOR_LEVEL_FALLING_0 0x00000000u /*!< BOR falling level 1 with threshold around 2.0V */ +#define OB_BOR_LEVEL_FALLING_0 0x00000000U /*!< BOR falling level 1 with threshold around 2.0V */ #define OB_BOR_LEVEL_FALLING_1 FLASH_OPTR_BORF_LEV_0 /*!< BOR falling level 2 with threshold around 2.2V */ #define OB_BOR_LEVEL_FALLING_2 FLASH_OPTR_BORF_LEV_1 /*!< BOR falling level 3 with threshold around 2.5V */ #define OB_BOR_LEVEL_FALLING_3 (FLASH_OPTR_BORF_LEV_0 | FLASH_OPTR_BORF_LEV_1) /*!< BOR falling level 4 with threshold around 2.8V */ -#define OB_BOR_LEVEL_RISING_0 0x00000000u /*!< BOR rising level 1 with threshold around 2.1V */ +#define OB_BOR_LEVEL_RISING_0 0x00000000U /*!< BOR rising level 1 with threshold around 2.1V */ #define OB_BOR_LEVEL_RISING_1 FLASH_OPTR_BORR_LEV_0 /*!< BOR rising level 2 with threshold around 2.3V */ #define OB_BOR_LEVEL_RISING_2 FLASH_OPTR_BORR_LEV_1 /*!< BOR rising level 3 with threshold around 2.6V */ #define OB_BOR_LEVEL_RISING_3 (FLASH_OPTR_BORR_LEV_0 | FLASH_OPTR_BORR_LEV_1) /*!< BOR rising level 4 with threshold around 2.9V */ @@ -349,7 +361,7 @@ typedef struct /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop * @{ */ -#define OB_STOP_RST 0x00000000u /*!< Reset generated when entering the stop mode */ +#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ /** * @} @@ -358,7 +370,7 @@ typedef struct /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby * @{ */ -#define OB_STANDBY_RST 0x00000000u /*!< Reset generated when entering the standby mode */ +#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ /** * @} @@ -368,7 +380,7 @@ typedef struct /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown * @{ */ -#define OB_SHUTDOWN_RST 0x00000000u /*!< Reset generated when entering the shutdown mode */ +#define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ #define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ /** * @} @@ -378,7 +390,7 @@ typedef struct /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type * @{ */ -#define OB_IWDG_HW 0x00000000u /*!< Hardware independent watchdog */ +#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ /** * @} @@ -387,7 +399,7 @@ typedef struct /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop * @{ */ -#define OB_IWDG_STOP_FREEZE 0x00000000u /*!< Independent watchdog counter is frozen in Stop mode */ +#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ /** * @} @@ -396,7 +408,7 @@ typedef struct /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby * @{ */ -#define OB_IWDG_STDBY_FREEZE 0x00000000u /*!< Independent watchdog counter is frozen in Standby mode */ +#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ /** * @} @@ -405,7 +417,7 @@ typedef struct /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type * @{ */ -#define OB_WWDG_HW 0x00000000u /*!< Hardware window watchdog */ +#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ /** * @} @@ -414,7 +426,7 @@ typedef struct /** @defgroup FLASH_OB_USER_SRAM_PARITY FLASH Option Bytes User SRAM parity * @{ */ -#define OB_SRAM_PARITY_ENABLE 0x00000000u /*!< Sram parity enable */ +#define OB_SRAM_PARITY_ENABLE 0x00000000U /*!< Sram parity enable */ #define OB_SRAM_PARITY_DISABLE FLASH_OPTR_RAM_PARITY_CHECK /*!< Sram parity disable */ /** * @} @@ -423,7 +435,7 @@ typedef struct /** @defgroup FLASH_OB_USER_nBOOT_SEL FLASH Option Bytes User Boot0 Selection * @{ */ -#define OB_BOOT0_FROM_PIN 0x00000000u /*!< BOOT0 signal is defined by PA14/BOOT0 pin value */ +#define OB_BOOT0_FROM_PIN 0x00000000U /*!< BOOT0 signal is defined by PA14/BOOT0 pin value */ #define OB_BOOT0_FROM_OB FLASH_OPTR_nBOOT_SEL /*!< BOOT0 signal is defined by nBOOT0 option bit */ /** * @} @@ -432,7 +444,7 @@ typedef struct /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type * @{ */ -#define OB_BOOT1_SRAM 0x00000000u /*!< Embedded SRAM is selected as boot space (if nBOOT0=0 or BOOT0_pin=1) */ +#define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM is selected as boot space (if nBOOT0=0 or BOOT0_pin=1) */ #define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if nBOOT0=0 or BOOT0_pin=1) */ /** * @} @@ -441,7 +453,7 @@ typedef struct /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit * @{ */ -#define OB_nBOOT0_RESET 0x00000000u /*!< nBOOT0 = 0 */ +#define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ #define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ /** * @} @@ -463,7 +475,7 @@ typedef struct /** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit * @{ */ -#define OB_IRH_ENABLE 0x00000000u /*!< Internal Reset handler enable */ +#define OB_IRH_ENABLE 0x00000000U /*!< Internal Reset handler enable */ #define OB_IRH_DISABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler disable */ /** * @} @@ -474,8 +486,8 @@ typedef struct /** @defgroup FLASH_OB_PCROP_ZONE FLASH Option Bytes PCROP ZONE * @{ */ -#define OB_PCROP_ZONE_A 0x01u /*!< Zone A */ -#define OB_PCROP_ZONE_B 0x02u /*!< Zone B */ +#define OB_PCROP_ZONE_A 0x00000001U /*!< PCROP Zone A */ +#define OB_PCROP_ZONE_B 0x00000002U /*!< PCROP Zone B */ /** * @} */ @@ -483,7 +495,7 @@ typedef struct /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type * @{ */ -#define OB_PCROP_RDP_NOT_ERASE 0x00000000u /*!< PCROP area is not erased when the RDP level +#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0 */ #define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase). @@ -497,7 +509,7 @@ typedef struct /** @defgroup FLASH_OB_SEC_BOOT_LOCK FLASH Option Bytes Secure boot lock * @{ */ -#define OB_BOOT_ENTRY_FORCED_NONE 0x00000000u /*!< Boot entry is free */ +#define OB_BOOT_ENTRY_FORCED_NONE 0x00000000U /*!< Boot entry is free */ #define OB_BOOT_ENTRY_FORCED_FLASH FLASH_SECR_BOOT_LOCK /*!< Boot entry is forced to Flash or System Flash */ /** * @} @@ -518,9 +530,9 @@ typedef struct * @brief Set the FLASH Latency. * @param __LATENCY__ FLASH Latency * This parameter can be one of the following values : - * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state - * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state + * @arg @ref FLASH_LATENCY_1 FLASH One wait state + * @arg @ref FLASH_LATENCY_2 FLASH Two wait states * @retval None */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) @@ -528,10 +540,10 @@ typedef struct /** * @brief Get the FLASH Latency. * @retval FLASH Latency - * This parameter can be one of the following values : - * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state - * @arg FLASH_LATENCY_2: FLASH Two wait states + * Returned value can be one of the following values : + * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state + * @arg @ref FLASH_LATENCY_1 FLASH One wait state + * @arg @ref FLASH_LATENCY_2 FLASH Two wait states */ #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) @@ -564,8 +576,9 @@ typedef struct * @note This function must be used only when the Instruction Cache is disabled. * @retval None */ -#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() SET_BIT(FLASH->ACR, FLASH_ACR_ICRST) - +#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + } while (0U) /** * @} */ @@ -579,10 +592,10 @@ typedef struct * @brief Enable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt - * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt(*) - * @arg FLASH_IT_ECCC: ECC Correction Interrupt + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt(*) + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt * @note (*) availability depends on devices * @retval none */ @@ -594,10 +607,10 @@ typedef struct * @brief Disable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt - * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt(*) - * @arg FLASH_IT_ECCC: ECC Correction Interrupt + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt(*) + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt * @note (*) availability depends on devices * @retval none */ @@ -609,21 +622,21 @@ typedef struct * @brief Check whether the specified FLASH flag is set or not. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH Operation error flag - * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag - * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag - * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag - * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag(*) - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag - * @arg FLASH_FLAG_CFGBSY: FLASH configuration is busy : program or erase setting are used. - * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected - * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag + * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag + * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag(*) + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag + * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag + * @arg @ref FLASH_FLAG_CFGBSY FLASH configuration is busy : program or erase setting are used. + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected * @note (*) availability depends on devices * @retval The new state of FLASH_FLAG (SET or RESET). */ @@ -635,20 +648,20 @@ typedef struct * @brief Clear the FLASHs pending flags. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH Operation error flag - * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag - * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag - * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag - * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected - * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected - * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag + * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag + * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected + * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags * @retval None */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ @@ -660,6 +673,14 @@ typedef struct /* Include FLASH HAL Extended module */ #include "stm32g0xx_hal_flash_ex.h" +/* Exported variables --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Variables FLASH Exported Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_Exported_Functions @@ -672,7 +693,9 @@ typedef struct */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /** @@ -685,6 +708,7 @@ void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); */ HAL_StatusTypeDef HAL_FLASH_Unlock(void); HAL_StatusTypeDef HAL_FLASH_Lock(void); +/* Option bytes control */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); @@ -709,19 +733,7 @@ uint32_t HAL_FLASH_GetError(void); /** @defgroup FLASH_Private_types FLASH Private Types * @{ */ -/** -* @brief FLASH handle Structure definition -*/ -typedef struct -{ - HAL_LockTypeDef Lock; /* FLASH locking object */ - uint32_t ErrorCode; /* FLASH error code */ - uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ - uint32_t Address; /* Internal variable to save address selected for program in IT context */ - uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ - uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ -} FLASH_ProcessTypeDef; - +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @} */ @@ -732,21 +744,21 @@ typedef struct */ #define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE -#define FLASH_SIZE (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x00FFu)) << 10u) +#define FLASH_SIZE (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x00FFU)) << 10U) -#define FLASH_BANK_SIZE (FLASH_SIZE) +#define FLASH_BANK_SIZE (FLASH_SIZE) /*!< FLASH Bank Size */ -#define FLASH_PAGE_SIZE 0x800u +#define FLASH_PAGE_SIZE 0x00000800U /*!< FLASH Page Size, 2 KBytes */ #if defined(STM32G081xx)||defined(STM32G071xx)||defined(STM32G070xx) -#define FLASH_PAGE_NB 64u +#define FLASH_PAGE_NB 64U #else -#define FLASH_PAGE_NB 32u +#define FLASH_PAGE_NB 32U #endif -#define FLASH_TIMEOUT_VALUE 1000u /* 1 s */ +#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */ -#define FLASH_TYPENONE 0x00u +#define FLASH_TYPENONE 0x00000000U /*!< No Programmation Procedure On Going */ #if defined(FLASH_PCROP_SUPPORT) #define FLASH_FLAG_SR_ERROR (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ @@ -759,6 +771,8 @@ typedef struct FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | \ FLASH_FLAG_OPTVERR) /*!< All SR error flags */ #endif + +#define FLASH_FLAG_SR_CLEAR (FLASH_FLAG_SR_ERROR | FLASH_SR_EOP) /** * @} */ @@ -767,19 +781,19 @@ typedef struct /** @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ -#define IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1u))) +#define IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) -#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8u))) +#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8UL))) -#define IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= 0x1FFF7000u) && ((__ADDRESS__) <= (0x1FFF7400u - 8u))) +#define IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= 0x1FFF7000U) && ((__ADDRESS__) <= (0x1FFF7400U - 8UL))) #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__)) || (IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__))) -#define IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256u))) +#define IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256UL))) #define IS_FLASH_PAGE(__PAGE__) ((__PAGE__) < FLASH_PAGE_NB) -#define IS_FLASH_BANK(__BANK__) ((__BANK__) == 0x00u) +#define IS_FLASH_BANK(__BANK__) ((__BANK__) == 0x00UL) #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \ ((__VALUE__) == FLASH_TYPEERASE_MASS)) @@ -787,8 +801,8 @@ typedef struct #define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) -#define IS_OPTIONBYTE(__VALUE__) ((((__VALUE__) & OPTIONBYTE_ALL) != 0x00u) && \ - (((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00u)) +#define IS_OPTIONBYTE(__VALUE__) ((((__VALUE__) & OPTIONBYTE_ALL) != 0x00U) && \ + (((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U)) #define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B)) @@ -796,19 +810,19 @@ typedef struct ((__LEVEL__) == OB_RDP_LEVEL_1) ||\ ((__LEVEL__) == OB_RDP_LEVEL_2)) -#define IS_OB_USER_TYPE(__TYPE__) ((((__TYPE__) & OB_USER_ALL) != 0x00u) && \ - (((__TYPE__) & ~OB_USER_ALL) == 0x00u)) +#define IS_OB_USER_TYPE(__TYPE__) ((((__TYPE__) & OB_USER_ALL) != 0x00U) && \ + (((__TYPE__) & ~OB_USER_ALL) == 0x00U)) -#define IS_OB_USER_CONFIG(__TYPE__,__CONFIG__) ((~(__TYPE__) & (__CONFIG__)) == 0x00u) +#define IS_OB_USER_CONFIG(__TYPE__,__CONFIG__) ((~(__TYPE__) & (__CONFIG__)) == 0x00U) #if defined(FLASH_PCROP_SUPPORT) -#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00u) +#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U) #endif #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) #define IS_OB_SEC_BOOT_LOCK(__VALUE__) (((__VALUE__) == OB_BOOT_ENTRY_FORCED_NONE) || ((__VALUE__) == OB_BOOT_ENTRY_FORCED_FLASH)) -#define IS_OB_SEC_SIZE(__VALUE__) ((__VALUE__) < (FLASH_PAGE_NB + 1u)) +#define IS_OB_SEC_SIZE(__VALUE__) ((__VALUE__) < (FLASH_PAGE_NB + 1U)) #endif #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h index 86b2f65c8d679da2e50dba396bae3af6641464fe..25a8fc605419c8eb569875152ccc5fcba2277fd3 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -44,8 +44,8 @@ extern "C" { /** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check * @{ */ -#define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */ -#define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */ +#define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */ +#define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */ /** * @} */ @@ -86,8 +86,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants * @{ */ -#define FLASH_PCROP_GRANULARITY_OFFSET 9u -#define FLASH_PCROP_GRANULARITY (1u << FLASH_PCROP_GRANULARITY_OFFSET) +#define FLASH_PCROP_GRANULARITY_OFFSET 9u /*!< FLASH Code Readout Protection granularity offset */ +#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 512 Bytes */ /** * @} */ @@ -97,7 +97,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); * @{ */ #define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY)) - +void FLASH_PageErase(uint32_t Page); /** * @} */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h index f09f89e24d659fa61aab29f8deed4d162899ef6e..fd89eb32c78b7be16bcb0f0c441eeeae34b73789 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h @@ -251,8 +251,8 @@ typedef enum */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ - (((__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h index ad42bb75bc75654ee412d64f6ac4253ce3495293..939b87605decbb7c7ab4cb0cc5df676ca7f0dac2 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h @@ -47,6 +47,8 @@ extern "C" { * @{ */ + + #if defined (STM32G081xx) || defined (STM32G071xx) /*------------------------- STM32G081xx / STM32G071xx ------------------------*/ /** @@ -228,7 +230,152 @@ extern "C" { #endif /* STM32G070xx */ +#if defined (STM32G031xx) || defined (STM32G041xx) +/*------------------------- STM32G041xx / STM32G031xx ------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_LPUART1 ((uint8_t)0x01) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF5_LPTIM2 ((uint8_t)0x05) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /*!< LPUART1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G031xx || STM32G041xx */ + +#if defined (STM32G030xx) +/*------------------------- STM32G030xx --------------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) +#endif /* STM32G030xx */ /** * @} diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h index c255fecd57af485d79c5561fe66699bc246d438e..e05d5fad8383e5016e905d5c825c27db447387f2 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h @@ -86,17 +86,17 @@ typedef struct * 01 : Abort (Abort user request on going)\n * 10 : Timeout\n * 11 : Error\n - * b5 IP initilisation status\n - * 0 : Reset (IP not initialized)\n - * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n * b4 (not used)\n * x : Should be set to 0\n * b3\n * 0 : Ready or Busy (No Listen mode ongoing)\n - * 1 : Listen (IP in Address Listen Mode)\n + * 1 : Listen (peripheral in Address Listen Mode)\n * b2 Intrinsic process state\n * 0 : Ready\n - * 1 : Busy (IP busy with some configuration or internal operations)\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n * b1 Rx state\n * 0 : Ready (no Rx operation ongoing)\n * 1 : Busy (Rx operation ongoing)\n diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h index edf5754da7b6e167c7547ecc84bbb6b57fb02068..c856b7c75c66e79fec4560ba75cba2feb2cca84a 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h @@ -117,6 +117,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)) + + + /** * @} */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2s.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2s.h index 3e7274aba19bea4825de42cecdc77dd7e15d56c1..3aea71d65a407a98d4cc63f29280ae9ed8bd499f 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2s.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2s.h @@ -83,7 +83,11 @@ typedef enum /** * @brief I2S handle Structure definition */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1) typedef struct __I2S_HandleTypeDef +#else +typedef struct +#endif { SPI_TypeDef *Instance; /*!< I2S registers base address */ @@ -265,6 +269,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE #define I2S_FLAG_BSY SPI_SR_BSY + +#define I2S_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) /** * @} */ @@ -459,29 +465,65 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); /** @defgroup I2S_Private_Macros I2S Private Macros * @{ */ -#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ - ((MODE) == I2S_MODE_SLAVE_RX) || \ - ((MODE) == I2S_MODE_MASTER_TX) || \ - ((MODE) == I2S_MODE_MASTER_RX)) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \ - ((STANDARD) == I2S_STANDARD_MSB) || \ - ((STANDARD) == I2S_STANDARD_LSB) || \ - ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \ - ((STANDARD) == I2S_STANDARD_PCM_LONG)) +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of I2S SR regsiter. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXNE: Receive buffer not empty flag + * @arg I2S_FLAG_TXE: Transmit buffer empty flag + * @arg I2S_FLAG_UDR: Underrun error flag + * @arg I2S_FLAG_OVR: Overrun flag + * @arg I2S_FLAG_CHSIDE: Channel side flag + * @arg I2S_FLAG_BSY: Busy flag + * @retval SET or RESET. + */ +#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \ - ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \ - ((FORMAT) == I2S_DATAFORMAT_24B) || \ - ((FORMAT) == I2S_DATAFORMAT_32B)) +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of I2S CR2 regsiter. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \ - ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE)) +/** @brief Checks if I2S Mode parameter is in allowed range. + * @param __MODE__ specifies the I2S Mode. + * This parameter can be a value of @ref I2S_Mode + * @retval None + */ +#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ + ((__MODE__) == I2S_MODE_SLAVE_RX) || \ + ((__MODE__) == I2S_MODE_MASTER_TX) || \ + ((__MODE__) == I2S_MODE_MASTER_RX)) -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \ - ((FREQ) <= I2S_AUDIOFREQ_192K)) || \ - ((FREQ) == I2S_AUDIOFREQ_DEFAULT)) +#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ + ((__STANDARD__) == I2S_STANDARD_MSB) || \ + ((__STANDARD__) == I2S_STANDARD_LSB) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) +#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ + ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ + ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ + ((__FORMAT__) == I2S_DATAFORMAT_32B)) + +#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ + ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) + +#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ + ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ + ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) + +/** @brief Checks if I2S Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the I2S serial clock steady state. + * This parameter can be a value of @ref I2S_Clock_Polarity + * @retval None + */ #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \ ((CPOL) == I2S_CPOL_HIGH)) diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda.h index b4af07cfa2b144c2e3ad13c782fda9d216b02853..4329445c0b46ca76b8e79f79937db8df77e11a02 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda.h @@ -169,7 +169,7 @@ typedef struct __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations. This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ - uint32_t ErrorCode; /*!< IRDA Error code */ + __IO uint32_t ErrorCode; /*!< IRDA Error code */ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */ @@ -302,7 +302,7 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @} */ -/** @defgroup IRDA_ClockPrescaler Clock Prescaler +/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler * @{ */ #define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ @@ -456,8 +456,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer */ /** - * @} - */ + * @} + */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup IRDA_Exported_Macros IRDA Exported Macros @@ -487,10 +487,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @retval None */ #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ - } while(0U) + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified IRDA pending flag. * @param __HANDLE__ specifies the IRDA Handle. @@ -605,7 +605,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -620,8 +621,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @retval The new state of __IT__ (SET or RESET). */ #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) + (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. @@ -659,7 +660,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ -#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) +#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle. * @param __HANDLE__ specifies the IRDA Handle. @@ -706,7 +708,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @param __MODE__ IRDA communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) +#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\ + & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** @brief Ensure that IRDA power mode is valid. * @param __MODE__ IRDA power mode. @@ -720,17 +723,17 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ #define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) /** @brief Ensure that IRDA state is valid. * @param __STATE__ IRDA state mode. @@ -775,8 +778,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \ ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST)) /** - * @} - */ + * @} + */ /* Include IRDA HAL Extended module */ #include "stm32g0xx_hal_irda_ex.h" @@ -798,7 +801,8 @@ void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda_ex.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda_ex.h index daac9567010f132418dda0b53b2ab82ec8c2f808..1fe8a27512ae41e698daf670e056b11bd3697da3 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda_ex.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda_ex.h @@ -33,6 +33,7 @@ extern "C" { */ /** @defgroup IRDAEx IRDAEx + * @brief IRDA Extended HAL module driver * @{ */ @@ -74,8 +75,8 @@ extern "C" { do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -91,12 +92,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -112,14 +113,47 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else \ { \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#endif +#elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* STM32G081xx || STM32G071xx || STM32G070xx */ /** @brief Compute the mask to apply to retrieve the received data * according to the word length and to the parity bits activation. @@ -128,44 +162,44 @@ extern "C" { */ #define IRDA_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ + if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ -} while(0U) + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** @brief Ensure that IRDA frame length is valid. * @param __LENGTH__ IRDA frame length. diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h index bd1ea0b0b5ab8bb14519c193adbf64549e8be28e..23b3953ed4634b4d9b2641394c626b45053beb55 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -119,7 +119,7 @@ typedef struct /** * @brief Reload IWDG counter with value defined in the reload register - * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled). + * (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled). * @param __HANDLE__ IWDG handle * @retval None */ @@ -219,6 +219,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); */ #define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN) + /** * @} */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h index 29ab2b2ef60bfa4ba59a6d145f395b5cbfdc4c4f..fa4dc6542053cf0c046f4f18c494cf4ba7612d71 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h @@ -27,6 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g0xx_hal_def.h" +#include "stm32g0xx_ll_rcc.h" /** @addtogroup STM32G0xx_HAL_Driver * @{ @@ -2126,19 +2127,32 @@ typedef struct */ #if defined(RCC_PLLQ_SUPPORT) #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ - (RCC->PLLCFGR = ((uint32_t) (__PLLR__) | \ - (uint32_t) (__PLLQ__) | \ - (uint32_t) (__PLLP__) | \ - (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ - (uint32_t) (__PLLM__) | \ - (uint32_t) (__PLLSOURCE__))) + MODIFY_REG( RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | \ + RCC_PLLCFGR_PLLM | \ + RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLP | \ + RCC_PLLCFGR_PLLQ | \ + RCC_PLLCFGR_PLLR), \ + ((uint32_t) (__PLLSOURCE__) | \ + (uint32_t) (__PLLM__) | \ + (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + (uint32_t) (__PLLP__) | \ + (uint32_t) (__PLLQ__) | \ + (uint32_t) (__PLLR__))) #else #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLR__ ) \ - (RCC->PLLCFGR = ((uint32_t) (__PLLR__) | \ - (uint32_t) (__PLLP__) | \ - (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ - (uint32_t) (__PLLM__) | \ - (uint32_t) (__PLLSOURCE__))) + MODIFY_REG( RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | \ + RCC_PLLCFGR_PLLM | \ + RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLP | \ + RCC_PLLCFGR_PLLR), \ + ((uint32_t) (__PLLSOURCE__) | \ + (uint32_t) (__PLLM__) | \ + (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + (uint32_t) (__PLLP__) | \ + (uint32_t) (__PLLR__))) #endif /** @brief Macro to get the oscillator used as PLL clock source. * @retval The oscillator used as PLL clock source. The returned value can be one diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h index 77f29172a0561c7d3795cc52c9a5677e166ac894..a4cf2831877b87ba91ec2f8ab767a0fa2b883fbe 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h @@ -683,6 +683,36 @@ void HAL_RCCEx_DisableLSCO(void); (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32G041xx) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) +#elif defined(STM32G031xx) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) +#elif defined(STM32G030xx) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #endif /* STM32G081xx */ #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rng.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rng.h index fb360bbc424afd06519a73382193b751787c203c..d13c107c0ed3ec5cdd039af3f3411e515e5bf720 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rng.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rng.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -22,10 +22,9 @@ #define STM32G0xx_HAL_RNG_H #ifdef __cplusplus -extern "C" { + extern "C" { #endif -#if defined(STM32G081xx) /* Includes ------------------------------------------------------------------*/ #include "stm32g0xx_hal_def.h" @@ -33,6 +32,8 @@ extern "C" { * @{ */ +#if defined (RNG) + /** @defgroup RNG RNG * @brief RNG HAL module driver * @{ @@ -76,7 +77,11 @@ typedef enum /** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition * @{ */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) typedef struct __RNG_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */ { RNG_TypeDef *Instance; /*!< Register base address */ @@ -166,12 +171,14 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t /** @defgroup RNG_Error_Definition RNG Error Definition * @{ */ -#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) #define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ #define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ - +#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ +#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ +#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ /** * @} */ @@ -341,6 +348,7 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \ ((FLAG) == RNG_FLAG_CECS) || \ ((FLAG) == RNG_FLAG_SECS)) + /** * @brief Verify the RNG Clock Error Detection mode. * @param __MODE__ RNG Clock Error Detection mode @@ -356,15 +364,17 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); * @} */ +#endif /* RNG */ + /** * @} */ -#endif #ifdef __cplusplus } #endif + #endif /* STM32G0xx_HAL_RNG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h index d8db732a24a14f956334f4ea1725c57df3128c89..d82256ceb7d1cb17f89543ded50d58d080946e74 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h @@ -467,10 +467,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @} */ -/** @defgroup RTC_Interruption_Mask RTC Interruptions Flag Mask +/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) describe in RTC_Flags_Definitions * @{ */ -#define RTC_IT_MASK 0x001Fu /*!< RTC interruptions flags mask */ +#define RTC_FLAG_MASK 0x001Fu /*!< RTC flags mask (5bits) */ /** * @} */ @@ -480,23 +480,23 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * - YYYYY : Interrupt flag position in the XX register (5bits) * - XX : Interrupt status register (2bits) * - 01: ICSR register - * - 10: SR register + * - 10: SR or SCR or MISR or SMISR registers * @{ */ -#define RTC_FLAG_RECALPF 0x00000110u /*!< Recalibration pending Flag */ -#define RTC_FLAG_INITF 0x00000106u /*!< Initialization flag */ -#define RTC_FLAG_RSF 0x00000105u /*!< Registers synchronization flag */ -#define RTC_FLAG_INITS 0x00000104u /*!< Initialization status flag */ -#define RTC_FLAG_SHPF 0x00000103u /*!< Shift operation pending flag */ -#define RTC_FLAG_WUTWF 0x00000102u /*!< Wakeup timer write flag */ -#define RTC_FLAG_ALRBWF 0x00000101u /*!< Alarm B write flag */ -#define RTC_FLAG_ALRAWF 0x00000100u /*!< Alarm A write flag */ -#define RTC_FLAG_ITSF 0x00000205u /*!< Internal Time-stamp flag */ -#define RTC_FLAG_TSOVF 0x00000204u /*!< Time-stamp overflow flag */ -#define RTC_FLAG_TSF 0x00000203u /*!< Time-stamp flag */ -#define RTC_FLAG_WUTF 0x00000202u /*!< Wakeup timer flag */ -#define RTC_FLAG_ALRBF 0x00000201u /*!< Alarm B flag */ -#define RTC_FLAG_ALRAF 0x00000200u /*!< Alarm A flag */ +#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */ +#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */ +#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */ +#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */ +#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */ +#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */ +#define RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos) /*!< Alarm B write flag */ +#define RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos) /*!< Alarm A write flag */ +#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Internal Time-stamp flag */ +#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Time-stamp overflow flag */ +#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Time-stamp flag */ +#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Wakeup timer flag */ +#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Alarm B flag */ +#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Alarm A flag */ /** * @} */ @@ -936,6 +936,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); uint8_t RTC_ByteToBcd2(uint8_t Value); uint8_t RTC_Bcd2ToByte(uint8_t Value); /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h index 90800b27a01f8bac023331733c49b24bd65b0553..5166bd81f2109fccd68377403fa28893edd1318c 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -391,8 +391,8 @@ typedef struct * @arg @ref RTC_FLAG_ALRAF Alarm A flag * @retval None */ -#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))) != 0U) ? 1U : 0U) :\ - ((((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))) != 0U) ? 1U : 0U)) +#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U) :\ + ((((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U)) /* ---------------------------------WAKEUPTIMER---------------------------------*/ /** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer @@ -581,8 +581,7 @@ typedef struct * @arg @ref RTC_FLAG_TSOVF * @retval None */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_TSF) ? (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSF)) : \ - (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSOVF))) +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__))) /** * @brief Enable interrupt on the RTC Timestamp associated Exti line. @@ -961,12 +960,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc); /** * @} */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard.h index 594db44c8c46256304177b2c000edb2be6aedd13..8727e2a56329f87ee2b833e7a8c89c90a17d9908 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard.h @@ -234,7 +234,7 @@ typedef struct __SMARTCARD_HandleTypeDef __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ - uint32_t ErrorCode; /*!< SmartCard Error code */ + __IO uint32_t ErrorCode; /*!< SmartCard Error code */ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */ @@ -557,15 +557,15 @@ typedef enum */ #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0U) #else #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ } while(0U) #endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -573,11 +573,11 @@ typedef enum * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ -#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ - } while(0U) +#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified SMARTCARD pending flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -726,7 +726,8 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -750,8 +751,8 @@ typedef enum * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -792,7 +793,8 @@ typedef enum * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ -#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable the USART associated to the SMARTCARD Handle. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -825,8 +827,8 @@ typedef enum do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ break; \ @@ -842,12 +844,12 @@ typedef enum default: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ break; \ @@ -863,14 +865,47 @@ typedef enum default: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else \ { \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#endif +#elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* STM32G081xx || STM32G071xx || STM32G070xx */ /** @brief Check the Baud rate range. * @note The maximum Baud Rate is derived from the maximum clock on G0 (64 MHz) @@ -931,7 +966,8 @@ typedef enum * @param __CPOL__ SMARTCARD frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ -#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) +#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\ + || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) /** @brief Ensure that SMARTCARD frame phase is valid. * @param __CPHA__ SMARTCARD frame phase. @@ -971,18 +1007,18 @@ typedef enum * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ -#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) +#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) /** @brief Ensure that SMARTCARD advanced features initialization is valid. * @param __INIT__ SMARTCARD advanced features initialization. @@ -1077,8 +1113,10 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** @@ -1090,8 +1128,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @{ */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard_ex.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard_ex.h index 70d4cc4b0646126a396bebbc74ac2ca5ca31f8d1..5ea3ee326bc48b20034e3858ce79dc14bc977187 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard_ex.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard_ex.h @@ -207,7 +207,7 @@ extern "C" { do { \ if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ { \ - (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ + (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ } \ else \ { \ @@ -238,29 +238,29 @@ extern "C" { * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ - ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) + ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) /** @brief Ensure that SMARTCARD TXFIFO threshold level is valid. * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) /** @brief Ensure that SMARTCARD RXFIFO threshold level is valid. * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) /** * @} diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h index 99dba1f0f0d38b1bb2eb08440f0362f78439db1d..271dec44a0f80eec2153b0f308095028879a32c7 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h @@ -673,7 +673,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to ((__CPHA__) == SPI_PHASE_2EDGE)) /** @brief Checks if SPI Slave Select parameter is in allowed range. - * @param __NSS__ specifies the SPI Slave Slelect management parameter. + * @param __NSS__ specifies the SPI Slave Select management parameter. * This parameter can be a value of @ref SPI_Slave_Select_management * @retval None */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h index 35fdb93491d01bba0b2d709ae05f5c9f6409768d..bad7fae96ac738aebb129239ba091713a867cb80 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -22,7 +22,7 @@ #define STM32G0xx_HAL_TIM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -90,7 +90,7 @@ typedef struct This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for timer instances supporting break feature. */ - uint32_t OCFastMode; /*!< Specifies the Fast mode state. + uint32_t OCFastMode; /*!< Specifies the Fast mode state. This parameter can be a value of @ref TIM_Output_Fast_State @note This parameter is valid only in PWM1 and PWM2 mode. */ @@ -145,8 +145,8 @@ typedef struct */ typedef struct { - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -202,8 +202,8 @@ typedef struct This parameter can be a value of @ref TIM_Clock_Polarity */ uint32_t ClockPrescaler; /*!< TIM clock prescaler This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClockConfigTypeDef; /** @@ -219,8 +219,8 @@ typedef struct This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; /** @@ -228,14 +228,19 @@ typedef struct * @note Advanced timers provide TRGO2 internal line which is redirected * to the ADC */ -typedef struct +typedef struct { uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ + This parameter can be a value of @ref TIM_Master_Mode_Selection */ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ } TIM_MasterConfigTypeDef; /** @@ -244,15 +249,15 @@ typedef struct typedef struct { uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ + This parameter can be a value of @ref TIM_Slave_Mode */ uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ + This parameter can be a value of @ref TIM_Trigger_Selection */ uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ + This parameter can be a value of @ref TIM_Trigger_Polarity */ uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ + This parameter can be a value of @ref TIM_Trigger_Prescaler */ uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_SlaveConfigTypeDef; @@ -263,32 +268,32 @@ typedef struct */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t BreakFilter; /*!< Specifies the break input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. - This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ - uint32_t Break2State; /*!< TIM Break2 State - This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ - uint32_t Break2Polarity; /*!< TIM Break2 input polarity - This parameter can be a value of @ref TIM_Break2_Polarity */ - uint32_t Break2Filter; /*!< TIM break2 input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. - This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t BreakFilter; /*!< Specifies the break input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. + This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + uint32_t Break2State; /*!< TIM Break2 State + This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + uint32_t Break2Polarity; /*!< TIM Break2 input polarity + This parameter can be a value of @ref TIM_Break2_Polarity */ + uint32_t Break2Filter; /*!< TIM break2 input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. + This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; /** @@ -314,7 +319,7 @@ typedef enum HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ } HAL_TIM_ActiveChannel; /** @@ -324,47 +329,47 @@ typedef enum typedef struct __TIM_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - void (* Base_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ - void (* Base_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ - void (* IC_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ - void (* IC_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ - void (* OC_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ - void (* OC_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ - void (* PWM_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ - void (* PWM_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ - void (* OnePulse_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ - void (* OnePulse_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ - void (* Encoder_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ - void (* Encoder_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ - void (* HallSensor_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ - void (* HallSensor_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ - void (* PeriodElapsedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ - void (* TriggerCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ - void (* IC_CaptureCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ - void (* OC_DelayElapsedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ - void (* PWM_PulseFinishedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ - void (* ErrorCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ - void (* CommutationCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ - void (* BreakCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -}TIM_HandleTypeDef; +} TIM_HandleTypeDef; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** @@ -401,12 +406,12 @@ typedef enum ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ -}HAL_TIM_CallbackIDTypeDef; +} HAL_TIM_CallbackIDTypeDef; /** * @brief HAL TIM Callback pointer definition */ -typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to the TIM callback function */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -462,6 +467,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to #define TIM_DMABASE_CCR6 0x00000017U #define TIM_DMABASE_AF1 0x00000018U #define TIM_DMABASE_AF2 0x00000019U +#define TIM_DMABASE_TISEL 0x0000001AU /** * @} */ @@ -674,9 +680,9 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to * @} */ -/** @defgroup TIM_Commutation_Source TIM Commutation Source +/** @defgroup TIM_Commutation_Source TIM Commutation Source * @{ - */ + */ #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ /** @@ -700,22 +706,22 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ -#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ -#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ -#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ -#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ -#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ -#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ -#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ -#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ -#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ -#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ /** * @} */ @@ -737,8 +743,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ -#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ @@ -981,7 +987,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ -#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ @@ -989,7 +995,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ -#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ /** * @} */ @@ -1082,7 +1088,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/15/16/17 */ #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */ -#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */ /** * @} */ @@ -1127,7 +1133,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to * @brief Enable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None - */ + */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** @@ -1143,15 +1149,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } \ - } while(0) + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) /** * @brief Disable the TIM main Output. @@ -1160,15 +1166,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ - } \ - } \ - } while(0) + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) /** * @brief Disable the TIM main Output. @@ -1253,8 +1259,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to * @arg TIM_FLAG_CC6: Compare 6 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag @@ -1277,8 +1283,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to * @arg TIM_FLAG_CC6: Compare 6 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag @@ -1303,7 +1309,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to * @arg TIM_IT_BREAK: Break interrupt * @retval The state of TIM_IT (SET or RESET). */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. * @param __HANDLE__ TIM handle @@ -1351,8 +1358,7 @@ mode. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ - ((__HANDLE__)->Instance->CNT) +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) /** * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. @@ -1361,18 +1367,17 @@ mode. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) /** * @brief Get the TIM Autoreload Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ - ((__HANDLE__)->Instance->ARR) +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. @@ -1385,11 +1390,11 @@ mode. * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) /** * @brief Get the TIM Clock Division value on runtime. @@ -1399,8 +1404,7 @@ mode. * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. @@ -1420,10 +1424,10 @@ mode. * @retval None */ #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) /** * @brief Get the TIM Input Capture prescaler on runtime. @@ -1461,12 +1465,12 @@ mode. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) /** * @brief Get the TIM Capture Compare Register value on runtime. @@ -1482,12 +1486,12 @@ mode. * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ - ((__HANDLE__)->Instance->CCR6)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) /** * @brief Set the TIM Output compare preload. @@ -1503,12 +1507,12 @@ mode. * @retval None */ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) /** * @brief Reset the TIM Output compare preload. @@ -1524,37 +1528,85 @@ mode. * @retval None */ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is set, only counter + * @note When the URS bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) * @retval None */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if * enabled): * _ Counter overflow underflow * _ Setting the UG bit * _ Update generation through the slave mode controller * @retval None */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) /** * @brief Set the TIM Capture x input polarity on runtime. @@ -1565,18 +1617,18 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__ Polarity for TIx source + * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge * @retval None */ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) - + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + /** * @} */ @@ -1627,12 +1679,13 @@ mode. ((__BASE__) == TIM_DMABASE_CCR3) || \ ((__BASE__) == TIM_DMABASE_CCR4) || \ ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR1) || \ ((__BASE__) == TIM_DMABASE_CCMR3) || \ ((__BASE__) == TIM_DMABASE_CCR5) || \ ((__BASE__) == TIM_DMABASE_CCR6) || \ - ((__BASE__) == TIM_DMABASE_OR1) || \ ((__BASE__) == TIM_DMABASE_AF1) || \ - ((__BASE__) == TIM_DMABASE_AF2)) + ((__BASE__) == TIM_DMABASE_AF2) || \ + ((__BASE__) == TIM_DMABASE_TISEL)) #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) @@ -1882,13 +1935,13 @@ mode. #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) #if defined(PWR_PVD_SUPPORT) -#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) #else -#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) #endif /* PWR_PVD_SUPPORT */ @@ -1896,28 +1949,28 @@ mode. ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) /** * @} @@ -1932,10 +1985,10 @@ mode. * @{ */ -/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions * @brief Time Base functions - * @{ - */ + * @{ + */ /* Time Base functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); @@ -1954,10 +2007,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); * @} */ -/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * @{ - */ +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ /* Timer Output Compare functions *********************************************/ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); @@ -1976,10 +2029,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * @{ - */ +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ /* Timer PWM functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); @@ -1998,10 +2051,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @} */ -/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * @{ - */ +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ /* Timer Input Capture functions **********************************************/ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); @@ -2020,10 +2073,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * @{ - */ +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ /* Timer One Pulse functions **************************************************/ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); @@ -2039,12 +2092,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @} */ -/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * @{ - */ +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ /* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); @@ -2055,7 +2108,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2071,25 +2125,27 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); * @} */ -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions * @{ */ /* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -2098,7 +2154,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions + * @brief TIM Callbacks functions * @{ */ /* Callback in non blocking modes (Interrupt and DMA) *************************/ @@ -2115,7 +2171,8 @@ void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -2123,10 +2180,10 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @} */ -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * @{ - */ +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ /* Peripheral State functions ************************************************/ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); @@ -2145,12 +2202,12 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); /* Private functions----------------------------------------------------------*/ /** @defgroup TIM_Private_Functions TIM Private Functions -* @{ -*/ + * @{ + */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); @@ -2158,15 +2215,15 @@ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** -* @} -*/ + * @} + */ /* End of private functions --------------------------------------------------*/ /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h index b187972a6d139eb268a66d41d7592dc49c7b1019..f99c2eef70b82a87338a9a941eb0e5e1c57224bc 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h @@ -6,23 +6,23 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G0xx_HAL_TIM_EX_H #define STM32G0xx_HAL_TIM_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -34,34 +34,34 @@ /** @addtogroup TIMEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types * @{ */ -/** - * @brief TIM Hall sensor Configuration Structure definition +/** + * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - + uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; -/** - * @brief TIM Break/Break2 input configuration +/** + * @brief TIM Break/Break2 input configuration */ typedef struct { @@ -77,14 +77,14 @@ TIMEx_BreakInputConfigTypeDef; /** * @} */ -/* End of exported types -----------------------------------------------------*/ +/* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants * @{ */ -/** @defgroup TIMEx_Remap TIM Extended Remapping +/** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ #define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ @@ -110,18 +110,18 @@ TIMEx_BreakInputConfigTypeDef; #endif /* TIM3 */ /** * @} - */ + */ -/** @defgroup TIMEx_Break_Input TIM Extended Break input +/** @defgroup TIMEx_Break_Input TIM Extended Break input * @{ */ #define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ #define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ /** * @} - */ + */ -/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source * @{ */ #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ @@ -140,18 +140,18 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ /** * @} - */ + */ -/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity * @{ */ #define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ /** * @} - */ - -/** @defgroup TIMEx_Timer_Input_Selection TIM Timer input selection + */ + +/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection * @{ */ #define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */ @@ -159,7 +159,7 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM1_TI1_COMP1 0x00000001U /* !< TIM1_TI1 is connected to COMP1 OUT */ #endif /* COMP1 */ -#define TIM_TIM1_TI2_GPIO 0x00000000U /* !< TIM1_TI2 is connected to GPIO */ + #define TIM_TIM1_TI2_GPIO 0x00000000U /* !< TIM1_TI2 is connected to GPIO */ #if defined(COMP2) #define TIM_TIM1_TI2_COMP2 0x00000100U /* !< TIM1_TI2 is connected to COMP2 OUT */ #endif /* COMP2 */ @@ -211,24 +211,24 @@ TIMEx_BreakInputConfigTypeDef; /** * @} - */ + */ /* End of exported constants -------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros * @{ - */ + */ /** * @} - */ + */ /* End of exported macro -----------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros * @{ - */ -#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) + */ +#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) @@ -247,11 +247,11 @@ TIMEx_BreakInputConfigTypeDef; #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) -#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) +#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) /** * @} - */ + */ /* End of private macro ------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -260,17 +260,17 @@ TIMEx_BreakInputConfigTypeDef; */ /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * @{ - */ + * @brief Timer Hall Sensor functions + * @{ + */ /* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); - /* Blocking mode: Polling */ +/* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ @@ -284,9 +284,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); */ /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * @{ - */ + * @brief Timer Complementary Output Compare functions + * @{ + */ /* Timer Complementary Output Compare functions *****************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -304,9 +304,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann */ /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * @{ - */ + * @brief Timer Complementary PWM functions + * @{ + */ /* Timer Complementary PWM functions ****************************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -323,9 +323,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * @{ - */ + * @brief Timer Complementary One Pulse functions + * @{ + */ /* Timer Complementary One Pulse functions **********************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); @@ -339,19 +339,25 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t */ /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ + * @brief Peripheral Control functions + * @{ + */ /* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); -HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection , uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); @@ -384,28 +390,28 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); /** * @} - */ + */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions -* @{ -*/ +/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); /** -* @} -*/ + * @} + */ /* End of private functions --------------------------------------------------*/ /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h index d866e380b89312e3e01c86f1839caf89011cb806..94d136db56c0bef832201d88cfe5b695b7e9b7a3 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h @@ -806,9 +806,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0U) + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified UART pending flag. * @param __HANDLE__ specifies the UART Handle. @@ -973,7 +973,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) /** @brief Check whether the specified UART interrupt source is enabled or not. * @param __HANDLE__ specifies the UART Handle. @@ -998,8 +999,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. @@ -1161,7 +1162,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U) + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\ + + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1169,7 +1171,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U) + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1177,7 +1180,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__))) + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Check whether or not UART instance is Low Power UART. * @param __HANDLE__ specifies the UART Handle. @@ -1238,10 +1242,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ - (((__CONTROL__) == UART_HWCONTROL_NONE) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS) || \ - ((__CONTROL__) == UART_HWCONTROL_CTS) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) /** * @brief Ensure that UART communication mode is valid. @@ -1509,7 +1513,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -1589,10 +1594,13 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); /** @addtogroup UART_Private_Functions UART Private Functions * @{ */ - +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h index 7d80b6c052374b2c6f4c557705d490ab3e32ae63..f28e7e6218361e68f4f13178e175c8cd6388961c 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h @@ -138,7 +138,8 @@ typedef struct */ /* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); /** * @} @@ -194,8 +195,8 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -211,12 +212,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -232,20 +233,20 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ } \ else if((__HANDLE__)->Instance == USART4) \ { \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ } \ else if((__HANDLE__)->Instance == LPUART1) \ { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ case RCC_LPUART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -261,7 +262,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else \ { \ @@ -278,8 +279,8 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -295,12 +296,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -316,15 +317,112 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ } \ else if((__HANDLE__)->Instance == USART4) \ { \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(STM32G041xx) || defined(STM32G031xx) +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(STM32G030xx) +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ } \ else \ { \ @@ -344,44 +442,44 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 */ #define UART_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ -} while(0U) + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** * @brief Ensure that UART frame length is valid. diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h index c63dc5924a95d32f7081db434ad595b233c9c27f..2bb787c77c1ee0fcfbe798df7c8cbabc655df442 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h @@ -434,10 +434,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_USART_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) + (__HANDLE__)->State = HAL_USART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) #else #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -591,7 +591,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -614,8 +615,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. @@ -702,7 +703,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__)) +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Report the USART clock source. * @param __HANDLE__ specifies the USART Handle. @@ -714,8 +716,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ break; \ @@ -731,12 +733,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin default: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ break; \ @@ -752,7 +754,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin default: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ @@ -767,7 +769,40 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#endif +#elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* STM32G081xx || STM32G071xx || STM32G070xx */ /** @brief Check USART Baud rate. * @param __BAUDRATE__ Baudrate specified by the user. @@ -890,7 +925,8 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -905,13 +941,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart_ex.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart_ex.h index 7acbe23902949be36184a7e893b9b8ce63115288..7f719d35cec14e783a738f9b85c3bd85f45cadf1 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart_ex.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart_ex.h @@ -130,44 +130,44 @@ extern "C" { */ #define USART_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ + if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x01FFU; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x00FFU; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x00FFU; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x007FU; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x007FU; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x003FU; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ -} while(0U) + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h index 9b5b61d1924ab74eab6f4b357c63f48e1586912f..9b7fef6bb015ab90ef6c4dfd9c78be916f4cf71a 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h @@ -64,7 +64,11 @@ typedef struct /** * @brief WWDG handle Structure definition */ +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) typedef struct __WWDG_HandleTypeDef +#else +typedef struct +#endif { WWDG_TypeDef *Instance; /*!< Register base address */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h index 1c43bfddde9b8939a61efdeb09b77111254ae598..859d7785324f02edfe4c944fe6a73317554c5ced 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h @@ -271,7 +271,7 @@ extern "C" { * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) /** * @} @@ -371,7 +371,7 @@ typedef struct */ typedef struct { - uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). @@ -471,17 +471,17 @@ typedef struct * @{ */ #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */ -#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ /** * @} */ @@ -612,19 +612,19 @@ typedef struct * @{ */ #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #if defined(TIM2) -#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #endif -#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #if defined(TIM6) -#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #endif #if defined(TIM15) -#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #endif -#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -670,8 +670,8 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility * @{ */ -#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */ -#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */ +#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */ +#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */ /** * @} */ @@ -841,14 +841,14 @@ typedef struct /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays - * @note Only ADC IP HW delays are defined in ADC LL driver driver, + * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, * not timeout values. * For details on delays values, refer to descriptions in source code * above each literal definition. * @{ */ -/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ +/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ /* not timeout values. */ /* Timeout values for ADC operations are dependent to device clock */ /* configuration (system clock versus ADC clock), */ @@ -1695,7 +1695,7 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) * - * (1) ADC common clock asynchonous prescaler is applied to + * (1) ADC common clock asynchronous prescaler is applied to * each ADC instance if the corresponding ADC instance clock * is set to clock source asynchronous. * (refer to function @ref LL_ADC_SetClock() ). @@ -1725,7 +1725,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) * - * (1) ADC common clock asynchonous prescaler is applied to + * (1) ADC common clock asynchronous prescaler is applied to * each ADC instance if the corresponding ADC instance clock * is set to clock source asynchronous. * (refer to function @ref LL_ADC_SetClock() ). @@ -1736,9 +1736,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) } /** - * @brief Set parameter common to several ADC: Clock low frequency mode. - * Refer to reference manual for alignments formats - * dependencies to ADC resolutions. + * @brief Legacy feature, useless on STM32G0 (ADC common clock low frequency + mode is automatically managed by ADC peripheral on STM32G0). + Function kept for legacy purpose. * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going @@ -1746,20 +1746,20 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) * @rmtoll CCR LFMEN LL_ADC_SetCommonFrequencyMode * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param Resolution This parameter can be one of the following values: + * @param CommonFrequencyMode This parameter can be one of the following values: * @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH * @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW * @retval None */ -__STATIC_INLINE void LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Resolution) +__STATIC_INLINE void LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonFrequencyMode) { - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_LFMEN, Resolution); + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_LFMEN, CommonFrequencyMode); } /** - * @brief Get parameter common to several ADC: Clock low frequency mode. - * Refer to reference manual for alignments formats - * dependencies to ADC resolutions. + * @brief Legacy feature, useless on STM32G0 (ADC common clock low frequency + mode is automatically managed by ADC peripheral on STM32G0). + Function kept for legacy purpose. * @rmtoll CCR LFMEN LL_ADC_GetCommonFrequencyMode * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -2245,7 +2245,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, /** * @brief Set ADC group regular conversion trigger source: - * internal (SW start) or from external IP (timer event, + * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note On this STM32 serie, setting trigger source to external trigger * also set trigger polarity to rising edge @@ -2286,7 +2286,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri /** * @brief Get ADC group regular conversion trigger source: - * internal (SW start) or from external IP (timer event, + * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note To determine whether group regular trigger source is * internal (SW start) or external, without detail @@ -2313,7 +2313,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { - register uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); + register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ @@ -2563,7 +2563,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) { - register uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); + register __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); register uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; register uint32_t RankIndex; @@ -3150,7 +3150,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Ch */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) { - register uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); + register uint32_t ChannelsBitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) @@ -3175,6 +3175,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) #endif ); } + /** * @brief Set ADC continuous conversion mode on ADC group regular. * @note Description of ADC continuous conversion mode: @@ -3480,7 +3481,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { - register uint32_t smpr = READ_REG(ADCx->SMPR); + register __IO uint32_t smpr = READ_REG(ADCx->SMPR); /* Retrieve sampling time bit corresponding to the selected channel */ /* and shift it to position 0. */ @@ -3576,7 +3577,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ - register uint32_t *preg; + register __IO uint32_t *preg; if(AWDy == LL_ADC_AWD1) { @@ -3672,8 +3673,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); @@ -3794,7 +3795,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, @@ -3871,7 +3872,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); MODIFY_REG(*preg, AWDThresholdsHighLow, @@ -3913,7 +3914,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_bus.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_bus.h index bafded27f8be58192e71e042fcec3e4c6a5f75cc..56ae9e49426f600e9d4c0f6033a0bf43e834a174 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_bus.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_bus.h @@ -216,7 +216,7 @@ extern "C" { * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @note (*) RNG & CRYP IP available only on STM32G081xx + * @note (*) RNG & CRYP Peripherals available only on STM32G081xx * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) @@ -241,7 +241,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @note (*) RNG & CRYP IP available only on STM32G081xx + * @note (*) RNG & CRYP Peripherals available only on STM32G081xx * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) @@ -262,7 +262,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @note (*) RNG & CRYP IP available only on STM32G081xx + * @note (*) RNG & CRYP Peripherals available only on STM32G081xx * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) @@ -284,7 +284,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @note (*) RNG & CRYP IP available only on STM32G081xx + * @note (*) RNG & CRYP Peripherals available only on STM32G081xx * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) @@ -306,7 +306,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @note (*) RNG & CRYP IP available only on STM32G081xx + * @note (*) RNG & CRYP Peripherals available only on STM32G081xx * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) @@ -329,7 +329,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @note (*) RNG & CRYP IP available only on STM32G081xx + * @note (*) RNG & CRYP Peripherals available only on STM32G081xx * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) @@ -356,7 +356,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @note (*) RNG & CRYP IP available only on STM32G081xx + * @note (*) RNG & CRYP Peripherals available only on STM32G081xx * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h index 343a67f76301206fa961d22fff5a359fb4643fd2..191b16d70a74ec54eee1d0a57647fe832fe1c63a 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h @@ -81,7 +81,7 @@ extern "C" { * @retval Pointer to register address */ #define __COMP_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) /** * @} @@ -100,32 +100,32 @@ typedef struct { uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed. This parameter can be a value of @ref COMP_LL_EC_POWERMODE - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */ uint32_t InputMinus; /*!< Set comparator input minus (inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus. This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */ uint32_t OutputPolarity; /*!< Set comparator output polarity. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */ uint32_t OutputBlankingSource; /*!< Set comparator blanking source. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */ } LL_COMP_InitTypeDef; @@ -240,7 +240,7 @@ typedef struct */ /** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays - * @note Only COMP IP HW delays are defined in COMP LL driver driver, + * @note Only COMP peripheral HW delays are defined in COMP LL driver driver, * not timeout values. * For details on delays values, refer to descriptions in source code * above each literal definition. @@ -347,14 +347,14 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM { /* Note: On this STM32 serie, window mode can be set from one of the pair */ /* of COMP instances: COMP1 or COMP2. */ - register uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); - + register __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); + /* Clear the potential previous setting of window mode */ - register uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (~(WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL)); + register __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (~(WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL)); CLEAR_BIT(*preg_clear, COMP_CSR_WINMODE ); - + /* Set window mode */ MODIFY_REG(*preg, COMP_CSR_WINMODE, @@ -377,10 +377,10 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy { /* Note: On this STM32 serie, window mode can be set from one of the pair */ /* of COMP instances: COMP1 or COMP2. */ - register uint32_t window_mode_comp_odd = READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE); - register uint32_t window_mode_comp_even = READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE); - - return (uint32_t)( window_mode_comp_odd + register const uint32_t window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE); + register const uint32_t window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + + return (uint32_t)(window_mode_comp_odd | window_mode_comp_even | ((window_mode_comp_even >> LL_COMP_WINDOWMODE_BITOFFSET_POS) * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)); } @@ -400,16 +400,16 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy */ __STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput) { - register uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); - + register __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); + /* Clear the potential previous setting of window output on the relevant comparator instance */ /* (clear bit of window output unless specific case of setting of comparator both output selected) */ - register uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (~(WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL)); + register __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (~(WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL)); MODIFY_REG(*preg_clear, COMP_CSR_WINOUT, ((WindowOutput & LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) >> LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW) ); - + /* Set window output */ MODIFY_REG(*preg, COMP_CSR_WINOUT, @@ -431,11 +431,11 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_C */ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON) { - register uint32_t window_output_comp_odd = READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT); - register uint32_t window_output_comp_even = READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT); - + register const uint32_t window_output_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT); + register const uint32_t window_output_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT); + /* Construct value corresponding to LL_COMP_WINDOWOUTPUT_xxx */ - return (uint32_t)( window_output_comp_odd + return (uint32_t)(window_output_comp_odd | window_output_comp_even | ((window_output_comp_even >> COMP_CSR_WINOUT_Pos) * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) | (window_output_comp_odd + window_output_comp_even)); @@ -493,10 +493,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) * when COMP input is based on VrefInt (VrefInt or subdivision * of VrefInt): * Voltage scaler requires a delay for voltage stabilization. - * Refer to device datasheet, parameter "xxxx". -*/ -//#warning "Specify parameter name in STM32G0 datasheet" -/* + * Refer to device datasheet, parameter "tSTART_SCALER". * @rmtoll CSR INMSEL LL_COMP_ConfigInputs\n * CSR INPSEL LL_COMP_ConfigInputs\n * @param COMPx Comparator instance @@ -567,10 +564,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) * when COMP input is based on VrefInt (VrefInt or subdivision * of VrefInt): * Voltage scaler requires a delay for voltage stabilization. - * Refer to device datasheet, parameter "xxxx". -*/ -//#warning "Specify parameter name in STM32G0 datasheet" -/* + * Refer to device datasheet, parameter "tSTART_SCALER". * @rmtoll CSR INMSEL LL_COMP_SetInputMinus * @param COMPx Comparator instance * @param InputMinus This parameter can be one of the following values: @@ -694,7 +688,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3 (1) * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3 (1) * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2 (1) - * + * * (1) Parameter availability depending on timer availability * on the selected device. * @retval None @@ -719,7 +713,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3 (1) * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3 (1) * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2 (1) - * + * * (1) Parameter availability depending on timer availability * on the selected device. */ @@ -740,9 +734,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) * @brief Enable comparator instance. * @note After enable from off state, comparator requires a delay * to reach reach propagation delay specification. -*/ -//#warning "Specify startup time naming in datasheet for the selected IP" -/* + * Refer to device datasheet, parameter "tSTART". * @rmtoll CSR EN LL_COMP_Enable * @param COMPx Comparator instance * @retval None diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crc.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crc.h index 05b0f87e696a1c7b83a9308130833a468a0417b2..ddb5116241464ace8a059ac52bd4b73b88d03e9d 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crc.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crc.h @@ -338,7 +338,7 @@ __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) { __IO uint16_t *pReg; - pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); + pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = InData; } diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dac.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dac.h index 3a4ef281b06c7c72a95119b229da9b6a69aa880d..b28eac4e5caaf8a2c16f083e65b4518cc31ad185 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dac.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dac.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -53,7 +53,6 @@ extern "C" { /* - channel register offset of data holding register DHRx */ /* - channel register offset of data output register DORx */ /* - channel register offset of sample-and-hold sample time register SHSRx */ - #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) @@ -76,11 +75,11 @@ extern "C" { #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ #define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) - #define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */ #define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */ #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) + #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */ #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */ @@ -118,7 +117,7 @@ extern "C" { * @retval Pointer to register address */ #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) /** * @} @@ -136,7 +135,7 @@ extern "C" { */ typedef struct { - uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ @@ -159,6 +158,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ + uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION @@ -168,7 +168,6 @@ typedef struct This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */ - } LL_DAC_InitTypeDef; /** @@ -230,15 +229,15 @@ typedef struct * @{ */ #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */ -#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ -#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 TRGO. */ -#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 TRGO. */ -#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM3 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ /** * @} */ @@ -341,7 +340,7 @@ typedef struct */ /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays - * @note Only DAC IP HW delays are defined in DAC LL driver driver, + * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, * not timeout values. * For details on delays values, refer to descriptions in source code * above each literal definition. @@ -362,7 +361,6 @@ typedef struct /* Unit: us */ #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ - /* Delay for DAC channel voltage settling time. */ /* Note: DAC channel startup time depends on board application environment: */ /* impedance connected to DAC channel output. */ @@ -459,7 +457,7 @@ typedef struct ) \ : \ ( \ - 0 \ + 0U \ ) \ ) \ ) @@ -803,7 +801,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 * @retval None */ -__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) +__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, + uint32_t TriangleAmplitude) { MODIFY_REG(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), @@ -884,7 +883,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL * @retval None */ -__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection) +__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, + uint32_t OutputBuffer, uint32_t OutputConnection) { MODIFY_REG(DACx->MCR, (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), @@ -1057,7 +1057,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, @@ -1077,7 +1077,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32 */ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); } @@ -1253,7 +1253,8 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ - return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); + return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, + ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); } /** * @} @@ -1416,7 +1417,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha */ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, @@ -1438,7 +1439,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ */ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, @@ -1460,7 +1461,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, @@ -1479,7 +1480,8 @@ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, + uint32_t DataChannel2) { MODIFY_REG(DACx->DHR12RD, (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), @@ -1497,7 +1499,8 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uin * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, + uint32_t DataChannel2) { /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ @@ -1518,7 +1521,8 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF * @retval None */ -__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, + uint32_t DataChannel2) { MODIFY_REG(DACx->DHR8RD, (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), @@ -1542,7 +1546,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint */ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); } diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h index 5c8cb9afcebdc1ab95c9bf2cc459445a7c3c9f6c..150ef7ebcb408571311b3a07920a66f5e59bf91a 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h @@ -454,7 +454,8 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel-1U]))->CCR, DMA_CCR_EN); } /** @@ -473,7 +474,8 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel-1U]))->CCR, DMA_CCR_EN); } /** @@ -492,8 +494,9 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } /** @@ -527,7 +530,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); } @@ -553,7 +557,8 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); } @@ -577,7 +582,8 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); } @@ -602,7 +608,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_CIRC, Mode); } @@ -624,7 +631,8 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_CIRC)); } @@ -647,7 +655,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PINC, PeriphOrM2MSrcIncMode); } @@ -669,7 +678,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PINC)); } @@ -692,7 +702,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MINC, MemoryOrM2MDstIncMode); } @@ -714,7 +725,8 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MINC)); } @@ -738,7 +750,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize); } @@ -761,7 +774,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PSIZE)); } @@ -785,7 +799,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MSIZE, MemoryOrM2MDstDataSize); } @@ -808,7 +823,8 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MSIZE)); } @@ -833,7 +849,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PL, Priority); } @@ -857,7 +874,8 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PL)); } @@ -880,7 +898,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CNDTR, DMA_CNDTR_NDT, NbData); } @@ -902,14 +921,15 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CNDTR, DMA_CNDTR_NDT)); } /** * @brief Configure the Source and Destination addresses. * @note This API must not be called when the DMA channel is enabled. - * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). + * @note Each peripheral using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n * CMAR MA LL_DMA_ConfigAddresses * @param DMAx DMAx Instance @@ -932,17 +952,18 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { + uint32_t dma_base_addr = (uint32_t)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, DstAddress); } /* Direction Periph to Memory and Memory to Memory */ else { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, DstAddress); } } @@ -965,7 +986,8 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, MemoryAddress); } /** @@ -987,7 +1009,8 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, PeriphAddress); } /** @@ -1007,7 +1030,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR)); } /** @@ -1027,7 +1051,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR)); } /** @@ -1049,7 +1074,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, MemoryAddress); } /** @@ -1071,7 +1097,8 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, MemoryAddress); } /** @@ -1091,7 +1118,8 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR)); } /** @@ -1111,7 +1139,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR)); } /** @@ -1194,6 +1223,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { + (void)(DMAx); MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Channel - 1UL))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); } @@ -1276,6 +1306,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)(DMAx); return (READ_BIT(((DMAMUX_Channel_TypeDef *)(((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Channel - 1UL)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1926,7 +1957,8 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TCIE); } /** @@ -1945,7 +1977,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_HTIE); } /** @@ -1964,7 +1997,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE); } /** @@ -1983,7 +2017,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TCIE); } /** @@ -2002,7 +2037,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_HTIE); } /** @@ -2021,7 +2057,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE); } /** @@ -2040,7 +2077,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } @@ -2060,7 +2098,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } @@ -2080,7 +2119,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h index c54c341bcc1129a1a8b75e600d4e010df8abf86d..2464678d3b0a113fedb4ef28c11d511a33e8dcc5 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h @@ -449,7 +449,8 @@ extern "C" { */ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); } /** @@ -531,7 +532,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); } /** @@ -551,7 +553,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); } /** @@ -570,7 +573,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); + (void)(DMAMUXx); + return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); } /** @@ -594,7 +598,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) { - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SPOL, Polarity); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); } /** @@ -617,7 +622,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SPOL)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); } /** @@ -636,7 +642,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU */ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE); + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); } /** @@ -655,7 +662,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE); + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); } /** @@ -674,7 +682,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return ((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL); + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL); } /** @@ -693,7 +702,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD */ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE); + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); } /** @@ -712,7 +722,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 */ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE); + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); } /** @@ -731,7 +742,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return ((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL); + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL); } /** @@ -774,7 +786,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx */ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) { - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); } /** @@ -816,7 +829,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID)); } /** @@ -832,7 +846,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui */ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + (void)(DMAMUXx); + SET_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -848,7 +863,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + (void)(DMAMUXx); + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -864,6 +880,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { + (void)(DMAMUXx); return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL); } @@ -885,7 +902,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *D */ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) { - MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); } /** @@ -905,7 +923,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); } /** @@ -923,6 +942,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef */ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) { + (void)(DMAMUXx); MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); } @@ -939,6 +959,7 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { + (void)(DMAMUXx); return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); } @@ -979,7 +1000,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMU */ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) { - MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); } /** @@ -1018,7 +1040,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUX */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); } /** @@ -1037,6 +1060,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); } @@ -1048,6 +1072,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);; } @@ -1059,6 +1084,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);; } @@ -1070,6 +1096,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);; } @@ -1081,6 +1108,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);; } @@ -1093,6 +1121,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);; } #endif @@ -1105,6 +1134,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); } #endif @@ -1117,6 +1147,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);; } @@ -1128,6 +1159,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);; } @@ -1139,6 +1171,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);; } @@ -1150,6 +1183,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);; } @@ -1161,6 +1195,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); } @@ -1172,6 +1207,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); } @@ -1183,6 +1219,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); } @@ -1194,6 +1231,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); } @@ -1205,6 +1243,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); } @@ -1217,6 +1256,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); } #endif @@ -1229,6 +1269,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); } #endif @@ -1241,6 +1282,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); } @@ -1252,6 +1294,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); } @@ -1263,6 +1306,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); } @@ -1274,6 +1318,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); } @@ -1301,7 +1346,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); } /** @@ -1320,7 +1366,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint */ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); } /** @@ -1339,7 +1386,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL); + (void)(DMAMUXx); + return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL); } /** @@ -1355,7 +1403,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUX */ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE); + (void)(DMAMUXx); + SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); } /** @@ -1371,7 +1420,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE); + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); } /** @@ -1387,7 +1437,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))? 1UL : 0UL); + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))? 1UL : 0UL); } /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_gpio.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_gpio.h index f6e4f0a4002029472816f1e1c464655b14455bba..10496dc275ed00e1852c5f57cace070006287800 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_gpio.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_gpio.h @@ -32,7 +32,7 @@ extern "C" { * @{ */ -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOF) +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) /** @defgroup GPIO_LL GPIO * @{ @@ -681,6 +681,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); WRITE_REG(GPIOx->LCKR, PinMask); WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ temp = READ_REG(GPIOx->LCKR); (void) temp; } @@ -938,7 +939,7 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); * @} */ -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOF) */ +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ /** * @} */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_iwdg.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_iwdg.h index b7eaa6b121f371567cfc0e3edb7b0e2f6d2cb8df..a4757d2f7d7f692bb4c9e0930a54d14c34647d26 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_iwdg.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_iwdg.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -327,7 +327,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) * @} */ -#endif /* IWDG) */ +#endif /* IWDG */ /** * @} diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lptim.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lptim.h index 07eddba948aac360107361b8dbeb4e8d582ab40f..7ec8d868dd50e18768cc4a106d5701b1166ea679 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lptim.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lptim.h @@ -301,7 +301,7 @@ typedef struct * @param __VALUE__ Value to be written in the register * @retval None */ -#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->(__REG__), (__VALUE__)) +#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) /** * @brief Read a value in LPTIM register @@ -309,7 +309,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__)) +#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) /** * @} */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h index e0f144f9743d82ea377f58efc814ea19b0bd25a5..a4283ffd074ce74f4f552b11b0925e818f3cdac6 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h @@ -442,7 +442,8 @@ typedef struct * @param __BAUDRATE__ Baud Rate value to achieve * @retval LPUARTDIV value to be used for BRR register filling */ -#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\ + + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) /** * @} @@ -1341,7 +1342,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) * @param BaudRate Baud Rate * @retval None */ -__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate) +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t BaudRate) { LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); } @@ -1380,6 +1382,10 @@ __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t { brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); } + else + { + brrresult = 0x0UL; + } return (brrresult); } @@ -2481,12 +2487,12 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t) & (LPUARTx->TDR); + data_reg_addr = (uint32_t) &(LPUARTx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t) & (LPUARTx->RDR); + data_reg_addr = (uint32_t) &(LPUARTx->RDR); } return data_reg_addr; @@ -2508,7 +2514,7 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32 */ __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) { - return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); + return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); } /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h index c1c5cc23806569d4bdd52068bf1a9985eea6b165..8290c34f6ec24d418b38bdd377e12310b479727a 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h @@ -99,8 +99,8 @@ extern "C" { /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR * @{ */ -#define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_0) -#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_1) +#define LL_PWR_MODE_STOP0 (0x00000000UL) +#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0) #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1|PWR_CR1_LPMS_0) #if defined (PWR_CR1_LPMS_2) #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2) @@ -164,6 +164,9 @@ extern "C" { #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB))) #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC))) #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD))) +#if defined(GPIOE) +#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE))) +#endif #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF))) /** * @} @@ -896,7 +899,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) */ __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { - SET_BIT(*((uint32_t *)GPIO), GPIONumber); + SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber); } /** @@ -933,7 +936,7 @@ __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) */ __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { - CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber); + CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber); } /** @@ -970,7 +973,7 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { - return ((READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); + return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); } /** @@ -1007,8 +1010,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIO */ __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp = (uint32_t)(GPIO) + 4U; - SET_BIT(*((uint32_t *)(temp)), GPIONumber); + SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); } /** @@ -1045,8 +1047,7 @@ __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe */ __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp = (uint32_t)(GPIO) + 4U; - CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber); + CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); } /** @@ -1083,8 +1084,7 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp = (uint32_t)(GPIO) + 4UL; - return ((READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); + return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); } /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h index 90839b58ea2cd09ceb79842821b378e99181a0da..20377e6645adc7e563be020fc68036d50f774271 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h @@ -116,7 +116,7 @@ typedef struct #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ #if !defined (EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#define EXTERNAL_CLOCK_VALUE 48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */ #endif /* EXTERNAL_CLOCK_VALUE */ /** * @} @@ -2442,7 +2442,7 @@ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void) /** * @brief Disable PLL output mapped on ADC domain clock * @note Cannot be disabled if the PLL clock is used as the system clock - * @note User shall check that PLL is not used by any other IP + * @note User shall check that PLL is not used by any other peripheral * (ex: I2S1) * @note In order to save power, when the PLLCLK of the PLL is * not used, should be 0 @@ -2469,7 +2469,7 @@ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S1(void) /** * @brief Disable PLL output mapped on I2S1 domain clock * @note Cannot be disabled if the PLL clock is used as the system clock - * @note User shall check that PLL is not used by any other IP + * @note User shall check that PLL is not used by any other peripheral * (ex: RNG) * @note In order to save power, when the PLLCLK of the PLL is * not used, should be 0 @@ -2497,7 +2497,7 @@ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_RNG(void) /** * @brief Disable PLL output mapped on RNG domain clock * @note Cannot be disabled if the PLL clock is used as the system clock - * @note User shall check that PLL is not used by any other IP + * @note User shall check that PLL is not used by any other peripheral * (ex: TIM, TIM15) * @note In order to save power, when the PLLCLK of the PLL is * not used, should be 0 @@ -2526,7 +2526,7 @@ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM1(void) /** * @brief Disable PLL output mapped on TIM1 domain clock * @note Cannot be disabled if the PLL clock is used as the system clock - * @note User shall check that PLL is not used by any other IP + * @note User shall check that PLL is not used by any other peripheral * (ex: RNG, TIM15) * @note In order to save power, when the PLLCLK of the PLL is * not used, should be 0 @@ -2555,7 +2555,7 @@ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM15(void) /** * @brief Disable PLL output mapped on TIM15 domain clock * @note Cannot be disabled if the PLL clock is used as the system clock - * @note User shall check that PLL is not used by any other IP + * @note User shall check that PLL is not used by any other peripheral * (ex: RNG, TIM1) * @note In order to save power, when the PLLCLK of the PLL is * not used, should be 0 diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h index 482a740b1e2b4ddddb160dcfef75e8b6dfee2c5b..7270bf80bb9f62e40b2c59c1c46cc172e9247128 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -32,7 +32,7 @@ extern "C" { * @{ */ -#if defined(RNG) +#if defined (RNG) /** @defgroup RNG_LL RNG * @{ @@ -49,6 +49,7 @@ extern "C" { * @{ */ + /** * @brief LL RNG Init Structure Definition */ @@ -64,7 +65,6 @@ typedef struct * @} */ #endif /* USE_FULL_LL_DRIVER */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants * @{ @@ -386,7 +386,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); * @} */ -#endif /* defined(RNG) */ +#endif /* RNG */ /** * @} @@ -396,6 +396,6 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); } #endif -#endif /* STM32G0xx_LL_RNG_H */ +#endif /* __STM32G0xx_LL_RNG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h index 06c382a42814a2eff77839794e9e639af0af4da9..d220592e906709ea1c8a9b78e85ee574941e778a 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -240,7 +240,7 @@ typedef struct #define LL_RTC_SCR_TSF RTC_SCR_CTSF #define LL_RTC_SCR_WUTF RTC_SCR_CWUTF #define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF -#define LL_RTC_CSR_ALRAF RTC_SCR_CALRAF +#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF #define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF #define LL_RTC_ICSR_INITF RTC_ICSR_INITF @@ -322,8 +322,8 @@ typedef struct /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE * @{ */ -#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM is open-drain output */ -#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is push-pull output */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U /*!< RTC_ALARM is push-pull output */ /** * @} */ @@ -2412,7 +2412,7 @@ __STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx) * @brief Set Time-stamp event active edge * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting - * @rmtoll RTC_CR ITSEDGE LL_RTC_TS_SetActiveEdge + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge * @param RTCx RTC Instance * @param Edge This parameter can be one of the following values: * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING @@ -2427,7 +2427,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) /** * @brief Get Time-stamp event active edge * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll RTC_CR ITSEDGE LL_RTC_TS_GetActiveEdge + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING @@ -2468,7 +2468,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) * @brief Get Timestamp Minutes in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format * @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute\n - * RTC_TSTR HU LL_RTC_TS_GetMinute + * RTC_TSTR MNU LL_RTC_TS_GetMinute * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -2481,7 +2481,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) * @brief Get Timestamp Seconds in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format * @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond\n - * RTC_TSTR HU LL_RTC_TS_GetSecond + * RTC_TSTR SU LL_RTC_TS_GetSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -3056,7 +3056,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t Backup tmp = &(TAMPx->BKP0R) + BackupRegister; - /* Write the specified register */ + /* Write the specified register */ *tmp = Data; } diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h index 9cc1d0dee242d5bccc195ab9c8f92bbaa19df1e1..2cc12f7ba1e43fb3063fdfb75b68488f92c76284 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h @@ -130,7 +130,7 @@ extern "C" { * @{ */ #define LL_SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD1 STROBE sw configuration */ -#define LL_SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD2 STROBE sw configuration */ +#define LL_SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE /*!< UCPD2 STROBE sw configuration */ /** * @} */ @@ -177,6 +177,22 @@ extern "C" { * @} */ +#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +/** @defgroup SYSTEM_LL_EC_CLAMPING_DIODE SYSCFG CLAMPING DIODE + * @{ + */ +#define LL_SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN /*!< Enables Clamping diode of PA1 */ +#define LL_SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN /*!< Enables Clamping diode of PA3 */ +#define LL_SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN /*!< Enables Clamping diode of PA5 */ +#define LL_SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN /*!< Enables Clamping diode of PA6 */ +#define LL_SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN /*!< Enables Clamping diode of PA13 */ +#define LL_SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN /*!< Enables Clamping diode of PB0 */ +#define LL_SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN /*!< Enables Clamping diode of PB1 */ +#define LL_SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN /*!< Enables Clamping diode of PB2 */ +/** + * @} + */ +#endif /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP * @{ @@ -1335,6 +1351,84 @@ __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF); } +#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +/** + * @brief Enable Clamping Diode on specific pin + * @rmtoll SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_EnableClampingDiode\n + * SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_EnableClampingDiode\n + * SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_EnableClampingDiode\n + * SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_EnableClampingDiode\n + * SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_EnableClampingDiode\n + * SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_EnableClampingDiode\n + * SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_EnableClampingDiode\n + * SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_EnableClampingDiode + * @param ConfigClampingDiode This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableClampingDiode(uint32_t ConfigClampingDiode) +{ + SET_BIT(SYSCFG->CFGR2, ConfigClampingDiode); +} + +/** + * @brief Disable Clamping Diode on specific pin + * @rmtoll SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_DisableClampingDiode\n + * SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_DisableClampingDiode\n + * SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_DisableClampingDiode\n + * SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_DisableClampingDiode\n + * SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_DisableClampingDiode\n + * SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_DisableClampingDiode\n + * SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_DisableClampingDiode\n + * SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_DisableClampingDiode + * @param ConfigClampingDiode This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableClampingDiode(uint32_t ConfigClampingDiode) +{ + CLEAR_BIT(SYSCFG->CFGR2, ConfigClampingDiode); +} +/** + * @brief Indicates whether clamping diode(s) is(are) enabled. + * @rmtoll SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_IsEnabledClampingDiode\n + * SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_IsEnabledClampingDiode\n + * SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_IsEnabledClampingDiode\n + * SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_IsEnabledClampingDiode\n + * SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_IsEnabledClampingDiode\n + * SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_IsEnabledClampingDiode\n + * SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_IsEnabledClampingDiode\n + * SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_IsEnabledClampingDiode + * @param ConfigClampingDiode This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN + * @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledClampingDiode(uint32_t ConfigClampingDiode) +{ + return ((READ_BIT(SYSCFG->CFGR2, ConfigClampingDiode) == (ConfigClampingDiode)) ? 1UL : 0UL); +} +#endif /** * @} diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h index b00f3349fb96ef9f4164bc7b41529ae8a56a3958..46bf4293a0a536b5e4b97a3e5055b4a8bf2e0850 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -117,7 +117,7 @@ static const uint8_t SHIFT_TAB_OISx[] = */ /* Defines used for the bit position in the register and perform offsets */ -#define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FU) +#define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FUL) /* Generic bit definitions for TIMx_AF1 register */ #define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKIN input enable */ @@ -160,7 +160,7 @@ static const uint8_t SHIFT_TAB_OISx[] = /** Legacy definitions for compatibility purpose @cond 0 -*/ + */ /** @endcond */ @@ -189,14 +189,14 @@ static const uint8_t SHIFT_TAB_OISx[] = * @retval none */ #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ -(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) /** @brief Calculate the deadtime sampling period(in ps). * @param __TIMCLK__ timer input clock frequency (in Hz). @@ -207,9 +207,9 @@ static const uint8_t SHIFT_TAB_OISx[] = * @retval none */ #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ - (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ - ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ - ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) /** * @} */ @@ -710,7 +710,7 @@ typedef struct #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!TIMx_CCRy else active.*/ #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ @@ -766,7 +766,7 @@ typedef struct /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler * @{ */ -#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ +#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ @@ -938,13 +938,13 @@ typedef struct /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source * @{ */ -#define LL_TIM_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ +#define LL_TIM_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #if defined(COMP1) && defined(COMP2) -#define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ -#define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ +#define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #endif /* COMP1 && COMP2 */ #define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */ -#define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */ +#define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */ #define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */ #define LL_TIM_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */ /** @@ -1057,7 +1057,7 @@ typedef struct /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY * @{ */ -#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */ +#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */ #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */ /** * @} @@ -1072,7 +1072,7 @@ typedef struct * @} */ - /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE +/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE * @{ */ #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ @@ -1102,12 +1102,13 @@ typedef struct #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR1 register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_AF1 register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */ /** * @} */ @@ -1279,7 +1280,7 @@ typedef struct /** Legacy definitions for compatibility purpose @cond 0 -*/ + */ #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK /** @endcond @@ -1329,7 +1330,7 @@ typedef struct * @retval UIF status bit */ #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ - (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) /** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. @@ -1343,11 +1344,11 @@ typedef struct * @retval DTG[0:7] */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ - ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ - 0U) + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) /** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. @@ -1357,7 +1358,7 @@ typedef struct * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. @@ -1368,7 +1369,7 @@ typedef struct * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ - ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) /** * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. @@ -1379,8 +1380,8 @@ typedef struct * @retval Compare value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ -((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ - / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). @@ -1392,8 +1393,8 @@ typedef struct * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ - ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ - + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) /** * @brief HELPER macro retrieving the ratio of the input capture prescaler @@ -1406,7 +1407,7 @@ typedef struct * @retval Input capture prescaler ratio (1, 2, 4 or 8) */ #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ - ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) /** @@ -1555,7 +1556,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) /** * @brief Set the timer counter counting mode. - * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) @@ -1579,7 +1580,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo /** * @brief Get actual counter mode. - * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n @@ -1632,7 +1633,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) /** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. * @rmtoll CR1 CKD LL_TIM_SetClockDivision @@ -1650,7 +1651,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi /** * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. * @rmtoll CR1 CKD LL_TIM_GetClockDivision @@ -1667,7 +1668,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) /** * @brief Set the counter value. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @rmtoll CNT CNT LL_TIM_SetCounter * @param TIMx Timer instance @@ -1681,7 +1682,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) /** * @brief Get the counter value. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @rmtoll CNT CNT LL_TIM_GetCounter * @param TIMx Timer instance @@ -1735,7 +1736,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) /** * @brief Set the auto-reload value. * @note The counter is blocked while the auto-reload value is null. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter * @rmtoll ARR ARR LL_TIM_SetAutoReload @@ -1751,7 +1752,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload /** * @brief Get the auto-reload value. * @rmtoll ARR ARR LL_TIM_GetAutoReload - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @param TIMx Timer instance * @retval Auto-reload value @@ -1764,7 +1765,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) /** * @brief Set the repetition counter value. * @note For advanced timer instances RepetitionCounter can be up to 65535. - * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_SetRepetitionCounter * @param TIMx Timer instance @@ -1778,7 +1779,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep /** * @brief Get the repetition counter value. - * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_GetRepetitionCounter * @param TIMx Timer instance @@ -1824,7 +1825,7 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, * they are updated only when a commutation event (COM) occurs. * @note Only on channels that have a complementary output. - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload * @param TIMx Timer instance @@ -1837,7 +1838,7 @@ __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) /** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload * @param TIMx Timer instance @@ -1850,7 +1851,7 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate * @param TIMx Timer instance @@ -1894,7 +1895,7 @@ __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) /** * @brief Set the lock level to freeze the * configuration of several capture/compare parameters. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * the lock mechanism is supported by a timer instance. * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel * @param TIMx Timer instance @@ -2196,7 +2197,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann /** * @brief Set the IDLE state of an output channel * @note This function is significant only for the timer instances - * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) * can be used to check whether or not a timer instance provides * a break input. * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n @@ -2420,7 +2421,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t /** * @brief Enable clearing the output channel on an external event. * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n * CCMR1 OC2CE LL_TIM_OC_EnableClear\n @@ -2447,7 +2448,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) /** * @brief Disable clearing the output channel on an external event. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n * CCMR1 OC2CE LL_TIM_OC_DisableClear\n @@ -2476,7 +2477,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) * @brief Indicates clearing the output channel on an external event is enabled for the output channel. * @note This function enables clearing the output channel on an external event. * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n @@ -2504,7 +2505,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch /** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime @@ -2520,9 +2521,9 @@ __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) /** * @brief Set compare value for output channel 1 (TIMx_CCR1). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * output channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 * @param TIMx Timer instance @@ -2537,9 +2538,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 2 (TIMx_CCR2). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * output channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 * @param TIMx Timer instance @@ -2554,9 +2555,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 3 (TIMx_CCR3). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * output channel is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 * @param TIMx Timer instance @@ -2571,9 +2572,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 4 (TIMx_CCR4). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * output channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 * @param TIMx Timer instance @@ -2587,7 +2588,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 5 (TIMx_CCR5). - * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not * output channel 5 is supported by a timer instance. * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 * @param TIMx Timer instance @@ -2596,12 +2597,12 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare */ __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) { - WRITE_REG(TIMx->CCR5, CompareValue); + MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); } /** * @brief Set compare value for output channel 6 (TIMx_CCR6). - * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not * output channel 6 is supported by a timer instance. * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 * @param TIMx Timer instance @@ -2616,9 +2617,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Get compare value (TIMx_CCR1) set for output channel 1. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * output channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 * @param TIMx Timer instance @@ -2632,9 +2633,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR2) set for output channel 2. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * output channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 * @param TIMx Timer instance @@ -2648,9 +2649,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR3) set for output channel 3. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * output channel 3 is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 * @param TIMx Timer instance @@ -2664,9 +2665,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR4) set for output channel 4. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * output channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 * @param TIMx Timer instance @@ -2679,7 +2680,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR5) set for output channel 5. - * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not * output channel 5 is supported by a timer instance. * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 * @param TIMx Timer instance @@ -2687,12 +2688,12 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) { - return (uint32_t)(READ_REG(TIMx->CCR5)); + return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); } /** * @brief Get compare value (TIMx_CCR6) set for output channel 6. - * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not * output channel 6 is supported by a timer instance. * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 * @param TIMx Timer instance @@ -2705,13 +2706,13 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) /** * @brief Select on which reference signal the OC5REF is combined to. - * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports the combined 3-phase PWM mode. * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels * @param TIMx Timer instance - * @param GroupCH5 This parameter can be one of the following values: + * @param GroupCH5 This parameter can be a combination of the following values: * @arg @ref LL_TIM_GROUPCH5_NONE * @arg @ref LL_TIM_GROUPCH5_OC1REFC * @arg @ref LL_TIM_GROUPCH5_OC2REFC @@ -2720,7 +2721,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) { - MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5); + MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); } /** @@ -3009,7 +3010,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann /** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination * @param TIMx Timer instance @@ -3022,7 +3023,7 @@ __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) /** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination * @param TIMx Timer instance @@ -3035,7 +3036,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) /** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination * @param TIMx Timer instance @@ -3049,9 +3050,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 1. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * input channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 * @param TIMx Timer instance @@ -3065,9 +3066,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 2. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * input channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 * @param TIMx Timer instance @@ -3081,9 +3082,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 3. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * input channel 3 is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 * @param TIMx Timer instance @@ -3097,9 +3098,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 4. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * input channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 * @param TIMx Timer instance @@ -3120,7 +3121,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) /** * @brief Enable external clock mode 2. * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_EnableExternalClock * @param TIMx Timer instance @@ -3133,7 +3134,7 @@ __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) /** * @brief Disable external clock mode 2. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_DisableExternalClock * @param TIMx Timer instance @@ -3146,7 +3147,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) /** * @brief Indicate whether external clock mode 2 is enabled. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock * @param TIMx Timer instance @@ -3163,9 +3164,9 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() * function. This timer input must be configured by calling * the @ref LL_TIM_IC_Config() function. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode1. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR SMS LL_TIM_SetClockSource\n * SMCR ECE LL_TIM_SetClockSource @@ -3183,7 +3184,7 @@ __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSour /** * @brief Set the encoder interface mode. - * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports the encoder mode. * @rmtoll SMCR SMS LL_TIM_SetEncoderMode * @param TIMx Timer instance @@ -3207,7 +3208,7 @@ __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMo */ /** * @brief Set the trigger output (TRGO) used for timer synchronization . - * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance can operate as a master timer. * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput * @param TIMx Timer instance @@ -3229,7 +3230,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSy /** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . - * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check * whether or not a timer instance can be used for ADC synchronization. * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 * @param TIMx Timer Instance @@ -3259,7 +3260,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSyn /** * @brief Set the synchronization mode of a slave timer. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR SMS LL_TIM_SetSlaveMode * @param TIMx Timer instance @@ -3278,7 +3279,7 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) /** * @brief Set the selects the trigger input to be used to synchronize the counter. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR TS LL_TIM_SetTriggerInput * @param TIMx Timer instance @@ -3300,7 +3301,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerI /** * @brief Enable the Master/Slave mode. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode * @param TIMx Timer instance @@ -3313,7 +3314,7 @@ __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) /** * @brief Disable the Master/Slave mode. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode * @param TIMx Timer instance @@ -3326,7 +3327,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) /** * @brief Indicates whether the Master/Slave mode is enabled. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode * @param TIMx Timer instance @@ -3339,7 +3340,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) /** * @brief Configure the external trigger (ETR) input. - * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an external trigger input. * @rmtoll SMCR ETP LL_TIM_ConfigETR\n * SMCR ETPS LL_TIM_ConfigETR\n @@ -3380,7 +3381,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u /** * @brief Select the external trigger (ETR) input source. - * @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or + * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports ETR source selection. * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource * @param TIMx Timer instance @@ -3429,7 +3430,7 @@ __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) */ /** * @brief Enable the break function. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR BKE LL_TIM_EnableBRK * @param TIMx Timer instance @@ -3444,7 +3445,7 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) * @brief Disable the break function. * @rmtoll BDTR BKE LL_TIM_DisableBRK * @param TIMx Timer instance - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @retval None */ @@ -3455,16 +3456,16 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) /** * @brief Configure the break input. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @note Bidirectional mode is only supported by advanced timer instances. - * Macro @ref IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not * a timer instance is an advanced-control timer. - * @note In bidirectional mode (BKBID bit set), the Break input is configured both + * @note In bidirectional mode (BKBID bit set), the Break input is configured both * in input mode and in open drain output mode. Any active Break event will * assert a low logic level on the Break input to indicate an internal break * event to external devices. - * @note When bidirectional mode isn't supported, BreakAFMode must be set to + * @note When bidirectional mode isn't supported, BreakAFMode must be set to * LL_TIM_BREAK_AFMODE_INPUT. * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n * BDTR BKF LL_TIM_ConfigBRK\n @@ -3495,9 +3496,10 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL * @retval None */ -__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, uint32_t BreakAFMode) +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, + uint32_t BreakAFMode) { - MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID , BreakPolarity | BreakFilter | BreakAFMode); + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode); } /** @@ -3529,7 +3531,7 @@ __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) /** * @brief Enable the break 2 function. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 * @param TIMx Timer instance @@ -3542,7 +3544,7 @@ __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) /** * @brief Disable the break 2 function. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 * @param TIMx Timer instance @@ -3555,16 +3557,16 @@ __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) /** * @brief Configure the break 2 input. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @note Bidirectional mode is only supported by advanced timer instances. - * Macro @ref IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not * a timer instance is an advanced-control timer. - * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both + * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both * in input mode and in open drain output mode. Any active Break event will * assert a low logic level on the Break 2 input to indicate an internal break * event to external devices. - * @note When bidirectional mode isn't supported, Break2AFMode must be set to + * @note When bidirectional mode isn't supported, Break2AFMode must be set to * LL_TIM_BREAK2_AFMODE_INPUT. * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n * BDTR BK2F LL_TIM_ConfigBRK2\n @@ -3595,7 +3597,8 @@ __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL * @retval None */ -__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, uint32_t Break2AFMode) +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, + uint32_t Break2AFMode) { MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode); } @@ -3629,7 +3632,7 @@ __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n * BDTR OSSR LL_TIM_SetOffStates @@ -3649,7 +3652,7 @@ __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdl /** * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput * @param TIMx Timer instance @@ -3662,7 +3665,7 @@ __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) /** * @brief Disable automatic output (MOE can be set only by software). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput * @param TIMx Timer instance @@ -3675,7 +3678,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) /** * @brief Indicate whether automatic output is enabled. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput * @param TIMx Timer instance @@ -3690,7 +3693,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by * software and is reset in case of break or break2 event - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs * @param TIMx Timer instance @@ -3705,7 +3708,7 @@ __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by * software and is reset in case of break or break2 event. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs * @param TIMx Timer instance @@ -3718,7 +3721,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) /** * @brief Indicates whether outputs are enabled. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs * @param TIMx Timer instance @@ -3731,7 +3734,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) /** * @brief Enable the signals connected to the designated timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n * @if STM32G081xx @@ -3763,7 +3766,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B /** * @brief Disable the signals connected to the designated timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n * @if STM32G081xx @@ -3795,7 +3798,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t /** * @brief Set the polarity of the break signal for the timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n * @if STM32G081xx @@ -3826,7 +3829,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3 uint32_t Polarity) { register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); - MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE) , (Polarity << TIM_POSITION_BRK_SOURCE)); + MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); } /** * @} @@ -3837,7 +3840,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3 */ /** * @brief Configures the timer DMA burst feature. - * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports the DMA burst mode. * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n * DCR DBA LL_TIM_ConfigDMABurst @@ -3861,12 +3864,13 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL * @param DMABurstLength This parameter can be one of the following values: * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS @@ -3902,7 +3906,7 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB */ /** * @brief Remap TIM inputs (input channel, internal/external triggers). - * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not * a some timer inputs can be remapped. * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n * TIM1_TISEL TI2SEL LL_TIM_SetRemap\n diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_ucpd.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_ucpd.h index bd9f6848f411019dae47fe73294f5b1c88a803db..963de56dec20d52bb012d3afe8f9e32284cd21e8 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_ucpd.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_ucpd.h @@ -58,18 +58,18 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_UCPD_SetPSCClk().*/ uint32_t transwin; /*!< Specifies the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) to achieve a legal - tTransitionWindow (set according to IP clock to define an interval of between 12 and 20 us). - This parameter can be a value between 0x1 and 0x3FF + tTransitionWindow (set according to peripheral clock to define an interval of between 12 and 20 us). + This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F This value can be modified afterwards using unitary function @ref LL_UCPD_SetTransWin().*/ uint32_t IfrGap; /*!< Specifies the definition of the clock divider (minus 1) in order to generate tInterframeGap - from the IP clock. - This parameter can be a value between 0x1 and 0x3FF + from the peripheral clock. + This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F This feature can be modified afterwards using unitary function @ref LL_UCPD_SetIfrGap().*/ - uint32_t HbitClockDiv; /*!< Specifies the number of cycles (minus one) at the IP for a half bit clock e.g. program 3 - for a bit clock that takes 8 cycles of the IP clock "UCPD1_CLK".. - This parameter can be a value between 0x0 and 0x1F. + uint32_t HbitClockDiv; /*!< Specifies the number of cycles (minus one) at UCPD peripheral for a half bit clock e.g. program 3 + for a bit clock that takes 8 cycles of the peripheral clock "UCPD1_CLK".. + This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F. This feature can be modified afterwards using unitary function @ref LL_UCPD_SetHbitClockDiv().*/ } LL_UCPD_InitTypeDef; @@ -370,7 +370,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const * const UCPDx) * @brief Set the receiver ordered set detection enable * @rmtoll CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet * @param UCPDx UCPD Instance - * @param OrderSet This parameter can be combinaison of the following values: + * @param OrderSet This parameter can be combination of the following values: * @arg @ref LL_UCPD_ORDERSET_SOP * @arg @ref LL_UCPD_ORDERSET_SOP1 * @arg @ref LL_UCPD_ORDERSET_SOP2 @@ -408,7 +408,7 @@ __STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc) * @brief Set the number of cycles (minus 1) of the half bit clock * @rmtoll CFG1 TRANSWIN LL_UCPD_SetTransWin * @param UCPDx UCPD Instance - * @param TransWin a value between 1 and 0x3FF + * @param TransWin a value between Min_Data=0x1 and Max_Data=0x1F * @retval None */ __STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin) @@ -420,7 +420,7 @@ __STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin) * @brief Set the clock divider value to generate an interframe gap * @rmtoll CFG1 IFRGAP LL_UCPD_SetIfrGap * @param UCPDx UCPD Instance - * @param IfrGap a value between 1 and 0x3FF + * @param IfrGap a value between Min_Data=0x1 and Max_Data=0x1F * @retval None */ __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) @@ -432,7 +432,7 @@ __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) * @brief Set the clock divider value to generate an interframe gap * @rmtoll CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv * @param UCPDx UCPD Instance - * @param HbitClock a value between 0 and 31 + * @param HbitClock a value between Min_Data=0x0 and Max_Data=0x3F * @retval None */ __STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock) diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h index 61e8cd4b7f724146208d1372f63d6710be18e2e1..9f681c7081cd4307491751cbea8d6f95e6e05c04 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h @@ -44,33 +44,26 @@ extern "C" { * @{ */ /* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ -static const uint16_t USART_PRESCALER_TAB[] = -{ - (uint16_t)1, - (uint16_t)2, - (uint16_t)4, - (uint16_t)6, - (uint16_t)8, - (uint16_t)10, - (uint16_t)12, - (uint16_t)16, - (uint16_t)32, - (uint16_t)64, - (uint16_t)128, - (uint16_t)256 +static const uint32_t USART_PRESCALER_TAB[] = +{ + 1UL, + 2UL, + 4UL, + 6UL, + 8UL, + 10UL, + 12UL, + 16UL, + 32UL, + 64UL, + 128UL, + 256UL }; /** * @} */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup USART_LL_Private_Constants USART Private Constants - * @{ - */ -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup USART_LL_Private_Macros USART Private Macros @@ -570,7 +563,8 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @brief Compute USARTDIV value according to Peripheral Clock and @@ -592,7 +586,8 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case */ -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @} @@ -1864,22 +1859,27 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) * @param BaudRate Baud Rate * @retval None */ -__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling, uint32_t BaudRate) { - register uint32_t usartdiv; + uint32_t usartdiv; register uint32_t brrtemp; - if (OverSampling == LL_USART_OVERSAMPLING_8) + if (PrescalerValue > LL_USART_PRESCALER_DIV256) + { + /* Do not overstep the size of USART_PRESCALER_TAB */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) { - usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint16_t)PrescalerValue, BaudRate)); + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); brrtemp = usartdiv & 0xFFF0U; brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); USARTx->BRR = brrtemp; } else { - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint16_t)PrescalerValue, BaudRate)); + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); } } @@ -1909,11 +1909,12 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @arg @ref LL_USART_OVERSAMPLING_8 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling) +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling) { register uint32_t usartdiv; register uint32_t brrresult = 0x0U; - register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue])); + register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); usartdiv = USARTx->BRR; @@ -3264,7 +3265,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) /** * @brief Clear Noise Error detected Flag - * @rmtoll ICR NECF LL_USART_ClearFlag_NE + * @rmtoll ICR NECF LL_USART_ClearFlag_NE * @param USARTx USART Instance * @retval None */ @@ -4200,12 +4201,12 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t) & (USARTx->TDR); + data_reg_addr = (uint32_t) &(USARTx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t) & (USARTx->RDR); + data_reg_addr = (uint32_t) &(USARTx->RDR); } return data_reg_addr; @@ -4227,7 +4228,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t */ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) { - return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); } /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c index 9012cae6cd9da894731c624452dd5c3142b25380..db00b82b6da43e24b9ecf6b4500493c0aa2bc1d8 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c @@ -56,7 +56,7 @@ * @brief STM32G0xx HAL Driver version number */ #define __STM32G0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32G0xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ +#define __STM32G0xx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32G0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32G0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\ @@ -331,7 +331,7 @@ uint32_t HAL_GetTickPrio(void) /** * @brief Set new tick Freq. - * @retval Status + * @retval status */ HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) { @@ -340,10 +340,12 @@ HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) if (uwTickFreq != Freq) { - uwTickFreq = Freq; - /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); + if (status == HAL_OK) + { + uwTickFreq = Freq; + } } return status; @@ -676,6 +678,35 @@ void HAL_SYSCFG_DisableRemap(uint32_t PinRemap) CLEAR_BIT(SYSCFG->CFGR1, PinRemap); } +#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +/** + * @brief Enable Clamping Diode on specified IO + * @param PinConfig specifies on which pins clamping Diode has to be enabled + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_ClampingDiode + * @retval None + */ +void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig)); + SET_BIT(SYSCFG->CFGR2, PinConfig); +} + +/** + * @brief Disable Clamping Diode on specified IO + * @param PinConfig specifies on which pins clamping Diode has to be disabled + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_ClampingDiode + * @retval None + */ +void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig)); + CLEAR_BIT(SYSCFG->CFGR2, PinConfig); +} +#endif #if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c index 69a0be929d5bdaac001e39d89a150937e6df605d..5d658f7f6b3f680ba04a6a4c97de2b3c11a5eae8 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c @@ -484,12 +484,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ - if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U) + if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC IP internal error */ + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; @@ -588,7 +588,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - /* Set ADC error code to ADC IP internal error */ + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } @@ -706,7 +706,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) } /* Check back that ADC registers have effectively been configured to */ - /* ensure of no potential problem of ADC core IP clocking. */ + /* ensure of no potential problem of ADC core peripheral clocking. */ /* Check through register CFGR1 (excluding analog watchdog configuration: */ /* set into separate dedicated function, and bits of ADC resolution set */ /* out of temporary variable 'tmpCFGR1'). */ @@ -728,7 +728,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC IP internal error */ + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; @@ -926,7 +926,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID @@ -951,7 +951,7 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call return HAL_ERROR; } - if ((hadc->State & HAL_ADC_STATE_READY) != 0) + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) { @@ -1041,7 +1041,7 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID @@ -1386,7 +1386,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - /* Set ADC error code to ADC IP internal error */ + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } @@ -1966,7 +1966,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - /* Set ADC error code to ADC IP internal error */ + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } @@ -2692,7 +2692,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC IP internal error */ + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; @@ -2728,7 +2728,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC IP internal error */ + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; @@ -2764,7 +2764,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC IP internal error */ + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; @@ -2808,7 +2808,7 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC IP internal error */ + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; @@ -2825,7 +2825,7 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC IP internal error */ + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; @@ -2883,7 +2883,7 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - /* Set ADC error code to ADC IP internal error */ + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c index 6eade57112e1d35e6683aa342ef91747a91563ea..38d17bbc5e721543196a168f13b03bba3f9aa20a 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c @@ -61,6 +61,7 @@ /* Calibration time max = 116 / fADC (refer to datasheet) */ /* = 193 024 CPU cycles */ #define ADC_CALIBRATION_TIMEOUT (193024UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ + /** * @} */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cec.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cec.c index 9e9e9f13fdeb8768a3600d7f42a81ceda8051113..bdb35b6003b4e9f9b547ee7b1b3873cb07bb0b0b 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cec.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cec.c @@ -6,9 +6,9 @@ * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface * Consumer Electronics Control Peripheral (CEC). - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions + * + Initialization and de-initialization function + * + IO operation function + * + Peripheral Control function * * @verbatim @@ -98,11 +98,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -204,13 +204,13 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) /* Allocate lock resource and initialize it */ hcec->Lock = HAL_UNLOCKED; - hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */ hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */ + hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */ if (hcec->MspInitCallback == NULL) { - hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit */ + hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit */ } /* Init the low level hardware */ @@ -238,21 +238,22 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) hcec->Init.ListenMode; /* Enable the following CEC Transmission/Reception interrupts as - * well as the following CEC Transmission/Reception Errors interrupts - * Rx Byte Received IT - * End of Reception IT - * Rx overrun - * Rx bit rising error - * Rx short bit period error - * Rx long bit period error - * Rx missing acknowledge - * Tx Byte Request IT - * End of Transmission IT - * Tx Missing Acknowledge IT - * Tx-Error IT - * Tx-Buffer Underrun IT - * Tx arbitration lost */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND | CEC_IER_TX_ALL_ERR); + * well as the following CEC Transmission/Reception Errors interrupts + * Rx Byte Received IT + * End of Reception IT + * Rx overrun + * Rx bit rising error + * Rx short bit period error + * Rx long bit period error + * Rx missing acknowledge + * Tx Byte Request IT + * End of Transmission IT + * Tx Missing Acknowledge IT + * Tx-Error IT + * Tx-Buffer Underrun IT + * Tx arbitration lost */ + __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND | + CEC_IER_TX_ALL_ERR); /* Enable the CEC Peripheral */ __HAL_CEC_ENABLE(hcec); @@ -303,21 +304,22 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND | CEC_FLAG_TXBR | CEC_FLAG_RXBR | CEC_FLAG_RXEND | CEC_ISR_ALL_ERROR); /* Disable the following CEC Transmission/Reception interrupts as - * well as the following CEC Transmission/Reception Errors interrupts - * Rx Byte Received IT - * End of Reception IT - * Rx overrun - * Rx bit rising error - * Rx short bit period error - * Rx long bit period error - * Rx missing acknowledge - * Tx Byte Request IT - * End of Transmission IT - * Tx Missing Acknowledge IT - * Tx-Error IT - * Tx-Buffer Underrun IT - * Tx arbitration lost */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND | CEC_IER_TX_ALL_ERR); + * well as the following CEC Transmission/Reception Errors interrupts + * Rx Byte Received IT + * End of Reception IT + * Rx overrun + * Rx bit rising error + * Rx short bit period error + * Rx long bit period error + * Rx missing acknowledge + * Tx Byte Request IT + * End of Transmission IT + * Tx Missing Acknowledge IT + * Tx-Error IT + * Tx-Buffer Underrun IT + * Tx arbitration lost */ + __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND | + CEC_IER_TX_ALL_ERR); hcec->ErrorCode = HAL_CEC_ERROR_NONE; hcec->gState = HAL_CEC_STATE_RESET; @@ -417,7 +419,8 @@ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, + pCEC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -655,7 +658,7 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec) This subsection provides a set of functions allowing to manage the CEC data transfers. (#) The CEC handle must contain the initiator (TX side) and the destination (RX side) - logical addresses (4-bit long addresses, 0x0F for broadcast messages destination) + logical addresses (4-bit long addresses, 0xF for broadcast messages destination) (#) The communication is performed using Interrupts. These API's return the HAL status. @@ -690,9 +693,10 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec) * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @retval HAL status */ -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, + uint8_t *pData, uint32_t Size) { - /* if the IP isn't already busy and if there is no previous transmission + /* if the peripheral isn't already busy and if there is no previous transmission already pending due to arbitration lost */ if (hcec->gState == HAL_CEC_STATE_READY) { @@ -712,7 +716,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator hcec->ErrorCode = HAL_CEC_ERROR_NONE; /* initialize the number of bytes to send, - * 0 means only one header is sent (ping operation) */ + * 0 means only one header is sent (ping operation) */ hcec->TxXferCount = (uint16_t)Size; /* in case of no payload (Size = 0), sender is only pinging the system; @@ -774,27 +778,29 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) uint32_t reg; reg = hcec->Instance->ISR; - /*----------------------- Arbitration Lost Management ----------------------*/ - /* CEC TX arbitration error interrupt occurred -----------------------------*/ + + /* ----------------------------Arbitration Lost Management----------------------------------*/ + /* CEC TX arbitration error interrupt occurred --------------------------------------*/ if ((reg & CEC_FLAG_ARBLST) != 0U) { hcec->ErrorCode = HAL_CEC_ERROR_ARBLST; __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); } - /*------------------------------ Rx Management -----------------------------*/ - /* CEC RX byte received interrupt -----------------------------------------*/ + /* ----------------------------Rx Management----------------------------------*/ + /* CEC RX byte received interrupt ---------------------------------------------------*/ if ((reg & CEC_FLAG_RXBR) != 0U) { /* reception is starting */ hcec->RxState = HAL_CEC_STATE_BUSY_RX; hcec->RxXferSize++; /* read received byte */ - *hcec->Init.RxBuffer++ = (uint8_t) hcec->Instance->RXDR; + *hcec->Init.RxBuffer = (uint8_t) hcec->Instance->RXDR; + hcec->Init.RxBuffer++; __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); } - /* CEC RX end received interrupt ------------------------------------------*/ + /* CEC RX end received interrupt ---------------------------------------------------*/ if ((reg & CEC_FLAG_RXEND) != 0U) { /* clear IT */ @@ -804,7 +810,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) hcec->RxState = HAL_CEC_STATE_READY; hcec->ErrorCode = HAL_CEC_ERROR_NONE; hcec->Init.RxBuffer -= hcec->RxXferSize; -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U) hcec->RxCpltCallback(hcec, hcec->RxXferSize); #else HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize); @@ -812,48 +818,53 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) hcec->RxXferSize = 0U; } - /*------------------------------ Tx Management -----------------------------*/ - /* CEC TX byte request interrupt -------------------------------------------*/ + /* ----------------------------Tx Management----------------------------------*/ + /* CEC TX byte request interrupt ------------------------------------------------*/ if ((reg & CEC_FLAG_TXBR) != 0U) { if (hcec->TxXferCount == 0U) { /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ __HAL_CEC_LAST_BYTE_TX_SET(hcec); - hcec->Instance->TXDR = *hcec->pTxBuffPtr++; + hcec->Instance->TXDR = *hcec->pTxBuffPtr; + hcec->pTxBuffPtr++; } else { - hcec->Instance->TXDR = *hcec->pTxBuffPtr++; + hcec->Instance->TXDR = *hcec->pTxBuffPtr; + hcec->pTxBuffPtr++; hcec->TxXferCount--; } /* clear Tx-Byte request flag */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); } - /* CEC TX end interrupt ----------------------------------------------------*/ + /* CEC TX end interrupt ------------------------------------------------*/ if ((reg & CEC_FLAG_TXEND) != 0U) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND); /* Tx process is ended, restore hcec->gState to Ready */ hcec->gState = HAL_CEC_STATE_READY; - /* Call the Process Unlocked before calling the Tx call back API to give the - possibility to start again the Transmission under the Tx call back API */ + /* Call the Process Unlocked before calling the Tx call back API to give the possibility to + start again the Transmission under the Tx call back API */ __HAL_UNLOCK(hcec); hcec->ErrorCode = HAL_CEC_ERROR_NONE; -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U) hcec->TxCpltCallback(hcec); #else HAL_CEC_TxCpltCallback(hcec); #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ } - /*------------------------- Rx/Tx Error Management -------------------------*/ - if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U) + /* ----------------------------Rx/Tx Error Management----------------------------------*/ + if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR | + CEC_ISR_TXACKE)) != 0U) { hcec->ErrorCode = reg; - __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE | HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE); + __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE | + HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE); + if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U) { @@ -861,22 +872,26 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) hcec->RxXferSize = 0U; hcec->RxState = HAL_CEC_STATE_READY; } - else if (((reg & CEC_ISR_ARBLST) == 0U)&&((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0U)) + else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)) { /* Set the CEC state ready to be able to start again the process */ hcec->gState = HAL_CEC_STATE_READY; } - else + else { /* Nothing todo*/ - } -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) + } +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U) hcec->ErrorCallback(hcec); #else /* Error Call Back */ HAL_CEC_ErrorCallback(hcec); #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ } + else + { + /* Nothing todo*/ + } } /** @@ -948,8 +963,7 @@ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) */ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) { - uint32_t temp1; - uint32_t temp2; + uint32_t temp1, temp2; temp1 = hcec->gState; temp2 = hcec->RxState; @@ -957,11 +971,11 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) } /** - * @brief Return the CEC error code - * @param hcec pointer to a CEC_HandleTypeDef structure that contains - * the configuration information for the specified CEC. - * @retval CEC Error Code - */ + * @brief Return the CEC error code + * @param hcec pointer to a CEC_HandleTypeDef structure that contains + * the configuration information for the specified CEC. + * @retval CEC Error Code + */ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) { return hcec->ErrorCode; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c index 4bb6306aa4654b71bbd981018f1408704bed8296..9419b126cb31f21a4069ed7b727ab2259fde2d8b 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c @@ -3,14 +3,14 @@ * @file stm32g0xx_hal_comp.c * @author MCD Application Team * @brief COMP HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: * + Initialization and de-initialization functions * + Start/Stop operation functions in polling mode * + Start/Stop operation functions in interrupt mode (through EXTI interrupt) * + Peripheral control functions * + Peripheral state functions - * + * @verbatim ================================================================================ ##### COMP Peripheral features ##### @@ -22,18 +22,18 @@ (#) Comparators input minus (inverting input) and input plus (non inverting input) can be set to internal references or to GPIO pins (refer to GPIO list in reference manual). - + (#) Comparators output level is available using HAL_COMP_GetOutputLevel() and can be redirected to other peripherals: GPIO pins (in mode alternate functions for comparator), timers. (refer to GPIO list in reference manual). - + (#) The comparators have interrupt capability through the EXTI controller with wake-up from sleep and stop modes. - + (#) Pairs of comparators instances can be combined in window mode (2 consecutive instances odd and even COMP and COMP). - + From the corresponding IRQ handler, the right interrupt source can be retrieved using macro __HAL_COMP_COMPx_EXTI_GET_FLAG(). @@ -42,18 +42,18 @@ [..] This driver provides functions to configure and program the comparator instances of STM32G0xx devices. - + To use the comparator, perform the following steps: - + (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit(): (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode using HAL_GPIO_Init(). (++) If needed, configure the GPIO connected to comparator output in alternate function mode using HAL_GPIO_Init(). - (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and + (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator interrupt vector using HAL_NVIC_EnableIRQ() function. - + (#) Configure the comparator using HAL_COMP_Init() function: (++) Select the input minus (inverting input) (++) Select the input plus (non-inverting input) @@ -62,29 +62,29 @@ (++) Select the output polarity (++) Select the power mode (++) Select the window mode - + -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() to enable internal control clock of the comparators. However, this is a legacy strategy. In future STM32 families, COMP clock enable must be implemented by user in "HAL_COMP_MspInit()". - Therefore, for compatibility anticipation, it is recommended to + Therefore, for compatibility anticipation, it is recommended to implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()". - + (#) Reconfiguration on-the-fly of comparator can be done by calling again function HAL_COMP_Init() with new input structure parameters values. - + (#) Enable the comparator using HAL_COMP_Start() function. - + (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions to manage comparator outputs (events and output level). - + (#) Disable the comparator using HAL_COMP_Stop() function. - + (#) De-initialize the comparator using HAL_COMP_DeInit() function. - + (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function. The only way to unlock the comparator is a device hardware reset. - + *** Callback registration *** ============================================= [..] @@ -141,7 +141,7 @@ When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. - + @endverbatim ****************************************************************************** @@ -209,14 +209,14 @@ * @{ */ -/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and de-initialization functions. - * -@verbatim +/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and de-initialization functions. + * +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This section provides functions to initialize and de-initialize comparators + [..] This section provides functions to initialize and de-initialize comparators @endverbatim * @{ @@ -237,7 +237,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */ __IO uint32_t wait_loop_index = 0UL; HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) { @@ -256,23 +256,23 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol)); assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode)); assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); - assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); + assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) { assert_param(IS_COMP_WINDOWOUTPUT(hcomp->Init.WindowOutput)); } - + if(hcomp->State == HAL_COMP_STATE_RESET) { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; - + /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); - - + + #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) /* Init the COMP Callback settings */ hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ @@ -281,7 +281,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ } - + /* Init the low level hardware */ /* Note: Internal control clock of the comparators must */ /* be enabled in "HAL_COMP_MspInit()" */ @@ -295,10 +295,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) HAL_COMP_MspInit(hcomp); #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } - + /* Memorize voltage scaler state before initialization */ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)); - + /* Set COMP parameters */ tmp_csr = ( hcomp->Init.InputMinus | hcomp->Init.InputPlus @@ -307,7 +307,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) | hcomp->Init.OutputPol | hcomp->Init.Mode ); - + /* Set parameters in COMP register */ /* Note: Update all bits except read-only, lock and enable bits */ MODIFY_REG(hcomp->Instance->CSR, @@ -316,7 +316,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) COMP_CSR_BLANKING , tmp_csr ); - + /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ @@ -336,7 +336,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); } - + /* Set window mode output */ /* Note: Window mode mode output can also be used when window mode */ /* is disabled, to use comparators in independent mode with their */ @@ -347,23 +347,23 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); break; - + case COMP_WINDOWOUTPUT_COMP2: CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); break; - + case COMP_WINDOWOUTPUT_BOTH: SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); break; - + default: /* COMP_WINDOWOUTPUT_EACH_COMP */ CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); break; } - + /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is required and not already enabled */ if ((READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)) != 0UL) && @@ -379,10 +379,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) wait_loop_index--; } } - + /* Get the EXTI line corresponding to the selected COMP instance */ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); - + /* Manage EXTI settings */ if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) { @@ -395,7 +395,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { LL_EXTI_DisableRisingTrig_0_31(exti_line); } - + /* Configure EXTI falling edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) { @@ -405,11 +405,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { LL_EXTI_DisableFallingTrig_0_31(exti_line); } - + /* Clear COMP EXTI pending bit (if any) */ LL_EXTI_ClearRisingFlag_0_31(exti_line); LL_EXTI_ClearFallingFlag_0_31(exti_line); - + /* Configure EXTI event mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) { @@ -419,7 +419,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { LL_EXTI_DisableEvent_0_31(exti_line); } - + /* Configure EXTI interrupt mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) { @@ -434,11 +434,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { /* Disable EXTI event mode */ LL_EXTI_DisableEvent_0_31(exti_line); - + /* Disable EXTI interrupt mode */ LL_EXTI_DisableIT_0_31(exti_line); } - + /* Set HAL COMP handle state */ /* Note: Transition from state reset to state ready, */ /* otherwise (coming from state ready or busy) no state update. */ @@ -447,7 +447,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) hcomp->State = HAL_COMP_STATE_READY; } } - + return status; } @@ -461,7 +461,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) { @@ -475,30 +475,30 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - + /* Set COMP_CSR register to reset value */ WRITE_REG(hcomp->Instance->CSR, 0x00000000UL); - + #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) if (hcomp->MspDeInitCallback == NULL) { hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ } - + /* DeInit the low level hardware: GPIO, RCC clock, NVIC */ hcomp->MspDeInitCallback(hcomp); #else /* DeInit the low level hardware: GPIO, RCC clock, NVIC */ HAL_COMP_MspDeInit(hcomp); #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ - + /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hcomp); } - + return status; } @@ -511,7 +511,7 @@ __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcomp); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_COMP_MspInit could be implemented in the user file */ @@ -526,7 +526,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcomp); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_COMP_MspDeInit could be implemented in the user file */ @@ -549,7 +549,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - + if (pCallback == NULL) { /* Update the error code */ @@ -557,7 +557,7 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_ return HAL_ERROR; } - + if (HAL_COMP_STATE_READY == hcomp->State) { switch (CallbackID) @@ -565,19 +565,19 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_ case HAL_COMP_TRIGGER_CB_ID : hcomp->TriggerCallback = pCallback; break; - + case HAL_COMP_MSPINIT_CB_ID : hcomp->MspInitCallback = pCallback; break; - + case HAL_COMP_MSPDEINIT_CB_ID : hcomp->MspDeInitCallback = pCallback; break; - + default : /* Update the error code */ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; break; @@ -590,15 +590,15 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_ case HAL_COMP_MSPINIT_CB_ID : hcomp->MspInitCallback = pCallback; break; - + case HAL_COMP_MSPDEINIT_CB_ID : hcomp->MspDeInitCallback = pCallback; break; - + default : /* Update the error code */ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; break; @@ -608,11 +608,11 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_ { /* Update the error code */ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; } - + return status; } @@ -639,7 +639,7 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM case HAL_COMP_TRIGGER_CB_ID : hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ break; - + case HAL_COMP_MSPINIT_CB_ID : hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ break; @@ -696,13 +696,13 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM * @} */ -/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions - * @brief Start-Stop operation functions. - * -@verbatim +/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions + * @brief Start-Stop operation functions. + * +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Start a comparator instance. (+) Stop a comparator instance. @@ -720,7 +720,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { __IO uint32_t wait_loop_index = 0UL; HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) { @@ -739,10 +739,10 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN); - + /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_BUSY; - + /* Delay for COMP startup time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ @@ -771,7 +771,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) { @@ -785,7 +785,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - + /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */ /* (all states except HAL_COMP_STATE_RESET and except locked status. */ if(hcomp->State != HAL_COMP_STATE_RESET) @@ -801,7 +801,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) status = HAL_ERROR; } } - + return status; } @@ -816,7 +816,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); uint32_t comparator_window_mode_odd = READ_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); uint32_t comparator_window_mode_even = READ_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); - + /* Check COMP EXTI flag */ if(LL_EXTI_IsActiveRisingFlag_0_31(exti_line) != 0UL) { @@ -838,7 +838,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) /* Clear COMP EXTI line pending bit */ LL_EXTI_ClearRisingFlag_0_31(exti_line); } - + /* COMP trigger user callback */ #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) hcomp->TriggerCallback(hcomp); @@ -866,7 +866,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) /* Clear COMP EXTI line pending bit */ LL_EXTI_ClearFallingFlag_0_31(exti_line); } - + /* COMP trigger callback */ #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) hcomp->TriggerCallback(hcomp); @@ -884,15 +884,15 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) * @} */ -/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions - * @brief Management functions. - * -@verbatim +/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions. + * +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the comparators. + This subsection provides a set of functions allowing to control the comparators. @endverbatim * @{ @@ -909,7 +909,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) { @@ -923,7 +923,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - + /* Set HAL COMP handle state */ switch(hcomp->State) { @@ -938,18 +938,18 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) break; } } - + if(status == HAL_OK) { /* Set the lock bit corresponding to selected comparator */ __HAL_COMP_LOCK(hcomp); } - - return status; + + return status; } /** - * @brief Return the output level (high or low) of the selected comparator. + * @brief Return the output level (high or low) of the selected comparator. * The output level depends on the selected polarity. * If the polarity is not inverted: * - Comparator output is low when the input plus is at a lower @@ -962,16 +962,16 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * - Comparator output is low when the input plus is at a higher * voltage than the input minus * @param hcomp COMP handle - * @retval Returns the selected comparator output level: + * @retval Returns the selected comparator output level: * @arg COMP_OUTPUT_LEVEL_LOW * @arg COMP_OUTPUT_LEVEL_HIGH - * + * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - + return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE) >> COMP_OUTPUT_LEVEL_BITOFFSET_POS); } @@ -985,7 +985,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcomp); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_COMP_TriggerCallback should be implemented in the user file */ @@ -996,13 +996,13 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @} */ -/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim +/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection permit to get in run-time the status of the peripheral. @@ -1039,7 +1039,7 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) { /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - + return hcomp->ErrorCode; } diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c index 8c7ca67baeb34a15b4c9c21ad638c866adeb6d6f..94bd980a7d2f5fe7a7eaecbc1849ac777b019282 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c @@ -16,10 +16,10 @@ ##### How to use this driver ##### ============================================================================== [..] - The CRYP HAL driver can be used in CRYP or TinyAES IP as follows: + The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows: (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): - (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES IP + (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT()) (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() @@ -41,6 +41,9 @@ (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM. (##) The initialization vector (counter). It is not used in ECB mode. (##) The key buffer used for encryption/decryption. + (+++) In some specific configurations, the key is written by the application + code out of the HAL scope. In that case, user can still resort to the + HAL APIs as usual but must make sure that pKey pointer is set to NULL. (##) The Header used only in AES GCM and CCM Algorithm for authentication. (##) The HeaderSize The size of header buffer in word. (##) The B0 block is the first authentication block used only in AES CCM mode. @@ -64,15 +67,21 @@ (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. + (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt() + without having to configure again the Key or the Initialization Vector between each API call, + the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE. + Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA() + or HAL_CRYP_Decrypt_DMA(). + [..] The cryptographic processor supports following standards: - (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP: + (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 peripheral: (##)64-bit data block processing (##) chaining modes supported : (+++) Electronic Code Book(ECB) (+++) Cipher Block Chaining (CBC) (##) keys length supported :64-bit, 128-bit and 192-bit. - (#) The advanced encryption standard (AES) supported by CRYP1 & TinyAES IP: + (#) The advanced encryption standard (AES) supported by CRYP1 & TinyAES peripheral: (##)128-bit data block processing (##) chaining modes supported : (+++) Electronic Code Book(ECB) @@ -81,21 +90,69 @@ (+++) Galois/counter mode (GCM/GMAC) (+++) Counter with Cipher Block Chaining-Message(CCM) (##) keys length Supported : - (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit. - (+++) for TinyAES IP: 128-bit and 256-bit + (+++) for CRYP1 peripheral: 128-bit, 192-bit and 256-bit. + (+++) for TinyAES peripheral: 128-bit and 256-bit - [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 and TinyAES IP: + [..] + (@) Specific care must be taken to format the key and the Initialization Vector IV! + + [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where + b127 is the MSB and b0 the LSB, the key must be stored in MCU memory + (+) as a sequence of words where the MSB word comes first (occupies the + lowest memory address) + (++) address n+0 : 0b b127 .. b120 b119 .. b112 b111 .. b104 b103 .. b96 + (++) address n+4 : 0b b95 .. b88 b87 .. b80 b79 .. b72 b71 .. b64 + (++) address n+8 : 0b b63 .. b56 b55 .. b48 b47 .. b40 b39 .. b32 + (++) address n+C : 0b b31 .. b24 b23 .. b16 b15 .. b8 b7 .. b0 + [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}. + The 4 32-bit words that make the key must be stored as follows in MCU memory: + (+) address n+0 : 0x B15 B14 B13 B12 + (+) address n+4 : 0x B11 B10 B9 B8 + (+) address n+8 : 0x B7 B6 B5 B4 + (+) address n+C : 0x B3 B2 B1 B0 + [..] which leads to the expected setting + (+) AES_KEYR3 = 0x B15 B14 B13 B12 + (+) AES_KEYR2 = 0x B11 B10 B9 B8 + (+) AES_KEYR1 = 0x B7 B6 B5 B4 + (+) AES_KEYR0 = 0x B3 B2 B1 B0 + + [..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}. + The 8 32-bit words that make the key must be stored as follows in MCU memory: + (+) address n+00 : 0x B31 B30 B29 B28 + (+) address n+04 : 0x B27 B26 B25 B24 + (+) address n+08 : 0x B23 B22 B21 B20 + (+) address n+0C : 0x B19 B18 B17 B16 + (+) address n+10 : 0x B15 B14 B13 B12 + (+) address n+14 : 0x B11 B10 B9 B8 + (+) address n+18 : 0x B7 B6 B5 B4 + (+) address n+1C : 0x B3 B2 B1 B0 + [..] which leads to the expected setting + (+) AES_KEYR7 = 0x B31 B30 B29 B28 + (+) AES_KEYR6 = 0x B27 B26 B25 B24 + (+) AES_KEYR5 = 0x B23 B22 B21 B20 + (+) AES_KEYR4 = 0x B19 B18 B17 B16 + (+) AES_KEYR3 = 0x B15 B14 B13 B12 + (+) AES_KEYR2 = 0x B11 B10 B9 B8 + (+) AES_KEYR1 = 0x B7 B6 B5 B4 + (+) AES_KEYR0 = 0x B3 B2 B1 B0 + + [..] Initialization Vector IV (4 32-bit words) format must follow the same as + that of a 128-bit long key. + + [..] Note that key and IV registers are not sensitive to swap mode selection. + + [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 and TinyAES peripherals: (#) Algorithm supported : (##) Galois/counter mode (GCM) (##) Galois message authentication code (GMAC) :is exactly the same as GCM algorithm composed only by an header. (#) Four phases are performed in GCM : - (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing - (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash + (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing + (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash computation only. - (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream + (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream encryption + data XORing. It works in a similar way for ciphertext (C). - (##) Final phase: IP generates the authenticated tag (T) using the last block of data. + (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. (#) structure of message construction in GCM is defined as below : (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter @@ -129,7 +186,7 @@ |-----------|--------------------|-----------|----------------------| [..] This section describe The AES Counter with Cipher Block Chaining-Message - Authentication Code (CCM) supported by both CRYP1 and TinyAES IP: + Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral: (#) Specific parameters for CCM : (##) B0 block : According to NIST Special Publication 800-38C, @@ -176,28 +233,30 @@ - Generation of CTR0: same as CTR1 with bit[0] set to zero. - (#) Four phases are performed in CCM for CRYP1 IP: - (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing - (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash + (#) Four phases are performed in CCM for CRYP1 peripheral: + (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing + (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash computation only. - (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream + (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream encryption + data XORing. It works in a similar way for ciphertext (C). - (##) Final phase: IP generates the authenticated tag (T) using the last block of data. - (#) CCM in TinyAES IP: + (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. + (#) CCM in TinyAES peripheral: (##) To perform message payload encryption or decryption AES is configured in CTR mode. (##) For authentication two phases are performed : - - Header phase: IP processes the Additional Authenticated Data (AAD) first, then the cleartext message + - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message only cleartext payload (not the ciphertext payload) is used and no outpout. - (##) Final phase: IP generates the authenticated tag (T) using the last block of data. + (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. *** Callback registration *** - ============================================= + ============================= + [..] The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() to register an interrupt callback. + [..] Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. (+) OutCpltCallback : Output FIFO transfer completed callback. @@ -207,6 +266,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. + [..] Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default weak function. @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, @@ -218,6 +278,7 @@ (+) MspInitCallback : CRYP MspInit. (+) MspDeInitCallback : CRYP MspDeInit. + [..] By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET all callbacks are set to the corresponding weak functions : examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback(). @@ -227,6 +288,7 @@ if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit() keep and use the user MspInit/MspDeInit functions (registered beforehand) + [..] Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only. Exception done MspInit/MspDeInit callbacks that can be registered/unregistered in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state, @@ -235,14 +297,16 @@ using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit() or @ref HAL_CRYP_Init() function. + [..] When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. *** Suspend/Resume feature *** - ============================================= + ============================== + [..] The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1 allows the user to resort to the suspend/resume feature. A low priority block processing can be suspended to process a high priority block @@ -263,15 +327,24 @@ (i.e when the low priority block processing is about to end). There is no use to suspend the tag generation processing for authentication algorithms. + [..] + (@) If the key is written out of HAL scope (case pKey pointer set to NULL by the user), + the block processing suspension/resumption mechanism is NOT applicable. + + [..] + (@) If the Key and Initialization Vector are configured only once and configuration is + skipped for consecutive processings (case KeyIVConfigSkip set to CRYP_KEYIVCONFIG_ONCE), + the block processing suspension/resumption mechanism is NOT applicable. + @endverbatim ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -407,10 +480,10 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); (+) Key size (+) Data Type : 32,16, 8 or 1bit (+) AlgoMode : - - for CRYP1 IP : + - for CRYP1 peripheral : ECB and CBC in DES/TDES Standard ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard. - - for TinyAES2 IP, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported. + - for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported. (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef @endverbatim @@ -436,6 +509,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize)); assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm)); + assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip)); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) if (hcryp->State == HAL_CRYP_STATE_RESET) @@ -466,12 +540,15 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ - /* Set the key size(This bit field is do not care in the DES or TDES modes) data type and Algorithm */ + /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and Algorithm */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /* Reset Error Code field */ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; + /* Reset peripheral Key and IV configuration flag */ + hcryp->KeyIVConfig = 0U; + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -573,7 +650,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.B0 = pConf->B0; hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; - /* Set the key size(This bit field is do not care in the DES or TDES modes) data type, AlgoMode and operating mode*/ + /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /*clear error flags*/ @@ -895,11 +972,11 @@ void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp) /** - * @brief CRYP processing suspension and IP internal parameters storage. + * @brief CRYP processing suspension and peripheral internal parameters storage. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @note IP internal parameters are stored to be readily available when - * suspended processing is resumed later on. + * @note peripheral internal parameters are stored to be readily available when + * suspended processing is resumed later on. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) @@ -920,7 +997,7 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) /* Suspend Processing */ /* If authentication algorithms on-going, carry out first saving steps - before disable the IP */ + before disable the peripheral */ if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || \ (hcryp->Init.Algorithm == CRYP_AES_CCM)) { @@ -953,9 +1030,9 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) /* Save Initialisation Vector registers */ CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved); } - + /* Save Control register */ - hcryp->CR_saved = hcryp->Instance->CR; + hcryp->CR_saved = hcryp->Instance->CR; } return HAL_OK; @@ -979,11 +1056,11 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) } else { - + /* Restore low-priority block CRYP handle parameters */ hcryp->Init = hcryp->Init_saved; hcryp->State = hcryp->State_saved; - + /* Chaining algorithms case */ if ((hcryp->Init_saved.Algorithm == CRYP_AES_ECB) || \ (hcryp->Init_saved.Algorithm == CRYP_AES_CBC) || \ @@ -1060,10 +1137,10 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) ============================================================================== [..] This section provides API allowing to Encrypt/Decrypt Data following Standard DES/TDES or AES, and Algorithm configured by the user: - (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported : + (+) Standard DES/TDES only supported by CRYP1 peripheral, below list of Algorithm supported : - Electronic Code Book(ECB) - Cipher Block Chaining (CBC) - (+) Standard AES supported by CRYP1 IP & TinyAES, list of Algorithm supported: + (+) Standard AES supported by CRYP1 peripheral & TinyAES, list of Algorithm supported: - Electronic Code Book(ECB) - Cipher Block Chaining (CBC) - Counter mode (CTR) @@ -1488,6 +1565,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu { HAL_StatusTypeDef status; uint32_t algo; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1526,18 +1604,38 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu case CRYP_AES_CBC: case CRYP_AES_CTR: - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the Initialization Vector*/ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } } + if (DoKeyIVConfig == 1U) + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Set the Initialization Vector*/ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } + } /* if (DoKeyIVConfig == 1U) */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -1748,7 +1846,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) /** * @brief Return the CRYP error code. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for the CRYP IP + * the configuration information for the CRYP peripheral * @retval CRYP error code */ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) @@ -1837,19 +1935,40 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti { uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - if (hcryp->Init.Algorithm != CRYP_AES_ECB) + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { - /* Set the Initialization Vector*/ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } } + if (DoKeyIVConfig == 1U) + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } + } /* if (DoKeyIVConfig == 1U) */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -1884,18 +2003,40 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti */ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) { + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - if (hcryp->Init.Algorithm != CRYP_AES_ECB) + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { - /* Set the Initialization Vector*/ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } } + + if (DoKeyIVConfig == 1U) + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } + } /* if (DoKeyIVConfig == 1U) */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -1941,65 +2082,87 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti { uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ - - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (DoKeyIVConfig == 1U) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { + if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + { + /* Set key preparation for decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Wait for CCF flag to be raised */ - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); - /* Change state & error code*/ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Change state & error code*/ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); } - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + else /*Mode 4 : decryption & Key preparation*/ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + /* Set decryption & Key preparation operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + } } - else /*Mode 4 : decryption & Key preparation*/ + else /*Algorithm CTR */ { /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } - /* Set decryption & Key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); } - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } + } /* if (DoKeyIVConfig == 1U) */ - /* Set IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); - } /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2034,73 +2197,94 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) { __IO uint32_t count = 0U; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) + if (DoKeyIVConfig == 1U) { - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + { + /* Set key preparation for decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do - { - count-- ; - if (count == 0U) + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Mode 4 : decryption & key preparation*/ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + /* Set decryption & key preparation operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + } } - else /*Mode 4 : decryption & key preparation*/ + else /*Algorithm CTR */ { /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set decryption & key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); } - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } + } /* if (DoKeyIVConfig == 1U) */ - /* Set IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); - } /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; if (hcryp->Size != 0U) @@ -2142,71 +2326,93 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) { __IO uint32_t count = 0U; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/ + if (hcryp->KeyIVConfig == 1U) { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (DoKeyIVConfig == 1U) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { + if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/ + { + /* Set key preparation for decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do - { - count-- ; - if (count == 0U) + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Mode 4 : decryption & key preparation*/ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + /* Set decryption & Key preparation operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + } } - else /*Mode 4 : decryption & key preparation*/ + else /*Algorithm CTR */ { /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } - /* Set decryption & Key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); } - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } + } /* if (DoKeyIVConfig == 1U) */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); - } /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2238,8 +2444,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) { CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit - in the DMACR register */ + /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); /* Call input data transfer complete callback */ @@ -2267,9 +2472,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - /* Disable the DMA transfer for output FIFO request by resetting - the DOEN bit in the DMACR register */ - + /* Stop the DMA transfers to the OUT FIFO by clearing to "0" the DMAOUTEN */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); /* Clear CCF flag */ @@ -2593,7 +2796,7 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ @@ -2602,7 +2805,7 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); } @@ -2652,33 +2855,38 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param KeySize Size of Key + * @note If pKey is NULL, the Key registers are not written. This configuration + * occurs when the key is written out of HAL scope. * @retval None */ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize) { - switch (KeySize) + if (hcryp->Init.pKey != NULL) { - case CRYP_KEYSIZE_256B: - hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U); - hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U); - hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U); - hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U); - hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U); - hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U); - hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U); - break; - case CRYP_KEYSIZE_128B: - hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U); - hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U); - hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U); - - break; - default: - break; - } -} + switch (KeySize) + { + case CRYP_KEYSIZE_256B: + hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U); + hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U); + hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U); + hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U); + hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U); + hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U); + hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U); + break; + case CRYP_KEYSIZE_128B: + hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U); + hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U); + hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U); + + break; + default: + break; + } + } +} /** * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG @@ -2697,57 +2905,86 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t lastwordsize; uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } - /****************************** Init phase **********************************/ + if (DoKeyIVConfig == 1U) + { - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /****************************** Init phase **********************************/ - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* just wait for hash computation */ - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); - /* Process unlocked & return error */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /************************ Header phase *************************************/ + /* Process unlocked & return error */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) - { - return HAL_ERROR; - } + /************************ Header phase *************************************/ - /*************************Payload phase ************************************/ + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /*************************Payload phase ************************************/ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + } /* if (DoKeyIVConfig == 1U) */ if ((hcryp->Size % 16U) != 0U) { @@ -2848,6 +3085,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->CrypOutCount++; } } + /* Return function status */ return HAL_OK; } @@ -2864,6 +3102,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t loopcounter; uint32_t lastwordsize; uint32_t npblb; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -2873,67 +3112,224 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) } #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } - /******************************* Init phase *********************************/ + /* Configure Key, IV and process message (header and payload) */ + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /******************************* Init phase *********************************/ - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); - /* just wait for hash computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /***************************** Header phase *********************************/ + /***************************** Header phase *********************************/ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if (hcryp->CrypInCount == (hcryp->Size / 4U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 16Bytes : first block is the last block*/ + { + /* Workaround not implemented for TinyAES2*/ + /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: + Workaround is implemented in polling mode, so if last block of + payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ + + + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - ((uint32_t)hcryp->Size); + + if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + { + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + } + else if ((hcryp->Init.HeaderSize) < 4U) + { + for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + else + { + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + + } /* end of if (DoKeyIVConfig == 1U) */ + else /* Key and IV have already been configured, + header has already been processed; + only process here message payload */ { - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - /* Select payload phase once the header phase is performed */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); @@ -3013,49 +3409,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) } } } - else if ((hcryp->Init.HeaderSize) < 4U) - { - for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - while (loopcounter < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - - /* Call Input transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - else - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - } /* Return function status */ return HAL_OK; @@ -3076,67 +3429,96 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) uint32_t npblb; uint32_t lastwordsize; uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (DoKeyIVConfig == 1U) + { - /*************************** Init phase ************************************/ + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /*************************** Init phase ************************************/ - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); - /* just wait for hash computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /************************ Header phase *************************************/ + /************************ Header phase *************************************/ - if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) - { - return HAL_ERROR; - } + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } - /************************ Payload phase ************************************/ + /************************ Payload phase ************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + } /* if (DoKeyIVConfig == 1U) */ if (hcryp->Size == 0U) { @@ -3231,6 +3613,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; hcryp->CrypOutCount++; } + /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; @@ -3245,7 +3628,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /** * @brief AES CCM encryption/decryption processing in polling mode - * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation. + * for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Timeout Timeout duration @@ -3261,58 +3644,86 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t temp; /* Temporary CrypOutBuff */ uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } - /********************** Init phase ******************************************/ + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /********************** Init phase ******************************************/ - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the initialization vector (IV) with B0 */ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Set the initialization vector (IV) with B0 */ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* just wait for hash computation */ - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked & return error */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /* Process unlocked & return error */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /************************ Header phase *************************************/ + /* Header block(B1) : associated data length expressed in bytes concatenated + with Associated Data (A)*/ + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } - /************************ Header phase *************************************/ - /* Header block(B1) : associated data length expressed in bytes concatenated - with Associated Data (A)*/ - if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) - { - return HAL_ERROR; - } + /*************************Payload phase ************************************/ - /*************************Payload phase ************************************/ + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Select payload phase once the header phase is performed */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); - /* Select payload phase once the header phase is performed */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + } /* if (DoKeyIVConfig == 1U) */ if ((hcryp->Size % 16U) != 0U) { @@ -3321,7 +3732,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t } /* Get tick */ tickstart = HAL_GetTick(); - + /* Write input data and get output data */ incount = hcryp->CrypInCount; outcount = hcryp->CrypOutCount; @@ -3415,7 +3826,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /** * @brief AES CCM encryption/decryption process in interrupt mode - * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation. + * for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status @@ -3427,6 +3838,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t lastwordsize; uint32_t npblb; uint32_t mode; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -3436,75 +3848,205 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) } #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + /* Configure Key, IV and process message (header and payload) */ + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /********************** Init phase ******************************************/ + /********************** Init phase ******************************************/ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector (IV) with B0 */ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); + /* Set the initialization vector (IV) with B0 */ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /* just wait for hash computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /***************************** Header phase *********************************/ + /***************************** Header phase *********************************/ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ - { - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - if (hcryp->Init.Algorithm == CRYP_AES_CCM) + if (hcryp->Init.Algorithm == CRYP_AES_CCM) + { + /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */ + hcryp->CrypHeaderCount++; + } + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 4 words : first block is the last block*/ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)hcryp->Size; + + mode = hcryp->Instance->CR & AES_CR_MODE; + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + } + else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */ { - /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */ + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; } + + } /* end of if (DoKeyIVConfig == 1U) */ + else /* Key and IV have already been configured, + header has already been processed; + only process here message payload */ + { /* Write the payload Input block in the IN FIFO */ if (hcryp->Size == 0U) { @@ -3577,40 +4119,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) } } } - else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */ - { - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - while (loopcounter < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - } - else - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - } /* Return function status */ return HAL_OK; } + /** * @brief AES CCM encryption/decryption process in DMA mode - * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation. + * for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status @@ -3623,69 +4139,98 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) uint32_t npblb; uint32_t lastwordsize; uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /********************** Init phase ******************************************/ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /********************** Init phase ******************************************/ - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the initialization vector (IV) with B0 */ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Set the initialization vector (IV) with B0 */ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); - /* just wait for hash computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /********************* Header phase *****************************************/ + /********************* Header phase *****************************************/ - if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) - { - return HAL_ERROR; - } + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } - /******************** Payload phase *****************************************/ + /******************** Payload phase *****************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + /* Select payload phase once the header phase is performed */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); - /* Select payload phase once the header phase is performed */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); + } /* if (DoKeyIVConfig == 1U) */ if (hcryp->Size == 0U) { @@ -3777,6 +4322,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; hcryp->CrypOutCount++; } + /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; @@ -3789,7 +4335,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) } /** - * @brief Sets the payload phase in iterrupt mode + * @brief Sets the payload phase in interrupt mode * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval state @@ -3824,8 +4370,13 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) outcount = hcryp->CrypOutCount; if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size)) { - /* Disable computation complete flag and errors interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); + + /* When in CCM with Key and IV configuration skipped, don't disable interruptions */ + if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U))) + { + /* Disable computation complete flag and errors interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); + } /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -3895,7 +4446,7 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { /* Compute the number of padding bytes in last block of payload */ npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size); - + mode = hcryp->Instance->CR & AES_CR_MODE; if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) @@ -4048,7 +4599,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u { if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { - /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/ + /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); /* Select header phase */ @@ -4455,7 +5006,7 @@ static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Outp __IO uint32_t count = 0U; /* In case of GCM payload phase encryption, check that suspension can be carried out */ - if (READ_BIT(hcryp->Instance->CR, (AES_CR_GCMPH|AES_CR_MODE)) == (AES_CR_GCMPH_1|0x0)) + if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0)) { /* Wait for BUSY flag to be cleared */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c index 8c0375ad581f7a708ab71543a71c1348933bc142..890c37997bd439873f6770610b910f291e590c1f 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c @@ -9,11 +9,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -100,7 +100,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u { uint32_t tickstart; uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */ - uint64_t inputlength = (uint64_t)hcryp->Size * 8U; /* input length in bits */ + uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */ uint32_t tagaddr = (uint32_t)AuthTag; if (hcryp->State == HAL_CRYP_STATE_READY) @@ -139,7 +139,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Set the encrypt operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - /*TinyAES IP from V3.1.1 : data has to be inserted normally (no swapping)*/ + /*TinyAES peripheral from V3.1.1 : data has to be inserted normally (no swapping)*/ /* Write into the AES_DINR register the number of bits in header (64 bits) followed by the number of bits in the payload */ @@ -220,6 +220,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Process locked */ __HAL_LOCK(hcryp); + /* Disable interrupts in case they were kept enabled to proceed + a single message in several iterations */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); + /* Change the CRYP peripheral state */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -318,7 +322,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u ============================================================================== [..] This section provides functions allowing to Enable or Disable the the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure - These function are allowed only in TinyAES IP. + These function are allowed only in TinyAES peripheral. @endverbatim * @{ */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c index b4cfb2c5211f950f7280e11dd3663c320bff98c9..62ba4d7601fa848bf8565a872ce761f6783e6d54 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c @@ -102,8 +102,6 @@ & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime, DAC_HoldTime & DAC_RefreshTime; - - *** DAC calibration feature *** =================================== [..] @@ -192,6 +190,7 @@ [..] (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length of data to be transferred at each end of conversion + First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue(). (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() @@ -263,8 +262,6 @@ not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. - - *** DAC HAL driver macros list *** ============================================= [..] @@ -282,11 +279,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -320,19 +317,9 @@ * @} */ -/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup DAC_Private_Functions DAC Private Functions - * @{ - */ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); -/** - * @} - */ /* Exported functions -------------------------------------------------------*/ /** @defgroup DAC_Exported_Functions DAC Exported Functions @@ -340,8 +327,8 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); */ /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -498,8 +485,8 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) */ /** @defgroup DAC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * + * @brief IO operation functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -542,7 +529,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) if (Channel == DAC_CHANNEL_1) { /* Check if software trigger enabled */ - if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1) + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); @@ -551,7 +538,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) else { /* Check if software trigger enabled */ - if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2) + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << Channel)) { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); @@ -610,7 +597,8 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment) +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, + uint32_t Alignment) { HAL_StatusTypeDef status; uint32_t tmpreg = 0U; @@ -960,8 +948,8 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) */ /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * + * @brief Peripheral Control functions + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -1013,7 +1001,8 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { - uint32_t tmpreg1, tmpreg2; + uint32_t tmpreg1; + uint32_t tmpreg2; uint32_t tickstart = 0U; /* Check the DAC parameters */ @@ -1137,7 +1126,6 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; - /* Disable wave generation */ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL)); @@ -1156,8 +1144,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf */ /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * + * @brief Peripheral State and Errors functions + * @verbatim ============================================================================== ##### Peripheral State and Errors functions ##### @@ -1226,13 +1214,14 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID - * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID - * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID + * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID * * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, + pDAC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1274,10 +1263,10 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call case HAL_DAC_CH2_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh2 = pCallback; break; - case HAL_DAC_MSP_INIT_CB_ID : + case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = pCallback; break; - case HAL_DAC_MSP_DEINIT_CB_ID : + case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = pCallback; break; default : @@ -1292,10 +1281,10 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call { switch (CallbackID) { - case HAL_DAC_MSP_INIT_CB_ID : + case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = pCallback; break; - case HAL_DAC_MSP_DEINIT_CB_ID : + case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = pCallback; break; default : @@ -1333,8 +1322,8 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID - * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID - * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID + * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks * @retval status */ @@ -1373,10 +1362,10 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca case HAL_DAC_CH2_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; break; - case HAL_DAC_MSP_INIT_CB_ID : + case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = HAL_DAC_MspInit; break; - case HAL_DAC_MSP_DEINIT_CB_ID : + case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = HAL_DAC_MspDeInit; break; case HAL_DAC_ALL_CB_ID : @@ -1403,10 +1392,10 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca { switch (CallbackID) { - case HAL_DAC_MSP_INIT_CB_ID : + case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = HAL_DAC_MspInit; break; - case HAL_DAC_MSP_DEINIT_CB_ID : + case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = HAL_DAC_MspDeInit; break; default : @@ -1449,7 +1438,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) +void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -1468,7 +1457,7 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) +void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Conversion complete callback */ @@ -1485,7 +1474,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) +void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c index 6816ed6e852879173a93c1087c80dc081b0266d5..5c400d239badd04eb7e0b135db55f886bdd87990 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c @@ -12,9 +12,15 @@ ##### How to use this driver ##### ============================================================================== [..] + *** Dual mode IO operation *** + ============================== (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : Use HAL_DACEx_DualGetValue() to get digital data to be converted and use - HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. + HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in + Channel 1 and Channel 2. + + *** Signal generation operation *** + =================================== (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. @@ -28,11 +34,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -68,8 +74,8 @@ */ /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions - * @brief Extended IO operation functions - * + * @brief Extended IO operation functions + * @verbatim ============================================================================== ##### Extended features functions ##### @@ -201,7 +207,8 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t */ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) { - uint32_t data, tmp; + uint32_t data; + uint32_t tmp; /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); @@ -435,7 +442,8 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue) +HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, + uint32_t NewTrimmingValue) { HAL_StatusTypeDef status = HAL_OK; @@ -491,8 +499,8 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) */ /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions - * @brief Extended Peripheral Control functions - * + * @brief Extended Peripheral Control functions + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -532,7 +540,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) /* Private functions ---------------------------------------------------------*/ /** @defgroup DACEx_Private_Functions DACEx private functions - * @brief Extended private functions + * @brief Extended private functions * @{ */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c index 368292d530c5bf483999d4cfd06c18b8938c1a90..7e828f0c2e4b3703590c47ff49d539788543a170 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c @@ -220,12 +220,6 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) hdma->DMAmuxRequestGenStatusMask = 0U; } - /* Clean callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -293,6 +287,12 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->DMAmuxRequestGen = 0U; hdma->DMAmuxRequestGenStatus = 0U; hdma->DMAmuxRequestGenStatusMask = 0U; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c index fb8a45d4f8b01a7579da80d4e2cf3144ef40ce34..a3d5d1961eb9961eb654d4b4ca6a9bc166471121 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c @@ -55,7 +55,7 @@ (#) Option bytes management functions : (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and HAL_FLASH_OB_Lock() functions - (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function. + (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function. In this case, a reset is generated [..] @@ -73,11 +73,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -108,13 +108,13 @@ /** * @brief Variable used for Program/Erase sectors under interruption */ -extern FLASH_ProcessTypeDef pFlash; FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ .ErrorCode = HAL_FLASH_ERROR_NONE, \ .ProcedureOnGoing = FLASH_TYPENONE, \ .Address = 0U, \ .Page = 0U, \ - .NbPagesToErase = 0U}; + .NbPagesToErase = 0U + }; /** * @} */ @@ -123,8 +123,6 @@ FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ /** @defgroup FLASH_Private_Functions FLASH Private Functions * @{ */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -extern void FLASH_PageErase(uint32_t Page); static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); /** @@ -155,10 +153,10 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); * @brief Program double word or fast program of a row at a specified address. * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed * This parameter is the data for the double word program and the address where - * are stored the data for the row fast program + * are stored the data for the row fast program. * * @retval HAL_StatusTypeDef HAL Status */ @@ -168,6 +166,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); /* Process Locked */ __HAL_LOCK(&pFlash); @@ -201,8 +200,8 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG or FSTPG Bit */ - CLEAR_BIT(FLASH->CR, TypeProgram); - } + CLEAR_BIT(FLASH->CR, TypeProgram); + } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); @@ -211,15 +210,14 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint return status; } - /** * @brief Program double word or fast program of a row at a specified address with interrupt enabled. * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed * This parameter is the data for the double word program and the address where - * are stored the data for the row fast program + * are stored the data for the row fast program. * * @retval HAL Status */ @@ -229,6 +227,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); /* Process Locked */ __HAL_LOCK(&pFlash); @@ -275,31 +274,30 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u return status; } - /** * @brief Handle FLASH interrupt request. * @retval None */ void HAL_FLASH_IRQHandler(void) { - uint32_t param = 0xFFFFFFFFu; + uint32_t param = 0xFFFFFFFFU; uint32_t error; - /* save flash errors. Only ECC detection can be checked here as ECCC + /* Save flash errors. Only ECC detection can be checked here as ECCC generates NMI */ error = (FLASH->SR & FLASH_FLAG_SR_ERROR); error |= (FLASH->ECCR & FLASH_FLAG_ECCC); CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing); - + /* A] Set parameter for user or error callbacks */ /* check operation was a program or erase */ - if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0x00u) + if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0x00U) { /* return adress being programmed */ param = pFlash.Address; } - else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASS | FLASH_TYPEERASE_PAGES)) != 0x00u) + else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASS | FLASH_TYPEERASE_PAGES)) != 0x00U) { /* return page number being erased (0 for mass erase) */ param = pFlash.Page; @@ -310,14 +308,13 @@ void HAL_FLASH_IRQHandler(void) } /* B] Check errors */ - if (error != 0x00u) + if (error != 0x00U) { /*Save the error code*/ pFlash.ErrorCode |= error; /* clear error flags */ - FLASH->SR = FLASH_FLAG_SR_ERROR; - FLASH->ECCR |= FLASH_FLAG_ECCC; + __HAL_FLASH_CLEAR_FLAG(error); /*Stop the procedure ongoing*/ pFlash.ProcedureOnGoing = FLASH_TYPENONE; @@ -327,7 +324,7 @@ void HAL_FLASH_IRQHandler(void) } /* C] Check FLASH End of Operation flag */ - if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != 0x00u) + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != 0x00U) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); @@ -338,7 +335,7 @@ void HAL_FLASH_IRQHandler(void) pFlash.NbPagesToErase--; /* Check if there are still pages to erase*/ - if (pFlash.NbPagesToErase != 0x00u) + if (pFlash.NbPagesToErase != 0x00U) { /* Increment page number */ pFlash.Page++; @@ -363,14 +360,13 @@ void HAL_FLASH_IRQHandler(void) if (pFlash.ProcedureOnGoing == FLASH_TYPENONE) { /* Disable End of Operation and Error interrupts */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR | FLASH_IT_ECCC); /* Process Unlocked */ __HAL_UNLOCK(&pFlash); } } - /** * @brief FLASH end of operation interrupt callback. * @param ReturnValue The value saved in this parameter depends on the ongoing procedure @@ -389,7 +385,6 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) */ } - /** * @brief FLASH operation error interrupt callback. * @param ReturnValue The value saved in this parameter depends on the ongoing procedure @@ -435,14 +430,14 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { HAL_StatusTypeDef status = HAL_OK; - if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u) + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); /* verify Flash is unlock */ - if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u) + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) { status = HAL_ERROR; } @@ -451,7 +446,6 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void) return status; } - /** * @brief Lock the FLASH control register access. * @retval HAL Status @@ -463,7 +457,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); - /* verify Flash is lock */ + /* verify Flash is locked */ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u) { status = HAL_OK; @@ -472,7 +466,6 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) return status; } - /** * @brief Unlock the FLASH Option Bytes Registers access. * @retval HAL Status @@ -481,14 +474,14 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { HAL_StatusTypeDef status = HAL_ERROR; - if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00u) + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00U) { /* Authorizes the Option Byte register programming */ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); - /* verify option bytes are unlock */ - if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0x00u) + /* verify option bytes are unlocked */ + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0x00U) { status = HAL_OK; } @@ -497,7 +490,6 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) return status; } - /** * @brief Lock the FLASH Option Bytes Registers access. * @retval HAL Status @@ -509,7 +501,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); - /* verify option bytes are lock */ + /* verify option bytes are locked */ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00u) { status = HAL_OK; @@ -518,7 +510,6 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) return status; } - /** * @brief Launch the option byte loading. * @retval HAL Status @@ -553,24 +544,19 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) /** * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode: The returned value can be: - * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)(*) - * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag - * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag - * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag - * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag - * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag - * @arg HAL_FLASH_ERROR_NONE: No error set - * @arg HAL_FLASH_ERROR_OP: FLASH Operation error - * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error - * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error - * @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error - * @arg HAL_FLASH_ERROR_SIZ: FLASH Size error - * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error - * @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error - * @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error - * @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error - * @arg HAL_FLASH_ERROR_ECCC: FLASH on ECC error have been detected and corrected + * @retval FLASH_ErrorCode The returned value can be + * @arg @ref HAL_FLASH_ERROR_NONE No error set + * @arg @ref HAL_FLASH_ERROR_OP FLASH Operation error + * @arg @ref HAL_FLASH_ERROR_PROG FLASH Programming error + * @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protection error + * @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming alignment error + * @arg @ref HAL_FLASH_ERROR_SIZ FLASH Size error + * @arg @ref HAL_FLASH_ERROR_PGS FLASH Programming sequence error + * @arg @ref HAL_FLASH_ERROR_MIS FLASH Fast programming data miss error + * @arg @ref HAL_FLASH_ERROR_FAST FLASH Fast programming error + * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error (PCROP)(*) + * @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option validity error + * @arg @ref HAL_FLASH_ERROR_ECCD FLASH two ECC errors have been detected * @note (*) availability depends on devices */ uint32_t HAL_FLASH_GetError(void) @@ -600,35 +586,41 @@ uint32_t HAL_FLASH_GetError(void) HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { uint32_t error; + uint32_t eccerr; /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t timeout = HAL_GetTick() + Timeout; /* Wait if any operation is ongoing */ - while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != 0x00u) + while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != 0x00U) { - if (Timeout != HAL_MAX_DELAY) + if (HAL_GetTick() >= timeout) { - if (HAL_GetTick() >= timeout) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } /* check flash errors. Only ECC correction can be checked here as ECCD generates NMI */ error = (FLASH->SR & FLASH_FLAG_SR_ERROR); - error |= (FLASH->ECCR & FLASH_FLAG_ECCC); - if (error != 0x00u) + + /* Clear SR register */ + FLASH->SR = FLASH_FLAG_SR_CLEAR; + + /* Update error with ECC error value */ + eccerr = (FLASH->ECCR & FLASH_FLAG_ECCC); + + if(eccerr != 0x00u) { - /*Save the error code*/ - pFlash.ErrorCode |= error; + FLASH->ECCR |= eccerr; + error |= eccerr; + } - /* clear error flags */ - FLASH->SR = FLASH_FLAG_SR_ERROR; - FLASH->ECCR |= FLASH_FLAG_ECCC; + if (error != 0x00U) + { + /*Save the error code*/ + pFlash.ErrorCode = error; return HAL_ERROR; } @@ -636,25 +628,21 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) /* Wait for control register to be written */ timeout = HAL_GetTick() + Timeout; - while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_CFGBSY) != 0x00u) + while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_CFGBSY) != 0x00U) { - if (Timeout != HAL_MAX_DELAY) + if (HAL_GetTick() >= timeout) { - if (HAL_GetTick() >= timeout) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } return HAL_OK; } - /** * @brief Program double-word (64-bit) at a specified address. - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed. + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed. * @retval None */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) @@ -662,16 +650,21 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) /* Set PG bit */ SET_BIT(FLASH->CR, FLASH_CR_PG); - /* Program the double word */ + /* Program first word */ *(uint32_t *)Address = (uint32_t)Data; - *(uint32_t *)(Address + 4u) = (uint32_t)(Data >> 32u); -} + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ + *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U); +} /** * @brief Fast program a 32 row double-word (64-bit) at a specified address. - * @param Address specifies the address to be programmed. - * @param DataAddress specifies the address where the data are stored. + * @param Address Specifies the address to be programmed. + * @param DataAddress Specifies the address where the data are stored. * @retval None */ static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) @@ -689,18 +682,18 @@ static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress __disable_irq(); /* Fast Program : 64 words */ - while (index < 64u) + while (index < 64U) { *(uint32_t *)dest = *(uint32_t *)src; - src += 4u; - dest += 4u; + src += 4U; + dest += 4U; index++; } /* wait for BSY1 in order to be sure that flash operation is ended befoire allowing prefetch in flash. Timeout does not return status, as it will be anyway done later */ - while((FLASH->SR & FLASH_SR_BSY1) != 0x00u) + while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U) { } diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c index 35865a23fb588c5fdc6911712e6b4d11ffc445bf..2ef362ee30b7a1a6f0d6da69178d8ece8777ed83 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c @@ -58,11 +58,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -77,7 +77,7 @@ */ /** @defgroup FLASHEx FLASHEx - * @brief FALSH Extended HAL module driver + * @brief FLASH Extended HAL module driver * @{ */ @@ -87,20 +87,10 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables - * @{ - */ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions * @{ */ -extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_PageErase(uint32_t Page); static void FLASH_MassErase(void); void FLASH_FlushCaches(void); static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); @@ -145,12 +135,11 @@ static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecS @endverbatim * @{ */ - /** * @brief Perform a mass erase or erase the specified FLASH memory pages. - * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. - * @param[out] PageError pointer to variable that contains the configuration + * @param[out] PageError Pointer to variable that contains the configuration * information on faulty page in case of error (0xFFFFFFFF means that all * the pages have been correctly erased) * @retval HAL Status @@ -185,7 +174,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t else { /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFFu; + *PageError = 0xFFFFFFFFU; for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++) { @@ -218,7 +207,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /** * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. - * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * @retval HAL Status */ @@ -274,15 +263,14 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) return status; } - /** * @brief Program Option bytes. - * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that * contains the configuration information for the programming. * @note To configure any option bytes, the option lock bit OPTLOCK must be - * cleared with the call of HAL_FLASH_OB_Unlock() function. + * cleared with the call of @ref HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account only - * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() + * - after an option bytes launch through the call of @ref HAL_FLASH_OB_Launch() * - a Power On Reset * - an exit from Standby or Shutdown mode. * @retval HAL Status @@ -301,7 +289,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Write protection configuration */ - if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0x00u) + if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0x00U) { /* Configure of Write protection on the selected area */ FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset); @@ -313,13 +301,13 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) /* Fully modify OPTR register with RDP & user datas */ FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, pOBInit->RDPLevel); } - else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0x00u) + else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0x00U) { /* Only modify RDP so get current user data */ optr = FLASH_OB_GetUser(); FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel); } - else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0x00u) + else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0x00U) { /* Only modify user so get current RDP level */ optr = FLASH_OB_GetRDP(); @@ -332,18 +320,18 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) #if defined(FLASH_PCROP_SUPPORT) /* PCROP Configuration */ - if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0x00u) + if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0x00U) { /* Check the parameters */ assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig)); - if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0x00u) + if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0x00U) { /* Configure the 1A Proprietary code readout protection */ FLASH_OB_PCROP1AConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAddr); } - if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0x00u) + if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0x00U) { /* Configure the 1B Proprietary code readout protection */ FLASH_OB_PCROP1BConfig(pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr); @@ -352,7 +340,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) #endif #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) /* Securable Memory Area Configuration */ - if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0x00u) + if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0x00U) { /* Configure the securable memory area protection */ FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize); @@ -381,16 +369,15 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) return status; } - /** * @brief Get the Option bytes configuration. * @note warning: this API only read flash register, it does not reflect any * change that would have been programmed between previous Option byte * loading and current call. - * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that contains the * configuration information. The fields pOBInit->WRPArea and * pOBInit->PCROPConfig should indicate which area is requested - * for the WRP and PCROP + * for the WRP and PCROP. * @retval None */ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) @@ -510,12 +497,10 @@ void HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank) */ static void FLASH_MassErase(void) { - /* Set the Mass Erase Bit, then Start bit */ + /* Set the Mass Erase Bit and start bit */ FLASH->CR |= (FLASH_CR_STRT | FLASH_CR_MER1); - } - /** * @brief Erase the specified FLASH memory page. * @param Page FLASH page to erase @@ -526,6 +511,9 @@ void FLASH_PageErase(uint32_t Page) { uint32_t tmp; + /* Check the parameters */ + assert_param(IS_FLASH_PAGE(Page)); + /* Get configuration register, then clear page number */ tmp = (FLASH->CR & ~FLASH_CR_PNB); @@ -533,7 +521,6 @@ void FLASH_PageErase(uint32_t Page) FLASH->CR = (tmp | (FLASH_CR_STRT | (Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER)); } - /** * @brief Flush the instruction cache. * @retval None @@ -562,15 +549,15 @@ void FLASH_FlushCaches(void) * it is not possible to program or erase Flash memory if the CPU debug * features are connected (JTAG or single wire) or boot code is being * executed from RAM or System flash, even if WRP is not activated. - * @param WRPArea specifies the area to be configured. + * @param WRPArea Specifies the area to be configured. * This parameter can be one of the following values: - * @arg OB_WRPAREA_ZONE_A: Flash Zone A - * @arg OB_WRPAREA_ZONE_B: Flash Zone B - * @param WRPStartOffset specifies the start page of the write protected area - * This parameter is a page number between 0 and (max number of pages in Flash - 1) - * @param WRDPEndOffset specifies the end page of the write protected area - * This parameter is a be page number between WRPStartOffset and (max number of pages in Flash - 1) - * @retval HAL Status + * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A + * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B + * @param WRPStartOffset Specifies the start page of the write protected area + * This parameter can be page number between 0 and (max number of pages in the Flash - 1) + * @param WRDPEndOffset Specifies the end page of the write protected area + * This parameter can be page number between WRPStartOffset and (max number of pages in the Flash - 1) + * @retval None */ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) { @@ -590,14 +577,13 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32 } } - /** - * @brief Set user & RDP configiuration + * @brief Set user & RDP configuration * @note !!! Warning : When enabling OB_RDP level 2 it is no more possible * to go back to level 1 or 0 !!! - * @param UserType User Option Bytes to be modified. + * @param UserType The FLASH User Option Bytes to be modified. * This parameter can be a combination of @ref FLASH_OB_USER_Type - * @param UserConfig The selected user option Bytes values. + * @param UserConfig The FLASH User Option Bytes values. * This parameter can be a combination of: * @arg @ref FLASH_OB_USER_BOR_ENABLE(*), * @arg @ref FLASH_OB_USER_BOR_LEVEL(*), @@ -616,11 +602,11 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32 * @arg @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*) * @param RDPLevel specifies the read protection level. * This parameter can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Memory Read protection - * @arg OB_RDP_LEVEL_2: Full chip protection + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Memory Read protection + * @arg @ref OB_RDP_LEVEL_2 Full chip protection * @note (*) availability depends on devices - * @retval HAL status + * @retval None */ static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel) { @@ -647,11 +633,11 @@ static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t * has to be set to 512 Bytes * @param PCROPConfig specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE) * on RDP level 1 regression. - * @param PCROP1AStartAddr specifies the start address of the 1A Proprietary code readout protection + * @param PCROP1AStartAddr Specifies the Zone 1A Start address of the Proprietary code readout protection * This parameter can be an address between begin and end of the flash - * @param PCROP1AEndAddr specifies the end address of the 1A Proprietary code readout protection + * @param PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protection * This parameter can be an address between PCROP1AStartAddr and end of the flash - * @retval HAL Status + * @retval None */ static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr) { @@ -668,7 +654,7 @@ static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAd pcrop1aend = FLASH->PCROP1AER; /* Configure the Proprietary code readout protection offset */ - if ((PCROPConfig & OB_PCROP_ZONE_A) != 0x00u) + if ((PCROPConfig & OB_PCROP_ZONE_A) != 0x00U) { /* Compute offset depending on pcrop granularity */ startoffset = ((PCROP1AStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); @@ -683,7 +669,7 @@ static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAd } /* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */ - if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0x00u) + if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0x00U) { pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP; } @@ -692,7 +678,6 @@ static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAd FLASH->PCROP1AER = pcrop1aend; } - /** * @brief Configure the 1B Proprietary code readout protection. * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid @@ -700,11 +685,11 @@ static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAd * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END. * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity * has to be set to 512 Bytes - * @param PCROP1BStartAddr specifies the start address of the 1B Proprietary code readout protection - * This parameter can be an address between begin and end of the bank - * @param PCROP1BEndAddr specifies the end address of the 1B Proprietary code readout protection - * This parameter can be an address between PCROP1BStartAddr and end of the bank - * @retval HAL Status + * @param PCROP1BStartAddr Specifies the Zone 1B Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP1BEndAddr Specifies the Zone 1B end address of the Proprietary code readout protection + * This parameter can be an address between PCROP1BStartAddr and end of the flash + * @retval None */ static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr) { @@ -735,7 +720,7 @@ static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEn * @arg @ref OB_BOOT_ENTRY_FORCED_FLASH FLash selected as unique entry boot * @param SecSize specifies number of pages to protect as securable memory area, starting from * beginning of the Flash (page 0). - * @retval HAL Status + * @retval None */ static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize) { @@ -754,13 +739,13 @@ static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize) /** * @brief Return the FLASH Write Protection Option Bytes value. - * @param[in] WRPArea specifies the area to be returned. + * @param[in] WRPArea Specifies the area to be returned. * This parameter can be one of the following values: * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B - * @param[out] WRPStartOffset specifies the address where to copied the start page + * @param[out] WRPStartOffset Specifies the address where to copied the start page * of the write protected area - * @param[out] WRDPEndOffset specifies the address where to copied the end page of + * @param[out] WRDPEndOffset Dpecifies the address where to copied the end page of * the write protected area * @retval None */ @@ -786,9 +771,9 @@ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t * @brief Return the FLASH Read Protection level. * @retval FLASH ReadOut Protection Status: * This return value can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection */ static uint32_t FLASH_OB_GetRDP(void) { @@ -804,10 +789,9 @@ static uint32_t FLASH_OB_GetRDP(void) } } - /** * @brief Return the FLASH User Option Byte value. - * @retval The FLASH User Option Bytes values. It will be a combination of + * @retval The FLASH User Option Bytes values. It will be a combination of all the following values: * @ref FLASH_OB_USER_BOR_ENABLE(*), * @ref FLASH_OB_USER_BOR_LEVEL(*), * @ref FLASH_OB_USER_RESET_CONFIG(*), @@ -835,9 +819,9 @@ static uint32_t FLASH_OB_GetUser(void) /** * @brief Return the FLASH PCROP Protection Option Bytes value. * @param PCROPConfig [out] specifies the configuration of PCROP_RDP option. - * @param PCROP1AStartAddr [out] specifies the address where to copied the start address + * @param PCROP1AStartAddr [out] Specifies the address where to copied the start address * of the 1A Proprietary code readout protection - * @param PCROP1AEndAddr [out] specifies the address where to copied the end address of + * @param PCROP1AEndAddr [out] Specifies the address where to copied the end address of * the 1A Proprietary code readout protection * @retval None */ @@ -851,7 +835,7 @@ static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAdd pcrop = FLASH->PCROP1AER; *PCROP1AEndAddr = ((pcrop & FLASH_PCROP1AER_PCROP1A_END) << FLASH_PCROP_GRANULARITY_OFFSET); - *PCROP1AEndAddr += (FLASH_BASE + FLASH_PCROP_GRANULARITY - 1u); + *PCROP1AEndAddr += (FLASH_BASE + FLASH_PCROP_GRANULARITY - 1U); *PCROPConfig &= ~OB_PCROP_RDP_ERASE; *PCROPConfig |= (pcrop & FLASH_PCROP1AER_PCROP_RDP); @@ -860,9 +844,9 @@ static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAdd /** * @brief Return the FLASH PCROP Protection Option Bytes value. - * @param PCROP1BStartAddr [out] specifies the address where to copied the start address + * @param PCROP1BStartAddr [out] Specifies the address where to copied the start address * of the 1B Proprietary code readout protection - * @param PCROP1BEndAddr [out] specifies the address where to copied the end address of + * @param PCROP1BEndAddr [out] Specifies the address where to copied the end address of * the 1B Proprietary code readout protection * @retval None */ @@ -876,7 +860,7 @@ static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEnd pcrop = (FLASH->PCROP1BER & FLASH_PCROP1BER_PCROP1B_END); *PCROP1BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); - *PCROP1BEndAddr += (FLASH_BASE + FLASH_PCROP_GRANULARITY - 1u); + *PCROP1BEndAddr += (FLASH_BASE + FLASH_PCROP_GRANULARITY - 1U); } #endif diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c index d12bf0307bd6ed4b96c3cb89e58ceb3a8a1183a1..e5e0d90c7652fd3fa9ef8930de2e776502db4ee8 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c @@ -314,9 +314,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) tmp &= (0x0FuL << (8u * (position & 0x03u))); if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)))) { - tmp = 0x0FuL << (8u * (position & 0x03u)); - EXTI->EXTICR[position >> 2u] &= ~tmp; - /* Clear EXTI line configuration */ EXTI->IMR1 &= ~(iocurrent); EXTI->EMR1 &= ~(iocurrent); @@ -324,6 +321,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Clear Rising Falling edge configuration */ EXTI->RTSR1 &= ~(iocurrent); EXTI->FTSR1 &= ~(iocurrent); + + tmp = 0x0FuL << (8u * (position & 0x03u)); + EXTI->EXTICR[position >> 2u] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ @@ -432,13 +432,13 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin) + if ((GPIOx->ODR & GPIO_Pin) != 0x00u) { - GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; + GPIOx->BRR = (uint32_t)GPIO_Pin; } else { - GPIOx->BSRR = GPIO_Pin; + GPIOx->BSRR = (uint32_t)GPIO_Pin; } } @@ -469,9 +469,10 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) GPIOx->LCKR = GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; - /* Read LCKK bit*/ + /* Read LCKK register. This read is mandatory to complete key lock sequence */ tmp = GPIOx->LCKR; + /* read again in order to confirm lock is active */ if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) { return HAL_OK; @@ -514,7 +515,7 @@ __weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file + the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file */ } @@ -529,7 +530,7 @@ __weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file + the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file */ } diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c index cb19b73d09759f7a1ef5853977657f9118ac6af1..9f3f3aa003bef849b24016c163a71d17489f684a 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c @@ -223,12 +223,12 @@ *** Callback registration *** ============================================= - + [..] The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() to register an interrupt callback. - + [..] Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. @@ -243,9 +243,9 @@ (+) MspDeInitCallback : callback for Msp DeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - + [..] For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). - + [..] Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default weak function. @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, @@ -262,9 +262,9 @@ (+) AbortCpltCallback : callback for abort completion process. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. - + [..] For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). - + [..] By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). @@ -273,7 +273,7 @@ these callbacks are null (not registered beforehand). If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - + [..] Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, @@ -281,7 +281,7 @@ Then, the user first registers the MspInit/MspDeInit user callbacks using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() or @ref HAL_I2C_Init() function. - + [..] When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @@ -4595,11 +4595,12 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; /* Process Locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4612,8 +4613,11 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; @@ -4623,7 +4627,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; @@ -4634,7 +4638,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { @@ -4674,7 +4678,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -4705,10 +4709,10 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Nothing to do */ } - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); + I2C_ITMasterCplt(hi2c, tmpITFlags); } /* Process Unlocked */ @@ -4728,11 +4732,12 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; /* Process locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -4743,7 +4748,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); + I2C_ITListenCplt(hi2c, tmpITFlags); } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) { @@ -4779,10 +4784,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { if (hi2c->XferCount > 0U) { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; @@ -4800,11 +4808,11 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint I2C_ITSlaveSeqCplt(hi2c); } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { - I2C_ITAddrCplt(hi2c, ITFlags); + I2C_ITAddrCplt(hi2c, tmpITFlags); } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ @@ -4837,10 +4845,10 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); + I2C_ITSlaveCplt(hi2c, tmpITFlags); } /* Process Unlocked */ @@ -5012,18 +5020,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Split check of hdmarx, for MISRA compliance */ if (hi2c->hdmarx != NULL) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) { - treatdmanack = 1U; + if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } } } /* Split check of hdmatx, for MISRA compliance */ if (hi2c->hdmatx != NULL) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) { - treatdmanack = 1U; + if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } } } @@ -5532,6 +5546,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -5569,8 +5584,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } /* Store Last receive data if any */ - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; @@ -5604,11 +5622,14 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) if (hi2c->State == HAL_I2C_STATE_LISTEN) { /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); + I2C_ITListenCplt(hi2c, tmpITFlags); } } else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { + /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */ + I2C_ITSlaveSeqCplt(hi2c); + hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2s.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2s.c index 7c18f17ea30438f2860f2aabac361ead5c45bf78..86d363d4f6e02b8ee693b60c73fbd2d1f5ff056d 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2s.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2s.c @@ -156,7 +156,7 @@ using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit() or HAL_I2S_Init() function. - When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. @@ -205,7 +205,7 @@ static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void I2S_DMAError(DMA_HandleTypeDef *hdma); static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout); /** * @} @@ -254,8 +254,11 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, */ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) { - uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 16U; - uint32_t tmp = 0U, i2sclk = 0U; + uint32_t i2sdiv; + uint32_t i2sodd; + uint32_t packetlength; + uint32_t tmp; + uint32_t i2sclk; /* Check the I2S handle allocation */ if (hi2s == NULL) @@ -739,13 +742,6 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tmpreg_cfgr; - HAL_StatusTypeDef errorcode = HAL_OK; - - if (hi2s->State != HAL_I2S_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -755,6 +751,12 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin /* Process Locked */ __HAL_LOCK(hi2s); + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -773,6 +775,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin hi2s->TxXferCount = Size; } + tmpreg_cfgr = hi2s->Instance->I2SCFGR; + /* Check if the I2S is already enabled */ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) { @@ -785,13 +789,15 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin { /* Set the error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - errorcode = HAL_ERROR; - goto error; + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; } while (hi2s->TxXferCount > 0U) { - hi2s->Instance->DR = (*pData++); + hi2s->Instance->DR = (*hi2s->pTxBuffPtr); + hi2s->pTxBuffPtr++; hi2s->TxXferCount--; /* Wait until TXE flag is set */ @@ -799,8 +805,9 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin { /* Set the error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - errorcode = HAL_ERROR; - goto error; + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; } /* Check if an underrun occurs */ @@ -815,27 +822,22 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin } /* Check if Slave mode is selected */ - if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) + if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) { /* Wait until Busy flag is reset */ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK) { /* Set the error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - errorcode = HAL_ERROR; - goto error; + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; } } - if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE) - { - errorcode = HAL_ERROR; - } - -error : hi2s->State = HAL_I2S_STATE_READY; __HAL_UNLOCK(hi2s); - return errorcode; + return HAL_OK; } /** @@ -858,13 +860,6 @@ error : HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tmpreg_cfgr; - HAL_StatusTypeDef errorcode = HAL_OK; - - if (hi2s->State != HAL_I2S_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -874,6 +869,12 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint /* Process Locked */ __HAL_LOCK(hi2s); + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -915,11 +916,13 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint { /* Set the error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - errorcode = HAL_ERROR; - goto error; + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; } - (*pData++) = hi2s->Instance->DR; + (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; + hi2s->pRxBuffPtr++; hi2s->RxXferCount--; /* Check if an overrun occurs */ @@ -933,15 +936,9 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint } } - if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE) - { - errorcode = HAL_ERROR; - } - -error : hi2s->State = HAL_I2S_STATE_READY; __HAL_UNLOCK(hi2s); - return errorcode; + return HAL_OK; } /** @@ -961,13 +958,6 @@ error : HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { uint32_t tmpreg_cfgr; - HAL_StatusTypeDef errorcode = HAL_OK; - - if (hi2s->State != HAL_I2S_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -977,6 +967,12 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, /* Process Locked */ __HAL_LOCK(hi2s); + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1005,9 +1001,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, __HAL_I2S_ENABLE(hi2s); } -error : __HAL_UNLOCK(hi2s); - return errorcode; + return HAL_OK; } /** @@ -1022,20 +1017,13 @@ error : * the Size parameter means the number of 16-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). - * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation + * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization * between Master and Slave otherwise the I2S interrupt should be optimized. * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { uint32_t tmpreg_cfgr; - HAL_StatusTypeDef errorcode = HAL_OK; - - if (hi2s->State != HAL_I2S_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -1045,6 +1033,12 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u /* Process Locked */ __HAL_LOCK(hi2s); + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1073,9 +1067,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u __HAL_I2S_ENABLE(hi2s); } -error : __HAL_UNLOCK(hi2s); - return errorcode; + return HAL_OK; } /** @@ -1095,13 +1088,6 @@ error : HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { uint32_t tmpreg_cfgr; - HAL_StatusTypeDef errorcode = HAL_OK; - - if (hi2s->State != HAL_I2S_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -1111,6 +1097,12 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /* Process Locked */ __HAL_LOCK(hi2s); + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1139,7 +1131,15 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, hi2s->hdmatx->XferErrorCallback = I2S_DMAError; /* Enable the Tx DMA Stream/Channel */ - HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize)) + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } /* Check if the I2S is already enabled */ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) @@ -1155,9 +1155,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); } -error : __HAL_UNLOCK(hi2s); - return errorcode; + return HAL_OK; } /** @@ -1177,13 +1176,6 @@ error : HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { uint32_t tmpreg_cfgr; - HAL_StatusTypeDef errorcode = HAL_OK; - - if (hi2s->State != HAL_I2S_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -1193,6 +1185,12 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /* Process Locked */ __HAL_LOCK(hi2s); + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1229,7 +1227,15 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, } /* Enable the Rx DMA Stream/Channel */ - HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize); + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize)) + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } /* Check if the I2S is already enabled */ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) @@ -1245,9 +1251,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); } -error : __HAL_UNLOCK(hi2s); - return errorcode; + return HAL_OK; } /** @@ -1307,6 +1312,7 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) { /* nothing to do */ } + /* If the I2S peripheral is still not enabled, enable it */ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) { @@ -1328,8 +1334,12 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) */ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) { - /* Process Locked */ - __HAL_LOCK(hi2s); + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() + when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() + */ /* Disable the I2S Tx/Rx DMA requests */ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); @@ -1339,16 +1349,22 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) if (hi2s->hdmatx != NULL) { /* Disable the I2S DMA tx Stream/Channel */ - __HAL_DMA_DISABLE(hi2s->hdmatx); - HAL_DMA_Abort(hi2s->hdmatx); + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } } /* Abort the I2S DMA rx Stream/Channel */ if (hi2s->hdmarx != NULL) { - /* Disable the I2S DMA Stream/Channel */ - __HAL_DMA_DISABLE(hi2s->hdmarx); - HAL_DMA_Abort(hi2s->hdmarx); + /* Disable the I2S DMA rx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } } /* Disable I2S peripheral */ @@ -1356,10 +1372,7 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) hi2s->State = HAL_I2S_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; + return errorcode; } /** @@ -1370,28 +1383,29 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) */ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) { - uint32_t i2ssr = hi2s->Instance->SR; + uint32_t itsource = hi2s->Instance->CR2; + uint32_t itflag = hi2s->Instance->SR; /* I2S in mode Receiver ------------------------------------------------*/ - if (((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) && - ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) + if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) && + (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET)) { I2S_Receive_IT(hi2s); return; } /* I2S in mode Tramitter -----------------------------------------------*/ - if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) + if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET)) { I2S_Transmit_IT(hi2s); return; } /* I2S interrupt error -------------------------------------------------*/ - if (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET) + if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET) { /* I2S Overrun error interrupt occurred ---------------------------------*/ - if ((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) + if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET) { /* Disable RXNE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); @@ -1401,7 +1415,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) } /* I2S Underrun error interrupt occurred --------------------------------*/ - if ((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) + if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET) { /* Disable TXE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); @@ -1561,7 +1575,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) */ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ /* if DMA is configured in DMA_NORMAL Mode */ if (hdma->Init.Mode == DMA_NORMAL) @@ -1588,7 +1602,7 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) */ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ /* Call user Tx half complete callback */ #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) @@ -1606,7 +1620,7 @@ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) */ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ /* if DMA is configured in DMA_NORMAL Mode */ if (hdma->Init.Mode == DMA_NORMAL) @@ -1632,7 +1646,7 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) */ static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ /* Call user Rx half complete callback */ #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) @@ -1650,7 +1664,7 @@ static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void I2S_DMAError(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ /* Disable Rx and Tx DMA Request */ CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); @@ -1678,7 +1692,8 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma) static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) { /* Transmit data */ - hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + hi2s->Instance->DR = (*hi2s->pTxBuffPtr); + hi2s->pTxBuffPtr++; hi2s->TxXferCount--; if (hi2s->TxXferCount == 0U) @@ -1705,7 +1720,8 @@ static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) { /* Receive data */ - (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; + (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; + hi2s->pRxBuffPtr++; hi2s->RxXferCount--; if (hi2s->RxXferCount == 0U) @@ -1732,7 +1748,7 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) * @param Timeout Duration of the timeout * @retval HAL status */ -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout) +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout) { uint32_t tickstart; @@ -1744,7 +1760,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Set the I2S State ready */ hi2s->State = HAL_I2S_STATE_READY; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_irda.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_irda.c index 501c35335008b89d3653e92e234470624803824f..d27e79d219c850906b6bea63b6e3141a2dd83fcc 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_irda.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_irda.c @@ -206,7 +206,7 @@ #define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */ #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ - | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ + | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ #define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ @@ -225,7 +225,8 @@ * @param __PRESCALER__ IRDA clock prescaler value. * @retval Division result */ -#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** * @} */ @@ -240,7 +241,8 @@ void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda); #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -476,7 +478,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -715,6 +718,7 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. + [..] (#) There are two modes of transfer: (++) Blocking mode: the communication is performed in polling mode. The HAL status of all data processing is returned by the same function @@ -752,28 +756,28 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD (++) HAL_IRDA_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_IRDA_Abort() - (+) HAL_IRDA_AbortTransmit() - (+) HAL_IRDA_AbortReceive() - (+) HAL_IRDA_Abort_IT() - (+) HAL_IRDA_AbortTransmit_IT() - (+) HAL_IRDA_AbortReceive_IT() + (++) HAL_IRDA_Abort() + (++) HAL_IRDA_AbortTransmit() + (++) HAL_IRDA_AbortReceive() + (++) HAL_IRDA_Abort_IT() + (++) HAL_IRDA_AbortTransmit_IT() + (++) HAL_IRDA_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_IRDA_AbortCpltCallback() - (+) HAL_IRDA_AbortTransmitCpltCallback() - (+) HAL_IRDA_AbortReceiveCpltCallback() + (++) HAL_IRDA_AbortCpltCallback() + (++) HAL_IRDA_AbortTransmitCpltCallback() + (++) HAL_IRDA_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -781,10 +785,13 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD /** * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Specify timeout value. * @retval HAL status */ @@ -884,10 +891,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Specify timeout value. * @retval HAL status */ @@ -989,10 +999,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ /** @@ -1048,10 +1061,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ /** @@ -1114,10 +1130,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData pointer to data buffer. - * @param Size amount of data to be sent. + * @param pData pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ /** @@ -1206,12 +1225,15 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @note When the IRDA parity is enabled (PCE = 1), the received data contains * the parity bit (MSB position). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ /** @@ -1456,7 +1478,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1542,7 +1564,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ @@ -1594,7 +1616,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1652,7 +1674,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) { uint32_t abortcplt = 1U; @@ -1784,7 +1806,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ @@ -1862,7 +1884,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1945,6 +1967,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) uint32_t cr1its = READ_REG(hirda->Instance->CR1); uint32_t cr3its; uint32_t errorflags; + uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); @@ -2008,8 +2031,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ + errorcode = hirda->ErrorCode; if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) || - ((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != 0U)) + ((errorcode & HAL_IRDA_ERROR_ORE) != 0U)) { /* Blocking error : transfer is aborted Set the IRDA state ready to be able to start again the process, @@ -2251,7 +2275,8 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = (uint32_t)hirda->gState; temp2 = (uint32_t)hirda->RxState; @@ -2314,6 +2339,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) IRDA_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + uint32_t pclk; /* Check the communication parameters */ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); @@ -2342,7 +2368,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler); /*-------------------------- USART GTPR Configuration ----------------------*/ - MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, hirda->Init.Prescaler); + MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler); /*-------------------------- USART BRR Configuration -----------------------*/ IRDA_GETCLOCKSOURCE(hirda, clocksource); @@ -2350,13 +2376,15 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) switch (clocksource) { case IRDA_CLOCKSOURCE_PCLK1: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_HSI: tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_SYSCLK: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_LSE: tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); @@ -2436,7 +2464,8 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c index ea92e5dfafdb1e3a7e27f71902ca2ec1aba912a4..e4b6b6e7f888688c0efdcc65c09fc4319a36f209 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c @@ -36,7 +36,7 @@ (+) Debug mode : When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module, accessible through - __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros + __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s The IWDG timeout may vary due to LSI frequency dispersion. STM32G0xx @@ -48,19 +48,19 @@ ============================================================================== [..] (#) Use IWDG using HAL_IWDG_Init() function to : - (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI - clock is forced ON and IWDG counter starts downcounting. - (+) Enable write access to configuration register: IWDG_PR, IWDG_RLR & - IWDG_WINR. - (+) Configure the IWDG prescaler and counter reload value. This reload + (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI + clock is forced ON and IWDG counter starts counting down. + (++) Enable write access to configuration registers: + IWDG_PR, IWDG_RLR and IWDG_WINR. + (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. - (+) wait for status flags to be reset" - (+) Depending on window parameter: - (++) If Window Init parameter is same as Window register value, + (++) Wait for status flags to be reset. + (++) Depending on window parameter: + (+++) If Window Init parameter is same as Window register value, nothing more is done but reload counter value in order to exit - function withy exact time base. - (++) Else modify Window register. This will automatically reload + function with exact time base. + (+++) Else modify Window register. This will automatically reload watchdog counter. (#) Then the application program must refresh the IWDG counter at regular @@ -79,11 +79,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -167,7 +167,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); - /* Enable IWDG. LSI is turned on automaticaly */ + /* Enable IWDG. LSI is turned on automatically */ __HAL_IWDG_START(hiwdg); /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_lptim.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_lptim.c index b762dd697bef942c8898688c0c3aed13509f90c0..da5f4ba565f7ef26c75230fa3b1620cf713c0a3a 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_lptim.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_lptim.c @@ -92,19 +92,19 @@ *** Callback registration *** ============================================= - + [..] The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - + [..] Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - + [..] Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the default weak function. @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. - + [..] These functions allow to register/unregister following callbacks: (+) MspInitCallback : LPTIM Base Msp Init Callback. @@ -117,15 +117,18 @@ (+) DirectionUpCallback : Up-counting direction change Callback. (+) DirectionDownCallback : Down-counting direction change Callback. + [..] By default, after the Init and when the state is HAL_LPTIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback(). + [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functionalities in the Init/DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + [..] Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only. Exception done MspInit/MspDeInit that can be registered/unregistered in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, @@ -133,6 +136,7 @@ In that case first register the MspInit/MspDeInit user callbacks using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + [..] When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @@ -148,8 +152,7 @@ * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_msp_template.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_msp_template.c index b9cbf9708fbc710706c07c223eb5586ac6cdfaa7..2a5f58727642e223740b7bf7a9840d948ddfa535 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_msp_template.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_msp_template.c @@ -5,16 +5,6 @@ * @brief HAL MSP module. * This file template is located in the HAL folder and should be copied * to the user folder. - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - This file is generated automatically by STM32CubeMX and eventually modified - by the user - - @endverbatim ****************************************************************************** * @attention * diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c index db1eb61fb8599fe5a37a11fc7f05b7c7f98b06a7..a656a846cc31d525c67913c97232be7a028d2803 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c @@ -273,7 +273,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) SystemCoreClock = HSI_VALUE; /* Adapt Systick interrupt period */ - if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } @@ -399,7 +399,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Adapt Systick interrupt period */ - if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } @@ -680,7 +680,27 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - return HAL_ERROR; + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp_pllckcfg = RCC->PLLCFGR; + if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || +#if defined (RCC_PLLQ_SUPPORT) + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || +#endif + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + { + return HAL_ERROR; + } + } } } return HAL_OK; @@ -870,7 +890,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); /* Configure the source of time base considering new system clocks settings*/ - return HAL_InitTick(TICK_INT_PRIORITY); + return HAL_InitTick(uwTickPrio); } /** @@ -1067,7 +1087,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos]) & 0x1FU)); + return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); } /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c index 65a9154ab5ceafb267a8156efc421666e6eda6c1..5441e8c82d9588bfa3fa8c9410cfcfbcf5b95778 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c @@ -501,7 +501,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for RTC*/ else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else @@ -578,7 +578,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for USART1 */ else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } break; #if defined(RCC_CCIPR_USART2SEL) @@ -605,7 +605,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for USART2 */ else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } break; #endif /* RCC_CCIPR_USART2SEL */ @@ -625,7 +625,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for CEC */ else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } break; #endif /* RCC_CCIPR_CECSEL */ @@ -654,7 +654,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for LPUART1 */ else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } break; #endif /* RCC_CCIPR_LPUART1SEL */ @@ -683,7 +683,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for ADC */ else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } break; @@ -706,7 +706,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for I2C1 */ else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } break; @@ -739,7 +739,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for I2S1 */ else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } break; @@ -767,7 +767,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for LPTIM1 */ else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } break; #endif /* RCC_CCIPR_LPTIM1SEL */ @@ -796,7 +796,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for LPTIM2 */ else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } break; #endif /* RCC_CCIPR_LPTIM2SEL */ @@ -821,7 +821,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else /* No clock source */ { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } break; #endif /* RCC_CCIPR_TIM1SEL */ @@ -846,7 +846,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else /* No clock source */ { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } break; #endif /* RCC_CCIPR_TIM15SEL */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rng.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rng.c index 4288ba89934e4e9cb2e96a31953127c02d55cd72..481824cb3f2ed7a63b40b22c441d9bf4217f062c 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rng.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rng.c @@ -81,11 +81,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -99,6 +99,8 @@ * @{ */ +#if defined (RNG) + /** @addtogroup RNG * @brief RNG HAL module driver. * @{ @@ -106,7 +108,6 @@ #ifdef HAL_RNG_MODULE_ENABLED -#if defined(STM32G081xx) /* Private types -------------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -225,7 +226,6 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) /* Clear Clock Error Detection bit */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED); - /* Disable the RNG Peripheral */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); @@ -308,7 +308,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call if (pCallback == NULL) { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } /* Process locked */ @@ -318,50 +318,50 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call { switch (CallbackID) { - case HAL_RNG_ERROR_CB_ID : - hrng->ErrorCallback = pCallback; - break; - - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = pCallback; - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = pCallback; + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else if (HAL_RNG_STATE_RESET == hrng->State) { switch (CallbackID) { - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = pCallback; - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } @@ -393,50 +393,50 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca { switch (CallbackID) { - case HAL_RNG_ERROR_CB_ID : - hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else if (HAL_RNG_STATE_RESET == hrng->State) { switch (CallbackID) { - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ - break; - - default : - /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } @@ -460,7 +460,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRN if (pCallback == NULL) { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } /* Process locked */ @@ -473,7 +473,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRN else { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } @@ -503,7 +503,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) else { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } @@ -537,8 +537,16 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) /** * @brief Generates a 32-bit random number. - * @note Each time the random number data is read the RNG_FLAG_DRDY flag - * is automatically cleared. + * @note This function checks value of RNG_FLAG_DRDY flag to know if valid + * random number is available in the DR register (RNG_FLAG_DRDY flag set + * whenever a random number is available through the RNG_DR register). + * After transitioning from 0 to 1 (random number available), + * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading + * four words from the RNG_DR register, i.e. further function calls + * will immediately return a new u32 random number (additional words are + * available and can be read by the application, till RNG_FLAG_DRDY flag remains high). + * @note When no more random number data is available in DR register, RNG_FLAG_DRDY + * flag is automatically cleared. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @param random32bit pointer to generated random number variable if successful. @@ -547,7 +555,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit) { - uint32_t tickstart; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ @@ -568,7 +576,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hrng); return HAL_ERROR; @@ -583,6 +591,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t } else { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; status = HAL_ERROR; } @@ -619,6 +628,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) /* Process Unlocked */ __HAL_UNLOCK(hrng); + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; status = HAL_ERROR; } @@ -649,23 +659,27 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { uint32_t rngclockerror = 0U; - + /* RNG clock error interrupt occurred */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; rngclockerror = 1U; } else { /* Nothing to do */ } - - if (rngclockerror == 1U) - { + + if (rngclockerror == 1U) + { /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_ERROR; @@ -696,7 +710,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) hrng->State = HAL_RNG_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hrng); - + #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) /* Call registered Data Ready callback */ hrng->ReadyDataCallback(hrng, hrng->RandomNumber); @@ -721,6 +735,11 @@ uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) /** * @brief Data Ready callback in non-blocking mode. + * @note When RNG_FLAG_DRDY flag value is set, first random number has been read + * from DR register in IRQ Handler and is provided as callback parameter. + * Depending on valid data available in the conditioning output buffer, + * additional words can be read by the application from DR register till + * DRDY bit remains high. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @param random32bit generated random number. @@ -799,13 +818,14 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) * @} */ -#endif #endif /* HAL_RNG_MODULE_ENABLED */ /** * @} */ +#endif /* RNG */ + /** * @} */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c index 0c605dd8491465917dd5a5c98a2703debbe5dbf7..fae24eeb62358bcb0d64f0537475590c574adedc 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c @@ -30,13 +30,13 @@ [..] The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset values. A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the + (+) Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - (#) Tamper detection event resets all data backup registers. + (+) VDD or VBAT power on, if both supplies have previously been powered off. + (+) Tamper detection event resets all data backup registers. ##### Backup Domain Access ##### - ================================================================== + ============================================================================= [..] After reset, the backup domain (RTC registers and RTC backup data registers) is protected against possible unwanted write accesses. [..] To enable access to the RTC Domain and RTC registers, proceed as follows: @@ -47,9 +47,9 @@ (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for + (+) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32) - (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro. + (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro. ##### How to use RTC Driver ##### =================================================================== @@ -92,25 +92,27 @@ *** Callback registration *** ============================================= + [..] The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. + [..] Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: - (+) AlarmAEventCallback : RTC AlarmAEventCallback - (+) AlarmBEventCallback : RTCEx AlarmBEventCallback - (+) TimeStampEventCallback : RTCEx TimeStampEventCallback - (+) WakeUpTimerEventCallback : RTCEx WakeUpTimerEventCallback - (+) Tamper1EventCallback : RTCEx Tamper1EventCallback - (+) Tamper2EventCallback : RTCEx Tamper2EventCallback - (+) InternalTamper1EventCallback : RTCEx InternalTamper1EventCallback - (+) InternalTamper3EventCallback : RTCEx InternalTamper3EventCallback - (+) InternalTamper4EventCallback : RTCEx InternalTamper4EventCallback - (+) InternalTamper5EventCallback : RTCEx InternalTamper5EventCallback - (+) InternalTamper6EventCallback : RTCEx InternalTamper6EventCallback - (+) InternalTamper7EventCallback : RTCEx InternalTamper7EventCallback - (+) MspInitCallback : RTC MspInit. - (+) MspDeInitCallback : RTC MspDeInit. + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) Tamper1EventCallback : RTC Tamper1Event callback. + (+) Tamper2EventCallback : RTC Tamper2Event callback. + (+) InternalTamper1EventCallback : RTC Internal Tamper 1 Event callback. + (+) InternalTamper3EventCallback : RTC Internal Tamper 3 Event callback. + (+) InternalTamper4EventCallback : RTC Internal Tamper 4 Event callback. + (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Event callback. + (+) InternalTamper6EventCallback : RTC Internal Tamper 6 Event callback. + (+) InternalTamper7EventCallback : RTC Internal Tamper 7 Event callback. + (+) MspInitCallback : RTC MspInit. + (+) MspDeInitCallback : RTC MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. @@ -131,9 +133,10 @@ (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Event callback. (+) InternalTamper6EventCallback : RTC Internal Tamper 6 Event callback. (+) InternalTamper7EventCallback : RTC Internal Tamper 7 Event callback. - (+) MspInitCallback : RTC MspInit callback. - (+) MspDeInitCallback : RTC MspDeInit callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + [..] By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, all callbacks are set to the corresponding weak functions : examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback(). @@ -143,6 +146,7 @@ If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + [..] Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. Exception done MspInit/MspDeInit that can be registered/unregistered in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, @@ -151,11 +155,13 @@ using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() or @ref HAL_RTC_Init() function. + [..] When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim + ****************************************************************************** * @attention * @@ -258,7 +264,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; - /* Process TAMP ip offset from RTC one */ + /* Process TAMP peripheral offset from RTC one */ hrtc->TampOffset = (TAMP_BASE - RTC_BASE); #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -296,16 +302,9 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - } - else + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if(status == HAL_OK) { /* Clear RTC_CR FMT, OSEL and POL Bits */ hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE); @@ -314,39 +313,26 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Configure the RTC PRER */ hrtc->Instance->PRER = (hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (hrtc->Init.AsynchPrediv << 16U); + hrtc->Instance->PRER |= (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); /* Exit Initialization mode */ - CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); - - hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU |RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN); - hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) + status = RTC_ExitInitMode(hrtc); + if (status == HAL_OK) { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } + hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU |RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN); + hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); } + } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Set RTC state */ + if (status == HAL_OK) + { hrtc->State = HAL_RTC_STATE_READY; - - status = HAL_OK; } } - /* return status */ return status; } @@ -358,6 +344,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { + HAL_StatusTypeDef status; uint32_t tickstart; /* Check the parameters */ @@ -369,18 +356,9 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if(status == HAL_OK) { /* Reset TR, DR and CR registers */ hrtc->Instance->TR = 0x00000000U; @@ -417,46 +395,35 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) hrtc->Instance->ALRMBSSR = 0x00000000U; /* Exit initialization mode */ - CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } + status = RTC_ExitInitMode(hrtc); } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + if (status == HAL_OK) + { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if(hrtc->MspDeInitCallback == NULL) - { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - } + if(hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } /* DeInit the low level hardware: CLOCK, NVIC.*/ hrtc->MspDeInitCallback(hrtc); #else - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ - hrtc->State = HAL_RTC_STATE_RESET; + hrtc->State = HAL_RTC_STATE_RESET; + } - /* Release Lock */ - __HAL_UNLOCK(hrtc); + /* Release Lock */ + __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -585,7 +552,7 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call /** * @brief Unregister an RTC Callback - * RTC callabck is redirected to the weak predefined callback + * RTC callback is redirected to the weak predefined callback * @param hrtc RTC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -762,6 +729,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { uint32_t tmpreg; + HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -776,21 +744,9 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if(status == HAL_OK) { if(Format == RTC_FORMAT_BIN) { @@ -807,10 +763,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim assert_param(IS_RTC_MINUTES(sTime->Minutes)); assert_param(IS_RTC_SECONDS(sTime->Seconds)); - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16U)); + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \ + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); } else { @@ -826,10 +782,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ - ((uint32_t)(sTime->Minutes) << 8U) | \ - ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16U)); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \ + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); } /* Set the RTC_TR register */ @@ -842,34 +798,21 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); /* Exit Initialization mode */ - CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + status = RTC_ExitInitMode(hrtc); + } + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { hrtc->State = HAL_RTC_STATE_READY; + } - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_OK; - } + return status; } /** @@ -910,10 +853,10 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U); - sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U); + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); + sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -940,6 +883,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { uint32_t datetmpreg; + HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -962,10 +906,10 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat assert_param(IS_RTC_MONTH(sDate->Month)); assert_param(IS_RTC_DATE(sDate->Date)); - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13U)); + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \ + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); } else { @@ -973,64 +917,38 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); - datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ - (((uint32_t)sDate->Month) << 8U) | \ - ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13U)); + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + (((uint32_t)sDate->Date) << RTC_DR_DU_Pos)| \ + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if(status == HAL_OK) { /* Set the RTC_DR register */ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); /* Exit Initialization mode */ - CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } + status = RTC_ExitInitMode(hrtc); + } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_READY ; + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_OK; - } + return status; } /** @@ -1057,10 +975,10 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U); - sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U); + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); + sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -1143,11 +1061,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -1176,11 +1094,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -1324,11 +1242,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -1356,11 +1274,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -1575,12 +1493,12 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); /* Fill the structure with the read parameters */ - sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U); - sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U); - sAlarm->AlarmTime.Seconds = (uint8_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> 16U); + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_SU_Pos); sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U); + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos); sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); } @@ -1592,12 +1510,12 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); /* Fill the structure with the read parameters */ - sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> 16U); - sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> 8U); - sAlarm->AlarmTime.Seconds = (uint8_t)(tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> 16U); + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> RTC_ALRMBR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)) >> RTC_ALRMBR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> RTC_ALRMBR_PM_Pos); sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> 24U); + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> RTC_ALRMBR_DU_Pos); sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL); sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); } @@ -1812,6 +1730,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) { uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; /* Check if the Initialization mode is set */ if((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) @@ -1821,19 +1740,56 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) tickstart = HAL_GetTick(); /* Wait till RTC is in INIT state and if Time out is reached exit */ - while((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) + while(((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + status = HAL_TIMEOUT; + hrtc->State = HAL_RTC_STATE_TIMEOUT; } } } - return HAL_OK; + return status; } +/** + * @brief Exit the RTC Initialization mode. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Exit Initialization mode */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + } + else /* WA 2.7.1 Calendar initialization may fail in case of consecutive INIT mode entry. + Please look at STM32G0 Errata sheet on the internet for details. */ + { + /* Clear BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + /* Restore BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + } + return status; +} /** * @brief Convert a 2 digit decimal to BCD format. * @param Value Byte to be converted diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c index 2337efc5ad641cc607fba5f5f925a6ae9634ffd6..a495be13faf5b6db3225f465fc5de313a8d42106 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c @@ -385,17 +385,17 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); - sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U); + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TSTR_HU_Pos); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >>RTC_TSTR_MNU_Pos); + sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TSTR_SU_Pos); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> RTC_TSTR_PM_Pos); sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; /* Fill the Date structure fields with the read parameters */ sTimeStampDate->Year = 0U; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U); + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> RTC_TSDR_MU_Pos); sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> RTC_TSDR_WDU_Pos); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -545,50 +545,32 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(RTC->CR, RTC_CR_WUTE); + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) { tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; } } } - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - /* Clear the Wakeup Timer clock source bits in CR register */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; @@ -635,50 +617,32 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) - { - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } /* Disable the Wake-Up timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); /* Clear flag Wake-Up */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + tickstart = HAL_GetTick(); + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } @@ -1129,6 +1093,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) */ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) { + HAL_StatusTypeDef status; + /* Process Locked */ __HAL_LOCK(hrtc); @@ -1137,38 +1103,29 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if(status == HAL_OK) { + /* Enable clockref detection */ __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); /* Exit Initialization mode */ - hrtc->Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT; + status = RTC_ExitInitMode(hrtc); } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ + if (status == HAL_OK) + { hrtc->State = HAL_RTC_STATE_READY; + } /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** @@ -1178,6 +1135,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) */ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) { + HAL_StatusTypeDef status; + /* Process Locked */ __HAL_LOCK(hrtc); @@ -1186,38 +1145,29 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) { + /* Disable clockref detection */ __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); /* Exit Initialization mode */ - hrtc->Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT; + status = RTC_ExitInitMode(hrtc); } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ + if (status == HAL_OK) + { hrtc->State = HAL_RTC_STATE_READY; + } /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c index 8de7a28752cd5779c89d1b311ca926e7957277e4..606605001bcad735f13ada79a06aedd091dc36a1 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c @@ -196,8 +196,8 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants - * @{ - */ + * @{ + */ #define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ @@ -231,7 +231,8 @@ void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -481,7 +482,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -603,7 +605,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -795,7 +798,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint8_t *ptmpdata = pData; @@ -841,7 +845,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); ptmpdata++; } - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, + Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -882,7 +887,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint8_t *ptmpdata = pData; @@ -1139,7 +1145,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard hsmartcard->hdmatx->XferAbortCallback = NULL; /* Enable the SMARTCARD transmit DMA channel */ - if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size) == HAL_OK) + if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, + Size) == HAL_OK) { /* Clear the TC flag in the ICR register */ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); @@ -1215,7 +1222,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size) == HAL_OK) + if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, + Size) == HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); @@ -1268,7 +1276,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* Disable the SMARTCARD DMA Tx request if enabled */ @@ -1326,7 +1336,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1456,7 +1468,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1484,7 +1498,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) uint32_t abortcplt = 1U; /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised @@ -1581,7 +1597,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1709,7 +1727,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1751,7 +1769,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc hsmartcard->RxISR = NULL; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1775,7 +1795,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc hsmartcard->RxISR = NULL; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1805,6 +1827,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1); uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3); uint32_t errorflags; + uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); @@ -1890,8 +1913,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) - Overrun error in Reception - any error occurs in DMA mode reception */ + errorcode = hsmartcard->ErrorCode; if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) - || ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U)) + || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U)) { /* Blocking error : transfer is aborted Set the SMARTCARD state ready to be able to start again the process, @@ -1943,7 +1967,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) - Frame error in Transmission */ else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) - && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != 0U)) + && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U)) { /* Blocking error : transfer is aborted Set the SMARTCARD state ready to be able to start again the process, @@ -2042,7 +2066,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) { - if(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) { SMARTCARD_EndTransmit_IT(hsmartcard); return; @@ -2204,7 +2228,8 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsma HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) { /* Return SMARTCARD handle state */ - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = (uint32_t)hsmartcard->gState; temp2 = (uint32_t)hsmartcard->RxState; @@ -2267,6 +2292,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard SMARTCARD_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + uint32_t pclk; /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); @@ -2338,13 +2364,15 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard switch (clocksource) { case SMARTCARD_CLOCKSOURCE_PCLK1: - tmpreg = (uint16_t)(((HAL_RCC_GetPCLK1Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + pclk = HAL_RCC_GetPCLK1Freq(); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_SYSCLK: - tmpreg = (uint16_t)(((HAL_RCC_GetSysClockFreq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + pclk = HAL_RCC_GetSysClockFreq(); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); @@ -2458,7 +2486,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -2468,7 +2497,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -2495,7 +2525,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar * @param Timeout Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) @@ -2619,7 +2650,7 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) /* Stop SMARTCARD DMA Tx request if ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { hsmartcard->TxXferCount = 0U; SMARTCARD_EndTxTransfer(hsmartcard); @@ -2698,7 +2729,9 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2745,7 +2778,9 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2805,7 +2840,9 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c index 3e877655f5ee8b912d418b8f583bcd67c3444325..5c1dc93629998cb6d4a75d01267a7e046e1656ec 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c @@ -89,12 +89,12 @@ *** Callback registration *** ============================================= - + [..] The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback() to register an interrupt callback. - + [..] Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. @@ -106,9 +106,9 @@ (+) MspDeInitCallback : callback for Msp DeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - + [..] For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback. - + [..] Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default weak function. @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, @@ -122,9 +122,9 @@ (+) ErrorCallback : callback for error detection. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. - + [..] For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback. - + [..] By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback(). @@ -133,7 +133,7 @@ these callbacks are null (not registered beforehand). If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - + [..] Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, @@ -141,7 +141,7 @@ Then, the user first registers the MspInit/MspDeInit user callbacks using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit() or @ref HAL_SMBUS_Init() function. - + [..] When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c index 02a23225ad29ba3cea1a71ea1503ea3667062236..f744ce9cc18238a88fcb686ee9305dbcc6be1c9a 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c @@ -117,7 +117,7 @@ and weak (surcharged) callbacks are used. [..] - Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, + Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes, the following table resume the max SPI frequency reached with data size 8bits/16bits, according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. @@ -2253,6 +2253,9 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); count = resetcount; + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) { @@ -2290,11 +2293,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) count = resetcount; } - /* Clear ERRIE interrupts in case of DMA Mode */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); - - /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */ - if ((READ_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN))) == (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)) + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) { /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ if (hspi->hdmatx != NULL) @@ -2326,6 +2326,11 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ if (hspi->hdmarx != NULL) { @@ -2411,6 +2416,9 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); count = resetcount; + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) { @@ -2448,9 +2456,6 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) count = resetcount; } - /* Clear ERRIE interrupts in case of DMA Mode */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); - /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ @@ -2482,41 +2487,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) } } - /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ - if ((READ_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN))) == (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)) - { - /* Abort the SPI DMA Tx Stream/Channel */ - if (hspi->hdmatx != NULL) - { - /* Abort DMA Tx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) - { - hspi->hdmatx->XferAbortCallback = NULL; - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - else - { - abortcplt = 0U; - } - } - /* Abort the SPI DMA Rx Stream/Channel */ - if (hspi->hdmarx != NULL) - { - /* Abort DMA Rx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) - { - hspi->hdmarx->XferAbortCallback = NULL; - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - abortcplt = 1U; - } - else - { - abortcplt = 0U; - } - } - } - - /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + /* Disable the SPI DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) { /* Abort the SPI DMA Tx Stream/Channel */ @@ -2534,7 +2505,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) } } } - /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + /* Disable the SPI DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) { /* Abort the SPI DMA Rx Stream/Channel */ @@ -2972,7 +2943,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); /* DMA Normal Mode */ @@ -3443,7 +3414,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Receive data in packing mode */ if (hspi->RxXferCount > 1U) { - *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount -= 2U; if (hspi->RxXferCount == 1U) @@ -3566,7 +3537,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Receive data in 16 Bit mode */ - *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; @@ -3727,7 +3698,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { - *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; @@ -4181,8 +4152,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); /* Check RXNEIE is disabled */ do @@ -4223,8 +4194,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + /* Disable TXEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); /* Check TXEIE is disabled */ do @@ -4252,6 +4223,36 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } + /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + + /* Check RXNEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } hspi->State = HAL_SPI_STATE_ABORT; } diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c index f6e1db5500f4192953dbe80cce958aed4c01e18e..bbc05a0308f57ee11bc91f1c87baced3270bcea7 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c @@ -5,30 +5,30 @@ * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: - * + Time Base Initialization - * + Time Base Start - * + Time Base Start Interruption - * + Time Base Start DMA - * + Time Output Compare/PWM Initialization - * + Time Output Compare/PWM Channel Configuration - * + Time Output Compare/PWM Start - * + Time Output Compare/PWM Start Interruption - * + Time Output Compare/PWM Start DMA - * + Time Input Capture Initialization - * + Time Input Capture Channel Configuration - * + Time Input Capture Start - * + Time Input Capture Start Interruption - * + Time Input Capture Start DMA - * + Time One Pulse Initialization - * + Time One Pulse Channel Configuration - * + Time One Pulse Start - * + Time Encoder Interface Initialization - * + Time Encoder Interface Start - * + Time Encoder Interface Start Interruption - * + Time Encoder Interface Start DMA + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA * + Commutation Event configuration with Interruption and DMA - * + Time OCRef clear configuration - * + Time External Clock configuration + * + TIM OCRef clear configuration + * + TIM External Clock configuration @verbatim ============================================================================== ##### TIMER Generic features ##### @@ -79,8 +79,8 @@ PWM signal. (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. (#) Activate the TIM peripheral using one of the start functions depending from the feature used: @@ -98,77 +98,85 @@ *** Callback registration *** ============================================= + [..] The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. + [..] Use Function @ref HAL_TIM_RegisterCallback() to register a callback. @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. + [..] Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. + [..] These functions allow to register/unregister following callbacks: - (+) Base_MspInitCallback : TIM Base Msp Init Callback. - (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. - (+) IC_MspInitCallback : TIM IC Msp Init Callback. - (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. - (+) OC_MspInitCallback : TIM OC Msp Init Callback. - (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. - (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. - (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. - (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. - (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. - (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. - (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. - (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. - (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerCallback : TIM Trigger Callback. (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. - (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. - (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. - (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. - (+) ErrorCallback : TIM Error Callback. - (+) CommutationCallback : TIM Commutation Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. - (+) BreakCallback : TIM Break Callback. + (+) BreakCallback : TIM Break Callback. (+) Break2Callback : TIM Break2 Callback. - By default, after the Init and when the state is HAL_TIM_STATE_RESET - all interrupt callbacks are set to the corresponding weak functions: + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak - functionalities in the Init/DeInit only when these callbacks are null - (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in HAL_TIM_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. - When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. @endverbatim ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -218,13 +226,13 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t TIM_ICFilter); static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint32_t InputTriggerSource); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig); + TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ @@ -234,9 +242,9 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, * @{ */ -/** @defgroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @verbatim ============================================================================== ##### Time Base functions ##### @@ -268,7 +276,7 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -279,7 +287,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; @@ -288,7 +296,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); - if(htim->Base_MspInitCallback == NULL) + if (htim->Base_MspInitCallback == NULL) { htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; } @@ -301,13 +309,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } @@ -383,7 +391,7 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; @@ -392,17 +400,17 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -412,20 +420,20 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) * @brief Stops the TIM Base generation. * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -435,7 +443,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; @@ -450,7 +458,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -461,7 +469,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) * @brief Stops the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ @@ -490,13 +498,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { - if ((pData == NULL ) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -509,7 +517,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat { /* nothing to do */ } - + /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; @@ -530,7 +538,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -566,23 +574,23 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) * @} */ -/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @verbatim ============================================================================== - ##### Time Output Compare functions ##### + ##### TIM Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Output Compare. (+) De-initialize the TIM Output Compare. - (+) Start the Time Output Compare. - (+) Stop the Time Output Compare. - (+) Start the Time Output Compare and enable interrupt. - (+) Stop the Time Output Compare and disable interrupt. - (+) Start the Time Output Compare and enable DMA transfer. - (+) Stop the Time Output Compare and disable DMA transfer. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. @endverbatim * @{ @@ -597,10 +605,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) * @param htim TIM Output Compare handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -611,7 +619,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; @@ -620,7 +628,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); - if(htim->OC_MspInitCallback == NULL) + if (htim->OC_MspInitCallback == NULL) { htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; } @@ -633,13 +641,13 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } @@ -660,7 +668,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if(htim->OC_MspDeInitCallback == NULL) + if (htim->OC_MspDeInitCallback == NULL) { htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; } @@ -722,7 +730,7 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; @@ -733,7 +741,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -743,7 +751,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -849,7 +857,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -909,7 +917,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -937,18 +945,18 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { - uint32_t tmpsmcr; + uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { - if ((pData == NULL ) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -961,7 +969,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel { /* nothing to do */ } - + switch (Channel) { case TIM_CHANNEL_1: @@ -974,7 +982,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length)!= HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { return HAL_ERROR; } @@ -994,7 +1002,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length)!= HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { return HAL_ERROR; } @@ -1014,7 +1022,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length)!= HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { return HAL_ERROR; } @@ -1033,7 +1041,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length)!= HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { return HAL_ERROR; } @@ -1049,7 +1057,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1059,7 +1067,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -1076,7 +1084,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1143,23 +1151,23 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @verbatim ============================================================================== - ##### Time PWM functions ##### + ##### TIM PWM functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM PWM. (+) De-initialize the TIM PWM. - (+) Start the Time PWM. - (+) Stop the Time PWM. - (+) Start the Time PWM and enable interrupt. - (+) Stop the Time PWM and disable interrupt. - (+) Start the Time PWM and enable DMA transfer. - (+) Stop the Time PWM and disable DMA transfer. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. @endverbatim * @{ @@ -1177,7 +1185,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -1188,7 +1196,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; @@ -1197,7 +1205,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); - if(htim->PWM_MspInitCallback == NULL) + if (htim->PWM_MspInitCallback == NULL) { htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; } @@ -1210,13 +1218,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } @@ -1237,7 +1245,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if(htim->PWM_MspDeInitCallback == NULL) + if (htim->PWM_MspDeInitCallback == NULL) { htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; } @@ -1299,7 +1307,7 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; @@ -1310,7 +1318,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1320,7 +1328,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -1339,7 +1347,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1348,7 +1356,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1374,7 +1382,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; @@ -1428,7 +1436,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -1445,8 +1453,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1513,7 +1521,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; @@ -1521,13 +1529,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { - if((pData == NULL ) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -1592,7 +1600,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { return HAL_ERROR; } @@ -1627,7 +1635,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1637,7 +1645,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -1654,7 +1662,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1701,7 +1709,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1721,9 +1729,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @} */ -/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @verbatim ============================================================================== ##### TIM Input Capture functions ##### @@ -1755,7 +1763,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -1766,7 +1774,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; @@ -1775,7 +1783,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); - if(htim->IC_MspInitCallback == NULL) + if (htim->IC_MspInitCallback == NULL) { htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; } @@ -1788,13 +1796,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } @@ -1815,7 +1823,7 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if(htim->IC_MspDeInitCallback == NULL) + if (htim->IC_MspDeInitCallback == NULL) { htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; } @@ -1876,7 +1884,7 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; @@ -1890,7 +1898,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -1934,7 +1942,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; @@ -1961,14 +1969,14 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; + break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; + break; } default: @@ -1981,7 +1989,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -1998,7 +2006,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -2069,13 +2077,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { - if((pData == NULL ) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -2178,7 +2186,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -2256,9 +2264,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief TIM One Pulse functions - * +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @verbatim ============================================================================== ##### TIM One Pulse functions ##### @@ -2284,7 +2292,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() - * @param htim TIM OnePulse handle + * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. @@ -2294,7 +2302,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -2306,7 +2314,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_OPM_MODE(OnePulseMode)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; @@ -2315,7 +2323,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); - if(htim->OnePulse_MspInitCallback == NULL) + if (htim->OnePulse_MspInitCallback == NULL) { htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; } @@ -2328,7 +2336,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the One Pulse Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); @@ -2340,7 +2348,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul htim->Instance->CR1 |= OnePulseMode; /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } @@ -2361,7 +2369,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if(htim->OnePulse_MspDeInitCallback == NULL) + if (htim->OnePulse_MspDeInitCallback == NULL) { htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; } @@ -2437,7 +2445,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -2470,7 +2478,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -2515,7 +2523,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -2553,7 +2561,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -2570,9 +2578,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @} */ -/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @verbatim ============================================================================== ##### TIM Encoder functions ##### @@ -2604,14 +2612,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -2631,7 +2639,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; @@ -2640,7 +2648,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); - if(htim->Encoder_MspInitCallback == NULL) + if (htim->Encoder_MspInitCallback == NULL) { htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; } @@ -2653,7 +2661,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); @@ -2698,7 +2706,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini htim->Instance->CCER = tmpccer; /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } @@ -2720,7 +2728,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if(htim->Encoder_MspDeInitCallback == NULL) + if (htim->Encoder_MspDeInitCallback == NULL) { htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; } @@ -2799,7 +2807,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } - + default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -2838,13 +2846,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); break; } - + case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); break; } - + default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -2885,14 +2893,14 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } - + case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } - + default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -2927,14 +2935,14 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) + if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } - else if(Channel == TIM_CHANNEL_2) + else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2974,18 +2982,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) { /* Check the parameters */ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { - if((((pData1 == NULL) || (pData2 == NULL) )) && (Length > 0U)) + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { return HAL_ERROR; } @@ -3011,7 +3020,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { return HAL_ERROR; } @@ -3115,7 +3124,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) + if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -3123,7 +3132,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); } - else if(Channel == TIM_CHANNEL_2) + else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -3157,8 +3166,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha * @} */ /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * + * @brief TIM IRQ handler management + * @verbatim ============================================================================== ##### IRQ handler management ##### @@ -3177,16 +3186,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { /* Capture compare 1 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); @@ -3210,14 +3219,14 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 2 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); @@ -3240,14 +3249,14 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 3 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); @@ -3270,14 +3279,14 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 4 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); @@ -3300,9 +3309,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Update event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -3313,9 +3322,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break input event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -3339,9 +3348,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Trigger detection event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -3352,9 +3361,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM commutation event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -3370,9 +3379,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @} */ -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions - * +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -3405,7 +3414,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, + TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ @@ -3504,7 +3513,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); @@ -3604,7 +3613,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, + TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ @@ -3746,9 +3755,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) { TIM_OC_InitTypeDef temp1; @@ -3756,7 +3770,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - if(OutputChannel != InputChannel) + if (OutputChannel != InputChannel) { /* Process Locked */ __HAL_LOCK(htim); @@ -3851,7 +3865,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3871,9 +3885,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @arg TIM_DMABASE_AF1 - * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -3886,10 +3904,11 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t* BurstBuffer, uint32_t BurstLength) + uint32_t *BurstBuffer, uint32_t BurstLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -3897,13 +3916,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { - if((BurstBuffer == NULL ) && (BurstLength > 0U)) + if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -3916,7 +3935,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t { /* nothing to do */ } - switch(BurstRequestSrc) + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { @@ -3936,15 +3955,16 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t } case TIM_DMA_CC1: { - /* Set the DMA compare callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -3953,14 +3973,15 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t case TIM_DMA_CC2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -3969,14 +3990,15 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t case TIM_DMA_CC3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -3985,14 +4007,15 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t case TIM_DMA_CC4: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4008,7 +4031,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4024,7 +4048,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4058,7 +4083,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { @@ -4101,8 +4126,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B if (HAL_OK == status) { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); } /* Return function status */ @@ -4132,9 +4157,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @arg TIM_DMABASE_AF1 - * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -4147,10 +4176,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -4158,13 +4188,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { - if((BurstBuffer == NULL ) && (BurstLength > 0U)) + if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -4176,8 +4206,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B else { /* nothing to do */ - } - switch(BurstRequestSrc) + } + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { @@ -4189,7 +4219,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U)!= HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4198,14 +4228,14 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B case TIM_DMA_CC1: { /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U)!= HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4214,14 +4244,14 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B case TIM_DMA_CC2: { /* Set the DMA capture/compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U)!= HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4230,14 +4260,14 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B case TIM_DMA_CC3: { /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U)!= HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4246,14 +4276,14 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B case TIM_DMA_CC4: { /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U)!= HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4269,7 +4299,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U)!= HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4285,7 +4315,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U)!= HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4320,7 +4350,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { @@ -4363,8 +4393,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu if (HAL_OK == status) { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); } /* Return function status */ @@ -4441,7 +4471,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - + htim->State = HAL_TIM_STATE_BUSY; switch (sClearInputConfig->ClearInputSource) @@ -4450,7 +4480,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { /* Clear the OCREF clear selection bit and the the ETR Bits */ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); - + /* Clear TIMx_OR1_OCREF_CLR (reset value) */ CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); break; @@ -4475,7 +4505,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, break; } #endif /* COMP1 && COMP2 */ - + case TIM_CLEARINPUTSOURCE_ETR: { /* Check the parameters */ @@ -4486,7 +4516,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) { - htim->State = HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } @@ -4498,12 +4528,12 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /* Set the OCREF clear selection bit */ SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - + /* Clear TIMx_OR1_OCREF_CLR (reset value) */ CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); break; } - + default: break; } @@ -4512,7 +4542,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { case TIM_CHANNEL_1: { - if(sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 1 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); @@ -4526,7 +4556,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } case TIM_CHANNEL_2: { - if(sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 2 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); @@ -4540,7 +4570,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } case TIM_CHANNEL_3: { - if(sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 3 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); @@ -4554,7 +4584,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } case TIM_CHANNEL_4: { - if(sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 4 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); @@ -4568,7 +4598,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } case TIM_CHANNEL_5: { - if(sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 5 */ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); @@ -4582,7 +4612,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } case TIM_CHANNEL_6: { - if(sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 6 */ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); @@ -4599,7 +4629,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); return HAL_OK; @@ -4612,7 +4642,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, * contains the clock source information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { uint32_t tmpsmcr; @@ -4690,7 +4720,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); @@ -4807,9 +4837,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC htim->State = HAL_TIM_STATE_BUSY; - if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { - htim->State = HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } @@ -4837,20 +4867,20 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) - { + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - + __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; - if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { - htim->State = HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } @@ -4940,19 +4970,19 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * + * @brief TIM Callbacks functions + * @verbatim ============================================================================== ##### TIM Callbacks functions ##### ============================================================================== [..] This section provides TIM callback functions: - (+) Timer Period elapsed callback - (+) Timer Output Compare callback - (+) Timer Input capture callback - (+) Timer Trigger callback - (+) Timer Error callback + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback @endverbatim * @{ @@ -5142,206 +5172,207 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID - * @param pCallback pointer to the callback function - * @retval status + * @param pCallback pointer to the callback function + * @retval status */ -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } /* Process locked */ __HAL_LOCK(htim); - if(htim->State == HAL_TIM_STATE_READY) + if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = pCallback; - break; + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = pCallback; - break; + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = pCallback; - break; + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : htim->PeriodElapsedHalfCpltCallback = pCallback; break; - case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = pCallback; - break; + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; case HAL_TIM_TRIGGER_HALF_CB_ID : htim->TriggerHalfCpltCallback = pCallback; break; - case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = pCallback; - break; + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : htim->IC_CaptureHalfCpltCallback = pCallback; break; - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = pCallback; - break; + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = pCallback; - break; + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : htim->PWM_PulseFinishedHalfCpltCallback = pCallback; break; - case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = pCallback; - break; + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; - case HAL_TIM_COMMUTATION_CB_ID : - htim->CommutationCallback = pCallback; - break; + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; case HAL_TIM_COMMUTATION_HALF_CB_ID : htim->CommutationHalfCpltCallback = pCallback; break; - case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = pCallback; - break; + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; case HAL_TIM_BREAK2_CB_ID : htim->Break2Callback = pCallback; break; - default : - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(htim->State == HAL_TIM_STATE_RESET) + else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = pCallback; - break; + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = pCallback; - break; + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; - default : - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -5390,7 +5421,7 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID - * @retval status + * @retval status */ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) { @@ -5399,192 +5430,192 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca /* Process locked */ __HAL_LOCK(htim); - if(htim->State == HAL_TIM_STATE_READY) + if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ - break; + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ - break; + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ - break; + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ - break; + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ - break; + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ - break; + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ - break; + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ - break; + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ - break; + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ - break; + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ - break; + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ - break; + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ - break; + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ - break; + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ - break; + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ break; - case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ - break; + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; case HAL_TIM_TRIGGER_HALF_CB_ID : htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ break; - case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ - break; + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ break; - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ - break; + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + break; - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ - break; + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ break; - case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ - break; + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + break; - case HAL_TIM_COMMUTATION_CB_ID : + case HAL_TIM_COMMUTATION_CB_ID : htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ break; case HAL_TIM_COMMUTATION_HALF_CB_ID : htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ - break; + break; - case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ - break; + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + break; case HAL_TIM_BREAK2_CB_ID : htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ break; - default : - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(htim->State == HAL_TIM_STATE_RESET) + else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ - break; + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ - break; + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ - break; + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ - break; + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ - break; + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ - break; + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ - break; + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ - break; + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ - break; + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ - break; + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ - break; + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ - break; + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ - break; + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ - break; + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; - default : - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -5604,9 +5635,9 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @} */ -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State functions ##### @@ -5698,12 +5729,12 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) */ void TIM_DMAError(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->ErrorCallback(htim); + htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -5716,9 +5747,9 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) */ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { @@ -5798,9 +5829,9 @@ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { @@ -5880,9 +5911,9 @@ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); @@ -5916,15 +5947,15 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); - #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** @@ -5964,7 +5995,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) tmpcr1 |= Structure->CounterMode; } - if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; @@ -6027,7 +6058,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); @@ -6040,7 +6071,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccer &= ~TIM_CCER_CC1NE; } - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); @@ -6103,7 +6134,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); @@ -6116,7 +6147,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) } - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); @@ -6178,7 +6209,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); @@ -6190,7 +6221,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccer &= ~TIM_CCER_CC3NE; } - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); @@ -6253,7 +6284,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); @@ -6311,7 +6342,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; @@ -6364,7 +6395,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; @@ -6392,7 +6423,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) + TIM_SlaveConfigTypeDef *sSlaveConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; @@ -6413,7 +6444,7 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - + /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) { @@ -6425,19 +6456,19 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } - + case TIM_TS_TI1F_ED: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) { return HAL_ERROR; @@ -6446,46 +6477,46 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = htim->Instance->CCER; htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - + tmpccmr1 = htim->Instance->CCMR1; + /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); - + /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; + htim->Instance->CCER = tmpccer; break; } - + case TIM_TS_TI1FP1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + /* Configure TI1 Filter and Polarity */ TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } - + case TIM_TS_TI2FP2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } - + case TIM_TS_ITR0: case TIM_TS_ITR1: case TIM_TS_ITR2: @@ -6495,7 +6526,7 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); break; } - + default: break; } @@ -6534,7 +6565,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ tmpccer = TIMx->CCER; /* Select the Input */ - if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) { tmpccmr1 &= ~TIM_CCMR1_CC1S; tmpccmr1 |= TIM_ICSelection; @@ -6816,7 +6847,7 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) * This parameter must be a value between 0x00 and 0x0F * @retval None */ -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { uint32_t tmpsmcr; @@ -6848,7 +6879,7 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { uint32_t tmp; @@ -6875,19 +6906,19 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */ } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c index ad4e31de0ce68916aeb0d9c8461dbe955f277837..409d69017ccaf1f2cd8b2ea52c34d734fde2f4e3 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c @@ -50,10 +50,10 @@ (#) Configure the TIM in the desired functioning mode using one of the initialization function of this driver: (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). (#) Activate the TIM peripheral using one of the start functions: (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() @@ -65,16 +65,16 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** -*/ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32g0xx_hal.h" @@ -106,7 +106,7 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions @@ -140,12 +140,12 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -159,7 +159,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; @@ -168,7 +168,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen /* Reset interrupt callbacks to legacy week callbacks */ TIM_ResetCallback(htim); - if(htim->HallSensor_MspInitCallback == NULL) + if (htim->HallSensor_MspInitCallback == NULL) { htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; } @@ -222,7 +222,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen htim->Instance->CR2 |= TIM_TRGO_OC2REF; /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } @@ -243,7 +243,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if(htim->HallSensor_MspDeInitCallback == NULL) + if (htim->HallSensor_MspDeInitCallback == NULL) { htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; } @@ -272,7 +272,7 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file */ @@ -287,7 +287,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file */ @@ -313,7 +313,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -409,25 +409,25 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - /* nothing to do */ - } + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -450,7 +450,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -535,7 +535,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -619,7 +619,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - + /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -630,7 +630,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -721,13 +721,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { - if(((uint32_t)pData == 0U ) && (Length > 0U)) + if (((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -791,7 +791,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { return HAL_ERROR; } @@ -814,7 +814,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -944,7 +944,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -1037,7 +1037,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -1055,7 +1055,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpccer; @@ -1129,13 +1129,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { - if(((uint32_t)pData == 0U ) && (Length > 0U)) + if (((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -1198,7 +1198,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { return HAL_ERROR; } @@ -1221,7 +1221,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); } /* Return function status */ @@ -1323,7 +1323,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) - { +{ /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); @@ -1444,7 +1444,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t ============================================================================== [..] This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure the commutation event in case of use of the Hall sensor interface. (+) Configure Output channels for OC and PWM mode. (+) Configure Complementary channels, break features and dead time. @@ -1479,7 +1479,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); @@ -1534,7 +1535,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); @@ -1590,7 +1592,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); @@ -1639,7 +1642,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef * sMasterConfig) + TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; @@ -1651,7 +1654,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Check input state */ __HAL_LOCK(htim); - + /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; @@ -1688,7 +1691,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; @@ -1698,15 +1701,18 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, } /** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; @@ -1737,16 +1743,16 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) { /* Check the parameters */ assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); - + /* Set BREAK AF mode */ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); } - + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { /* Check the parameters */ @@ -1763,7 +1769,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, { /* Check the parameters */ assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); - + /* Set BREAK2 AF mode */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } @@ -1807,8 +1813,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, /* Check input state */ __HAL_LOCK(htim); - - switch(sBreakInputConfig->Source) + + switch (sBreakInputConfig->Source) { case TIM_BREAKINPUTSOURCE_BKIN: { @@ -1837,56 +1843,56 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, } #endif /* COMP1 && COMP2 */ - default: + default: { bkin_enable_mask = 0U; - bkin_enable_bitpos = 0U; bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; bkin_polarity_bitpos = 0U; break; } } - - switch(BreakInput) + + switch (BreakInput) { case TIM_BREAKINPUT_BRK: { /* Get the TIMx_AF1 register value */ tmporx = htim->Instance->AF1; - + /* Enable the break input */ tmporx &= ~bkin_enable_mask; tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - + /* Set the break input polarity */ tmporx &= ~bkin_polarity_mask; tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - + /* Set TIMx_AF1 */ - htim->Instance->AF1 = tmporx; + htim->Instance->AF1 = tmporx; break; } case TIM_BREAKINPUT_BRK2: { /* Get the TIMx_AF2 register value */ tmporx = htim->Instance->AF2; - + /* Enable the break input */ tmporx &= ~bkin_enable_mask; tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - + /* Set the break input polarity */ tmporx &= ~bkin_polarity_mask; tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - + /* Set TIMx_AF2 */ - htim->Instance->AF2 = tmporx; + htim->Instance->AF2 = tmporx; break; - } - default: + } + default: break; } - + __HAL_UNLOCK(htim); return HAL_OK; @@ -1926,11 +1932,11 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /* Check parameters */ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); assert_param(IS_TIM_REMAP(Remap)); - + __HAL_LOCK(htim); MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap); - + __HAL_UNLOCK(htim); return HAL_OK; @@ -1991,14 +1997,14 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection , uint32_t Channel) +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; - + /* Check parameters */ assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance)); assert_param(IS_TIM_TISEL(TISelection)); - + __HAL_LOCK(htim); switch (Channel) @@ -2013,7 +2019,7 @@ HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISel status = HAL_ERROR; break; } - + __HAL_UNLOCK(htim); return status; @@ -2042,7 +2048,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan htim->State = HAL_TIM_STATE_BUSY; /* Clear GC5Cx bit fields */ - htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1); + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); /* Set GC5Cx bit fields */ htim->Instance->CCR5 |= Channels; @@ -2079,34 +2085,34 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B switch (BreakInput) { case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) { - /* Check initial conditions */ - tmpbdtr = READ_REG(htim->Instance->BDTR); - if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && - (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) - { - /* Break input BRK is disarmed */ - SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); - } - break; + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); } - + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) { - /* Check initial conditions */ - tmpbdtr = READ_REG(htim->Instance->BDTR); - if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && - (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) - { - /* Break input BRK is disarmed */ - SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); - } + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); + } break; - } + } default: break; } - + return HAL_OK; } @@ -2132,10 +2138,10 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br switch (BreakInput) { case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) { - /* Check initial conditions */ - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) - { /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -2148,15 +2154,15 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); return HAL_TIMEOUT; - } - break; } + break; + } case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) { - /* Check initial conditions */ - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) - { /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -2169,9 +2175,9 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); return HAL_TIMEOUT; - } - break; } + break; + } default: break; } @@ -2295,7 +2301,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) */ /* Private functions ---------------------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions * @{ */ @@ -2306,10 +2312,10 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the htim state */ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); @@ -2350,7 +2356,7 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) { uint32_t tmp; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c index 84e0a9a4c104e30770bef2f42529332db0fe121d..1a20eb409897ced833d57ed46eae1bfba8a6ad3d 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c @@ -195,9 +195,6 @@ /** @addtogroup UART_Private_Functions * @{ */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_EndRxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -337,7 +334,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -357,7 +353,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -404,7 +399,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -427,7 +421,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -492,7 +485,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -518,7 +510,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -578,7 +569,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -607,7 +597,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Set the wake up method by setting the WAKE bit in the CR1 register */ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -633,7 +622,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); huart->Instance->CR1 = 0x0U; @@ -656,7 +644,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; - /* Process Unlock */ __HAL_UNLOCK(huart); return HAL_OK; @@ -715,18 +702,18 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ + __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_READY) @@ -786,10 +773,8 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } @@ -807,24 +792,19 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } } else { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(huart); return status; @@ -855,7 +835,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ __HAL_LOCK(huart); if (HAL_UART_STATE_READY == huart->gState) @@ -915,10 +894,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } @@ -936,24 +913,19 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } } else { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(huart); return status; @@ -1043,6 +1015,9 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR /** * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @note When FIFO mode is enabled, writing a data in the TDR register adds one * data to the TXFIFO. Write operations to the TDR register are performed * when TXFNF flag is set. From hardware perspective, TXFNF flag and @@ -1052,8 +1027,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ @@ -1082,7 +1057,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u } } - /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1094,7 +1068,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->TxXferSize = Size; huart->TxXferCount = Size; - /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; @@ -1133,7 +1107,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1146,6 +1119,9 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO * is not empty. Read operations from the RDR register are performed when * RXFNE flag is set. From hardware perspective, RXFNE flag and @@ -1155,8 +1131,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u * (as received data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Timeout duration. * @retval HAL status */ @@ -1186,7 +1162,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui } } - /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1237,7 +1212,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1251,12 +1225,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1280,7 +1257,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData } } - /* Process Locked */ __HAL_LOCK(huart); huart->pTxBuffPtr = pData; @@ -1304,7 +1280,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT_FIFOEN; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the TX FIFO threshold interrupt */ @@ -1322,7 +1297,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the Transmit Data Register Empty interrupt */ @@ -1340,12 +1314,15 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) * (as received data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1369,7 +1346,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, } } - /* Process Locked */ __HAL_LOCK(huart); huart->pRxBuffPtr = pData; @@ -1399,7 +1375,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, huart->RxISR = UART_RxISR_8BIT_FIFOEN; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ @@ -1418,7 +1393,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, huart->RxISR = UART_RxISR_8BIT; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ @@ -1436,12 +1410,15 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1465,7 +1442,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat } } - /* Process Locked */ __HAL_LOCK(huart); huart->pTxBuffPtr = pData; @@ -1495,7 +1471,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Restore huart->gState to ready */ @@ -1507,7 +1482,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the DMA transfer for transmit request by setting the DMAT bit @@ -1527,12 +1501,15 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat * @note When the UART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1556,7 +1533,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData } } - /* Process Locked */ __HAL_LOCK(huart); huart->pRxBuffPtr = pData; @@ -1585,7 +1561,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Restore huart->gState to ready */ @@ -1594,7 +1569,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ @@ -1625,7 +1599,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) const HAL_UART_StateTypeDef gstate = huart->gState; const HAL_UART_StateTypeDef rxstate = huart->RxState; - /* Process Locked */ __HAL_LOCK(huart); if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && @@ -1645,7 +1618,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1658,7 +1630,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_BUSY_TX) @@ -1679,7 +1650,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1764,7 +1734,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1841,7 +1811,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Reset Handle ErrorCode to No Error */ huart->ErrorCode = HAL_UART_ERROR_NONE; return HAL_OK; @@ -1858,7 +1827,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TCIE, TXEIE and TXFTIE interrupts */ @@ -1916,7 +1885,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ @@ -1976,7 +1945,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { uint32_t abortcplt = 1U; @@ -2120,7 +2089,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable interrupts */ @@ -2210,7 +2179,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -2665,7 +2634,6 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2686,7 +2654,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2717,7 +2684,6 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2729,7 +2695,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2742,7 +2707,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2754,7 +2718,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2771,7 +2734,6 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2781,7 +2743,6 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2792,8 +2753,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief UART Peripheral State functions - * + * @brief UART Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -2815,7 +2776,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = huart->gState; temp2 = huart->RxState; @@ -2827,7 +2789,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code -*/ + */ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { return huart->ErrorCode; @@ -2881,6 +2843,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) uint32_t usartdiv = 0x00000000U; HAL_StatusTypeDef ret = HAL_OK; uint32_t lpuart_ker_ck_pres = 0x00000000U; + uint32_t pclk; /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); @@ -2976,13 +2939,15 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_HSI: usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_LSE: usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); @@ -3010,13 +2975,15 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_HSI: usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_LSE: usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); @@ -3043,13 +3010,15 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_HSI: usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_LSE: usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); @@ -3196,7 +3165,6 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -3211,7 +3179,8 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) @@ -3228,7 +3197,6 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_TIMEOUT; diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c index 5116c9e443d740a0673cba2b0597202a4ec48965..38b349b71ddb8dfa68372a06c90a29ada7391bb0 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c @@ -74,9 +74,6 @@ /** @defgroup UARTEx_Private_Functions UARTEx Private Functions * @{ */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -extern void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); /** @@ -166,7 +163,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); * oversampling rate). * @retval HAL status */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) { uint32_t temp; @@ -317,7 +315,7 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions * @brief Extended Peripheral Control functions - * + * @verbatim =============================================================================== ##### Peripheral Control functions ##### diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c index d4e4abb4849a0af69f3a8cb75f28d9a579bcbde6..d1707274f880afa7caf3662db00209c8e3c22980 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c @@ -190,7 +190,8 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma); static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); @@ -421,7 +422,8 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) * @param pCallback pointer to the Callback function * @retval HAL status + */ -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -733,12 +735,15 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /** * @brief Simplex send an amount of data in blocking mode. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData. * @param husart USART handle. - * @param pTxData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pTxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ @@ -840,14 +845,17 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Receive an amount of data in blocking mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) * (as received data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData. * @param husart USART handle. - * @param pRxData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pRxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Timeout duration. * @retval HAL status */ @@ -965,17 +973,21 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send and Receive an amount of data in blocking mode. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits) * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData. * @param husart USART handle. - * @param pTxData pointer to TX data buffer. - * @param pRxData pointer to RX data buffer. - * @param Size amount of data to be sent (same amount to be received). + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint8_t *prxdata8bits; uint16_t *prxdata16bits; @@ -1125,12 +1137,15 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Send an amount of data in interrupt mode. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData. * @param husart USART handle. - * @param pTxData pointer to data buffer. - * @param Size amount of data to be sent. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) @@ -1218,14 +1233,17 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /** * @brief Receive an amount of data in interrupt mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) * (as received data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData. * @param husart USART handle. - * @param pRxData pointer to data buffer. - * @param Size amount of data to be received. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -1335,16 +1353,20 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits) * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData. * @param husart USART handle. - * @param pTxData pointer to TX data buffer. - * @param pRxData pointer to RX data buffer. - * @param Size amount of data to be sent (same amount to be received). + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) @@ -1445,12 +1467,15 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /** * @brief Send an amount of data in DMA mode. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData. * @param husart USART handle. - * @param pTxData pointer to data buffer. - * @param Size amount of data to be sent. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) @@ -1540,14 +1565,17 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p * @brief Receive an amount of data in DMA mode. * @note When the USART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). - * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData. * @param husart USART handle. - * @param pRxData pointer to data buffer. - * @param Size amount of data to be received. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -1670,16 +1698,20 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits) * (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData. * @param husart USART handle. - * @param pTxData pointer to TX data buffer. - * @param pRxData pointer to RX data buffer. - * @param Size amount of data to be received/sent. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received/sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { HAL_StatusTypeDef status; uint32_t *tmp; @@ -1956,11 +1988,12 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) { /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* Disable the USART DMA Tx request if enabled */ @@ -2051,13 +2084,14 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) { uint32_t abortcplt = 1U; /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised @@ -2517,8 +2551,8 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) */ /** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief USART Peripheral State and Error functions - * + * @brief USART Peripheral State and Error functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -2564,8 +2598,8 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) */ /** @defgroup USART_Private_Functions USART Private Functions - * @{ - */ + * @{ + */ /** * @brief Initialize the callbacks to their default values. @@ -2596,7 +2630,8 @@ void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart) static void USART_EndTransfer(USART_HandleTypeDef *husart) { /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* At end of process, restore husart->State to Ready */ @@ -2904,7 +2939,8 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) * @param Timeout timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) @@ -2938,6 +2974,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) HAL_StatusTypeDef ret = HAL_OK; uint16_t brrtemp; uint32_t usartdiv = 0x00000000; + uint32_t pclk; /* Check the parameters */ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); @@ -2984,13 +3021,15 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) switch (clocksource) { case USART_CLOCKSOURCE_PCLK1: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_HSI: usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_LSE: usartdiv = (uint32_t)(USART_DIV_SAMPLING8((uint32_t)LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); @@ -3299,6 +3338,7 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) const HAL_USART_StateTypeDef state = husart->State; uint16_t txdatacount; uint16_t uhMask = husart->Mask; + uint32_t txftie; if ((state == HAL_USART_STATE_BUSY_RX) || (state == HAL_USART_STATE_BUSY_TX_RX)) @@ -3318,7 +3358,8 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) /* Clear RxISR function pointer */ husart->RxISR = NULL; - /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); txdatacount = husart->TxXferCount; if (state == HAL_USART_STATE_BUSY_RX) @@ -3342,6 +3383,7 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ @@ -3388,6 +3430,7 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) uint16_t txdatacount; uint16_t *tmp; uint16_t uhMask = husart->Mask; + uint32_t txftie; if ((state == HAL_USART_STATE_BUSY_RX) || (state == HAL_USART_STATE_BUSY_TX_RX)) @@ -3408,7 +3451,8 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) /* Clear RxISR function pointer */ husart->RxISR = NULL; - /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); txdatacount = husart->TxXferCount; if (state == HAL_USART_STATE_BUSY_RX) @@ -3432,6 +3476,7 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ @@ -3479,6 +3524,7 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) uint16_t rxdatacount; uint16_t uhMask = husart->Mask; uint16_t nb_rx_data; + uint32_t txftie; /* Check that a Rx process is ongoing */ if ((state == HAL_USART_STATE_BUSY_RX) || @@ -3503,7 +3549,8 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) /* Clear RxISR function pointer */ husart->RxISR = NULL; - /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); txdatacount = husart->TxXferCount; if (state == HAL_USART_STATE_BUSY_RX) @@ -3528,6 +3575,7 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ @@ -3609,6 +3657,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) uint16_t *tmp; uint16_t uhMask = husart->Mask; uint16_t nb_rx_data; + uint32_t txftie; /* Check that a Tx process is ongoing */ if ((state == HAL_USART_STATE_BUSY_RX) || @@ -3634,7 +3683,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) /* Clear RxISR function pointer */ husart->RxISR = NULL; - /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); txdatacount = husart->TxXferCount; if (state == HAL_USART_STATE_BUSY_RX) @@ -3659,6 +3709,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart_ex.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart_ex.c index 469123cf3a87e0dd64b71f99ffc3a3eb4cce1e52..5a2323ff9aadea4776c10b02e81f4cea6385b3d0 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart_ex.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart_ex.c @@ -54,11 +54,17 @@ #ifdef HAL_USART_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Constants USARTEx Private Constants + * @{ + */ /* UART RX FIFO depth */ #define RX_FIFO_DEPTH 8U /* UART TX FIFO depth */ #define TX_FIFO_DEPTH 8U +/** + * @} + */ /* Private define ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c index 7d7593ee7560b646a6bab3a85e82161f2d7db02c..f37aac564e529c0f085aacfe7204e9c8e301c6c8 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c @@ -33,16 +33,18 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) @56 MHz(PCLK1) with zero prescaler: - max timeout before reset: ~73.14 µs + max timeout before reset: approximately 73.14 microseconds (++) Counter max (T[5;0] = 0x3F) @56 MHz(PCLK1) with prescaler dividing by 128: - max timeout before reset: ~599.18 ms + max timeout before reset: approximately 599.18 milliseconds ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] + *** Common driver usage *** =========================== + + [..] (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). (+) Set the WWDG prescaler, refresh window and counter value using HAL_WWDG_Init() function. @@ -59,9 +61,10 @@ HAL_WWDG_Refresh() function. This operation must occur only when the counter is lower than the refresh window value already programmed. - [..] *** Callback registration *** ============================= + + [..] The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_WWDG_RegisterCallback() to register a user callback. @@ -79,12 +82,14 @@ This function allows to reset following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. - + + [..] When calling @ref HAL_WWDG_Init function, callbacks are reset to the corresponding legacy weak (surcharged) functions: @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have not been registered before. + [..] When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c index cddebbae78290cc3f83644f490d3ccb6a7c21b85..6b95fef65e1477cddf7ab4861594bedc2a56e848 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c @@ -46,7 +46,7 @@ */ /* Definitions of ADC hardware constraints delays */ -/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ +/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ /* not timeout values: */ /* Timeout values for ADC operations are dependent to device clock */ /* configuration (system clock versus ADC clock), */ @@ -363,6 +363,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) { /* Time-out error */ status = ERROR; + break; } } @@ -378,6 +379,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) { /* Time-out error */ status = ERROR; + break; } } } @@ -439,7 +441,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) CLEAR_BIT(ADCx->CFGR2, ( ADC_CFGR2_CKMODE | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR - | ADC_CFGR2_OVSE | ADC_CFGR2_CKMODE ) + | ADC_CFGR2_OVSE ) ); /* Reset register SMPR */ @@ -472,6 +474,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) { /* Time-out error */ status = ERROR; + break; } } @@ -567,12 +570,18 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) | ADC_InitStruct->LowPowerMode ); + MODIFY_REG(ADCx->CFGR2, + ADC_CFGR2_CKMODE + , + ADC_InitStruct->Clock + ); } else { /* Initialization error: ADC instance is not disabled. */ status = ERROR; } + return status; } diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c index cf119c69fce6c24185998ad48d7d84b0c572ca40..b57b57f4a0cb4dbeb44cbbcaad65c2824640d5c1 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c @@ -22,9 +22,9 @@ #include "stm32g0xx_ll_comp.h" #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32G0xx_LL_Driver @@ -131,13 +131,13 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(COMPx)); - + /* Note: Hardware constraint (refer to description of this function): */ /* COMP instance must not be locked. */ - if(LL_COMP_IsLocked(COMPx) == 0UL) + if (LL_COMP_IsLocked(COMPx) == 0UL) { LL_COMP_WriteReg(COMPx, CSR, 0x00000000UL); @@ -149,7 +149,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) /* The only way to unlock the comparator is a device hardware reset. */ status = ERROR; } - + return status; } @@ -168,7 +168,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(COMPx)); assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode)); @@ -177,10 +177,10 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis)); assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity)); assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMP_InitStruct->OutputBlankingSource)); - + /* Note: Hardware constraint (refer to description of this function) */ /* COMP instance must not be locked. */ - if(LL_COMP_IsLocked(COMPx) == 0UL) + if (LL_COMP_IsLocked(COMPx) == 0UL) { /* Configuration of comparator instance : */ /* - PowerMode */ @@ -190,14 +190,14 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru /* - OutputPolarity */ /* - OutputBlankingSource */ MODIFY_REG(COMPx->CSR, - COMP_CSR_PWRMODE + COMP_CSR_PWRMODE | COMP_CSR_INPSEL | COMP_CSR_INMSEL | COMP_CSR_HYST | COMP_CSR_POLARITY | COMP_CSR_BLANKING - , - COMP_InitStruct->PowerMode + , + COMP_InitStruct->PowerMode | COMP_InitStruct->InputPlus | COMP_InitStruct->InputMinus | COMP_InitStruct->InputHysteresis @@ -211,7 +211,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru /* Initialization error: COMP instance is locked. */ status = ERROR; } - + return status; } diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dac.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dac.c index 8bb57460457edbacc916f624ef928316d72c2da0..135842ae3aa3e5eacd4e68320d708a04bfe7610b 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dac.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dac.c @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -194,7 +194,8 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration)); if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) { - assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration, DAC_InitStruct->WaveAutoGenerationConfig)); + assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration, + DAC_InitStruct->WaveAutoGenerationConfig)); } /* Note: Hardware constraint (refer to description of this function) */ @@ -233,7 +234,6 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } - MODIFY_REG(DACx->MCR, (DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0 diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c index a3dcbd234bd0b3500d4b41ded013cfb328398a47..9c862c2824fe99f1ed53697f3ad80b209f83382e 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c @@ -67,7 +67,13 @@ #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) -#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= 40U) +#if defined(STM32G081xx)||defined(STM32G071xx) +#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_REQ_UCPD2_TX) +#elif defined(STM32G070xx) +#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_REQ_USART4_TX) +#elif defined(STM32G041xx)||defined(STM32G031xx)||defined(STM32G030xx) +#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_REQ_USART2_TX) +#endif #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ @@ -83,6 +89,13 @@ ((CHANNEL) == LL_DMA_CHANNEL_5) || \ ((CHANNEL) == LL_DMA_CHANNEL_6) || \ ((CHANNEL) == LL_DMA_CHANNEL_7)))) +#elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5)))) #endif /** * @} @@ -117,7 +130,6 @@ */ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) { - DMA_Channel_TypeDef *tmp; ErrorStatus status = SUCCESS; /* Check the DMA Instance DMAx and Channel parameters*/ @@ -150,22 +162,24 @@ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) } else { + DMA_Channel_TypeDef *tmp; + tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); /* Disable the selected DMAx_Channely */ CLEAR_BIT(tmp->CCR, DMA_CCR_EN); /* Reset DMAx_Channely control register */ - LL_DMA_WriteReg((tmp), CCR, 0U); + WRITE_REG(tmp->CCR, 0U); /* Reset DMAx_Channely remaining bytes register */ - LL_DMA_WriteReg((tmp), CNDTR, 0U); + WRITE_REG(tmp->CNDTR, 0U); /* Reset DMAx_Channely peripheral address register */ - LL_DMA_WriteReg((tmp), CPAR, 0U); + WRITE_REG(tmp->CPAR, 0U); /* Reset DMAx_Channely memory address register */ - LL_DMA_WriteReg((tmp), CMAR, 0U); + WRITE_REG(tmp->CMAR, 0U); /* Reset Request register field for DMAx Channel */ LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM); diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c index 887a9437157b1d9da5a6dc389794cb7854aa4ac3..f1740a159adfe21d6996359bff9f8c08b6a89427 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c @@ -31,7 +31,7 @@ * @{ */ -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOF) +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) /** @addtogroup GPIO_LL * @{ @@ -128,6 +128,13 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOD); } #endif /* GPIOD */ +#if defined(GPIOE) + else if (GPIOx == GPIOE) + { + LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOE); + LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOE); + } +#endif /* GPIOE */ #if defined(GPIOF) else if (GPIOx == GPIOF) { @@ -251,7 +258,7 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) * @} */ -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOF) */ +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ /** * @} diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lpuart.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lpuart.c index 21a4a090eebf60cd256f097cf7c9e5f8ae83cdc4..a334a9864d1e0cd11142e57501a1084f2095dc4b 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lpuart.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lpuart.c @@ -22,11 +22,11 @@ #include "stm32g0xx_ll_lpuart.h" #include "stm32g0xx_ll_rcc.h" #include "stm32g0xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -58,17 +58,17 @@ /* Check of parameters for configuration of LPUART registers */ #define IS_LL_LPUART_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */ /* value : */ @@ -85,25 +85,25 @@ #define IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU) #define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) + || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) #define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \ - || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ - || ((__VALUE__) == LL_LPUART_PARITY_ODD)) + || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ + || ((__VALUE__) == LL_LPUART_PARITY_ODD)) #define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \ - || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) + || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) #define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \ - || ((__VALUE__) == LL_LPUART_STOPBITS_2)) + || ((__VALUE__) == LL_LPUART_STOPBITS_2)) #define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) /** * @} diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c index 73d7fbd7f288b784117ac4511d7487d51c8e408e..c0396b1ca1d4ed0bd89272e70f3d141f3256869e 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c @@ -45,6 +45,8 @@ #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx) #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) +#elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE) #endif #if defined(LPUART1) diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c index 8587734ee40af9597680623bc1c47e546b5b1b22..f9690a0c4d2f5e9d9844c8b00c3f7ef94679f327 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -42,7 +42,7 @@ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_LL_Private_Macros RNG Private Macros +/** @addtogroup RNG_LL_Private_Macros * @{ */ #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \ @@ -51,7 +51,6 @@ /** * @} */ - /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -74,20 +73,18 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); - /* Enable RNG reset state */ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG); /* Release RNG from reset state */ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG); - return (SUCCESS); } /** * @brief Initialize RNG registers according to the specified parameters in RNG_InitStruct. * @param RNGx RNG Instance - * @param RNG_InitStruct: pointer to a LL_RNG_InitTypeDef structure + * @param RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure * that contains the configuration information for the specified RNG peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content @@ -107,7 +104,7 @@ ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) /** * @brief Set each @ref LL_RNG_InitTypeDef field to default value. - * @param RNG_InitStruct Pointer to a @ref LL_RNG_InitTypeDef structure + * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -117,7 +114,6 @@ void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct) RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE; } - /** * @} */ @@ -130,7 +126,7 @@ void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct) * @} */ -#endif /* defined (RNG) */ +#endif /* RNG */ /** * @} diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c index e44b25c5fd8032cd7eba638551c62c8952fa0018..ef368f2b3023a45e639fef1abad382c009a01f8b 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c @@ -169,7 +169,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) @@ -358,7 +358,7 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) /** * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure * @retval An ErrorStatus enumeration value: @@ -488,7 +488,7 @@ void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). * @param SPIx SPI Instance - * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF. + * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. * @param PrescalerParity This parameter can be one of the following values: * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c index 57cf1c08b0a0acd49f91c0f715a3b89ca8dcf1cd..25e756fb81f6fceb5f36d49d7c4496252b9bee18 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -46,141 +46,141 @@ * @{ */ #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ - || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) + || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ - || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ - || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ - || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) + || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) + || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ - || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \ - || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL)) + || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL)) #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ - || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) + || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \ - || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL)) #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ - || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) /** * @} */ @@ -699,12 +699,12 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * and DTG[7:0] can be write-locked depending on the LOCK configuration, it * can be necessary to configure all of them during the first write access to * the TIMx_BDTR register. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @param TIMx Timer Instance - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure) + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable @@ -770,7 +770,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT */ /** @addtogroup TIM_LL_Private_Functions TIM Private Functions - * @brief Private functions + * @brief Private functions * @{ */ /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_ucpd.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_ucpd.c index ad1e324af5ee61addefbe34ec8e577d56261e7c4..84d68f1370d699073d7df33fd370b2a707a3f1b4 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_ucpd.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_ucpd.c @@ -119,7 +119,7 @@ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) /** * @brief Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct. * @note As some bits in ucpd configuration registers can only be written when the ucpd is disabled (ucpd_CR1_SPE bit =0), - * UCPD IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * UCPD peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @param UCPDx UCPD Instance * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains * the configuration information for the UCPD peripheral. @@ -145,8 +145,8 @@ ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStru /*---------------------------- UCPDx CFG1 Configuration ------------------------*/ MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV, - UCPD_InitStruct->psc_ucpdclk | UCPD_InitStruct->transwin | - UCPD_InitStruct->IfrGap | UCPD_InitStruct->HbitClockDiv); + UCPD_InitStruct->psc_ucpdclk | (UCPD_InitStruct->transwin << UCPD_CFG1_TRANSWIN_Pos) | + (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv); return SUCCESS; } @@ -160,10 +160,10 @@ ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStru void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct) { /* Set UCPD_InitStruct fields to default values */ - UCPD_InitStruct->psc_ucpdclk = 0x0; - UCPD_InitStruct->transwin = 0x3800; - UCPD_InitStruct->IfrGap = 0x400; - UCPD_InitStruct->HbitClockDiv = 0x19; + UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV1; + UCPD_InitStruct->transwin = 0x7; /* Divide by 8 */ + UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ + UCPD_InitStruct->HbitClockDiv = 0x19; /* Divide by 26 to produce HBITCLK */ } /** diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c index 52eed5386b17b4819b68c68e5ca4ebefabfc2f90..bfae03ffe39f360b6bbbc3b131bd3b561240f298 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c @@ -22,11 +22,11 @@ #include "stm32g0xx_ll_usart.h" #include "stm32g0xx_ll_rcc.h" #include "stm32g0xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -41,31 +41,23 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup USART_LL_Private_Constants - * @{ - */ - -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /** @addtogroup USART_LL_Private_Macros * @{ */ #define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) + || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available * divided by the smallest oversampling used on the USART (i.e. 8) */ @@ -78,42 +70,42 @@ #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_USART_DIRECTION_RX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ - || ((__VALUE__) == LL_USART_PARITY_EVEN) \ - || ((__VALUE__) == LL_USART_PARITY_ODD)) + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ - || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ - || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ - || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ - || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ - || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_1) \ - || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_2)) + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) /** * @} @@ -207,7 +199,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; #if !defined(RCC_CCIPR_USART3SEL)&&!defined(RCC_CCIPR_USART4SEL)||!defined(RCC_CCIPR_USART2SEL) LL_RCC_ClocksTypeDef RCC_Clocks; -#endif +#endif /* !RCC_CCIPR_USART3SEL && !RCC_CCIPR_USART4SEL || !RCC_CCIPR_USART2SEL */ /* Check the parameters */ assert_param(IS_UART_INSTANCE(USARTx)); @@ -265,7 +257,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* USART2 clock is PCLK */ LL_RCC_GetSystemClocksFreq(&RCC_Clocks); periphclk = RCC_Clocks.PCLK1_Frequency; -#endif +#endif /* RCC_CCIPR_USART2SEL */ } #if defined(USART3) else if (USARTx == USART3) @@ -276,7 +268,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* USART3 clock is PCLK */ LL_RCC_GetSystemClocksFreq(&RCC_Clocks); periphclk = RCC_Clocks.PCLK1_Frequency; -#endif +#endif /* RCC_CCIPR_USART3SEL */ } #endif /* USART3 */ #if defined(USART4) @@ -288,7 +280,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* USART4 clock is PCLK1 */ LL_RCC_GetSystemClocksFreq(&RCC_Clocks); periphclk = RCC_Clocks.PCLK1_Frequency; -#endif +#endif /* RCC_CCIPR_USART4SEL */ } #endif /* USART4 */ else diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c index ebd31aeb83d6005afc58303ec4538e0df8ab7e7b..3e08ffcfd8e069d31c0ccb822472938e1a92d5df 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -99,7 +99,7 @@ || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ || ((__VALUE__) == LL_RCC_PLLM_DIV_8)) -#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86)) +#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \ || ((__VALUE__) == LL_RCC_PLLR_DIV_3) \