diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c index fd4212e92ce59edcc3a324d42dd0146a8edef1a7..8223a54e6a576c1fd340b81531967aa6ec11a841 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c @@ -44,63 +44,63 @@ static rt_uint32_t n32_adc_get_channel(rt_uint32_t channel) switch (channel) { - case 0: - n32_channel = ADC_CH_0; - break; - case 1: - n32_channel = ADC_CH_1; - break; - case 2: - n32_channel = ADC_CH_2; - break; - case 3: - n32_channel = ADC_CH_3; - break; - case 4: - n32_channel = ADC_CH_4; - break; - case 5: - n32_channel = ADC_CH_5; - break; - case 6: - n32_channel = ADC_CH_6; - break; - case 7: - n32_channel = ADC_CH_7; - break; - case 8: - n32_channel = ADC_CH_8; - break; - case 9: - n32_channel = ADC_CH_9; - break; - case 10: - n32_channel = ADC_CH_10; - break; - case 11: - n32_channel = ADC_CH_11; - break; - case 12: - n32_channel = ADC_CH_12; - break; - case 13: - n32_channel = ADC_CH_13; - break; - case 14: - n32_channel = ADC_CH_14; - break; - case 15: - n32_channel = ADC_CH_15; - break; - case 16: - n32_channel = ADC_CH_16; - break; - case 17: - n32_channel = ADC_CH_17; - break; - case 18: - n32_channel = ADC_CH_18; - break; + case 0: + n32_channel = ADC_CH_0; + break; + case 1: + n32_channel = ADC_CH_1; + break; + case 2: + n32_channel = ADC_CH_2; + break; + case 3: + n32_channel = ADC_CH_3; + break; + case 4: + n32_channel = ADC_CH_4; + break; + case 5: + n32_channel = ADC_CH_5; + break; + case 6: + n32_channel = ADC_CH_6; + break; + case 7: + n32_channel = ADC_CH_7; + break; + case 8: + n32_channel = ADC_CH_8; + break; + case 9: + n32_channel = ADC_CH_9; + break; + case 10: + n32_channel = ADC_CH_10; + break; + case 11: + n32_channel = ADC_CH_11; + break; + case 12: + n32_channel = ADC_CH_12; + break; + case 13: + n32_channel = ADC_CH_13; + break; + case 14: + n32_channel = ADC_CH_14; + break; + case 15: + n32_channel = ADC_CH_15; + break; + case 16: + n32_channel = ADC_CH_16; + break; + case 17: + n32_channel = ADC_CH_17; + break; + case 18: + n32_channel = ADC_CH_18; + break; } return n32_channel; @@ -124,27 +124,23 @@ static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe ADC_InitStructure.ChsNumber = 1; ADC_Init(n32_adc_handler, &ADC_InitStructure); - /* ADCx regular channels configuration */ - ADC_ConfigRegularChannel(n32_adc_handler, n32_adc_get_channel(channel), 1, ADC_SAMP_TIME_28CYCLES5); - if (((n32_adc_handler == ADC2) || (n32_adc_handler == ADC2)) - && ((n32_adc_get_channel(channel) == ADC_CH_16) || (n32_adc_get_channel(channel) == ADC_CH_18))) + && ((n32_adc_get_channel(channel) == ADC_CH_16) + || (n32_adc_get_channel(channel) == ADC_CH_18))) { ADC_EnableTempSensorVrefint(ENABLE); } - /* Enable ADCx */ - ADC_Enable(n32_adc_handler, ENABLE); - - /* Start ADCx calibration */ - ADC_StartCalibration(n32_adc_handler); - /* Check the end of ADCx calibration */ - while(ADC_GetCalibrationStatus(n32_adc_handler)); - if (enabled) { /* Enable ADC1 */ ADC_Enable(n32_adc_handler, ENABLE); + /*Check ADC Ready*/ + while (ADC_GetFlagStatusNew(n32_adc_handler, ADC_FLAG_RDY) == RESET); + /* Start ADCx calibration */ + ADC_StartCalibration(n32_adc_handler); + /* Check the end of ADCx calibration */ + while (ADC_GetCalibrationStatus(n32_adc_handler)); } else { @@ -164,11 +160,16 @@ static rt_err_t n32_get_adc_value(struct rt_adc_device *device, rt_uint32_t chan n32_adc_handler = device->parent.user_data; + /* ADCx regular channels configuration */ + ADC_ConfigRegularChannel(n32_adc_handler, n32_adc_get_channel(channel), 1, ADC_SAMP_TIME_28CYCLES5); + /* Start ADCx Software Conversion */ ADC_EnableSoftwareStartConv(n32_adc_handler, ENABLE); /* Wait for the ADC to convert */ - while(ADC_GetFlagStatus(n32_adc_handler, ADC_FLAG_ENDC) == RESET); + while (ADC_GetFlagStatus(n32_adc_handler, ADC_FLAG_ENDC) == RESET); + + ADC_ClearFlag(n32_adc_handler, ADC_FLAG_ENDC); /* get ADC value */ *value = ADC_GetDat(n32_adc_handler); @@ -191,8 +192,8 @@ static int rt_hw_adc_init(void) { /* register ADC device */ if (rt_hw_adc_register(&n32_adc_obj[i].n32_adc_device, - n32_adc_obj[i].name, &at_adc_ops, - n32_adc_obj[i].ADC_Handler) == RT_EOK) + n32_adc_obj[i].name, &at_adc_ops, + n32_adc_obj[i].ADC_Handler) == RT_EOK) { LOG_D("%s register success", n32_adc_obj[i].name); } diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_common.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_common.c index fc46b2065dd830b25c9398ff0aeb1dc8ea1f4155..d70dfb2789f47b3e21afe8a5ce4665a942e36a1e 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_common.c +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_common.c @@ -12,11 +12,11 @@ #include "board.h" #ifdef RT_USING_SERIAL -#ifdef RT_USING_SERIAL_V2 -#include "drv_usart_v2.h" -#else -#include "drv_usart.h" -#endif + #ifdef RT_USING_SERIAL_V2 + #include "drv_usart_v2.h" + #else + #include "drv_usart.h" + #endif #endif #ifdef RT_USING_FINSH diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_common.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_common.h index 9f053e4a07885c5c4ff01d4f4b4b573f687edc05..9fb8b211d783fc2477e8edfd7c9a8ab2101948e8 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_common.h +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_common.h @@ -14,7 +14,7 @@ #include #include #ifdef RT_USING_DEVICE -#include + #include #endif #ifdef __cplusplus diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c index 85839243c8d752b17cfc1f6642f22221502d24b6..637562bf3b4a8532e57c0e7e7c3588218306727e 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c @@ -15,7 +15,7 @@ #include "drv_flash.h" #if defined(PKG_USING_FAL) -#include "fal.h" + #include "fal.h" #endif //#define DRV_DEBUG @@ -147,11 +147,11 @@ int n32_flash_erase(rt_uint32_t addr, size_t size) return -RT_EINVAL; } - while(addr < end_addr) + while (addr < end_addr) { page_addr = get_page(addr); - if(FLASH_EraseOnePage(page_addr) != FLASH_COMPL) + if (FLASH_EraseOnePage(page_addr) != FLASH_COMPL) { result = -RT_ERROR; goto __exit; @@ -160,10 +160,10 @@ int n32_flash_erase(rt_uint32_t addr, size_t size) addr += FLASH_PAGE_SIZE; } - FLASH_Lock(); + FLASH_Lock(); __exit: - if(result != RT_EOK) + if (result != RT_EOK) { return result; } diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c index 87975f995b1c957d89985b6b1d28cd1bac2b5556..690253959f8c34c0fbe2a505c088ad5dfff4ca30 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c @@ -573,9 +573,9 @@ void n32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) { int i; - for(i = 0; i < 32; i++) + for (i = 0; i < 32; i++) { - if((0x01 << i) == bit) + if ((0x01 << i) == bit) { return i; } @@ -585,7 +585,7 @@ rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) { rt_int32_t mapindex = bit2bitno(pinbit); - if(mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) { return RT_NULL; } @@ -604,22 +604,22 @@ rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, return -RT_ENOSYS; } irqindex = bit2bitno(index->pin); - if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) { return -RT_ENOSYS; } level = rt_hw_interrupt_disable(); - if(pin_irq_hdr_tab[irqindex].pin == pin && - pin_irq_hdr_tab[irqindex].hdr == hdr && - pin_irq_hdr_tab[irqindex].mode == mode && - pin_irq_hdr_tab[irqindex].args == args - ) + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args + ) { rt_hw_interrupt_enable(level); return RT_EOK; } - if(pin_irq_hdr_tab[irqindex].pin != -1) + if (pin_irq_hdr_tab[irqindex].pin != -1) { rt_hw_interrupt_enable(level); return -RT_EBUSY; @@ -644,13 +644,13 @@ rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) return -RT_ENOSYS; } irqindex = bit2bitno(index->pin); - if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) { return -RT_ENOSYS; } level = rt_hw_interrupt_disable(); - if(pin_irq_hdr_tab[irqindex].pin == -1) + if (pin_irq_hdr_tab[irqindex].pin == -1) { rt_hw_interrupt_enable(level); return RT_EOK; @@ -679,15 +679,15 @@ rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin, { return -RT_ENOSYS; } - if(enabled == PIN_IRQ_ENABLE) + if (enabled == PIN_IRQ_ENABLE) { irqindex = bit2bitno(index->pin); - if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) { return -RT_ENOSYS; } level = rt_hw_interrupt_disable(); - if(pin_irq_hdr_tab[irqindex].pin == -1) + if (pin_irq_hdr_tab[irqindex].pin == -1) { rt_hw_interrupt_enable(level); return -RT_ENOSYS; @@ -701,35 +701,35 @@ rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin, GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitPeripheral(index->gpio, &GPIO_InitStructure); - NVIC_InitStructure.NVIC_IRQChannel= irqmap->irqno; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority= 2; - NVIC_InitStructure.NVIC_IRQChannelSubPriority= 2; - NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE; + NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); GPIO_ConfigEXTILine(index->port_source, index->pin_source); EXTI_InitStructure.EXTI_Line = irqmap->irqbit; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - switch(pin_irq_hdr_tab[irqindex].mode) + switch (pin_irq_hdr_tab[irqindex].mode) { - case PIN_IRQ_MODE_RISING: - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - break; - case PIN_IRQ_MODE_FALLING: - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - break; - case PIN_IRQ_MODE_RISING_FALLING: - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; - break; + case PIN_IRQ_MODE_RISING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + break; + case PIN_IRQ_MODE_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + break; + case PIN_IRQ_MODE_RISING_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + break; } EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_InitPeripheral(&EXTI_InitStructure); rt_hw_interrupt_enable(level); } - else if(enabled == PIN_IRQ_DISABLE) + else if (enabled == PIN_IRQ_DISABLE) { irqmap = get_pin_irq_map(index->pin); - if(irqmap == RT_NULL) + if (irqmap == RT_NULL) { return -RT_ENOSYS; } @@ -768,7 +768,7 @@ INIT_BOARD_EXPORT(n32_hw_pin_init); rt_inline void pin_irq_hdr(int irqno) { EXTI_ClrITPendBit(pin_irq_map[irqno].irqbit); - if(pin_irq_hdr_tab[irqno].hdr) + if (pin_irq_hdr_tab[irqno].hdr) { pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); } @@ -817,23 +817,23 @@ void EXTI9_5_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if(EXTI_GetITStatus(EXTI_LINE5) != RESET) + if (EXTI_GetITStatus(EXTI_LINE5) != RESET) { pin_irq_hdr(5); } - if(EXTI_GetITStatus(EXTI_LINE6) != RESET) + if (EXTI_GetITStatus(EXTI_LINE6) != RESET) { pin_irq_hdr(6); } - if(EXTI_GetITStatus(EXTI_LINE7) != RESET) + if (EXTI_GetITStatus(EXTI_LINE7) != RESET) { pin_irq_hdr(7); } - if(EXTI_GetITStatus(EXTI_LINE8) != RESET) + if (EXTI_GetITStatus(EXTI_LINE8) != RESET) { pin_irq_hdr(8); } - if(EXTI_GetITStatus(EXTI_LINE9) != RESET) + if (EXTI_GetITStatus(EXTI_LINE9) != RESET) { pin_irq_hdr(9); } @@ -844,27 +844,27 @@ void EXTI15_10_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if(EXTI_GetITStatus(EXTI_LINE10) != RESET) + if (EXTI_GetITStatus(EXTI_LINE10) != RESET) { pin_irq_hdr(10); } - if(EXTI_GetITStatus(EXTI_LINE11) != RESET) + if (EXTI_GetITStatus(EXTI_LINE11) != RESET) { pin_irq_hdr(11); } - if(EXTI_GetITStatus(EXTI_LINE12) != RESET) + if (EXTI_GetITStatus(EXTI_LINE12) != RESET) { pin_irq_hdr(12); } - if(EXTI_GetITStatus(EXTI_LINE13) != RESET) + if (EXTI_GetITStatus(EXTI_LINE13) != RESET) { pin_irq_hdr(13); } - if(EXTI_GetITStatus(EXTI_LINE14) != RESET) + if (EXTI_GetITStatus(EXTI_LINE14) != RESET) { pin_irq_hdr(14); } - if(EXTI_GetITStatus(EXTI_LINE15) != RESET) + if (EXTI_GetITStatus(EXTI_LINE15) != RESET) { pin_irq_hdr(15); } diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c index 688186e920ba06acc0f59528be2af62c8bca61ea..ee2532d53b189b09585b032d9c7ce51669989691 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c @@ -82,7 +82,7 @@ enum struct n32_hwtimer { rt_hwtimer_t time_device; - TIM_Module* tim_handle; + TIM_Module *tim_handle; IRQn_Type tim_irqn; char *name; }; @@ -198,7 +198,7 @@ static void n32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); - TIM_ConfigInt(tim, TIM_INT_UPDATE ,ENABLE); + TIM_ConfigInt(tim, TIM_INT_UPDATE, ENABLE); TIM_ClrIntPendingBit(tim, TIM_INT_UPDATE); LOG_D("%s init success", tim_device->name); @@ -270,29 +270,29 @@ static rt_err_t n32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) tim = (TIM_Module *)timer->parent.user_data; - switch(cmd) + switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: - { - rt_uint32_t freq; - rt_uint16_t val; + case HWTIMER_CTRL_FREQ_SET: + { + rt_uint32_t freq; + rt_uint16_t val; - /* set timer frequence */ - freq = *((rt_uint32_t *)arg); + /* set timer frequence */ + freq = *((rt_uint32_t *)arg); - /* time init */ - RCC_GetClocksFreqValue(&RCC_ClockStruct); + /* time init */ + RCC_GetClocksFreqValue(&RCC_ClockStruct); - val = RCC_ClockStruct.SysclkFreq / freq; + val = RCC_ClockStruct.SysclkFreq / freq; - TIM_ConfigPrescaler(tim, val - 1, TIM_PSC_RELOAD_MODE_IMMEDIATE); - } - break; - default: - { - result = -RT_ENOSYS; - } - break; + TIM_ConfigPrescaler(tim, val - 1, TIM_PSC_RELOAD_MODE_IMMEDIATE); + } + break; + default: + { + result = -RT_ENOSYS; + } + break; } return result; @@ -314,7 +314,7 @@ void TIM2_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if(TIM_GetIntStatus(TIM2, TIM_INT_UPDATE) == SET) + if (TIM_GetIntStatus(TIM2, TIM_INT_UPDATE) == SET) { rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM2_INDEX].time_device); @@ -332,7 +332,7 @@ void TIM3_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if(TIM_GetIntStatus(TIM3, TIM_INT_UPDATE) == SET) + if (TIM_GetIntStatus(TIM3, TIM_INT_UPDATE) == SET) { rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM3_INDEX].time_device); @@ -350,7 +350,7 @@ void TIM4_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if(TIM_GetIntStatus(TIM4, TIM_INT_UPDATE) == SET) + if (TIM_GetIntStatus(TIM4, TIM_INT_UPDATE) == SET) { rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM4_INDEX].time_device); @@ -368,7 +368,7 @@ void TIM5_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if(TIM_GetIntStatus(TIM5, TIM_INT_UPDATE) == SET) + if (TIM_GetIntStatus(TIM5, TIM_INT_UPDATE) == SET) { rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM5_INDEX].time_device); @@ -386,7 +386,7 @@ void TIM6_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if(TIM_GetIntStatus(TIM6, TIM_INT_UPDATE) == SET) + if (TIM_GetIntStatus(TIM6, TIM_INT_UPDATE) == SET) { rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM6_INDEX].time_device); @@ -404,7 +404,7 @@ void TIM7_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if(TIM_GetIntStatus(TIM7, TIM_INT_UPDATE) == SET) + if (TIM_GetIntStatus(TIM7, TIM_INT_UPDATE) == SET) { rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM7_INDEX].time_device); diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_log.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_log.h index d91f70d37ce6517c4a1193e784fbe57e277e3287..0c8631bdbbf03e380ecc85df10760da422223fbd 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_log.h +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_log.h @@ -13,15 +13,15 @@ */ #ifndef LOG_TAG -#define DBG_TAG "drv" + #define DBG_TAG "drv" #else -#define DBG_TAG LOG_TAG + #define DBG_TAG LOG_TAG #endif /* LOG_TAG */ #ifdef DRV_DEBUG -#define DBG_LVL DBG_LOG + #define DBG_LVL DBG_LOG #else -#define DBG_LVL DBG_INFO + #define DBG_LVL DBG_INFO #endif /* DRV_DEBUG */ #include diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c index f61402c9c3ef71f116c931d19d41a26371fd6d8f..fbdb40634ecf720db7f7e694f2abe32f110d4d85 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c @@ -12,10 +12,10 @@ #include "drv_pwm.h" #ifdef RT_USING_PWM -#if !defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \ - !defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4) -#error "Please define at least one BSP_USING_TIMx_CHx" -#endif + #if !defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \ + !defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4) + #error "Please define at least one BSP_USING_TIMx_CHx" + #endif #endif /* RT_USING_PWM */ #define DRV_DEBUG @@ -28,7 +28,7 @@ struct rt_device_pwm pwm_device; struct n32_pwm { struct rt_device_pwm pwm_device; - TIM_Module* tim_handle; + TIM_Module *tim_handle; rt_uint8_t channel; char *name; }; @@ -58,45 +58,45 @@ static struct rt_pwm_ops drv_ops = drv_pwm_control }; -static rt_err_t drv_pwm_enable(TIM_Module* TIMx, struct rt_pwm_configuration *configuration, rt_bool_t enable) +static rt_err_t drv_pwm_enable(TIM_Module *TIMx, struct rt_pwm_configuration *configuration, rt_bool_t enable) { /* Get the value of channel */ rt_uint32_t channel = configuration->channel; if (!enable) { - if(channel == 1) + if (channel == 1) { TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE); } - else if(channel == 2) + else if (channel == 2) { TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE); } - else if(channel == 3) + else if (channel == 3) { TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE); } - else if(channel == 4) + else if (channel == 4) { TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE); } } else { - if(channel == 1) + if (channel == 1) { TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE); } - else if(channel == 2) + else if (channel == 2) { TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_ENABLE); } - else if(channel == 3) + else if (channel == 3) { TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_ENABLE); } - else if(channel == 4) + else if (channel == 4) { TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_ENABLE); } @@ -107,7 +107,7 @@ static rt_err_t drv_pwm_enable(TIM_Module* TIMx, struct rt_pwm_configuration *co return RT_EOK; } -static rt_err_t drv_pwm_get(TIM_Module* TIMx, struct rt_pwm_configuration *configuration) +static rt_err_t drv_pwm_get(TIM_Module *TIMx, struct rt_pwm_configuration *configuration) { RCC_ClocksType RCC_Clockstruct; rt_uint32_t ar, div, cc1, cc2, cc3, cc4; @@ -128,19 +128,19 @@ static rt_err_t drv_pwm_get(TIM_Module* TIMx, struct rt_pwm_configuration *confi /* Convert nanosecond to frequency and duty cycle. */ tim_clock /= 1000000UL; configuration->period = (ar + 1) * (div + 1) * 1000UL / tim_clock; - if(channel == 1) + if (channel == 1) configuration->pulse = (cc1 + 1) * (div + 1) * 1000UL / tim_clock; - if(channel == 2) - configuration->pulse = (cc2 + 1) * (div+ 1) * 1000UL / tim_clock; - if(channel == 3) + if (channel == 2) + configuration->pulse = (cc2 + 1) * (div + 1) * 1000UL / tim_clock; + if (channel == 3) configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock; - if(channel == 4) + if (channel == 4) configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock; return RT_EOK; } -static rt_err_t drv_pwm_set(TIM_Module* TIMx, struct rt_pwm_configuration *configuration) +static rt_err_t drv_pwm_set(TIM_Module *TIMx, struct rt_pwm_configuration *configuration) { /* Init timer pin and enable clock */ n32_msp_tim_init(TIMx); @@ -155,7 +155,7 @@ static rt_err_t drv_pwm_set(TIM_Module* TIMx, struct rt_pwm_configuration *confi } else { - if (1 == (RCC_Clock.HclkFreq/RCC_Clock.Pclk1Freq)) + if (1 == (RCC_Clock.HclkFreq / RCC_Clock.Pclk1Freq)) input_clock = RCC_Clock.Pclk1Freq; else input_clock = RCC_Clock.Pclk1Freq * 2; @@ -186,22 +186,22 @@ static rt_err_t drv_pwm_set(TIM_Module* TIMx, struct rt_pwm_configuration *confi TIM_OCInitStructure.OcPolarity = TIM_OC_POLARITY_HIGH; rt_uint32_t channel = configuration->channel; - if(channel == 1) + if (channel == 1) { TIM_InitOc1(TIMx, &TIM_OCInitStructure); TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); } - else if(channel == 2) + else if (channel == 2) { TIM_InitOc2(TIMx, &TIM_OCInitStructure); TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); } - else if(channel == 3) + else if (channel == 3) { TIM_InitOc3(TIMx, &TIM_OCInitStructure); TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); } - else if(channel == 4) + else if (channel == 4) { TIM_InitOc4(TIMx, &TIM_OCInitStructure); TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); @@ -220,16 +220,16 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg switch (cmd) { - case PWM_CMD_ENABLE: - return drv_pwm_enable(TIMx, configuration, RT_TRUE); - case PWM_CMD_DISABLE: - return drv_pwm_enable(TIMx, configuration, RT_FALSE); - case PWM_CMD_SET: - return drv_pwm_set(TIMx, configuration); - case PWM_CMD_GET: - return drv_pwm_get(TIMx, configuration); - default: - return RT_EINVAL; + case PWM_CMD_ENABLE: + return drv_pwm_enable(TIMx, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return drv_pwm_enable(TIMx, configuration, RT_FALSE); + case PWM_CMD_SET: + return drv_pwm_set(TIMx, configuration); + case PWM_CMD_GET: + return drv_pwm_get(TIMx, configuration); + default: + return RT_EINVAL; } } @@ -238,9 +238,9 @@ static int rt_hw_pwm_init(void) int i = 0; int result = RT_EOK; - for(i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++) + for (i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++) { - if(rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, n32_pwm_obj[i].tim_handle) == RT_EOK) + if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, n32_pwm_obj[i].tim_handle) == RT_EOK) { LOG_D("%s register success", n32_pwm_obj[i].name); } diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c index 0b49dba5d7ec3cd9b897793a09fe90ce31ea0697..3f5ebf450c27674d9e7122ebe5967505115a3a52 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c @@ -17,8 +17,8 @@ #include #if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) -#error "Please define at least one BSP_USING_I2Cx" -/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ + #error "Please define at least one BSP_USING_I2Cx" + /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ #endif static const struct n32_soft_i2c_config soft_i2c_config[] = @@ -46,7 +46,7 @@ static struct n32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0 */ static void n32_i2c_gpio_init(struct n32_i2c *i2c) { - struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)i2c->ops.data; + struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)i2c->ops.data; rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); @@ -63,7 +63,7 @@ static void n32_i2c_gpio_init(struct n32_i2c *i2c) */ static void n32_set_sda(void *data, rt_int32_t state) { - struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data; if (state) { rt_pin_write(cfg->sda, PIN_HIGH); @@ -82,7 +82,7 @@ static void n32_set_sda(void *data, rt_int32_t state) */ static void n32_set_scl(void *data, rt_int32_t state) { - struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data; if (state) { rt_pin_write(cfg->scl, PIN_HIGH); @@ -100,7 +100,7 @@ static void n32_set_scl(void *data, rt_int32_t state) */ static rt_int32_t n32_get_sda(void *data) { - struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data; return rt_pin_read(cfg->sda); } @@ -111,7 +111,7 @@ static rt_int32_t n32_get_sda(void *data) */ static rt_int32_t n32_get_scl(void *data) { - struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data; return rt_pin_read(cfg->scl); } /** @@ -199,7 +199,7 @@ int rt_hw_i2c_init(void) for (int i = 0; i < obj_num; i++) { i2c_obj[i].ops = n32_bit_ops_default; - i2c_obj[i].ops.data = (void*)&soft_i2c_config[i]; + i2c_obj[i].ops.data = (void *)&soft_i2c_config[i]; i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops; n32_i2c_gpio_init(&i2c_obj[i]); result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name); @@ -207,9 +207,9 @@ int rt_hw_i2c_init(void) n32_i2c_bus_unlock(&soft_i2c_config[i]); LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", - soft_i2c_config[i].bus_name, - soft_i2c_config[i].scl, - soft_i2c_config[i].sda); + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, + soft_i2c_config[i].sda); } return RT_EOK; diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c index b39298b9a0e6847061e75c05e267a8b6ed7b0a45..fae66686715e4aa8614afd724ac2804a26eaffb8 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c @@ -51,7 +51,7 @@ static void DMA_Configuration(struct rt_serial_device *serial); static rt_err_t n32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - struct n32_uart* uart; + struct n32_uart *uart; USART_InitType USART_InitStructure; RT_ASSERT(serial != RT_NULL); @@ -102,14 +102,14 @@ static rt_err_t n32_uart_configure(struct rt_serial_device *serial, struct seria /* Enable USART */ USART_Enable(uart->uart_device, ENABLE); - USART_ClrFlag(uart->uart_device, USART_FLAG_TXDE|USART_FLAG_TXC); + USART_ClrFlag(uart->uart_device, USART_FLAG_TXDE | USART_FLAG_TXC); return RT_EOK; } static rt_err_t n32_uart_control(struct rt_serial_device *serial, int cmd, void *arg) { - struct n32_uart* uart; + struct n32_uart *uart; rt_uint32_t ctrl_arg = (rt_uint32_t)(arg); RT_ASSERT(serial != RT_NULL); @@ -117,34 +117,34 @@ static rt_err_t n32_uart_control(struct rt_serial_device *serial, int cmd, void switch (cmd) { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_DISABLE_IRQ(uart->irq); /* disable interrupt */ - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - UART_DISABLE_IRQ(uart->irq); - /* disable interrupt */ - USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, DISABLE); - break; + USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, DISABLE); + break; + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_ENABLE_IRQ(uart->irq); /* enable interrupt */ - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - UART_ENABLE_IRQ(uart->irq); - /* enable interrupt */ - USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, ENABLE); - break; - /* USART config */ - case RT_DEVICE_CTRL_CONFIG : - if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) - { - DMA_Configuration(serial); - } - break; + USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, ENABLE); + break; + /* USART config */ + case RT_DEVICE_CTRL_CONFIG : + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) + { + DMA_Configuration(serial); + } + break; } return RT_EOK; } static int n32_uart_putc(struct rt_serial_device *serial, char c) { - struct n32_uart* uart; + struct n32_uart *uart; RT_ASSERT(serial != RT_NULL); uart = (struct n32_uart *)serial->parent.user_data; @@ -171,7 +171,7 @@ static int n32_uart_putc(struct rt_serial_device *serial, char c) static int n32_uart_getc(struct rt_serial_device *serial) { int ch; - struct n32_uart* uart; + struct n32_uart *uart; RT_ASSERT(serial != RT_NULL); uart = (struct n32_uart *)serial->parent.user_data; @@ -250,23 +250,23 @@ static void uart_isr(struct rt_serial_device *serial) RT_ASSERT(uart != RT_NULL); - if(USART_GetIntStatus(uart->uart_device, USART_INT_RXDNE) != RESET) + if (USART_GetIntStatus(uart->uart_device, USART_INT_RXDNE) != RESET) { - if(USART_GetFlagStatus(uart->uart_device, USART_FLAG_PEF) == RESET) + if (USART_GetFlagStatus(uart->uart_device, USART_FLAG_PEF) == RESET) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } /* clear interrupt */ USART_ClrIntPendingBit(uart->uart_device, USART_INT_RXDNE); } - if(USART_GetIntStatus(uart->uart_device, USART_INT_IDLEF) != RESET) + if (USART_GetIntStatus(uart->uart_device, USART_INT_IDLEF) != RESET) { dma_uart_rx_idle_isr(serial); } if (USART_GetIntStatus(uart->uart_device, USART_INT_TXC) != RESET) { /* clear interrupt */ - if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) + if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); } @@ -443,7 +443,7 @@ void DMA2_Channel3_IRQHandler(void) } #endif /* BSP_USING_UART4 */ -static void NVIC_Configuration(struct n32_uart* uart) +static void NVIC_Configuration(struct n32_uart *uart) { NVIC_InitType NVIC_InitStructure; @@ -473,7 +473,7 @@ static void DMA_Configuration(struct rt_serial_device *serial) /* rx dma config */ DMA_DeInit(uart->dma.rx_ch); - DMA_InitStructure.PeriphAddr = (uint32_t)&(uart->uart_device->DAT); + DMA_InitStructure.PeriphAddr = (uint32_t) & (uart->uart_device->DAT); DMA_InitStructure.MemAddr = (uint32_t)(rx_fifo->buffer); DMA_InitStructure.Direction = DMA_DIR_PERIPH_SRC; DMA_InitStructure.BufSize = serial->config.bufsz; @@ -500,7 +500,7 @@ static void DMA_Configuration(struct rt_serial_device *serial) int rt_hw_usart_init(void) { - struct n32_uart* uart; + struct n32_uart *uart; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #if defined(BSP_USING_UART1) diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/board.c b/bsp/n32g452xx/n32g452xx-mini-system/board/board.c index 4405e2894193021f19c36ad9ff89c8e9a8ff4049..f5fd86b93256238558808c4e1ca3b2a7b0852e83 100644 --- a/bsp/n32g452xx/n32g452xx-mini-system/board/board.c +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/board.c @@ -15,7 +15,7 @@ #include #ifdef BSP_USING_SRAM -#include "drv_sram.h" + #include "drv_sram.h" #endif /** * @brief This function is executed in case of error occurrence. diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c index 09d2dd80bb3e4fa24d12f26c3dbd82489d09776d..178c7d536d5b58c7e3821fea44e2469693488c16 100644 --- a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c @@ -23,7 +23,7 @@ void n32_msp_usart_init(void *Instance) GPIO_InitStruct(&GPIO_InitCtlStruct); GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz; #ifdef BSP_USING_UART1 - if(USART1 == USARTx) + if (USART1 == USARTx) { RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); @@ -37,7 +37,7 @@ void n32_msp_usart_init(void *Instance) } #endif #ifdef BSP_USING_UART2 - if(USART2 == USARTx) + if (USART2 == USARTx) { RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); @@ -51,7 +51,7 @@ void n32_msp_usart_init(void *Instance) } #endif #ifdef BSP_USING_UART3 - if(USART3 == USARTx) + if (USART3 == USARTx) { RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); @@ -65,7 +65,7 @@ void n32_msp_usart_init(void *Instance) } #endif #ifdef BSP_USING_UART4 - if(UART4 == USARTx) + if (UART4 == USARTx) { RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART4, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); @@ -91,7 +91,7 @@ void n32_msp_spi_init(void *Instance) GPIO_InitStruct(&GPIO_InitCtlStruct); GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz; #ifdef BSP_USING_SPI1 - if(SPI1 == SPIx) + if (SPI1 == SPIx) { RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI1, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); @@ -108,7 +108,7 @@ void n32_msp_spi_init(void *Instance) } #endif #ifdef BSP_USING_SPI2 - if(SPI2 == SPIx) + if (SPI2 == SPIx) { RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); @@ -137,7 +137,7 @@ void n32_msp_sdio_init(void *Instance) GPIO_InitStruct(&GPIO_InitCtlStructure); GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz; - if(SDIO == SDIOx) + if (SDIO == SDIOx) { /* if used dma ... */ RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_DMA2, ENABLE); @@ -162,7 +162,7 @@ void n32_msp_tim_init(void *Instance) GPIO_InitStruct(&GPIO_InitCtlStructure); TIM_Module *TIMx = (TIM_Module *)Instance; - if(TIMx == TIM1) + if (TIMx == TIM1) { /* TIM1 clock enable */ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE); @@ -177,7 +177,7 @@ void n32_msp_tim_init(void *Instance) GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure); } - if(TIMx == TIM2) + if (TIMx == TIM2) { /* TIM2 clock enable */ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE); @@ -192,12 +192,12 @@ void n32_msp_tim_init(void *Instance) GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure); } - if(TIMx == TIM3) + if (TIMx == TIM3) { /* TIM3 clock enable */ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE); /* GPIOA clock enable */ - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA|RCC_APB2_PERIPH_GPIOB, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA | RCC_APB2_PERIPH_GPIOB, ENABLE); GPIO_InitCtlStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7; GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP; @@ -218,15 +218,15 @@ void n32_msp_adc_init(void *Instance) ADC_Module *ADCx = (ADC_Module *)Instance; #ifdef BSP_USING_ADC1 - if(ADCx == ADC1) + if (ADCx == ADC1) { /* ADC1 & GPIO clock enable */ RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC1, ENABLE); - ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB,RCC_ADCHCLK_DIV8); + ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV8); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); /* Configure ADC Channel as analog input */ - GPIO_InitCtlStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitCtlStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3; GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_2MHz; GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AIN; GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct); @@ -234,11 +234,11 @@ void n32_msp_adc_init(void *Instance) #endif #ifdef BSP_USING_ADC2 - if(ADCx == ADC2) + if (ADCx == ADC2) { /* ADC2 & GPIO clock enable */ RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC2, ENABLE); - ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB,RCC_ADCHCLK_DIV8); + ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV8); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); /* Configure ADC Channel as analog input */ @@ -257,7 +257,7 @@ void n32_msp_hwtim_init(void *Instance) TIM_Module *TIMx = (TIM_Module *)Instance; #ifdef BSP_USING_HWTIM3 - if(TIMx == TIM3) + if (TIMx == TIM3) { /* TIM3 clock enable */ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE); @@ -265,7 +265,7 @@ void n32_msp_hwtim_init(void *Instance) #endif #ifdef BSP_USING_HWTIM4 - if(TIMx == TIM4) + if (TIMx == TIM4) { /* TIM4 clock enable */ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM4, ENABLE); @@ -273,7 +273,7 @@ void n32_msp_hwtim_init(void *Instance) #endif #ifdef BSP_USING_HWTIM5 - if(TIMx == TIM5) + if (TIMx == TIM5) { /* TIM5 clock enable */ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM5, ENABLE); @@ -281,19 +281,19 @@ void n32_msp_hwtim_init(void *Instance) #endif #ifdef BSP_USING_HWTIM6 - if(TIMx == TIM6) - { - /* TIM6 clock enable */ - RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM6, ENABLE); - } + if (TIMx == TIM6) + { + /* TIM6 clock enable */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM6, ENABLE); + } #endif #ifdef BSP_USING_HWTIM7 - if(TIMx == TIM7) - { - /* TIM7 clock enable */ - RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM7, ENABLE); - } + if (TIMx == TIM7) + { + /* TIM7 clock enable */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM7, ENABLE); + } #endif } #endif @@ -307,7 +307,7 @@ void n32_msp_can_init(void *Instance) GPIO_InitStruct(&GPIO_InitCtlStruct); GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz; #ifdef BSP_USING_CAN1 - if(CAN1 == CANx) + if (CAN1 == CANx) { RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN1, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); @@ -321,7 +321,7 @@ void n32_msp_can_init(void *Instance) } #endif #ifdef BSP_USING_CAN2 - if(CAN2 == CANx) + if (CAN2 == CANx) { RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN2, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); @@ -347,7 +347,7 @@ static void uart_test_rw(rt_device_t uartx, const char *name) if (uartx == NULL) { uartx = rt_device_find(name); - rt_err_t err = rt_device_open(uartx, RT_DEVICE_FLAG_INT_RX|RT_DEVICE_FLAG_DMA_RX); + rt_err_t err = rt_device_open(uartx, RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX); RT_ASSERT(err == RT_EOK); } rt_device_write(uartx, 0, name, strlen(name)); @@ -356,7 +356,7 @@ static void uart_test_rw(rt_device_t uartx, const char *name) int ret = rt_device_read(uartx, 0, recv_buf, sizeof(recv_buf)); if (ret != 0) { - for (int i=0; iCPU - backtrace.c + showmem.c 1 - ..\..\..\libcpu\arm\common\backtrace.c + ..\..\..\libcpu\arm\common\showmem.c @@ -404,9 +404,9 @@ - showmem.c + backtrace.c 1 - ..\..\..\libcpu\arm\common\showmem.c + ..\..\..\libcpu\arm\common\backtrace.c @@ -449,30 +449,30 @@ - workqueue.c + pipe.c 1 - ..\..\..\components\drivers\src\workqueue.c + ..\..\..\components\drivers\src\pipe.c - waitqueue.c + ringbuffer.c 1 - ..\..\..\components\drivers\src\waitqueue.c + ..\..\..\components\drivers\src\ringbuffer.c - pipe.c + completion.c 1 - ..\..\..\components\drivers\src\pipe.c + ..\..\..\components\drivers\src\completion.c - completion.c + ringblk_buf.c 1 - ..\..\..\components\drivers\src\completion.c + ..\..\..\components\drivers\src\ringblk_buf.c @@ -484,16 +484,16 @@ - ringblk_buf.c + workqueue.c 1 - ..\..\..\components\drivers\src\ringblk_buf.c + ..\..\..\components\drivers\src\workqueue.c - ringbuffer.c + waitqueue.c 1 - ..\..\..\components\drivers\src\ringbuffer.c + ..\..\..\components\drivers\src\waitqueue.c @@ -508,16 +508,16 @@ - startup_n32g45x.s - 2 - ..\Libraries\N32_Std_Driver\CMSIS\device\startup\startup_n32g45x.s + board.c + 1 + board\board.c - board.c - 1 - board\board.c + startup_n32g45x.s + 2 + ..\Libraries\N32_Std_Driver\CMSIS\device\startup\startup_n32g45x.s @@ -577,98 +577,105 @@ Kernel - clock.c + irq.c 1 - ..\..\..\src\clock.c + ..\..\..\src\irq.c - thread.c + mempool.c 1 - ..\..\..\src\thread.c + ..\..\..\src\mempool.c - mempool.c + ipc.c 1 - ..\..\..\src\mempool.c + ..\..\..\src\ipc.c - scheduler.c + clock.c 1 - ..\..\..\src\scheduler.c + ..\..\..\src\clock.c - device.c + object.c 1 - ..\..\..\src\device.c + ..\..\..\src\object.c - idle.c + timer.c 1 - ..\..\..\src\idle.c + ..\..\..\src\timer.c - ipc.c + scheduler.c 1 - ..\..\..\src\ipc.c + ..\..\..\src\scheduler.c - timer.c + device.c 1 - ..\..\..\src\timer.c + ..\..\..\src\device.c - mem.c + thread.c 1 - ..\..\..\src\mem.c + ..\..\..\src\thread.c - irq.c + components.c 1 - ..\..\..\src\irq.c + ..\..\..\src\components.c - object.c + kservice.c 1 - ..\..\..\src\object.c + ..\..\..\src\kservice.c - components.c + idle.c 1 - ..\..\..\src\components.c + ..\..\..\src\idle.c - kservice.c + mem.c 1 - ..\..\..\src\kservice.c + ..\..\..\src\mem.c libc + + + libc.c + 1 + ..\..\..\components\libc\compilers\armlibc\libc.c + + syscalls.c @@ -685,9 +692,9 @@ - libc.c + time.c 1 - ..\..\..\components\libc\compilers\armlibc\libc.c + ..\..\..\components\libc\compilers\common\time.c @@ -697,35 +704,28 @@ ..\..\..\components\libc\compilers\common\stdlib.c - - - time.c - 1 - ..\..\..\components\libc\compilers\common\time.c - - Libraries - n32g45x_rtc.c + n32g45x_wwdg.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_rtc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_wwdg.c - n32g45x_qspi.c + n32g45x_adc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_qspi.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_adc.c - n32g45x_sdio.c + n32g45x_comp.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_sdio.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_comp.c @@ -737,177 +737,178 @@ - n32g45x_bkp.c + n32g45x_i2c.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_bkp.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_i2c.c - n32g45x_dma.c + n32g45x_gpio.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dma.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_gpio.c - n32g45x_usart.c + n32g45x_pwr.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_usart.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_pwr.c - n32g45x_adc.c + n32g45x_flash.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_adc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_flash.c - n32g45x_dvp.c + n32g45x_spi.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dvp.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_spi.c - n32g45x_opamp.c + n32g45x_exti.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_opamp.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_exti.c - misc.c + n32g45x_xfmc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\misc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_xfmc.c - n32g45x_spi.c + n32g45x_rtc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_spi.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_rtc.c - n32g45x_dac.c + n32g45x_crc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dac.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_crc.c - n32g45x_exti.c + n32g45x_iwdg.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_exti.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_iwdg.c - n32g45x_gpio.c + n32g45x_qspi.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_gpio.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_qspi.c - n32g45x_xfmc.c + n32g45x_tsc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_xfmc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tsc.c - n32g45x_can.c + n32g45x_opamp.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_can.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_opamp.c - n32g45x_pwr.c + n32g45x_tim.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_pwr.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tim.c - n32g45x_i2c.c + n32g45x_bkp.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_i2c.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_bkp.c - n32g45x_wwdg.c + n32g45x_dma.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dma.c - n32g45x_dbg.c + n32g45x_rcc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dbg.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_rcc.c - n32g45x_tim.c + n32g45x_usart.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tim.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_usart.c - n32g45x_crc.c + system_n32g45x.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_crc.c + ..\Libraries\N32_Std_Driver\CMSIS\device\system_n32g45x.c - n32g45x_tsc.c + n32g45x_dvp.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tsc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dvp.c - n32g45x_iwdg.c + n32g45x_can.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_can.c - n32g45x_rcc.c + n32g45x_dbg.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_rcc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dbg.c - system_n32g45x.c + misc.c 1 - ..\Libraries\N32_Std_Driver\CMSIS\device\system_n32g45x.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\misc.c - n32g45x_comp.c + n32g45x_dac.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_comp.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dac.c - n32g45x_flash.c + n32g45x_sdio.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_flash.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_sdio.c +