From a9d8168b4d0249d9f1fecf8b8c64a82bf70f640e Mon Sep 17 00:00:00 2001 From: myshowtogo <296570182@qq.com> Date: Mon, 24 Oct 2022 17:24:00 +0800 Subject: [PATCH] =?UTF-8?q?Modified=20=20=20bsp/stm32/libraries/HAL=5FDriv?= =?UTF-8?q?ers/config/f4/dma=5Fconfig.h=20Modified=20=20=20bsp/stm32/libra?= =?UTF-8?q?ries/HAL=5FDrivers/drv=5Fusart=5Fv2.c=20=E4=BF=AE=E5=A4=8Dstm32?= =?UTF-8?q?=E7=9A=84=E4=B8=B2=E5=8F=A3=20dma=E9=85=8D=E7=BD=AE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../HAL_Drivers/config/f4/dma_config.h | 216 ++++++++++++++++-- .../libraries/HAL_Drivers/drv_usart_v2.c | 61 ++++- 2 files changed, 255 insertions(+), 22 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h index 016ec32dee..54deed1d69 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h @@ -25,6 +25,12 @@ extern "C" { #define SPI3_RX_DMA_INSTANCE DMA1_Stream0 #define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 #define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) +#define I2C1_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define I2C1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define I2C1_RX_DMA_INSTANCE DMA1_Stream0 +#define I2C1_RX_DMA_CHANNEL DMA_CHANNEL_1 +#define I2C1_RX_DMA_IRQ DMA1_Stream0_IRQn #elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) #define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler #define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN @@ -46,12 +52,12 @@ extern "C" { #define UART3_RX_DMA_INSTANCE DMA1_Stream1 #define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn -#elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) -#define UART7_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler -#define UART7_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define UART7_RX_DMA_INSTANCE DMA1_Stream1 -#define UART7_RX_DMA_CHANNEL DMA_CHANNEL_5 -#define UART7_RX_DMA_IRQ DMA1_Stream1_IRQn +#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) +#define UART7_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler +#define UART7_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART7_TX_DMA_INSTANCE DMA1_Stream1 +#define UART7_TX_DMA_CHANNEL DMA_CHANNEL_5 +#define UART7_TX_DMA_IRQ DMA1_Stream1_IRQn #endif /* DMA1 stream2 */ @@ -61,12 +67,24 @@ extern "C" { #define SPI3_RX_DMA_INSTANCE DMA1_Stream2 #define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 #define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) +#define I2C3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define I2C3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define I2C3_RX_DMA_INSTANCE DMA1_Stream2 +#define I2C3_RX_DMA_CHANNEL DMA_CHANNEL_3 +#define I2C3_RX_DMA_IRQ DMA1_Stream2_IRQn #elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) #define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler #define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART4_RX_DMA_INSTANCE DMA1_Stream2 #define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) +#define I2C2_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define I2C2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define I2C2_RX_DMA_INSTANCE DMA1_Stream2 +#define I2C2_RX_DMA_CHANNEL DMA_CHANNEL_7 +#define I2C2_RX_DMA_IRQ DMA1_Stream2_IRQn #endif /* DMA1 stream3 */ @@ -82,12 +100,18 @@ extern "C" { #define UART3_TX_DMA_INSTANCE DMA1_Stream3 #define UART3_TX_DMA_CHANNEL DMA_CHANNEL_4 #define UART3_TX_DMA_IRQ DMA1_Stream3_IRQn -#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) +#elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) #define UART7_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler #define UART7_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART7_RX_DMA_INSTANCE DMA1_Stream3 #define UART7_RX_DMA_CHANNEL DMA_CHANNEL_5 #define UART7_RX_DMA_IRQ DMA1_Stream3_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) +#define I2C2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler +#define I2C2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define I2C2_RX_DMA_INSTANCE DMA1_Stream3 +#define I2C2_RX_DMA_CHANNEL DMA_CHANNEL_7 +#define I2C2_RX_DMA_IRQ DMA1_Stream3_IRQn #endif /* DMA1 stream4 */ @@ -97,12 +121,24 @@ extern "C" { #define SPI2_TX_DMA_INSTANCE DMA1_Stream4 #define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 #define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) +#define I2C3_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler +#define I2C3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define I2C3_TX_DMA_INSTANCE DMA1_Stream4 +#define I2C3_TX_DMA_CHANNEL DMA_CHANNEL_3 +#define I2C3_TX_DMA_IRQ DMA1_Stream4_IRQn #elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) #define UART4_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler #define UART4_TX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART4_TX_DMA_INSTANCE DMA1_Stream4 #define UART4_TX_DMA_CHANNEL DMA_CHANNEL_4 #define UART4_TX_DMA_IRQ DMA1_Stream4_IRQn +#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) +#define UART3_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler +#define UART3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART3_TX_DMA_INSTANCE DMA1_Stream4 +#define UART3_TX_DMA_CHANNEL DMA_CHANNEL_7 +#define UART3_TX_DMA_IRQ DMA1_Stream4_IRQn #endif /* DMA1 stream5 */ @@ -112,6 +148,12 @@ extern "C" { #define SPI3_TX_DMA_INSTANCE DMA1_Stream5 #define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 #define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) +#define I2C1_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler +#define I2C1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define I2C1_RX_DMA_INSTANCE DMA1_Stream5 +#define I2C1_RX_DMA_CHANNEL DMA_CHANNEL_1 +#define I2C1_RX_DMA_IRQ DMA1_Stream5_IRQn #elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) #define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler #define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN @@ -121,7 +163,13 @@ extern "C" { #endif /* DMA1 stream6 */ -#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#if defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) +#define I2C1_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler +#define I2C1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define I2C1_TX_DMA_INSTANCE DMA1_Stream6 +#define I2C1_TX_DMA_CHANNEL DMA_CHANNEL_1 +#define I2C1_TX_DMA_IRQ DMA1_Stream6_IRQn +#elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) #define UART2_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler #define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART2_TX_DMA_INSTANCE DMA1_Stream6 @@ -142,16 +190,40 @@ extern "C" { #define SPI3_TX_DMA_INSTANCE DMA1_Stream7 #define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 #define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) +#define I2C1_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define I2C1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define I2C1_TX_DMA_INSTANCE DMA1_Stream7 +#define I2C1_TX_DMA_CHANNEL DMA_CHANNEL_1 +#define I2C1_TX_DMA_IRQ DMA1_Stream7_IRQn #elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) #define UART5_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler #define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART5_TX_DMA_INSTANCE DMA1_Stream7 #define UART5_TX_DMA_CHANNEL DMA_CHANNEL_4 #define UART5_TX_DMA_IRQ DMA1_Stream7_IRQn +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) +#define I2C2_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define I2C2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define I2C2_TX_DMA_INSTANCE DMA1_Stream7 +#define I2C2_TX_DMA_CHANNEL DMA_CHANNEL_7 +#define I2C2_TX_DMA_IRQ DMA1_Stream7_IRQn #endif /* DMA2 stream0 */ -#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#if defined(BSP_ADC1_USING_DMA) && !defined(ADC1_DMA_INSTANCE) +#define ADC1_DMA_IRQHandler DMA2_Stream0_IRQHandler +#define ADC1_DMA_RCC RCC_AHB1ENR_DMA2EN +#define ADC1_DMA_INSTANCE DMA2_Stream0 +#define ADC1_DMA_CHANNEL DMA_CHANNEL_0 +#define ADC1_DMA_IRQ DMA2_Stream0_IRQn +#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_DMA_INSTANCE) +#define ADC3_DMA_IRQHandler DMA2_Stream0_IRQHandler +#define ADC3_DMA_RCC RCC_AHB1ENR_DMA2EN +#define ADC3_DMA_INSTANCE DMA2_Stream0 +#define ADC3_DMA_CHANNEL DMA_CHANNEL_2 +#define ADC3_DMA_IRQ DMA2_Stream0_IRQn +#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) #define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI1_RX_DMA_INSTANCE DMA2_Stream0 @@ -163,10 +235,28 @@ extern "C" { #define SPI4_RX_DMA_INSTANCE DMA2_Stream0 #define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4 #define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn +#elif defined(BSP_MEMTOMEM0_USING_DMA) && !defined(MEMTOMEM0_DMA_INSTANCE) +#define MEMTOMEM0_DMA_IRQHandler DMA2_Stream0_IRQHandler +#define MEMTOMEM0_DMA_RCC RCC_AHB1ENR_DMA2EN +#define MEMTOMEM0_DMA_INSTANCE DMA2_Stream0 +#define MEMTOMEM0_DMA_CHANNEL DMA_CHANNEL_7 +#define MEMTOMEM0_DMA_IRQ DMA2_Stream0_IRQn #endif /* DMA2 stream1 */ -#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#if defined(BSP_ADC3_USING_DMA) && !defined(ADC3_DMA_INSTANCE) +#define ADC3_DMA_IRQHandler DMA2_Stream1_IRQHandler +#define ADC3_DMA_RCC RCC_AHB1ENR_DMA2EN +#define ADC3_DMA_INSTANCE DMA2_Stream1 +#define ADC3_DMA_CHANNEL DMA_CHANNEL_2 +#define ADC3_DMA_IRQ DMA2_Stream1_IRQn +#elif defined(BSP_MEMTOMEM1_USING_DMA) && !defined(MEMTOMEM1_DMA_INSTANCE) +#define MEMTOMEM1_DMA_IRQHandler DMA2_Stream1_IRQHandler +#define MEMTOMEM1_DMA_RCC RCC_AHB1ENR_DMA2EN +#define MEMTOMEM1_DMA_INSTANCE DMA2_Stream1 +#define MEMTOMEM1_DMA_CHANNEL DMA_CHANNEL_3 +#define MEMTOMEM1_DMA_IRQ DMA2_Stream1_IRQn +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) #define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler #define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI4_TX_DMA_INSTANCE DMA2_Stream1 @@ -181,7 +271,19 @@ extern "C" { #endif /* DMA2 stream2 */ -#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#if defined(BSP_ADC2_USING_DMA) && !defined(ADC2_DMA_INSTANCE) +#define ADC2_DMA_IRQHandler DMA2_Stream2_IRQHandler +#define ADC2_DMA_RCC RCC_AHB1ENR_DMA2EN +#define ADC2_DMA_INSTANCE DMA2_Stream2 +#define ADC2_DMA_CHANNEL DMA_CHANNEL_1 +#define ADC2_DMA_IRQ DMA2_Stream2_IRQn +#elif defined(BSP_MEMTOMEM2_USING_DMA) && !defined(MEMTOMEM2_DMA_INSTANCE) +#define MEMTOMEM2_DMA_IRQHandler DMA2_Stream2_IRQHandler +#define MEMTOMEM2_DMA_RCC RCC_AHB1ENR_DMA2EN +#define MEMTOMEM2_DMA_INSTANCE DMA2_Stream2 +#define MEMTOMEM2_DMA_CHANNEL DMA_CHANNEL_2 +#define MEMTOMEM2_DMA_IRQ DMA2_Stream2_IRQn +#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) #define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI1_RX_DMA_INSTANCE DMA2_Stream2 @@ -193,10 +295,28 @@ extern "C" { #define UART1_RX_DMA_INSTANCE DMA2_Stream2 #define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn +#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) +#define UART6_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define UART6_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define UART6_RX_DMA_INSTANCE DMA2_Stream2 +#define UART6_RX_DMA_CHANNEL DMA_CHANNEL_5 +#define UART6_RX_DMA_IRQ DMA2_Stream2_IRQn #endif /* DMA2 stream3 */ -#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#if defined(BSP_MEMTOMEM3_USING_DMA) && !defined(MEMTOMEM3_DMA_INSTANCE) +#define MEMTOMEM3_DMA_IRQHandler DMA2_Stream3_IRQHandler +#define MEMTOMEM3_DMA_RCC RCC_AHB1ENR_DMA2EN +#define MEMTOMEM3_DMA_INSTANCE DMA2_Stream3 +#define MEMTOMEM3_DMA_CHANNEL DMA_CHANNEL_0 +#define MEMTOMEM3_DMA_IRQ DMA2_Stream3_IRQn +#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_DMA_INSTANCE) +#define ADC2_DMA_IRQHandler DMA2_Stream3_IRQHandler +#define ADC2_DMA_RCC RCC_AHB1ENR_DMA2EN +#define ADC2_DMA_INSTANCE DMA2_Stream3 +#define ADC2_DMA_CHANNEL DMA_CHANNEL_1 +#define ADC2_DMA_IRQ DMA2_Stream3_IRQn +#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) #define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler #define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI5_RX_DMA_INSTANCE DMA2_Stream3 @@ -208,6 +328,12 @@ extern "C" { #define SPI1_TX_DMA_INSTANCE DMA2_Stream3 #define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 #define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn +#elif defined(BSP_SDIO_RX_USING_DMA) && !defined(SDIO_RX_DMA_INSTANCE) +#define SDIO_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SDIO_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SDIO_RX_DMA_INSTANCE DMA2_Stream3 +#define SDIO_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define SDIO_RX_DMA_IRQ DMA2_Stream3_IRQn #elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) #define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler #define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN @@ -217,12 +343,24 @@ extern "C" { #endif /* DMA2 stream4 */ -#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#if defined(BSP_ADC1_USING_DMA) && !defined(ADC1_DMA_INSTANCE) +#define ADC1_DMA_IRQHandler DMA2_Stream4_IRQHandler +#define ADC1_DMA_RCC RCC_AHB1ENR_DMA2EN +#define ADC1_DMA_INSTANCE DMA2_Stream4 +#define ADC1_DMA_CHANNEL DMA_CHANNEL_0 +#define ADC1_DMA_IRQ DMA2_Stream4_IRQn +#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) #define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler #define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI5_TX_DMA_INSTANCE DMA2_Stream4 #define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 #define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn +#elif defined(BSP_MEMTOMEM4_USING_DMA) && !defined(MEMTOMEM4_DMA_INSTANCE) +#define MEMTOMEM4_DMA_IRQHandler DMA2_Stream4_IRQHandler +#define MEMTOMEM4_DMA_RCC RCC_AHB1ENR_DMA2EN +#define MEMTOMEM4_DMA_INSTANCE DMA2_Stream4 +#define MEMTOMEM4_DMA_CHANNEL DMA_CHANNEL_4 +#define MEMTOMEM4_DMA_IRQ DMA2_Stream4_IRQn #elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) #define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler #define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN @@ -232,7 +370,13 @@ extern "C" { #endif /* DMA2 stream5 */ -#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE) +#define SPI6_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI6_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI6_TX_DMA_INSTANCE DMA2_Stream5 +#define SPI6_TX_DMA_CHANNEL DMA_CHANNEL_1 +#define SPI6_TX_DMA_IRQ DMA2_Stream5_IRQn +#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) #define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI1_TX_DMA_INSTANCE DMA2_Stream5 @@ -244,6 +388,12 @@ extern "C" { #define UART1_RX_DMA_INSTANCE DMA2_Stream5 #define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn +#elif defined(BSP_MEMTOMEM5_USING_DMA) && !defined(MEMTOMEM5_DMA_INSTANCE) +#define MEMTOMEM5_DMA_IRQHandler DMA2_Stream5_IRQHandler +#define MEMTOMEM5_DMA_RCC RCC_AHB1ENR_DMA2EN +#define MEMTOMEM5_DMA_INSTANCE DMA2_Stream5 +#define MEMTOMEM5_DMA_CHANNEL DMA_CHANNEL_5 +#define MEMTOMEM5_DMA_IRQ DMA2_Stream5_IRQn #elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) #define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler #define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN @@ -253,18 +403,36 @@ extern "C" { #endif /* DMA2 stream6 */ -#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) -#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler -#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 -#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 -#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn -#elif defined(BSP_UART6_TX_USING_DMA) && !defined(BSP_USING_SDIO) && !defined(UART6_TX_DMA_INSTANCE) +#if defined(BSP_SPI6_RX_USING_DMA) && !defined(SPI6_RX_DMA_INSTANCE) +#define SPI6_DMA_RX_IRQHandler DMA2_Stream6_IRQHandler +#define SPI6_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI6_RX_DMA_INSTANCE DMA2_Stream6 +#define SPI6_RX_DMA_CHANNEL DMA_CHANNEL_1 +#define SPI6_RX_DMA_IRQ DMA2_Stream6_IRQn +#elif defined(BSP_MEMTOMEM6_USING_DMA) && !defined(MEMTOMEM6_DMA_INSTANCE) +#define MEMTOMEM6_DMA_IRQHandler DMA2_Stream6_IRQHandler +#define MEMTOMEM6_DMA_RCC RCC_AHB1ENR_DMA2EN +#define MEMTOMEM6_DMA_INSTANCE DMA2_Stream6 +#define MEMTOMEM6_DMA_CHANNEL DMA_CHANNEL_3 +#define MEMTOMEM6_DMA_IRQ DMA2_Stream6_IRQn +#elif defined(BSP_SDIO_TX_USING_DMA) && !defined(SDIO_TX_DMA_INSTANCE) +#define SDIO_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#define SDIO_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SDIO_TX_DMA_INSTANCE DMA2_Stream6 +#define SDIO_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define SDIO_TX_DMA_IRQ DMA2_Stream6_IRQn +#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) #define UART6_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler #define UART6_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define UART6_TX_DMA_INSTANCE DMA2_Stream6 #define UART6_TX_DMA_CHANNEL DMA_CHANNEL_5 #define UART6_TX_DMA_IRQ DMA2_Stream6_IRQn +#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn #endif /* DMA2 stream7 */ @@ -280,6 +448,12 @@ extern "C" { #define UART6_TX_DMA_INSTANCE DMA2_Stream7 #define UART6_TX_DMA_CHANNEL DMA_CHANNEL_5 #define UART6_TX_DMA_IRQ DMA2_Stream7_IRQn +#elif defined(BSP_MEMTOMEM7_USING_DMA) && !defined(MEMTOMEM7_DMA_INSTANCE) +#define MEMTOMEM7_DMA_IRQHandler DMA2_Stream7_IRQHandler +#define MEMTOMEM7_DMA_RCC RCC_AHB1ENR_DMA2EN +#define MEMTOMEM7_DMA_INSTANCE DMA2_Stream7 +#define MEMTOMEM7_DMA_CHANNEL DMA_CHANNEL_6 +#define MEMTOMEM7_DMA_IRQ DMA2_Stream7_IRQn #endif #ifdef __cplusplus diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c index 1d8574b3ae..90b4d928c5 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c @@ -311,7 +311,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c) rt_uint32_t stm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity) { - rt_uint32_t mask; + rt_uint32_t mask = 0; if (word_length == UART_WORDLENGTH_8B) { if (parity == UART_PARITY_NONE) @@ -935,6 +935,7 @@ static void stm32_uart_get_config(void) static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG; uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx; #endif +#endif #ifdef BSP_USING_UART5 uart_obj[UART5_INDEX].serial.config = config; @@ -956,6 +957,64 @@ static void stm32_uart_get_config(void) #endif #endif +#ifdef BSP_USING_UART6 + uart_obj[UART6_INDEX].serial.config = config; + uart_obj[UART6_INDEX].uart_dma_flag = 0; + + uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE; + uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE; + +#ifdef BSP_UART6_RX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG; + uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx; +#endif + +#ifdef BSP_UART6_TX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG; + uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART7 + uart_obj[UART7_INDEX].serial.config = config; + uart_obj[UART7_INDEX].uart_dma_flag = 0; + + uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE; + uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE; + +#ifdef BSP_UART7_RX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG; + uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx; +#endif + +#ifdef BSP_UART7_TX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG; + uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART8 + uart_obj[UART8_INDEX].serial.config = config; + uart_obj[UART8_INDEX].uart_dma_flag = 0; + + uart_obj[UART8_INDEX].serial.config.rx_bufsz = BSP_UART8_RX_BUFSIZE; + uart_obj[UART8_INDEX].serial.config.tx_bufsz = BSP_UART8_TX_BUFSIZE; + +#ifdef BSP_UART8_RX_USING_DMA + uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG; + uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx; +#endif + +#ifdef BSP_UART8_TX_USING_DMA + uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG; + uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx; +#endif #endif } -- GitLab