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77973d8d
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体验新版 GitCode,发现更多精彩内容 >>
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77973d8d
编写于
4月 28, 2019
作者:
B
Bernard Xiong
提交者:
GitHub
4月 28, 2019
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差异文件
Merge pull request #2625 from misonyo/rttdev
[libcpu/cortex-m7]add cache driver
上级
c0a400cc
0f33da3f
变更
4
显示空白变更内容
内联
并排
Showing
4 changed file
with
24 addition
and
79 deletion
+24
-79
bsp/imxrt/Libraries/imxrt1021/drivers/SConscript
bsp/imxrt/Libraries/imxrt1021/drivers/SConscript
+0
-1
bsp/imxrt/Libraries/imxrt1050/drivers/SConscript
bsp/imxrt/Libraries/imxrt1050/drivers/SConscript
+0
-1
bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c
bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c
+0
-71
libcpu/arm/cortex-m7/cpu_cache.c
libcpu/arm/cortex-m7/cpu_cache.c
+24
-6
未找到文件。
bsp/imxrt/Libraries/imxrt1021/drivers/SConscript
浏览文件 @
77973d8d
...
...
@@ -5,7 +5,6 @@ cwd = GetCurrentDir()
# add the general drivers.
src
=
Split
(
"""
drv_uart.c
drv_cache.c
"""
)
CPPPATH
=
[
cwd
]
...
...
bsp/imxrt/Libraries/imxrt1050/drivers/SConscript
浏览文件 @
77973d8d
...
...
@@ -5,7 +5,6 @@ cwd = GetCurrentDir()
# add the general drivers.
src
=
Split
(
"""
drv_uart.c
drv_cache.c
"""
)
CPPPATH
=
[
cwd
]
...
...
bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c
已删除
100644 → 0
浏览文件 @
c0a400cc
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-04-02 tanek first implementation
*/
#include <rtthread.h>
#include <rthw.h>
#include <fsl_cache.h>
void
rt_hw_cpu_icache_enable
(
void
)
{
SCB_EnableICache
();
}
void
rt_hw_cpu_icache_disable
(
void
)
{
SCB_DisableICache
();
}
rt_base_t
rt_hw_cpu_icache_status
(
void
)
{
return
0
;
}
void
rt_hw_cpu_icache_ops
(
int
ops
,
void
*
addr
,
int
size
)
{
if
(
ops
&
RT_HW_CACHE_INVALIDATE
)
{
ICACHE_InvalidateByRange
((
uint32_t
)
addr
,
size
);
}
}
void
rt_hw_cpu_dcache_enable
(
void
)
{
SCB_EnableDCache
();
}
void
rt_hw_cpu_dcache_disable
(
void
)
{
SCB_DisableDCache
();
}
rt_base_t
rt_hw_cpu_dcache_status
(
void
)
{
return
0
;
}
void
rt_hw_cpu_dcache_ops
(
int
ops
,
void
*
addr
,
int
size
)
{
if
(
ops
&
(
RT_HW_CACHE_FLUSH
|
RT_HW_CACHE_INVALIDATE
))
{
DCACHE_CleanInvalidateByRange
((
uint32_t
)
addr
,
size
);
}
else
if
(
ops
&
RT_HW_CACHE_FLUSH
)
{
DCACHE_CleanByRange
((
uint32_t
)
addr
,
size
);
}
else
if
(
ops
&
RT_HW_CACHE_INVALIDATE
)
{
DCACHE_InvalidateByRange
((
uint32_t
)
addr
,
size
);
}
else
{
RT_ASSERT
(
0
);
}
}
bsp/imxrt/Libraries/imxrt1021/drivers/drv
_cache.c
→
libcpu/arm/cortex-m7/cpu
_cache.c
浏览文件 @
77973d8d
...
...
@@ -6,11 +6,15 @@
* Change Logs:
* Date Author Notes
* 2018-04-02 tanek first implementation
* 2019-04-27 misonyo update to cortex-m7 series
*/
#include <rtthread.h>
#include <rthw.h>
#include <fsl_cache.h>
#include <rtdef.h>
#include <board.h>
/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
#define L1CACHE_LINESIZE_BYTE (32)
void
rt_hw_cpu_icache_enable
(
void
)
{
...
...
@@ -29,9 +33,20 @@ rt_base_t rt_hw_cpu_icache_status(void)
void
rt_hw_cpu_icache_ops
(
int
ops
,
void
*
addr
,
int
size
)
{
rt_uint32_t
address
=
(
rt_uint32_t
)
addr
&
(
rt_uint32_t
)
~
(
L1CACHE_LINESIZE_BYTE
-
1
);
rt_int32_t
size_byte
=
size
+
address
-
(
rt_uint32_t
)
addr
;
rt_uint32_t
linesize
=
32U
;
if
(
ops
&
RT_HW_CACHE_INVALIDATE
)
{
ICACHE_InvalidateByRange
((
uint32_t
)
addr
,
size
);
__DSB
();
while
(
size_byte
>
0
)
{
SCB
->
ICIMVAU
=
address
;
address
+=
linesize
;
size_byte
-=
linesize
;
}
__DSB
();
__ISB
();
}
}
...
...
@@ -52,17 +67,20 @@ rt_base_t rt_hw_cpu_dcache_status(void)
void
rt_hw_cpu_dcache_ops
(
int
ops
,
void
*
addr
,
int
size
)
{
rt_uint32_t
startAddr
=
(
rt_uint32_t
)
addr
&
(
rt_uint32_t
)
~
(
L1CACHE_LINESIZE_BYTE
-
1
);
rt_uint32_t
size_byte
=
size
+
(
rt_uint32_t
)
addr
-
startAddr
;
if
(
ops
&
(
RT_HW_CACHE_FLUSH
|
RT_HW_CACHE_INVALIDATE
))
{
DCACHE_CleanInvalidateByRange
((
uint32_t
)
addr
,
siz
e
);
SCB_CleanInvalidateDCache_by_Addr
((
rt_uint32_t
*
)
startAddr
,
size_byt
e
);
}
else
if
(
ops
&
RT_HW_CACHE_FLUSH
)
{
DCACHE_CleanByRange
((
uint32_t
)
addr
,
siz
e
);
SCB_CleanDCache_by_Addr
((
rt_uint32_t
*
)
startAddr
,
size_byt
e
);
}
else
if
(
ops
&
RT_HW_CACHE_INVALIDATE
)
{
DCACHE_InvalidateByRange
((
uint32_t
)
addr
,
siz
e
);
SCB_InvalidateDCache_by_Addr
((
rt_uint32_t
*
)
startAddr
,
size_byt
e
);
}
else
{
...
...
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