diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml
index 2a5697964aa9fe498207654ba67aae101e50c2ee..e60f45de56bb1d87fa96f9bfb2161a9f13149fa8 100644
--- a/.github/workflows/action.yml
+++ b/.github/workflows/action.yml
@@ -78,6 +78,7 @@ jobs:
- {RTT_BSP: "stm32/stm32f103-onenet-nbiot", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f103-yf-ufun", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f107-uc-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+ - {RTT_BSP: "stm32/stm32f207-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"}
diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md
index ffdf1668f2d28c545ff63398b06a221e29fb442d..1a36605aa12cad184acdb8f31c2bfd76fa007582 100644
--- a/bsp/stm32/README.md
+++ b/bsp/stm32/README.md
@@ -20,6 +20,8 @@ STM32 系列 BSP 目前支持情况如下表所示:
| [stm32f103-onenet-nbiot](stm32f103-onenet-nbiot) | STM32F103 OneNET NB-IoT 开发板 |
| [stm32f103-yf-ufun](stm32f103-yf-ufun) | STM32F103 yf-ufun 开发板 |
| [stm32f107-uc-eval](stm32f107-uc-eval) | uC/Eval STM32F107 评估板(中国版) |
+| **F2 系列** | |
+| [stm32f207-st-nucleo](stm32f207-st-nucleo) | ST 官方 STM32F207-nucleo 开发板 |
| **F4 系列** | |
| [stm32f401-st-nucleo](stm32f401-st-nucleo) | ST 官方 STM32F401 Nucleo-64 开发板 |
| [stm32f405-smdz-breadfruit](stm32f405-smdz-breadfruit) | 三木电子 SM1432F405 开发板 |
diff --git a/bsp/stm32/stm32f207-st-nucleo/.config b/bsp/stm32/stm32f207-st-nucleo/.config
new file mode 100644
index 0000000000000000000000000000000000000000..2a50010a8185cf5795567c1e4918ea47683c4f5c
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/.config
@@ -0,0 +1,552 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart3"
+CONFIG_RT_VER_NUM=0x40003
+CONFIG_ARCH_ARM=y
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M3=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_LIBC_USING_TIME=y
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+CONFIG_SOC_FAMILY_STM32=y
+CONFIG_SOC_SERIES_STM32F2=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_STM32F207ZG=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART3=y
+# CONFIG_BSP_USING_UDID is not set
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/stm32/stm32f207-st-nucleo/.cproject b/bsp/stm32/stm32f207-st-nucleo/.cproject
new file mode 100644
index 0000000000000000000000000000000000000000..878ff7efa9b53d9eb471e2a9e5d122f1ca45bb40
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/.cproject
@@ -0,0 +1,200 @@
+
+
+
+
+
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diff --git a/bsp/stm32/stm32f207-st-nucleo/.gitignore b/bsp/stm32/stm32f207-st-nucleo/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..7221bde019df6157cbf9e42ef5ab8a78420e3b68
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/.gitignore
@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h
diff --git a/bsp/stm32/stm32f207-st-nucleo/.project b/bsp/stm32/stm32f207-st-nucleo/.project
new file mode 100644
index 0000000000000000000000000000000000000000..0d0159024c50f498f273aa2cdf851538e95b5c3e
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/.project
@@ -0,0 +1,28 @@
+
+
+ stm32f207-st-nucleo
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.rt-thread.studio.rttnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
+
diff --git a/bsp/stm32/stm32f207-st-nucleo/.settings/org.eclipse.core.runtime.prefs b/bsp/stm32/stm32f207-st-nucleo/.settings/org.eclipse.core.runtime.prefs
new file mode 100644
index 0000000000000000000000000000000000000000..9f1acfcfba240094ead0fe4da6c1cfcccdc26fd2
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/.settings/org.eclipse.core.runtime.prefs
@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1
\ No newline at end of file
diff --git a/bsp/stm32/stm32f207-st-nucleo/.settings/projcfg.ini b/bsp/stm32/stm32f207-st-nucleo/.settings/projcfg.ini
new file mode 100644
index 0000000000000000000000000000000000000000..37010cb7bb150cb6765246a4a90f4d0d47f92c6c
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/.settings/projcfg.ini
@@ -0,0 +1,22 @@
+#RT-Thread Studio Project Configuration
+#Sat Jan 16 15:18:32 CST 2021
+project_type=rtt
+chip_name=STM32F103RB
+cpu_name=None
+target_freq=
+clock_source=
+dvendor_name=
+rx_pin_name=
+rtt_path=
+source_freq=
+csp_path=
+sub_series_name=
+selected_rtt_version=latest
+cfg_version=v3.0
+tool_chain=gcc
+uart_name=
+tx_pin_name=
+rtt_nano_path=
+output_project_path=
+hardware_adapter=J-Link
+project_name=stm32f207-st-nucleo
\ No newline at end of file
diff --git a/bsp/stm32/stm32f207-st-nucleo/Kconfig b/bsp/stm32/stm32f207-st-nucleo/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..924a7509e0af66dc4887aa73a7b65529eed9db8d
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/Kconfig
@@ -0,0 +1,22 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "rt-thread"
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "libraries/Kconfig"
+source "board/Kconfig"
+
diff --git a/bsp/stm32/stm32f207-st-nucleo/README.md b/bsp/stm32/stm32f207-st-nucleo/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..e35cf14b4458f2cda517e50f9b7c338b73bc40f9
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/README.md
@@ -0,0 +1,130 @@
+# BSP README 模板
+
+## 简介
+
+本文档为 STM32F207 Nucleo-144 开发板的 BSP (板级支持包) 说明。
+
+主要内容如下:
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP,将 RT-Thread 运行在开发板上。在进阶使用指南章节,将会介绍更多高级功能,帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+STM32 Nucleo-144 是 ST 官方推出的开发板,搭载 STM32F207ZG 芯片,基于 ARM Cortex-M3 内核,最高主频 120 MHz,具有丰富的板载资源,可以充分发挥 STM32F207ZG 的芯片性能。
+
+开发板外观如下图所示:
+
+![board](figures/board.jpg)
+
+该开发板常用 **板载资源** 如下:
+
+- MCU:STM3207ZG,主频 120MHz,1MB FLASH ,128KB RAM
+- 常用外设
+ - LED:3个,LD1(绿色,PB0),LD2(蓝色,PB7),LD3(红色,PB14)
+ - 按键:2 个,USER and RESET 。
+- 常用接口:USB 转串口、以太网接口、Arduino Uno 和 ST morpho 两类扩展接口
+- 调试接口,标准 JTAG/SWD
+
+快速入门:[Getting started with STM32 Nucleo board software development tools](https://www.st.com/resource/en/user_manual/dm00105928-getting-started-with-stm32-nucleo-board-software-development-tools-stmicroelectronics.pdf)
+
+原理图下载:[STM32 Nucleo (144 pins) schematics](https://www.st.com/resource/en/schematic_pack/nucleo_144pins_sch.zip)
+
+*更多相关信息资料见 ST 官网详情页:[STM32 Nucleo-144 development board with STM32F207ZG MCU](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-f207zg.html)*
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下:
+
+| **板载外设** | **支持情况** | **备注** |
+| :----------------- | :----------: | :------------------------------------- |
+| USB 转串口 | 支持 | |
+| 以太网 | 暂不支持 | |
+| **片上外设** | **支持情况** | **备注** |
+| GPIO | 支持 | PA0, PA1... PH1 ---> PIN: 0, 1...144 |
+| UART | 支持 | UART3 |
+| SPI | 暂不支持 | |
+| I2C | 暂不支持 | |
+| RTC | 暂不支持 | |
+| PWM | 暂不支持 | |
+| USB Device | 暂不支持 | |
+| USB Host | 暂不支持 | |
+| IWG | 暂不支持 | |
+
+## 使用说明
+
+使用说明分为如下两个章节:
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明,遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上,看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置,可以开启更多板载资源,实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程,并且支持 GCC 开发环境。下面以 MDK5 开发环境为例,介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC,打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件,打开 MDK5 工程,编译并下载程序到开发板。
+
+> 工程默认配置使用 xxx 仿真器下载程序,在通过 xxx 连接开发板的基础上,点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后,系统会自动运行,红色 LD3 会周期性闪烁。。
+
+USB 虚拟 COM 端口默认连接串口 3,在终端工具里打开相应的串口(115200-8-1-N),复位设备后,可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 4.0.3 build Apr 12 2021
+ 2006 - 2021 Copyright by rt-thread team
+msh >
+
+```
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口3 的功能,更多高级功能需要利用 ENV 工具对 BSP 进行配置,步骤如下:
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程,配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
+
+## 注意事项
+
+- 关于 pin 序号规则,与旧 bsp 使用封装管脚序号不同,在新的 stm32 bsp 框架中,统一采用顺序编号的方式,对 GPIO 驱动进行管理,在移植旧 bsp 时特别要注意这点。
+
+ pin 序号与引脚名对应关系如下表:
+
+ | STM32 引脚名 | 管脚序号 pin |
+ | ------------ | ------------ |
+ | PA0 - PA15 | 0 - 15 |
+ | PB0 - PB15 | 16 - 31 |
+ | PC0 - PC15 | 32 - 47 |
+ | PD0 - ... | 48 - ... |
+
+
+## 联系人信息
+
+维护人:
+
+- [wanghaijing](https://github.com/whj4674672) ,邮箱:
\ No newline at end of file
diff --git a/bsp/stm32/stm32f207-st-nucleo/SConscript b/bsp/stm32/stm32f207-st-nucleo/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..20f7689c53ca71a676748f79187f9764065466c5
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/stm32/stm32f207-st-nucleo/SConstruct b/bsp/stm32/stm32f207-st-nucleo/SConstruct
new file mode 100644
index 0000000000000000000000000000000000000000..c0afbd9669b0743feefd6d984bd4ffcb024cb443
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/SConstruct
@@ -0,0 +1,64 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+# set RTT_ROOT
+if not os.getenv("RTT_ROOT"):
+ RTT_ROOT="rt-thread"
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+ libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+ libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+stm32_library = 'STM32F2xx_HAL'
+rtconfig.BSP_LIBRARY_TYPE = stm32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/stm32/stm32f207-st-nucleo/applications/SConscript b/bsp/stm32/stm32f207-st-nucleo/applications/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..c25223940b16b691854388e4c99e2fc5179e137c
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/applications/SConscript
@@ -0,0 +1,12 @@
+import rtconfig
+from building import *
+
+cwd = GetCurrentDir()
+CPPPATH = [cwd]
+src = Split("""
+main.c
+""")
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/stm32/stm32f207-st-nucleo/applications/main.c b/bsp/stm32/stm32f207-st-nucleo/applications/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..b88176a8acd96766ecc51d5f65f4ff4758bf837e
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/applications/main.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-06 SummerGift first version
+ */
+
+#include
+#include
+#include
+
+/* defined the LED0 pin: PB14 */
+#define LED0_PIN GET_PIN(B, 14)
+
+int main(void)
+{
+ int count = 1;
+ /* set LED0 pin mode to output */
+ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
+ while (count++)
+ {
+ rt_pin_write(LED0_PIN, PIN_HIGH);
+ rt_thread_mdelay(500);
+ rt_pin_write(LED0_PIN, PIN_LOW);
+ rt_thread_mdelay(500);
+ }
+
+ return RT_EOK;
+}
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/.mxproject
new file mode 100644
index 0000000000000000000000000000000000000000..67b3ed7df22446273f2a21b7a495f15e2fc2dec2
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/.mxproject
@@ -0,0 +1,25 @@
+[PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=3
+HeaderFiles#0=D:/rt-thread/rt_thread_master/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/stm32f2xx_it.h
+HeaderFiles#1=D:/rt-thread/rt_thread_master/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/stm32f2xx_hal_conf.h
+HeaderFiles#2=D:/rt-thread/rt_thread_master/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/main.h
+HeaderFolderListSize=1
+HeaderPath#0=D:/rt-thread/rt_thread_master/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc
+HeaderFiles=;
+SourceFileListSize=3
+SourceFiles#0=D:/rt-thread/rt_thread_master/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_it.c
+SourceFiles#1=D:/rt-thread/rt_thread_master/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_hal_msp.c
+SourceFiles#2=D:/rt-thread/rt_thread_master/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/main.c
+SourceFolderListSize=1
+SourcePath#0=D:/rt-thread/rt_thread_master/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src
+SourceFiles=;
+
+[PreviousLibFiles]
+LibFiles=Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_def.h;Drivers/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cortex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_exti.h;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim_ex.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc_ex.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cortex.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash_ex.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr_ex.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma_ex.c;Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_exti.c;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_def.h;Drivers/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cortex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma_ex.h;Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f207xx.h;Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h;Drivers/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h;Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+
+[PreviousUsedKeilFiles]
+SourceFiles=..\Core\Src\main.c;..\Core\Src\stm32f2xx_it.c;..\Core\Src\stm32f2xx_hal_msp.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim_ex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc_ex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cortex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash_ex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr_ex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma_ex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_exti.c;..\Core\Src/system_stm32f2xx.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim_ex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc_ex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cortex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash_ex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr_ex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma_ex.c;..\Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_exti.c;..\Core\Src/system_stm32f2xx.c;..\Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c;;
+HeaderPath=..\Drivers\STM32F2xx_HAL_Driver\Inc;..\Drivers\STM32F2xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F2xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc;
+CDefines=USE_HAL_DRIVER;STM32F207xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/main.h b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/main.h
new file mode 100644
index 0000000000000000000000000000000000000000..cc46ee20d9cc1f32d40f13df608d414533c6f6a0
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.h
+ * @brief : Header for main.c file.
+ * This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f2xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/stm32f2xx_hal_conf.h b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/stm32f2xx_hal_conf.h
new file mode 100644
index 0000000000000000000000000000000000000000..057a2a974e48b2090c259c18ed408d778f2a21b5
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/stm32f2xx_hal_conf.h
@@ -0,0 +1,410 @@
+/**
+ ******************************************************************************
+ * @file stm32f2xx_hal_conf.h
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F2xx_HAL_CONF_H
+#define __STM32F2xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+
+#define HAL_MODULE_ENABLED
+/*#define HAL_ADC_MODULE_ENABLED */
+/*#define HAL_CRYP_MODULE_ENABLED */
+/*#define HAL_CAN_MODULE_ENABLED */
+/*#define HAL_CAN_LEGACY_MODULE_ENABLED */
+/*#define HAL_CRC_MODULE_ENABLED */
+/*#define HAL_CRYP_MODULE_ENABLED */
+/*#define HAL_DAC_MODULE_ENABLED */
+/*#define HAL_DCMI_MODULE_ENABLED */
+/*#define HAL_ETH_MODULE_ENABLED */
+/*#define HAL_NAND_MODULE_ENABLED */
+/*#define HAL_NOR_MODULE_ENABLED */
+/*#define HAL_PCCARD_MODULE_ENABLED */
+/*#define HAL_SRAM_MODULE_ENABLED */
+/*#define HAL_HASH_MODULE_ENABLED */
+/*#define HAL_I2C_MODULE_ENABLED */
+/*#define HAL_I2S_MODULE_ENABLED */
+/*#define HAL_IWDG_MODULE_ENABLED */
+/*#define HAL_RNG_MODULE_ENABLED */
+/*#define HAL_RTC_MODULE_ENABLED */
+/*#define HAL_SD_MODULE_ENABLED */
+/*#define HAL_MMC_MODULE_ENABLED */
+/*#define HAL_SPI_MODULE_ENABLED */
+/*#define HAL_TIM_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED */
+/*#define HAL_IRDA_MODULE_ENABLED */
+/*#define HAL_SMARTCARD_MODULE_ENABLED */
+/*#define HAL_WWDG_MODULE_ENABLED */
+/*#define HAL_PCD_MODULE_ENABLED */
+/*#define HAL_HCD_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature.*/
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External audio frequency in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
+#define INSTRUCTION_CACHE_ENABLE 1U
+#define DATA_CACHE_ENABLE 1U
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
+#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
+#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
+#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
+#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
+#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
+#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
+#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
+#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2U
+#define MAC_ADDR1 0U
+#define MAC_ADDR2 0U
+#define MAC_ADDR3 0U
+#define MAC_ADDR4 0U
+#define MAC_ADDR5 0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848_PHY_ADDRESS Address*/
+#define DP83848_PHY_ADDRESS 0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY 0x00000FFFU
+
+#define PHY_READ_TO 0x0000FFFFU
+#define PHY_WRITE_TO 0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC 0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f2xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f2xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32f2xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f2xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f2xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f2xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f2xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #include "stm32f2xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f2xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f2xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f2xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f2xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f2xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f2xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f2xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f2xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f2xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f2xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f2xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f2xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f2xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f2xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f2xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f2xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f2xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f2xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f2xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f2xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f2xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f2xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f2xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f2xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f2xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f2xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f2xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f2xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F2xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/stm32f2xx_it.h b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/stm32f2xx_it.h
new file mode 100644
index 0000000000000000000000000000000000000000..843a15b2f0ff03a5728493180fa16ac79daf3f68
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Inc/stm32f2xx_it.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32f2xx_it.h
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F2xx_IT_H
+#define __STM32F2xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F2xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/main.c b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..1d74773d4851872536bc5974f637ac36334f17aa
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/main.c
@@ -0,0 +1,240 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart3;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART3_UART_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* USER CODE BEGIN 1 */
+
+ /* USER CODE END 1 */
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* Configure the system clock */
+ SystemClock_Config();
+
+ /* USER CODE BEGIN SysInit */
+
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ MX_USART3_UART_Init();
+ /* USER CODE BEGIN 2 */
+
+ /* USER CODE END 2 */
+
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 13;
+ RCC_OscInitStruct.PLL.PLLN = 195;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 4;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+/**
+ * @brief USART3 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_USART3_UART_Init(void)
+{
+
+ /* USER CODE BEGIN USART3_Init 0 */
+
+ /* USER CODE END USART3_Init 0 */
+
+ /* USER CODE BEGIN USART3_Init 1 */
+
+ /* USER CODE END USART3_Init 1 */
+ huart3.Instance = USART3;
+ huart3.Init.BaudRate = 115200;
+ huart3.Init.WordLength = UART_WORDLENGTH_8B;
+ huart3.Init.StopBits = UART_STOPBITS_1;
+ huart3.Init.Parity = UART_PARITY_NONE;
+ huart3.Init.Mode = UART_MODE_TX_RX;
+ huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ huart3.Init.OverSampling = UART_OVERSAMPLING_16;
+ if (HAL_UART_Init(&huart3) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN USART3_Init 2 */
+
+ /* USER CODE END USART3_Init 2 */
+
+}
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : PB14 */
+ GPIO_InitStruct.Pin = GPIO_PIN_14;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_hal_msp.c b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_hal_msp.c
new file mode 100644
index 0000000000000000000000000000000000000000..24b027c37b77d15af49a20312012412dbb518b07
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_hal_msp.c
@@ -0,0 +1,149 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32f2xx_hal_msp.c
+ * @brief This file provides code for the MSP Initialization
+ * and de-Initialization codes.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* System interrupt init*/
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if(huart->Instance==USART3)
+ {
+ /* USER CODE BEGIN USART3_MspInit 0 */
+
+ /* USER CODE END USART3_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_USART3_CLK_ENABLE();
+
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ /**USART3 GPIO Configuration
+ PD8 ------> USART3_TX
+ PD9 ------> USART3_RX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN USART3_MspInit 1 */
+
+ /* USER CODE END USART3_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+ if(huart->Instance==USART3)
+ {
+ /* USER CODE BEGIN USART3_MspDeInit 0 */
+
+ /* USER CODE END USART3_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_USART3_CLK_DISABLE();
+
+ /**USART3 GPIO Configuration
+ PD8 ------> USART3_TX
+ PD9 ------> USART3_RX
+ */
+ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9);
+
+ /* USER CODE BEGIN USART3_MspDeInit 1 */
+
+ /* USER CODE END USART3_MspDeInit 1 */
+ }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_it.c b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_it.c
new file mode 100644
index 0000000000000000000000000000000000000000..26930848b2edabbefcb6f23fa15d88c49fa65ea8
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/stm32f2xx_it.c
@@ -0,0 +1,205 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32f2xx_it.c
+ * @brief Interrupt Service Routines.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f2xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/* Cortex-M3 Processor Interruption and Exception Handlers */
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ {
+ }
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+ /* USER CODE END W1_HardFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Pre-fetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ /* USER CODE END W1_BusFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ /* USER CODE END W1_UsageFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+ /* USER CODE BEGIN SVCall_IRQn 0 */
+
+ /* USER CODE END SVCall_IRQn 0 */
+ /* USER CODE BEGIN SVCall_IRQn 1 */
+
+ /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+void PendSV_Handler(void)
+{
+ /* USER CODE BEGIN PendSV_IRQn 0 */
+
+ /* USER CODE END PendSV_IRQn 0 */
+ /* USER CODE BEGIN PendSV_IRQn 1 */
+
+ /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F2xx Peripheral Interrupt Handlers */
+/* Add here the Interrupt Handlers for the used peripherals. */
+/* For the available peripheral interrupt handler names, */
+/* please refer to the startup file (startup_stm32f2xx.s). */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/system_stm32f2xx.c b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/system_stm32f2xx.c
new file mode 100644
index 0000000000000000000000000000000000000000..2139bbf9130aaf4aa2b58abc79b6645990d6d0d4
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/Core/Src/system_stm32f2xx.c
@@ -0,0 +1,344 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f2xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f2xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f2xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F2xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f2xx.h"
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F2xx_System_Private_Defines
+ * @{
+ */
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on STM322xG_EVAL board as data memory */
+/* #define DATA_IN_ExtSRAM */
+
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F2xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F2xx_System_Private_Variables
+ * @{
+ */
+
+ /* This variable can be updated in Three ways :
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 16000000;
+ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F2xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemFrequency variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+#ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value
+ * depends on the application requirements), user has to ensure that HSE_VALUE
+ * is same as the real frequency of the crystal used. Otherwise, this function
+ * may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ SYSCLK = PLL_VCO / PLL_P
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ SystemCoreClock = pllvco/pllp;
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK frequency --------------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f2xx.s before jump to main.
+ * This function configures the external SRAM mounted on STM322xG_EVAL board
+ * This SRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmp = 0x00;
+
+/*-- GPIOs Configuration -----------------------------------------------------*/
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHB1ENR |= 0x00000078;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+ (void)(tmp);
+
+ /* Connect PDx pins to FSMC Alternate function */
+ GPIOD->AFR[0] = 0x00CCC0CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A8A;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0FCF;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FSMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA828A;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FSMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA000AAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FSMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x000000C0;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00085AAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0x000CAFFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*--FSMC Configuration -------------------------------------------------------*/
+ /* Enable the FSMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+ /* Configure and enable Bank1_SRAM2 */
+ FSMC_Bank1->BTCR[2] = 0x00001011;
+ FSMC_Bank1->BTCR[3] = 0x00000201;
+ FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc
new file mode 100644
index 0000000000000000000000000000000000000000..6833480982f107e1793327642729aa184af14c6a
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc
@@ -0,0 +1,106 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+Mcu.Family=STM32F2
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=USART3
+Mcu.IPNb=4
+Mcu.Name=STM32F207Z(C-E-F-G)Tx
+Mcu.Package=LQFP144
+Mcu.Pin0=PB14
+Mcu.Pin1=PD8
+Mcu.Pin2=PD9
+Mcu.Pin3=VP_SYS_VS_Systick
+Mcu.PinsNb=4
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32F207ZGTx
+MxCube.Version=6.2.0
+MxDb.Version=DB.6.0.20
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PB14.Locked=true
+PB14.Signal=GPIO_Output
+PD8.Locked=true
+PD8.Mode=Asynchronous
+PD8.Signal=USART3_TX
+PD9.Locked=true
+PD9.Mode=Asynchronous
+PD9.Signal=USART3_RX
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32F207ZGTx
+ProjectManager.FirmwarePackage=STM32Cube FW_F2 V1.9.2
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=0
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CubeMX_Config.ioc
+ProjectManager.ProjectName=CubeMX_Config
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=MDK-ARM V5
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true
+RCC.48MHZClocksFreq_Value=60000000
+RCC.AHBFreq_Value=120000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV4
+RCC.APB1Freq_Value=30000000
+RCC.APB1TimFreq_Value=60000000
+RCC.APB2CLKDivider=RCC_HCLK_DIV2
+RCC.APB2Freq_Value=60000000
+RCC.APB2TimFreq_Value=120000000
+RCC.CortexFreq_Value=120000000
+RCC.EthernetFreq_Value=120000000
+RCC.FCLKCortexFreq_Value=120000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=120000000
+RCC.HSE_VALUE=25000000
+RCC.HSI_VALUE=16000000
+RCC.I2SClocksFreq_Value=118153846.15384614
+RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO2PinFreq_Value=120000000
+RCC.PLLCLKFreq_Value=120000000
+RCC.PLLM=13
+RCC.PLLN=195
+RCC.RTCFreq_Value=32000
+RCC.RTCHSEDivFreq_Value=12500000
+RCC.SYSCLKFreq_VALUE=120000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.VCOI2SOutputFreq_Value=236307692.3076923
+RCC.VCOInputFreq_Value=1230769.2307692308
+RCC.VCOOutputFreq_Value=240000000
+RCC.VcooutputI2S=118153846.15384614
+USART3.IPParameters=VirtualMode
+USART3.VirtualMode=VM_ASYNC
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/Kconfig b/bsp/stm32/stm32f207-st-nucleo/board/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..5aa107d6acdf3d48a149d457d87dad699328fa94
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/Kconfig
@@ -0,0 +1,39 @@
+menu "Hardware Drivers Config"
+
+config SOC_STM32F207ZG
+ bool
+ select SOC_SERIES_STM32F2
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+ config BSP_USING_GPIO
+ bool "Enable GPIO"
+ select RT_USING_PIN
+ default y
+
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default y
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ config BSP_USING_UART3
+ bool "Enable UART3"
+ default y
+ endif
+
+ source "libraries/HAL_Drivers/Kconfig"
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/SConscript b/bsp/stm32/stm32f207-st-nucleo/board/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..fba49958f966cb50f42ae46d3a81c2d4ccd68bac
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/SConscript
@@ -0,0 +1,32 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+CubeMX_Config/Core/Src/stm32f2xx_hal_msp.c
+''')
+
+path = [cwd]
+path += [cwd + '/CubeMX_Config/Core/Inc']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+ src += [startup_path_prefix + '/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f207xx.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src += [startup_path_prefix + '/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f207xx.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src += [startup_path_prefix + '/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f207xx.s']
+
+# STM32F205xx || STM32F207xx || STM32F215xx
+# STM32F217xx
+# You can select chips from the list above
+CPPDEFINES = ['STM32F207xx']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+Return('group')
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/board.c b/bsp/stm32/stm32f207-st-nucleo/board/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..efc28d32e87f8c03ee0e06fdf17cbb5df8b14d55
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/board.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-06 SummerGift first version
+ */
+
+#include "board.h"
+
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 13;
+ RCC_OscInitStruct.PLL.PLLN = 195;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 4;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/board.h b/bsp/stm32/stm32f207-st-nucleo/board/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..77143ecb0eadd792ce3fb66a609e5dea9bede0fd
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/board.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-5 SummerGift first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include
+#include
+#include "drv_common.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
+#define STM32_FLASH_SIZE (1024 * 1024)
+#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
+
+/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/
+#define STM32_SRAM_SIZE 128
+#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN ((void *)&__bss_end)
+#endif
+
+#define HEAP_END STM32_SRAM_END
+
+void SystemClock_Config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H__ */
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.icf
new file mode 100644
index 0000000000000000000000000000000000000000..067691151fc3f4882a9e276ee7ec08ada97a9e3d
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0400;
+define symbol __ICFEDIT_size_heap__ = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.lds
new file mode 100644
index 0000000000000000000000000000000000000000..8f785689ace24e6934d1665abcd59159e44e73d3
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.lds
@@ -0,0 +1,143 @@
+/*
+ * linker script for STM32F10x with GNU ld
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+ ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
+ RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _stext = .;
+ KEEP(*(.isr_vector)) /* Startup code */
+
+ . = ALIGN(4);
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+
+ . = ALIGN(4);
+ _etext = .;
+ } > ROM = 0
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = .;
+ } > ROM
+ __exidx_end = .;
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_sidata)
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >RAM
+
+ .stack :
+ {
+ . = ALIGN(4);
+ _sstack = .;
+ . = . + _system_stack_size;
+ . = ALIGN(4);
+ _estack = .;
+ } >RAM
+
+ __bss_start = .;
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+
+ *(.bss.init)
+ } > RAM
+ __bss_end = .;
+
+ _end = .;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
diff --git a/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.sct b/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.sct
new file mode 100644
index 0000000000000000000000000000000000000000..0d7c47992d534c7779fea3df8bb47bb75c11bbc7
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/board/linker_scripts/link.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00100000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00020000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/stm32/stm32f207-st-nucleo/figures/board.jpg b/bsp/stm32/stm32f207-st-nucleo/figures/board.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..49a29915b23ebab9a675c2dcf4fa979a101d1c2e
Binary files /dev/null and b/bsp/stm32/stm32f207-st-nucleo/figures/board.jpg differ
diff --git a/bsp/stm32/stm32f207-st-nucleo/makefile.targets b/bsp/stm32/stm32f207-st-nucleo/makefile.targets
new file mode 100644
index 0000000000000000000000000000000000000000..e71da5a6e1e87e11715cee3ed2297204f7bcf380
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/makefile.targets
@@ -0,0 +1,6 @@
+clean2:
+ -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS)
+ -$(RM) $(OBJS) *.elf
+ -@echo ' '
+
+*.elf: $(wildcard ../linkscripts/*/*.lds) $(wildcard ../linkscripts/*/*/*.lds)
\ No newline at end of file
diff --git a/bsp/stm32/stm32f207-st-nucleo/project.ewd b/bsp/stm32/stm32f207-st-nucleo/project.ewd
new file mode 100644
index 0000000000000000000000000000000000000000..211a0959100c2a111350c2498a344960670baadc
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/project.ewd
@@ -0,0 +1,2966 @@
+
+
+ 3
+
+ rtthread
+
+ ARM
+
+ 1
+
+ C-SPY
+ 2
+
+ 31
+ 1
+ 1
+
+ CInput
+ 1
+
+
+ CEndian
+ 1
+
+
+ CProcessor
+ 1
+
+
+ OCVariant
+ 0
+
+
+ MacOverride
+ 0
+
+
+ MacFile
+
+
+
+ MemOverride
+ 0
+
+
+ MemFile
+ $TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F207ZG.ddf
+
+
+ RunToEnable
+ 1
+
+
+ RunToName
+ main
+
+
+ CExtraOptionsCheck
+ 0
+
+
+ CExtraOptions
+
+
+
+ CFpuProcessor
+ 1
+
+
+ OCDDFArgumentProducer
+
+
+
+ OCDownloadSuppressDownload
+ 0
+
+
+ OCDownloadVerifyAll
+ 0
+
+
+ OCProductVersion
+ 8.40.1.21529
+
+
+ OCDynDriverList
+ STLINK_ID
+
+
+ OCLastSavedByProductVersion
+ 8.40.1.21529
+
+
+ UseFlashLoader
+ 1
+
+
+ CLowLevel
+ 1
+
+
+ OCBE8Slave
+ 1
+
+
+ MacFile2
+
+
+
+ CDevice
+ 1
+
+
+ FlashLoadersV3
+ $TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F205xG.board
+
+
+ OCImagesSuppressCheck1
+ 0
+
+
+ OCImagesPath1
+
+
+
+ OCImagesSuppressCheck2
+ 0
+
+
+ OCImagesPath2
+
+
+
+ OCImagesSuppressCheck3
+ 0
+
+
+ OCImagesPath3
+
+
+
+ OverrideDefFlashBoard
+ 0
+
+
+ OCImagesOffset1
+
+
+
+ OCImagesOffset2
+
+
+
+ OCImagesOffset3
+
+
+
+ OCImagesUse1
+ 0
+
+
+ OCImagesUse2
+ 0
+
+
+ OCImagesUse3
+ 0
+
+
+ OCDeviceConfigMacroFile
+ 1
+
+
+ OCDebuggerExtraOption
+ 1
+
+
+ OCAllMTBOptions
+ 1
+
+
+ OCMulticoreNrOfCores
+ 1
+
+
+ OCMulticoreWorkspace
+
+
+
+ OCMulticoreSlaveProject
+
+
+
+ OCMulticoreSlaveConfiguration
+
+
+
+ OCDownloadExtraImage
+ 1
+
+
+ OCAttachSlave
+ 0
+
+
+ MassEraseBeforeFlashing
+ 0
+
+
+ OCMulticoreNrOfCoresSlave
+ 1
+
+
+ OCMulticoreAMPConfigType
+ 0
+
+
+ OCMulticoreSessionFile
+
+
+
+
+
+ ARMSIM_ID
+ 2
+
+ 1
+ 1
+ 1
+
+ OCSimDriverInfo
+ 1
+
+
+ OCSimEnablePSP
+ 0
+
+
+ OCSimPspOverrideConfig
+ 0
+
+
+ OCSimPspConfigFile
+
+
+
+
+
+ CADI_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ CCadiMemory
+ 1
+
+
+ Fast Model
+
+
+
+ CCADILogFileCheck
+ 0
+
+
+ CCADILogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ CMSISDAP_ID
+ 2
+
+ 4
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ CMSISDAPResetList
+ 1
+ 10
+
+
+ CMSISDAPHWResetDuration
+ 300
+
+
+ CMSISDAPHWResetDelay
+ 200
+
+
+ CMSISDAPDoLogfile
+ 0
+
+
+ CMSISDAPLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CMSISDAPInterfaceRadio
+ 0
+
+
+ CMSISDAPInterfaceCmdLine
+ 0
+
+
+ CMSISDAPMultiTargetEnable
+ 0
+
+
+ CMSISDAPMultiTarget
+ 0
+
+
+ CMSISDAPJtagSpeedList
+ 0
+ 0
+
+
+ CMSISDAPBreakpointRadio
+ 0
+
+
+ CMSISDAPRestoreBreakpointsCheck
+ 0
+
+
+ CMSISDAPUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ CMSISDAPMultiCPUEnable
+ 0
+
+
+ CMSISDAPMultiCPUNumber
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+
+ CMSISDAPProbeConfigRadio
+ 0
+
+
+ CMSISDAPSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+
+ OCJetEmuParams
+ 1
+
+
+ CCCMSISDAPUsbSerialNo
+
+
+
+ CCCMSISDAPUsbSerialNoSelect
+ 0
+
+
+
+
+ GDBSERVER_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ TCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJTagBreakpointRadio
+ 0
+
+
+ CCJTagDoUpdateBreakpoints
+ 0
+
+
+ CCJTagUpdateBreakpoints
+ _call_main
+
+
+
+
+ IJET_ID
+ 2
+
+ 8
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ IjetResetList
+ 1
+ 10
+
+
+ IjetHWResetDuration
+ 300
+
+
+ IjetHWResetDelay
+ 200
+
+
+ IjetPowerFromProbe
+ 1
+
+
+ IjetPowerRadio
+ 0
+
+
+ IjetDoLogfile
+ 0
+
+
+ IjetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ IjetInterfaceRadio
+ 0
+
+
+ IjetInterfaceCmdLine
+ 0
+
+
+ IjetMultiTargetEnable
+ 0
+
+
+ IjetMultiTarget
+ 0
+
+
+ IjetScanChainNonARMDevices
+ 0
+
+
+ IjetIRLength
+ 0
+
+
+ IjetJtagSpeedList
+ 0
+ 0
+
+
+ IjetProtocolRadio
+ 0
+
+
+ IjetSwoPin
+ 0
+
+
+ IjetCpuClockEdit
+
+
+
+ IjetSwoPrescalerList
+ 1
+ 0
+
+
+ IjetBreakpointRadio
+ 0
+
+
+ IjetRestoreBreakpointsCheck
+ 0
+
+
+ IjetUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+
+ IjetProbeConfigRadio
+ 0
+
+
+ IjetMultiCPUEnable
+ 0
+
+
+ IjetMultiCPUNumber
+ 0
+
+
+ IjetSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+
+ OCJetEmuParams
+ 1
+
+
+ IjetPreferETB
+ 1
+
+
+ IjetTraceSettingsList
+ 0
+ 0
+
+
+ IjetTraceSizeList
+ 0
+ 4
+
+
+ FlashBoardPathSlave
+ 0
+
+
+ CCIjetUsbSerialNo
+
+
+
+ CCIjetUsbSerialNoSelect
+ 0
+
+
+
+
+ JLINK_ID
+ 2
+
+ 16
+ 1
+ 1
+
+ JLinkSpeed
+ 1000
+
+
+ CCJLinkDoLogfile
+ 0
+
+
+ CCJLinkLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJLinkHWResetDelay
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+ JLinkInitialSpeed
+ 1000
+
+
+ CCDoJlinkMultiTarget
+ 0
+
+
+ CCScanChainNonARMDevices
+ 0
+
+
+ CCJLinkMultiTarget
+ 0
+
+
+ CCJLinkIRLength
+ 0
+
+
+ CCJLinkCommRadio
+ 0
+
+
+ CCJLinkTCPIP
+ aaa.bbb.ccc.ddd
+
+
+ CCJLinkSpeedRadioV2
+ 0
+
+
+ CCUSBDevice
+ 1
+ 1
+
+
+ CCRDICatchReset
+ 0
+
+
+ CCRDICatchUndef
+ 0
+
+
+ CCRDICatchSWI
+ 0
+
+
+ CCRDICatchData
+ 0
+
+
+ CCRDICatchPrefetch
+ 0
+
+
+ CCRDICatchIRQ
+ 0
+
+
+ CCRDICatchFIQ
+ 0
+
+
+ CCJLinkBreakpointRadio
+ 0
+
+
+ CCJLinkDoUpdateBreakpoints
+ 0
+
+
+ CCJLinkUpdateBreakpoints
+ _call_main
+
+
+ CCJLinkInterfaceRadio
+ 0
+
+
+ CCJLinkResetList
+ 6
+ 5
+
+
+ CCJLinkInterfaceCmdLine
+ 0
+
+
+ CCCatchCORERESET
+ 0
+
+
+ CCCatchMMERR
+ 0
+
+
+ CCCatchNOCPERR
+ 0
+
+
+ CCCatchCHRERR
+ 0
+
+
+ CCCatchSTATERR
+ 0
+
+
+ CCCatchBUSERR
+ 0
+
+
+ CCCatchINTERR
+ 0
+
+
+ CCCatchSFERR
+ 0
+
+
+ CCCatchHARDERR
+ 0
+
+
+ CCCatchDummy
+ 0
+
+
+ OCJLinkScriptFile
+ 1
+
+
+ CCJLinkUsbSerialNo
+
+
+
+ CCTcpIpAlt
+ 0
+ 0
+
+
+ CCJLinkTcpIpSerialNo
+
+
+
+ CCCpuClockEdit
+
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ OCJLinkTraceSource
+ 0
+
+
+ OCJLinkTraceSourceDummy
+ 0
+
+
+ OCJLinkDeviceName
+ 1
+
+
+
+
+ LMIFTDI_ID
+ 2
+
+ 2
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ LmiftdiSpeed
+ 500
+
+
+ CCLmiftdiDoLogfile
+ 0
+
+
+ CCLmiftdiLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCLmiFtdiInterfaceRadio
+ 0
+
+
+ CCLmiFtdiInterfaceCmdLine
+ 0
+
+
+
+
+ NULINK_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ PEMICRO_ID
+ 2
+
+ 3
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCJPEMicroShowSettings
+ 0
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ STLINK_ID
+ 2
+
+ 6
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCSTLinkInterfaceRadio
+ 1
+
+
+ CCSTLinkInterfaceCmdLine
+ 0
+
+
+ CCSTLinkResetList
+ 3
+ 0
+
+
+ CCCpuClockEdit
+ 120.0
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCSTLinkDoUpdateBreakpoints
+ 0
+
+
+ CCSTLinkUpdateBreakpoints
+ _call_main
+
+
+ CCSTLinkCatchCORERESET
+ 0
+
+
+ CCSTLinkCatchMMERR
+ 0
+
+
+ CCSTLinkCatchNOCPERR
+ 0
+
+
+ CCSTLinkCatchCHRERR
+ 0
+
+
+ CCSTLinkCatchSTATERR
+ 0
+
+
+ CCSTLinkCatchBUSERR
+ 0
+
+
+ CCSTLinkCatchINTERR
+ 0
+
+
+ CCSTLinkCatchSFERR
+ 0
+
+
+ CCSTLinkCatchHARDERR
+ 0
+
+
+ CCSTLinkCatchDummy
+ 0
+
+
+ CCSTLinkUsbSerialNo
+
+
+
+ CCSTLinkUsbSerialNoSelect
+ 0
+
+
+ CCSTLinkJtagSpeedList
+ 2
+ 0
+
+
+ CCSTLinkDAPNumber
+
+
+
+ CCSTLinkDebugAccessPortRadio
+ 0
+
+
+ CCSTLinkUseServerSelect
+ 0
+
+
+ CCSTLinkProbeList
+ 0
+ 1
+
+
+
+
+ THIRDPARTY_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ CThirdPartyDriverDll
+ ###Uninitialized###
+
+
+ CThirdPartyLogFileCheck
+ 0
+
+
+ CThirdPartyLogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ TIFET_ID
+ 2
+
+ 1
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCMSPFetResetList
+ 0
+ 0
+
+
+ CCMSPFetInterfaceRadio
+ 0
+
+
+ CCMSPFetInterfaceCmdLine
+ 0
+
+
+ CCMSPFetTargetVccTypeDefault
+ 0
+
+
+ CCMSPFetTargetVoltage
+ ###Uninitialized###
+
+
+ CCMSPFetVCCDefault
+ 1
+
+
+ CCMSPFetTargetSettlingtime
+ 0
+
+
+ CCMSPFetRadioJtagSpeedType
+ 1
+
+
+ CCMSPFetConnection
+ 0
+ 0
+
+
+ CCMSPFetUsbComPort
+ Automatic
+
+
+ CCMSPFetAllowAccessToBSL
+ 0
+
+
+ CCMSPFetDoLogfile
+ 0
+
+
+ CCMSPFetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCMSPFetRadioEraseFlash
+ 1
+
+
+
+
+ XDS100_ID
+ 2
+
+ 8
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ TIPackageOverride
+ 0
+
+
+ TIPackage
+
+
+
+ BoardFile
+
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCXds100BreakpointRadio
+ 0
+
+
+ CCXds100DoUpdateBreakpoints
+ 0
+
+
+ CCXds100UpdateBreakpoints
+ _call_main
+
+
+ CCXds100CatchReset
+ 0
+
+
+ CCXds100CatchUndef
+ 0
+
+
+ CCXds100CatchSWI
+ 0
+
+
+ CCXds100CatchData
+ 0
+
+
+ CCXds100CatchPrefetch
+ 0
+
+
+ CCXds100CatchIRQ
+ 0
+
+
+ CCXds100CatchFIQ
+ 0
+
+
+ CCXds100CatchCORERESET
+ 0
+
+
+ CCXds100CatchMMERR
+ 0
+
+
+ CCXds100CatchNOCPERR
+ 0
+
+
+ CCXds100CatchCHRERR
+ 0
+
+
+ CCXds100CatchSTATERR
+ 0
+
+
+ CCXds100CatchBUSERR
+ 0
+
+
+ CCXds100CatchINTERR
+ 0
+
+
+ CCXds100CatchSFERR
+ 0
+
+
+ CCXds100CatchHARDERR
+ 0
+
+
+ CCXds100CatchDummy
+ 0
+
+
+ CCXds100CpuClockEdit
+
+
+
+ CCXds100SwoClockAuto
+ 0
+
+
+ CCXds100SwoClockEdit
+ 1000
+
+
+ CCXds100HWResetDelay
+ 0
+
+
+ CCXds100ResetList
+ 0
+ 0
+
+
+ CCXds100UsbSerialNo
+
+
+
+ CCXds100UsbSerialNoSelect
+ 0
+
+
+ CCXds100JtagSpeedList
+ 0
+ 0
+
+
+ CCXds100InterfaceRadio
+ 2
+
+
+ CCXds100InterfaceCmdLine
+ 0
+
+
+ CCXds100ProbeList
+ 0
+ 3
+
+
+ CCXds100SWOPortRadio
+ 0
+
+
+ CCXds100SWOPort
+ 1
+
+
+ CCXDSTargetVccEnable
+ 0
+
+
+ CCXDSTargetVoltage
+ ###Uninitialized###
+
+
+ OCXDSDigitalStatesConfigFile
+ 1
+
+
+
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+ 0
+
+
+
+
+ Release
+
+ ARM
+
+ 0
+
+ C-SPY
+ 2
+
+ 31
+ 1
+ 0
+
+ CInput
+ 1
+
+
+ CEndian
+ 1
+
+
+ CProcessor
+ 1
+
+
+ OCVariant
+ 0
+
+
+ MacOverride
+ 0
+
+
+ MacFile
+
+
+
+ MemOverride
+ 0
+
+
+ MemFile
+
+
+
+ RunToEnable
+ 1
+
+
+ RunToName
+ main
+
+
+ CExtraOptionsCheck
+ 0
+
+
+ CExtraOptions
+
+
+
+ CFpuProcessor
+ 1
+
+
+ OCDDFArgumentProducer
+
+
+
+ OCDownloadSuppressDownload
+ 0
+
+
+ OCDownloadVerifyAll
+ 0
+
+
+ OCProductVersion
+ 8.11.3.13977
+
+
+ OCDynDriverList
+ ARMSIM_ID
+
+
+ OCLastSavedByProductVersion
+
+
+
+ UseFlashLoader
+ 1
+
+
+ CLowLevel
+ 1
+
+
+ OCBE8Slave
+ 1
+
+
+ MacFile2
+
+
+
+ CDevice
+ 1
+
+
+ FlashLoadersV3
+
+
+
+ OCImagesSuppressCheck1
+ 0
+
+
+ OCImagesPath1
+
+
+
+ OCImagesSuppressCheck2
+ 0
+
+
+ OCImagesPath2
+
+
+
+ OCImagesSuppressCheck3
+ 0
+
+
+ OCImagesPath3
+
+
+
+ OverrideDefFlashBoard
+ 0
+
+
+ OCImagesOffset1
+
+
+
+ OCImagesOffset2
+
+
+
+ OCImagesOffset3
+
+
+
+ OCImagesUse1
+ 0
+
+
+ OCImagesUse2
+ 0
+
+
+ OCImagesUse3
+ 0
+
+
+ OCDeviceConfigMacroFile
+ 1
+
+
+ OCDebuggerExtraOption
+ 1
+
+
+ OCAllMTBOptions
+ 1
+
+
+ OCMulticoreNrOfCores
+
+
+
+ OCMulticoreWorkspace
+
+
+
+ OCMulticoreSlaveProject
+
+
+
+ OCMulticoreSlaveConfiguration
+
+
+
+ OCDownloadExtraImage
+ 1
+
+
+ OCAttachSlave
+ 0
+
+
+ MassEraseBeforeFlashing
+ 0
+
+
+ OCMulticoreNrOfCoresSlave
+ 1
+
+
+ OCMulticoreAMPConfigType
+ 0
+
+
+ OCMulticoreSessionFile
+
+
+
+
+
+ ARMSIM_ID
+ 2
+
+ 1
+ 1
+ 0
+
+ OCSimDriverInfo
+ 1
+
+
+ OCSimEnablePSP
+ 0
+
+
+ OCSimPspOverrideConfig
+ 0
+
+
+ OCSimPspConfigFile
+
+
+
+
+
+ CADI_ID
+ 2
+
+ 0
+ 1
+ 0
+
+ CCadiMemory
+ 1
+
+
+ Fast Model
+
+
+
+ CCADILogFileCheck
+ 0
+
+
+ CCADILogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ CMSISDAP_ID
+ 2
+
+ 4
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ CMSISDAPResetList
+ 1
+ 10
+
+
+ CMSISDAPHWResetDuration
+ 300
+
+
+ CMSISDAPHWResetDelay
+ 200
+
+
+ CMSISDAPDoLogfile
+ 0
+
+
+ CMSISDAPLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CMSISDAPInterfaceRadio
+ 0
+
+
+ CMSISDAPInterfaceCmdLine
+ 0
+
+
+ CMSISDAPMultiTargetEnable
+ 0
+
+
+ CMSISDAPMultiTarget
+ 0
+
+
+ CMSISDAPJtagSpeedList
+ 0
+ 0
+
+
+ CMSISDAPBreakpointRadio
+ 0
+
+
+ CMSISDAPRestoreBreakpointsCheck
+ 0
+
+
+ CMSISDAPUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ CMSISDAPMultiCPUEnable
+ 0
+
+
+ CMSISDAPMultiCPUNumber
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+
+ CMSISDAPProbeConfigRadio
+ 0
+
+
+ CMSISDAPSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+
+ OCJetEmuParams
+ 1
+
+
+ CCCMSISDAPUsbSerialNo
+
+
+
+ CCCMSISDAPUsbSerialNoSelect
+ 0
+
+
+
+
+ GDBSERVER_ID
+ 2
+
+ 0
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ TCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJTagBreakpointRadio
+ 0
+
+
+ CCJTagDoUpdateBreakpoints
+ 0
+
+
+ CCJTagUpdateBreakpoints
+ _call_main
+
+
+
+
+ IJET_ID
+ 2
+
+ 8
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ IjetResetList
+ 1
+ 10
+
+
+ IjetHWResetDuration
+ 300
+
+
+ IjetHWResetDelay
+ 200
+
+
+ IjetPowerFromProbe
+ 1
+
+
+ IjetPowerRadio
+ 0
+
+
+ IjetDoLogfile
+ 0
+
+
+ IjetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ IjetInterfaceRadio
+ 0
+
+
+ IjetInterfaceCmdLine
+ 0
+
+
+ IjetMultiTargetEnable
+ 0
+
+
+ IjetMultiTarget
+ 0
+
+
+ IjetScanChainNonARMDevices
+ 0
+
+
+ IjetIRLength
+ 0
+
+
+ IjetJtagSpeedList
+ 0
+ 0
+
+
+ IjetProtocolRadio
+ 0
+
+
+ IjetSwoPin
+ 0
+
+
+ IjetCpuClockEdit
+
+
+
+ IjetSwoPrescalerList
+ 1
+ 0
+
+
+ IjetBreakpointRadio
+ 0
+
+
+ IjetRestoreBreakpointsCheck
+ 0
+
+
+ IjetUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+
+ IjetProbeConfigRadio
+ 0
+
+
+ IjetMultiCPUEnable
+ 0
+
+
+ IjetMultiCPUNumber
+ 0
+
+
+ IjetSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+
+ OCJetEmuParams
+ 1
+
+
+ IjetPreferETB
+ 1
+
+
+ IjetTraceSettingsList
+ 0
+ 0
+
+
+ IjetTraceSizeList
+ 0
+ 4
+
+
+ FlashBoardPathSlave
+ 0
+
+
+ CCIjetUsbSerialNo
+
+
+
+ CCIjetUsbSerialNoSelect
+ 0
+
+
+
+
+ JLINK_ID
+ 2
+
+ 16
+ 1
+ 0
+
+ JLinkSpeed
+ 1000
+
+
+ CCJLinkDoLogfile
+ 0
+
+
+ CCJLinkLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJLinkHWResetDelay
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+ JLinkInitialSpeed
+ 1000
+
+
+ CCDoJlinkMultiTarget
+ 0
+
+
+ CCScanChainNonARMDevices
+ 0
+
+
+ CCJLinkMultiTarget
+ 0
+
+
+ CCJLinkIRLength
+ 0
+
+
+ CCJLinkCommRadio
+ 0
+
+
+ CCJLinkTCPIP
+ aaa.bbb.ccc.ddd
+
+
+ CCJLinkSpeedRadioV2
+ 0
+
+
+ CCUSBDevice
+ 1
+ 1
+
+
+ CCRDICatchReset
+ 0
+
+
+ CCRDICatchUndef
+ 0
+
+
+ CCRDICatchSWI
+ 0
+
+
+ CCRDICatchData
+ 0
+
+
+ CCRDICatchPrefetch
+ 0
+
+
+ CCRDICatchIRQ
+ 0
+
+
+ CCRDICatchFIQ
+ 0
+
+
+ CCJLinkBreakpointRadio
+ 0
+
+
+ CCJLinkDoUpdateBreakpoints
+ 0
+
+
+ CCJLinkUpdateBreakpoints
+ _call_main
+
+
+ CCJLinkInterfaceRadio
+ 0
+
+
+ CCJLinkResetList
+ 6
+ 5
+
+
+ CCJLinkInterfaceCmdLine
+ 0
+
+
+ CCCatchCORERESET
+ 0
+
+
+ CCCatchMMERR
+ 0
+
+
+ CCCatchNOCPERR
+ 0
+
+
+ CCCatchCHRERR
+ 0
+
+
+ CCCatchSTATERR
+ 0
+
+
+ CCCatchBUSERR
+ 0
+
+
+ CCCatchINTERR
+ 0
+
+
+ CCCatchSFERR
+ 0
+
+
+ CCCatchHARDERR
+ 0
+
+
+ CCCatchDummy
+ 0
+
+
+ OCJLinkScriptFile
+ 1
+
+
+ CCJLinkUsbSerialNo
+
+
+
+ CCTcpIpAlt
+ 0
+ 0
+
+
+ CCJLinkTcpIpSerialNo
+
+
+
+ CCCpuClockEdit
+
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ OCJLinkTraceSource
+ 0
+
+
+ OCJLinkTraceSourceDummy
+ 0
+
+
+ OCJLinkDeviceName
+ 1
+
+
+
+
+ LMIFTDI_ID
+ 2
+
+ 2
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ LmiftdiSpeed
+ 500
+
+
+ CCLmiftdiDoLogfile
+ 0
+
+
+ CCLmiftdiLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCLmiFtdiInterfaceRadio
+ 0
+
+
+ CCLmiFtdiInterfaceCmdLine
+ 0
+
+
+
+
+ NULINK_ID
+ 2
+
+ 0
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ PEMICRO_ID
+ 2
+
+ 3
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ CCJPEMicroShowSettings
+ 0
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ STLINK_ID
+ 2
+
+ 6
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ CCSTLinkInterfaceRadio
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+ 0
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+ 0
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+
+
+
diff --git a/bsp/stm32/stm32f207-st-nucleo/project.ewp b/bsp/stm32/stm32f207-st-nucleo/project.ewp
new file mode 100644
index 0000000000000000000000000000000000000000..7f6bc20f73421f4347a3f9b8287e787fa4a400fb
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/project.ewp
@@ -0,0 +1,2315 @@
+
+ 3
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+ rtthread
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+ build\iar\Exe
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+ Automatic choice of formatter, without multibyte support.
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+ Automatic choice of formatter, without multibyte support.
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+ Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+
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+ OGProductVersion
+ 6.30.6.53380
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+ OGChipSelectEditMenu
+ STM32F207ZG ST STM32F207ZG
+
+
+ GenLowLevelInterface
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+
+ GEndianModeBE
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+ OGBufferedTerminalOutput
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+
+ CoreVariant
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+ GFPUDeviceSlave
+ STM32F207ZG ST STM32F207ZG
+
+
+ FPU2
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diff --git a/bsp/stm32/stm32f207-st-nucleo/project.eww b/bsp/stm32/stm32f207-st-nucleo/project.eww
new file mode 100644
index 0000000000000000000000000000000000000000..c2cb02eb1e89d73e24183274c1c886ddf74f9537
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/project.eww
@@ -0,0 +1,10 @@
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+
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diff --git a/bsp/stm32/stm32f207-st-nucleo/project.uvopt b/bsp/stm32/stm32f207-st-nucleo/project.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..7946319ef93db8bc541b3471e1621191e6ad0d99
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/project.uvopt
@@ -0,0 +1,162 @@
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+
+
+ 1.0
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+ ### uVision Project, (C) Keil Software
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diff --git a/bsp/stm32/stm32f207-st-nucleo/project.uvoptx b/bsp/stm32/stm32f207-st-nucleo/project.uvoptx
new file mode 100644
index 0000000000000000000000000000000000000000..8441e1cc37f661d4a9568d2a5fba6d64947a77f8
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/project.uvoptx
@@ -0,0 +1,853 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
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+
+ *.c
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+
+
+ 0
+ JL2CM3
+ -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN0
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F2xx_1024 -FL080000 -FS08000000 -FP0($$Device:STM32F207VETx$CMSIS\Flash\STM32F2xx_1024.FLM)
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diff --git a/bsp/stm32/stm32f207-st-nucleo/project.uvproj b/bsp/stm32/stm32f207-st-nucleo/project.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..f7cd8f7822decd316ab73cffe692fabc45f83403
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/project.uvproj
@@ -0,0 +1,1126 @@
+
+
+ 1.1
+ ### uVision Project, (C) Keil Software
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+
+ STM32F103RB
+ STMicroelectronics
+ IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")
+
+ "STARTUP\ST\STM32F10x\startup_stm32f10x_md.s" ("STM32 Medium Density Line Startup Code")
+ UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)
+ 4231
+ stm32f10x.h
+
+
+
+
+
+
+
+
+
+ SFD\ST\STM32F1xx\STM32F103xx.sfr
+ 0
+ 0
+
+
+
+ ST\STM32F10x\
+ ST\STM32F10x\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\build\keil\Obj\
+ rt-thread
+ 1
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+ .\build\keil\List\
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+
+ 0
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+
+
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+ 1
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+ fromelf --bin !L --output rtthread.bin
+
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+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+
+ DARMSTM.DLL
+ -pSTM32F103RB
+ SARMCM3.DLL
+
+ TARMSTM.DLL
+ -pSTM32F103RB
+
+
+
+ 1
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+
+
+
+
+
+
+
+ Segger\JL2CM3.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+
+
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+ "Cortex-M3"
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+
+
+ STM32F103xB, USE_HAL_DRIVER
+
+ applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m3;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Include;..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Inc;..\libraries\STM32F1xx_HAL\CMSIS\Include
+
+
+
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+
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+ .\board\linker_scripts\link.sct
+
+
+ --keep *.o(.rti_fn.*) --keep *.o(FSymTab)
+
+
+
+
+
+
+
+ Applications
+
+
+ main.c
+ 1
+ applications\main.c
+
+
+
+
+ Drivers
+
+
+ board.c
+ 1
+ board\board.c
+
+
+
+
+ stm32f1xx_hal_msp.c
+ 1
+ board\CubeMX_Config\Src\stm32f1xx_hal_msp.c
+
+
+
+
+ startup_stm32f103xb.s
+ 2
+ ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\arm\startup_stm32f103xb.s
+
+
+
+
+ drv_gpio.c
+ 1
+ ..\libraries\HAL_Drivers\drv_gpio.c
+
+
+
+
+ drv_usart.c
+ 1
+ ..\libraries\HAL_Drivers\drv_usart.c
+
+
+
+
+ drv_common.c
+ 1
+ ..\libraries\HAL_Drivers\drv_common.c
+
+
+
+
+ Kernel
+
+
+ clock.c
+ 1
+ ..\..\..\src\clock.c
+
+
+
+
+ components.c
+ 1
+ ..\..\..\src\components.c
+
+
+
+
+ device.c
+ 1
+ ..\..\..\src\device.c
+
+
+
+
+ idle.c
+ 1
+ ..\..\..\src\idle.c
+
+
+
+
+ ipc.c
+ 1
+ ..\..\..\src\ipc.c
+
+
+
+
+ irq.c
+ 1
+ ..\..\..\src\irq.c
+
+
+
+
+ kservice.c
+ 1
+ ..\..\..\src\kservice.c
+
+
+
+
+ mem.c
+ 1
+ ..\..\..\src\mem.c
+
+
+
+
+ mempool.c
+ 1
+ ..\..\..\src\mempool.c
+
+
+
+
+ object.c
+ 1
+ ..\..\..\src\object.c
+
+
+
+
+ scheduler.c
+ 1
+ ..\..\..\src\scheduler.c
+
+
+
+
+ signal.c
+ 1
+ ..\..\..\src\signal.c
+
+
+
+
+ thread.c
+ 1
+ ..\..\..\src\thread.c
+
+
+
+
+ timer.c
+ 1
+ ..\..\..\src\timer.c
+
+
+
+
+ CORTEX-M3
+
+
+ cpuport.c
+ 1
+ ..\..\..\libcpu\arm\cortex-m3\cpuport.c
+
+
+
+
+ context_rvds.S
+ 2
+ ..\..\..\libcpu\arm\cortex-m3\context_rvds.S
+
+
+
+
+ backtrace.c
+ 1
+ ..\..\..\libcpu\arm\common\backtrace.c
+
+
+
+
+ div0.c
+ 1
+ ..\..\..\libcpu\arm\common\div0.c
+
+
+
+
+ showmem.c
+ 1
+ ..\..\..\libcpu\arm\common\showmem.c
+
+
+
+
+ DeviceDrivers
+
+
+ pin.c
+ 1
+ ..\..\..\components\drivers\misc\pin.c
+
+
+
+
+ serial.c
+ 1
+ ..\..\..\components\drivers\serial\serial.c
+
+
+
+
+ completion.c
+ 1
+ ..\..\..\components\drivers\src\completion.c
+
+
+
+
+ dataqueue.c
+ 1
+ ..\..\..\components\drivers\src\dataqueue.c
+
+
+
+
+ pipe.c
+ 1
+ ..\..\..\components\drivers\src\pipe.c
+
+
+
+
+ ringblk_buf.c
+ 1
+ ..\..\..\components\drivers\src\ringblk_buf.c
+
+
+
+
+ ringbuffer.c
+ 1
+ ..\..\..\components\drivers\src\ringbuffer.c
+
+
+
+
+ waitqueue.c
+ 1
+ ..\..\..\components\drivers\src\waitqueue.c
+
+
+
+
+ workqueue.c
+ 1
+ ..\..\..\components\drivers\src\workqueue.c
+
+
+
+
+ finsh
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+
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diff --git a/bsp/stm32/stm32f207-st-nucleo/project.uvprojx b/bsp/stm32/stm32f207-st-nucleo/project.uvprojx
new file mode 100644
index 0000000000000000000000000000000000000000..208f7bd20d1479e48e8ad9791ac0da943b50113b
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/project.uvprojx
@@ -0,0 +1,698 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rtthread
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::.\ARMCC
+ 0
+
+
+ STM32F207VETx
+ STMicroelectronics
+ Keil.STM32F2xx_DFP.2.7.0
+ http://www.keil.com/pack
+ IROM(0x08000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL080000 -FP0($$Device:STM32F207VETx$CMSIS/Flash/STM32F2xx_1024.FLM))
+ 0
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+
+
+
+
+
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+ $$Device:STM32F207VETx$CMSIS\SVD\STM32F20x.svd
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+ SARMCM3.DLL
+ -REMAP -MPU
+ DCM.DLL
+ -pCM3
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+ -MPU
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+ "" ()
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+ USE_HAL_DRIVER, STM32F207xx, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
+
+ applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Core\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\libraries\STM32F2xx_HAL\CMSIS\Device\ST\STM32F2xx\Include;..\libraries\STM32F2xx_HAL\STM32F2xx_HAL_Driver\Inc;..\libraries\STM32F2xx_HAL\CMSIS\Include
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+
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+ Applications
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+ CPU
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+ Drivers
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+
+ stm32f2xx_hal_msp.c
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+
+
+ startup_stm32f207xx.s
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+
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+
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+
+ drv_usart.c
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+
+ drv_common.c
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+
+
+
+ finsh
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+
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+
+
+ msh.c
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+
+ cmd.c
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+
+
+
+ Kernel
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+
+ thread.c
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+
+ ipc.c
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+ clock.c
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+
+ mempool.c
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+
+ scheduler.c
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+
+ kservice.c
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+
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+
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+
+ libc
+
+
+ time.c
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+
+
+
+
+ Libraries
+
+
+ stm32f2xx_hal_usart.c
+ 1
+ ..\libraries\STM32F2xx_HAL\STM32F2xx_HAL_Driver\Src\stm32f2xx_hal_usart.c
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+ 1
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+
+
+ system_stm32f2xx.c
+ 1
+ ..\libraries\STM32F2xx_HAL\CMSIS\Device\ST\STM32F2xx\Source\Templates\system_stm32f2xx.c
+
+
+ stm32f2xx_hal_gpio.c
+ 1
+ ..\libraries\STM32F2xx_HAL\STM32F2xx_HAL_Driver\Src\stm32f2xx_hal_gpio.c
+
+
+ stm32f2xx_hal_rcc.c
+ 1
+ ..\libraries\STM32F2xx_HAL\STM32F2xx_HAL_Driver\Src\stm32f2xx_hal_rcc.c
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+
+ stm32f2xx_hal_crc.c
+ 1
+ ..\libraries\STM32F2xx_HAL\STM32F2xx_HAL_Driver\Src\stm32f2xx_hal_crc.c
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+
+
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+ 1
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+ 1
+ ..\libraries\STM32F2xx_HAL\STM32F2xx_HAL_Driver\Src\stm32f2xx_hal_rcc_ex.c
+
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diff --git a/bsp/stm32/stm32f207-st-nucleo/rtconfig.h b/bsp/stm32/stm32f207-st-nucleo/rtconfig.h
new file mode 100644
index 0000000000000000000000000000000000000000..93941825e71b25c03e8e1530cfcf221f5a6bc80b
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/rtconfig.h
@@ -0,0 +1,181 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart3"
+#define RT_VER_NUM 0x40003
+#define ARCH_ARM
+#define RT_USING_CPU_FFS
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M3
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_LIBC_USING_TIME
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+#define SOC_FAMILY_STM32
+#define SOC_SERIES_STM32F2
+
+/* Hardware Drivers Config */
+
+#define SOC_STM32F207ZG
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART3
+
+/* Board extended module Drivers */
+
+
+#endif
diff --git a/bsp/stm32/stm32f207-st-nucleo/rtconfig.py b/bsp/stm32/stm32f207-st-nucleo/rtconfig.py
new file mode 100644
index 0000000000000000000000000000000000000000..c3838da594e10184a6b6dc59d53adbfa90a9a5a6
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/rtconfig.py
@@ -0,0 +1,150 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m3'
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+ CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'gcc':
+ PLATFORM = 'gcc'
+ EXEC_PATH = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+ EXEC_PATH = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+ PLATFORM = 'iar'
+ EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ CXX = PREFIX + 'g++'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'elf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
+ CFLAGS = DEVICE + ' -std=c99 -Dgcc'
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2 -g'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ CXX = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --cpu Cortex-M3 '
+ CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+ AFLAGS = DEVICE + ' --apcs=interwork '
+ LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+ LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+ CFLAGS += ' -D__MICROLIB '
+ AFLAGS += ' --pd "__MICROLIB SETA 1" '
+ LFLAGS += ' --library_type=microlib '
+ EXEC_PATH += '/ARM/ARMCC/bin/'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+ CFLAGS += ' -std=c99'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+ # toolchains
+ CC = 'iccarm'
+ CXX = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = '-Dewarm'
+
+ CFLAGS = DEVICE
+ CFLAGS += ' --diag_suppress Pa050'
+ CFLAGS += ' --no_cse'
+ CFLAGS += ' --no_unroll'
+ CFLAGS += ' --no_inline'
+ CFLAGS += ' --no_code_motion'
+ CFLAGS += ' --no_tbaa'
+ CFLAGS += ' --no_clustering'
+ CFLAGS += ' --no_scheduling'
+ CFLAGS += ' --endian=little'
+ CFLAGS += ' --cpu=Cortex-M3'
+ CFLAGS += ' -e'
+ CFLAGS += ' --fpu=None'
+ CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+ CFLAGS += ' --silent'
+
+ AFLAGS = DEVICE
+ AFLAGS += ' -s+'
+ AFLAGS += ' -w+'
+ AFLAGS += ' -r'
+ AFLAGS += ' --cpu Cortex-M3'
+ AFLAGS += ' --fpu None'
+ AFLAGS += ' -S'
+
+ if BUILD == 'debug':
+ CFLAGS += ' --debug'
+ CFLAGS += ' -On'
+ else:
+ CFLAGS += ' -Oh'
+
+ LFLAGS = ' --config "board/linker_scripts/link.icf"'
+ LFLAGS += ' --entry __iar_program_start'
+
+ CXXFLAGS = CFLAGS
+
+ EXEC_PATH = EXEC_PATH + '/arm/bin/'
+ POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/stm32/stm32f207-st-nucleo/template.ewp b/bsp/stm32/stm32f207-st-nucleo/template.ewp
new file mode 100644
index 0000000000000000000000000000000000000000..5e7b630ab05d022ce7317f65ba10ccf565a1cc44
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/template.ewp
@@ -0,0 +1,2106 @@
+
+
+ 3
+
+ rtthread
+
+ ARM
+
+ 1
+
+ General
+ 3
+
+ 31
+ 1
+ 1
+
+ ExePath
+ build\iar\Exe
+
+
+ ObjPath
+ build\iar\Obj
+
+
+ ListPath
+ build\iar\List
+
+
+ GEndianMode
+ 0
+
+
+ Input description
+ Automatic choice of formatter, without multibyte support.
+
+
+ Output description
+ Automatic choice of formatter, without multibyte support.
+
+
+ GOutputBinary
+ 0
+
+
+ OGCoreOrChip
+ 1
+
+
+ GRuntimeLibSelect
+ 0
+ 1
+
+
+ GRuntimeLibSelectSlave
+ 0
+ 1
+
+
+ RTDescription
+ Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+
+
+ OGProductVersion
+ 6.30.6.53380
+
+
+ OGLastSavedByProductVersion
+ 8.40.1.21529
+
+
+ GeneralEnableMisra
+ 0
+
+
+ GeneralMisraVerbose
+ 0
+
+
+ OGChipSelectEditMenu
+ STM32F207ZG ST STM32F207ZG
+
+
+ GenLowLevelInterface
+ 1
+
+
+ GEndianModeBE
+ 1
+
+
+ OGBufferedTerminalOutput
+ 0
+
+
+ GenStdoutInterface
+ 0
+
+
+ GeneralMisraRules98
+ 0
+ 1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111
+
+
+ GeneralMisraVer
+ 0
+
+
+ GeneralMisraRules04
+ 0
+ 111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111
+
+
+ RTConfigPath2
+ $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h
+
+
+ GBECoreSlave
+ 27
+ 38
+
+
+ OGUseCmsis
+ 0
+
+
+ OGUseCmsisDspLib
+ 0
+
+
+ GRuntimeLibThreads
+ 0
+
+
+ CoreVariant
+ 27
+ 38
+
+
+ GFPUDeviceSlave
+ STM32F207ZG ST STM32F207ZG
+
+
+ FPU2
+ 0
+ 0
+
+
+ NrRegs
+ 0
+ 0
+
+
+ NEON
+ 0
+
+
+ GFPUCoreSlave2
+ 27
+ 38
+
+
+ OGCMSISPackSelectDevice
+
+
+ OgLibHeap
+ 0
+
+
+ OGLibAdditionalLocale
+ 0
+
+
+ OGPrintfVariant
+ 0
+ 0
+
+
+ OGPrintfMultibyteSupport
+ 0
+
+
+ OGScanfVariant
+ 0
+ 0
+
+
+ OGScanfMultibyteSupport
+ 0
+
+
+ GenLocaleTags
+
+
+
+ GenLocaleDisplayOnly
+
+
+
+ DSPExtension
+ 0
+
+
+ TrustZone
+ 0
+
+
+ TrustZoneModes
+ 0
+ 0
+
+
+
+
+ ICCARM
+ 2
+
+ 35
+ 1
+ 1
+
+ CCOptimizationNoSizeConstraints
+ 0
+
+
+ CCDefines
+
+
+
+ CCPreprocFile
+ 0
+
+
+ CCPreprocComments
+ 0
+
+
+ CCPreprocLine
+ 0
+
+
+ CCListCFile
+ 0
+
+
+ CCListCMnemonics
+ 0
+
+
+ CCListCMessages
+ 0
+
+
+ CCListAssFile
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+ 0
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+
+ CCDiagSuppress
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+
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+
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+ 0
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+
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+ 0
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+
+ CCCompilerRuntimeInfo
+ 0
+
+
+ IFpuProcessor
+ 1
+
+
+ OutputFile
+ $FILE_BNAME$.o
+
+
+ CCLibConfigHeader
+ 1
+
+
+ PreInclude
+
+
+
+ CompilerMisraOverride
+ 0
+
+
+ CCIncludePath2
+
+
+
+ CCStdIncCheck
+ 0
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+
+ CCCodeSection
+ .text
+
+
+ IProcessorMode2
+ 1
+
+
+ CCOptLevel
+ 1
+
+
+ CCOptStrategy
+ 0
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+ CCOptLevelSlave
+ 1
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+
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+
+
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+
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diff --git a/bsp/stm32/stm32f207-st-nucleo/template.eww b/bsp/stm32/stm32f207-st-nucleo/template.eww
new file mode 100644
index 0000000000000000000000000000000000000000..bd036bb4c98c1598f04b85f64b0dff37f6ec6028
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/template.eww
@@ -0,0 +1,10 @@
+
+
+
+
+ $WS_DIR$\template.ewp
+
+
+
+
+
diff --git a/bsp/stm32/stm32f207-st-nucleo/template.uvopt b/bsp/stm32/stm32f207-st-nucleo/template.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..d2d5c5420207edc7311ceaca125cee9eda0f873c
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/template.uvopt
@@ -0,0 +1,177 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj
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+
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diff --git a/bsp/stm32/stm32f207-st-nucleo/template.uvoptx b/bsp/stm32/stm32f207-st-nucleo/template.uvoptx
new file mode 100644
index 0000000000000000000000000000000000000000..d42e3138b2d14620861a2f5411e1894046129194
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/template.uvoptx
@@ -0,0 +1,185 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
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+
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+
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+ 0x4
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diff --git a/bsp/stm32/stm32f207-st-nucleo/template.uvproj b/bsp/stm32/stm32f207-st-nucleo/template.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..7029f88ee52408b432526e7bca8ab8d6d79c1e72
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/template.uvproj
@@ -0,0 +1,438 @@
+
+
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+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rtthread
+ 0x4
+ ARM-ADS
+ 0
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+
+ STM32F103RB
+ STMicroelectronics
+ IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")
+
+ "STARTUP\ST\STM32F10x\startup_stm32f10x_md.s" ("STM32 Medium Density Line Startup Code")
+ UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)
+ 4231
+ stm32f10x.h
+
+
+
+
+
+
+
+
+
+ SFD\ST\STM32F1xx\STM32F103xx.sfr
+ 0
+ 0
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+ ST\STM32F10x\
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+ DARMSTM.DLL
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+ .\board\linker_scripts\link.sct
+
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+
+ <Project Info>
+
+
+
+
+
+ 0
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+
diff --git a/bsp/stm32/stm32f207-st-nucleo/template.uvprojx b/bsp/stm32/stm32f207-st-nucleo/template.uvprojx
new file mode 100644
index 0000000000000000000000000000000000000000..9008edfdf741ba2c42a6b16c4d2b134fc418f0e7
--- /dev/null
+++ b/bsp/stm32/stm32f207-st-nucleo/template.uvprojx
@@ -0,0 +1,410 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rtthread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ STM32F207ZGTx
+ STMicroelectronics
+ Keil.STM32F2xx_DFP.2.7.0
+ http://www.keil.com/pack
+ IRAM(0x20000000,0x20000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207ZGTx$CMSIS\Flash\STM32F2xx_1024.FLM))
+ 0
+ $$Device:STM32F207ZGTx$Drivers\CMSIS\Device\ST\STM32F2xx\Include\stm32f2xx.h
+
+
+
+
+
+
+
+
+
+ $$Device:STM32F207ZGTx$CMSIS\SVD\STM32F20x.svd
+ 0
+ 0
+
+
+
+
+
+
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+ .\build\keil\Obj\
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+
+ SARMCM3.DLL
+ -REMAP -MPU
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
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+ .\board\linker_scripts\link.sct
+
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+
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+ Source Group 1
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