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体验新版 GitCode,发现更多精彩内容 >>
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3d2b66a8
编写于
3月 03, 2020
作者:
B
Bernard Xiong
提交者:
GitHub
3月 03, 2020
浏览文件
操作
浏览文件
下载
差异文件
Merge pull request #3422 from bigmagic123/raspi_fix_driver
Raspi fix driver
上级
dc47abf4
cc95025f
变更
25
隐藏空白更改
内联
并排
Showing
25 changed file
with
871 addition
and
2166 deletion
+871
-2166
bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c
bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c
+22
-0
bsp/raspberry-pi/raspi3-64/.config
bsp/raspberry-pi/raspi3-64/.config
+8
-5
bsp/raspberry-pi/raspi3-64/applications/main.c
bsp/raspberry-pi/raspi3-64/applications/main.c
+44
-2
bsp/raspberry-pi/raspi3-64/driver/Kconfig
bsp/raspberry-pi/raspi3-64/driver/Kconfig
+0
-1
bsp/raspberry-pi/raspi3-64/driver/SConscript
bsp/raspberry-pi/raspi3-64/driver/SConscript
+1
-1
bsp/raspberry-pi/raspi3-64/driver/bcm283x.c
bsp/raspberry-pi/raspi3-64/driver/bcm283x.c
+0
-575
bsp/raspberry-pi/raspi3-64/driver/bcm283x.h
bsp/raspberry-pi/raspi3-64/driver/bcm283x.h
+0
-651
bsp/raspberry-pi/raspi3-64/driver/board.c
bsp/raspberry-pi/raspi3-64/driver/board.c
+2
-0
bsp/raspberry-pi/raspi3-64/driver/board.h
bsp/raspberry-pi/raspi3-64/driver/board.h
+0
-4
bsp/raspberry-pi/raspi3-64/driver/drv_fb.c
bsp/raspberry-pi/raspi3-64/driver/drv_fb.c
+91
-428
bsp/raspberry-pi/raspi3-64/driver/drv_fb.h
bsp/raspberry-pi/raspi3-64/driver/drv_fb.h
+6
-40
bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
+160
-314
bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
+7
-6
bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
+51
-33
bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
+12
-14
bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c
bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c
+31
-31
bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h
bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h
+1
-4
bsp/raspberry-pi/raspi3-64/driver/mbox.c
bsp/raspberry-pi/raspi3-64/driver/mbox.c
+0
-4
bsp/raspberry-pi/raspi3-64/driver/raspi.h
bsp/raspberry-pi/raspi3-64/driver/raspi.h
+418
-49
bsp/raspberry-pi/raspi3-64/link.lds
bsp/raspberry-pi/raspi3-64/link.lds
+3
-1
bsp/raspberry-pi/raspi3-64/rtconfig.h
bsp/raspberry-pi/raspi3-64/rtconfig.h
+8
-0
libcpu/aarch64/cortex-a53/cp15.h
libcpu/aarch64/cortex-a53/cp15.h
+0
-1
libcpu/aarch64/cortex-a53/interrupt.c
libcpu/aarch64/cortex-a53/interrupt.c
+2
-2
libcpu/aarch64/cortex-a53/interrupt.h
libcpu/aarch64/cortex-a53/interrupt.h
+2
-0
libcpu/aarch64/cortex-a53/mmu.h
libcpu/aarch64/cortex-a53/mmu.h
+2
-0
未找到文件。
bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c
浏览文件 @
3d2b66a8
...
...
@@ -114,4 +114,26 @@ int rt_hw_wdt_init(void)
}
INIT_DEVICE_EXPORT
(
rt_hw_wdt_init
);
/**
* Reboot
*/
int
reboot
(
void
)
{
unsigned
int
r
;
rt_kprintf
(
"reboot system...
\n
"
);
rt_thread_mdelay
(
100
);
// trigger a restart by instructing the GPU to boot from partition 0
r
=
PM_RSTS
;
r
&=
~
0xfffffaaa
;
PM_RSTS
=
PM_PASSWORD
|
r
;
// boot from partition 0
PM_WDOG
=
PM_PASSWORD
|
10
;
PM_RSTC
=
PM_PASSWORD
|
PM_RSTC_WRCFG_FULL_RESET
;
while
(
1
);
return
0
;
}
MSH_CMD_EXPORT
(
reboot
,
reboot
system
...);
#endif
/*BSP_USING_WDT */
bsp/raspberry-pi/raspi3-64/.config
浏览文件 @
3d2b66a8
...
...
@@ -146,7 +146,7 @@ CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ
=
64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
CONFIG_RT_USING_HWTIMER
=
y
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN
=
y
...
...
@@ -164,7 +164,7 @@ CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION
=
16
CONFIG_RT_SDIO_DEBUG
=
y
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
CONFIG_RT_USING_WDT
=
y
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
...
...
@@ -465,10 +465,12 @@ CONFIG_BSP_USING_UART=y
CONFIG_RT_USING_UART1
=
y
CONFIG_BSP_USING_PIN
=
y
CONFIG_BSP_USING_CORETIMER
=
y
# CONFIG_BSP_USING_SYSTIMER is not set
CONFIG_BSP_USING_SYSTIMER
=
y
CONFIG_RT_USING_SYSTIMER1
=
y
CONFIG_RT_USING_SYSTIMER3
=
y
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_WDT is not set
CONFIG_BSP_USING_WDT
=
y
# CONFIG_BSP_USING_RTC is not set
CONFIG_BSP_USING_SDIO
=
y
CONFIG_BSP_USING_SDIO0
=
y
...
...
@@ -476,4 +478,5 @@ CONFIG_BSP_USING_SDIO0=y
#
# Board Peripheral Drivers
#
# CONFIG_BSP_USING_HDMI is not set
CONFIG_BSP_USING_HDMI
=
y
CONFIG_BSP_USING_HDMI_DISPLAY
=
y
bsp/raspberry-pi/raspi3-64/applications/main.c
浏览文件 @
3d2b66a8
...
...
@@ -9,11 +9,53 @@
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#include "mbox.h"
void
set_led
(
int
state
)
//set state LED nyala atau mati
{
if
(
state
==
1
)
//LED nyala
{
mbox
[
0
]
=
8
*
4
;
// length of the message
mbox
[
1
]
=
MBOX_REQUEST
;
// this is a request message
mbox
[
2
]
=
0x00038041
;
// get serial number command
mbox
[
3
]
=
8
;
// buffer size
mbox
[
4
]
=
0
;
mbox
[
5
]
=
130
;
// clear output buffer
mbox
[
6
]
=
1
;
mbox
[
7
]
=
MBOX_TAG_LAST
;
mbox_call
(
8
,
MMU_DISABLE
);
}
else
if
(
state
==
0
)
//LED mati
{
mbox
[
0
]
=
8
*
4
;
// length of the message
mbox
[
1
]
=
MBOX_REQUEST
;
// this is a request message
mbox
[
2
]
=
0x00038041
;
// get serial number command
mbox
[
3
]
=
8
;
// buffer size
mbox
[
4
]
=
0
;
mbox
[
5
]
=
130
;
// clear output buffer
mbox
[
6
]
=
0
;
mbox
[
7
]
=
MBOX_TAG_LAST
;
mbox_call
(
8
,
MMU_DISABLE
);
}
}
int
main
(
int
argc
,
char
**
argv
)
{
int
count
=
1
;
rt_kprintf
(
"Hi, this is RT-Thread!!
\n
"
);
return
0
;
}
while
(
count
++
)
{
set_led
(
1
);
rt_thread_mdelay
(
500
);
set_led
(
0
);
rt_thread_mdelay
(
500
);
}
return
RT_EOK
;
}
bsp/raspberry-pi/raspi3-64/driver/Kconfig
浏览文件 @
3d2b66a8
...
...
@@ -105,7 +105,6 @@ menu "Hardware Drivers Config"
menu "Board Peripheral Drivers"
menuconfig BSP_USING_HDMI
bool "Enable HDMI"
select BSP_USING_SPI
default n
if BSP_USING_HDMI
...
...
bsp/raspberry-pi/raspi3-64/driver/SConscript
浏览文件 @
3d2b66a8
...
...
@@ -5,8 +5,8 @@ from building import *
cwd
=
GetCurrentDir
()
src
=
Split
(
'''
board.c
bcm283x.c
drv_uart.c
mbox.c
'''
)
CPPPATH
=
[
cwd
]
...
...
bsp/raspberry-pi/raspi3-64/driver/bcm283x.c
已删除
100644 → 0
浏览文件 @
dc47abf4
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#include "bcm283x.h"
rt_uint32_t
bcm283x_peri_read
(
volatile
rt_ubase_t
addr
)
{
rt_uint32_t
ret
;
__sync_synchronize
();
ret
=
HWREG32
(
addr
);
__sync_synchronize
();
return
ret
;
}
rt_uint32_t
bcm283x_peri_read_nb
(
volatile
rt_ubase_t
addr
)
{
return
HWREG32
(
addr
);
}
void
bcm283x_peri_write
(
volatile
rt_ubase_t
addr
,
rt_uint32_t
value
)
{
__sync_synchronize
();
HWREG32
(
addr
)
=
value
;
__sync_synchronize
();
}
void
bcm283x_peri_write_nb
(
volatile
rt_ubase_t
addr
,
rt_uint32_t
value
)
{
HWREG32
(
addr
)
=
value
;
}
void
bcm283x_peri_set_bits
(
volatile
rt_ubase_t
addr
,
rt_uint32_t
value
,
rt_uint32_t
mask
)
{
rt_uint32_t
v
=
bcm283x_peri_read
(
addr
);
v
=
(
v
&
~
mask
)
|
(
value
&
mask
);
bcm283x_peri_write
(
addr
,
v
);
}
void
bcm283x_gpio_fsel
(
rt_uint8_t
pin
,
rt_uint8_t
mode
)
{
volatile
rt_ubase_t
addr
=
(
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPFSEL0
+
(
pin
/
10
)
*
4
);
rt_uint8_t
shift
=
(
pin
%
10
)
*
3
;
rt_uint32_t
mask
=
BCM283X_GPIO_FSEL_MASK
<<
shift
;
rt_uint32_t
value
=
mode
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
value
,
mask
);
}
void
bcm283x_gpio_set
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPSET0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
bcm283x_peri_write
(
addr
,
1
<<
shift
);
}
void
bcm283x_gpio_clr
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPCLR0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
bcm283x_peri_write
(
addr
,
1
<<
shift
);
}
rt_uint8_t
bcm283x_gpio_lev
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM2835_GPIO_GPLEV0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
bcm283x_peri_read
(
addr
);
return
(
value
&
(
1
<<
shift
))
?
HIGH
:
LOW
;
}
rt_uint8_t
bcm283x_gpio_eds
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPEDS0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
bcm283x_peri_read
(
addr
);
return
(
value
&
(
1
<<
shift
))
?
HIGH
:
LOW
;
}
/* Write a 1 to clear the bit in EDS */
void
bcm283x_gpio_set_eds
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPEDS0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_write
(
addr
,
value
);
}
/* Rising edge detect enable */
void
bcm283x_gpio_ren
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPREN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
value
,
value
);
}
void
bcm283x_gpio_clr_ren
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPREN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
0
,
value
);
}
/* Falling edge detect enable */
void
bcm283x_gpio_fen
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPFEN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
value
,
value
);
}
void
bcm283x_gpio_clr_fen
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPFEN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
0
,
value
);
}
/* High detect enable */
void
bcm283x_gpio_hen
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPHEN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
value
,
value
);
}
void
bcm283x_gpio_clr_hen
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPHEN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
0
,
value
);
}
/* Low detect enable */
void
bcm283x_gpio_len
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPLEN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
value
,
value
);
}
void
bcm283x_gpio_clr_len
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPLEN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
0
,
value
);
}
/* Async rising edge detect enable */
void
bcm283x_gpio_aren
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPAREN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
value
,
value
);
}
void
bcm283x_gpio_clr_aren
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPAREN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
0
,
value
);
}
/* Async falling edge detect enable */
void
bcm283x_gpio_afen
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPAFEN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
value
,
value
);
}
void
bcm283x_gpio_clr_afen
(
rt_uint8_t
pin
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPAFEN0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
value
=
1
<<
shift
;
bcm283x_peri_set_bits
(
addr
,
0
,
value
);
}
/* Set pullup/down */
void
bcm283x_gpio_pud
(
rt_uint8_t
pud
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPPUD
;
bcm283x_peri_write
(
addr
,
pud
);
}
/* Pullup/down clock
// Clocks the value of pud into the GPIO pin
*/
void
bcm283x_gpio_pudclk
(
rt_uint8_t
pin
,
rt_uint8_t
on
)
{
volatile
rt_ubase_t
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPPUDCLK0
+
(
pin
/
32
)
*
4
;
rt_uint8_t
shift
=
pin
%
32
;
bcm283x_peri_write
(
addr
,
(
on
?
1
:
0
)
<<
shift
);
}
void
bcm283x_gpio_set_pud
(
rt_uint8_t
pin
,
rt_uint8_t
pud
)
{
bcm283x_gpio_pud
(
pud
);
bcm283x_clo_delayMicros
(
10
);
bcm283x_gpio_pudclk
(
pin
,
1
);
bcm283x_clo_delayMicros
(
10
);
bcm283x_gpio_pud
(
BCM283X_GPIO_PUD_OFF
);
bcm283x_gpio_pudclk
(
pin
,
0
);
}
void
bcm283x_gpio_write
(
rt_uint8_t
pin
,
rt_uint8_t
val
)
{
if
(
val
)
bcm283x_gpio_set
(
pin
);
else
bcm283x_gpio_clr
(
pin
);
}
rt_uint64_t
bcm283x_st_read
(
void
)
{
volatile
rt_ubase_t
addr
;
rt_uint32_t
hi
,
lo
;
rt_uint64_t
st
;
addr
=
BCM283X_ST_BASE
+
BCM283X_ST_CHI
;
hi
=
bcm283x_peri_read
(
addr
);
addr
=
BCM283X_ST_BASE
+
BCM283X_ST_CLO
;
lo
=
bcm283x_peri_read
(
addr
);
addr
=
BCM283X_ST_BASE
+
BCM283X_ST_CHI
;
st
=
bcm283x_peri_read
(
addr
);
/* Test for overflow */
if
(
st
==
hi
)
{
rt_kprintf
(
">> 1crash???
\n
"
);
st
<<=
32
;
st
+=
lo
;
rt_kprintf
(
">> 2crash!!!
\n
"
);
}
else
{
st
<<=
32
;
addr
=
BCM283X_ST_BASE
+
BCM283X_ST_CLO
;
st
+=
bcm283x_peri_read
(
addr
);
}
return
st
;
}
/* microseconds */
void
bcm283x_delayMicroseconds
(
rt_uint64_t
micros
)
{
rt_uint64_t
start
;
start
=
bcm283x_st_read
();
rt_kprintf
(
"bcm283x_st_read result: %d
\n
"
,
start
);
/* Not allowed to access timer registers (result is not as precise)*/
if
(
start
==
0
)
return
;
bcm283x_st_delay
(
start
,
micros
);
}
void
bcm283x_clo_delayMicros
(
rt_uint32_t
micros
)
{
volatile
rt_uint32_t
addr
;
rt_uint32_t
compare
;
addr
=
BCM283X_ST_BASE
+
BCM283X_ST_CLO
;
compare
=
bcm283x_peri_read
(
addr
)
+
micros
;
while
(
bcm283x_peri_read
(
addr
)
<
compare
);
}
void
bcm283x_st_delay
(
rt_uint64_t
offset_micros
,
rt_uint64_t
micros
)
{
rt_uint64_t
compare
=
offset_micros
+
micros
;
while
(
bcm283x_st_read
()
<
compare
);
}
/* Read an number of bytes from I2C */
rt_uint8_t
bcm283x_i2c_read
(
rt_uint32_t
base
,
rt_uint8_t
*
buf
,
rt_uint32_t
len
)
{
volatile
rt_uint32_t
dlen
=
base
+
BCM283X_BSC_DLEN
;
volatile
rt_uint32_t
fifo
=
base
+
BCM283X_BSC_FIFO
;
volatile
rt_uint32_t
status
=
base
+
BCM283X_BSC_S
;
volatile
rt_uint32_t
control
=
base
+
BCM283X_BSC_C
;
rt_uint32_t
remaining
=
len
;
rt_uint32_t
i
=
0
;
rt_uint8_t
reason
=
BCM283X_I2C_REASON_OK
;
/* Clear FIFO */
bcm283x_peri_set_bits
(
control
,
BCM283X_BSC_C_CLEAR_1
,
BCM283X_BSC_C_CLEAR_1
);
/* Clear Status */
bcm283x_peri_write_nb
(
status
,
BCM283X_BSC_S_CLKT
|
BCM283X_BSC_S_ERR
|
BCM283X_BSC_S_DONE
);
/* Set Data Length */
bcm283x_peri_write_nb
(
dlen
,
len
);
/* Start read */
bcm283x_peri_write_nb
(
control
,
BCM283X_BSC_C_I2CEN
|
BCM283X_BSC_C_ST
|
BCM283X_BSC_C_READ
);
/* wait for transfer to complete */
while
(
!
(
bcm283x_peri_read_nb
(
status
)
&
BCM283X_BSC_S_DONE
))
{
/* we must empty the FIFO as it is populated and not use any delay */
while
(
remaining
&&
bcm283x_peri_read_nb
(
status
)
&
BCM283X_BSC_S_RXD
)
{
/* Read from FIFO, no barrier */
buf
[
i
]
=
bcm283x_peri_read_nb
(
fifo
);
i
++
;
remaining
--
;
}
}
/* transfer has finished - grab any remaining stuff in FIFO */
while
(
remaining
&&
(
bcm283x_peri_read_nb
(
status
)
&
BCM283X_BSC_S_RXD
))
{
/* Read from FIFO, no barrier */
buf
[
i
]
=
bcm283x_peri_read_nb
(
fifo
);
i
++
;
remaining
--
;
}
/* Received a NACK */
if
(
bcm283x_peri_read
(
status
)
&
BCM283X_BSC_S_ERR
)
{
reason
=
BCM283X_I2C_REASON_ERROR_NACK
;
}
/* Received Clock Stretch Timeout */
else
if
(
bcm283x_peri_read
(
status
)
&
BCM283X_BSC_S_CLKT
)
{
reason
=
BCM283X_I2C_REASON_ERROR_CLKT
;
}
/* Not all data is received */
else
if
(
remaining
)
{
reason
=
BCM283X_I2C_REASON_ERROR_DATA
;
}
bcm283x_peri_set_bits
(
control
,
BCM283X_BSC_S_DONE
,
BCM283X_BSC_S_DONE
);
return
reason
;
}
int
bcm283x_i2c_begin
(
int
no
)
{
if
(
0
==
no
)
{
bcm283x_gpio_fsel
(
BCM_GPIO_PIN_0
,
BCM283X_GPIO_FSEL_ALT0
);
/* SDA */
bcm283x_gpio_fsel
(
BCM_GPIO_PIN_1
,
BCM283X_GPIO_FSEL_ALT0
);
/* SCL */
}
else
{
bcm283x_gpio_fsel
(
BCM_GPIO_PIN_2
,
BCM283X_GPIO_FSEL_ALT0
);
/* SDA */
bcm283x_gpio_fsel
(
BCM_GPIO_PIN_3
,
BCM283X_GPIO_FSEL_ALT0
);
/* SCL */
}
return
0
;
}
void
bcm283x_i2c_end
(
int
no
)
{
if
(
0
==
no
)
{
bcm283x_gpio_fsel
(
BCM_GPIO_PIN_0
,
BCM283X_GPIO_FSEL_INPT
);
/* SDA */
bcm283x_gpio_fsel
(
BCM_GPIO_PIN_1
,
BCM283X_GPIO_FSEL_INPT
);
/* SCL */
}
else
{
bcm283x_gpio_fsel
(
BCM_GPIO_PIN_2
,
BCM283X_GPIO_FSEL_INPT
);
/* SDA */
bcm283x_gpio_fsel
(
BCM_GPIO_PIN_3
,
BCM283X_GPIO_FSEL_INPT
);
/* SCL */
}
}
void
bcm283x_i2c_setSlaveAddress
(
int
no
,
rt_uint8_t
saddr
)
{
volatile
rt_uint32_t
addr
;
if
(
0
==
no
)
addr
=
PER_BASE
+
BCM283X_BSC0_BASE
+
BCM283X_BSC_A
;
else
addr
=
PER_BASE
+
BCM283X_BSC1_BASE
+
BCM283X_BSC_A
;
bcm283x_peri_write
(
addr
,
saddr
);
}
void
bcm283x_i2c_setClockDivider
(
int
no
,
rt_uint16_t
divider
)
{
volatile
rt_uint32_t
addr
;
if
(
0
==
no
)
addr
=
PER_BASE
+
BCM283X_BSC0_BASE
+
BCM283X_BSC_DIV
;
else
addr
=
PER_BASE
+
BCM283X_BSC0_BASE
+
BCM283X_BSC_DIV
;
bcm283x_peri_write
(
addr
,
divider
);
}
void
bcm283x_i2c_set_baudrate
(
int
no
,
rt_uint32_t
baudrate
)
{
rt_uint32_t
divider
;
divider
=
(
BCM283X_CORE_CLK_HZ
/
baudrate
)
&
0xFFFE
;
bcm283x_i2c_setClockDivider
(
no
,
(
rt_uint16_t
)
divider
);
}
/* Writes an number of bytes to I2C */
rt_uint8_t
bcm283x_i2c_write
(
rt_uint32_t
base
,
const
rt_uint8_t
*
buf
,
rt_uint32_t
len
)
{
volatile
rt_uint32_t
dlen
=
base
+
BCM283X_BSC_DLEN
;
volatile
rt_uint32_t
fifo
=
base
+
BCM283X_BSC_FIFO
;
volatile
rt_uint32_t
status
=
base
+
BCM283X_BSC_S
;
volatile
rt_uint32_t
control
=
base
+
BCM283X_BSC_C
;
rt_uint32_t
remaining
=
len
;
rt_uint32_t
i
=
0
;
rt_uint8_t
reason
=
BCM283X_I2C_REASON_OK
;
/* Clear FIFO */
bcm283x_peri_set_bits
(
control
,
BCM283X_BSC_C_CLEAR_1
,
BCM283X_BSC_C_CLEAR_1
);
/* Clear Status */
bcm283x_peri_write
(
status
,
BCM283X_BSC_S_CLKT
|
BCM283X_BSC_S_ERR
|
BCM283X_BSC_S_DONE
);
/* Set Data Length */
bcm283x_peri_write
(
dlen
,
len
);
/* pre populate FIFO with max buffer */
while
(
remaining
&&
(
i
<
BCM283X_BSC_FIFO_SIZE
))
{
bcm283x_peri_write_nb
(
fifo
,
buf
[
i
]);
i
++
;
remaining
--
;
}
/* Enable device and start transfer */
bcm283x_peri_write
(
control
,
BCM283X_BSC_C_I2CEN
|
BCM283X_BSC_C_ST
);
/* Transfer is over when BCM2835_BSC_S_DONE */
while
(
!
(
bcm283x_peri_read
(
status
)
&
BCM283X_BSC_S_DONE
))
{
while
(
remaining
&&
(
bcm283x_peri_read
(
status
)
&
BCM283X_BSC_S_TXD
))
{
/* Write to FIFO */
bcm283x_peri_write
(
fifo
,
buf
[
i
]);
i
++
;
remaining
--
;
}
}
/* Received a NACK */
if
(
bcm283x_peri_read
(
status
)
&
BCM283X_BSC_S_ERR
)
{
reason
=
BCM283X_I2C_REASON_ERROR_NACK
;
}
/* Received Clock Stretch Timeout */
else
if
(
bcm283x_peri_read
(
status
)
&
BCM283X_BSC_S_CLKT
)
{
reason
=
BCM283X_I2C_REASON_ERROR_CLKT
;
}
/* Not all data is sent */
else
if
(
remaining
)
{
reason
=
BCM283X_I2C_REASON_ERROR_DATA
;
}
bcm283x_peri_set_bits
(
control
,
BCM283X_BSC_S_DONE
,
BCM283X_BSC_S_DONE
);
return
reason
;
}
rt_uint8_t
bcm283x_i2c_write_read_rs
(
char
*
cmds
,
rt_uint32_t
cmds_len
,
char
*
buf
,
rt_uint32_t
buf_len
)
{
volatile
rt_uint32_t
dlen
=
PER_BASE
+
BCM283X_BSC0_BASE
+
BCM283X_BSC_DLEN
;
volatile
rt_uint32_t
fifo
=
PER_BASE
+
BCM283X_BSC0_BASE
+
BCM283X_BSC_FIFO
;
volatile
rt_uint32_t
status
=
PER_BASE
+
BCM283X_BSC0_BASE
+
BCM283X_BSC_S
;
volatile
rt_uint32_t
control
=
PER_BASE
+
BCM283X_BSC0_BASE
+
BCM283X_BSC_C
;
rt_uint32_t
remaining
=
cmds_len
;
rt_uint32_t
i
=
0
;
rt_uint8_t
reason
=
BCM283X_I2C_REASON_OK
;
/* Clear FIFO */
bcm283x_peri_set_bits
(
control
,
BCM283X_BSC_C_CLEAR_1
,
BCM283X_BSC_C_CLEAR_1
);
/* Clear Status */
bcm283x_peri_write
(
status
,
BCM283X_BSC_S_CLKT
|
BCM283X_BSC_S_ERR
|
BCM283X_BSC_S_DONE
);
/* Set Data Length */
bcm283x_peri_write
(
dlen
,
cmds_len
);
/* pre populate FIFO with max buffer */
while
(
remaining
&&
(
i
<
BCM283X_BSC_FIFO_SIZE
))
{
bcm283x_peri_write_nb
(
fifo
,
cmds
[
i
]);
i
++
;
remaining
--
;
}
/* Enable device and start transfer */
bcm283x_peri_write
(
control
,
BCM283X_BSC_C_I2CEN
|
BCM283X_BSC_C_ST
);
/* poll for transfer has started (way to do repeated start, from BCM2835 datasheet) */
while
(
!
(
bcm283x_peri_read
(
status
)
&
BCM283X_BSC_S_TA
))
{
/* Linux may cause us to miss entire transfer stage */
if
(
bcm283x_peri_read_nb
(
status
)
&
BCM283X_BSC_S_DONE
)
break
;
}
remaining
=
buf_len
;
i
=
0
;
/* Send a repeated start with read bit set in address */
bcm283x_peri_write
(
dlen
,
buf_len
);
bcm283x_peri_write
(
control
,
BCM283X_BSC_C_I2CEN
|
BCM283X_BSC_C_ST
|
BCM283X_BSC_C_READ
);
/* Wait for write to complete and first byte back. */
bcm283x_clo_delayMicros
(
100
);
/* wait for transfer to complete */
while
(
!
(
bcm283x_peri_read_nb
(
status
)
&
BCM283X_BSC_S_DONE
))
{
/* we must empty the FIFO as it is populated and not use any delay */
while
(
remaining
&&
bcm283x_peri_read
(
status
)
&
BCM283X_BSC_S_RXD
)
{
/* Read from FIFO, no barrier */
buf
[
i
]
=
bcm283x_peri_read_nb
(
fifo
);
i
++
;
remaining
--
;
}
}
/* transfer has finished - grab any remaining stuff in FIFO */
while
(
remaining
&&
(
bcm283x_peri_read
(
status
)
&
BCM283X_BSC_S_RXD
))
{
/* Read from FIFO */
buf
[
i
]
=
bcm283x_peri_read
(
fifo
);
i
++
;
remaining
--
;
}
/* Received a NACK */
if
(
bcm283x_peri_read
(
status
)
&
BCM283X_BSC_S_ERR
)
{
reason
=
BCM283X_I2C_REASON_ERROR_NACK
;
}
/* Received Clock Stretch Timeout */
else
if
(
bcm283x_peri_read
(
status
)
&
BCM283X_BSC_S_CLKT
)
{
reason
=
BCM283X_I2C_REASON_ERROR_CLKT
;
}
/* Not all data is sent */
else
if
(
remaining
)
{
reason
=
BCM283X_I2C_REASON_ERROR_DATA
;
}
bcm283x_peri_set_bits
(
control
,
BCM283X_BSC_S_DONE
,
BCM283X_BSC_S_DONE
);
return
reason
;
}
bsp/raspberry-pi/raspi3-64/driver/bcm283x.h
已删除
100644 → 0
浏览文件 @
dc47abf4
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-15 RT-Thread the first version
* 2019-07-29 zdzn add macro definition
*/
#ifndef __BCM283X_H__
#define __BCM283X_H__
#include <rthw.h>
#include <rtthread.h>
#define PER_BASE (0x3F000000)
#define PER_BASE_40000000 (0x40000000)
#define HIGH 0x1
#define LOW 0x0
#define BCM283X_CORE_CLK_HZ 250000000
/* 50 MHz */
/*! Offsets for the bases of various peripherals within the peripherals block
* Base Address of the System Timer registers
*/
/*! Base Address of the Pads registers */
#define BCM283X_GPIO_PADS 0x100000
/*! Base Address of the Clock/timer registers */
#define BCM283X_CLOCK_BASE 0x101000
/*! Base Address of the GPIO registers */
//#define BCM283X_GPIO_BASE 0x200000
/*! Base Address of the SPI0 registers */
#define BCM283X_SPI0_BASE 0x204000
/*! Base Address of the PWM registers */
#define BCM283X_GPIO_PWM 0x20C000
/*! Base Address of the AUX registers */
#define BCM283X_AUX_BASE 0x215000
/*! Base Address of the AUX_SPI1 registers */
#define BCM283X_SPI1_BASE 0x215080
/*! Base Address of the AUX_SPI2 registers */
#define BCM283X_SPI2_BASE 0x2150C0
/*! Base Address of the BSC0 registers */
#define BCM283X_BSC0_BASE 0x205000 //for i2c0
/*! Base Address of the BSC1 registers */
#define BCM283X_BSC1_BASE 0x804000 //for i2c1
/*! Base Address of the BSC1 registers */
#define BCM283X_BSC2_BASE 0x805000 //for hdmi i2c not use
/*
* GPIO
*/
#define GPIO_BASE (PER_BASE + 0x200000)
#define GPIO_GPFSEL0 HWREG32(GPIO_BASE + 0x0000)
/* GPIO Function Select 0 32bit R/W */
#define GPIO_GPFSEL1 HWREG32(GPIO_BASE + 0x0004)
/* GPIO Function Select 1 32bit R/W */
#define GPIO_GPFSEL2 HWREG32(GPIO_BASE + 0x0008)
/* GPIO Function Select 2 32bit R/W */
#define GPIO_GPFSEL4 HWREG32(GPIO_BASE + 0x0010)
/* GPIO Function Select 4 32bit R/W */
#define GPIO_GPFSEL5 HWREG32(GPIO_BASE + 0x0014)
/* GPIO Function Select 5 32bit R/W */
#define GPIO_GPSET0 HWREG32(GPIO_BASE + 0x001C)
#define GPIO_GPSET1 HWREG32(GPIO_BASE + 0x0020)
#define GPIO_GPCLR0 HWREG32(GPIO_BASE + 0x0028)
#define GPIO_GPCLR1 HWREG32(GPIO_BASE + 0x002C)
#define GPIO_GPEDS0 HWREG32(GPIO_BASE + 0x0040)
/* GPIO Pin Event Detect Status */
#define GPIO_GPEDS1 HWREG32(GPIO_BASE + 0x0044)
#define GPIO_GPREN0 HWREG32(GPIO_BASE + 0x004c)
/* GPIO Pin Rising Edge Detect Enable */
#define GPIO_GPREN1 HWREG32(GPIO_BASE + 0x0050)
#define GPIO_GPFEN0 HWREG32(GPIO_BASE + 0x0058)
/* GPIO Pin Falling Edge Detect Enable */
#define GPIO_GPFEN1 HWREG32(GPIO_BASE + 0x005C)
#define GPIO_GPHEN0 HWREG32(GPIO_BASE + 0x0064)
/* GPIO Pin High Detect Enable */
#define GPIO_GPHEN1 HWREG32(GPIO_BASE + 0x0068)
#define GPIO_GPLEN0 HWREG32(GPIO_BASE + 0x0070)
/* GPIO Pin Low Detect Enable 0 */
#define GPIO_GPLEN1 HWREG32(GPIO_BASE + 0x0074)
#define GPIO_GPAREN0 HWREG32(GPIO_BASE + 0x007C)
/* GPIO Pin Async. Rising Edge Detect */
#define GPIO_GPAREN1 HWREG32(GPIO_BASE + 0x0080)
#define GPIO_GPAFEN0 HWREG32(GPIO_BASE + 0x0088)
/* GPIO Pin Async. Falling Edge Detect */
#define GPIO_GPAFEN1 HWREG32(GPIO_BASE + 0x008C)
#define GPIO_GPPUD HWREG32(GPIO_BASE + 0x0094)
/* GPIO Pin Pull-up/down Enable */
#define GPIO_GPPUDCLK0 HWREG32(GPIO_BASE + 0x0098)
/* GPIO Pin Pull-up/down Enable Clock 0 */
#define GPIO_GPPUDCLK1 HWREG32(GPIO_BASE + 0x009C)
/* GPIO Pin Pull-up/down Enable Clock 1 */
#define BCM283X_GPIO_BASE (PER_BASE + 0x200000)
#define BCM283X_GPIO_GPFSEL0 (0x0000)
/* GPIO Function Select 0 32bit R/W */
#define BCM283X_GPIO_GPFSEL1 (0x0004)
/* GPIO Function Select 1 32bit R/W */
#define BCM283X_GPIO_GPFSEL2 (0x0008)
/* GPIO Function Select 2 32bit R/W */
#define BCM283X_GPIO_GPFSEL4 (0x0010)
/* GPIO Function Select 4 32bit R/W */
#define BCM283X_GPIO_GPFSEL5 (0x0014)
/* GPIO Function Select 5 32bit R/W */
#define BCM283X_GPIO_GPSET0 (0x001C)
#define BCM283X_GPIO_GPSET1 (0x0020)
#define BCM283X_GPIO_GPCLR0 (0x0028)
#define BCM283X_GPIO_GPCLR1 (0x002C)
#define BCM2835_GPIO_GPLEV0 (0x0034)
/*!< GPIO Pin Level 0 */
#define BCM2835_GPIO_GPLEV1 (0x0038)
/*!< GPIO Pin Level 1 */
#define BCM283X_GPIO_GPEDS0 (0x0040)
/* GPIO Pin Event Detect Status */
#define BCM283X_GPIO_GPEDS1 (0x0044)
#define BCM283X_GPIO_GPREN0 (0x004c)
/* GPIO Pin Rising Edge Detect Enable */
#define BCM283X_GPIO_GPREN1 (0x0050)
#define BCM283X_GPIO_GPFEN0 (0x0058)
/* GPIO Pin Falling Edge Detect Enable */
#define BCM283X_GPIO_GPFEN1 (0x005C)
#define BCM283X_GPIO_GPHEN0 (0x0064)
/* GPIO Pin High Detect Enable */
#define BCM283X_GPIO_GPHEN1 (0x0068)
#define BCM283X_GPIO_GPLEN0 (0x0070)
/* GPIO Pin Low Detect Enable 0 */
#define BCM283X_GPIO_GPLEN1 (0x0074)
#define BCM283X_GPIO_GPAREN0 (0x007C)
/* GPIO Pin Async. Rising Edge Detect */
#define BCM283X_GPIO_GPAREN1 (0x0080)
#define BCM283X_GPIO_GPAFEN0 (0x0088)
/* GPIO Pin Async. Falling Edge Detect */
#define BCM283X_GPIO_GPAFEN1 (0x008C)
#define BCM283X_GPIO_GPPUD (0x0094)
/* GPIO Pin Pull-up/down Enable */
#define BCM283X_GPIO_GPPUDCLK0 (0x0098)
/* GPIO Pin Pull-up/down Enable Clock 0 */
#define BCM283X_GPIO_GPPUDCLK1 (0x009C)
/* GPIO Pin Pull-up/down Enable Clock 1 */
enum
gpio_function_select
{
BCM283X_GPIO_FSEL_INPT
=
0x00
,
/*!< Input 0b000 */
BCM283X_GPIO_FSEL_OUTP
=
0x01
,
/*!< Output 0b001 */
BCM283X_GPIO_FSEL_ALT0
=
0x04
,
/*!< Alternate function 0 0b100 */
BCM283X_GPIO_FSEL_ALT1
=
0x05
,
/*!< Alternate function 1 0b101 */
BCM283X_GPIO_FSEL_ALT2
=
0x06
,
/*!< Alternate function 2 0b110, */
BCM283X_GPIO_FSEL_ALT3
=
0x07
,
/*!< Alternate function 3 0b111 */
BCM283X_GPIO_FSEL_ALT4
=
0x03
,
/*!< Alternate function 4 0b011 */
BCM283X_GPIO_FSEL_ALT5
=
0x02
,
/*!< Alternate function 5 0b010 */
BCM283X_GPIO_FSEL_MASK
=
0x07
/*!< Function select bits mask 0b111 */
};
enum
gpio_pud_mode
{
BCM283X_GPIO_PUD_OFF
=
0x00
,
/*!< Off ? disable pull-up/down 0b00 */
BCM283X_GPIO_PUD_DOWN
=
0x01
,
/*!< Enable Pull Down control 0b01 */
BCM283X_GPIO_PUD_UP
=
0x02
/*!< Enable Pull Up control 0b10 */
};
/* Defines for BSC I2C
* GPIO register offsets from BCM283X_BSC*_BASE.
* Offsets into the BSC Peripheral block in bytes per 3.1 BSC Register Map
*/
/* I2C Address Map offset address */
#define BCM283X_BSC_C 0x0000
/*!< BSC Master Control */
#define BCM283X_BSC_S 0x0004
/*!< BSC Master Status */
#define BCM283X_BSC_DLEN 0x0008
/*!< BSC Master Data Length */
#define BCM283X_BSC_A 0x000c
/*!< BSC Master Slave Address */
#define BCM283X_BSC_FIFO 0x0010
/*!< BSC Master Data FIFO */
#define BCM283X_BSC_DIV 0x0014
/*!< BSC Master Clock Divider */
#define BCM283X_BSC_DEL 0x0018
/*!< BSC Master Data Delay */
#define BCM283X_BSC_CLKT 0x001c
/*!< BSC Master Clock Stretch Timeout */
/* Register masks for C Register */
#define BCM283X_BSC_C_I2CEN 0x00008000
/*!< I2C Enable, 0 = disabled, 1 = enabled */
#define BCM283X_BSC_C_INTR 0x00000400
/*!< Interrupt on RX */
#define BCM283X_BSC_C_INTT 0x00000200
/*!< Interrupt on TX */
#define BCM283X_BSC_C_INTD 0x00000100
/*!< Interrupt on DONE */
#define BCM283X_BSC_C_ST 0x00000080
/*!< Start transfer, 1 = Start a new transfer */
#define BCM283X_BSC_C_CLEAR_1 0x00000020
/*!< Clear FIFO Clear */
#define BCM283X_BSC_C_CLEAR_2 0x00000010
/*!< Clear FIFO Clear */
#define BCM283X_BSC_C_READ 0x00000001
/*!< Read transfer */
/* Register masks for S Register */
#define BCM283X_BSC_S_CLKT 0x00000200
/*!< Clock stretch timeout */
#define BCM283X_BSC_S_ERR 0x00000100
/*!< ACK error */
#define BCM283X_BSC_S_RXF 0x00000080
/*!< RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
#define BCM283X_BSC_S_TXE 0x00000040
/*!< TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
#define BCM283X_BSC_S_RXD 0x00000020
/*!< RXD FIFO contains data */
#define BCM283X_BSC_S_TXD 0x00000010
/*!< TXD FIFO can accept data */
#define BCM283X_BSC_S_RXR 0x00000008
/*!< RXR FIFO needs reading (full) */
#define BCM283X_BSC_S_TXW 0x00000004
/*!< TXW FIFO needs writing (full) */
#define BCM283X_BSC_S_DONE 0x00000002
/*!< Transfer DONE */
#define BCM283X_BSC_S_TA 0x00000001
/*!< Transfer Active */
#define BCM283X_BSC_FIFO_SIZE 16
/*!< BSC FIFO size */
enum
i2c_clock_divider
{
BCM283X_I2C_CLOCK_DIVIDER_2500
=
2500
,
/*!< 2500 = 10us = 100 kHz */
BCM283X_I2C_CLOCK_DIVIDER_626
=
626
,
/*!< 622 = 2.504us = 399.3610 kHz */
BCM283X_I2C_CLOCK_DIVIDER_150
=
150
,
/*!< 150 = 60ns = 1.666 MHz (default at reset) */
BCM283X_I2C_CLOCK_DIVIDER_148
=
148
/*!< 148 = 59ns = 1.689 MHz */
};
enum
i2c_reason_codes
{
BCM283X_I2C_REASON_OK
=
0x00
,
/*!< Success */
BCM283X_I2C_REASON_ERROR_NACK
=
0x01
,
/*!< Received a NACK */
BCM283X_I2C_REASON_ERROR_CLKT
=
0x02
,
/*!< Received Clock Stretch Timeout */
BCM283X_I2C_REASON_ERROR_DATA
=
0x04
/*!< Not all data is sent / received */
};
/*
* Interrupt Controler
*/
#define IRQ_BASE (PER_BASE + 0xB200)
#define IRQ_PEND_BASIC HWREG32(IRQ_BASE + 0x00)
#define IRQ_PEND1 HWREG32(IRQ_BASE + 0x04)
#define IRQ_PEND2 HWREG32(IRQ_BASE + 0x08)
#define IRQ_FIQ_CONTROL HWREG32(IRQ_BASE + 0x0C)
#define IRQ_ENABLE1 HWREG32(IRQ_BASE + 0x10)
#define IRQ_ENABLE2 HWREG32(IRQ_BASE + 0x14)
#define IRQ_ENABLE_BASIC HWREG32(IRQ_BASE + 0x18)
#define IRQ_DISABLE1 HWREG32(IRQ_BASE + 0x1C)
#define IRQ_DISABLE2 HWREG32(IRQ_BASE + 0x20)
#define IRQ_DISABLE_BASIC HWREG32(IRQ_BASE + 0x24)
/*
* Gtimer IRQ flag
*/
#define SYSTEM_TIMER_IRQ_0 (1 << 0)
#define SYSTEM_TIMER_IRQ_1 (1 << 1)
#define SYSTEM_TIMER_IRQ_2 (1 << 2)
#define SYSTEM_TIMER_IRQ_3 (1 << 3)
#define NON_SECURE_TIMER_IRQ (1 << 1)
/*
* System Timer
*/
#define STIMER_BASE (PER_BASE + 0x3000)
#define STIMER_CS HWREG32(STIMER_BASE + 0x00)
#define STIMER_CLO HWREG32(STIMER_BASE + 0x04)
#define STIMER_CHI HWREG32(STIMER_BASE + 0x08)
#define STIMER_C0 HWREG32(STIMER_BASE + 0x0C)
#define STIMER_C1 HWREG32(STIMER_BASE + 0x10)
#define STIMER_C2 HWREG32(STIMER_BASE + 0x14)
#define STIMER_C3 HWREG32(STIMER_BASE + 0x18)
/* Defines for ST */
#define BCM283X_ST_BASE (PER_BASE + 0x3000)
#define BCM283X_ST_CS 0x0000
/*!< System Timer Control/Status */
#define BCM283X_ST_CLO 0x0004
/*!< System Timer Counter Lower 32 bits */
#define BCM283X_ST_CHI 0x0008
/*!< System Timer Counter Upper 32 bits */
#define BCM283X_ST_C0 0x000C
#define BCM283X_ST_C1 0x0010
#define BCM283X_ST_C2 0x0014
#define BCM283X_ST_C3 0x0018
/*
* ARM Timer
*/
#define ARM_TIMER_BASE (PER_BASE + 0xB000)
#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400)
#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404)
#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408)
#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C)
#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410)
#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414)
#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418)
#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C)
#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420)
/*
* Core Timer
*/
#define CTIMER_CTL HWREG32(PER_BASE_40000000 + 0x00)
/* Control register */
#define CTIMER_PRE HWREG32(PER_BASE_40000000 + 0x08)
/* Core timer prescaler */
#define CTIMER_LS32B HWREG32(PER_BASE_40000000 + 0x1C)
/* Core timer access LS 32 bits */
#define CTIMER_MS32B HWREG32(PER_BASE_40000000 + 0x20)
/* Core timer access MS 32 bits */
/*
* ARM Core Timer
*/
#define C0TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x40)
/* Core0 timers Interrupt control */
#define C1TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x44)
/* Core1 timers Interrupt control */
#define C2TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x48)
/* Core2 timers Interrupt control */
#define C3TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x4C)
/* Core3 timers Interrupt control */
#define CORETIMER_INTCTL(n) HWREG32(PER_BASE_40000000 + 0x40 + n*4)
/* Core3 timers Interrupt control */
/*
* ARM Core Mailbox interrupt
*/
#define C0MB_INTCTL HWREG32(PER_BASE_40000000 + 0x50)
/* Core0 Mailboxes Interrupt control */
#define C1MB_INTCTL HWREG32(PER_BASE_40000000 + 0x54)
/* Core1 Mailboxes Interrupt control */
#define C2MB_INTCTL HWREG32(PER_BASE_40000000 + 0x58)
/* Core2 Mailboxes Interrupt control */
#define C3MB_INTCTL HWREG32(PER_BASE_40000000 + 0x5C)
/* Core3 Mailboxes Interrupt control */
#define COREMB_INTCTL(n) HWREG32(PER_BASE_40000000 + 0x50 + 4*n)
/* Core3 Mailboxes Interrupt control */
/*
* ARM Core IRQ/FIQ status
*/
#define C0_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x60)
/* Core0 IRQ Source */
#define C1_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x64)
/* Core1 IRQ Source */
#define C2_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x68)
/* Core2 IRQ Source */
#define C3_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x6C)
/* Core3 IRQ Source */
#define C0_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x70)
/* Core0 FIQ Source */
#define C1_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x74)
/* Core1 FIQ Source */
#define C2_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x78)
/* Core2 FIQ Source */
#define C3_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x7C)
/* Core3 FIQ Source */
#define CORE_IRQSOURCE(n) HWREG32(PER_BASE_40000000 + 0x60+ n*0x4)
#define CORE_FIQSOURCE(n) HWREG32(PER_BASE_40000000 + 0x70+ n*0x4)
#define CORE_MAILBOX3_SET(n) HWREG32(PER_BASE_40000000 + 0x8C + n*0x10)
#define CORE_MAILBOX3_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xCC + n*0x10)
#define CORE_MAILBOX2_SET(n) HWREG32(PER_BASE_40000000 + 0x88 + n*0x10)
#define CORE_MAILBOX2_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xC8 + n*0x10)
#define CORE_MAILBOX1_SET(n) HWREG32(PER_BASE_40000000 + 0x84 + n*0x10)
#define CORE_MAILBOX1_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xC4 + n*0x10)
#define CORE_MAILBOX0_SET(n) HWREG32(PER_BASE_40000000 + 0x80 + n*0x10)
#define CORE_MAILBOX0_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xC0 + n*0x10)
/* for smp ipi using mailbox0 */
#define IPI_MAILBOX_SET CORE_MAILBOX0_SET
#define IPI_MAILBOX_CLEAR CORE_MAILBOX0_CLEAR
#define IPI_MAILBOX_INT_MASK (0x01)
#define IRQ_ARM_TIMER 64
#define IRQ_ARM_MAILBOX 65
#define IRQ_ARM_DB0 66
#define IRQ_ARM_DB1 67
#define IRQ_ARM_GPU0_HALT 68
#define IRQ_ARM_GPU1_HALT 69
#define IRQ_ARM_ILLEGAL_ACC1 70
#define IRQ_ARM_ILLEGAL_ACC0 71
#define IRQ_SYSTIMER_MATCH_1 1
#define IRQ_SYSTIMER_MATCH_3 3
#define IRQ_AUX 29
#define IRQ_IIC_SPI_SLV 43
#define IRQ_PWA0 45
#define IRQ_PWA1 46
#define IRQ_SMI 48
#define IRQ_GPIO0 49
#define IRQ_GPIO1 50
#define IRQ_GPIO2 51
#define IRQ_GPIO3 52
#define IRQ_IIC 53
#define IRQ_SPI 54
#define IRQ_PCM 55
#define IRQ_UART 57
/* CLOCK */
#define BCM283X_PLLA 0
#define BCM283X_PLLB 1
#define BCM283X_PLLC 2
#define BCM283X_PLLD 3
#define BCM283X_PLLH 4
#define BCM283X_PLLA_CORE 5
#define BCM283X_PLLA_PER 6
#define BCM283X_PLLB_ARM 7
#define BCM283X_PLLC_CORE0 8
#define BCM283X_PLLC_CORE1 9
#define BCM283X_PLLC_CORE2 10
#define BCM283X_PLLC_PER 11
#define BCM283X_PLLD_CORE 12
#define BCM283X_PLLD_PER 13
#define BCM283X_PLLH_RCAL 14
#define BCM283X_PLLH_AUX 15
#define BCM283X_PLLH_PIX 16
#define BCM283X_CLOCK_TIMER 17
#define BCM283X_CLOCK_OTP 18
#define BCM283X_CLOCK_UART 19
#define BCM283X_CLOCK_VPU 20
#define BCM283X_CLOCK_V3D 21
#define BCM283X_CLOCK_ISP 22
#define BCM283X_CLOCK_H264 23
#define BCM283X_CLOCK_VEC 24
#define BCM283X_CLOCK_HSM 25
#define BCM283X_CLOCK_SDRAM 26
#define BCM283X_CLOCK_TSENS 27
#define BCM283X_CLOCK_EMMC 28
#define BCM283X_CLOCK_PERI_IMAGE 29
#define BCM283X_CLOCK_COUNT 30
#define CM_PASSWORD 0x5a000000
#define CM_GNRICCTL 0x000
#define CM_GNRICDIV 0x004
#define CM_VPUCTL 0x008
#define CM_VPUDIV 0x00c
#define CM_SYSCTL 0x010
#define CM_SYSDIV 0x014
#define CM_PERIACTL 0x018
#define CM_PERIADIV 0x01c
#define CM_PERIICTL 0x020
#define CM_PERIIDIV 0x024
#define CM_H264CTL 0x028
#define CM_H264DIV 0x02c
#define CM_ISPCTL 0x030
#define CM_ISPDIV 0x034
#define CM_V3DCTL 0x038
#define CM_V3DDIV 0x03c
#define CM_CAM0CTL 0x040
#define CM_CAM0DIV 0x044
#define CM_CAM1CTL 0x048
#define CM_CAM1DIV 0x04c
#define CM_CCP2CTL 0x050
#define CM_CCP2DIV 0x054
#define CM_DSI0ECTL 0x058
#define CM_DSI0EDIV 0x05c
#define CM_DSI0PCTL 0x060
#define CM_DSI0PDIV 0x064
#define CM_DPICTL 0x068
#define CM_DPIDIV 0x06c
#define CM_GP0CTL 0x070
#define CM_GP0DIV 0x074
#define CM_GP1CTL 0x078
#define CM_GP1DIV 0x07c
#define CM_GP2CTL 0x080
#define CM_GP2DIV 0x084
#define CM_HSMCTL 0x088
#define CM_HSMDIV 0x08c
#define CM_OTPCTL 0x090
#define CM_OTPDIV 0x094
#define CM_PWMCTL 0x0a0
#define CM_PWMDIV 0x0a4
#define CM_SMICTL 0x0b0
#define CM_SMIDIV 0x0b4
#define CM_TSENSCTL 0x0e0
#define CM_TSENSDIV 0x0e4
#define CM_TIMERCTL 0x0e8
#define CM_TIMERDIV 0x0ec
#define CM_UARTCTL 0x0f0
#define CM_UARTDIV 0x0f4
#define CM_VECCTL 0x0f8
#define CM_VECDIV 0x0fc
#define CM_PULSECTL 0x190
#define CM_PULSEDIV 0x194
#define CM_SDCCTL 0x1a8
#define CM_SDCDIV 0x1ac
#define CM_ARMCTL 0x1b0
#define CM_EMMCCTL 0x1c0
#define CM_EMMCDIV 0x1c4
#define BCM283X_AUX_IRQ 0x0000
/*!< xxx */
#define BCM283X_AUX_ENABLE 0x0004
/*!< */
#define BCM283X_AUX_ENABLE_UART1 0x01
/*!< */
#define BCM283X_AUX_ENABLE_SPI0 0x02
/*!< SPI0 (SPI1 in the device) */
#define BCM283X_AUX_ENABLE_SPI1 0x04
/*!< SPI1 (SPI2 in the device) */
#define BCM283X_AUX_SPI_CNTL0 0x0000
/*!< */
#define BCM283X_AUX_SPI_CNTL1 0x0004
/*!< */
#define BCM283X_AUX_SPI_STAT 0x0008
/*!< */
#define BCM283X_AUX_SPI_PEEK 0x000C
/*!< Read but do not take from FF */
#define BCM283X_AUX_SPI_IO 0x0020
/*!< Write = TX, read=RX */
#define BCM283X_AUX_SPI_TXHOLD 0x0030
/*!< Write = TX keep CS, read=RX */
#define BCM283X_AUX_SPI_CLOCK_MIN 30500
/*!< 30,5kHz */
#define BCM283X_AUX_SPI_CLOCK_MAX 125000000
/*!< 125Mhz */
#define BCM283X_AUX_SPI_CNTL0_SPEED 0xFFF00000
/*!< */
#define BCM283X_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
/*!< */
#define BCM283X_AUX_SPI_CNTL0_SPEED_SHIFT 20
/*!< */
#define BCM283X_AUX_SPI_CNTL0_CS0_N 0x000C0000
/*!< CS 0 low */
#define BCM283X_AUX_SPI_CNTL0_CS1_N 0x000A0000
/*!< CS 1 low */
#define BCM283X_AUX_SPI_CNTL0_CS2_N 0x00060000
/*!< CS 2 low */
#define BCM283X_AUX_SPI_CNTL0_POSTINPUT 0x00010000
/*!< */
#define BCM283X_AUX_SPI_CNTL0_VAR_CS 0x00008000
/*!< */
#define BCM283X_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
/*!< */
#define BCM283X_AUX_SPI_CNTL0_DOUTHOLD 0x00003000
/*!< */
#define BCM283X_AUX_SPI_CNTL0_ENABLE 0x00000800
/*!< */
#define BCM283X_AUX_SPI_CNTL0_CPHA_IN 0x00000400
/*!< */
#define BCM283X_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
/*!< */
#define BCM283X_AUX_SPI_CNTL0_CPHA_OUT 0x00000100
/*!< */
#define BCM283X_AUX_SPI_CNTL0_CPOL 0x00000080
/*!< */
#define BCM283X_AUX_SPI_CNTL0_MSBF_OUT 0x00000040
/*!< */
#define BCM283X_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F
/*!< */
#define BCM283X_AUX_SPI_CNTL1_CSHIGH 0x00000700
/*!< */
#define BCM283X_AUX_SPI_CNTL1_IDLE 0x00000080
/*!< */
#define BCM283X_AUX_SPI_CNTL1_TXEMPTY 0x00000040
/*!< */
#define BCM283X_AUX_SPI_CNTL1_MSBF_IN 0x00000002
/*!< */
#define BCM283X_AUX_SPI_CNTL1_KEEP_IN 0x00000001
/*!< */
#define BCM283X_AUX_SPI_STAT_TX_LVL 0xFF000000
/*!< */
#define BCM283X_AUX_SPI_STAT_RX_LVL 0x00FF0000
/*!< */
#define BCM283X_AUX_SPI_STAT_TX_FULL 0x00000400
/*!< */
#define BCM283X_AUX_SPI_STAT_TX_EMPTY 0x00000200
/*!< */
#define BCM283X_AUX_SPI_STAT_RX_FULL 0x00000100
/*!< */
#define BCM283X_AUX_SPI_STAT_RX_EMPTY 0x00000080
/*!< */
#define BCM283X_AUX_SPI_STAT_BUSY 0x00000040
/*!< */
#define BCM283X_AUX_SPI_STAT_BITCOUNT 0x0000003F
/*!< */
/* Defines for SPI */
#define BCM283X_SPI0_CS 0x0000
/*!< SPI Master Control and Status */
#define BCM283X_SPI0_FIFO 0x0004
/*!< SPI Master TX and RX FIFOs */
#define BCM283X_SPI0_CLK 0x0008
/*!< SPI Master Clock Divider */
#define BCM283X_SPI0_DLEN 0x000c
/*!< SPI Master Data Length */
#define BCM283X_SPI0_LTOH 0x0010
/*!< SPI LOSSI mode TOH */
#define BCM283X_SPI0_DC 0x0014
/*!< SPI DMA DREQ Controls */
/* Register masks for SPI0_CS */
#define BCM283X_SPI0_CS_LEN_LONG 0x02000000
/*!< Enable Long data word in Lossi mode if DMA_LEN is set */
#define BCM283X_SPI0_CS_DMA_LEN 0x01000000
/*!< Enable DMA mode in Lossi mode */
#define BCM283X_SPI0_CS_CSPOL2 0x00800000
/*!< Chip Select 2 Polarity */
#define BCM283X_SPI0_CS_CSPOL1 0x00400000
/*!< Chip Select 1 Polarity */
#define BCM283X_SPI0_CS_CSPOL0 0x00200000
/*!< Chip Select 0 Polarity */
#define BCM283X_SPI0_CS_RXF 0x00100000
/*!< RXF - RX FIFO Full */
#define BCM283X_SPI0_CS_RXR 0x00080000
/*!< RXR RX FIFO needs Reading (full) */
#define BCM283X_SPI0_CS_TXD 0x00040000
/*!< TXD TX FIFO can accept Data */
#define BCM283X_SPI0_CS_RXD 0x00020000
/*!< RXD RX FIFO contains Data */
#define BCM283X_SPI0_CS_DONE 0x00010000
/*!< Done transfer Done */
#define BCM283X_SPI0_CS_TE_EN 0x00008000
/*!< Unused */
#define BCM283X_SPI0_CS_LMONO 0x00004000
/*!< Unused */
#define BCM283X_SPI0_CS_LEN 0x00002000
/*!< LEN LoSSI enable */
#define BCM283X_SPI0_CS_REN 0x00001000
/*!< REN Read Enable */
#define BCM283X_SPI0_CS_ADCS 0x00000800
/*!< ADCS Automatically Deassert Chip Select */
#define BCM283X_SPI0_CS_INTR 0x00000400
/*!< INTR Interrupt on RXR */
#define BCM283X_SPI0_CS_INTD 0x00000200
/*!< INTD Interrupt on Done */
#define BCM283X_SPI0_CS_DMAEN 0x00000100
/*!< DMAEN DMA Enable */
#define BCM283X_SPI0_CS_TA 0x00000080
/*!< Transfer Active */
#define BCM283X_SPI0_CS_CSPOL 0x00000040
/*!< Chip Select Polarity */
#define BCM283X_SPI0_CS_CLEAR 0x00000030
/*!< Clear FIFO Clear RX and TX */
#define BCM283X_SPI0_CS_CLEAR_RX 0x00000020
/*!< Clear FIFO Clear RX */
#define BCM283X_SPI0_CS_CLEAR_TX 0x00000010
/*!< Clear FIFO Clear TX */
#define BCM283X_SPI0_CS_CPOL 0x00000008
/*!< Clock Polarity */
#define BCM283X_SPI0_CS_CPHA 0x00000004
/*!< Clock Phase */
#define BCM283X_SPI0_CS_CS 0x00000003
/*!< Chip Select */
enum
spi_bit_order
{
BCM283X_SPI_BIT_ORDER_LSBFIRST
=
0
,
/*!< LSB First */
BCM283X_SPI_BIT_ORDER_MSBFIRST
=
1
/*!< MSB First */
};
enum
spi_mode
{
BCM283X_SPI_MODE0
=
0
,
/*!< CPOL = 0, CPHA = 0 */
BCM283X_SPI_MODE1
=
1
,
/*!< CPOL = 0, CPHA = 1 */
BCM283X_SPI_MODE2
=
2
,
/*!< CPOL = 1, CPHA = 0 */
BCM283X_SPI_MODE3
=
3
/*!< CPOL = 1, CPHA = 1 */
};
enum
spi_chip_select
{
BCM283X_SPI_CS0
=
0
,
/*!< Chip Select 0 */
BCM283X_SPI_CS1
=
1
,
/*!< Chip Select 1 */
BCM283X_SPI_CS2
=
2
,
/*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */
BCM283X_SPI_CS_NONE
=
3
/*!< No CS, control it yourself */
};
enum
spi_clock_divider
{
BCM283X_SPI_CLOCK_DIVIDER_65536
=
0
,
/*!< 65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_32768
=
32768
,
/*!< 32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_16384
=
16384
,
/*!< 16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_8192
=
8192
,
/*!< 8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_4096
=
4096
,
/*!< 4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_2048
=
2048
,
/*!< 2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_1024
=
1024
,
/*!< 1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_512
=
512
,
/*!< 512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_256
=
256
,
/*!< 256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_128
=
128
,
/*!< 128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_64
=
64
,
/*!< 64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_32
=
32
,
/*!< 32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_16
=
16
,
/*!< 16 = 15.625MHz on Rpi2, 25MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_8
=
8
,
/*!< 8 = 31.25MHz on Rpi2, 50MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_4
=
4
,
/*!< 4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably. */
BCM283X_SPI_CLOCK_DIVIDER_2
=
2
,
/*!< 2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to work reliably.*/
BCM283X_SPI_CLOCK_DIVIDER_1
=
1
/*!< 1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536 */
};
/* BCM IO pin */
enum
bcm_gpio_pin
{
BCM_GPIO_PIN_0
=
0
,
BCM_GPIO_PIN_1
,
BCM_GPIO_PIN_2
,
BCM_GPIO_PIN_3
,
BCM_GPIO_PIN_4
,
BCM_GPIO_PIN_5
,
BCM_GPIO_PIN_6
,
BCM_GPIO_PIN_7
,
BCM_GPIO_PIN_8
,
BCM_GPIO_PIN_9
,
BCM_GPIO_PIN_10
,
BCM_GPIO_PIN_11
,
BCM_GPIO_PIN_12
,
BCM_GPIO_PIN_13
,
BCM_GPIO_PIN_14
,
BCM_GPIO_PIN_15
,
BCM_GPIO_PIN_16
,
BCM_GPIO_PIN_17
,
BCM_GPIO_PIN_18
,
BCM_GPIO_PIN_19
,
BCM_GPIO_PIN_20
,
BCM_GPIO_PIN_21
,
BCM_GPIO_PIN_22
,
BCM_GPIO_PIN_23
,
BCM_GPIO_PIN_24
,
BCM_GPIO_PIN_25
,
BCM_GPIO_PIN_26
,
BCM_GPIO_PIN_27
,
BCM_GPIO_PIN_28
,
BCM_GPIO_PIN_29
,
BCM_GPIO_PIN_30
,
BCM_GPIO_PIN_31
,
BCM_GPIO_PIN_32
,
BCM_GPIO_PIN_33
,
BCM_GPIO_PIN_34
,
BCM_GPIO_PIN_35
,
BCM_GPIO_PIN_36
,
BCM_GPIO_PIN_37
,
BCM_GPIO_PIN_38
,
BCM_GPIO_PIN_39
,
BCM_GPIO_PIN_40
,
BCM_GPIO_PIN_41
,
BCM_GPIO_PIN_42
,
BCM_GPIO_PIN_43
,
BCM_GPIO_PIN_44
,
BCM_GPIO_PIN_45
,
BCM_GPIO_PIN_46
,
BCM_GPIO_PIN_47
,
BCM_GPIO_PIN_48
,
BCM_GPIO_PIN_49
,
BCM_GPIO_PIN_50
,
BCM_GPIO_PIN_51
,
BCM_GPIO_PIN_52
,
BCM_GPIO_PIN_53
,
BCM_GPIO_PIN_NUM
,
};
rt_uint32_t
bcm283x_peri_read
(
volatile
rt_ubase_t
addr
);
rt_uint32_t
bcm283x_peri_read_nb
(
volatile
rt_ubase_t
addr
);
void
bcm283x_peri_write
(
volatile
rt_ubase_t
addr
,
rt_uint32_t
value
);
void
bcm283x_peri_write_nb
(
volatile
rt_ubase_t
addr
,
rt_uint32_t
value
);
void
bcm283x_peri_set_bits
(
volatile
rt_ubase_t
addr
,
rt_uint32_t
value
,
rt_uint32_t
mask
);
void
bcm283x_gpio_fsel
(
rt_uint8_t
pin
,
rt_uint8_t
mode
);
void
bcm283x_gpio_set
(
rt_uint8_t
pin
);
void
bcm283x_gpio_clr
(
rt_uint8_t
pin
);
rt_uint8_t
bcm283x_gpio_lev
(
rt_uint8_t
pin
);
rt_uint8_t
bcm283x_gpio_eds
(
rt_uint8_t
pin
);
void
bcm283x_gpio_set_eds
(
rt_uint8_t
pin
);
void
bcm283x_gpio_ren
(
rt_uint8_t
pin
);
void
bcm283x_gpio_clr_ren
(
rt_uint8_t
pin
);
void
bcm283x_gpio_fen
(
rt_uint8_t
pin
);
void
bcm283x_gpio_clr_fen
(
rt_uint8_t
pin
);
void
bcm283x_gpio_hen
(
rt_uint8_t
pin
);
void
bcm283x_gpio_clr_hen
(
rt_uint8_t
pin
);
void
bcm283x_gpio_len
(
rt_uint8_t
pin
);
void
bcm283x_gpio_clr_len
(
rt_uint8_t
pin
);
void
bcm283x_gpio_aren
(
rt_uint8_t
pin
);
void
bcm283x_gpio_clr_aren
(
rt_uint8_t
pin
);
void
bcm283x_gpio_afen
(
rt_uint8_t
pin
);
void
bcm283x_gpio_clr_afen
(
rt_uint8_t
pin
);
void
bcm283x_gpio_pud
(
rt_uint8_t
pud
);
void
bcm283x_gpio_pudclk
(
rt_uint8_t
pin
,
rt_uint8_t
on
);
void
bcm283x_gpio_set_pud
(
rt_uint8_t
pin
,
rt_uint8_t
pud
);
void
bcm283x_gpio_write
(
rt_uint8_t
pin
,
rt_uint8_t
val
);
void
bcm283x_st_delay
(
rt_uint64_t
offset_micros
,
rt_uint64_t
micros
);
rt_uint64_t
bcm283x_st_read
(
void
);
void
bcm283x_delayMicroseconds
(
rt_uint64_t
micros
);
void
bcm283x_clo_delayMicros
(
rt_uint32_t
micros
);
int
bcm283x_i2c_begin
(
int
no
);
void
bcm283x_i2c_end
(
int
no
);
void
bcm283x_i2c_setSlaveAddress
(
int
no
,
rt_uint8_t
saddr
);
void
bcm283x_i2c_setClockDivider
(
int
no
,
rt_uint16_t
divider
);
void
bcm283x_i2c_set_baudrate
(
int
no
,
rt_uint32_t
baudrate
);
rt_uint8_t
bcm283x_i2c_read
(
rt_uint32_t
base
,
rt_uint8_t
*
buf
,
rt_uint32_t
len
);
rt_uint8_t
bcm283x_i2c_write
(
rt_uint32_t
base
,
const
rt_uint8_t
*
buf
,
rt_uint32_t
len
);
rt_uint8_t
bcm283x_i2c_write_read_rs
(
char
*
cmds
,
rt_uint32_t
cmds_len
,
char
*
buf
,
rt_uint32_t
buf_len
);
#endif
bsp/raspberry-pi/raspi3-64/driver/board.c
浏览文件 @
3d2b66a8
...
...
@@ -17,6 +17,7 @@
#include "cp15.h"
#include "mmu.h"
#include "raspi.h"
#ifdef BSP_USING_CORETIMER
static
rt_uint64_t
timerStep
;
...
...
@@ -98,6 +99,7 @@ void rt_hw_board_init(void)
armv8_map
(
0x3f200000
,
0x3f200000
,
0x16000
,
MEM_ATTR_IO
);
//uart
armv8_map
(
0x40000000
,
0x40000000
,
0x1000
,
MEM_ATTR_IO
);
//core timer
armv8_map
(
0x3F300000
,
0x3F300000
,
0x1000
,
MEM_ATTR_IO
);
//sdio
armv8_map
(
0xc00000
,
0xc00000
,
0x1000
,
MEM_ATTR_IO
);
//mbox
mmu_enable
();
/* initialize hardware interrupt */
...
...
bsp/raspberry-pi/raspi3-64/driver/board.h
浏览文件 @
3d2b66a8
...
...
@@ -13,10 +13,6 @@
#include <stdint.h>
#include <rthw.h>
#include <bcm283x.h>
#define __REG32 HWREG32
extern
unsigned
char
__bss_start
;
extern
unsigned
char
__bss_end
;
...
...
bsp/raspberry-pi/raspi3-64/driver/drv_fb.c
浏览文件 @
3d2b66a8
...
...
@@ -9,283 +9,30 @@
*/
#include <rthw.h>
#include <stdint.h>
#include <rtthread.h>
#include "mbox.h"
#include "drv_fb.h"
#include "mmu.h"
#define CHAR_W 8
#define CHAR_H 12
#define LCD_WIDTH (640)
#define LCD_HEIGHT (480)
#define LCD_DEPTH (32)
#define COLOR_DELTA 0.05
static
struct
rt_hdmi_fb_device
_hdmi
;
// https://github.com/xinu-os/xinu/blob/1789b7a50b5b73c2ea76ebd764c54a034097d04d/device/framebuffer_rpi/font.c
unsigned
char
FONT
[]
=
{
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*' '*/
0x00
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x00
,
0x08
,
0x00
,
0x00
,
0x00
,
/*'!'*/
0x00
,
0x14
,
0x14
,
0x14
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*'"'*/
0x00
,
0x00
,
0x14
,
0x14
,
0x3e
,
0x14
,
0x3e
,
0x14
,
0x14
,
0x00
,
0x00
,
0x00
,
/*'#'*/
0x00
,
0x00
,
0x08
,
0x3c
,
0x0a
,
0x1c
,
0x28
,
0x1e
,
0x08
,
0x00
,
0x00
,
0x00
,
/*'$'*/
0x00
,
0x00
,
0x06
,
0x26
,
0x10
,
0x08
,
0x04
,
0x32
,
0x30
,
0x00
,
0x00
,
0x00
,
/*'%'*/
0x00
,
0x00
,
0x1c
,
0x02
,
0x02
,
0x04
,
0x2a
,
0x12
,
0x2c
,
0x00
,
0x00
,
0x00
,
/*'&'*/
0x00
,
0x18
,
0x08
,
0x04
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*'''*/
0x20
,
0x10
,
0x10
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x10
,
0x10
,
0x20
,
0x00
,
/*'('*/
0x02
,
0x04
,
0x04
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x04
,
0x04
,
0x02
,
0x00
,
/*')'*/
0x00
,
0x00
,
0x00
,
0x08
,
0x2a
,
0x1c
,
0x2a
,
0x08
,
0x00
,
0x00
,
0x00
,
0x00
,
/*'*'*/
0x00
,
0x00
,
0x00
,
0x08
,
0x08
,
0x3e
,
0x08
,
0x08
,
0x00
,
0x00
,
0x00
,
0x00
,
/*'+'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x18
,
0x18
,
0x08
,
0x04
,
0x00
,
/*','*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x3e
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*'-'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x18
,
0x18
,
0x00
,
0x00
,
0x00
,
/*'.'*/
0x20
,
0x20
,
0x10
,
0x10
,
0x08
,
0x08
,
0x04
,
0x04
,
0x02
,
0x02
,
0x00
,
0x00
,
/*'/'*/
0x00
,
0x1c
,
0x22
,
0x32
,
0x2a
,
0x26
,
0x22
,
0x22
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'0'*/
0x00
,
0x08
,
0x0c
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x00
,
0x00
,
0x00
,
/*'1'*/
0x00
,
0x1c
,
0x22
,
0x20
,
0x10
,
0x08
,
0x04
,
0x02
,
0x3e
,
0x00
,
0x00
,
0x00
,
/*'2'*/
0x00
,
0x1c
,
0x22
,
0x20
,
0x18
,
0x20
,
0x20
,
0x22
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'3'*/
0x00
,
0x10
,
0x18
,
0x18
,
0x14
,
0x14
,
0x3e
,
0x10
,
0x38
,
0x00
,
0x00
,
0x00
,
/*'4'*/
0x00
,
0x3e
,
0x02
,
0x02
,
0x1e
,
0x20
,
0x20
,
0x22
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'5'*/
0x00
,
0x18
,
0x04
,
0x02
,
0x1e
,
0x22
,
0x22
,
0x22
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'6'*/
0x00
,
0x3e
,
0x22
,
0x20
,
0x20
,
0x10
,
0x10
,
0x08
,
0x08
,
0x00
,
0x00
,
0x00
,
/*'7'*/
0x00
,
0x1c
,
0x22
,
0x22
,
0x1c
,
0x22
,
0x22
,
0x22
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'8'*/
0x00
,
0x1c
,
0x22
,
0x22
,
0x22
,
0x3c
,
0x20
,
0x10
,
0x0c
,
0x00
,
0x00
,
0x00
,
/*'9'*/
0x00
,
0x00
,
0x00
,
0x18
,
0x18
,
0x00
,
0x00
,
0x18
,
0x18
,
0x00
,
0x00
,
0x00
,
/*':'*/
0x00
,
0x00
,
0x00
,
0x18
,
0x18
,
0x00
,
0x00
,
0x18
,
0x18
,
0x08
,
0x04
,
0x00
,
/*';'*/
0x00
,
0x00
,
0x00
,
0x30
,
0x0c
,
0x03
,
0x0c
,
0x30
,
0x00
,
0x00
,
0x00
,
0x00
,
/*'<'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x3e
,
0x00
,
0x3e
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*'='*/
0x00
,
0x00
,
0x00
,
0x03
,
0x0c
,
0x30
,
0x0c
,
0x03
,
0x00
,
0x00
,
0x00
,
0x00
,
/*'>'*/
0x00
,
0x1c
,
0x22
,
0x20
,
0x10
,
0x08
,
0x08
,
0x00
,
0x08
,
0x00
,
0x00
,
0x00
,
/*'?'*/
0x00
,
0x00
,
0x1c
,
0x22
,
0x3a
,
0x3a
,
0x1a
,
0x02
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'@'*/
0x00
,
0x00
,
0x08
,
0x14
,
0x22
,
0x22
,
0x3e
,
0x22
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'A'*/
0x00
,
0x00
,
0x1e
,
0x22
,
0x22
,
0x1e
,
0x22
,
0x22
,
0x1e
,
0x00
,
0x00
,
0x00
,
/*'B'*/
0x00
,
0x00
,
0x1c
,
0x22
,
0x02
,
0x02
,
0x02
,
0x22
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'C'*/
0x00
,
0x00
,
0x0e
,
0x12
,
0x22
,
0x22
,
0x22
,
0x12
,
0x0e
,
0x00
,
0x00
,
0x00
,
/*'D'*/
0x00
,
0x00
,
0x3e
,
0x02
,
0x02
,
0x1e
,
0x02
,
0x02
,
0x3e
,
0x00
,
0x00
,
0x00
,
/*'E'*/
0x00
,
0x00
,
0x3e
,
0x02
,
0x02
,
0x1e
,
0x02
,
0x02
,
0x02
,
0x00
,
0x00
,
0x00
,
/*'F'*/
0x00
,
0x00
,
0x1c
,
0x22
,
0x02
,
0x32
,
0x22
,
0x22
,
0x3c
,
0x00
,
0x00
,
0x00
,
/*'G'*/
0x00
,
0x00
,
0x22
,
0x22
,
0x22
,
0x3e
,
0x22
,
0x22
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'H'*/
0x00
,
0x00
,
0x3e
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x3e
,
0x00
,
0x00
,
0x00
,
/*'I'*/
0x00
,
0x00
,
0x38
,
0x20
,
0x20
,
0x20
,
0x22
,
0x22
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'J'*/
0x00
,
0x00
,
0x22
,
0x12
,
0x0a
,
0x06
,
0x0a
,
0x12
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'K'*/
0x00
,
0x00
,
0x02
,
0x02
,
0x02
,
0x02
,
0x02
,
0x02
,
0x3e
,
0x00
,
0x00
,
0x00
,
/*'L'*/
0x00
,
0x00
,
0x22
,
0x36
,
0x2a
,
0x2a
,
0x22
,
0x22
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'M'*/
0x00
,
0x00
,
0x22
,
0x26
,
0x26
,
0x2a
,
0x32
,
0x32
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'N'*/
0x00
,
0x00
,
0x1c
,
0x22
,
0x22
,
0x22
,
0x22
,
0x22
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'O'*/
0x00
,
0x00
,
0x1e
,
0x22
,
0x22
,
0x1e
,
0x02
,
0x02
,
0x02
,
0x00
,
0x00
,
0x00
,
/*'P'*/
0x00
,
0x00
,
0x1c
,
0x22
,
0x22
,
0x22
,
0x22
,
0x22
,
0x1c
,
0x30
,
0x00
,
0x00
,
/*'Q'*/
0x00
,
0x00
,
0x1e
,
0x22
,
0x22
,
0x1e
,
0x0a
,
0x12
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'R'*/
0x00
,
0x00
,
0x1c
,
0x22
,
0x02
,
0x1c
,
0x20
,
0x22
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'S'*/
0x00
,
0x00
,
0x3e
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x00
,
0x00
,
0x00
,
/*'T'*/
0x00
,
0x00
,
0x22
,
0x22
,
0x22
,
0x22
,
0x22
,
0x22
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'U'*/
0x00
,
0x00
,
0x22
,
0x22
,
0x22
,
0x14
,
0x14
,
0x08
,
0x08
,
0x00
,
0x00
,
0x00
,
/*'V'*/
0x00
,
0x00
,
0x22
,
0x22
,
0x22
,
0x2a
,
0x2a
,
0x36
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'W'*/
0x00
,
0x00
,
0x22
,
0x22
,
0x14
,
0x08
,
0x14
,
0x22
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'X'*/
0x00
,
0x00
,
0x22
,
0x22
,
0x14
,
0x08
,
0x08
,
0x08
,
0x08
,
0x00
,
0x00
,
0x00
,
/*'Y'*/
0x00
,
0x00
,
0x3e
,
0x20
,
0x10
,
0x08
,
0x04
,
0x02
,
0x3e
,
0x00
,
0x00
,
0x00
,
/*'Z'*/
0x38
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x38
,
0x00
,
/*'['*/
0x02
,
0x02
,
0x04
,
0x04
,
0x08
,
0x08
,
0x10
,
0x10
,
0x20
,
0x20
,
0x00
,
0x00
,
/*'\'*/
0x0e
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x0e
,
0x00
,
/*']'*/
0x00
,
0x08
,
0x14
,
0x22
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*'^'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x3f
,
0x00
,
0x00
,
/*'_'*/
0x00
,
0x0c
,
0x08
,
0x10
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*'`'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x3c
,
0x22
,
0x22
,
0x32
,
0x2c
,
0x00
,
0x00
,
0x00
,
/*'a'*/
0x00
,
0x02
,
0x02
,
0x02
,
0x1e
,
0x22
,
0x22
,
0x22
,
0x1e
,
0x00
,
0x00
,
0x00
,
/*'b'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x3c
,
0x02
,
0x02
,
0x02
,
0x3c
,
0x00
,
0x00
,
0x00
,
/*'c'*/
0x00
,
0x20
,
0x20
,
0x20
,
0x3c
,
0x22
,
0x22
,
0x22
,
0x3c
,
0x00
,
0x00
,
0x00
,
/*'d'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x1c
,
0x22
,
0x3e
,
0x02
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'e'*/
0x00
,
0x38
,
0x04
,
0x04
,
0x1e
,
0x04
,
0x04
,
0x04
,
0x04
,
0x00
,
0x00
,
0x00
,
/*'f'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x3c
,
0x22
,
0x22
,
0x22
,
0x3c
,
0x20
,
0x20
,
0x1c
,
/*'g'*/
0x00
,
0x02
,
0x02
,
0x02
,
0x1e
,
0x22
,
0x22
,
0x22
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'h'*/
0x00
,
0x08
,
0x08
,
0x00
,
0x0c
,
0x08
,
0x08
,
0x08
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'i'*/
0x00
,
0x10
,
0x10
,
0x00
,
0x1c
,
0x10
,
0x10
,
0x10
,
0x10
,
0x10
,
0x10
,
0x0e
,
/*'j'*/
0x00
,
0x02
,
0x02
,
0x02
,
0x12
,
0x0a
,
0x06
,
0x0a
,
0x12
,
0x00
,
0x00
,
0x00
,
/*'k'*/
0x00
,
0x0c
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'l'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x16
,
0x2a
,
0x2a
,
0x2a
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'m'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x1a
,
0x26
,
0x22
,
0x22
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'n'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x1c
,
0x22
,
0x22
,
0x22
,
0x1c
,
0x00
,
0x00
,
0x00
,
/*'o'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x1e
,
0x22
,
0x22
,
0x22
,
0x1e
,
0x02
,
0x02
,
0x02
,
/*'p'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x3c
,
0x22
,
0x22
,
0x22
,
0x3c
,
0x20
,
0x20
,
0x20
,
/*'q'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x1a
,
0x06
,
0x02
,
0x02
,
0x02
,
0x00
,
0x00
,
0x00
,
/*'r'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x3c
,
0x02
,
0x1c
,
0x20
,
0x1e
,
0x00
,
0x00
,
0x00
,
/*'s'*/
0x00
,
0x08
,
0x08
,
0x08
,
0x3e
,
0x08
,
0x08
,
0x08
,
0x30
,
0x00
,
0x00
,
0x00
,
/*'t'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x22
,
0x22
,
0x22
,
0x32
,
0x2c
,
0x00
,
0x00
,
0x00
,
/*'u'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x36
,
0x14
,
0x14
,
0x08
,
0x08
,
0x00
,
0x00
,
0x00
,
/*'v'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x22
,
0x2a
,
0x2a
,
0x2a
,
0x14
,
0x00
,
0x00
,
0x00
,
/*'w'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x22
,
0x14
,
0x08
,
0x14
,
0x22
,
0x00
,
0x00
,
0x00
,
/*'x'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x22
,
0x22
,
0x22
,
0x22
,
0x3c
,
0x20
,
0x20
,
0x1c
,
/*'y'*/
0x00
,
0x00
,
0x00
,
0x00
,
0x3e
,
0x10
,
0x08
,
0x04
,
0x3e
,
0x00
,
0x00
,
0x00
,
/*'z'*/
0x20
,
0x10
,
0x10
,
0x10
,
0x10
,
0x08
,
0x10
,
0x10
,
0x10
,
0x10
,
0x20
,
0x00
,
/*'{'*/
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x08
,
0x00
,
/*'|'*/
0x02
,
0x04
,
0x04
,
0x04
,
0x04
,
0x08
,
0x04
,
0x04
,
0x04
,
0x04
,
0x02
,
0x00
,
/*'}'*/
0x00
,
0x04
,
0x2a
,
0x10
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
0x00
,
/*'~'*/
0x00
,
0x00
,
0x00
,
0x08
,
0x08
,
0x14
,
0x14
,
0x22
,
0x3e
,
0x00
,
0x00
,
0x00
,
/*DEL*/
};
void
newline
(
fb_t
*
fb
)
{
uint8_t
*
to
;
uint8_t
*
from
;
int
i
;
fb
->
y
++
;
fb
->
x
=
0
;
if
(
fb
->
y
==
(
fb
->
height
/
CHAR_H
))
{
to
=
(
uint8_t
*
)
fb
->
addr
;
from
=
to
+
(
CHAR_H
*
fb
->
pitch
);
for
(
i
=
0
;
i
<
((
fb
->
height
-
CHAR_H
)
*
fb
->
pitch
);
i
++
)
{
*
to
++
=
*
from
++
;
}
uint32_t
*
addr
=
(
uint32_t
*
)
(
fb
->
addr
)
+
(
fb
->
height
-
CHAR_H
)
*
fb
->
width
;
for
(
i
=
0
;
i
<
(
CHAR_H
*
fb
->
width
);
i
++
)
{
*
addr
++
=
fb
->
back
;
}
fb
->
y
--
;
}
}
void
clear_line
(
fb_t
*
fb
,
const
int
line
)
{
int
i
;
uint32_t
*
addr
;
if
(
line
>
fb
->
height
/
CHAR_H
)
{
fb
->
y
=
0
;
}
else
{
fb
->
y
=
line
;
}
fb
->
x
=
0
;
addr
=
(
uint32_t
*
)
(
fb
->
addr
+
(
line
*
CHAR_H
*
fb
->
depth
*
fb
->
width
));
for
(
i
=
0
;
i
<
(
CHAR_H
*
fb
->
width
);
i
++
)
{
*
addr
++
=
fb
->
back
;
}
}
#define TAG_ALLOCATE_BUFFER 0x00040001
#define TAG_SET_PHYS_WIDTH_HEIGHT 0x00048003
#define TAG_SET_VIRT_WIDTH_HEIGHT 0x00048004
#define TAG_SET_DEPTH 0x00048005
#define TAG_SET_PIXEL_ORDER 0x00048006
#define TAG_GET_PITCH 0x00040008
#define TAG_SET_VIRT_OFFSET 0x00048009
#define TAG_END 0x00000000
void
clear
(
fb_t
*
fb
,
const
uint32_t
color
)
{
uint32_t
*
addr
=
(
uint32_t
*
)
fb
->
addr
;
uint32_t
i
;
for
(
i
=
0
;
i
<
(
fb
->
height
*
fb
->
width
);
i
++
)
{
*
addr
++
=
color
;
}
fb
->
x
=
0
;
fb
->
y
=
0
;
#define LCD_DEVICE(dev) (struct rt_hdmi_fb_device*)(dev)
}
void
fb_draw_char
(
fb_t
*
fb
,
char
s
)
{
unsigned
char
*
addr
=
(
unsigned
char
*
)
fb
->
addr
;
unsigned
char
*
glyph
=
(
unsigned
char
*
)
FONT
+
(
s
)
*
12
;
// calculate the offset on screen
int
offs
=
(
fb
->
y
*
CHAR_H
*
fb
->
pitch
)
+
(
fb
->
x
*
(
CHAR_W
+
1
)
*
4
);
// variables
int
i
,
j
,
line
,
mask
,
bytesperline
=
(
CHAR_W
+
7
)
/
8
;
// display a character
for
(
j
=
0
;
j
<
CHAR_H
;
j
++
)
{
// display one row
line
=
offs
;
mask
=
1
;
for
(
i
=
0
;
i
<
CHAR_W
;
i
++
)
{
// if bit set, we use white color, otherwise black
*
((
unsigned
int
*
)
(
addr
+
line
))
=
((
int
)
*
glyph
)
&
mask
?
fb
->
fore
:
fb
->
back
;
mask
<<=
1
;
line
+=
4
;
}
// adjust to next line
glyph
+=
bytesperline
;
offs
+=
fb
->
pitch
;
}
}
void
fb_print
(
fb_t
*
fb
,
char
*
s
)
{
static
struct
rt_hdmi_fb_device
_hdmi
;
// draw next character if it's not zero
while
(
*
s
)
{
// handle carrige return
if
(
*
s
==
'\r'
)
{
fb
->
x
=
0
;
}
else
if
(
*
s
==
'\n'
)
{
newline
(
fb
);
}
else
if
(
*
s
==
'\t'
)
{
fb
->
x
=
((
fb
->
x
+
4
)
>>
2
)
<<
2
;
}
else
if
(
*
s
==
'\b'
)
{
if
(
fb
->
x
)
{
fb
->
x
--
;
fb_draw_char
(
fb
,
' '
);
}
}
else
{
fb_draw_char
(
fb
,
*
s
);
fb
->
x
++
;
}
// next character
if
(
fb
->
x
==
fb
->
width
/
CHAR_W
)
{
newline
(
fb
);
}
s
++
;
}
}
typedef
rt_uint16_t
color_t
;
rt_err_t
hdmi_fb_open
(
rt_device_t
dev
,
rt_uint16_t
oflag
)
{
...
...
@@ -299,46 +46,44 @@ rt_err_t hdmi_fb_close(rt_device_t dev)
rt_size_t
hdmi_fb_read
(
rt_device_t
dev
,
rt_off_t
pos
,
void
*
buf
,
rt_size_t
size
)
{
#ifdef BSP_USING_USPI
char
*
buffer
=
(
char
*
)
buf
;
if
(
keyboard_available
())
{
int
i
=
0
;
int
j
=
0
;
while
(
i
!=
size
)
{
int
ch
=
keyboard_getchar
();
if
(
ch
!=
-
1
)
buffer
[
j
++
]
=
ch
;
i
++
;
}
return
j
;
}
#endif
return
0
;
}
rt_size_t
hdmi_fb_write
(
rt_device_t
dev
,
rt_off_t
pos
,
const
void
*
buffer
,
rt_size_t
size
)
{
fb_print
(
&
_hdmi
.
fb
,
(
char
*
)
buffer
);
#ifdef BSP_USING_HDMI_DISPLAY
rt_device_t
uart
=
rt_device_find
(
"uart1"
);
int
old_flag
=
uart
->
open_flag
;
uart
->
open_flag
|=
RT_DEVICE_FLAG_STREAM
;
rt_device_write
(
uart
,
0
,
buffer
,
size
);
uart
->
open_flag
=
old_flag
;
#endif
return
size
;
}
rt_err_t
hdmi_fb_control
(
rt_device_t
dev
,
int
cmd
,
void
*
args
)
{
struct
rt_hdmi_fb_device
*
lcd
=
LCD_DEVICE
(
dev
);
switch
(
cmd
)
{
case
RTGRAPHIC_CTRL_RECT_UPDATE
:
{
struct
rt_device_rect_info
*
info
=
(
struct
rt_device_rect_info
*
)
args
;
info
=
info
;
}
break
;
case
RTGRAPHIC_CTRL_GET_INFO
:
{
struct
rt_device_graphic_info
*
info
=
(
struct
rt_device_graphic_info
*
)
args
;
RT_ASSERT
(
info
!=
RT_NULL
);
info
->
pixel_format
=
RTGRAPHIC_PIXEL_FORMAT_RGB888
;
info
->
bits_per_pixel
=
LCD_DEPTH
;
info
->
width
=
lcd
->
width
;
info
->
height
=
lcd
->
height
;
info
->
framebuffer
=
lcd
->
fb
;
//(rt_uint8_t *)lcd->fb;
}
break
;
}
return
RT_EOK
;
}
const
static
struct
rt_device_ops
hdmi_fb_ops
=
{
const
static
struct
rt_device_ops
hdmi_fb_ops
=
{
RT_NULL
,
hdmi_fb_open
,
hdmi_fb_close
,
...
...
@@ -347,73 +92,12 @@ const static struct rt_device_ops hdmi_fb_ops = {
hdmi_fb_control
};
static
struct
rt_device_graphic_info
_hdmi_info
;
static
void
hdmi_draw_rect
(
const
char
*
pixel
,
int
x1
,
int
y1
,
int
x2
,
int
y2
)
{
int
i
,
j
;
int
line
;
for
(
j
=
y1
;
j
<=
y2
;
j
++
)
{
line
=
(
j
*
_hdmi
.
fb
.
pitch
)
+
(
x1
*
4
);
for
(
i
=
x1
;
i
<=
x2
;
i
++
)
{
// if bit set, we use white color, otherwise black
*
((
unsigned
int
*
)
(
_hdmi_info
.
framebuffer
+
line
))
=
*
(
unsigned
int
*
)
pixel
;
line
+=
4
;
}
}
}
static
void
hdmi_set_pixel
(
const
char
*
pixel
,
int
x
,
int
y
)
{
*
(
uint32_t
*
)
(
_hdmi
.
fb
.
addr
+
(
y
*
_hdmi
.
fb
.
pitch
+
x
*
4
))
=
*
(
uint32_t
*
)
pixel
;
}
static
void
hdmi_get_pixel
(
char
*
pixel
,
int
x
,
int
y
)
{
uint32_t
ret
=
0
;
ret
=
(
*
(
uint32_t
*
)
(
_hdmi
.
fb
.
addr
+
(
y
*
_hdmi
.
fb
.
pitch
+
x
*
4
))
&
0x00FFFFFF
);
*
pixel
=
ret
;
}
static
void
hdmi_draw_hline
(
const
char
*
pixel
,
int
x1
,
int
x2
,
int
y
)
{
hdmi_draw_rect
(
pixel
,
x1
,
y
,
x2
,
y
);
}
static
void
hdmi_draw_vline
(
const
char
*
pixel
,
int
x
,
int
y1
,
int
y2
)
{
hdmi_draw_rect
(
pixel
,
x
,
y1
,
x
,
y2
);
}
static
void
hdmi_blit_line
(
const
char
*
pixels
,
int
x
,
int
y
,
rt_size_t
size
)
{
int
i
=
0
;
uint32_t
*
pixel_base
=
(
uint32_t
*
)
(
_hdmi
.
fb
.
addr
+
(
y
*
_hdmi
.
fb
.
pitch
+
x
*
4
));
uint32_t
*
colors
=
(
uint32_t
*
)
pixels
;
for
(
i
=
0
;
i
<
size
;
i
++
)
{
pixel_base
[
i
]
=
colors
[
i
];
}
}
static
struct
rt_device_graphic_ops
hdmi_ops
=
{
hdmi_set_pixel
,
hdmi_get_pixel
,
hdmi_draw_hline
,
hdmi_draw_vline
,
hdmi_blit_line
};
rt_err_t
rt_hdmi_fb_device_init
(
struct
rt_hdmi_fb_device
*
hdmi_fb
,
const
char
*
name
)
{
struct
rt_device
*
device
;
RT_ASSERT
(
hdmi_fb
!=
RT_NULL
);
device
=
&
hdmi_fb
->
parent
;
device
->
user_data
=
&
hdmi_ops
;
/* set device type */
device
->
type
=
RT_Device_Class_Graphic
;
...
...
@@ -435,89 +119,68 @@ rt_err_t rt_hdmi_fb_device_init(struct rt_hdmi_fb_device *hdmi_fb, const char *n
return
RT_EOK
;
}
/**
* Show a picture
*/
void
print_fb_info
()
{
rt_kprintf
(
"FrameBuffer Info:
\n
\t
width %x
\t
height %x
\t
depth %x
\t
addr %x
\t
size %x
\t
\n
"
,
fb_info
.
width
,
fb_info
.
height
,
fb_info
.
depth
,
fb_info
.
addr
,
fb_info
.
size
);
rt_kprintf
(
"call mbox:%x,%x,%x,%x,%x
\n
"
,
mbox
[
0
],
mbox
[
1
],
mbox
[
2
],
mbox
[
3
],
mbox
[
4
]);
}
void
hdmi_fb_init
()
int
hdmi_fb_init
(
void
)
{
unsigned
int
*
mbox
=
(
unsigned
int
*
)
MBOX_ADDR
;
mbox
[
0
]
=
35
*
4
;
mbox
[
0
]
=
4
*
35
;
mbox
[
1
]
=
MBOX_REQUEST
;
mbox
[
2
]
=
0x48003
;
//set phy wh
mbox
[
2
]
=
TAG_ALLOCATE_BUFFER
;
//get framebuffer, gets alignment on request
mbox
[
3
]
=
8
;
mbox
[
4
]
=
8
;
mbox
[
5
]
=
640
;
//FrameBufferInfo.width
mbox
[
6
]
=
480
;
//FrameBufferInfo.height
mbox
[
4
]
=
0
;
mbox
[
5
]
=
4096
;
//FrameBufferInfo.pointer
mbox
[
6
]
=
0
;
//FrameBufferInfo.size
mbox
[
7
]
=
0x48004
;
//set virt wh
mbox
[
7
]
=
TAG_SET_PHYS_WIDTH_HEIGHT
;
mbox
[
8
]
=
8
;
mbox
[
9
]
=
8
;
mbox
[
10
]
=
640
;
//FrameBufferInfo.virtual_width
mbox
[
11
]
=
480
;
//FrameBufferInfo.virtual_height
mbox
[
9
]
=
0
;
mbox
[
10
]
=
LCD_WIDTH
;
mbox
[
11
]
=
LCD_HEIGHT
;
mbox
[
12
]
=
0x48009
;
//set virt offset
mbox
[
12
]
=
TAG_SET_VIRT_WIDTH_HEIGHT
;
mbox
[
13
]
=
8
;
mbox
[
14
]
=
8
;
mbox
[
15
]
=
0
;
//FrameBufferInfo.x_offset
mbox
[
16
]
=
0
;
//FrameBufferInfo.y.offset
mbox
[
14
]
=
0
;
mbox
[
15
]
=
LCD_WIDTH
;
mbox
[
16
]
=
LCD_HEIGHT
;
mbox
[
17
]
=
0x48005
;
//set depth
mbox
[
17
]
=
TAG_SET_DEPTH
;
mbox
[
18
]
=
4
;
mbox
[
19
]
=
4
;
mbox
[
20
]
=
32
;
//FrameBufferInfo.depth
mbox
[
19
]
=
0
;
mbox
[
20
]
=
16
;
//FrameBufferInfo.depth RGB 565
mbox
[
21
]
=
0x48006
;
//set pixel order
mbox
[
21
]
=
TAG_SET_PIXEL_ORDER
;
mbox
[
22
]
=
4
;
mbox
[
23
]
=
4
;
mbox
[
24
]
=
1
;
//RGB, not BGR preferably
mbox
[
25
]
=
0x40001
;
//get framebuffer, gets alignment on request
mbox
[
26
]
=
8
;
mbox
[
27
]
=
8
;
mbox
[
28
]
=
4096
;
//FrameBufferInfo.pointer
mbox
[
29
]
=
0
;
//FrameBufferInfo.size
mbox
[
30
]
=
0x40008
;
//get pitch
mbox
[
31
]
=
4
;
mbox
[
32
]
=
4
;
mbox
[
33
]
=
0
;
//FrameBufferInfo.pitch
mbox
[
34
]
=
MBOX_TAG_LAST
;
if
(
mbox_call
(
MBOX_CH_PROP
,
MMU_DISABLE
)
&&
mbox
[
20
]
==
32
&&
mbox
[
28
]
!=
0
)
{
mbox
[
28
]
&=
0x3FFFFFFF
;
_hdmi
.
fb
.
width
=
mbox
[
5
];
_hdmi
.
fb
.
height
=
mbox
[
6
];
_hdmi
.
fb
.
pitch
=
mbox
[
33
];
//_hdmi.fb.addr = (void*)((unsigned long)mbox[28]);
_hdmi
.
fb
.
addr
=
(
rt_uint32_t
)
mbox
[
28
];
_hdmi
.
fb
.
size
=
mbox
[
29
];
_hdmi
.
fb
.
depth
=
32
;
_hdmi
.
fb
.
x
=
0
;
_hdmi
.
fb
.
y
=
0
;
_hdmi
.
fb
.
fore
=
CONSOLE_WHITE
;
_hdmi
.
fb
.
back
=
CONSOLE_BLACK
;
rt_hdmi_fb_device_init
(
&
_hdmi
,
"hdmi"
);
rt_hw_change_mmu_table
(
_hdmi
.
fb
.
addr
,
_hdmi
.
fb
.
size
,
_hdmi
.
fb
.
addr
,
DEVICE_MEM
);
fb_info
.
width
=
_hdmi
.
fb
.
width
;
fb_info
.
height
=
_hdmi
.
fb
.
height
;
fb_info
.
addr
=
_hdmi
.
fb
.
addr
;
fb_info
.
size
=
_hdmi
.
fb
.
size
;
fb_info
.
pitch
=
_hdmi
.
fb
.
pitch
;
fb_info
.
depth
=
_hdmi
.
fb
.
depth
;
_hdmi_info
.
pixel_format
=
RTGRAPHIC_PIXEL_FORMAT_RGB888
;
_hdmi_info
.
bits_per_pixel
=
_hdmi
.
fb
.
depth
;
_hdmi_info
.
width
=
_hdmi
.
fb
.
width
;
_hdmi_info
.
height
=
_hdmi
.
fb
.
height
;
_hdmi_info
.
framebuffer
=
(
rt_uint8_t
*
)
_hdmi
.
fb
.
addr
;
}
mbox
[
23
]
=
0
;
mbox
[
24
]
=
1
;
//RGB, not BGR preferably
mbox
[
25
]
=
TAG_GET_PITCH
;
mbox
[
26
]
=
4
;
mbox
[
27
]
=
0
;
mbox
[
28
]
=
0
;
mbox
[
29
]
=
TAG_SET_VIRT_OFFSET
;
mbox
[
30
]
=
8
;
mbox
[
31
]
=
8
;
mbox
[
32
]
=
0
;
mbox
[
33
]
=
0
;
mbox
[
34
]
=
TAG_END
;
mbox_call
(
MBOX_CH_PROP
,
MMU_DISABLE
);
_hdmi
.
fb
=
(
rt_uint8_t
*
)(
uintptr_t
)(
mbox
[
5
]
&
0x3FFFFFFF
);
_hdmi
.
width
=
LCD_WIDTH
;
_hdmi
.
height
=
LCD_HEIGHT
;
_hdmi
.
depth
=
LCD_DEPTH
;
_hdmi
.
pitch
=
0
;
_hdmi
.
pixel_format
=
RTGRAPHIC_PIXEL_FORMAT_RGB888
;
armv8_map
((
unsigned
long
)
_hdmi
.
fb
,
(
unsigned
long
)
_hdmi
.
fb
,
0x200000
,
MEM_ATTR_MEMORY
);
rt_kprintf
(
"_hdmi.fb is %p
\n
"
,
_hdmi
.
fb
);
rt_hdmi_fb_device_init
(
&
_hdmi
,
"lcd"
);
return
0
;
}
INIT_DEVICE_EXPORT
(
hdmi_fb_init
);
bsp/raspberry-pi/raspi3-64/driver/drv_fb.h
浏览文件 @
3d2b66a8
...
...
@@ -11,50 +11,16 @@
#define __DRV_FB_H__
#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b)))
#define COLOR_BLACK RGB(0, 0, 0)
#define COLOR_GREEN RGB(0, 255, 0)
#define COLOR_CYAN RGB(0, 255, 255)
#define COLOR_RED RGB(255, 0, 0)
#define COLOR_YELLOW RGB(255, 255, 0)
#define COLOR_WHITE RGB(255, 255, 255)
#define CONSOLE_WHITE COLOR_WHITE
#define CONSOLE_BLACK COLOR_BLACK
#define CONSOLE_GREEN COLOR_GREEN
#define CONSOLE_CYAN COLOR_CYAN
#define CONSOLE_RED COLOR_RED
#define CONSOLE_YELLOW COLOR_YELLOW
typedef
struct
struct
rt_hdmi_fb_device
{
struct
rt_device
parent
;
rt_uint32_t
width
;
rt_uint32_t
height
;
rt_uint32_t
vwidth
;
rt_uint32_t
vheight
;
rt_uint32_t
pitch
;
rt_uint32_t
depth
;
rt_uint32_t
fore
;
rt_uint32_t
back
;
rt_uint32_t
x
;
rt_uint32_t
y
;
rt_uint32_t
addr
;
rt_uint32_t
size
;
}
fb_t
;
rt_uint32_t
pitch
;
rt_uint32_t
pixel_format
;
struct
rt_hdmi_fb_device
{
struct
rt_device
parent
;
fb_t
fb
;
rt_uint8_t
*
fb
;
};
fb_t
fb_info
;
void
print_fb_info
();
void
hdmi_fb_init
();
#endif
/* __DRV_FB_H__ */
bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
浏览文件 @
3d2b66a8
...
...
@@ -10,62 +10,8 @@
#include "raspi.h"
#include "drv_gpio.h"
#ifdef BSP_USING_PIN
struct
rpi_pin_index
{
rt_uint8_t
phy_id
;
rt_uint8_t
bcm_id
;
rt_uint8_t
signal_name
;
rt_uint8_t
magic
;
};
//raspi phy id and bcm id
static
struct
rpi_pin_index
phypin_index
[]
=
{
{
0
,
0
,
0
,
0
},
{
1
,
0
,
0
,
0
},
{
2
,
0
,
0
,
0
},
{
3
,
BCM_GPIO_PIN_2
,
RPI_SDA1
,
PIN_MAGIC
},
{
4
,
0
,
0
,
0
},
{
5
,
BCM_GPIO_PIN_3
,
RPI_SCL1
,
PIN_MAGIC
},
{
6
,
0
,
0
,
0
},
{
7
,
BCM_GPIO_PIN_4
,
RPI_GPIO_GCLK
,
PIN_MAGIC
},
{
8
,
BCM_GPIO_PIN_14
,
RPI_TXD0
,
PIN_MAGIC
},
{
9
,
0
,
0
,
0
},
{
10
,
BCM_GPIO_PIN_15
,
RPI_RXD0
,
PIN_MAGIC
},
{
11
,
BCM_GPIO_PIN_17
,
RPI_GPIO_GEN0
,
PIN_MAGIC
},
{
12
,
BCM_GPIO_PIN_18
,
RPI_GPIO_GEN1
,
PIN_MAGIC
},
{
13
,
BCM_GPIO_PIN_27
,
RPI_GPIO_GEN2
,
PIN_MAGIC
},
{
14
,
0
,
0
,
0
},
{
15
,
BCM_GPIO_PIN_22
,
RPI_GPIO_GEN3
,
PIN_MAGIC
},
{
16
,
BCM_GPIO_PIN_23
,
RPI_GPIO_GEN4
,
PIN_MAGIC
},
{
17
,
0
,
0
,
0
},
{
18
,
BCM_GPIO_PIN_24
,
RPI_GPIO_GEN5
,
PIN_MAGIC
},
{
19
,
BCM_GPIO_PIN_10
,
RPI_SPI_MOSI
,
PIN_MAGIC
},
{
20
,
0
,
0
,
0
},
{
21
,
BCM_GPIO_PIN_9
,
RPI_SPI_MISO
,
PIN_MAGIC
},
{
22
,
BCM_GPIO_PIN_25
,
RPI_GPIO_GEN6
,
PIN_MAGIC
},
{
23
,
BCM_GPIO_PIN_11
,
RPI_SPI_SCLK
,
PIN_MAGIC
},
{
24
,
BCM_GPIO_PIN_8
,
RPI_SPI_CE0_N
,
PIN_MAGIC
},
{
25
,
0
,
0
,
0
},
{
26
,
BCM_GPIO_PIN_7
,
RPI_SPI_CE1_N
,
PIN_MAGIC
},
{
27
,
BCM_GPIO_PIN_0
,
RPI_SDA0
,
PIN_MAGIC
},
{
28
,
BCM_GPIO_PIN_1
,
RPI_SCL0
,
PIN_MAGIC
},
{
29
,
BCM_GPIO_PIN_5
,
RPI_CAM_CLK
,
PIN_MAGIC
},
{
30
,
0
,
0
,
0
},
{
31
,
BCM_GPIO_PIN_6
,
RPI_LAN_RUN
,
PIN_MAGIC
},
{
32
,
BCM_GPIO_PIN_12
,
0
,
PIN_MAGIC
},
{
33
,
BCM_GPIO_PIN_13
,
0
,
PIN_MAGIC
},
{
34
,
0
,
0
,
0
},
{
35
,
BCM_GPIO_PIN_19
,
0
,
PIN_MAGIC
},
{
36
,
BCM_GPIO_PIN_16
,
RPI_STATUS_LED_N
,
PIN_MAGIC
},
{
37
,
BCM_GPIO_PIN_26
,
0
,
PIN_MAGIC
},
{
38
,
BCM_GPIO_PIN_20
,
0
,
PIN_MAGIC
},
{
39
,
0
,
0
,
0
},
{
40
,
BCM_GPIO_PIN_21
,
RPI_CAM_GPIO
,
PIN_MAGIC
},
};
#ifdef BSP_USING_PIN
/*
* gpio_int[0] for BANK0 (pins 0-27)
* gpio_int[1] for BANK1 (pins 28-45)
...
...
@@ -73,286 +19,262 @@ static struct rpi_pin_index phypin_index[] =
*/
static
struct
gpio_irq_def
_g_gpio_irq_tbl
[
GPIO_IRQ_NUM
];
int
gpio_set_func
(
enum
gpio_code
code
,
enum
bcm_gpio_pin
pin
,
rt_uint8_t
func
)
void
gpio_set_pud
(
rt_uint8_t
pin
,
rt_uint8_t
pud
)
{
RT_ASSERT
((
GPIO_CODE_PHY
<=
code
)
&&
(
code
<
GPIO_CODE_NUM
));
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_53
));
if
(
func
&
0x8
)
{
rt_kprintf
(
"[line]:%d There is a warning with parameter input"
,
__LINE__
);
return
RT_EINVAL
;
}
rt_uint8_t
num
=
pin
/
32
;
rt_uint8_t
shift
=
pin
%
32
;
BCM283X_GPIO_GPPUD
=
pud
;
DELAY_MICROS
(
10
);
BCM283X_GPIO_GPPUDCLK
(
num
)
=
1
<<
shift
;
DELAY_MICROS
(
10
);
BCM283X_GPIO_GPPUD
=
BCM283X_GPIO_PUD_OFF
;
BCM283X_GPIO_GPPUDCLK
(
num
)
=
0
<<
shift
;
}
switch
(
func
)
{
case
0x00
:
bcm283x_gpio_fsel
(
pin
,
BCM283X_GPIO_FSEL_OUTP
);
break
;
case
0x01
:
bcm283x_gpio_fsel
(
pin
,
BCM283X_GPIO_FSEL_INPT
);
break
;
case
0x02
:
bcm283x_gpio_set_pud
(
pin
,
BCM283X_GPIO_PUD_UP
);
bcm283x_gpio_fsel
(
pin
,
BCM283X_GPIO_FSEL_INPT
);
break
;
case
0x03
:
bcm283x_gpio_set_pud
(
pin
,
BCM283X_GPIO_PUD_DOWN
);
bcm283x_gpio_fsel
(
pin
,
BCM283X_GPIO_FSEL_INPT
);
break
;
case
0x04
:
bcm283x_gpio_set_pud
(
pin
,
BCM283X_GPIO_PUD_OFF
);
bcm283x_gpio_fsel
(
pin
,
BCM283X_GPIO_FSEL_OUTP
);
break
;
}
static
void
gpio_ack_irq
(
int
irq
,
bcm_gpio_pin
pin
)
{
rt_uint32_t
data
;
data
=
IRQ_PEND2
;
data
&=
(
0x0
<<
(
irq
-
32
));
IRQ_PEND2
=
data
;
return
RT_EOK
;
data
=
IRQ_DISABLE2
;
data
|=
(
0x1
<<
(
irq
-
32
));
IRQ_DISABLE2
=
data
;
}
int
gpio_set_value
(
enum
gpio_code
code
,
enum
bcm_gpio_pin
pin
,
rt_uint8_t
value
)
void
gpio_irq_disable
(
rt_uint8_t
index
,
bcm_gpio_pin
pin
)
{
int
irq
=
0
;
rt_uint32_t
reg_value
;
rt_uint8_t
irq_type
;
irq
=
IRQ_GPIO0
+
index
;
RT_ASSERT
((
GPIO_CODE_PHY
<=
code
)
&&
(
code
<
GPIO_CODE_NUM
));
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_53
));
gpio_ack_irq
(
irq
,
pin
);
irq_type
=
_g_gpio_irq_tbl
[
index
].
irq_type
[
pin
];
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
mask
=
1
<<
shift
;
if
(
value
&
0xE
)
switch
(
irq_type
)
{
rt_kprintf
(
"[line]:%d There is a warning with parameter input"
,
__LINE__
);
return
RT_EINVAL
;
case
PIN_IRQ_MODE_RISING
:
reg_value
=
BCM283X_GPIO_GPREN
(
pin
/
32
);
BCM283X_GPIO_GPREN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_LOW
&
mask
);
break
;
case
PIN_IRQ_MODE_FALLING
:
reg_value
=
BCM283X_GPIO_GPFEN
(
pin
/
32
);
BCM283X_GPIO_GPFEN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_LOW
&
mask
);
break
;
case
PIN_IRQ_MODE_RISING_FALLING
:
reg_value
=
BCM283X_GPIO_GPAREN
(
pin
/
32
);
BCM283X_GPIO_GPAREN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_LOW
&
mask
);
reg_value
=
BCM283X_GPIO_GPAFEN
(
pin
/
32
);
BCM283X_GPIO_GPAFEN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_LOW
&
mask
);
break
;
case
PIN_IRQ_MODE_HIGH_LEVEL
:
reg_value
=
BCM283X_GPIO_GPHEN
(
pin
/
32
);
BCM283X_GPIO_GPHEN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_LOW
&
mask
);
break
;
case
PIN_IRQ_MODE_LOW_LEVEL
:
reg_value
=
BCM283X_GPIO_GPLEN
(
pin
/
32
);
BCM283X_GPIO_GPLEN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_LOW
&
mask
);
break
;
}
bcm283x_gpio_write
(
pin
,
value
);
return
RT_EOK
;
}
int
gpio_get_value
(
enum
gpio_code
code
,
enum
bcm_gpio_pin
pin
)
void
gpio_irq_enable
(
rt_uint8_t
index
,
bcm_gpio_pin
pin
)
{
rt_uint8_t
data
;
RT_ASSERT
((
GPIO_CODE_PHY
<=
code
)
&&
(
code
<
GPIO_CODE_NUM
));
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_53
));
rt_uint32_t
offset
;
rt_uint32_t
data
;
data
=
bcm283x_gpio_lev
(
pin
);
return
data
;
}
offset
=
pin
;
if
(
index
==
0
)
offset
=
IRQ_GPIO0
-
32
;
else
if
(
index
==
1
)
offset
=
IRQ_GPIO1
-
32
;
else
offset
=
IRQ_GPIO2
-
32
;
void
gpio_set_irq_callback
(
enum
gpio_code
port
,
enum
bcm_gpio_pin
pin
,
void
(
*
irq_cb
)(
void
*
),
void
*
irq_arg
)
{
RT_ASSERT
((
GPIO_CODE_PHY
<
port
)
&&
(
port
<
GPIO_CODE_NUM
));
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_53
));
data
=
IRQ_ENABLE2
;
data
|=
0x1
<<
offset
;
IRQ_ENABLE2
=
data
;
rt_uint8_t
index
;
if
(
pin
<=
27
)
{
index
=
0
;
}
else
if
(
pin
<=
45
)
{
index
=
1
;
}
else
{
index
=
2
;
}
_g_gpio_irq_tbl
[
index
].
irq_cb
[
pin
]
=
irq_cb
;
_g_gpio_irq_tbl
[
index
].
irq_arg
[
pin
]
=
irq_arg
;
}
void
gpio_set_irq_type
(
enum
gpio_code
port
,
enum
bcm_gpio_pin
pin
,
rt_uint8_t
irq_typ
e
)
static
void
raspi_pin_mode
(
struct
rt_device
*
dev
,
rt_base_t
pin
,
rt_base_t
mod
e
)
{
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_NULL
));
RT_ASSERT
(
!
(
mode
&
0x8
));
RT_ASSERT
((
GPIO_CODE_PHY
<
port
)
&&
(
port
<
GPIO_CODE_NUM
));
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_53
));
rt_uint8_t
index
;
if
(
pin
<=
27
)
{
index
=
0
;
}
else
if
(
pin
<=
45
)
switch
(
mode
)
{
index
=
1
;
}
else
{
index
=
2
;
}
_g_gpio_irq_tbl
[
index
].
irq_type
[
pin
]
=
irq_type
;
switch
(
irq_type
)
{
case
0x00
:
bcm283x_gpio_ren
(
pin
);
case
PIN_MODE_OUTPUT
:
GPIO_FSEL
(
pin
,
BCM283X_GPIO_FSEL_OUTP
);
break
;
case
0x01
:
bcm283x_gpio_fen
(
pin
);
case
PIN_MODE_INPUT
:
GPIO_FSEL
(
pin
,
BCM283X_GPIO_FSEL_INPT
);
break
;
case
0x02
:
bcm283x_gpio_aren
(
pin
);
bcm283x_gpio_afen
(
pin
);
case
PIN_MODE_INPUT_PULLUP
:
gpio_set_pud
(
pin
,
BCM283X_GPIO_PUD_UP
);
GPIO_FSEL
(
pin
,
BCM283X_GPIO_FSEL_INPT
);
break
;
case
0x03
:
bcm283x_gpio_hen
(
pin
);
case
PIN_MODE_INPUT_PULLDOWN
:
gpio_set_pud
(
pin
,
BCM283X_GPIO_PUD_DOWN
);
GPIO_FSEL
(
pin
,
BCM283X_GPIO_FSEL_INPT
);
break
;
case
0x04
:
bcm283x_gpio_len
(
pin
);
case
PIN_MODE_OUTPUT_OD
:
gpio_set_pud
(
pin
,
BCM283X_GPIO_PUD_OFF
);
GPIO_FSEL
(
pin
,
BCM283X_GPIO_FSEL_OUTP
);
break
;
}
}
static
void
gpio_ack_irq
(
int
irq
,
enum
bcm_gpio_pin
pin
)
static
void
raspi_pin_write
(
struct
rt_device
*
dev
,
rt_base_t
pin
,
rt_base_t
value
)
{
rt_uint32_t
data
;
data
=
IRQ_PEND2
;
data
&=
(
0x0
<<
(
irq
-
32
));
IRQ_PEND2
=
data
;
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_NULL
));
RT_ASSERT
(
!
(
value
&
0xE
));
if
(
value
)
BCM283X_GPIO_GPSET
(
pin
/
32
)
|=
(
1
<<
(
pin
%
32
));
else
BCM283X_GPIO_GPCLR
(
pin
/
32
)
|=
(
0
<<
(
pin
%
32
));
data
=
IRQ_DISABLE2
;
data
|=
(
0x1
<<
(
irq
-
32
));
IRQ_DISABLE2
=
data
;
}
void
gpio_irq_disable
(
enum
gpio_code
port
,
enum
bcm_gpio_pin
pin
)
static
int
raspi_pin_read
(
struct
rt_device
*
device
,
rt_base_t
pin
)
{
rt_uint8_t
index
;
int
irq
=
0
;
RT_ASSERT
((
GPIO_CODE_PHY
<
port
)
&&
(
port
<
GPIO_CODE_NUM
));
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_53
));
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_NULL
));
return
(
BCM2835_GPIO_GPLEV
(
pin
/
32
)
&
(
1
<<
(
pin
%
32
)))
?
PIN_HIGH
:
PIN_LOW
;
}
static
rt_err_t
raspi_pin_attach_irq
(
struct
rt_device
*
device
,
rt_int32_t
pin
,
rt_uint32_t
mode
,
void
(
*
hdr
)(
void
*
args
),
void
*
args
)
{
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_NULL
));
rt_uint8_t
index
;
rt_uint32_t
reg_value
;
if
(
pin
<=
27
)
{
index
=
0
;
irq
=
IRQ_GPIO0
;
}
else
if
(
pin
<=
45
){
else
if
(
pin
<=
45
)
index
=
1
;
irq
=
IRQ_GPIO1
;
}
else
{
else
index
=
2
;
irq
=
IRQ_GPIO2
;
}
_g_gpio_irq_tbl
[
index
].
irq_cb
[
pin
]
=
hdr
;
_g_gpio_irq_tbl
[
index
].
irq_arg
[
pin
]
=
args
;
_g_gpio_irq_tbl
[
index
].
irq_type
[
pin
]
=
mode
;
gpio_ack_irq
(
irq
,
pin
);
rt_uint8_t
irq_type
=
_g_gpio_irq_tbl
[
index
].
irq_type
[
pin
];
rt_uint8_t
shift
=
pin
%
32
;
rt_uint32_t
mask
=
1
<<
shift
;
switch
(
irq_typ
e
)
switch
(
mod
e
)
{
case
0x00
:
bcm283x_gpio_clr_ren
(
pin
);
case
PIN_IRQ_MODE_RISING
:
reg_value
=
BCM283X_GPIO_GPREN
(
pin
/
32
);
BCM283X_GPIO_GPREN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_HIGH
&
mask
);
break
;
case
0x01
:
bcm283x_gpio_clr_fen
(
pin
);
case
PIN_IRQ_MODE_FALLING
:
reg_value
=
BCM283X_GPIO_GPFEN
(
pin
/
32
);
BCM283X_GPIO_GPFEN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_HIGH
&
mask
);
break
;
case
0x02
:
bcm283x_gpio_clr_aren
(
pin
);
bcm283x_gpio_clr_afen
(
pin
);
case
PIN_IRQ_MODE_RISING_FALLING
:
reg_value
=
BCM283X_GPIO_GPAREN
(
pin
/
32
);
BCM283X_GPIO_GPAREN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_HIGH
&
mask
);
reg_value
=
BCM283X_GPIO_GPAFEN
(
pin
/
32
);
BCM283X_GPIO_GPAFEN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_HIGH
&
mask
);
break
;
case
0x03
:
bcm283x_gpio_clr_hen
(
pin
);
case
PIN_IRQ_MODE_HIGH_LEVEL
:
reg_value
=
BCM283X_GPIO_GPHEN
(
pin
/
32
);
BCM283X_GPIO_GPHEN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_HIGH
&
mask
);
break
;
case
0x04
:
bcm283x_gpio_clr_len
(
pin
);
case
PIN_IRQ_MODE_LOW_LEVEL
:
reg_value
=
BCM283X_GPIO_GPLEN
(
pin
/
32
);
BCM283X_GPIO_GPLEN
(
pin
/
32
)
=
(
reg_value
&
~
mask
)
|
(
PIN_HIGH
&
mask
);
break
;
}
return
RT_EOK
;
}
void
gpio_clear_irq_callback
(
enum
gpio_code
port
,
enum
bcm_gpio_pin
pin
)
static
rt_err_t
raspi_pin_detach_irq
(
struct
rt_device
*
device
,
rt_int32_t
pin
)
{
rt_uint8_t
index
;
gpio_irq_disable
(
port
,
pin
);
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_NULL
));
rt_uint8_t
index
;
if
(
pin
<=
27
)
{
index
=
0
;
}
else
if
(
pin
<=
45
)
{
index
=
1
;
}
else
{
index
=
2
;
}
gpio_irq_disable
(
index
,
pin
);
_g_gpio_irq_tbl
[
index
].
irq_cb
[
pin
]
=
RT_NULL
;
_g_gpio_irq_tbl
[
index
].
irq_arg
[
pin
]
=
RT_NULL
;
_g_gpio_irq_tbl
[
index
].
irq_type
[
pin
]
=
RT_NULL
;
return
RT_EOK
;
}
void
gpio_irq_enable
(
enum
gpio_code
port
,
enum
bcm_gpio_pin
pin
)
rt_err_t
raspi_pin_irq_enable
(
struct
rt_device
*
device
,
rt_base_t
pin
,
rt_uint32_t
enabled
)
{
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_NULL
));
rt_uint32_t
offset
;
rt_uint32_t
data
;
RT_ASSERT
((
GPIO_CODE_PHY
<
port
)
&&
(
port
<
GPIO_CODE_NUM
));
RT_ASSERT
((
BCM_GPIO_PIN_0
<=
pin
)
&&
(
pin
<
BCM_GPIO_PIN_53
));
offset
=
pin
;
rt_uint8_t
index
;
if
(
pin
<=
27
)
{
offset
=
IRQ_GPIO0
-
32
;
}
index
=
0
;
else
if
(
pin
<=
45
)
{
offset
=
IRQ_GPIO1
-
32
;
}
index
=
1
;
else
{
offset
=
IRQ_GPIO2
-
32
;
}
index
=
2
;
data
=
IRQ_ENABLE2
;
data
|=
0x1
<<
offset
;
IRQ_ENABLE2
=
data
;
if
(
enabled
)
gpio_irq_enable
(
index
,
pin
);
else
gpio_irq_disable
(
index
,
pin
);
return
RT_EOK
;
}
//gpio_int[0] for BANK0 (pins 0-27)
//gpio_int[1] for BANK1 (pins 28-45)
//gpio_int[2] for BANK2 (pins 46-53)
static
void
gpio_irq_handler
(
int
irq
,
void
*
param
)
{
struct
gpio_irq_def
*
irq_def
=
(
struct
gpio_irq_def
*
)
param
;
rt_uint32_t
pin
;
rt_uint32_t
addr
;
rt_uint32_t
value
;
rt_uint32_t
tmpvalue
;
if
(
irq
==
IRQ_GPIO0
)
{
/* 0~27 */
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPEDS0
;
// 0~31
value
=
bcm283x_peri_read
(
addr
);
value
=
BCM283X_GPIO_GPEDS
(
0
);
value
&=
0x0fffffff
;
pin
=
0
;
BCM283X_GPIO_GPEDS
(
0
)
=
0
;
}
else
if
(
irq
==
IRQ_GPIO1
)
{
/* 28-45 */
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPEDS0
;
tmpvalue
=
bcm283x_peri_read
(
addr
);
tmpvalue
=
BCM283X_GPIO_GPEDS
(
0
);
tmpvalue
&=
(
~
0x0fffffff
);
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPEDS1
;
value
=
bcm283x_peri_read
(
addr
);
value
=
BCM283X_GPIO_GPEDS
(
1
);
value
&=
0x3fff
;
value
=
(
value
<<
4
)
|
tmpvalue
;
pin
=
28
;
BCM283X_GPIO_GPEDS
(
0
)
=
0
;
BCM283X_GPIO_GPEDS
(
1
)
=
0
;
}
else
if
(
irq
==
IRQ_GPIO2
)
{
/* 46-53 */
addr
=
BCM283X_GPIO_BASE
+
BCM283X_GPIO_GPEDS1
;
value
=
bcm283x_peri_read
(
addr
);
value
=
BCM283X_GPIO_GPEDS
(
1
);
value
&=
(
~
0x3fff
);
value
&=
0xff600000
;
pin
=
46
;
BCM283X_GPIO_GPEDS
(
1
)
=
0
;
}
bcm283x_peri_write
(
addr
,
0
);
while
(
value
)
{
if
((
value
&
0x1
)
&&
(
irq_def
->
irq_cb
[
pin
]
!=
RT_NULL
))
...
...
@@ -365,90 +287,14 @@ static void gpio_irq_handler(int irq, void *param)
}
}
static
void
pin_mode
(
struct
rt_device
*
dev
,
rt_base_t
pin
,
rt_base_t
mode
)
{
if
((
pin
>
PIN_NUM
(
phypin_index
))
||
(
phypin_index
[
pin
].
magic
!=
PIN_MAGIC
))
{
rt_kprintf
(
"pin:%d value wrongful"
,
pin
);
return
;
}
gpio_set_func
(
GPIO_CODE_BCM
,
phypin_index
[
pin
].
bcm_id
,
mode
);
}
static
void
pin_write
(
struct
rt_device
*
dev
,
rt_base_t
pin
,
rt_base_t
value
)
{
if
((
pin
>
PIN_NUM
(
phypin_index
))
||
(
phypin_index
[
pin
].
magic
!=
PIN_MAGIC
))
{
rt_kprintf
(
"pin:%d value wrongful"
,
pin
);
return
;
}
gpio_set_value
(
GPIO_CODE_BCM
,
phypin_index
[
pin
].
bcm_id
,
value
);
}
static
int
pin_read
(
struct
rt_device
*
device
,
rt_base_t
pin
)
{
if
((
pin
>
PIN_NUM
(
phypin_index
))
||
(
phypin_index
[
pin
].
magic
!=
PIN_MAGIC
))
{
rt_kprintf
(
"pin:%d value wrongful"
,
pin
);
return
0
;
}
return
gpio_get_value
(
GPIO_CODE_BCM
,
phypin_index
[
pin
].
bcm_id
);
}
static
rt_err_t
pin_attach_irq
(
struct
rt_device
*
device
,
rt_int32_t
pin
,
rt_uint32_t
mode
,
void
(
*
hdr
)(
void
*
args
),
void
*
args
)
{
if
((
pin
>
PIN_NUM
(
phypin_index
))
||
(
phypin_index
[
pin
].
magic
!=
PIN_MAGIC
))
{
rt_kprintf
(
"pin:%d value wrongful"
,
pin
);
return
RT_ERROR
;
}
gpio_set_irq_callback
(
GPIO_CODE_BCM
,
phypin_index
[
pin
].
bcm_id
,
hdr
,
args
);
gpio_set_irq_type
(
GPIO_CODE_BCM
,
phypin_index
[
pin
].
bcm_id
,
mode
);
return
RT_EOK
;
}
static
rt_err_t
pin_detach_irq
(
struct
rt_device
*
device
,
rt_int32_t
pin
)
{
if
((
pin
>
PIN_NUM
(
phypin_index
))
||
(
phypin_index
[
pin
].
magic
!=
PIN_MAGIC
))
{
rt_kprintf
(
"pin:%d value wrongful"
,
pin
);
return
RT_ERROR
;
}
gpio_clear_irq_callback
(
GPIO_CODE_BCM
,
phypin_index
[
pin
].
bcm_id
);
return
RT_EOK
;
}
rt_err_t
pin_irq_enable
(
struct
rt_device
*
device
,
rt_base_t
pin
,
rt_uint32_t
enabled
)
{
if
((
pin
>
PIN_NUM
(
phypin_index
))
||
(
phypin_index
[
pin
].
magic
!=
PIN_MAGIC
))
{
rt_kprintf
(
"pin:%d value wrongful"
,
pin
);
return
RT_ERROR
;
}
if
(
enabled
)
gpio_irq_enable
(
GPIO_CODE_BCM
,
phypin_index
[
pin
].
bcm_id
);
else
gpio_irq_disable
(
GPIO_CODE_BCM
,
phypin_index
[
pin
].
bcm_id
);
return
RT_EOK
;
}
static
const
struct
rt_pin_ops
ops
=
{
pin_mode
,
pin_write
,
pin_read
,
pin_attach_irq
,
pin_detach_irq
,
pin_irq_enable
,
raspi_
pin_mode
,
raspi_
pin_write
,
raspi_
pin_read
,
raspi_
pin_attach_irq
,
raspi_
pin_detach_irq
,
raspi_
pin_irq_enable
,
};
#endif
...
...
@@ -456,7 +302,6 @@ int rt_hw_gpio_init(void)
{
#ifdef BSP_USING_PIN
rt_device_pin_register
(
"gpio"
,
&
ops
,
RT_NULL
);
#endif
/* install ISR */
rt_hw_interrupt_install
(
IRQ_GPIO0
,
gpio_irq_handler
,
&
_g_gpio_irq_tbl
[
0
],
"gpio0_irq"
);
...
...
@@ -467,6 +312,7 @@ int rt_hw_gpio_init(void)
rt_hw_interrupt_install
(
IRQ_GPIO2
,
gpio_irq_handler
,
&
_g_gpio_irq_tbl
[
2
],
"gpio2_irq"
);
rt_hw_interrupt_umask
(
IRQ_GPIO2
);
#endif
return
0
;
}
...
...
bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
浏览文件 @
3d2b66a8
...
...
@@ -11,19 +11,20 @@
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <rtdebug.h>
#include <rtdbg.h>
#include "interrupt.h"
#include "bcm283x.h"
#include "raspi.h"
#include "board.h"
#include "interrupt.h"
#define GPIO_IRQ_NUM 3
#define IRQ_GPIO0 49
#define IRQ_GPIO1 50
#define IRQ_GPIO2 51
#define IRQ_GPIO3 52
struct
gpio_irq_def
{
void
*
irq_arg
[
32
];
...
...
bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
浏览文件 @
3d2b66a8
...
...
@@ -8,58 +8,60 @@
* 2019-07-29 zdzn first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "bcm283x.h"
#include "drv_timer.h"
#include
<drivers/hwtimer.h>
#include "
cp15
.h"
#include
"interrupt.h"
#include "
raspi
.h"
static
void
rt_systimer_init
(
rt_hwtimer_t
*
hwtimer
,
rt_uint32_t
state
)
#ifdef BSP_USING_SYSTIMER
static
void
raspi_systimer_init
(
rt_hwtimer_t
*
hwtimer
,
rt_uint32_t
state
)
{
if
(
state
==
0
)
hwtimer
->
ops
->
stop
(
hwtimer
);
}
static
rt_err_t
r
t
_systimer_start
(
rt_hwtimer_t
*
hwtimer
,
rt_uint32_t
cnt
,
rt_hwtimer_mode_t
mode
)
static
rt_err_t
r
aspi
_systimer_start
(
rt_hwtimer_t
*
hwtimer
,
rt_uint32_t
cnt
,
rt_hwtimer_mode_t
mode
)
{
rt_err_t
result
=
RT_EOK
;
rt_systimer_t
*
timer
=
(
rt_systimer_t
*
)
hwtimer
->
parent
.
user_data
;
int
timer_id
=
timer
->
timer_id
;
if
(
mode
==
HWTIMER_MODE_PERIOD
)
timer
->
cnt
=
cnt
;
else
timer
->
cnt
=
0
;
__DSB
();
__sync_synchronize
();
if
(
timer_id
==
1
)
{
rt_hw_interrupt_umask
(
IRQ_SYST
IMER_MATCH_1
);
rt_hw_interrupt_umask
(
IRQ_SYST
EM_TIMER_1
);
STIMER_C1
=
STIMER_CLO
+
cnt
;
}
else
if
(
timer_id
==
3
)
{
rt_hw_interrupt_umask
(
IRQ_SYST
IMER_MATCH_3
);
rt_hw_interrupt_umask
(
IRQ_SYST
EM_TIMER_3
);
STIMER_C3
=
STIMER_CLO
+
cnt
;
}
else
result
=
-
RT_ERROR
;
__DSB
();
__sync_synchronize
();
return
result
;
}
static
void
r
t
_systimer_stop
(
rt_hwtimer_t
*
hwtimer
)
static
void
r
aspi
_systimer_stop
(
rt_hwtimer_t
*
hwtimer
)
{
rt_systimer_t
*
timer
=
(
rt_systimer_t
*
)
hwtimer
->
parent
.
user_data
;
int
timer_id
=
timer
->
timer_id
;
if
(
timer_id
==
1
)
rt_hw_interrupt_mask
(
IRQ_SYST
IMER_MATCH_1
);
rt_hw_interrupt_mask
(
IRQ_SYST
EM_TIMER_1
);
else
if
(
timer_id
==
3
)
rt_hw_interrupt_mask
(
IRQ_SYST
IMER_MATCH_3
);
rt_hw_interrupt_mask
(
IRQ_SYST
EM_TIMER_3
);
}
static
rt_err_t
r
t
_systimer_ctrl
(
rt_hwtimer_t
*
timer
,
rt_uint32_t
cmd
,
void
*
arg
)
static
rt_err_t
r
aspi
_systimer_ctrl
(
rt_hwtimer_t
*
timer
,
rt_uint32_t
cmd
,
void
*
arg
)
{
/* The frequency value is an immutable value. */
if
(
cmd
==
HWTIMER_CTRL_FREQ_SET
)
...
...
@@ -72,23 +74,17 @@ static rt_err_t rt_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg
}
}
const
static
struct
rt_hwtimer_ops
systimer_ops
=
{
rt_systimer_init
,
rt_systimer_start
,
rt_systimer_stop
,
RT_NULL
,
rt_systimer_ctrl
};
void
rt_device_systimer_isr
(
int
vector
,
void
*
param
)
{
rt_hwtimer_t
*
hwtimer
=
(
rt_hwtimer_t
*
)
param
;
rt_systimer_t
*
timer
=
(
rt_systimer_t
*
)
hwtimer
->
parent
.
user_data
;
RT_ASSERT
(
timer
!=
RT_NULL
);
int
timer_id
=
timer
->
timer_id
;
__
DSB
();
__
sync_synchronize
();
if
(
timer_id
==
1
)
{
STIMER_CS
=
0x2
;
...
...
@@ -99,15 +95,29 @@ void rt_device_systimer_isr(int vector, void *param)
STIMER_CS
=
0x8
;
STIMER_C3
=
STIMER_CLO
+
timer
->
cnt
;
}
__DSB
();
__sync_synchronize
();
rt_device_hwtimer_isr
(
hwtimer
);
}
#ifdef RT_USING_SYSTIMER1
static
struct
rt_hwtimer_device
_hwtimer1
;
static
rt_systimer_t
_systimer1
;
#endif
#ifdef RT_USING_SYSTIMER3
static
struct
rt_hwtimer_device
_hwtimer3
;
static
struct
rt_systimer_device
_systimer1
;
static
struct
rt_systimer_device
_systimer3
;
static
rt_systimer_t
_systimer3
;
#endif
const
static
struct
rt_hwtimer_ops
systimer_ops
=
{
raspi_systimer_init
,
raspi_systimer_start
,
raspi_systimer_stop
,
RT_NULL
,
raspi_systimer_ctrl
};
static
const
struct
rt_hwtimer_info
_info
=
{
...
...
@@ -117,15 +127,20 @@ static const struct rt_hwtimer_info _info =
HWTIMER_CNTMODE_UP
/* count mode (inc/dec) */
};
#endif
int
rt_hw_systimer_init
(
void
)
{
#ifdef BSP_USING_SYSTIMER
#ifdef RT_USING_SYSTIMER1
_systimer1
.
timer_id
=
1
;
_hwtimer1
.
ops
=
&
systimer_ops
;
_hwtimer1
.
info
=
&
_info
;
rt_device_hwtimer_register
(
&
_hwtimer1
,
"timer1"
,
&
_systimer1
);
rt_hw_interrupt_install
(
IRQ_SYST
IMER_MATCH
_1
,
rt_device_systimer_isr
,
&
_hwtimer1
,
"systimer1"
);
rt_hw_interrupt_umask
(
IRQ_SYST
IMER_MATCH
_1
);
rt_hw_interrupt_install
(
IRQ_SYST
EM_TIMER
_1
,
rt_device_systimer_isr
,
&
_hwtimer1
,
"systimer1"
);
rt_hw_interrupt_umask
(
IRQ_SYST
EM_TIMER
_1
);
#endif
#ifdef RT_USING_SYSTIMER3
...
...
@@ -133,9 +148,12 @@ int rt_hw_systimer_init(void)
_hwtimer3
.
ops
=
&
systimer_ops
;
_hwtimer3
.
info
=
&
_info
;
rt_device_hwtimer_register
(
&
_hwtimer3
,
"timer3"
,
&
_systimer3
);
rt_hw_interrupt_install
(
IRQ_SYSTIMER_MATCH_3
,
rt_device_systimer_isr
,
&
_hwtimer3
,
"systimer3"
);
rt_hw_interrupt_install
(
IRQ_SYSTEM_TIMER_3
,
rt_device_systimer_isr
,
&
_hwtimer3
,
"systimer3"
);
rt_hw_interrupt_umask
(
IRQ_SYSTEM_TIMER_3
);
#endif
#endif
return
0
;
}
INIT_DEVICE_EXPORT
(
rt_hw_systimer_init
);
bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
浏览文件 @
3d2b66a8
...
...
@@ -12,11 +12,10 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "raspi.h"
#include "board.h"
#include "drv_uart.h"
#include <rtdevice.h>
#define AUX_BASE (0x3F000000 + 0x215000)
struct
hw_uart_device
...
...
@@ -34,20 +33,19 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
if
(
uart
->
hw_base
==
AUX_BASE
)
{
rt_uint32_t
value
;
rt_uint32_t
value
;
/* GPIO function set */
value
=
GPIO_GPFSEL1
;
value
&=
~
(
7
<<
12
);
/* GPIO14 */
value
|=
2
<<
12
;
/* ALT5 */
value
&=
~
(
7
<<
15
);
/* GPIO15 */
value
|=
2
<<
15
;
/* ALT5 */
GPIO_GPFSEL1
=
value
;
/* PullUD disable */
GPIO_GPPUD
=
0
;
GPIO_GPPUDCLK0
=
(
1
<<
14
)
|
(
1
<<
15
);
GPIO_GPPUDCLK0
=
0
;
value
=
BCM283X_GPIO_GPFSEL
(
1
);
value
&=
~
(
7
<<
12
);
/* GPIO14 */
value
|=
2
<<
12
;
/* ALT5 */
value
&=
~
(
7
<<
15
);
/* GPIO15 */
value
|=
2
<<
15
;
/* ALT5 */
BCM283X_GPIO_GPFSEL
(
1
)
=
value
;
BCM283X_GPIO_GPPUD
=
0
;
BCM283X_GPIO_GPPUDCLK
(
0
)
=
(
1
<<
14
)
|
(
1
<<
15
);
BCM283X_GPIO_GPPUDCLK
(
0
)
=
0
;
AUX_ENABLES
(
uart
->
hw_base
)
=
1
;
/* Enable UART1 */
AUX_MU_IER_REG
(
uart
->
hw_base
)
=
0
;
/* Disable interrupt */
...
...
bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c
浏览文件 @
3d2b66a8
...
...
@@ -8,30 +8,14 @@
* 2019-07-29 zdzn first version
*/
#include "drv_wdt.h"
#include "raspi.h"
#ifdef BSP_USING_WDT
#define PM_RSTC 0x1c
#define PM_RSTS 0x20
#define PM_WDOG 0x24
#define PM_PASSWORD 0x5a000000
#define PM_WDOG_TIME_SET 0x000fffff
#define PM_RSTC_WRCFG_CLR 0xffffffcf
#define PM_RSTS_HADWRH_SET 0x00000040
#define PM_RSTC_WRCFG_SET 0x00000030
#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
#define PM_RSTC_RESET 0x00000102
#define PM_RSTS_PARTITION_CLR 0xfffffaaa
#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
#define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
static
struct
raspi_wdt_driver
bcm_wdt
=
{
.
base
=
PER_BASE
,
};
static
struct
raspi_wdt_driver
bcm_wdt
;
void
raspi_watchdog_init
(
rt_uint32_t
time_init
)
{
...
...
@@ -41,21 +25,14 @@ void raspi_watchdog_init(rt_uint32_t time_init)
void
raspi_watchdog_start
()
{
volatile
rt_uint32_t
cur
;
bcm283x_peri_write
(
bcm_wdt
.
base
+
PM_WDOG
,
PM_PASSWORD
|
(
SECS_TO_WDOG_TICKS
(
bcm_wdt
.
timeout
)
&
PM_WDOG_TIME_SET
));
bcm283x_peri_write
(
bcm_wdt
.
base
+
PM_WDOG
,
PM_PASSWORD
|
(
SECS_TO_WDOG_TICKS
(
bcm_wdt
.
timeout
)
&
PM_WDOG_TIME_SET
));
cur
=
bcm283x_peri_read
(
bcm_wdt
.
base
+
PM_RSTC
);
bcm283x_peri_write
(
bcm_wdt
.
base
+
PM_RSTC
,
PM_PASSWORD
|
(
cur
&
PM_RSTC_WRCFG_CLR
)
|
PM_RSTC_WRCFG_FULL_RESET
);
PM_WDOG
=
PM_PASSWORD
|
(
SECS_TO_WDOG_TICKS
(
bcm_wdt
.
timeout
)
&
PM_WDOG_TIME_SET
);
cur
=
PM_RSTC
;
PM_RSTC
=
PM_PASSWORD
|
(
cur
&
PM_RSTC_WRCFG_CLR
)
|
PM_RSTC_WRCFG_FULL_RESET
;
}
void
raspi_watchdog_stop
()
{
bcm283x_peri_write
(
bcm_wdt
.
base
+
PM_RSTC
,
PM_PASSWORD
|
PM_RSTC_RESET
)
;
PM_RSTC
=
PM_PASSWORD
|
PM_RSTC_RESET
;
}
void
raspi_watchdog_clr
()
...
...
@@ -63,7 +40,7 @@ void raspi_watchdog_clr()
bcm_wdt
.
timeout
=
0
;
}
void
raspi_watchdog_set_timeout
(
rt_uint32_t
timeout_us
)
void
raspi_watchdog_set_timeout
(
rt_uint32_t
timeout_us
)
{
bcm_wdt
.
timeout
=
timeout_us
;
}
...
...
@@ -75,7 +52,7 @@ rt_uint64_t raspi_watchdog_get_timeout()
rt_uint64_t
raspi_watchdog_get_timeleft
()
{
rt_uint32_t
ret
=
bcm283x_peri_read
(
bcm_wdt
.
base
+
PM_WDOG
)
;
rt_uint32_t
ret
=
PM_WDOG
;
return
WDOG_TICKS_TO_SECS
(
ret
&
PM_WDOG_TIME_SET
);
}
...
...
@@ -136,5 +113,28 @@ int rt_hw_wdt_init(void)
rt_hw_watchdog_register
(
&
raspi_wdg
,
"wdg"
,
0
,
RT_NULL
);
return
RT_EOK
;
}
INIT_DEVICE_EXPORT
(
rt_hw_wdt_init
);
/**
* Reboot
*/
int
reboot
(
void
)
{
unsigned
int
r
;
rt_kprintf
(
"reboot system...
\n
"
);
rt_thread_mdelay
(
100
);
// trigger a restart by instructing the GPU to boot from partition 0
r
=
PM_RSTS
;
r
&=
~
0xfffffaaa
;
PM_RSTS
=
PM_PASSWORD
|
r
;
// boot from partition 0
PM_WDOG
=
PM_PASSWORD
|
10
;
PM_RSTC
=
PM_PASSWORD
|
PM_RSTC_WRCFG_FULL_RESET
;
while
(
1
);
return
0
;
}
MSH_CMD_EXPORT
(
reboot
,
reboot
system
...);
#endif
/*BSP_USING_WDT */
bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h
浏览文件 @
3d2b66a8
...
...
@@ -11,16 +11,13 @@
#ifndef __DRV_WDT_H__
#define __DRV_WDT_H__
#include <rtdef.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <drivers/watchdog.h>
#include "b
cm283x
.h"
#include "b
oard
.h"
struct
raspi_wdt_driver
{
volatile
rt_uint32_t
base
;
rt_uint32_t
timeout
;
};
...
...
bsp/raspberry-pi/raspi3-64/driver/mbox.c
浏览文件 @
3d2b66a8
...
...
@@ -17,10 +17,6 @@ volatile unsigned int *mbox = (volatile unsigned int *) MBOX_ADDR;
/**
* Make a mailbox call. Returns 0 on failure, non-zero on success
*/
void
init_mbox_mmu_map
(){
rt_hw_change_mmu_table
(
MBOX_ADDR
,
96
,
MBOX_ADDR
,
STRONG_ORDER_MEM
);
}
int
mbox_call
(
unsigned
char
ch
,
int
mmu_enable
)
{
unsigned
int
r
=
(((
MBOX_ADDR
)
&~
0xF
)
|
(
ch
&
0xF
));
...
...
bsp/raspberry-pi/raspi3-64/driver/raspi.h
浏览文件 @
3d2b66a8
...
...
@@ -12,60 +12,160 @@
#ifndef __RASPI_H__
#define __RASPI_H__
#include
"bcm283x.h"
#include
<rthw.h>
#define PIN_MAGIC (0x5A)
#define PIN_NUM(_N) (sizeof(_N) / sizeof(_N[0]))
#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x)))
enum
gpio_code
typedef
enum
{
GPIO_CODE_PHY
=
0
,
GPIO_CODE_BCM
,
GPIO_CODE_WIRING
,
GPIO_CODE_NUM
,
};
BCM_GPIO_PIN_0
=
0
,
BCM_GPIO_PIN_1
,
BCM_GPIO_PIN_2
,
BCM_GPIO_PIN_3
,
BCM_GPIO_PIN_4
,
BCM_GPIO_PIN_5
,
BCM_GPIO_PIN_6
,
BCM_GPIO_PIN_7
,
BCM_GPIO_PIN_8
,
BCM_GPIO_PIN_9
,
BCM_GPIO_PIN_10
,
BCM_GPIO_PIN_11
,
BCM_GPIO_PIN_12
,
BCM_GPIO_PIN_13
,
BCM_GPIO_PIN_14
,
BCM_GPIO_PIN_15
,
BCM_GPIO_PIN_16
,
BCM_GPIO_PIN_17
,
BCM_GPIO_PIN_18
,
BCM_GPIO_PIN_19
,
BCM_GPIO_PIN_20
,
BCM_GPIO_PIN_21
,
BCM_GPIO_PIN_22
,
BCM_GPIO_PIN_23
,
BCM_GPIO_PIN_24
,
BCM_GPIO_PIN_25
,
BCM_GPIO_PIN_26
,
BCM_GPIO_PIN_27
,
BCM_GPIO_PIN_28
,
BCM_GPIO_PIN_29
,
BCM_GPIO_PIN_30
,
BCM_GPIO_PIN_31
,
BCM_GPIO_PIN_32
,
BCM_GPIO_PIN_33
,
BCM_GPIO_PIN_34
,
BCM_GPIO_PIN_35
,
BCM_GPIO_PIN_36
,
BCM_GPIO_PIN_37
,
BCM_GPIO_PIN_38
,
BCM_GPIO_PIN_39
,
BCM_GPIO_PIN_40
,
BCM_GPIO_PIN_41
,
BCM_GPIO_PIN_42
,
BCM_GPIO_PIN_43
,
BCM_GPIO_PIN_44
,
BCM_GPIO_PIN_45
,
BCM_GPIO_PIN_46
,
BCM_GPIO_PIN_47
,
BCM_GPIO_PIN_48
,
BCM_GPIO_PIN_49
,
BCM_GPIO_PIN_50
,
BCM_GPIO_PIN_51
,
BCM_GPIO_PIN_52
,
BCM_GPIO_PIN_53
,
BCM_GPIO_PIN_NULL
,
}
bcm_gpio_pin
;
enum
rpi_pin_name
typedef
enum
{
RPI_SDA0
=
0
,
RPI_SCL0
,
RPI_SDA1
,
RPI_SCL1
,
RPI_GPIO_GCLK
,
RPI_CAM_CLK
,
RPI_LAN_RUN
,
RPI_SPI_CE1_N
,
RPI_SPI_CE0_N
,
RPI_SPI_MISO
,
RPI_SPI_MOSI
,
RPI_SPI_SCLK
,
RPI_TXD0
,
RPI_RXD0
,
RPI_STATUS_LED_N
,
RPI_GPIO_GEN0
,
RPI_GPIO_GEN1
,
RPI_CAM_GPIO
,
RPI_GPIO_GEN3
,
RPI_GPIO_GEN4
,
RPI_GPIO_GEN5
,
RPI_GPIO_GEN6
,
RPI_GPIO_GEN2
,
RPI_GPIO_GEN7
,
RPI_GPIO_GEN8
,
RPI_GPIO_GEN9
,
RPI_GPIO_GEN10
,
RPI_PWM0_OUT
,
RPI_PWM1_OUT
,
RPI_HDMI_HPD_P
,
RPI_SD_CARD_DET
,
RPI_SD_CLK_R
,
RPI_SD_CMD_R
,
RPI_SD_DATA0_R
,
RPI_SD_DATA1_R
,
RPI_SD_DATA2_R
,
RPI_SD_DATA3_R
,
RPI_GPIO_PIN_NUM
,
};
BCM283X_GPIO_FSEL_INPT
=
0x00
,
/*!< Input 0b000 */
BCM283X_GPIO_FSEL_OUTP
=
0x01
,
/*!< Output 0b001 */
BCM283X_GPIO_FSEL_ALT0
=
0x04
,
/*!< Alternate function 0 0b100 */
BCM283X_GPIO_FSEL_ALT1
=
0x05
,
/*!< Alternate function 1 0b101 */
BCM283X_GPIO_FSEL_ALT2
=
0x06
,
/*!< Alternate function 2 0b110, */
BCM283X_GPIO_FSEL_ALT3
=
0x07
,
/*!< Alternate function 3 0b111 */
BCM283X_GPIO_FSEL_ALT4
=
0x03
,
/*!< Alternate function 4 0b011 */
BCM283X_GPIO_FSEL_ALT5
=
0x02
,
/*!< Alternate function 5 0b010 */
BCM283X_GPIO_FSEL_MASK
=
0x07
/*!< Function select bits mask 0b111 */
}
gpio_function_select
;
typedef
enum
{
BCM283X_GPIO_PUD_OFF
=
0x00
,
/*!< Off ? disable pull-up/down 0b00 */
BCM283X_GPIO_PUD_DOWN
=
0x01
,
/*!< Enable Pull Down control 0b01 */
BCM283X_GPIO_PUD_UP
=
0x02
/*!< Enable Pull Up control 0b10 */
}
gpio_pud_mode
;
#define BCM283X_CORE_CLK_HZ 250000000
/* 50 MHz */
/* Base Address */
#define PER_BASE (0x3F000000)
#define PER_BASE_40000000 (0x40000000)
//#define BCM283X_PERI_BASE (0x3F000000)
//#define BCM283X_PER_BASE_40000000 (0x40000000)
/* Base Address Registers Offset */
#define ST_BASE_OFFSET (0x003000)
#define GPIO_PAD_OFFSET (0x100000)
#define CLOCK_BASE_OFFSET (0x101000)
#define GPIO_BASE_OFFSET (0x200000)
#define SPI0_BASE_OFFSET (0x204000)
#define BSC0_BASE_OFFSET (0x205000)
#define GPIO_PWM_OFFSET (0x20C000)
#define AUX_BASE_OFFSET (0x215000)
#define SPI1_BASE_OFFSET (0x215080)
#define SPI2_BASE_OFFSET (0x2150C0)
#define BSC1_BASE_OFFSET (0x804000)
#define BSC2_BASE_OFFSET (0x805000)
/* IRQ */
#define IRQ_SYSTEM_TIMER_0 0
#define IRQ_SYSTEM_TIMER_1 1
#define IRQ_SYSTEM_TIMER_2 2
#define IRQ_SYSTEM_TIMER_3 3
#define IRQ_USB 9
#define IRQ_AUX 29
#define IRQ_PCM 55
#define IRQ_ARM_TIMER 64
#define IRQ_ARM_MAILBOX 65
/* Interrupt Controler */
#define IRQ_BASE (PER_BASE + 0xB200)
#define IRQ_PEND_BASIC __REG32(IRQ_BASE + 0x0000)
#define IRQ_PEND1 __REG32(IRQ_BASE + 0x0004)
#define IRQ_PEND2 __REG32(IRQ_BASE + 0x0008)
#define IRQ_FIQ_CONTROL __REG32(IRQ_BASE + 0x000C)
#define IRQ_ENABLE1 __REG32(IRQ_BASE + 0x0010)
#define IRQ_ENABLE2 __REG32(IRQ_BASE + 0x0014)
#define IRQ_ENABLE_BASIC __REG32(IRQ_BASE + 0x0018)
#define IRQ_DISABLE1 __REG32(IRQ_BASE + 0x001C)
#define IRQ_DISABLE2 __REG32(IRQ_BASE + 0x0020)
#define IRQ_DISABLE_BASIC __REG32(IRQ_BASE + 0x0024)
/* Defines for WDT*/
#define PM_BASE (PER_BASE + GPIO_PAD_OFFSET)
#define PM_RSTC __REG32(PM_BASE + 0x001C)
#define PM_RSTS __REG32(PM_BASE + 0x0020)
#define PM_WDOG __REG32(PM_BASE + 0x0024)
#define PM_PASSWORD 0x5a000000
#define PM_WDOG_TIME_SET 0x000fffff
#define PM_RSTC_WRCFG_CLR 0xffffffcf
#define PM_RSTS_HADWRH_SET 0x00000040
#define PM_RSTC_WRCFG_SET 0x00000030
#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
#define PM_RSTC_RESET 0x00000102
#define PM_RSTS_PARTITION_CLR 0xfffffaaa
/* Defines for System Timer */
#define STIMER_BASE (PER_BASE + ST_BASE_OFFSET)
#define STIMER_CS __REG32(STIMER_BASE + 0x0000)
#define STIMER_CLO __REG32(STIMER_BASE + 0x0004)
#define STIMER_CHI __REG32(STIMER_BASE + 0x0008)
#define STIMER_C0 __REG32(STIMER_BASE + 0x000C)
#define STIMER_C1 __REG32(STIMER_BASE + 0x0010)
#define STIMER_C2 __REG32(STIMER_BASE + 0x0014)
#define STIMER_C3 __REG32(STIMER_BASE + 0x0018)
#define DELAY_MICROS(micros) \
do{ \
...
...
@@ -73,4 +173,273 @@ enum rpi_pin_name
while (STIMER_CLO < compare); \
} while (0) \
/* Defines for GPIO */
#define BCM283X_GPIO_BASE (PER_BASE + GPIO_BASE_OFFSET)
#define BCM283X_GPIO_GPFSEL(n) __REG32(BCM283X_GPIO_BASE + 0x0000 + 0x4 * n)
/* GPIO Function Select 32bit R/W */
#define BCM283X_GPIO_GPSET(n) __REG32(BCM283X_GPIO_BASE + 0x001C + 0x4 * n)
/* GPIO Pin Output Set */
#define BCM283X_GPIO_GPCLR(n) __REG32(BCM283X_GPIO_BASE + 0x0028 + 0x4 * n)
/* GPIO Pin Output Clear */
#define BCM2835_GPIO_GPLEV(n) __REG32(BCM283X_GPIO_BASE + 0x0034 + 0x4 * n)
/* GPIO Pin Level */
#define BCM283X_GPIO_GPEDS(n) __REG32(BCM283X_GPIO_BASE + 0x0040 + 0x4 * n)
/* GPIO Pin Event Detect Status */
#define BCM283X_GPIO_GPREN(n) __REG32(BCM283X_GPIO_BASE + 0x004c + 0x4 * n)
/* GPIO Pin Rising Edge Detect Enable */
#define BCM283X_GPIO_GPFEN(n) __REG32(BCM283X_GPIO_BASE + 0x0058 + 0x4 * n)
/* GPIO Pin Falling Edge Detect Enable */
#define BCM283X_GPIO_GPHEN(n) __REG32(BCM283X_GPIO_BASE + 0x0064 + 0x4 * n)
/* GPIO Pin High Detect Enable */
#define BCM283X_GPIO_GPLEN(n) __REG32(BCM283X_GPIO_BASE + 0x0070 + 0x4 * n)
/* GPIO Pin Low Detect Enable */
#define BCM283X_GPIO_GPAREN(n) __REG32(BCM283X_GPIO_BASE + 0x007C + 0x4 * n)
/* GPIO Pin Async. Rising Edge Detect */
#define BCM283X_GPIO_GPAFEN(n) __REG32(BCM283X_GPIO_BASE + 0x0088 + 0x4 * n)
/* GPIO Pin Async. Falling Edge Detect */
#define BCM283X_GPIO_GPPUD __REG32(BCM283X_GPIO_BASE + 0x0094)
/* GPIO Pin Pull-up/down Enable */
#define BCM283X_GPIO_GPPUDCLK(n) __REG32(BCM283X_GPIO_BASE + 0x0098 + 0x4 * n)
/* GPIO Pin Pull-up/down Enable Clock */
#define GPIO_FSEL_NUM(pin) (pin/10)
#define GPIO_FSEL_SHIFT(pin) ((pin%10)*3)
#define GPIO_FSEL(pin, mode) \
do{ \
__sync_synchronize(); \
BCM283X_GPIO_GPFSEL(GPIO_FSEL_NUM(pin)) |= ((mode & BCM283X_GPIO_FSEL_MASK) << GPIO_FSEL_SHIFT(pin)); \
} while (0) \
/* Defines for I2C */
#define BCM283X_BSC0_BASE (PER_BASE + BSC0_BASE_OFFSET) //for i2c0
#define BCM283X_BSC1_BASE (PER_BASE + BSC1_BASE_OFFSET) //for i2c1
#define BCM283X_BSC2_BASE (PER_BASE + BSC2_BASE_OFFSET) //for hdmi i2c not use
#define BCM283X_BSC_C(BASE) __REG32(BASE + 0x0000)
/* BSC Master Control */
#define BCM283X_BSC_S(BASE) __REG32(BASE + 0x0004)
/* BSC Master Status */
#define BCM283X_BSC_DLEN(BASE) __REG32(BASE + 0x0008)
/* BSC Master Data Length */
#define BCM283X_BSC_A(BASE) __REG32(BASE + 0x000c)
/* BSC Master Slave Address */
#define BCM283X_BSC_FIFO(BASE) __REG32(BASE + 0x0010)
/* BSC Master Data FIFO */
#define BCM283X_BSC_DIV(BASE) __REG32(BASE + 0x0014)
/* BSC Master Clock Divider */
#define BCM283X_BSC_DEL(BASE) __REG32(BASE + 0x0018)
/* BSC Master Data Delay */
#define BCM283X_BSC_CLKT(BASE) __REG32(BASE + 0x001c)
/* BSC Master Clock Stretch Timeout */
/* Register masks for C Register */
#define BSC_C_I2CEN 0x00008000
/* I2C Enable, 0 = disabled, 1 = enabled */
#define BSC_C_INTR 0x00000400
/* Interrupt on RX */
#define BSC_C_INTT 0x00000200
/* Interrupt on TX */
#define BSC_C_INTD 0x00000100
/* Interrupt on DONE */
#define BSC_C_ST 0x00000080
/* Start transfer, 1 = Start a new transfer */
#define BSC_C_CLEAR_1 0x00000020
/* Clear FIFO Clear */
#define BSC_C_CLEAR_2 0x00000010
/* Clear FIFO Clear */
#define BSC_C_READ 0x00000001
/* Read transfer */
/* Register masks for S Register */
#define BSC_S_CLKT 0x00000200
/* Clock stretch timeout */
#define BSC_S_ERR 0x00000100
/* ACK error */
#define BSC_S_RXF 0x00000080
/* RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
#define BSC_S_TXE 0x00000040
/* TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
#define BSC_S_RXD 0x00000020
/* RXD FIFO contains data */
#define BSC_S_TXD 0x00000010
/* TXD FIFO can accept data */
#define BSC_S_RXR 0x00000008
/* RXR FIFO needs reading (full) */
#define BSC_S_TXW 0x00000004
/* TXW FIFO needs writing (full) */
#define BSC_S_DONE 0x00000002
/* Transfer DONE */
#define BSC_S_TA 0x00000001
/* Transfer Active */
#define BSC_FIFO_SIZE (16)
/* BSC FIFO size */
/* Defines for SPI */
#define BCM283X_SPI0_BASE (PER_BASE + SPI0_BASE_OFFSET)
#define BCM283X_SPI1_BASE (PER_BASE + SPI1_BASE_OFFSET)
#define BCM283X_SPI2_BASE (PER_BASE + SPI2_BASE_OFFSET)
#define BCM283X_SPI0_CS(BASE) __REG32(BASE + 0x0000)
/* SPI Master Control and Status */
#define BCM283X_SPI0_FIFO(BASE) __REG32(BASE + 0x0004)
/* SPI Master TX and RX FIFOs */
#define BCM283X_SPI0_CLK(BASE) __REG32(BASE + 0x0008)
/* SPI Master Clock Divider */
#define BCM283X_SPI0_DLEN(BASE) __REG32(BASE + 0x000c)
/* SPI Master Data Length */
#define BCM283X_SPI0_LTOH(BASE) __REG32(BASE + 0x0010)
/* SPI LOSSI mode TOH */
#define BCM283X_SPI0_DC(BASE) __REG32(BASE + 0x0014)
/* SPI DMA DREQ Controls */
/* Register masks for SPI0_CS */
#define BCM283X_SPI0_CS_LEN_LONG 0x02000000
/* Enable Long data word in Lossi mode if DMA_LEN is set */
#define BCM283X_SPI0_CS_DMA_LEN 0x01000000
/* Enable DMA mode in Lossi mode */
#define BCM283X_SPI0_CS_CSPOL2 0x00800000
/* Chip Select 2 Polarity */
#define BCM283X_SPI0_CS_CSPOL1 0x00400000
/* Chip Select 1 Polarity */
#define BCM283X_SPI0_CS_CSPOL0 0x00200000
/* Chip Select 0 Polarity */
#define BCM283X_SPI0_CS_RXF 0x00100000
/* RXF - RX FIFO Full */
#define BCM283X_SPI0_CS_RXR 0x00080000
/* RXR RX FIFO needs Reading (full) */
#define BCM283X_SPI0_CS_TXD 0x00040000
/* TXD TX FIFO can accept Data */
#define BCM283X_SPI0_CS_RXD 0x00020000
/* RXD RX FIFO contains Data */
#define BCM283X_SPI0_CS_DONE 0x00010000
/* Done transfer Done */
#define BCM283X_SPI0_CS_TE_EN 0x00008000
/* Unused */
#define BCM283X_SPI0_CS_LMONO 0x00004000
/* Unused */
#define BCM283X_SPI0_CS_LEN 0x00002000
/* LEN LoSSI enable */
#define BCM283X_SPI0_CS_REN 0x00001000
/* REN Read Enable */
#define BCM283X_SPI0_CS_ADCS 0x00000800
/* ADCS Automatically Deassert Chip Select */
#define BCM283X_SPI0_CS_INTR 0x00000400
/* INTR Interrupt on RXR */
#define BCM283X_SPI0_CS_INTD 0x00000200
/* INTD Interrupt on Done */
#define BCM283X_SPI0_CS_DMAEN 0x00000100
/* DMAEN DMA Enable */
#define BCM283X_SPI0_CS_TA 0x00000080
/* Transfer Active */
#define BCM283X_SPI0_CS_CSPOL 0x00000040
/* Chip Select Polarity */
#define BCM283X_SPI0_CS_CLEAR 0x00000030
/* Clear FIFO Clear RX and TX */
#define BCM283X_SPI0_CS_CLEAR_RX 0x00000020
/* Clear FIFO Clear RX */
#define BCM283X_SPI0_CS_CLEAR_TX 0x00000010
/* Clear FIFO Clear TX */
#define BCM283X_SPI0_CS_CPOL 0x00000008
/* Clock Polarity */
#define BCM283X_SPI0_CS_CPHA 0x00000004
/* Clock Phase */
#define BCM283X_SPI0_CS_CS 0x00000003
/* Chip Select */
/* ARM Timer */
#define ARM_TIMER_BASE (PER_BASE + 0xB000)
#define ARM_TIMER_LOAD __REG32(ARM_TIMER_BASE + 0x400)
#define ARM_TIMER_VALUE __REG32(ARM_TIMER_BASE + 0x404)
#define ARM_TIMER_CTRL __REG32(ARM_TIMER_BASE + 0x408)
#define ARM_TIMER_IRQCLR __REG32(ARM_TIMER_BASE + 0x40C)
#define ARM_TIMER_RAWIRQ __REG32(ARM_TIMER_BASE + 0x410)
#define ARM_TIMER_MASKIRQ __REG32(ARM_TIMER_BASE + 0x414)
#define ARM_TIMER_RELOAD __REG32(ARM_TIMER_BASE + 0x418)
#define ARM_TIMER_PREDIV __REG32(ARM_TIMER_BASE + 0x41C)
#define ARM_TIMER_CNTR __REG32(ARM_TIMER_BASE + 0x420)
/* ARM Core Timer */
#define C0TIMER_INTCTL __REG32(PER_BASE_40000000 + 0x40)
/* Core0 timers Interrupt control */
#define C1TIMER_INTCTL __REG32(PER_BASE_40000000 + 0x44)
/* Core1 timers Interrupt control */
#define C2TIMER_INTCTL __REG32(PER_BASE_40000000 + 0x48)
/* Core2 timers Interrupt control */
#define C3TIMER_INTCTL __REG32(PER_BASE_40000000 + 0x4C)
/* Core3 timers Interrupt control */
#define CORETIMER_INTCTL(n) __REG32(PER_BASE_40000000 + 0x40 + n*4)
/* Coren timers Interrupt control */
/*
* Gtimer IRQ flag
*/
#define SYSTEM_TIMER_IRQ_0 (1 << 0)
#define SYSTEM_TIMER_IRQ_1 (1 << 1)
#define SYSTEM_TIMER_IRQ_2 (1 << 2)
#define SYSTEM_TIMER_IRQ_3 (1 << 3)
#define NON_SECURE_TIMER_IRQ (1 << 1)
/* ARM Core Mailbox interrupt */
#define C0MB_INTCTL __REG32(PER_BASE_40000000 + 0x50)
/* Core0 Mailboxes Interrupt control */
#define C1MB_INTCTL __REG32(PER_BASE_40000000 + 0x54)
/* Core1 Mailboxes Interrupt control */
#define C2MB_INTCTL __REG32(PER_BASE_40000000 + 0x58)
/* Core2 Mailboxes Interrupt control */
#define C3MB_INTCTL __REG32(PER_BASE_40000000 + 0x5C)
/* Core3 Mailboxes Interrupt control */
#define COREMB_INTCTL(n) __REG32(PER_BASE_40000000 + 0x50 + 4*n)
/* Coren Mailboxes Interrupt control */
/* ARM Core IRQ/FIQ status */
#define C0_IRQSOURCE __REG32(PER_BASE_40000000 + 0x60)
/* Core0 IRQ Source */
#define C1_IRQSOURCE __REG32(PER_BASE_40000000 + 0x64)
/* Core1 IRQ Source */
#define C2_IRQSOURCE __REG32(PER_BASE_40000000 + 0x68)
/* Core2 IRQ Source */
#define C3_IRQSOURCE __REG32(PER_BASE_40000000 + 0x6C)
/* Core3 IRQ Source */
#define C0_FIQSOURCE __REG32(PER_BASE_40000000 + 0x70)
/* Core0 FIQ Source */
#define C1_FIQSOURCE __REG32(PER_BASE_40000000 + 0x74)
/* Core1 FIQ Source */
#define C2_FIQSOURCE __REG32(PER_BASE_40000000 + 0x78)
/* Core2 FIQ Source */
#define C3_FIQSOURCE __REG32(PER_BASE_40000000 + 0x7C)
/* Core3 FIQ Source */
#define CORE_IRQSOURCE(n) __REG32(PER_BASE_40000000 + 0x60+ n*0x4)
#define CORE_FIQSOURCE(n) __REG32(PER_BASE_40000000 + 0x70+ n*0x4)
#define CORE_MAILBOX3_SET(n) __REG32(PER_BASE_40000000 + 0x8C + n*0x10)
#define CORE_MAILBOX3_CLEAR(n) __REG32(PER_BASE_40000000 + 0xCC + n*0x10)
#define CORE_MAILBOX2_SET(n) __REG32(PER_BASE_40000000 + 0x88 + n*0x10)
#define CORE_MAILBOX2_CLEAR(n) __REG32(PER_BASE_40000000 + 0xC8 + n*0x10)
#define CORE_MAILBOX1_SET(n) __REG32(PER_BASE_40000000 + 0x84 + n*0x10)
#define CORE_MAILBOX1_CLEAR(n) __REG32(PER_BASE_40000000 + 0xC4 + n*0x10)
#define CORE_MAILBOX0_SET(n) __REG32(PER_BASE_40000000 + 0x80 + n*0x10)
#define CORE_MAILBOX0_CLEAR(n) __REG32(PER_BASE_40000000 + 0xC0 + n*0x10)
/* For SMP IPI use MailBox0 */
#define IPI_MAILBOX_SET CORE_MAILBOX0_SET
#define IPI_MAILBOX_CLEAR CORE_MAILBOX0_CLEAR
#define IPI_MAILBOX_INT_MASK (0x01)
enum
spi_bit_order
{
BCM283X_SPI_BIT_ORDER_LSBFIRST
=
0
,
/*!< LSB First */
BCM283X_SPI_BIT_ORDER_MSBFIRST
=
1
/*!< MSB First */
};
enum
spi_mode
{
BCM283X_SPI_MODE0
=
0
,
/*!< CPOL = 0, CPHA = 0 */
BCM283X_SPI_MODE1
=
1
,
/*!< CPOL = 0, CPHA = 1 */
BCM283X_SPI_MODE2
=
2
,
/*!< CPOL = 1, CPHA = 0 */
BCM283X_SPI_MODE3
=
3
/*!< CPOL = 1, CPHA = 1 */
};
enum
spi_chip_select
{
BCM283X_SPI_CS0
=
0
,
/*!< Chip Select 0 */
BCM283X_SPI_CS1
=
1
,
/*!< Chip Select 1 */
BCM283X_SPI_CS2
=
2
,
/*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */
BCM283X_SPI_CS_NONE
=
3
/*!< No CS, control it yourself */
};
enum
spi_clock_divider
{
BCM283X_SPI_CLOCK_DIVIDER_65536
=
0
,
/*!< 65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_32768
=
32768
,
/*!< 32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_16384
=
16384
,
/*!< 16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_8192
=
8192
,
/*!< 8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_4096
=
4096
,
/*!< 4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_2048
=
2048
,
/*!< 2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_1024
=
1024
,
/*!< 1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_512
=
512
,
/*!< 512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_256
=
256
,
/*!< 256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_128
=
128
,
/*!< 128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_64
=
64
,
/*!< 64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_32
=
32
,
/*!< 32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_16
=
16
,
/*!< 16 = 15.625MHz on Rpi2, 25MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_8
=
8
,
/*!< 8 = 31.25MHz on Rpi2, 50MHz on RPI3 */
BCM283X_SPI_CLOCK_DIVIDER_4
=
4
,
/*!< 4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably. */
BCM283X_SPI_CLOCK_DIVIDER_2
=
2
,
/*!< 2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to work reliably.*/
BCM283X_SPI_CLOCK_DIVIDER_1
=
1
/*!< 1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536 */
};
/*redefine for raspi*/
typedef
gpio_function_select
raspi_pin_select
;
typedef
enum
{
RPI_GPIO_P1_01
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_02
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_03
=
BCM_GPIO_PIN_2
,
RPI_GPIO_P1_04
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_05
=
BCM_GPIO_PIN_3
,
RPI_GPIO_P1_06
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_07
=
BCM_GPIO_PIN_4
,
RPI_GPIO_P1_08
=
BCM_GPIO_PIN_14
,
RPI_GPIO_P1_09
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_10
=
BCM_GPIO_PIN_15
,
RPI_GPIO_P1_11
=
BCM_GPIO_PIN_17
,
RPI_GPIO_P1_12
=
BCM_GPIO_PIN_18
,
RPI_GPIO_P1_13
=
BCM_GPIO_PIN_27
,
RPI_GPIO_P1_14
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_15
=
BCM_GPIO_PIN_22
,
RPI_GPIO_P1_16
=
BCM_GPIO_PIN_23
,
RPI_GPIO_P1_17
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_18
=
BCM_GPIO_PIN_24
,
RPI_GPIO_P1_19
=
BCM_GPIO_PIN_10
,
RPI_GPIO_P1_20
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_21
=
BCM_GPIO_PIN_9
,
RPI_GPIO_P1_22
=
BCM_GPIO_PIN_25
,
RPI_GPIO_P1_23
=
BCM_GPIO_PIN_11
,
RPI_GPIO_P1_24
=
BCM_GPIO_PIN_8
,
RPI_GPIO_P1_25
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_26
=
BCM_GPIO_PIN_7
,
RPI_GPIO_P1_27
=
BCM_GPIO_PIN_0
,
RPI_GPIO_P1_28
=
BCM_GPIO_PIN_1
,
RPI_GPIO_P1_29
=
BCM_GPIO_PIN_5
,
RPI_GPIO_P1_30
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_31
=
BCM_GPIO_PIN_6
,
RPI_GPIO_P1_32
=
BCM_GPIO_PIN_12
,
RPI_GPIO_P1_33
=
BCM_GPIO_PIN_13
,
RPI_GPIO_P1_34
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_35
=
BCM_GPIO_PIN_19
,
RPI_GPIO_P1_36
=
BCM_GPIO_PIN_16
,
RPI_GPIO_P1_37
=
BCM_GPIO_PIN_26
,
RPI_GPIO_P1_38
=
BCM_GPIO_PIN_20
,
RPI_GPIO_P1_39
=
BCM_GPIO_PIN_NULL
,
RPI_GPIO_P1_40
=
BCM_GPIO_PIN_21
,
}
raspi_gpio_pin
;
typedef
enum
{
BCM283X_I2C_CLOCK_DIVIDER_2500
=
2500
,
/* 2500 = 10us = 100 kHz */
BCM283X_I2C_CLOCK_DIVIDER_626
=
626
,
/* 622 = 2.504us = 399.3610 kHz */
BCM283X_I2C_CLOCK_DIVIDER_150
=
150
,
/* 150 = 60ns = 1.666 MHz (default at reset) */
BCM283X_I2C_CLOCK_DIVIDER_148
=
148
/* 148 = 59ns = 1.689 MHz */
}
i2c_clock_divider
;
typedef
enum
{
BCM283X_I2C_REASON_OK
=
0x00
,
/* Success */
BCM283X_I2C_REASON_ERROR_NACK
=
0x01
,
/* Received a NACK */
BCM283X_I2C_REASON_ERROR_CLKT
=
0x02
,
/* Received Clock Stretch Timeout */
BCM283X_I2C_REASON_ERROR_DATA
=
0x04
/* Not all data is sent / received */
}
i2c_reason_codes
;
#endif
bsp/raspberry-pi/raspi3-64/link.lds
浏览文件 @
3d2b66a8
...
...
@@ -39,6 +39,8 @@ SECTIONS
*(.glue_7t)
*(.gnu.linkonce.t*)
*(COMMON)
/* section information for finsh shell */
. = ALIGN(16);
__fsymtab_start = .;
...
...
@@ -108,7 +110,7 @@ SECTIONS
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
PROVIDE(__bss_end = .);
}
_end = .;
...
...
bsp/raspberry-pi/raspi3-64/rtconfig.h
浏览文件 @
3d2b66a8
...
...
@@ -101,6 +101,7 @@
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_HWTIMER
#define RT_USING_PIN
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 2048
...
...
@@ -109,6 +110,7 @@
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_SDIO_DEBUG
#define RT_USING_WDT
/* Using USB */
...
...
@@ -193,10 +195,16 @@
#define RT_USING_UART1
#define BSP_USING_PIN
#define BSP_USING_CORETIMER
#define BSP_USING_SYSTIMER
#define RT_USING_SYSTIMER1
#define RT_USING_SYSTIMER3
#define BSP_USING_WDT
#define BSP_USING_SDIO
#define BSP_USING_SDIO0
/* Board Peripheral Drivers */
#define BSP_USING_HDMI
#define BSP_USING_HDMI_DISPLAY
#endif
libcpu/aarch64/cortex-a53/cp15.h
浏览文件 @
3d2b66a8
...
...
@@ -11,7 +11,6 @@
#ifndef __CP15_H__
#define __CP15_H__
#include "bcm283x.h"
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
...
...
libcpu/aarch64/cortex-a53/interrupt.c
浏览文件 @
3d2b66a8
...
...
@@ -12,12 +12,12 @@
*/
#include <rthw.h>
#include <board.h>
#include <rtthread.h>
#include "cp15.h"
#include "armv8.h"
#include <board.h>
#include "interrupt.h"
#define MAX_HANDLERS 72
...
...
libcpu/aarch64/cortex-a53/interrupt.h
浏览文件 @
3d2b66a8
...
...
@@ -14,6 +14,8 @@
#include <rthw.h>
#include <board.h>
#include "raspi.h"
#define INT_IRQ 0x00
#define INT_FIQ 0x01
...
...
libcpu/aarch64/cortex-a53/mmu.h
浏览文件 @
3d2b66a8
...
...
@@ -20,6 +20,8 @@
#define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
#define MEM_ATTR_IO ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000)
void
mmu_init
(
void
);
void
mmu_enable
(
void
);
...
...
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