From 998866dd8faeb3527d2aa1fbb54c4f0f4cd46709 Mon Sep 17 00:00:00 2001 From: lishaohui Date: Thu, 31 Mar 2022 13:14:42 +0800 Subject: [PATCH] up VeriSilicon projects --- projects/VeriSilicon/imports.yml | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/projects/VeriSilicon/imports.yml b/projects/VeriSilicon/imports.yml index 0c4fa19e4..d9c340ef7 100644 --- a/projects/VeriSilicon/imports.yml +++ b/projects/VeriSilicon/imports.yml @@ -7,47 +7,43 @@ group: description: '' mirrorRelease: false topic: '' -- name: 'tensorflow' + - name: 'tflite-vx-delegate' description: '' mirrorRelease: false topic: '' -- name: 'tflite-vx-delegate' + - name: 'acuitylite' description: '' mirrorRelease: false topic: '' -- name: 'acuitylite' + - name: 'tvm' description: '' mirrorRelease: false topic: '' -- name: 'tvm' + - name: 'mlcommons-inference' description: '' mirrorRelease: false topic: '' -- name: 'mlcommons-inference' + - name: 'ffmpeg' description: '' mirrorRelease: false topic: '' -- name: 'ffmpeg' + - name: 'acuity-models' description: '' mirrorRelease: false topic: '' -- name: 'acuity-models' + - name: 'solios-x-device-plugin' description: '' mirrorRelease: false topic: '' -- name: 'solios-x-device-plugin' + - name: 'vpe' description: '' mirrorRelease: false topic: '' -- name: 'vpe' + - name: 'acuity-dataset' description: '' mirrorRelease: false topic: '' -- name: 'acuity-dataset' - description: '' - mirrorRelease: false - topic: '' -- name: 'caffe' + - name: 'caffe' description: '' mirrorRelease: false topic: '' \ No newline at end of file -- GitLab