diff --git a/libraries/ESP32/examples/ResetReason/ResetReason.ino b/libraries/ESP32/examples/ResetReason/ResetReason.ino
index 2a69a9399bd49fa46e2f0b7565c68dbfdf59950c..e6927b2909319e5a72f80b2789dd660042fa3662 100644
--- a/libraries/ESP32/examples/ResetReason/ResetReason.ino
+++ b/libraries/ESP32/examples/ResetReason/ResetReason.ino
@@ -1,10 +1,21 @@
-/* Print last reset reason of ESP32
-*  by Evandro Luis Copercini - 2017
+/*
+*  Print last reset reason of ESP32
+*  =================================
+*
+*  Use either of the methods print_reset_reason
+*  or verbose_print_reset_reason to display the
+*  cause for the last reset of this device.
+*
 *  Public Domain License.
+*
+*  Author:
+*  Evandro Luis Copercini - 2017
 */
 
 #include <rom/rtc.h>
 
+#define uS_TO_S_FACTOR 1000000  /* Conversion factor for micro seconds to seconds */
+
 void print_reset_reason(RESET_REASON reason)
 {
   switch ( reason)
@@ -28,20 +39,109 @@ void print_reset_reason(RESET_REASON reason)
   }
 }
 
+void verbose_print_reset_reason(RESET_REASON reason)
+{
+  switch ( reason)
+  {
+    case 1  : Serial.println ("Vbat power on reset");break;
+    case 3  : Serial.println ("Software reset digital core");break;
+    case 4  : Serial.println ("Legacy watch dog reset digital core");break;
+    case 5  : Serial.println ("Deep Sleep reset digital core");break;
+    case 6  : Serial.println ("Reset by SLC module, reset digital core");break;
+    case 7  : Serial.println ("Timer Group0 Watch dog reset digital core");break;
+    case 8  : Serial.println ("Timer Group1 Watch dog reset digital core");break;
+    case 9  : Serial.println ("RTC Watch dog Reset digital core");break;
+    case 10 : Serial.println ("Instrusion tested to reset CPU");break;
+    case 11 : Serial.println ("Time Group reset CPU");break;
+    case 12 : Serial.println ("Software reset CPU");break;
+    case 13 : Serial.println ("RTC Watch dog Reset CPU");break;
+    case 14 : Serial.println ("for APP CPU, reseted by PRO CPU");break;
+    case 15 : Serial.println ("Reset when the vdd voltage is not stable");break;
+    case 16 : Serial.println ("RTC Watch dog reset digital core and rtc module");break;
+    default : Serial.println ("NO_MEAN");
+  }
+}
+
 void setup() {
   // put your setup code here, to run once:
   Serial.begin(115200);
   delay(2000);
 
-  Serial.println("CPU0 reset reason: ");
+  Serial.println("CPU0 reset reason:");
   print_reset_reason(rtc_get_reset_reason(0));
+  verbose_print_reset_reason(rtc_get_reset_reason(0));
 
-  Serial.println("CPU1 reset reason: ");
+  Serial.println("CPU1 reset reason:");
   print_reset_reason(rtc_get_reset_reason(1));
+  verbose_print_reset_reason(rtc_get_reset_reason(1));
 
+  // Set ESP32 to go to deep sleep to see a variation
+  // in the reset reason. Device will sleep for 5 seconds.
+  esp_deep_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_OFF);
+  Serial.println("Going to sleep");
+  esp_deep_sleep(5 * uS_TO_S_FACTOR);
 }
 
 void loop() {
   // put your main code here, to run repeatedly:
 
-}
\ No newline at end of file
+}
+
+/*
+  Example Serial Log:
+  ====================
+
+rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
+configsip: 0, SPIWP:0x00
+clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
+mode:DIO, clock div:1
+load:0x3fff0008,len:8
+load:0x3fff0010,len:160
+load:0x40078000,len:10632
+load:0x40080000,len:252
+entry 0x40080034
+CPU0 reset reason:
+RTCWDT_RTC_RESET
+RTC Watch dog reset digital core and rtc module
+CPU1 reset reason:
+EXT_CPU_RESET
+for APP CPU, reseted by PRO CPU
+Going to sleep
+ets Jun  8 2016 00:22:57
+
+rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
+configsip: 0, SPIWP:0x00
+clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
+mode:DIO, clock div:1
+load:0x3fff0008,len:8
+load:0x3fff0010,len:160
+load:0x40078000,len:10632
+load:0x40080000,len:252
+entry 0x40080034
+CPU0 reset reason:
+DEEPSLEEP_RESET
+Deep Sleep reset digital core
+CPU1 reset reason:
+EXT_CPU_RESET
+for APP CPU, reseted by PRO CPU
+Going to sleep
+ets Jun  8 2016 00:22:57
+
+rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
+configsip: 0, SPIWP:0x00
+clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
+mode:DIO, clock div:1
+load:0x3fff0008,len:8
+load:0x3fff0010,len:160
+load:0x40078000,len:10632
+load:0x40080000,len:252
+entry 0x40080034
+CPU0 reset reason:
+DEEPSLEEP_RESET
+Deep Sleep reset digital core
+CPU1 reset reason:
+EXT_CPU_RESET
+for APP CPU, reseted by PRO CPU
+Going to sleep
+
+*/