/**************************************************************************//** * @file fmc_reg.h * @version V1.00 * @brief FMC register definition header file * * SPDX-License-Identifier: Apache-2.0 * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. *****************************************************************************/ #ifndef __FMC_REG_H__ #define __FMC_REG_H__ #if defined ( __CC_ARM ) #pragma anon_unions #endif /** @addtogroup REGISTER Control Register @{ */ /** @addtogroup FMC Flash Memory Controller(FMC) Memory Mapped Structure for FMC Controller @{ */ typedef struct { /** * @var FMC_T::ISPCTL * Offset: 0x00 ISP Control Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * |[0] |ISPEN |ISP Enable Bit (Write Protection) * | | |ISP function enable bit. Set this bit to enable ISP function. * | | |0 = ISP function Disabled. * | | |1 = ISP function Enabled. * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. * |[1] |BS |Boot Select (Write Protection) * | | |Set/clear this bit to select next booting from LDROM/APROM, respectively. * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from. * | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened. * | | |0 = Booting from APROM. * | | |1 = Booting from LDROM. * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. * |[2] |SPUEN |SPROM Update Enable Bit (Write Protection) * | | |0 = SPROM cannot be updated. * | | |1 = SPROM can be updated. * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. * |[3] |APUEN |APROM Update Enable Bit (Write Protection) * | | |0 = APROM cannot be updated when the chip runs in APROM. * | | |1 = APROM can be updated when the chip runs in APROM. * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protection) * | | |0 = CONFIG cannot be updated. * | | |1 = CONFIG can be updated. * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. * |[5] |LDUEN |LDROM Update Enable Bit (Write Protection) * | | |LDROM update enable bit. * | | |0 = LDROM cannot be updated. * | | |1 = LDROM can be updated. * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. * |[6] |ISPFF |ISP Fail Flag (Write Protection) * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: * | | |This bit needs to be cleared by writing 1 to it. * | | |(1) APROM writes to itself if APUEN is set to 0. * | | |(2) LDROM writes to itself if LDUEN is set to 0. * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. * | | |(4) SPROM is erased/programmed if SPUEN is set to 0. * | | |(5) SPROM is programmed at SPROM secured mode. * | | |(6) Page Erase command at LOCK mode with ICE connection. * | | |(7) Erase or Program command at brown-out detected. * | | |(8) Destination address is illegal, such as over an available range. * | | |(9) Invalid ISP commands. * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. * @var FMC_T::ISPADDR * Offset: 0x04 ISP Address Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * |[31:0] |ISPADDR |ISP Address * | | |The NuMicro M031 series is equipped with embedded flash. * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation and ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command. * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation. * @var FMC_T::ISPDAT * Offset: 0x08 ISP Data Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * |[31:0] |ISPDAT |ISP Data * | | |Write data to this register before ISP program operation. * | | |Read data from this register after ISP read operation. * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment. * | | |For ISP Read Checksum command, ISPDAT is the checksum result. * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect. * @var FMC_T::ISPCMD * Offset: 0x0C ISP Command Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * |[6:0] |CMD |ISP CMD * | | |ISP command table is shown below: * | | |0x00 = FLASH Read. * | | |0x04 = Read Unique ID.. * | | |0x0B = Read Company ID. * | | |0x0C = Read Device ID. * | | |0x0D = Read CRC32 Checksum. * | | |0x21 = FLASH 32-bit Program. * | | |0x22 = FLASH Page Erase.. * | | |0x2D = Run CRC32 Checksum Calculation. * | | |0x2E = Vector Remap. * | | |The other commands are invalid. * @var FMC_T::ISPTRG * Offset: 0x10 ISP Trigger Control Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * |[0] |ISPGO |ISP Start Trigger (Write Protection) * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. * | | |0 = ISP operation is finished. * | | |1 = ISP is progressed. * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. * @var FMC_T::DFBA * Offset: 0x14 Data Flash Base Address * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * |[31:0] |DFBA |Data Flash Base Address * | | |This register indicates Data Flash start address. It is a read only register. * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1. * | | |This register is valid when DFEN (CONFIG0[0]) =0. * @var FMC_T::FTCTL * Offset: 0x18 Flash Access Time Control Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * |[6:4] |FOM |Frequency Optimization Mode (Write Protect) * | | |The NuMicro Mini58TM series support adjustable flash access timing to optimize the flash access cycles in different working frequency. * | | |0x1 = Frequency <= 24MHz.. * | | |Others = Frequency <= 50MHz. * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. * @var FMC_T::ISPSTS * Offset: 0x40 ISP Status Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * |[0] |ISPBUSY |ISP BUSY (Read Only) * | | |0 = ISP operation is finished. * | | |1 = ISP operation is busy. * |[2:1] |CBS |Boot Selection of CONFIG (Read Only) * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened. * | | |00 = LDROM with IAP mode. * | | |01 = LDROM without IAP mode. * | | |10 = APROM with IAP mode. * | | |11 = APROM without IAP mode. * |[6] |ISPFF |ISP Fail Flag (Write Protection) * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: * | | |(1) APROM writes to itself if APUEN is set to 0. * | | |(2) LDROM writes to itself if LDUEN is set to 0. * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. * | | |(4) SPROM is erased/programmed if SPUEN is set to 0. * | | |(5) SPROM is programmed at SPROM secured mode. * | | |(6) Page Erase command at LOCK mode with ICE connection. * | | |(7) Erase or Program command at brown-out detected. * | | |(8) Destination address is illegal, such as over an available range. * | | |(9) Invalid ISP commands. * |[29:9] |VECMAP |Vector Page Mapping Address (Read Only) * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}, except SPROM. * | | |VECMAP [20:19] = 00 system vector address is mapped to Flash memory. * | | |VECMAP [20:19] = 10 system vector address is mapped to SRAM memory. * | | |VECMAP [18:12] should be 0.All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF} * |[31] |SCODE |Security Code Active Flag * | | |This bit is set to 1 by hardware when detecting SPROM secured code is active at flash initialization, or software writes 1 to this bit to make secured code active; this bit is only cleared by SPROM page erase operation. * | | |0 = SPROM secured code is inactive. * | | |1 = SPROM secured code is active. */ __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ __I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */ __IO uint32_t FTCTL; /*!< [0x0018] Flash Access Time Control Register */ __IO uint32_t ICPCTL; /*!< [0x001C] Flash ICP Enable Control Register */ __I uint32_t RESERVE0[8]; __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ __I uint32_t RESERVE1[15]; __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ __I uint32_t RESERVE2[12]; __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ __I uint32_t RESERVE3[0x3CD]; __I uint32_t VERSION; /*!< [0x0FFC] FMC Version Register */ } FMC_T; /** @addtogroup FMC_CONST FMC Bit Field Definition Constant Definitions for FMC Controller @{ */ #define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ #define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ #define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */ #define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */ #define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ #define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ #define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ #define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ #define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */ #define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */ #define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ #define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ #define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ #define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ #define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */ #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */ #define FMC_FTCTL_FOM_Pos (4) /*!< FMC_T::FTCTL: FOM Position */ #define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) /*!< FMC_T::FTCTL: FOM Mask */ #define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ #define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */ #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ #define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ #define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ #define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ISPFF Position */ #define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) #define FMC_ISPSTS_INTFLAG_Pos (8) /*!< FMC_T::ISPSTS: INTFLAG Position */ #define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */ #define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ #define FMC_ISPSTS_VECMAP_Msk (0x1ffffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ #define FMC_ISPSTS_SCODE_Pos (31) /*!< FMC_T::ISPSTS: SCODE Position */ #define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) /*!< FMC_T::ISPSTS: SCODE Mask */ #define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ #define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ #define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ #define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ #define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ #define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ #define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ #define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ #define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ #define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ #define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ #define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ /**@}*/ /* FMC_CONST */ /**@}*/ /* end of FMC register group */ /**@}*/ /* end of REGISTER group */ #if defined ( __CC_ARM ) #pragma no_anon_unions #endif #endif /* __FMC_REG_H__ */