diff --git a/bsp/tm4c129x-dk/.config b/bsp/tm4c129x-dk/.config deleted file mode 100644 index 65b5b05742d3a26547b924342cafe8049ba541e8..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/.config +++ /dev/null @@ -1,219 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -CONFIG_RT_ALIGN_SIZE=4 -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_DEBUG=y -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_DEBUG_INIT=0 -# CONFIG_RT_DEBUG_THREAD is not set -CONFIG_RT_USING_HOOK=y -CONFIG_IDLE_THREAD_STACK_SIZE=256 -CONFIG_RT_USING_TIMER_SOFT=y -CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_MEMHEAP=y -CONFIG_RT_USING_HEAP=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -# CONFIG_RT_USING_MODULE is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y - -# -# C++ features -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Command shell -# -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_USING_DESCRIPTION=y -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 -# CONFIG_FINSH_USING_AUTH is not set -# CONFIG_FINSH_USING_MSH is not set - -# -# Device virtual file system -# -# CONFIG_RT_USING_DFS is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_USING_SERIAL=y -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_I2C is not set -# CONFIG_RT_USING_PIN is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# POSIX layer and C standard library -# -# CONFIG_RT_USING_LIBC is not set -# CONFIG_RT_USING_PTHREADS is not set - -# -# Network stack -# - -# -# light weight TCP/IP stack -# -CONFIG_RT_USING_LWIP=y -CONFIG_RT_USING_LWIP141=y -# CONFIG_RT_USING_LWIP202 is not set -# CONFIG_RT_LWIP_IGMP is not set -CONFIG_RT_LWIP_ICMP=y -# CONFIG_RT_LWIP_SNMP is not set -CONFIG_RT_LWIP_DNS=y -CONFIG_RT_LWIP_DHCP=y -CONFIG_IP_SOF_BROADCAST=1 -CONFIG_IP_SOF_BROADCAST_RECV=1 -# CONFIG_LWIP_USING_DHCPD is not set - -# -# Static IPv4 Address -# -CONFIG_RT_LWIP_IPADDR="192.168.1.30" -CONFIG_RT_LWIP_GWADDR="192.168.1.1" -CONFIG_RT_LWIP_MSKADDR="255.255.255.0" -CONFIG_RT_LWIP_UDP=y -CONFIG_RT_LWIP_TCP=y -# CONFIG_RT_LWIP_RAW is not set -# CONFIG_RT_LWIP_PPP is not set -# CONFIG_RT_LWIP_PPPOE is not set -# CONFIG_RT_LWIP_PPPOS is not set -CONFIG_RT_LWIP_PBUF_NUM=16 -CONFIG_RT_LWIP_RAW_PCB_NUM=4 -CONFIG_RT_LWIP_UDP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_SEG_NUM=40 -CONFIG_RT_LWIP_TCP_SND_BUF=8196 -CONFIG_RT_LWIP_TCP_WND=8196 -CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 -CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 -CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 -CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 -CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 -# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set -CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 -CONFIG_SO_REUSE=1 -CONFIG_LWIP_SO_RCVTIMEO=1 -CONFIG_LWIP_SO_SNDTIMEO=1 -CONFIG_LWIP_SO_RCVBUF=1 - -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set -# CONFIG_RT_USING_NETUTILS is not set - -# -# RT-Thread UI Engine -# -# CONFIG_PKG_USING_GUIENGINE is not set - -# -# RT-Thread online packages -# - -# -# system packages -# -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_SQLITE is not set - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_EZXML is not set - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_MARVELLWIFI is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set - -# -# language packages -# -# CONFIG_PKG_USING_JERRYSCRIPT is not set - -# -# multimedia packages -# - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYLOGGER is not set - -# -# miscellaneous packages -# -# CONFIG_PKG_USING_HELLO is not set - -# -# BSP_SPECIAL CONFIG -# -CONFIG_RT_USING_UART0=y diff --git a/bsp/tm4c129x-dk/Kconfig b/bsp/tm4c129x-dk/Kconfig deleted file mode 100644 index e6e03d257d1a4d77d9b03660bdc94b6ed0aebfa5..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config $BSP_DIR - string - option env="BSP_ROOT" - default "." - -config $RTT_DIR - string - option env="RTT_ROOT" - default "../.." - -config $PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" - -config RT_USING_UART0 - bool "Using RT_USING_UART0" - default y - diff --git a/bsp/tm4c129x-dk/README.md b/bsp/tm4c129x-dk/README.md deleted file mode 100644 index 8c01a26cf14d4c178c3d8ae4dae4c1057e3031ea..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/README.md +++ /dev/null @@ -1,65 +0,0 @@ -# TM4C129X-Development Board -http://www.ti.com/tool/dk-tm4c129x - -## 1. 简介 - -TM4C129X-DK是TI官方的开发板，此为其中一款开发板，带屏幕，配置更高。 -TI官方提供了详细的SDK支持，含USB，LWIP，甚至图形库。 - -核心板板载主要资源如下： - -| 硬件 | 描述 | -| -- | -- | -|芯片型号| TM4C129XNCZAD | -|CPU| ARM Cortex-M4F | -|主频| 120MHz | -|片内Flash| 1024B | -|片内SRAM| 256KB | - - -## 2. 编译说明 - -TM4C129X-DK板级包目前仅支持MDK5编译器，以下是具体版本信息： - -| IDE/编译器 | 已测试版本 | -| ---------- | ---------------------------- | -| MDK5 | MDK521a | - - -## 3. 烧写及执行 - -TM4C129X-DK本身提供了一个烧录接口，是Stellaris ICDI，keil本身不提供该驱动，需自行下载。 -http://www.ti.com.cn/tool/cn/stellaris_icdi_drivers - -供电方式：使用ICDI接口即可供电 - -### 3.1 运行结果 - -如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： - -```bash - \ | / -- RT - Thread Operating System - / | \ 3.0.3 build Feb 28 2018 - 2006 - 2018 Copyright by rt-thread team -finsh /> - -``` - -## 4. 驱动支持情况及计划 - -| 驱动 | 支持情况 | 备注 | -| ------ | ---- | :------: | - -### 4.1 IO在板级支持包中的映射情况 - -| IO号 | 板级包中的定义 | -| -- | -- | - -## 5. 联系人信息 - -维护人：[zero](https://github.com/Zero-Sky) - -## 6. 参考 - - diff --git a/bsp/tm4c129x-dk/SConscript b/bsp/tm4c129x-dk/SConscript deleted file mode 100644 index fe0ae941ae9a759ae478de901caec1c961e56af8..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -cwd = str(Dir('#')) -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/tm4c129x-dk/SConstruct b/bsp/tm4c129x-dk/SConstruct deleted file mode 100644 index 16877dd5b4a83494dfa80d8bbfb53dff7a27806c..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/SConstruct +++ /dev/null @@ -1,29 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/tm4c129x-dk/applications/SConscript b/bsp/tm4c129x-dk/applications/SConscript deleted file mode 100644 index 01eb940dfb35f92c503a78b0b49a4354590f9f3a..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/applications/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'applications') -src = Glob('*.c') -CPPPATH = [cwd, str(Dir('#'))] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/tm4c129x-dk/applications/application.c b/bsp/tm4c129x-dk/applications/application.c deleted file mode 100644 index 671511c36d5ac7ad902640515d6e895d26674672..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/applications/application.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-07-18 ArdaFu the first version for TM4C129X - */ - -#include - -int main(void) -{ - /* user app entry */ -} - diff --git a/bsp/tm4c129x-dk/applications/board.c b/bsp/tm4c129x-dk/applications/board.c deleted file mode 100644 index 0da547e8674d942548080d2c76c6e798c02892e1..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/applications/board.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first implementation - * 2014-07-18 ArdaFu Port to TM4C129X - */ - -#include -#include -#include "board.h" - - -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" -#include "driverlib/systick.h" -#include "driverlib/fpu.h" -#include "driverlib/rom_map.h" - -#define SYS_CLOCK_DEFAULT 120000000 -uint32_t SystemCoreClock; -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -extern void PendSV_Handler(void); -extern void HardFault_Handler(void); - -/** - * This function will initial LPC40xx board. - */ -void rt_hw_board_init() -{ - //init low level drivers. e.g. cpu uart etc. - rt_components_board_init(); - //redirect RTT stdio to CONSOLE device - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -} - -int rt_hw_cpu_init(void) -{ - MAP_IntMasterDisable(); - IntRegister(FAULT_HARD, HardFault_Handler); - IntRegister(FAULT_PENDSV, PendSV_Handler); - IntRegister(FAULT_SYSTICK, SysTick_Handler); - - // Enable lazy stacking for interrupt handlers. This allows floating-point - // instructions to be used within interrupt handlers, but at the expense of - // extra stack usage. - MAP_FPULazyStackingEnable(); - - // Set the clocking to run directly from the external crystal/oscillator. - // TODO: The SYSCTL_XTAL_ value must be changed to match the value of the - // crystal on your board. - SystemCoreClock = MAP_SysCtlClockFreqSet( - (SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), - SYS_CLOCK_DEFAULT); - - MAP_SysTickDisable(); - MAP_SysTickPeriodSet(SystemCoreClock/ RT_TICK_PER_SECOND - 1); - MAP_SysTickIntEnable(); - MAP_SysTickEnable(); - - return 0; -} -// rt_hw_cpu_init should be run before any other INIT_BOARD_EXPORT -// We use INIT_EXPORT here and set the sequence index to "0.xxxx" -INIT_EXPORT(rt_hw_cpu_init, "0.post"); diff --git a/bsp/tm4c129x-dk/applications/board.h b/bsp/tm4c129x-dk/applications/board.h deleted file mode 100644 index 8103d0b1f198bd148c5cffc44e69f31e6b3e48f2..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/applications/board.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - * 2010-02-04 Magicoe add board.h to LPC176x bsp - * 2014-07-18 ArdaFu port it to TM4C129X bsp - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include "tm4c1294ncpdt.h" -#include -#include -#include - -extern uint32_t SystemCoreClock; -#ifdef __CC_ARM -extern int Image$$RW_IRAM$$ZI$$Limit; -#define HEAP_BEGIN ((void *)&Image$$RW_IRAM$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) -#else -extern int _ebss; -#define HEAP_BEGIN ((void *)&_ebss) -#endif -#define HEAP_END (0x20000000 + 256*1024) - -#define FINSH_DEVICE_NAME RT_CONSOLE_DEVICE_NAME -void rt_hw_board_init(void); - -#endif diff --git a/bsp/tm4c129x-dk/context_rvds.lst b/bsp/tm4c129x-dk/context_rvds.lst deleted file mode 100644 index c112e11f8a96c24b5a1982daea986750f702aa2f..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/context_rvds.lst +++ /dev/null @@ -1,551 +0,0 @@ - - - -ARM Macro Assembler Page 1 - - - 1 00000000 ;/* - 2 00000000 ; * File : context_rvds.S - 3 00000000 ; * This file is part of RT-Thread RTOS - 4 00000000 ; * COPYRIGHT (C) 2009, RT-Thread Development Team - 5 00000000 ; * - 6 00000000 ; * The license and distribution terms for this file may - be - 7 00000000 ; * found in the file LICENSE in this distribution or at - - 8 00000000 ; * http://www.rt-thread.org/license/LICENSE - 9 00000000 ; * - 10 00000000 ; * Change Logs: - 11 00000000 ; * Date Author Notes - 12 00000000 ; * 2009-01-17 Bernard first version. - 13 00000000 ; * 2012-01-01 aozima support context switch l - oad/store FPU register. - 14 00000000 ; * 2013-06-18 aozima add restore MSP feature. - - 15 00000000 ; * 2013-06-23 aozima support lazy stack optim - ized. - 16 00000000 ; */ - 17 00000000 - 18 00000000 ;/** - 19 00000000 ; * @addtogroup cortex-m4 - 20 00000000 ; */ - 21 00000000 ;/*@{*/ - 22 00000000 - 23 00000000 E000ED08 - SCB_VTOR - EQU 0xE000ED08 ; Vector Table Offs - et Register - 24 00000000 E000ED04 - NVIC_INT_CTRL - EQU 0xE000ED04 ; interrupt control - state register - 25 00000000 E000ED20 - NVIC_SYSPRI2 - EQU 0xE000ED20 ; system priority r - egister (2) - 26 00000000 00FF0000 - NVIC_PENDSV_PRI - EQU 0x00FF0000 ; PendSV priority v - alue (lowest) - 27 00000000 10000000 - NVIC_PENDSVSET - EQU 0x10000000 ; value to trigger - PendSV exception - 28 00000000 - 29 00000000 AREA |.text|, CODE, READONLY, ALIGN= -2 - 30 00000000 THUMB - 31 00000000 REQUIRE8 - 32 00000000 PRESERVE8 - 33 00000000 - 34 00000000 IMPORT rt_thread_switch_interrupt_flag - 35 00000000 IMPORT rt_interrupt_from_thread - 36 00000000 IMPORT rt_interrupt_to_thread - 37 00000000 - 38 00000000 ;/* - - - -ARM Macro Assembler Page 2 - - - 39 00000000 ; * rt_base_t rt_hw_interrupt_disable(); - 40 00000000 ; */ - 41 00000000 rt_hw_interrupt_disable - PROC - 42 00000000 EXPORT rt_hw_interrupt_disable - 43 00000000 F3EF 8010 MRS r0, PRIMASK - 44 00000004 B672 CPSID I - 45 00000006 4770 BX LR - 46 00000008 ENDP - 47 00000008 - 48 00000008 ;/* - 49 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level); - 50 00000008 ; */ - 51 00000008 rt_hw_interrupt_enable - PROC - 52 00000008 EXPORT rt_hw_interrupt_enable - 53 00000008 F380 8810 MSR PRIMASK, r0 - 54 0000000C 4770 BX LR - 55 0000000E ENDP - 56 0000000E - 57 0000000E ;/* - 58 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 - to); - 59 0000000E ; * r0 --> from - 60 0000000E ; * r1 --> to - 61 0000000E ; */ - 62 0000000E rt_hw_context_switch_interrupt - 63 0000000E EXPORT rt_hw_context_switch_interrupt - 64 0000000E rt_hw_context_switch - PROC - 65 0000000E EXPORT rt_hw_context_switch - 66 0000000E - 67 0000000E ; set rt_thread_switch_interrupt_flag to 1 - 68 0000000E 4A3A LDR r2, =rt_thread_switch_interrupt -_flag - 69 00000010 6813 LDR r3, [r2] - 70 00000012 2B01 CMP r3, #1 - 71 00000014 D004 BEQ _reswitch - 72 00000016 F04F 0301 MOV r3, #1 - 73 0000001A 6013 STR r3, [r2] - 74 0000001C - 75 0000001C 4A37 LDR r2, =rt_interrupt_from_thread ; - set rt_interrupt_f - rom_thread - 76 0000001E 6010 STR r0, [r2] - 77 00000020 - 78 00000020 _reswitch - 79 00000020 4A37 LDR r2, =rt_interrupt_to_thread ; s - et rt_interrupt_to_ - thread - 80 00000022 6011 STR r1, [r2] - 81 00000024 - 82 00000024 4837 LDR r0, =NVIC_INT_CTRL ; trigger th - e PendSV exception - (causes context swi - tch) - 83 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET - 84 0000002A 6001 STR r1, [r0] - 85 0000002C 4770 BX LR - - - -ARM Macro Assembler Page 3 - - - 86 0000002E ENDP - 87 0000002E - 88 0000002E ; r0 --> switch from thread stack - 89 0000002E ; r1 --> switch to thread stack - 90 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from - ] stack - 91 0000002E PendSV_Handler - PROC - 92 0000002E EXPORT PendSV_Handler - 93 0000002E - 94 0000002E ; disable interrupt to protect context switch - 95 0000002E F3EF 8210 MRS r2, PRIMASK - 96 00000032 B672 CPSID I - 97 00000034 - 98 00000034 ; get rt_thread_switch_interrupt_flag - 99 00000034 4830 LDR r0, =rt_thread_switch_interrupt -_flag - 100 00000036 6801 LDR r1, [r0] - 101 00000038 B351 CBZ r1, pendsv_exit ; pendsv alread - y handled - 102 0000003A - 103 0000003A ; clear rt_thread_switch_interrupt_flag to 0 - 104 0000003A F04F 0100 MOV r1, #0x00 - 105 0000003E 6001 STR r1, [r0] - 106 00000040 - 107 00000040 482E LDR r0, =rt_interrupt_from_thread - 108 00000042 6801 LDR r1, [r0] - 109 00000044 B191 CBZ r1, switch_to_thread ; skip reg - ister save at the f - irst time - 110 00000046 - 111 00000046 F3EF 8109 MRS r1, psp ; get from thread s - tack pointer - 112 0000004A - 113 0000004A IF {FPU} != "SoftVFP" - 114 0000004A F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4] - ) - 115 0000004E BF08 ED21 - 8B10 VSTMFDEQ r1!, {d8 - d15} ; push FPU regi - ster s16~s31 - 116 00000054 ENDIF - 117 00000054 - 118 00000054 E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11 - register - 119 00000058 - 120 00000058 IF {FPU} != "SoftVFP" - 121 00000058 F04F 0400 MOV r4, #0x00 ; flag = 0 - 122 0000005C - 123 0000005C F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4] - ) - 124 00000060 BF08 2401 MOVEQ r4, #0x01 ; flag = 1 - 125 00000064 - 126 00000064 F841 4D04 STMFD r1!, {r4} ; push flag - 127 00000068 ENDIF - 128 00000068 - 129 00000068 6800 LDR r0, [r0] - 130 0000006A 6001 STR r1, [r0] ; update from threa - d stack pointer - 131 0000006C - - - -ARM Macro Assembler Page 4 - - - 132 0000006C switch_to_thread - 133 0000006C 4924 LDR r1, =rt_interrupt_to_thread - 134 0000006E 6809 LDR r1, [r1] - 135 00000070 6809 LDR r1, [r1] ; load thread stack - pointer - 136 00000072 - 137 00000072 IF {FPU} != "SoftVFP" - 138 00000072 C908 LDMFD r1!, {r3} ; pop flag - 139 00000074 ENDIF - 140 00000074 - 141 00000074 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11 - register - 142 00000078 - 143 00000078 IF {FPU} != "SoftVFP" - 144 00000078 2B00 CMP r3, #0 ; if(flag_r3 != 0) - 145 0000007A BF18 ECB1 - 8B10 VLDMFDNE r1!, {d8 - d15} ; pop FPU regis - ter s16~s31 - 146 00000080 ENDIF - 147 00000080 - 148 00000080 F381 8809 MSR psp, r1 ; update stack poin - ter - 149 00000084 - 150 00000084 IF {FPU} != "SoftVFP" - 151 00000084 F04E 0E10 ORR lr, lr, #0x10 ; lr |= (1 << 4) - , clean FPCA. - 152 00000088 2B00 CMP r3, #0 ; if(flag_r3 != 0) - 153 0000008A BF18 F02E - 0E10 BICNE lr, lr, #0x10 ; lr &= ~(1 << 4) - , set FPCA. - 154 00000090 ENDIF - 155 00000090 - 156 00000090 pendsv_exit - 157 00000090 ; restore interrupt - 158 00000090 F382 8810 MSR PRIMASK, r2 - 159 00000094 - 160 00000094 F04E 0E04 ORR lr, lr, #0x04 - 161 00000098 4770 BX lr - 162 0000009A ENDP - 163 0000009A - 164 0000009A ;/* - 165 0000009A ; * void rt_hw_context_switch_to(rt_uint32 to); - 166 0000009A ; * r0 --> to - 167 0000009A ; * this fucntion is used to perform the first thread sw - itch - 168 0000009A ; */ - 169 0000009A rt_hw_context_switch_to - PROC - 170 0000009A EXPORT rt_hw_context_switch_to - 171 0000009A ; set to thread - 172 0000009A 4919 LDR r1, =rt_interrupt_to_thread - 173 0000009C 6008 STR r0, [r1] - 174 0000009E - 175 0000009E IF {FPU} != "SoftVFP" - 176 0000009E ; CLEAR CONTROL.FPCA - 177 0000009E F3EF 8214 MRS r2, CONTROL ; read - 178 000000A2 F022 0204 BIC r2, #0x04 ; modify - 179 000000A6 F382 8814 MSR CONTROL, r2 ; write-back - 180 000000AA ENDIF - - - -ARM Macro Assembler Page 5 - - - 181 000000AA - 182 000000AA ; set from thread to 0 - 183 000000AA 4914 LDR r1, =rt_interrupt_from_thread - 184 000000AC F04F 0000 MOV r0, #0x0 - 185 000000B0 6008 STR r0, [r1] - 186 000000B2 - 187 000000B2 ; set interrupt flag to 1 - 188 000000B2 4911 LDR r1, =rt_thread_switch_interrupt -_flag - 189 000000B4 F04F 0001 MOV r0, #1 - 190 000000B8 6008 STR r0, [r1] - 191 000000BA - 192 000000BA ; set the PendSV exception priority - 193 000000BA 4813 LDR r0, =NVIC_SYSPRI2 - 194 000000BC F44F 017F LDR r1, =NVIC_PENDSV_PRI - 195 000000C0 F8D0 2000 LDR.W r2, [r0,#0x00] ; read - 196 000000C4 EA41 0102 ORR r1,r1,r2 ; modify - 197 000000C8 6001 STR r1, [r0] ; write-back - 198 000000CA - 199 000000CA ; trigger the PendSV exception (causes context switch) - 200 000000CA 480E LDR r0, =NVIC_INT_CTRL - 201 000000CC F04F 5180 LDR r1, =NVIC_PENDSVSET - 202 000000D0 6001 STR r1, [r0] - 203 000000D2 - 204 000000D2 ; restore MSP - 205 000000D2 480E LDR r0, =SCB_VTOR - 206 000000D4 6800 LDR r0, [r0] - 207 000000D6 6800 LDR r0, [r0] - 208 000000D8 F380 8808 MSR msp, r0 - 209 000000DC - 210 000000DC ; enable interrupts at processor level - 211 000000DC B661 CPSIE F - 212 000000DE B662 CPSIE I - 213 000000E0 - 214 000000E0 ; never reach here! - 215 000000E0 ENDP - 216 000000E0 - 217 000000E0 ; compatible with old version - 218 000000E0 rt_hw_interrupt_thread_switch - PROC - 219 000000E0 EXPORT rt_hw_interrupt_thread_switch - 220 000000E0 4770 BX lr - 221 000000E2 ENDP - 222 000000E2 - 223 000000E2 IMPORT rt_hw_hard_fault_exception - 224 000000E2 EXPORT HardFault_Handler - 225 000000E2 HardFault_Handler - PROC - 226 000000E2 - 227 000000E2 ; get current context - 228 000000E2 F3EF 8009 MRS r0, psp ; get fault thread - stack pointer - 229 000000E6 B500 PUSH {lr} - 230 000000E8 F7FF FFFE BL rt_hw_hard_fault_exception - 231 000000EC F85D EB04 POP {lr} - 232 000000F0 - 233 000000F0 F04E 0E04 ORR lr, lr, #0x04 - 234 000000F4 4770 BX lr - 235 000000F6 ENDP - - - -ARM Macro Assembler Page 6 - - - 236 000000F6 - 237 000000F6 00 00 ALIGN 4 - 238 000000F8 - 239 000000F8 END - 00000000 - 00000000 - 00000000 - E000ED04 - E000ED20 - E000ED08 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp --apcs=int -erwork --depend=.\build\context_rvds.d -o.\build\context_rvds.o -IC:\Users\zylw -w\Documents\Study\CodeHub\rt-thread\bsp\tm4c129x-dk\RTE -IC:\Software\Keil\ARM\ -PACK\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C129 -IC:\Software\Keil\ARM\CMSIS\In -clude --predefine="__UVISION_VERSION SETA 521" --predefine="TM4C129XNCZAD SETA -1" --list=.\context_rvds.lst ../../libcpu/arm/cortex-m4/context_rvds.S - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -.text 00000000 - -Symbol: .text - Definitions - At line 29 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - None -Comment: .text unused -HardFault_Handler 000000E2 - -Symbol: HardFault_Handler - Definitions - At line 225 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 224 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: HardFault_Handler used once -PendSV_Handler 0000002E - -Symbol: PendSV_Handler - Definitions - At line 91 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 92 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: PendSV_Handler used once -_reswitch 00000020 - -Symbol: _reswitch - Definitions - At line 78 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 71 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: _reswitch used once -pendsv_exit 00000090 - -Symbol: pendsv_exit - Definitions - At line 156 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 101 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: pendsv_exit used once -rt_hw_context_switch 0000000E - -Symbol: rt_hw_context_switch - Definitions - At line 64 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 65 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_context_switch used once -rt_hw_context_switch_interrupt 0000000E - -Symbol: rt_hw_context_switch_interrupt - Definitions - At line 62 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 63 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_context_switch_interrupt used once -rt_hw_context_switch_to 0000009A - -Symbol: rt_hw_context_switch_to - - - -ARM Macro Assembler Page 2 Alphabetic symbol ordering -Relocatable symbols - - Definitions - At line 169 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 170 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_context_switch_to used once -rt_hw_interrupt_disable 00000000 - -Symbol: rt_hw_interrupt_disable - Definitions - At line 41 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 42 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_interrupt_disable used once -rt_hw_interrupt_enable 00000008 - -Symbol: rt_hw_interrupt_enable - Definitions - At line 51 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 52 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_interrupt_enable used once -rt_hw_interrupt_thread_switch 000000E0 - -Symbol: rt_hw_interrupt_thread_switch - Definitions - At line 218 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 219 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_interrupt_thread_switch used once -switch_to_thread 0000006C - -Symbol: switch_to_thread - Definitions - At line 132 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 109 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: switch_to_thread used once -12 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Absolute symbols - -NVIC_INT_CTRL E000ED04 - -Symbol: NVIC_INT_CTRL - Definitions - At line 24 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 82 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 200 in file ../../libcpu/arm/cortex-m4/context_rvds.S - -NVIC_PENDSVSET 10000000 - -Symbol: NVIC_PENDSVSET - Definitions - At line 27 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 83 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 201 in file ../../libcpu/arm/cortex-m4/context_rvds.S - -NVIC_PENDSV_PRI 00FF0000 - -Symbol: NVIC_PENDSV_PRI - Definitions - At line 26 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 194 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: NVIC_PENDSV_PRI used once -NVIC_SYSPRI2 E000ED20 - -Symbol: NVIC_SYSPRI2 - Definitions - At line 25 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 193 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: NVIC_SYSPRI2 used once -SCB_VTOR E000ED08 - -Symbol: SCB_VTOR - Definitions - At line 23 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 205 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: SCB_VTOR used once -5 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -External symbols - -rt_hw_hard_fault_exception 00000000 - -Symbol: rt_hw_hard_fault_exception - Definitions - At line 223 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 230 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_hard_fault_exception used once -rt_interrupt_from_thread 00000000 - -Symbol: rt_interrupt_from_thread - Definitions - At line 35 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 75 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 107 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 183 in file ../../libcpu/arm/cortex-m4/context_rvds.S - -rt_interrupt_to_thread 00000000 - -Symbol: rt_interrupt_to_thread - Definitions - At line 36 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 79 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 133 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 172 in file ../../libcpu/arm/cortex-m4/context_rvds.S - -rt_thread_switch_interrupt_flag 00000000 - -Symbol: rt_thread_switch_interrupt_flag - Definitions - At line 34 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 68 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 99 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 188 in file ../../libcpu/arm/cortex-m4/context_rvds.S - -4 symbols -356 symbols in table diff --git a/bsp/tm4c129x-dk/drivers/SConscript b/bsp/tm4c129x-dk/drivers/SConscript deleted file mode 100644 index e5f4cd494566242fd5f19e775ccff2a69e43d2ac..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/drivers/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') - -# remove no need file. -if GetDepend('RT_USING_LWIP') == False: - SrcRemove(src, 'drv_emac.c') - -CPPPATH = [cwd] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/tm4c129x-dk/drivers/drv_eth.c b/bsp/tm4c129x-dk/drivers/drv_eth.c deleted file mode 100644 index baa46f1f01447e8e4791540c304a69610ada103e..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/drivers/drv_eth.c +++ /dev/null @@ -1,1444 +0,0 @@ -/* - * File : drv_eth.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-07-25 ArdaFu Port to TM4C129X - */ - -/** - * @file - tivaif.c - * lwIP Ethernet interface for Stellaris LM4F Devices - * - */ - -/** - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICui32AR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/** - * Copyright (c) 2008-2012 Texas Instruments Incorporated - * - * This file is derived from the ``ethernetif.c'' skeleton Ethernet network - * interface driver for lwIP. - * - */ - -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include -#include -#include "lwip/tcpip.h" -#include "netif/etharp.h" -#include "netif/ppp_oe.h" - - -/** - * Sanity Check: This interface driver will NOT work if the following defines - * are incorrect. - * - */ -#if (PBUF_LINK_HLEN != 16) -#error "PBUF_LINK_HLEN must be 16 for this interface driver!" -#endif -#if (ETH_PAD_SIZE != 0) -#error "ETH_PAD_SIZE must be 0 for this interface driver!" -#endif -#if (!SYS_LIGHTWEIGHT_PROT) -#error "SYS_LIGHTWEIGHT_PROT must be enabled for this interface driver!" -#endif - -/** - * Set the physical address of the PHY we will be using if this is not - * specified in lwipopts.h. We assume 0 for the internal PHY. - */ -#ifndef PHY_PHYS_ADDR -#define PHY_PHYS_ADDR 0 -#endif - -#ifndef EMAC_PHY_CONFIG -#define EMAC_PHY_CONFIG (EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | \ - EMAC_PHY_AN_100B_T_FULL_DUPLEX) -#endif - -/** - * If necessary, set the defaui32t number of transmit and receive DMA descriptors - * used by the Ethernet MAC. - * - */ -#ifndef NUM_RX_DESCRIPTORS -#define NUM_RX_DESCRIPTORS 4 -#endif - -#ifndef NUM_TX_DESCRIPTORS -#define NUM_TX_DESCRIPTORS 8 -#endif - -/** - * Setup processing for PTP (IEEE-1588). - * - */ -#if LWIP_PTPD -extern uint32_t g_ui32SysClk; -extern uint32_t g_ui32PTPTickRate; -extern void lwIPHostGetTime(u32_t *time_s, u32_t *time_ns); -#endif - -/** - * Stellaris DriverLib Header Files required for this interface driver. - * - */ -#include -#include -#include "inc/hw_emac.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" - -#include "driverlib/emac.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" -#include "driverlib/flash.h" -#include "driverlib/interrupt.h" - -#include "driverlib/pin_map.h" -#include "driverlib/rom_map.h" -#include "driverlib/gpio.h" - -#include -#include "lwipopts.h" -#include "drv_eth.h" - -/** - * A structure used to keep track of driver state and error counts. - */ -typedef struct { - uint32_t ui32TXCount; - uint32_t ui32TXCopyCount; - uint32_t ui32TXCopyFailCount; - uint32_t ui32TXNoDescCount; - uint32_t ui32TXBufQueuedCount; - uint32_t ui32TXBufFreedCount; - uint32_t ui32RXBufReadCount; - uint32_t ui32RXPacketReadCount; - uint32_t ui32RXPacketErrCount; - uint32_t ui32RXPacketCBErrCount; - uint32_t ui32RXNoBufCount; -} -tDriverStats; - -tDriverStats g_sDriverStats; - -#ifdef DEBUG -/** - * Note: This rather weird construction where we invoke the macro with the - * name of the field minus its Hungarian prefix is a workaround for a problem - * experienced with GCC which does not like concatenating tokens after an - * operator, specifically '.' or '->', in a macro. - */ -#define DRIVER_STATS_INC(x) do{ g_sDriverStats.ui32##x++; } while(0) -#define DRIVER_STATS_DEC(x) do{ g_sDriverStats.ui32##x--; } while(0) -#define DRIVER_STATS_ADD(x, inc) do{ g_sDriverStats.ui32##x += (inc); } while(0) -#define DRIVER_STATS_SUB(x, dec) do{ g_sDriverStats.ui32##x -= (dec); } while(0) -#else -#define DRIVER_STATS_INC(x) -#define DRIVER_STATS_DEC(x) -#define DRIVER_STATS_ADD(x, inc) -#define DRIVER_STATS_SUB(x, dec) -#endif - -/** - * Helper struct holding a DMA descriptor and the pbuf it currently refers - * to. - */ -typedef struct { - tEMACDMADescriptor Desc; - struct pbuf *pBuf; -} tDescriptor; - -typedef struct { - tDescriptor *pDescriptors; - uint32_t ui32NumDescs; - uint32_t ui32Read; - uint32_t ui32Write; -} tDescriptorList; - -/** - * Helper struct to hold private data used to operate your ethernet interface. - * Keeping the ethernet address of the MAC in this struct is not necessary - * as it is already kept in the struct netif. - * But this is only an example, anyway... - */ -typedef struct { - struct eth_addr *ethaddr; - /* Add whatever per-interface state that is needed here. */ - tDescriptorList *pTxDescList; - tDescriptorList *pRxDescList; -} tStellarisIF; - -/** - * Global variable for this interface's private data. Needed to allow - * the interrupt handlers access to this information outside of the - * context of the lwIP netif. - * - */ -tDescriptor g_pTxDescriptors[NUM_TX_DESCRIPTORS]; -tDescriptor g_pRxDescriptors[NUM_RX_DESCRIPTORS]; -tDescriptorList g_TxDescList = { - g_pTxDescriptors, NUM_TX_DESCRIPTORS, 0, 0 -}; -tDescriptorList g_RxDescList = { - g_pRxDescriptors, NUM_RX_DESCRIPTORS, 0, 0 -}; -static tStellarisIF g_StellarisIFData = { - 0, &g_TxDescList, &g_RxDescList -}; - -/** - * Interrupt counters (for debug purposes). - */ -volatile uint32_t g_ui32NormalInts; -volatile uint32_t g_ui32AbnormalInts; - -/** - * A macro which determines whether a pointer is within the SRAM address - * space and, hence, points to a buffer that the Ethernet MAC can directly - * DMA from. - */ -#define PTR_SAFE_FOR_EMAC_DMA(ptr) (((uint32_t)(ptr) >= 0x2000000) && \ - ((uint32_t)(ptr) < 0x20070000)) - - -typedef struct -{ - /* inherit from ethernet device */ - struct eth_device parent; - tStellarisIF* dma_if; - /* for rx_thread async get pbuf */ - rt_mailbox_t rx_pbuf_mb; -} net_device; -typedef net_device* net_device_t; - -static char rx_pbuf_mb_pool[8*4]; -static struct rt_mailbox eth_rx_pbuf_mb; -static net_device eth_dev_entry; -static net_device_t eth_dev = ð_dev_entry; - -/** - * Initialize the transmit and receive DMA descriptor lists. - */ -void -InitDMADescriptors(void) -{ - uint32_t ui32Loop; - - /* Transmit list - mark all descriptors as not owned by the hardware */ - for(ui32Loop = 0; ui32Loop < NUM_TX_DESCRIPTORS; ui32Loop++) - { - g_pTxDescriptors[ui32Loop].pBuf = (struct pbuf *)0; - g_pTxDescriptors[ui32Loop].Desc.ui32Count = 0; - g_pTxDescriptors[ui32Loop].Desc.pvBuffer1 = 0; - g_pTxDescriptors[ui32Loop].Desc.DES3.pLink = - ((ui32Loop == (NUM_TX_DESCRIPTORS - 1)) ? - &g_pTxDescriptors[0].Desc : &g_pTxDescriptors[ui32Loop + 1].Desc); - g_pTxDescriptors[ui32Loop].Desc.ui32CtrlStatus = DES0_TX_CTRL_INTERRUPT | - DES0_TX_CTRL_CHAINED | DES0_TX_CTRL_IP_ALL_CKHSUMS; - - } - - g_TxDescList.ui32Read = 0; - g_TxDescList.ui32Write = 0; - - - /* Receive list - tag each descriptor with a pbuf and set all fields to - * allow packets to be received. - */ - for(ui32Loop = 0; ui32Loop < NUM_RX_DESCRIPTORS; ui32Loop++) - { - g_pRxDescriptors[ui32Loop].pBuf = pbuf_alloc(PBUF_RAW, PBUF_POOL_BUFSIZE, - PBUF_POOL); - g_pRxDescriptors[ui32Loop].Desc.ui32Count = DES1_RX_CTRL_CHAINED; - if(g_pRxDescriptors[ui32Loop].pBuf) - { - /* Set the DMA to write directly into the pbuf payload. */ - g_pRxDescriptors[ui32Loop].Desc.pvBuffer1 = - g_pRxDescriptors[ui32Loop].pBuf->payload; - g_pRxDescriptors[ui32Loop].Desc.ui32Count |= - (g_pRxDescriptors[ui32Loop].pBuf->len << DES1_RX_CTRL_BUFF1_SIZE_S); - g_pRxDescriptors[ui32Loop].Desc.ui32CtrlStatus = DES0_RX_CTRL_OWN; - } - else - { - LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_init: pbuf_alloc error\n")); - - /* No pbuf available so leave the buffer pointer empty. */ - g_pRxDescriptors[ui32Loop].Desc.pvBuffer1 = 0; - g_pRxDescriptors[ui32Loop].Desc.ui32CtrlStatus = 0; - } - g_pRxDescriptors[ui32Loop].Desc.DES3.pLink = - ((ui32Loop == (NUM_RX_DESCRIPTORS - 1)) ? - &g_pRxDescriptors[0].Desc : &g_pRxDescriptors[ui32Loop + 1].Desc); - } - - g_TxDescList.ui32Read = 0; - g_TxDescList.ui32Write = 0; - - // - // Set the descriptor pointers in the hardware. - // - EMACRxDMADescriptorListSet(EMAC0_BASE, &g_pRxDescriptors[0].Desc); - EMACTxDMADescriptorListSet(EMAC0_BASE, &g_pTxDescriptors[0].Desc); -} - -/** - * In this function, the hardware should be initialized. - * Called from tivaif_init(). - * - * @param netif the already initialized lwip network interface structure - * for this ethernetif - */ -static void -tivaif_hwinit(struct netif *psNetif) -{ - uint16_t ui16Val; - - /* Initialize the DMA descriptors. */ - InitDMADescriptors(); - - /* Clear any stray PHY interrupts that may be set. */ - ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); - ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR2); - - /* Configure and enable the link status change interrupt in the PHY. */ - ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR); - ui16Val |= (EPHY_SCR_INTEN_EXT | EPHY_SCR_INTOE_EXT); - EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR, ui16Val); - EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1, (EPHY_MISR1_LINKSTATEN | - EPHY_MISR1_SPEEDEN | EPHY_MISR1_DUPLEXMEN | EPHY_MISR1_ANCEN)); - - /* Read the PHY interrupt status to clear any stray events. */ - ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); - - /** - * Set MAC filtering options. We receive all broadcast and mui32ticast - * packets along with those addressed specifically for us. - */ - EMACFrameFilterSet(EMAC0_BASE, (EMAC_FRMFILTER_HASH_AND_PERFECT | - EMAC_FRMFILTER_PASS_MULTICAST)); - -#if LWIP_PTPD - // - // Enable timestamping on all received packets. - // - // We set the fine clock adjustment mode and configure the subsecond - // increment to half the 25MHz PTPD clock. This will give us maximum control - // over the clock rate adjustment and keep the arithmetic easy later. It - // should be possible to synchronize with higher accuracy than this with - // appropriate juggling of the subsecond increment count and the addend - // register value, though. - // - EMACTimestampConfigSet(EMAC0_BASE, (EMAC_TS_ALL_RX_FRAMES | - EMAC_TS_DIGITAL_ROLLOVER | - EMAC_TS_PROCESS_IPV4_UDP | EMAC_TS_ALL | - EMAC_TS_PTP_VERSION_1 | EMAC_TS_UPDATE_FINE), - (1000000000 / (25000000 / 2))); - EMACTimestampAddendSet(EMAC0_BASE, 0x80000000); - EMACTimestampEnable(EMAC0_BASE); -#endif - - /* Clear any pending MAC interrupts. */ - EMACIntClear(EMAC0_BASE, EMACIntStatus(EMAC0_BASE, false)); - - /* Enable the Ethernet MAC transmitter and receiver. */ - EMACTxEnable(EMAC0_BASE); - EMACRxEnable(EMAC0_BASE); - - /* Enable the Ethernet RX and TX interrupt source. */ - EMACIntEnable(EMAC0_BASE, (EMAC_INT_RECEIVE | EMAC_INT_TRANSMIT | - EMAC_INT_TX_STOPPED | EMAC_INT_RX_NO_BUFFER | - EMAC_INT_RX_STOPPED | EMAC_INT_PHY)); - - /* Enable the Ethernet interrupt. */ - IntEnable(INT_EMAC0); - - /* Enable all processor interrupts. */ - IntMasterEnable(); - - /* Tell the PHY to start an auto-negotiation cycle. */ - EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMCR, (EPHY_BMCR_ANEN | - EPHY_BMCR_RESTARTAN)); -} - -#ifdef DEBUG -/** - * Dump the chain of pbuf pointers to the debug output. - */ -void -tivaif_trace_pbuf(const char *pcTitle, struct pbuf *p) -{ - LWIP_DEBUGF(NETIF_DEBUG, ("%s %08x (%d, %d)", pcTitle, p, p->tot_len, - p->len)); - - do - { - p = p->next; - if(p) - { - LWIP_DEBUGF(NETIF_DEBUG, ("->%08x(%d)", p, p->len)); - } - else - { - LWIP_DEBUGF(NETIF_DEBUG, ("->%08x", p)); - } - - } while((p != NULL) && (p->tot_len != p->len)); - - LWIP_DEBUGF(NETIF_DEBUG, ("\n")); -} -#endif - -/** - * This function is used to check whether a passed pbuf contains only buffers - * resident in regions of memory that the Ethernet MAC can access. If any - * buffers in the chain are outside a directly-DMAable section of memory, - * the pbuf is copied to SRAM and a different pointer returned. If all - * buffers are safe, the pbuf reference count is incremented and the original - * pointer returned. - */ -static struct pbuf * -tivaif_check_pbuf(struct pbuf *p) -{ - struct pbuf *pBuf; - rt_err_t Err; - - pBuf = p; - -#ifdef DEBUG - tivaif_trace_pbuf("Original:", p); -#endif - - /* Walk the list of buffers in the pbuf checking each. */ - do - { - /* Does this pbuf's payload reside in memory that the Ethernet DMA - * can access? - */ - if(!PTR_SAFE_FOR_EMAC_DMA(pBuf->payload)) - { - /* This buffer is outside the DMA-able memory space so we need - * to copy the pbuf. - */ - pBuf = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_POOL); - - /* If we got a new pbuf... */ - if(pBuf) - { - /* ...copy the old pbuf into the new one. */ - Err = pbuf_copy(pBuf, p); - - /* If we failed to copy the pbuf, free the newly allocated one - * and make sure we return a NULL to show a problem. - */ - if(Err != RT_EOK) - { - DRIVER_STATS_INC(TXCopyFailCount); - pbuf_free(pBuf); - pBuf = NULL; - } - else - { -#ifdef DEBUG - tivaif_trace_pbuf("Copied:", pBuf); -#endif - DRIVER_STATS_INC(TXCopyCount); - - /* Reduce the reference count on the original pbuf since - * we're not going to hold on to it after returning from - * tivaif_transmit. Note that we already bumped - * the reference count at the top of tivaif_transmit. - */ - pbuf_free(p); - } - } - - /* Send back the new pbuf pointer or NULL if an error occurred. */ - return(pBuf); - } - - /* Move on to the next buffer in the queue */ - pBuf = pBuf->next; - } - while(pBuf); - - /** - * If we get here, the passed pbuf can be safely used without needing to - * be copied. - */ - return(p); -} - -/** - * This function should do the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf might be - * chained. - * - * @param psNetif the lwip network interface structure for this ethernetif - * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) - * @return RT_EOK if the packet coui32d be sent - * an err_t value if the packet coui32dn't be sent - */ -static rt_err_t -tivaif_transmit(net_device_t dev, struct pbuf *p) -{ - tStellarisIF *pIF; - tDescriptor *pDesc; - struct pbuf *pBuf; - uint32_t ui32NumChained, ui32NumDescs; - bool bFirst; - SYS_ARCH_DECL_PROTECT(lev); - - LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_transmit 0x%08x, len %d\n", p, - p->tot_len)); - - /** - * This entire function must run within a "critical section" to preserve - * the integrity of the transmit pbuf queue. - */ - SYS_ARCH_PROTECT(lev); - - /* Update our transmit attempt counter. */ - DRIVER_STATS_INC(TXCount); - - /** - * Increase the reference count on the packet provided so that we can - * hold on to it until we are finished transmitting its content. - */ - pbuf_ref(p); - - /** - * Determine whether all buffers passed are within SRAM and, if not, copy - * the pbuf into SRAM-resident buffers so that the Ethernet DMA can access - * the data. - */ - p = tivaif_check_pbuf(p); - - /* Make sure we still have a valid buffer (it may have been copied) */ - if(!p) - { - LINK_STATS_INC(link.memerr); - SYS_ARCH_UNPROTECT(lev); - return(-RT_ENOMEM); - } - - /* Get our state data from the netif structure we were passed. */ - //pIF = (tStellarisIF *)psNetif->state; - pIF = dev->dma_if; - - /* Make sure that the transmit descriptors are not all in use */ - pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]); - if(pDesc->pBuf) - { - /** - * The current write descriptor has a pbuf attached to it so this - * implies that the ring is fui32l. Reject this transmit request with a - * memory error since we can't satisfy it just now. - */ - pbuf_free(p); - LINK_STATS_INC(link.memerr); - DRIVER_STATS_INC(TXNoDescCount); - SYS_ARCH_UNPROTECT(lev); - return (-RT_ENOMEM); - } - - /* How many pbufs are in the chain passed? */ - ui32NumChained = (uint32_t)pbuf_clen(p); - - /* How many free transmit descriptors do we have? */ - ui32NumDescs = (pIF->pTxDescList->ui32Read > pIF->pTxDescList->ui32Write) ? - (pIF->pTxDescList->ui32Read - pIF->pTxDescList->ui32Write) : - ((NUM_TX_DESCRIPTORS - pIF->pTxDescList->ui32Write) + - pIF->pTxDescList->ui32Read); - - /* Do we have enough free descriptors to send the whole packet? */ - if(ui32NumDescs < ui32NumChained) - { - /* No - we can't transmit this whole packet so return an error. */ - pbuf_free(p); - LINK_STATS_INC(link.memerr); - DRIVER_STATS_INC(TXNoDescCount); - SYS_ARCH_UNPROTECT(lev); - return (-RT_ENOMEM); - } - - /* Tag the first descriptor as the start of the packet. */ - bFirst = true; - pDesc->Desc.ui32CtrlStatus = DES0_TX_CTRL_FIRST_SEG; - - /* Here, we know we can send the packet so write it to the descriptors */ - pBuf = p; - - while(ui32NumChained) - { - /* Get a pointer to the descriptor we will write next. */ - pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]); - - /* Fill in the buffer pointer and length */ - pDesc->Desc.ui32Count = (uint32_t)pBuf->len; - pDesc->Desc.pvBuffer1 = pBuf->payload; - - /* Tag the first descriptor as the start of the packet. */ - if(bFirst) - { - bFirst = false; - pDesc->Desc.ui32CtrlStatus = DES0_TX_CTRL_FIRST_SEG; - } - else - { - pDesc->Desc.ui32CtrlStatus = 0; - } - - pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_IP_ALL_CKHSUMS | - DES0_TX_CTRL_CHAINED); - - /* Decrement our descriptor counter, move on to the next buffer in the - * pbuf chain. */ - ui32NumChained--; - pBuf = pBuf->next; - - /* Update the descriptor list write index. */ - pIF->pTxDescList->ui32Write++; - if(pIF->pTxDescList->ui32Write == NUM_TX_DESCRIPTORS) - { - pIF->pTxDescList->ui32Write = 0; - } - - /* If this is the last descriptor, mark it as the end of the packet. */ - if(!ui32NumChained) - { - pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_LAST_SEG | - DES0_TX_CTRL_INTERRUPT); - - /* Tag the descriptor with the original pbuf pointer. */ - pDesc->pBuf = p; - } - else - { - /* Set the lsb of the pbuf pointer. We use this as a signal that - * we should not free the pbuf when we are walking the descriptor - * list while processing the transmit interrupt. We only free the - * pbuf when processing the last descriptor used to transmit its - * chain. - */ - pDesc->pBuf = (struct pbuf *)((uint32_t)p + 1); - } - - DRIVER_STATS_INC(TXBufQueuedCount); - - /* Hand the descriptor over to the hardware. */ - pDesc->Desc.ui32CtrlStatus |= DES0_TX_CTRL_OWN; - } - - /* Tell the transmitter to start (in case it had stopped). */ - EMACTxDMAPollDemand(EMAC0_BASE); - - /* Update lwIP statistics */ - LINK_STATS_INC(link.xmit); - - SYS_ARCH_UNPROTECT(lev); - - return(RT_EOK); -} - -/** - * This function will process all transmit descriptors and free pbufs attached - * to any that have been transmitted since we last checked. - * - * This function is called only from the Ethernet interrupt handler. - * - * @param netif the lwip network interface structure for this ethernetif - * @return None. - */ -static void -tivaif_process_transmit(tStellarisIF *pIF) -{ - tDescriptorList *pDescList; - uint32_t ui32NumDescs; - - /* Get a pointer to the transmit descriptor list. */ - pDescList = pIF->pTxDescList; - - /* Walk the list until we have checked all descriptors or we reach the - * write pointer or find a descriptor that the hardware is still working - * on. - */ - for(ui32NumDescs = 0; ui32NumDescs < pDescList->ui32NumDescs; ui32NumDescs++) - { - /* Has the buffer attached to this descriptor been transmitted? */ - if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_TX_CTRL_OWN) - { - /* No - we're finished. */ - break; - } - - /* Does this descriptor have a buffer attached to it? */ - if(pDescList->pDescriptors[pDescList->ui32Read].pBuf) - { - /* Yes - free it if it's not marked as an intermediate pbuf */ - if(!((uint32_t)(pDescList->pDescriptors[pDescList->ui32Read].pBuf) & 1)) - { - pbuf_free(pDescList->pDescriptors[pDescList->ui32Read].pBuf); - DRIVER_STATS_INC(TXBufFreedCount); - } - pDescList->pDescriptors[pDescList->ui32Read].pBuf = NULL; - } - else - { - /* If the descriptor has no buffer, we are finished. */ - break; - } - - /* Move on to the next descriptor. */ - pDescList->ui32Read++; - if(pDescList->ui32Read == pDescList->ui32NumDescs) - { - pDescList->ui32Read = 0; - } - } -} - -/** - * This function will process all receive descriptors that contain newly read - * data and pass complete frames up the lwIP stack as they are found. The - * timestamp of the packet will be placed into the pbuf structure if PTPD is - * enabled. - * - * This function is called only from the Ethernet interrupt handler. - * - * @param psNetif the lwip network interface structure for this ethernetif - * @return None. - */ -static void -tivaif_receive(net_device_t dev) -{ - tDescriptorList *pDescList; - tStellarisIF *pIF; - struct pbuf *pBuf; - uint32_t ui32DescEnd; - - /* Get a pointer to our state data */ - pIF = dev->dma_if; - - /* Get a pointer to the receive descriptor list. */ - pDescList = pIF->pRxDescList; - - /* Start with a NULL pbuf so that we don't try to link chain the first - * time round. - */ - pBuf = NULL; - - /* Determine where we start and end our walk of the descriptor list */ - ui32DescEnd = pDescList->ui32Read ? (pDescList->ui32Read - 1) : (pDescList->ui32NumDescs - 1); - - /* Step through the descriptors that are marked for CPU attention. */ - while(pDescList->ui32Read != ui32DescEnd) - { - /* Does the current descriptor have a buffer attached to it? */ - if(pDescList->pDescriptors[pDescList->ui32Read].pBuf) - { - /* Yes - determine if the host has filled it yet. */ - if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_RX_CTRL_OWN) - { - /* The DMA engine still owns the descriptor so we are finished */ - break; - } - - DRIVER_STATS_INC(RXBufReadCount); - - /* If this descriptor contains the end of the packet, fix up the - * buffer size accordingly. - */ - if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_RX_STAT_LAST_DESC) - { - /* This is the last descriptor for the frame so fix up the - * length. It is safe for us to modify the internal fields - * directly here (rather than calling pbuf_realloc) since we - * know each of these pbufs is never chained. - */ - pDescList->pDescriptors[pDescList->ui32Read].pBuf->len = - (pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_RX_STAT_FRAME_LENGTH_M) >> - DES0_RX_STAT_FRAME_LENGTH_S; - pDescList->pDescriptors[pDescList->ui32Read].pBuf->tot_len = - pDescList->pDescriptors[pDescList->ui32Read].pBuf->len; - } - - if(pBuf) - { - /* Link this pbuf to the last one we looked at since this buffer - * is a continuation of an existing frame (split across mui32tiple - * pbufs). Note that we use pbuf_cat() here rather than - * pbuf_chain() since we don't want to increase the reference - * count of either pbuf - we only want to link them together. - */ - pbuf_cat(pBuf, pDescList->pDescriptors[pDescList->ui32Read].pBuf); - pDescList->pDescriptors[pDescList->ui32Read].pBuf = pBuf; - } - - /* Remember the buffer associated with this descriptor. */ - pBuf = pDescList->pDescriptors[pDescList->ui32Read].pBuf; - - /* Is this the last descriptor for the current frame? */ - if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_RX_STAT_LAST_DESC) - { - /* Yes - does the frame contain errors? */ - if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_RX_STAT_ERR) - { - /* This is a bad frame so discard it and update the relevant - * statistics. - */ - LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_receive: packet error\n")); - pbuf_free(pBuf); - LINK_STATS_INC(link.drop); - DRIVER_STATS_INC(RXPacketErrCount); - } - else - { - /* This is a good frame so pass it up the stack. */ - LINK_STATS_INC(link.recv); - DRIVER_STATS_INC(RXPacketReadCount); - -#if LWIP_PTPD - /* Place the timestamp in the PBUF if PTPD is enabled */ - pBuf->time_s = - pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32IEEE1588TimeHi; - pBuf->time_ns = - pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32IEEE1588TimeLo; -#endif - -#if NO_SYS - if(ethernet_input(pBuf, psNetif) != RT_EOK) - { -#else - //if(tcpip_input(pBuf, psNetif) != RT_EOK) - if((rt_mb_send(dev->rx_pbuf_mb, (rt_uint32_t)pBuf) != RT_EOK) || - (eth_device_ready(&(dev->parent)) != RT_EOK)) - { -#endif - /* drop the packet */ - LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_input: input error\n")); - pbuf_free(pBuf); - - /* Adjust the link statistics */ - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.drop); - DRIVER_STATS_INC(RXPacketCBErrCount); - } - - /* We're finished with this packet so make sure we don't try - * to link the next buffer to it. - */ - pBuf = NULL; - } - } - } - - /* Allocate a new buffer for this descriptor */ - pDescList->pDescriptors[pDescList->ui32Read].pBuf = pbuf_alloc(PBUF_RAW, - PBUF_POOL_BUFSIZE, - PBUF_POOL); - pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32Count = - DES1_RX_CTRL_CHAINED; - if(pDescList->pDescriptors[pDescList->ui32Read].pBuf) - { - /* We got a buffer so fill in the payload pointer and size. */ - pDescList->pDescriptors[pDescList->ui32Read].Desc.pvBuffer1 = - pDescList->pDescriptors[pDescList->ui32Read].pBuf->payload; - pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32Count |= - (pDescList->pDescriptors[pDescList->ui32Read].pBuf->len << - DES1_RX_CTRL_BUFF1_SIZE_S); - - /* Give this descriptor back to the hardware */ - pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus = - DES0_RX_CTRL_OWN; - } - else - { - LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_receive: pbuf_alloc error\n")); - - pDescList->pDescriptors[pDescList->ui32Read].Desc.pvBuffer1 = 0; - - /* Update the stats to show we coui32dn't allocate a pbuf. */ - DRIVER_STATS_INC(RXNoBufCount); - LINK_STATS_INC(link.memerr); - - /* Stop parsing here since we can't leave a broken descriptor in - * the chain. - */ - break; - } - - /* Move on to the next descriptor in the chain, taking care to wrap. */ - pDescList->ui32Read++; - if(pDescList->ui32Read == pDescList->ui32NumDescs) - { - pDescList->ui32Read = 0; - } - } -} - -/** - * Process interrupts from the PHY. - * - * should be called from the Stellaris Ethernet Interrupt Handler. This - * function will read packets from the Stellaris Ethernet fifo and place them - * into a pbuf queue. If the transmitter is idle and there is at least one packet - * on the transmit queue, it will place it in the transmit fifo and start the - * transmitter. - * - */ -void -tivaif_process_phy_interrupt(net_device_t dev) -{ - uint16_t ui16Val, ui16Status; - uint32_t ui32Config, ui32Mode, ui32RxMaxFrameSize; - - /* Read the PHY interrupt status. This clears all interrupt sources. - * Note that we are only enabling sources in EPHY_MISR1 so we don't - * read EPHY_MISR2. - */ - ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); - - /* - * Dummy read PHY REG EPHY_BMSR, it will force update the EPHY_STS register - */ - EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMSR); - /* Read the current PHY status. */ - ui16Status = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_STS); - - /* Has the link status changed? */ - if(ui16Val & EPHY_MISR1_LINKSTAT) - { - /* Is link up or down now? */ - if(ui16Status & EPHY_STS_LINK) - { - /* Tell lwIP the link is up. */ -#if NO_SYS - netif_set_link_up(psNetif); -#else - //tcpip_callback((tcpip_callback_fn)netif_set_link_up, psNetif); - eth_device_linkchange(&(dev->parent), RT_TRUE); -#endif - - /* In this case we drop through since we may need to reconfigure - * the MAC depending upon the speed and half/fui32l-duplex settings. - */ - } - else - { - /* Tell lwIP the link is down */ -#if NO_SYS - netif_set_link_down(psNetif); -#else - //tcpip_callback((tcpip_callback_fn)netif_set_link_down, psNetif); - eth_device_linkchange(&(dev->parent), RT_FALSE); -#endif - } - } - - /* Has the speed or duplex status changed? */ - if(ui16Val & (EPHY_MISR1_SPEED | EPHY_MISR1_SPEED | EPHY_MISR1_ANC)) - { - /* Get the current MAC configuration. */ - EMACConfigGet(EMAC0_BASE, &ui32Config, &ui32Mode, - &ui32RxMaxFrameSize); - - /* What speed is the interface running at now? - */ - if(ui16Status & EPHY_STS_SPEED) - { - /* 10Mbps is selected */ - ui32Config &= ~EMAC_CONFIG_100MBPS; - } - else - { - /* 100Mbps is selected */ - ui32Config |= EMAC_CONFIG_100MBPS; - } - - /* Are we in fui32l- or half-duplex mode? */ - if(ui16Status & EPHY_STS_DUPLEX) - { - /* Fui32l duplex. */ - ui32Config |= EMAC_CONFIG_FULL_DUPLEX; - } - else - { - /* Half duplex. */ - ui32Config &= ~EMAC_CONFIG_FULL_DUPLEX; - } - - /* Reconfigure the MAC */ - EMACConfigSet(EMAC0_BASE, ui32Config, ui32Mode, ui32RxMaxFrameSize); - } -} - -/** - * Process tx and rx packets at the low-level interrupt. - * - * should be called from the Stellaris Ethernet Interrupt Handler. This - * function will read packets from the Stellaris Ethernet fifo and place them - * into a pbuf queue. If the transmitter is idle and there is at least one packet - * on the transmit queue, it will place it in the transmit fifo and start the - * transmitter. - * - */ -void -tivaif_interrupt(net_device_t dev, uint32_t ui32Status) -{ - - /* Update our debug interrupt counters. */ - if(ui32Status & EMAC_INT_NORMAL_INT) - { - g_ui32NormalInts++; - } - - if(ui32Status & EMAC_INT_ABNORMAL_INT) - { - g_ui32AbnormalInts++; - } - - /* Is this an interrupt from the PHY? */ - if(ui32Status & EMAC_INT_PHY) - { - tivaif_process_phy_interrupt(dev); - } - - /* Process the transmit DMA list, freeing any buffers that have been - * transmitted since our last interrupt. - */ - if(ui32Status & EMAC_INT_TRANSMIT) - { - tivaif_process_transmit(dev->dma_if); - } - - /** - * Process the receive DMA list and pass all successfui32ly received packets - * up the stack. We also call this function in cases where the receiver has - * stalled due to missing buffers since the receive function will attempt to - * allocate new pbufs for descriptor entries which have none. - */ - if(ui32Status & (EMAC_INT_RECEIVE | EMAC_INT_RX_NO_BUFFER | - EMAC_INT_RX_STOPPED)) - { - tivaif_receive(dev); - } -} - -#if NETIF_DEBUG -/* Print an IP header by using LWIP_DEBUGF - * @param p an IP packet, p->payload pointing to the IP header - */ -void -tivaif_debug_print(struct pbuf *p) -{ - struct eth_hdr *ethhdr = (struct eth_hdr *)p->payload; - u16_t *plen = (u16_t *)p->payload; - - LWIP_DEBUGF(NETIF_DEBUG, ("ETH header:\n")); - LWIP_DEBUGF(NETIF_DEBUG, ("Packet Length:%5"U16_F" \n",*plen)); - LWIP_DEBUGF(NETIF_DEBUG, ("Destination: %02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"\n", - ethhdr->dest.addr[0], - ethhdr->dest.addr[1], - ethhdr->dest.addr[2], - ethhdr->dest.addr[3], - ethhdr->dest.addr[4], - ethhdr->dest.addr[5])); - LWIP_DEBUGF(NETIF_DEBUG, ("Source: %02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"\n", - ethhdr->src.addr[0], - ethhdr->src.addr[1], - ethhdr->src.addr[2], - ethhdr->src.addr[3], - ethhdr->src.addr[4], - ethhdr->src.addr[5])); - LWIP_DEBUGF(NETIF_DEBUG, ("Packet Type:0x%04"U16_F" \n", ethhdr->type)); -} -#endif /* NETIF_DEBUG */ - -void lwIPEthernetIntHandler(void) -{ - uint32_t ui32Status; -#ifdef DEF_INT_TEMPSTAMP - uint32_t ui32TimerStatus; -#endif - // - // Read and Clear the interrupt. - // - ui32Status = MAP_EMACIntStatus(EMAC0_BASE, true); - - // - // If the interrupt really came from the Ethernet and not our - // timer, clear it. - // - if(ui32Status) - { - MAP_EMACIntClear(EMAC0_BASE, ui32Status); - } -#ifdef DEF_INT_TEMPSTAMP - // - // Check to see whether a hardware timer interrupt has been reported. - // - if(ui32Status & EMAC_INT_TIMESTAMP) - { - // - // Yes - read and clear the timestamp interrupt status. - // - ui32TimerStatus = EMACTimestampIntStatus(EMAC0_BASE); - - // - // If a timer interrupt handler has been registered, call it. - // - if(g_pfnTimerHandler) - { - g_pfnTimerHandler(EMAC0_BASE, ui32TimerStatus); - } - } -#endif - // - // The handling of the interrupt is different based on the use of a RTOS. - // - - // - // No RTOS is being used. If a transmit/receive interrupt was active, - // run the low-level interrupt handler. - // - if(ui32Status) - { - tivaif_interrupt(eth_dev, ui32Status); - } - - // - // Service the lwIP timers. - // - //lwIPServiceTimers(); -} - - -// OUI:00-12-37 (hex) Texas Instruments, only for test -static int tiva_eth_mac_addr_init(void) -{ - int retVal =0; - uint32_t ulUser[2]; - uint8_t mac_addr[6]; - - MAP_FlashUserGet(&ulUser[0], &ulUser[1]); - if((ulUser[0] == 0xffffffff) || (ulUser[1] == 0xffffffff)) - { - rt_kprintf("Fail to get mac address from eeprom.\n"); - rt_kprintf("Using default mac address\n"); - // OUI:00-12-37 (hex) Texas Instruments, only for test - // Configure the hardware MAC address - ulUser[0] = 0x00371200; - ulUser[1] = 0x00563412; - //FlashUserSet(ulUser0, ulUser1); - retVal =-1; - } - - - //Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC - //address needed to program the hardware registers, then program the MAC - //address into the Ethernet Controller registers. - - mac_addr[0] = ((ulUser[0] >> 0) & 0xff); - mac_addr[1] = ((ulUser[0] >> 8) & 0xff); - mac_addr[2] = ((ulUser[0] >> 16) & 0xff); - mac_addr[3] = ((ulUser[1] >> 0) & 0xff); - mac_addr[4] = ((ulUser[1] >> 8) & 0xff); - mac_addr[5] = ((ulUser[1] >> 16) & 0xff); - - // - // Program the hardware with its MAC address (for filtering). - // - MAP_EMACAddrSet(EMAC0_BASE, 0, mac_addr); - return retVal; -} - - void tiva_eth_lowlevel_init(void) -{ - MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); - // - // PF1/PK4/PK6 are used for Ethernet LEDs. - // - MAP_GPIOPinConfigure(GPIO_PF0_EN0LED0); - MAP_GPIOPinConfigure(GPIO_PF4_EN0LED1); - GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0); - GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_4); - - // - // Enable the ethernet peripheral. - // - MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0); - MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0); - // - // Enable the internal PHY if it's present and we're being - // asked to use it. - // - if((EMAC_PHY_CONFIG & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL) - { - // - // We've been asked to configure for use with the internal - // PHY. Is it present? - // - if(SysCtlPeripheralPresent(SYSCTL_PERIPH_EPHY0)) - { - // - // Yes - enable and reset it. - // - MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0); - MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0); - } - else - { - // - // Internal PHY is not present on this part so hang here. - // - rt_kprintf("Internal PHY is not present on this part.\n"); - while(1) - { - } - } - } - - // - // Wait for the MAC to come out of reset. - // - while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0)) - { - } - - // - // Configure for use with whichever PHY the user requires. - // - MAP_EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_CONFIG); - - // - // Initialize the MAC and set the DMA mode. - // - MAP_EMACInit(EMAC0_BASE, 120000000, //system clock = 120MHz - EMAC_BCONFIG_MIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED, - 4, 4, 0); - - // - // Set MAC configuration options. - // - MAP_EMACConfigSet(EMAC0_BASE, (EMAC_CONFIG_FULL_DUPLEX | - EMAC_CONFIG_CHECKSUM_OFFLOAD | - EMAC_CONFIG_7BYTE_PREAMBLE | - EMAC_CONFIG_IF_GAP_96BITS | - EMAC_CONFIG_USE_MACADDR0 | - EMAC_CONFIG_SA_FROM_DESCRIPTOR | - EMAC_CONFIG_BO_LIMIT_1024), - (EMAC_MODE_RX_STORE_FORWARD | - EMAC_MODE_TX_STORE_FORWARD | - EMAC_MODE_TX_THRESHOLD_64_BYTES | - EMAC_MODE_RX_THRESHOLD_64_BYTES), 0); - - EMACIntRegister(EMAC0_BASE, lwIPEthernetIntHandler); - -} - -static rt_err_t eth_dev_init(rt_device_t device) -{ - net_device_t net_dev = (net_device_t)device; - struct netif *psNetif = (net_dev->parent.netif); - - LWIP_ASSERT("psNetif != NULL", (psNetif != NULL)); - -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - psNetif->hostname = "t4mc"; -#endif /* LWIP_NETIF_HOSTNAME */ - - /* - * Initialize the snmp variables and counters inside the struct netif. - * The last argument should be replaced with your link speed, in units - * of bits per second. - */ - //NETIF_INIT_SNMP(psNetif, snmp_ifType_ethernet_csmacd, 1000000); - - net_dev->dma_if = &g_StellarisIFData; - - /* Remember our MAC address. */ - g_StellarisIFData.ethaddr = (struct eth_addr *)&(psNetif->hwaddr[0]); - - /* Initialize the hardware */ - tivaif_hwinit(psNetif); - return RT_EOK; -} - -/* control the interface */ -static rt_err_t eth_dev_control(rt_device_t dev, int cmd, void *args) -{ - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) - MAP_EMACAddrGet(EMAC0_BASE, 0, (uint8_t*)args); - else - return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; -} - -/* Open the interface */ -static rt_err_t eth_dev_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -/* Close the interface */ -static rt_err_t eth_dev_close(rt_device_t dev) -{ - return RT_EOK; -} - -/* Read */ -static rt_size_t eth_dev_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -/* Write */ -static rt_size_t eth_dev_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -static rt_err_t eth_dev_tx(rt_device_t dev, struct pbuf *p) -{ - return tivaif_transmit((net_device_t)dev, p); -} - -static struct pbuf* eth_dev_rx(rt_device_t dev) -{ - rt_err_t result; - rt_uint32_t temp =0; - net_device_t net_dev = (net_device_t)dev; - result = rt_mb_recv(net_dev->rx_pbuf_mb, &temp, RT_WAITING_NO); - - return (result == RT_EOK)? (struct pbuf*)temp : RT_NULL; -} - -int rt_hw_tiva_eth_init(void) -{ - rt_err_t result; - - /* Clock GPIO and etc */ - tiva_eth_lowlevel_init(); - tiva_eth_mac_addr_init(); - - /* init rt-thread device interface */ - eth_dev->parent.parent.init = eth_dev_init; - eth_dev->parent.parent.open = eth_dev_open; - eth_dev->parent.parent.close = eth_dev_close; - eth_dev->parent.parent.read = eth_dev_read; - eth_dev->parent.parent.write = eth_dev_write; - eth_dev->parent.parent.control = eth_dev_control; - eth_dev->parent.eth_rx = eth_dev_rx; - eth_dev->parent.eth_tx = eth_dev_tx; - - result = rt_mb_init(ð_rx_pbuf_mb, "epbuf", - &rx_pbuf_mb_pool[0], sizeof(rx_pbuf_mb_pool)/4, - RT_IPC_FLAG_FIFO); - RT_ASSERT(result == RT_EOK); - eth_dev->rx_pbuf_mb = ð_rx_pbuf_mb; - - - result = eth_device_init(&(eth_dev->parent), "e0"); - return result; -} -// eth_device_init using malloc -// We use INIT_COMPONENT_EXPORT insted of INIT_BOARD_EXPORT -INIT_COMPONENT_EXPORT(rt_hw_tiva_eth_init); - - -#if 0 -#ifdef RT_USING_FINSH -#include "finsh.h" -void PHY_Read(uint8_t addr) -{ - uint16_t data = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, addr); - rt_kprintf("R PHY_REG[0x%02X] = 0x%04X\n", addr, data); -} -FINSH_FUNCTION_EXPORT(PHY_Read, (add)); - -void PHY_Write(uint8_t addr , uint16_t data) -{ - EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, addr, data); - rt_kprintf("W PHY_REG[0x%02X] = 0x%04X\n", addr, data); -} -FINSH_FUNCTION_EXPORT(PHY_Write, (add, data)); - -void PHY_SetAdd(uint8_t addr0, uint8_t addr1, uint8_t addr2, - uint8_t addr3, uint8_t addr4, uint8_t addr5) -{ - uint32_t ulUser[2]; - ulUser[0] = (((addr2<<8)|addr1)<<8)|addr0; - ulUser[1] = (((addr5<<8)|addr4)<<8)|addr3; - - MAP_FlashUserSet(ulUser[0], ulUser[1]); - MAP_FlashUserSave(); - rt_kprintf("Save to EEPROM. please reboot."); -} -FINSH_FUNCTION_EXPORT(PHY_SetAdd, (add0-add5)); -#endif //RT_USING_FINSH -#endif diff --git a/bsp/tm4c129x-dk/drivers/drv_eth.h b/bsp/tm4c129x-dk/drivers/drv_eth.h deleted file mode 100644 index 54431405fe0797ce399c0b8b0e763c3cb0a18792..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/drivers/drv_eth.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * File : drv_eth.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-07-25 ArdaFu Port to TM4C129X - */ - -#ifndef __TIVA_ETH_H__ -#define __TIVA_ETH_H__ - -int rt_hw_tiva_eth_init(void); - -#endif diff --git a/bsp/tm4c129x-dk/drivers/drv_uart.c b/bsp/tm4c129x-dk/drivers/drv_uart.c deleted file mode 100644 index ef95144af15667055cc6661c0652ebaac9d0d07b..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/drivers/drv_uart.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2013-05-18 Bernard The first version for LPC40xx - * 2014-07-18 ArdaFu Port to TM4C129X - */ - -#include -#include -#include - -#include "board.h" - -#include "inc/hw_memmap.h" -#include "driverlib/sysctl.h" -#include "driverlib/gpio.h" -#include "driverlib/uart.h" -#include "driverlib/pin_map.h" -#include "driverlib/interrupt.h" -#include "driverlib/rom_map.h" -typedef struct hw_uart_device -{ - uint32_t hw_base; // base address -}hw_uart_t; - -#define mUartGetHwPtr(serial) ((hw_uart_t*)(serial->parent.user_data)) - -static rt_err_t hw_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - uint32_t config = 0; - hw_uart_t* uart; - RT_ASSERT(serial != RT_NULL); - uart = mUartGetHwPtr(serial); - - MAP_UARTDisable(uart->hw_base); - // build UART Configuration parameter structure - switch(cfg->data_bits) - { - case DATA_BITS_9: - // enable 9bit address mode and set DATA_BIT_8 - MAP_UART9BitEnable(uart->hw_base); - case DATA_BITS_8: - config |= UART_CONFIG_WLEN_8; - break; - case DATA_BITS_7: - config |= UART_CONFIG_WLEN_7; - break; - case DATA_BITS_6: - config |= UART_CONFIG_WLEN_6; - break; - case DATA_BITS_5: - config |= UART_CONFIG_WLEN_5; - break; - default: - RT_ASSERT(0); - break; - } - switch(cfg->parity) - { - case PARITY_ODD: - config |= UART_CONFIG_PAR_ODD; - break; - case PARITY_EVEN: - config |= UART_CONFIG_PAR_EVEN; - break; - case PARITY_NONE: - config |= UART_CONFIG_PAR_NONE; - break; - default: - RT_ASSERT(0); - break; - } - switch(cfg->stop_bits) - { - case STOP_BITS_1: - config |= UART_CONFIG_STOP_ONE; - break; - case STOP_BITS_2: - config |= UART_CONFIG_STOP_TWO; - break; - default: - RT_ASSERT(0); - break; - } - - // Initialize UART0 peripheral with given to corresponding parameter - MAP_UARTConfigSetExpClk(uart->hw_base, SystemCoreClock, cfg->baud_rate, config); - MAP_UARTFIFOEnable(uart->hw_base); - - // Enable the UART. - MAP_UARTEnable(uart->hw_base); - return RT_EOK; -} - -static rt_err_t hw_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - hw_uart_t* uart; - RT_ASSERT(serial != RT_NULL); - uart = mUartGetHwPtr(serial); - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - MAP_UARTIntDisable(uart->hw_base, UART_INT_RX | UART_INT_RT); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - MAP_UARTIntEnable(uart->hw_base, UART_INT_RX | UART_INT_RT); - break; - } - - return RT_EOK; -} - -static int hw_putc(struct rt_serial_device *serial, char c) -{ - hw_uart_t* uart; - RT_ASSERT(serial != RT_NULL); - uart = mUartGetHwPtr(serial); - - MAP_UARTCharPut(uart->hw_base, *((uint8_t *)&c)); - return 1; -} - -static int hw_getc(struct rt_serial_device *serial) -{ - hw_uart_t* uart; - RT_ASSERT(serial != RT_NULL); - uart = mUartGetHwPtr(serial); - - return MAP_UARTCharGetNonBlocking(uart->hw_base); -} - -static const struct rt_uart_ops hw_uart_ops = -{ - hw_configure, - hw_control, - hw_putc, - hw_getc, -}; - -#if defined(RT_USING_UART0) -/* UART0 device driver structure */ -struct rt_serial_device serial0; -hw_uart_t uart0 = -{ - UART0_BASE, -}; - -void UART0_IRQHandler(void) -{ - uint32_t intsrc; - hw_uart_t *uart = &uart0; - - /* enter interrupt */ - rt_interrupt_enter(); - - /* Determine the interrupt source */ - intsrc = MAP_UARTIntStatus(uart->hw_base, true); - - // Receive Data Available or Character time-out - if (intsrc & (UART_INT_RX | UART_INT_RT)) - { - MAP_UARTIntClear(uart->hw_base, intsrc); - rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); - } - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -int rt_hw_uart_init(void) -{ - hw_uart_t* uart; - struct serial_configure config; - - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - -#ifdef RT_USING_UART0 - uart = &uart0; - serial0.ops = &hw_uart_ops; - serial0.config = config; - - MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - MAP_GPIOPinConfigure(GPIO_PA0_U0RX); - MAP_GPIOPinConfigure(GPIO_PA1_U0TX); - - MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); - MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - - /* preemption = 1, sub-priority = 1 */ - //IntPrioritySet(INT_UART0, ((0x01 << 5) | 0x01)); - - /* Enable Interrupt for UART channel */ - UARTIntRegister(uart->hw_base, UART0_IRQHandler); - MAP_IntEnable(INT_UART0); - MAP_UARTEnable(uart->hw_base); - - /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif - return 0; -} -INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/tm4c129x-dk/drivers/drv_uart.h b/bsp/tm4c129x-dk/drivers/drv_uart.h deleted file mode 100644 index 312c6da6b32363c47236ccc540547ae8556e6c50..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/drivers/drv_uart.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2013-05-18 Bernard The first version for LPC40xx - * 2014-07-18 ArdaFu Port to TM4C129X - */ -#ifndef __UART_H__ -#define __UART_H__ - -void rt_hw_uart_init(void); - -#endif diff --git a/bsp/tm4c129x-dk/libraries/SConscript b/bsp/tm4c129x-dk/libraries/SConscript deleted file mode 100644 index 56c7b84ab339e40f013a24cf305ed0337eb4b7e9..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/SConscript +++ /dev/null @@ -1,26 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -# The set of source files associated with this SConscript file. -cwd = GetCurrentDir() -src = Glob('driverlib/*.c') -SrcRemove(src, 'onewire.c') -CCFLAGS = '' - -# add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - src += ['startup/startup_gcc.c'] -elif rtconfig.CROSS_TOOL == 'keil': - src += ['startup/startup_rvmdk.S'] -elif rtconfig.CROSS_TOOL == 'iar': - src += ['startup/startup_ewarm.c'] - CCFLAGS += ' --diag_suppress=pe177' - -CPPPATH = [cwd, cwd + '/inc', cwd + '/driverlib'] - - -CPPDEFINES = [rtconfig.PART_TYPE] -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, CCFLAGS = CCFLAGS) - -Return('group') diff --git a/bsp/tm4c129x-dk/libraries/driverlib/adc.c b/bsp/tm4c129x-dk/libraries/driverlib/adc.c deleted file mode 100644 index 81e7dc05fc7a7f242629087da27896b6fa97ee37..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/adc.c +++ /dev/null @@ -1,2073 +0,0 @@ -//***************************************************************************** -// -// adc.c - Driver for the ADC. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup adc_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_adc.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_sysctl.h" -#include "driverlib/adc.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -// These defines are used by the ADC driver to simplify access to the ADC -// sequencer's registers. -// -//***************************************************************************** -#define ADC_SEQ (ADC_O_SSMUX0) -#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0) -#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0) -#define ADC_SSEMUX (ADC_O_SSEMUX0 - ADC_O_SSMUX0) -#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0) -#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0) -#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0) -#define ADC_SSOP (ADC_O_SSOP0 - ADC_O_SSMUX0) -#define ADC_SSDC (ADC_O_SSDC0 - ADC_O_SSMUX0) -#define ADC_SSTSH (ADC_O_SSTSH0 - ADC_O_SSMUX0) - -//***************************************************************************** -// -// The currently configured software oversampling factor for each of the ADC -// sequencers. -// -//***************************************************************************** -static uint8_t g_pui8OversampleFactor[2][3]; - -//***************************************************************************** -// -//! Returns the interrupt number for a given ADC base address and sequence -//! number. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function returns the interrupt number for the ADC module and sequence -//! number provided in the \e ui32Base and \e ui32SequenceNum parameters. -//! -//! \return Returns the ADC sequence interrupt number or 0 if the interrupt -//! does not exist. -// -//***************************************************************************** -static uint_fast8_t -_ADCIntNumberGet(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - uint_fast8_t ui8Int; - - // - // Determine the interrupt to register based on the sequence number. - // - if(CLASS_IS_TM4C123) - { - ui8Int = ((ui32Base == ADC0_BASE) ? - (INT_ADC0SS0_TM4C123 + ui32SequenceNum) : - (INT_ADC1SS0_TM4C123 + ui32SequenceNum)); - } - else if(CLASS_IS_TM4C129) - { - ui8Int = ((ui32Base == ADC0_BASE) ? - (INT_ADC0SS0_TM4C129 + ui32SequenceNum) : - (INT_ADC1SS0_TM4C129 + ui32SequenceNum)); - } - else - { - ui8Int = 0; - } - - return(ui8Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for an ADC interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param pfnHandler is a pointer to the function to be called when the -//! ADC sample sequence interrupt occurs. -//! -//! This function sets the handler to be called when a sample sequence -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; the sequence interrupt must be enabled with -//! ADCIntEnable(). It is the interrupt handler's responsibility to clear the -//! interrupt source via ADCIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum, - void (*pfnHandler)(void)) -{ - uint_fast8_t ui8Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Determine the interrupt to register based on the sequence number. - // - ui8Int = _ADCIntNumberGet(ui32Base, ui32SequenceNum); - ASSERT(ui8Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui8Int, pfnHandler); - - // - // Enable the timer interrupt. - // - IntEnable(ui8Int); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for an ADC interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function unregisters the interrupt handler. This function disables -//! the global interrupt in the interrupt controller; the sequence interrupt -//! must be disabled via ADCIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - uint_fast8_t ui8Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Determine the interrupt to unregister based on the sequence number. - // - ui8Int = _ADCIntNumberGet(ui32Base, ui32SequenceNum); - ASSERT(ui8Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui8Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui8Int); -} - -//***************************************************************************** -// -//! Disables a sample sequence interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function disables the requested sample sequence interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Disable this sample sequence interrupt. - // - HWREG(ui32Base + ADC_O_IM) &= ~(1 << ui32SequenceNum); -} - -//***************************************************************************** -// -//! Enables a sample sequence interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function enables the requested sample sequence interrupt. Any -//! outstanding interrupts are cleared before enabling the sample sequence -//! interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Clear any outstanding interrupts on this sample sequence. - // - HWREG(ui32Base + ADC_O_ISC) = 1 << ui32SequenceNum; - - // - // Enable this sample sequence interrupt. - // - HWREG(ui32Base + ADC_O_IM) |= 1 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the specified sample -//! sequence. Either the raw interrupt status or the status of interrupts that -//! are allowed to reflect to the processor can be returned. -//! -//! \return The current raw or masked interrupt status. -// -//***************************************************************************** -uint32_t -ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum, bool bMasked) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - ui32Temp = HWREG(ui32Base + ADC_O_ISC) & (0x10001 << ui32SequenceNum); - } - else - { - ui32Temp = (HWREG(ui32Base + ADC_O_RIS) & - (0x10000 | (1 << ui32SequenceNum))); - - // - // If the digital comparator status bit is set, reflect it to the - // appropriate sequence bit. - // - if(ui32Temp & 0x10000) - { - ui32Temp |= 0xF0000; - ui32Temp &= ~(0x10000 << ui32SequenceNum); - } - } - - // - // Return the interrupt status - // - return(ui32Temp); -} - -//***************************************************************************** -// -//! Clears sample sequence interrupt source. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! The specified sample sequence interrupt is cleared, so that it no longer -//! asserts. This function must be called in the interrupt handler to keep -//! the interrupt from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Clear the interrupt. - // - HWREG(ui32Base + ADC_O_ISC) = 1 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Enables a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! Allows the specified sample sequence to be captured when its trigger is -//! detected. A sample sequence must be configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Enable the specified sequence. - // - HWREG(ui32Base + ADC_O_ACTSS) |= 1 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Disables a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! Prevents the specified sample sequence from being captured when its trigger -//! is detected. A sample sequence must be disabled before it is configured. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Disable the specified sequences. - // - HWREG(ui32Base + ADC_O_ACTSS) &= ~(1 << ui32SequenceNum); -} - -//***************************************************************************** -// -//! Configures the trigger source and priority of a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param ui32Trigger is the trigger source that initiates the sample -//! sequence; must be one of the \b ADC_TRIGGER_* values. -//! \param ui32Priority is the relative priority of the sample sequence with -//! respect to the other sample sequences. -//! -//! This function configures the initiation criteria for a sample sequence. -//! Valid sample sequencers range from zero to three; sequencer zero captures -//! up to eight samples, sequencers one and two capture up to four samples, -//! and sequencer three captures a single sample. The trigger condition and -//! priority (with respect to other sample sequencer execution) are set. -//! -//! The \e ui32Trigger parameter can take on the following values: -//! -//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the -//! ADCProcessorTrigger() function. -//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port -//! B4 pin. Note that some microcontrollers can -//! select from any GPIO using the -//! GPIOADCTriggerEnable() function. -//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with -//! TimerControlTrigger(). -//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_PWM3 - A trigger generated by the fourth PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the -//! sample sequence to capture repeatedly (so long as -//! there is not a higher priority source active). -//! -//! When \b ADC_TRIGGER_PWM0, \b ADC_TRIGGER_PWM1, \b ADC_TRIGGER_PWM2 or -//! \b ADC_TRIGGER_PWM3 is specified, one of the following should be ORed into -//! \e ui32Trigger to select the PWM module from which the triggers will be -//! routed for this sequence: -//! -//! - \b ADC_TRIGGER_PWM_MOD0 - Selects PWM module 0 as the source of the -//! PWM0 to PWM3 triggers for this sequence. -//! - \b ADC_TRIGGER_PWM_MOD1 - Selects PWM module 1 as the source of the -//! PWM0 to PWM3 triggers for this sequence. -//! -//! Note that not all trigger sources are available on all Tiva family -//! members; consult the data sheet for the device in question to determine the -//! availability of triggers. -//! -//! The \e ui32Priority parameter is a value between 0 and 3, where 0 -//! represents the highest priority and 3 the lowest. Note that when -//! programming the priority among a set of sample sequences, each must have -//! unique priority; it is up to the caller to guarantee the uniqueness of the -//! priorities. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t ui32Trigger, uint32_t ui32Priority) -{ - uint32_t ui32Gen; - - // - // Check the arugments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - ASSERT(((ui32Trigger & 0xF) == ADC_TRIGGER_PROCESSOR) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP0) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP1) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP2) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_EXTERNAL) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_TIMER) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM0) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM1) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM2) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM3) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_ALWAYS) || - ((ui32Trigger & 0x30) == ADC_TRIGGER_PWM_MOD0) || - ((ui32Trigger & 0x30) == ADC_TRIGGER_PWM_MOD1)); - ASSERT(ui32Priority < 4); - - // - // Compute the shift for the bits that control this sample sequence. - // - ui32SequenceNum *= 4; - - // - // Set the trigger event for this sample sequence. - // - HWREG(ui32Base + ADC_O_EMUX) = ((HWREG(ui32Base + ADC_O_EMUX) & - ~(0xf << ui32SequenceNum)) | - ((ui32Trigger & 0xf) << ui32SequenceNum)); - - // - // Set the priority for this sample sequence. - // - HWREG(ui32Base + ADC_O_SSPRI) = ((HWREG(ui32Base + ADC_O_SSPRI) & - ~(0xf << ui32SequenceNum)) | - ((ui32Priority & 0x3) << - ui32SequenceNum)); - - // - // Set the source PWM module for this sequence's PWM triggers. - // - ui32Gen = ui32Trigger & 0x0f; - if(ui32Gen >= ADC_TRIGGER_PWM0 && ui32Gen <= ADC_TRIGGER_PWM3) - { - // - // Set the shift for the module and generator - // - ui32Gen = (ui32Gen - ADC_TRIGGER_PWM0) * 8; - - HWREG(ui32Base + ADC_O_TSSEL) = ((HWREG(ui32Base + ADC_O_TSSEL) & - ~(0x30 << ui32Gen)) | - ((ui32Trigger & 0x30) << ui32Gen)); - } -} - -//***************************************************************************** -// -//! Configure a step of the sample sequencer. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param ui32Step is the step to be configured. -//! \param ui32Config is the configuration of this step; must be a logical OR -//! of \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the -//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH23), and one of -//! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7). -//! -//! This function configures the ADC for one step of a sample sequence. The -//! ADC can be configured for single-ended or differential operation (the -//! \b ADC_CTL_D bit selects differential operation when set), the channel to -//! be sampled can be chosen (the \b ADC_CTL_CH0 through \b ADC_CTL_CH23 -//! values), and the internal temperature sensor can be selected (the -//! \b ADC_CTL_TS bit). Additionally, this step can be defined as the last in -//! the sequence (the \b ADC_CTL_END bit) and it can be configured to cause an -//! interrupt when the step is complete (the \b ADC_CTL_IE bit). If the -//! digital comparators are present on the device, this step may also be -//! configured to send the ADC sample to the selected comparator using -//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7. The configuration is used by the -//! ADC at the appropriate time when the trigger for this sequence occurs. -//! -//! \note If the Digital Comparator is present and enabled using the -//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample is NOT -//! written into the ADC sequence data FIFO. -//! -//! The \e ui32Step parameter determines the order in which the samples are -//! captured by the ADC when the trigger occurs. It can range from zero to -//! seven for the first sample sequencer, from zero to three for the second and -//! third sample sequencer, and can only be zero for the fourth sample -//! sequencer. -//! -//! Differential mode only works with adjacent channel pairs (for example, 0 -//! and 1). The channel select must be the number of the channel pair to -//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 -//! and 3) or undefined results are returned by the ADC. Additionally, if -//! differential mode is selected when the temperature sensor is being sampled, -//! undefined results are returned by the ADC. -//! -//! It is the responsibility of the caller to ensure that a valid configuration -//! is specified; this function does not check the validity of the specified -//! configuration. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t ui32Step, uint32_t ui32Config) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - ASSERT(((ui32SequenceNum == 0) && (ui32Step < 8)) || - ((ui32SequenceNum == 1) && (ui32Step < 4)) || - ((ui32SequenceNum == 2) && (ui32Step < 4)) || - ((ui32SequenceNum == 3) && (ui32Step < 1))); - - // - // Get the offset of the sequence to be configured. - // - ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); - - // - // Compute the shift for the bits that control this step. - // - ui32Step *= 4; - - // - // Set the analog mux value for this step. - // - HWREG(ui32Base + ADC_SSMUX) = ((HWREG(ui32Base + ADC_SSMUX) & - ~(0x0000000f << ui32Step)) | - ((ui32Config & 0x0f) << ui32Step)); - - // - // Set the upper bits of the analog mux value for this step. - // - HWREG(ui32Base + ADC_SSEMUX) = ((HWREG(ui32Base + ADC_SSEMUX) & - ~(0x0000000f << ui32Step)) | - (((ui32Config & 0xf00) >> 8) << ui32Step)); - - // - // Set the control value for this step. - // - HWREG(ui32Base + ADC_SSCTL) = ((HWREG(ui32Base + ADC_SSCTL) & - ~(0x0000000f << ui32Step)) | - (((ui32Config & 0xf0) >> 4) << ui32Step)); - - // - // Set the sample and hold time for this step. This is not available on - // all devices, however on devices that do not support this feature these - // reserved bits are ignored on write access. - // - HWREG(ui32Base + ADC_SSTSH) = ((HWREG(ui32Base + ADC_SSTSH) & - ~(0x0000000f << ui32Step)) | - (((ui32Config & 0xf00000) >> 20) << ui32Step)); - - // - // Enable digital comparator if specified in the ui32Config bit-fields. - // - if(ui32Config & 0x000F0000) - { - // - // Program the comparator for the specified step. - // - ui32Temp = HWREG(ui32Base + ADC_SSDC); - ui32Temp &= ~(0xF << ui32Step); - ui32Temp |= (((ui32Config & 0x00070000) >> 16) << ui32Step); - HWREG(ui32Base + ADC_SSDC) = ui32Temp; - - // - // Enable the comparator. - // - HWREG(ui32Base + ADC_SSOP) |= (1 << ui32Step); - } - - // - // Disable digital comparator if not specified. - // - else - { - HWREG(ui32Base + ADC_SSOP) &= ~(1 << ui32Step); - } -} - -//***************************************************************************** -// -//! Determines if a sample sequence overflow occurred. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function determines if a sample sequence overflow has occurred. -//! Overflow happens if the captured samples are not read from the FIFO before -//! the next trigger occurs. -//! -//! \return Returns zero if there was not an overflow, and non-zero if there -//! was. -// -//***************************************************************************** -int32_t -ADCSequenceOverflow(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Determine if there was an overflow on this sequence. - // - return(HWREG(ui32Base + ADC_O_OSTAT) & (1 << ui32SequenceNum)); -} - -//***************************************************************************** -// -//! Clears the overflow condition on a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function clears an overflow condition on one of the sample sequences. -//! The overflow condition must be cleared in order to detect a subsequent -//! overflow condition (it otherwise causes no harm). -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceOverflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Clear the overflow condition for this sequence. - // - HWREG(ui32Base + ADC_O_OSTAT) = 1 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Determines if a sample sequence underflow occurred. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function determines if a sample sequence underflow has occurred. -//! Underflow happens if too many samples are read from the FIFO. -//! -//! \return Returns zero if there was not an underflow, and non-zero if there -//! was. -// -//***************************************************************************** -int32_t -ADCSequenceUnderflow(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Determine if there was an underflow on this sequence. - // - return(HWREG(ui32Base + ADC_O_USTAT) & (1 << ui32SequenceNum)); -} - -//***************************************************************************** -// -//! Clears the underflow condition on a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function clears an underflow condition on one of the sample -//! sequencers. The underflow condition must be cleared in order to detect a -//! subsequent underflow condition (it otherwise causes no harm). -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceUnderflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Clear the underflow condition for this sequence. - // - HWREG(ui32Base + ADC_O_USTAT) = 1 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Gets the captured data for a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param pui32Buffer is the address where the data is stored. -//! -//! This function copies data from the specified sample sequencer output FIFO -//! to a memory resident buffer. The number of samples available in the -//! hardware FIFO are copied into the buffer, which is assumed to be large -//! enough to hold that many samples. This function only returns the samples -//! that are presently available, which may not be the entire sample sequence -//! if it is in the process of being executed. -//! -//! \return Returns the number of samples copied to the buffer. -// -//***************************************************************************** -int32_t -ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t *pui32Buffer) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Get the offset of the sequence to be read. - // - ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); - - // - // Read samples from the FIFO until it is empty. - // - ui32Count = 0; - while(!(HWREG(ui32Base + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && - (ui32Count < 8)) - { - // - // Read the FIFO and copy it to the destination. - // - *pui32Buffer++ = HWREG(ui32Base + ADC_SSFIFO); - - // - // Increment the count of samples read. - // - ui32Count++; - } - - // - // Return the number of samples read. - // - return(ui32Count); -} - -//***************************************************************************** -// -//! Causes a processor trigger for a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number, with -//! \b ADC_TRIGGER_WAIT or \b ADC_TRIGGER_SIGNAL optionally ORed into it. -//! -//! This function triggers a processor-initiated sample sequence if the sample -//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR. If -//! \b ADC_TRIGGER_WAIT is ORed into the sequence number, the -//! processor-initiated trigger is delayed until a later processor-initiated -//! trigger to a different ADC module that specifies \b ADC_TRIGGER_SIGNAL, -//! allowing multiple ADCs to start from a processor-initiated trigger in a -//! synchronous manner. -//! -//! \return None. -// -//***************************************************************************** -void -ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Generate a processor trigger for this sample sequence. - // - HWREG(ui32Base + ADC_O_PSSI) |= ((ui32SequenceNum & 0xffff0000) | - (1 << (ui32SequenceNum & 0xf))); -} - -//***************************************************************************** -// -//! Configures the software oversampling factor of the ADC. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param ui32Factor is the number of samples to be averaged. -//! -//! This function configures the software oversampling for the ADC, which can -//! be used to provide better resolution on the sampled data. Oversampling is -//! accomplished by averaging multiple samples from the same analog input. -//! Three different oversampling rates are supported; 2x, 4x, and 8x. -//! -//! Oversampling is only supported on the sample sequencers that are more than -//! one sample in depth (that is, the fourth sample sequencer is not -//! supported). Oversampling by 2x (for example) divides the depth of the -//! sample sequencer by two; so 2x oversampling on the first sample sequencer -//! can only provide four samples per trigger. This also means that 8x -//! oversampling is only available on the first sample sequencer. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSoftwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t ui32Factor) -{ - uint32_t ui32Value; - uint32_t ui32ADCInst; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 3); - ASSERT(((ui32Factor == 2) || (ui32Factor == 4) || (ui32Factor == 8)) && - ((ui32SequenceNum == 0) || (ui32Factor != 8))); - - // - // Convert the oversampling factor to a shift factor. - // - for(ui32Value = 0, ui32Factor >>= 1; ui32Factor; - ui32Value++, ui32Factor >>= 1) - { - } - - // - // Evaluate the ADC Instance. - // - if(ui32Base == ADC0_BASE) - { - ui32ADCInst = 0; - } - else - { - ui32ADCInst = 1; - } - - // - // Save the shift factor. - // - g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum] = ui32Value; -} - -//***************************************************************************** -// -//! Configures a step of the software oversampled sequencer. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param ui32Step is the step to be configured. -//! \param ui32Config is the configuration of this step. -//! -//! This function configures a step of the sample sequencer when using the -//! software oversampling feature. The number of steps available depends on -//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value -//! of \e ui32Config is the same as defined for ADCSequenceStepConfigure(). -//! -//! \return None. -// -//***************************************************************************** -void -ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t ui32Step, uint32_t ui32Config) -{ - uint32_t ui32ADCInst; - - // - // Evaluate the ADC Instance. - // - if(ui32Base == ADC0_BASE) - { - ui32ADCInst = 0; - } - else - { - ui32ADCInst = 1; - } - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 3); - ASSERT(((ui32SequenceNum == 0) && - (ui32Step < - (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) || - (ui32Step < - (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))); - - // - // Get the offset of the sequence to be configured. - // - ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); - - // - // Compute the shift for the bits that control this step. - // - ui32Step *= 4 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; - - // - // Loop through the hardware steps that make up this step of the software - // oversampled sequence. - // - for(ui32SequenceNum = - (1 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]); - ui32SequenceNum; ui32SequenceNum--) - { - // - // Set the analog mux value for this step. - // - HWREG(ui32Base + ADC_SSMUX) = ((HWREG(ui32Base + ADC_SSMUX) & - ~(0x0000000f << ui32Step)) | - ((ui32Config & 0x0f) << ui32Step)); - - // - // Set the upper bits of the analog mux value for this step. - // - HWREG(ui32Base + ADC_SSEMUX) = ((HWREG(ui32Base + ADC_SSEMUX) & - ~(0x0000000f << ui32Step)) | - (((ui32Config & 0xf00) >> 8) << - ui32Step)); - - // - // Set the control value for this step. - // - HWREG(ui32Base + ADC_SSCTL) = ((HWREG(ui32Base + ADC_SSCTL) & - ~(0x0000000f << ui32Step)) | - (((ui32Config & 0xf0) >> 4) << - ui32Step)); - if(ui32SequenceNum != 1) - { - HWREG(ui32Base + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 | - ADC_SSCTL0_END0) << ui32Step); - } - - // - // Go to the next hardware step. - // - ui32Step += 4; - } -} - -//***************************************************************************** -// -//! Gets the captured data for a sample sequence using software oversampling. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param pui32Buffer is the address where the data is stored. -//! \param ui32Count is the number of samples to be read. -//! -//! This function copies data from the specified sample sequence output FIFO to -//! a memory resident buffer with software oversampling applied. The requested -//! number of samples are copied into the data buffer; if there are not enough -//! samples in the hardware FIFO to satisfy this many oversampled data items, -//! then incorrect results are returned. It is the caller's responsibility to -//! read only the samples that are available and wait until enough data is -//! available, for example as a result of receiving an interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t *pui32Buffer, uint32_t ui32Count) -{ - uint32_t ui32Idx, ui32Accum; - uint32_t ui32ADCInst; - - // - // Evaluate the ADC Instance. - // - if(ui32Base == ADC0_BASE) - { - ui32ADCInst = 0; - } - else - { - ui32ADCInst = 1; - } - - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 3); - ASSERT(((ui32SequenceNum == 0) && - (ui32Count < - (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) || - (ui32Count < - (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))); - - // - // Get the offset of the sequence to be read. - // - ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); - - // - // Read the samples from the FIFO until it is empty. - // - while(ui32Count--) - { - // - // Compute the sum of the samples. - // - ui32Accum = 0; - for(ui32Idx = 1 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; - ui32Idx; ui32Idx--) - { - // - // Read the FIFO and add it to the accumulator. - // - ui32Accum += HWREG(ui32Base + ADC_SSFIFO); - } - - // - // Write the averaged sample to the output buffer. - // - *pui32Buffer++ = - ui32Accum >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; - } -} - -//***************************************************************************** -// -//! Configures the hardware oversampling factor of the ADC. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Factor is the number of samples to be averaged. -//! -//! This function configures the hardware oversampling for the ADC, which can -//! be used to provide better resolution on the sampled data. Oversampling is -//! accomplished by averaging multiple samples from the same analog input. Six -//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. -//! Specifying an oversampling factor of zero disables hardware -//! oversampling. -//! -//! Hardware oversampling applies uniformly to all sample sequencers. It does -//! not reduce the depth of the sample sequencers like the software -//! oversampling APIs; each sample written into the sample sequencer FIFO is a -//! fully oversampled analog input reading. -//! -//! Enabling hardware averaging increases the precision of the ADC at the cost -//! of throughput. For example, enabling 4x oversampling reduces the -//! throughput of a 250 k samples/second ADC to 62.5 k samples/second. -//! -//! \return None. -// -//***************************************************************************** -void -ADCHardwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32Factor) -{ - uint32_t ui32Value; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(((ui32Factor == 0) || (ui32Factor == 2) || (ui32Factor == 4) || - (ui32Factor == 8) || (ui32Factor == 16) || (ui32Factor == 32) || - (ui32Factor == 64))); - - // - // Convert the oversampling factor to a shift factor. - // - for(ui32Value = 0, ui32Factor >>= 1; ui32Factor; - ui32Value++, ui32Factor >>= 1) - { - } - - // - // Write the shift factor to the ADC to configure the hardware oversampler. - // - HWREG(ui32Base + ADC_O_SAC) = ui32Value; -} - -//***************************************************************************** -// -//! Configures an ADC digital comparator. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Comp is the index of the comparator to configure. -//! \param ui32Config is the configuration of the comparator. -//! -//! This function configures a comparator. The \e ui32Config parameter is -//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and -//! \b ADC_COMP_INT_xxx values. -//! -//! The \b ADC_COMP_TRIG_xxx term can take on the following values: -//! -//! - \b ADC_COMP_TRIG_NONE to never trigger PWM fault condition. -//! - \b ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when -//! ADC output is in the low-band. -//! - \b ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC -//! output transitions into the low-band. -//! - \b ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when -//! ADC output is in the low-band only if ADC output has been in the high-band -//! since the last trigger output. -//! - \b ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC -//! output transitions into low-band only if ADC output has been in the -//! high-band since the last trigger output. -//! - \b ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when -//! ADC output is in the mid-band. -//! - \b ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC -//! output transitions into the mid-band. -//! - \b ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when -//! ADC output is in the high-band. -//! - \b ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC -//! output transitions into the high-band. -//! - \b ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when -//! ADC output is in the high-band only if ADC output has been in the low-band -//! since the last trigger output. -//! - \b ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC -//! output transitions into high-band only if ADC output has been in the -//! low-band since the last trigger output. -//! -//! The \b ADC_COMP_INT_xxx term can take on the following values: -//! -//! - \b ADC_COMP_INT_NONE to never generate ADC interrupt. -//! - \b ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC -//! output is in the low-band. -//! - \b ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output -//! transitions into the low-band. -//! - \b ADC_COMP_INT_LOW_HALWAYS to always generate ADC interrupt when ADC -//! output is in the low-band only if ADC output has been in the high-band -//! since the last trigger output. -//! - \b ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output -//! transitions into low-band only if ADC output has been in the high-band -//! since the last trigger output. -//! - \b ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC -//! output is in the mid-band. -//! - \b ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output -//! transitions into the mid-band. -//! - \b ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC -//! output is in the high-band. -//! - \b ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output -//! transitions into the high-band. -//! - \b ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC -//! output is in the high-band only if ADC output has been in the low-band -//! since the last trigger output. -//! - \b ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output -//! transitions into high-band only if ADC output has been in the low-band -//! since the last trigger output. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, - uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32Comp < 8); - - // - // Save the new setting. - // - HWREG(ui32Base + ADC_O_DCCTL0 + (ui32Comp * 4)) = ui32Config; -} - -//***************************************************************************** -// -//! Defines the ADC digital comparator regions. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Comp is the index of the comparator to configure. -//! \param ui32LowRef is the reference point for the low/mid band threshold. -//! \param ui32HighRef is the reference point for the mid/high band threshold. -//! -//! The ADC digital comparator operation is based on three ADC value regions: -//! - \b low-band is defined as any ADC value less than or equal to the -//! \e ui32LowRef value. -//! - \b mid-band is defined as any ADC value greater than the \e ui32LowRef -//! value but less than or equal to the \e ui32HighRef value. -//! - \b high-band is defined as any ADC value greater than the \e ui32HighRef -//! value. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp, - uint32_t ui32LowRef, uint32_t ui32HighRef) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32Comp < 8); - ASSERT((ui32LowRef < 4096) && (ui32LowRef <= ui32HighRef)); - ASSERT(ui32HighRef < 4096); - - // - // Save the new region settings. - // - HWREG(ui32Base + ADC_O_DCCMP0 + (ui32Comp * 4)) = ((ui32HighRef << 16) | - ui32LowRef); -} - -//***************************************************************************** -// -//! Resets the current ADC digital comparator conditions. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Comp is the index of the comparator. -//! \param bTrigger is the flag to indicate reset of Trigger conditions. -//! \param bInterrupt is the flag to indicate reset of Interrupt conditions. -//! -//! Because the digital comparator uses current and previous ADC values, this -//! function allows the comparator to be reset to its initial -//! value to prevent stale data from being used when a sequence is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp, bool bTrigger, - bool bInterrupt) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32Comp < 8); - - // - // Set the appropriate bits to reset the trigger and/or interrupt - // comparator conditions. - // - ui32Temp = 0; - if(bTrigger) - { - ui32Temp |= (1 << (16 + ui32Comp)); - } - if(bInterrupt) - { - ui32Temp |= (1 << ui32Comp); - } - - HWREG(ui32Base + ADC_O_DCRIC) = ui32Temp; -} - -//***************************************************************************** -// -//! Disables a sample sequence comparator interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function disables the requested sample sequence comparator interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Disable this sample sequence comparator interrupt. - // - HWREG(ui32Base + ADC_O_IM) &= ~(0x10000 << ui32SequenceNum); -} - -//***************************************************************************** -// -//! Enables a sample sequence comparator interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function enables the requested sample sequence comparator interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Enable this sample sequence interrupt. - // - HWREG(ui32Base + ADC_O_IM) |= 0x10000 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Gets the current comparator interrupt status. -//! -//! \param ui32Base is the base address of the ADC module. -//! -//! This function returns the digital comparator interrupt status bits. This -//! status is sequence agnostic. -//! -//! \return The current comparator interrupt status. -// -//***************************************************************************** -uint32_t -ADCComparatorIntStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Return the digital comparator interrupt status. - // - return(HWREG(ui32Base + ADC_O_DCISC)); -} - -//***************************************************************************** -// -//! Clears sample sequence comparator interrupt source. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Status is the bit-mapped interrupts status to clear. -//! -//! The specified interrupt status is cleared. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Clear the interrupt. - // - HWREG(ui32Base + ADC_O_DCISC) = ui32Status; -} - -//***************************************************************************** -// -//! Disables ADC interrupt sources. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. -//! -//! This function disables the indicated ADC interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b ADC_INT_SS0 - interrupt due to ADC sample sequence 0. -//! - \b ADC_INT_SS1 - interrupt due to ADC sample sequence 1. -//! - \b ADC_INT_SS2 - interrupt due to ADC sample sequence 2. -//! - \b ADC_INT_SS3 - interrupt due to ADC sample sequence 3. -//! - \b ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0. -//! - \b ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1. -//! - \b ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2. -//! - \b ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3. -//! - \b ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample -//! sequence 0. -//! - \b ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample -//! sequence 1. -//! - \b ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample -//! sequence 2. -//! - \b ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample -//! sequence 3. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Disable the requested interrupts. - // - HWREG(ui32Base + ADC_O_IM) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Enables ADC interrupt sources. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. -//! -//! This function enables the indicated ADC interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b ADC_INT_SS0 - interrupt due to ADC sample sequence 0. -//! - \b ADC_INT_SS1 - interrupt due to ADC sample sequence 1. -//! - \b ADC_INT_SS2 - interrupt due to ADC sample sequence 2. -//! - \b ADC_INT_SS3 - interrupt due to ADC sample sequence 3. -//! - \b ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0. -//! - \b ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1. -//! - \b ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2. -//! - \b ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3. -//! - \b ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample -//! sequence 0. -//! - \b ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample -//! sequence 1. -//! - \b ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample -//! sequence 2. -//! - \b ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample -//! sequence 3. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Enable the requested interrupts. - // - HWREG(ui32Base + ADC_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets interrupt status for the specified ADC module. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status is returned. -//! -//! \return Returns the current interrupt status for the specified ADC module. -//! The value returned is the logical OR of the \b ADC_INT_* values that are -//! currently active. -// -//***************************************************************************** -uint32_t -ADCIntStatusEx(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Return either the masked interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - ui32Temp = HWREG(ui32Base + ADC_O_ISC); - } - else - { - // - // Read the Raw interrupt status to see if a digital comparator - // interrupt is active. - // - ui32Temp = HWREG(ui32Base + ADC_O_RIS); - - // - // Since, the raw interrupt status only indicates that any one of the - // digital comparators caused an interrupt, if the raw interrupt status - // is set then the return value is modified to indicate that all sample - // sequences have a pending digital comparator interrupt. - // This is exactly how the hardware works so the return code is - // modified to match this behavior. - // - if(ui32Temp & ADC_RIS_INRDC) - { - ui32Temp |= (ADC_INT_DCON_SS3 | ADC_INT_DCON_SS2 | - ADC_INT_DCON_SS1 | ADC_INT_DCON_SS0); - } - } - return(ui32Temp); -} - -//***************************************************************************** -// -//! Clears the specified ADC interrupt sources. -//! -//! \param ui32Base is the base address of the ADC port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. -//! -//! Clears the interrupt for the specified interrupt source(s). -//! -//! The \e ui32IntFlags parameter is the logical OR of the \b ADC_INT_* values. -//! See the ADCIntEnableEx() function for the list of possible \b ADC_INT* -//! values. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Note: The interrupt bits are "W1C" so we DO NOT use a logical OR - // here to clear the requested bits. Doing so would clear all outstanding - // interrupts rather than just those which the caller has specified. - // - HWREG(ui32Base + ADC_O_ISC) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Selects the ADC reference. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Ref is the reference to use. -//! -//! The ADC reference is set as specified by \e ui32Ref. It must be one of -//! \b ADC_REF_INT, or \b ADC_REF_EXT_3V for internal or external reference -//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and -//! no external reference is needed. If \b ADC_REF_EXT_3V is chosen, then -//! a 3V reference must be supplied to the AVREF pin. -//! -//! \note The ADC reference can only be selected on parts that have an external -//! reference. Consult the data sheet for your part to determine if there is -//! an external reference. -//! -//! \return None. -// -//***************************************************************************** -void -ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT((ui32Ref == ADC_REF_INT) || (ui32Ref == ADC_REF_EXT_3V)); - - // - // Set the reference. - // - HWREG(ui32Base + ADC_O_CTL) = - (HWREG(ui32Base + ADC_O_CTL) & ~ADC_CTL_VREF_M) | ui32Ref; -} - -//***************************************************************************** -// -//! Returns the current setting of the ADC reference. -//! -//! \param ui32Base is the base address of the ADC module. -//! -//! Returns the value of the ADC reference setting. The returned value is one -//! of \b ADC_REF_INT, or \b ADC_REF_EXT_3V. -//! -//! \note The value returned by this function is only meaningful if used on a -//! part that is capable of using an external reference. Consult the data -//! sheet for your part to determine if it has an external reference input. -//! -//! \return The current setting of the ADC reference. -// -//***************************************************************************** -uint32_t -ADCReferenceGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Return the value of the reference. - // - return(HWREG(ui32Base + ADC_O_CTL) & ADC_CTL_VREF_M); -} - -//***************************************************************************** -// -//! Sets the phase delay between a trigger and the start of a sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Phase is the phase delay, specified as one of \b ADC_PHASE_0, -//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90, -//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180, -//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270, -//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5. -//! -//! This function sets the phase delay between the detection of an ADC trigger -//! event and the start of the sample sequence. By selecting a different phase -//! delay for a pair of ADC modules (such as \b ADC_PHASE_0 and -//! \b ADC_PHASE_180) and having each ADC module sample the same analog input, -//! it is possible to increase the sampling rate of the analog input (with -//! samples N, N+2, N+4, and so on, coming from the first ADC and samples N+1, -//! N+3, N+5, and so on, coming from the second ADC). The ADC module has a -//! single phase delay that is applied to all sample sequences within that -//! module. -//! -//! \note This capability is not available on all parts. -//! -//! \return None. -// -//***************************************************************************** -void -ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT((ui32Phase == ADC_PHASE_0) || (ui32Phase == ADC_PHASE_22_5) || - (ui32Phase == ADC_PHASE_45) || (ui32Phase == ADC_PHASE_67_5) || - (ui32Phase == ADC_PHASE_90) || (ui32Phase == ADC_PHASE_112_5) || - (ui32Phase == ADC_PHASE_135) || (ui32Phase == ADC_PHASE_157_5) || - (ui32Phase == ADC_PHASE_180) || (ui32Phase == ADC_PHASE_202_5) || - (ui32Phase == ADC_PHASE_225) || (ui32Phase == ADC_PHASE_247_5) || - (ui32Phase == ADC_PHASE_270) || (ui32Phase == ADC_PHASE_292_5) || - (ui32Phase == ADC_PHASE_315) || (ui32Phase == ADC_PHASE_337_5)); - - // - // Set the phase delay. - // - HWREG(ui32Base + ADC_O_SPC) = ui32Phase; -} - -//***************************************************************************** -// -//! Gets the phase delay between a trigger and the start of a sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! -//! This function gets the current phase delay between the detection of an ADC -//! trigger event and the start of the sample sequence. -//! -//! \return Returns the phase delay, specified as one of \b ADC_PHASE_0, -//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90, -//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180, -//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270, -//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5. -// -//***************************************************************************** -uint32_t -ADCPhaseDelayGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Return the phase delay. - // - return(HWREG(ui32Base + ADC_O_SPC)); -} - -//***************************************************************************** -// -//! Enables DMA for sample sequencers. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! Allows DMA requests to be generated based on the FIFO level of the sample -//! sequencer. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Enable the DMA on the specified sequencer. - // - HWREG(ui32Base + ADC_O_ACTSS) |= 0x100 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Disables DMA for sample sequencers. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! Prevents the specified sample sequencer from generating DMA requests. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Disable the DMA on the specified sequencer. - // - HWREG(ui32Base + ADC_O_ACTSS) &= ~(0x100 << ui32SequenceNum); -} - -//***************************************************************************** -// -//! Determines whether the ADC is busy or not. -//! -//! \param ui32Base is the base address of the ADC. -//! -//! This function allows the caller to determine whether or not the ADC is -//! currently sampling . If \b false is returned, then the ADC is not -//! sampling data. -//! -//! Use this function to detect that the ADC is finished sampling data before -//! putting the device into deep sleep. Before using this function, it is -//! highly recommended that the event trigger is changed to -//! \b ADC_TRIGGER_NEVER on all enabled sequencers to prevent the ADC from -//! starting after checking the busy status. -//! -//! \return Returns \b true if the ADC is sampling or \b false if all -//! samples are complete. -// -//***************************************************************************** -bool -ADCBusy(uint32_t ui32Base) -{ - // - // Check the argument. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Determine if the ADC is busy. - // - return((HWREG(ui32Base + ADC_O_ACTSS) & ADC_ACTSS_BUSY) ? true : false); -} - -//***************************************************************************** -// -//! Sets the clock configuration for the ADC. -//! -//! \param ui32Base is the base address of the ADC to configure, which must -//! always be \b ADC0_BASE. -//! \param ui32Config is a combination of the \b ADC_CLOCK_SRC_ and -//! \b ADC_CLOCK_RATE_* values used to configure the ADC clock input. -//! \param ui32ClockDiv is the input clock divider for the clock selected by -//! the \b ADC_CLOCK_SRC value. -//! -//! This function is used to configure the input clock to the ADC modules. The -//! clock configuration is shared across ADC units so \e ui32Base must -//! always be \b ADC0_BASE. The \e ui32Config value is logical OR of one -//! of the \b ADC_CLOCK_RATE_ and one of the \b ADC_CLOCK_SRC_ values defined -//! below. The \b ADC_CLOCK_SRC_* values determine the input clock for the ADC. -//! Not all values are available on all devices so check the device data sheet -//! to determine value configuration options. Regardless of the source, the -//! final frequency for TM4C123x devices must be 16 MHz and for TM4C129x parts -//! after dividing must be between 16 and 32 MHz. -//! -//! \note For TM4C123x devices, if the PLL is enabled, the PLL/25 is used as -//! the ADC clock unless ADC_CLOCK_SRC_PIOSC is specified. If the PLL is -//! disabled, the MOSC is used as the clock source unless ADC_CLOCK_SRC_PIOSC -//! is specified. -//! -//! - \b ADC_CLOCK_SRC_PLL - The main PLL output (TM4x129 class only). -//! - \b ADC_CLOCK_SRC_PIOSC - The internal PIOSC at 16 MHz. -//! - \b ADC_CLOCK_SRC_ALTCLK - The output of the ALTCLK in the system control -//! module (TM4x129 class only). -//! - \b ADC_CLOCK_SRC_MOSC - The external MOSC (TM4x129 class only). -//! -//! \b ADC_CLOCK_RATE values control how often samples are provided back to the -//! application. The values are the following: -//! -//! - \b ADC_CLOCK_RATE_FULL - All samples. -//! - \b ADC_CLOCK_RATE_HALF - Every other sample. -//! - \b ADC_CLOCK_RATE_QUARTER - Every fourth sample. -//! - \b ADC_CLOCK_RATE_EIGHTH - Every either sample. -//! -//! The \e ui32ClockDiv parameter allows for dividing a higher frequency down -//! into the valid range for the ADCs. This parameter is typically only used -//! \b ADC_CLOCK_SRC_PLL option because it is the only clock value that can be -//! with the in the correct range to use the divider. The actual value ranges -//! from 1 to 64. -//! -//! \b Example: ADC Clock Configurations -//! -//! \verbatim -//! -//! // -//! // Configure the ADC to use PIOSC divided by one (16 MHz) and sample at -//! // half the rate. -//! // -//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_HALF, 1); -//! -//! ... -//! -//! // -//! // Configure the ADC to use PLL at 480 MHz divided by 24 to get an ADC -//! // clock of 20 MHz. -//! // -//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 24); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32ClockDiv) -{ - // - // Check the argument. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT((ui32ClockDiv - 1) <= (ADC_CC_CLKDIV_M >> ADC_CC_CLKDIV_S)); - - // - // A rate must be supplied. - // - ASSERT((ui32Config & ADC_CLOCK_RATE_FULL) != 0); - - // - // Write the sample conversion rate. - // - HWREG(ui32Base + ADC_O_PC) = (ui32Config >> 4) & ADC_PC_SR_M; - - // - // Write the clock select and divider. - // - HWREG(ui32Base + ADC_O_CC) = (ui32Config & ADC_CC_CS_M) | - (((ui32ClockDiv - 1) << ADC_CC_CLKDIV_S)) ; -} - -//***************************************************************************** -// -//! Returns the clock configuration for the ADC. -//! -//! \param ui32Base is the base address of the ADC to configure, which must -//! always be \b ADC0_BASE. -//! \param pui32ClockDiv is a pointer to the input clock divider for the clock -//! selected by the \b ADC_CLOCK_SRC in use by the ADCs. -//! -//! This function returns the ADC clock configuration and the clock divider for -//! the ADCs. -//! -//! \b Example: Read the current ADC clock configuration. -//! -//! \verbatim -//! uint32_t ui32Config, ui32ClockDiv; -//! -//! // -//! // Read the current ADC clock configuration. -//! // -//! ui32Config = ADCClockConfigGet(ADC0_BASE, &ui32ClockDiv); -//! \endverbatim -//! -//! \return The current clock configuration of the ADC defined as a combination -//! of one of \b ADC_CLOCK_SRC_PLL, \b ADC_CLOCK_SRC_PIOSC, -//! \b ADC_CLOCK_SRC_MOSC, or \b ADC_CLOCK_SRC_ALTCLK logical ORed with one of -//! \b ADC_CLOCK_RATE_FULL, \b ADC_CLOCK_RATE_HALF, \b ADC_CLOCK_RATE_QUARTER, -//! or \b ADC_CLOCK_RATE_EIGHTH. See ADCClockConfigSet() for more information -//! on these values. -// -//***************************************************************************** -uint32_t -ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv) -{ - uint32_t ui32Config; - - // - // Check the argument. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Read the current configuration. - // - ui32Config = HWREG(ui32Base + ADC_O_CC); - - // - // If the clock divider was requested provide the current value. - // - if(pui32ClockDiv) - { - *pui32ClockDiv = - ((ui32Config & ADC_CC_CLKDIV_M) >> ADC_CC_CLKDIV_S) + 1; - } - - // - // Clear out the divider bits. - // - ui32Config &= ~ADC_CC_CLKDIV_M; - - // - // Add in the sample interval to the configuration. - // - ui32Config |= (HWREG(ui32Base + ADC_O_PC) & ADC_PC_SR_M) << 4; - - return(ui32Config); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/adc.h b/bsp/tm4c129x-dk/libraries/driverlib/adc.h deleted file mode 100644 index 993b6a3fb5798570edde64667e78aa9a69f67479..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/adc.h +++ /dev/null @@ -1,327 +0,0 @@ -//***************************************************************************** -// -// adc.h - ADC headers for using the ADC driver functions. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_ADC_H__ -#define __DRIVERLIB_ADC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceConfigure as the ui32Trigger -// parameter. -// -//***************************************************************************** -#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event -#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event -#define ADC_TRIGGER_TIMER 0x00000005 // Timer event -#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event -#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event -#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event -#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event -#define ADC_TRIGGER_NEVER 0x0000000E // Never Trigger -#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event -#define ADC_TRIGGER_PWM_MOD0 0x00000000 // PWM triggers from PWM0 -#define ADC_TRIGGER_PWM_MOD1 0x00000010 // PWM triggers from PWM1 - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceStepConfigure as the ui32Config -// parameter. -// -//***************************************************************************** -#define ADC_CTL_TS 0x00000080 // Temperature sensor select -#define ADC_CTL_IE 0x00000040 // Interrupt enable -#define ADC_CTL_END 0x00000020 // Sequence end select -#define ADC_CTL_D 0x00000010 // Differential select -#define ADC_CTL_CH0 0x00000000 // Input channel 0 -#define ADC_CTL_CH1 0x00000001 // Input channel 1 -#define ADC_CTL_CH2 0x00000002 // Input channel 2 -#define ADC_CTL_CH3 0x00000003 // Input channel 3 -#define ADC_CTL_CH4 0x00000004 // Input channel 4 -#define ADC_CTL_CH5 0x00000005 // Input channel 5 -#define ADC_CTL_CH6 0x00000006 // Input channel 6 -#define ADC_CTL_CH7 0x00000007 // Input channel 7 -#define ADC_CTL_CH8 0x00000008 // Input channel 8 -#define ADC_CTL_CH9 0x00000009 // Input channel 9 -#define ADC_CTL_CH10 0x0000000A // Input channel 10 -#define ADC_CTL_CH11 0x0000000B // Input channel 11 -#define ADC_CTL_CH12 0x0000000C // Input channel 12 -#define ADC_CTL_CH13 0x0000000D // Input channel 13 -#define ADC_CTL_CH14 0x0000000E // Input channel 14 -#define ADC_CTL_CH15 0x0000000F // Input channel 15 -#define ADC_CTL_CH16 0x00000100 // Input channel 16 -#define ADC_CTL_CH17 0x00000101 // Input channel 17 -#define ADC_CTL_CH18 0x00000102 // Input channel 18 -#define ADC_CTL_CH19 0x00000103 // Input channel 19 -#define ADC_CTL_CH20 0x00000104 // Input channel 20 -#define ADC_CTL_CH21 0x00000105 // Input channel 21 -#define ADC_CTL_CH22 0x00000106 // Input channel 22 -#define ADC_CTL_CH23 0x00000107 // Input channel 23 -#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0 -#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1 -#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2 -#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3 -#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4 -#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5 -#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6 -#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7 -#define ADC_CTL_SHOLD_4 0x00000000 // Sample and hold 4 ADC clocks -#define ADC_CTL_SHOLD_8 0x00200000 // Sample and hold 8 ADC clocks -#define ADC_CTL_SHOLD_16 0x00400000 // Sample and hold 16 ADC clocks -#define ADC_CTL_SHOLD_32 0x00600000 // Sample and hold 32 ADC clocks -#define ADC_CTL_SHOLD_64 0x00800000 // Sample and hold 64 ADC clocks -#define ADC_CTL_SHOLD_128 0x00A00000 // Sample and hold 128 ADC clocks -#define ADC_CTL_SHOLD_256 0x00C00000 // Sample and hold 256 ADC clocks - -//***************************************************************************** -// -// Values that can be passed to ADCComparatorConfigure as part of the -// ui32Config parameter. -// -//***************************************************************************** -#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled -#define ADC_COMP_TRIG_LOW_ALWAYS \ - 0x00001000 // Trigger Low Always -#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once -#define ADC_COMP_TRIG_LOW_HALWAYS \ - 0x00001200 // Trigger Low Always (Hysteresis) -#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis) -#define ADC_COMP_TRIG_MID_ALWAYS \ - 0x00001400 // Trigger Mid Always -#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once -#define ADC_COMP_TRIG_HIGH_ALWAYS \ - 0x00001C00 // Trigger High Always -#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once -#define ADC_COMP_TRIG_HIGH_HALWAYS \ - 0x00001E00 // Trigger High Always (Hysteresis) -#define ADC_COMP_TRIG_HIGH_HONCE \ - 0x00001F00 // Trigger High Once (Hysteresis) - -#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled -#define ADC_COMP_INT_LOW_ALWAYS \ - 0x00000010 // Interrupt Low Always -#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once -#define ADC_COMP_INT_LOW_HALWAYS \ - 0x00000012 // Interrupt Low Always - // (Hysteresis) -#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis) -#define ADC_COMP_INT_MID_ALWAYS \ - 0x00000014 // Interrupt Mid Always -#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once -#define ADC_COMP_INT_HIGH_ALWAYS \ - 0x0000001C // Interrupt High Always -#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once -#define ADC_COMP_INT_HIGH_HALWAYS \ - 0x0000001E // Interrupt High Always - // (Hysteresis) -#define ADC_COMP_INT_HIGH_HONCE \ - 0x0000001F // Interrupt High Once (Hysteresis) - -//***************************************************************************** -// -// Values that can be used to modify the sequence number passed to -// ADCProcessorTrigger in order to get cross-module synchronous processor -// triggers. -// -//***************************************************************************** -#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger -#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger - -//***************************************************************************** -// -// Values that can be passed to ADCPhaseDelaySet as the ui32Phase parameter and -// returned from ADCPhaseDelayGet. -// -//***************************************************************************** -#define ADC_PHASE_0 0x00000000 // 0 degrees -#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees -#define ADC_PHASE_45 0x00000002 // 45 degrees -#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees -#define ADC_PHASE_90 0x00000004 // 90 degrees -#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees -#define ADC_PHASE_135 0x00000006 // 135 degrees -#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees -#define ADC_PHASE_180 0x00000008 // 180 degrees -#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees -#define ADC_PHASE_225 0x0000000A // 225 degrees -#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees -#define ADC_PHASE_270 0x0000000C // 270 degrees -#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees -#define ADC_PHASE_315 0x0000000E // 315 degrees -#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees - -//***************************************************************************** -// -// Values that can be passed to ADCReferenceSet as the ui32Ref parameter. -// -//***************************************************************************** -#define ADC_REF_INT 0x00000000 // Internal reference -#define ADC_REF_EXT_3V 0x00000001 // External 3V reference - -//***************************************************************************** -// -// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(), -// ADCIntClearEx() and ADCIntStatusEx(). -// -//***************************************************************************** -#define ADC_INT_SS0 0x00000001 -#define ADC_INT_SS1 0x00000002 -#define ADC_INT_SS2 0x00000004 -#define ADC_INT_SS3 0x00000008 -#define ADC_INT_DMA_SS0 0x00000100 -#define ADC_INT_DMA_SS1 0x00000200 -#define ADC_INT_DMA_SS2 0x00000400 -#define ADC_INT_DMA_SS3 0x00000800 -#define ADC_INT_DCON_SS0 0x00010000 -#define ADC_INT_DCON_SS1 0x00020000 -#define ADC_INT_DCON_SS2 0x00040000 -#define ADC_INT_DCON_SS3 0x00080000 - -//***************************************************************************** -// -// Values that can be passed to ADCClockConfigSet() and ADCClockConfigGet(). -// -//***************************************************************************** -#define ADC_CLOCK_RATE_FULL 0x00000070 -#define ADC_CLOCK_RATE_HALF 0x00000050 -#define ADC_CLOCK_RATE_FOURTH 0x00000030 -#define ADC_CLOCK_RATE_EIGHTH 0x00000010 -#define ADC_CLOCK_SRC_PLL 0x00000000 -#define ADC_CLOCK_SRC_PIOSC 0x00000001 -#define ADC_CLOCK_SRC_ALTCLK 0x00000001 -#define ADC_CLOCK_SRC_MOSC 0x00000002 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern uint32_t ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum, - bool bMasked); -extern void ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t ui32Trigger, uint32_t ui32Priority); -extern void ADCSequenceStepConfigure(uint32_t ui32Base, - uint32_t ui32SequenceNum, - uint32_t ui32Step, uint32_t ui32Config); -extern int32_t ADCSequenceOverflow(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern void ADCSequenceOverflowClear(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern int32_t ADCSequenceUnderflow(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern void ADCSequenceUnderflowClear(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern int32_t ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t *pui32Buffer); -extern void ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCSoftwareOversampleConfigure(uint32_t ui32Base, - uint32_t ui32SequenceNum, - uint32_t ui32Factor); -extern void ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, - uint32_t ui32SequenceNum, - uint32_t ui32Step, - uint32_t ui32Config); -extern void ADCSoftwareOversampleDataGet(uint32_t ui32Base, - uint32_t ui32SequenceNum, - uint32_t *pui32Buffer, - uint32_t ui32Count); -extern void ADCHardwareOversampleConfigure(uint32_t ui32Base, - uint32_t ui32Factor); -extern void ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32ClockDiv); -extern uint32_t ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv); - -extern void ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, - uint32_t ui32Config); -extern void ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp, - uint32_t ui32LowRef, uint32_t ui32HighRef); -extern void ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp, - bool bTrigger, bool bInterrupt); -extern void ADCComparatorIntDisable(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern void ADCComparatorIntEnable(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern uint32_t ADCComparatorIntStatus(uint32_t ui32Base); -extern void ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status); -extern void ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t ADCIntStatusEx(uint32_t ui32Base, bool bMasked); -extern void ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern bool ADCBusy(uint32_t ui32Base); -extern void ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref); -extern uint32_t ADCReferenceGet(uint32_t ui32Base); -extern void ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase); -extern uint32_t ADCPhaseDelayGet(uint32_t ui32Base); -extern void ADCSampleRateSet(uint32_t ui32Base, uint32_t ui32ADCClock, - uint32_t ui32Rate); -extern uint32_t ADCSampleRateGet(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_ADC_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/aes.c b/bsp/tm4c129x-dk/libraries/driverlib/aes.c deleted file mode 100644 index 06cf55bb0b10d8cc40b7ee422236404fcccb7574..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/aes.c +++ /dev/null @@ -1,1305 +0,0 @@ -//***************************************************************************** -// -// aes.c - Driver for the AES module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup aes_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include -#include "inc/hw_aes.h" -#include "inc/hw_ccm.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "driverlib/aes.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -//! Resets the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! -//! This function performs a softreset the AES module. -//! -//! \return None. -// -//***************************************************************************** -void -AESReset(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Trigger the reset. - // - HWREG(ui32Base + AES_O_SYSCONFIG) |= AES_SYSCONFIG_SOFTRESET; - - // - // Wait for the reset to finish. - // - while((HWREG(ui32Base + AES_O_SYSSTATUS) & - AES_SYSSTATUS_RESETDONE) == 0) - { - } -} - -//***************************************************************************** -// -//! Configures the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Config is the configuration of the AES module. -//! -//! This function configures the AES module based on the specified parameters. -//! It does not change any DMA- or interrupt-related parameters. -//! -//! The ui32Config parameter is a bit-wise OR of a number of configuration -//! flags. The valid flags are grouped based on their function. -//! -//! The direction of the operation is specified with only of following flags: -//! -//! - \b AES_CFG_DIR_ENCRYPT - Encryption mode -//! - \b AES_CFG_DIR_DECRYPT - Decryption mode -//! -//! The key size is specified with only one of the following flags: -//! -//! - \b AES_CFG_KEY_SIZE_128BIT - Key size of 128 bits -//! - \b AES_CFG_KEY_SIZE_192BIT - Key size of 192 bits -//! - \b AES_CFG_KEY_SIZE_256BIT - Key size of 256 bits -//! -//! The mode of operation is specified with only one of the following flags. -//! -//! - \b AES_CFG_MODE_ECB - Electronic codebook mode -//! - \b AES_CFG_MODE_CBC - Cipher-block chaining mode -//! - \b AES_CFG_MODE_CFB - Cipher feedback mode -//! - \b AES_CFG_MODE_CTR - Counter mode -//! - \b AES_CFG_MODE_ICM - Integer counter mode -//! - \b AES_CFG_MODE_XTS - Ciphertext stealing mode -//! - \b AES_CFG_MODE_XTS_TWEAKJL - XEX-based tweaked-codebook mode with -//! ciphertext stealing with previous/intermediate tweak value and j loaded -//! - \b AES_CFG_MODE_XTS_K2IJL - XEX-based tweaked-codebook mode with -//! ciphertext stealing with key2, i and j loaded -//! - \b AES_CFG_MODE_XTS_K2ILJ0 - XEX-based tweaked-codebook mode with -//! ciphertext stealing with key2 and i loaded, j = 0 -//! - \b AES_CFG_MODE_F8 - F8 mode -//! - \b AES_CFG_MODE_F9 - F9 mode -//! - \b AES_CFG_MODE_CBCMAC - Cipher block chaining message authentication -//! code mode -//! - \b AES_CFG_MODE_GCM_HLY0ZERO - Galois/counter mode with GHASH with H -//! loaded, Y0-encrypted forced to zero and counter is not enabled. -//! - \b AES_CFG_MODE_GCM_HLY0CALC - Galois/counter mode with GHASH with H -//! loaded, Y0-encrypted calculated internally and counter is enabled. -//! - \b AES_CFG_MODE_GCM_HY0CALC - Galois/Counter mode with autonomous GHASH -//! (both H and Y0-encrypted calculated internally) and counter is enabled. -//! - \b AES_CFG_MODE_CCM - Counter with CBC-MAC mode -//! -//! The following defines are used to specify the counter width. It is only -//! required to be defined when using CTR, CCM, or GCM modes, only one of the -//! following defines must be used to specify the counter width length: -//! -//! - \b AES_CFG_CTR_WIDTH_32 - Counter is 32 bits -//! - \b AES_CFG_CTR_WIDTH_64 - Counter is 64 bits -//! - \b AES_CFG_CTR_WIDTH_96 - Counter is 96 bits -//! - \b AES_CFG_CTR_WIDTH_128 - Counter is 128 bits -//! -//! Only one of the following defines must be used to specify the length field -//! for CCM operations (L): -//! -//! - \b AES_CFG_CCM_L_1 - 1 byte -//! - \b AES_CFG_CCM_L_2 - 2 bytes -//! - \b AES_CFG_CCM_L_3 - 3 bytes -//! - \b AES_CFG_CCM_L_4 - 4 bytes -//! - \b AES_CFG_CCM_L_5 - 5 bytes -//! - \b AES_CFG_CCM_L_6 - 6 bytes -//! - \b AES_CFG_CCM_L_7 - 7 bytes -//! - \b AES_CFG_CCM_L_8 - 8 bytes -//! -//! Only one of the following defines must be used to specify the length of the -//! authentication field for CCM operations (M) through the \e ui32Config -//! argument in the AESConfigSet() function: -//! -//! - \b AES_CFG_CCM_M_4 - 4 bytes -//! - \b AES_CFG_CCM_M_6 - 6 bytes -//! - \b AES_CFG_CCM_M_8 - 8 bytes -//! - \b AES_CFG_CCM_M_10 - 10 bytes -//! - \b AES_CFG_CCM_M_12 - 12 bytes -//! - \b AES_CFG_CCM_M_14 - 14 bytes -//! - \b AES_CFG_CCM_M_16 - 16 bytes -//! -//! \note When performing a basic GHASH operation for used with GCM mode, use -//! the \b AES_CFG_MODE_GCM_HLY0ZERO and do not specify a direction. -//! -//! \return None. -// -//***************************************************************************** -void -AESConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Config & AES_CFG_DIR_ENCRYPT) || - (ui32Config & AES_CFG_DIR_DECRYPT)); - ASSERT((ui32Config & AES_CFG_KEY_SIZE_128BIT) || - (ui32Config & AES_CFG_KEY_SIZE_192BIT) || - (ui32Config & AES_CFG_KEY_SIZE_256BIT)); - ASSERT((ui32Config & AES_CFG_MODE_ECB) || - (ui32Config & AES_CFG_MODE_CBC) || - (ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_ICM) || - (ui32Config & AES_CFG_MODE_CFB) || - (ui32Config & AES_CFG_MODE_XTS_TWEAKJL) || - (ui32Config & AES_CFG_MODE_XTS_K2IJL) || - (ui32Config & AES_CFG_MODE_XTS_K2ILJ0) || - (ui32Config & AES_CFG_MODE_F8) || - (ui32Config & AES_CFG_MODE_F9) || - (ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_CBCMAC) || - (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || - (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || - (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || - (ui32Config & AES_CFG_MODE_CCM)); - ASSERT(((ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || - (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || - (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || - (ui32Config & AES_CFG_MODE_CCM)) && - ((ui32Config & AES_CFG_CTR_WIDTH_32) || - (ui32Config & AES_CFG_CTR_WIDTH_64) || - (ui32Config & AES_CFG_CTR_WIDTH_96) || - (ui32Config & AES_CFG_CTR_WIDTH_128))); - ASSERT((ui32Config & AES_CFG_MODE_CCM) && - ((ui32Config & AES_CFG_CCM_L_1) || - (ui32Config & AES_CFG_CCM_L_2) || - (ui32Config & AES_CFG_CCM_L_3) || - (ui32Config & AES_CFG_CCM_L_4) || - (ui32Config & AES_CFG_CCM_L_5) || - (ui32Config & AES_CFG_CCM_L_6) || - (ui32Config & AES_CFG_CCM_L_7) || - (ui32Config & AES_CFG_CCM_L_8)) && - ((ui32Config & AES_CFG_CCM_M_4) || - (ui32Config & AES_CFG_CCM_M_6) || - (ui32Config & AES_CFG_CCM_M_8) || - (ui32Config & AES_CFG_CCM_M_10) || - (ui32Config & AES_CFG_CCM_M_12) || - (ui32Config & AES_CFG_CCM_M_14) || - (ui32Config & AES_CFG_CCM_M_16))); - - // - // Backup the save context field before updating the register. - // - if(HWREG(ui32Base + AES_O_CTRL) & AES_CTRL_SAVE_CONTEXT) - { - ui32Config |= AES_CTRL_SAVE_CONTEXT; - } - - // - // Write the CTRL register with the new value - // - HWREG(ui32Base + AES_O_CTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Writes the key 1 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui32Key is an array of 32-bit words, containing the key to be -//! configured. The least significant word in the 0th index. -//! \param ui32Keysize is the size of the key, which must be one of the -//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or -//! \b AES_CFG_KEY_SIZE_256. -//! -//! This function writes key 1 configuration registers based on the key -//! size. This function is used in all modes. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey1Set(uint32_t ui32Base, uint32_t *pui32Key, uint32_t ui32Keysize) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); - - // - // With all key sizes, the first 4 words are written. - // - HWREG(ui32Base + AES_O_KEY1_0) = pui32Key[0]; - HWREG(ui32Base + AES_O_KEY1_1) = pui32Key[1]; - HWREG(ui32Base + AES_O_KEY1_2) = pui32Key[2]; - HWREG(ui32Base + AES_O_KEY1_3) = pui32Key[3]; - - // - // The key is 192 or 256 bits. Write the next 2 words. - // - if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) - { - HWREG(ui32Base + AES_O_KEY1_4) = pui32Key[4]; - HWREG(ui32Base + AES_O_KEY1_5) = pui32Key[5]; - } - - // - // The key is 256 bits. Write the last 2 words. - // - if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) - { - HWREG(ui32Base + AES_O_KEY1_6) = pui32Key[6]; - HWREG(ui32Base + AES_O_KEY1_7) = pui32Key[7]; - } -} - -//***************************************************************************** -// -//! Writes the key 2 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui32Key is an array of 32-bit words, containing the key to be -//! configured. The least significant word in the 0th index. -//! \param ui32Keysize is the size of the key, which must be one of the -//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or -//! \b AES_CFG_KEY_SIZE_256. -//! -//! This function writes the key 2 configuration registers based on the key -//! size. This function is used in the F8, F9, XTS, CCM, and CBC-MAC modes. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey2Set(uint32_t ui32Base, uint32_t *pui32Key, uint32_t ui32Keysize) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); - - // - // With all key sizes, the first 4 words are written. - // - HWREG(ui32Base + AES_O_KEY2_0) = pui32Key[0]; - HWREG(ui32Base + AES_O_KEY2_1) = pui32Key[1]; - HWREG(ui32Base + AES_O_KEY2_2) = pui32Key[2]; - HWREG(ui32Base + AES_O_KEY2_3) = pui32Key[3]; - - // - // The key is 192 or 256 bits. Write the next 2 words. - // - if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) - { - HWREG(ui32Base + AES_O_KEY2_4) = pui32Key[4]; - HWREG(ui32Base + AES_O_KEY2_5) = pui32Key[5]; - } - - // - // The key is 256 bits. Write the last 2 words. - // - if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) - { - HWREG(ui32Base + AES_O_KEY2_6) = pui32Key[6]; - HWREG(ui32Base + AES_O_KEY2_7) = pui32Key[7]; - } -} - -//***************************************************************************** -// -//! Writes key 3 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui32Key is a pointer to an array of 4 words (128 bits), containing -//! the key to be configured. The least significant word is in the 0th index. -//! -//! This function writes the key 2 configuration registers with key 3 data -//! used in CBC-MAC and F8 modes. This key is always 128 bits. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey3Set(uint32_t ui32Base, uint32_t *pui32Key) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the key into the upper 4 key registers - // - HWREG(ui32Base + AES_O_KEY2_4) = pui32Key[0]; - HWREG(ui32Base + AES_O_KEY2_5) = pui32Key[1]; - HWREG(ui32Base + AES_O_KEY2_6) = pui32Key[2]; - HWREG(ui32Base + AES_O_KEY2_7) = pui32Key[3]; -} - -//***************************************************************************** -// -//! Writes the Initial Vector (IV) register, needed in some of the AES Modes. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32IVdata is an array of 4 words (128 bits), containing the IV -//! value to be configured. The least significant word is in the 0th index. -//! -//! This functions writes the initial vector registers in the AES module. -//! -//! \return None. -// -//***************************************************************************** -void -AESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the initial vector registers. - // - HWREG(ui32Base + AES_O_IV_IN_0) = pui32IVdata[0]; - HWREG(ui32Base + AES_O_IV_IN_1) = pui32IVdata[1]; - HWREG(ui32Base + AES_O_IV_IN_2) = pui32IVdata[2]; - HWREG(ui32Base + AES_O_IV_IN_3) = pui32IVdata[3]; -} - -//***************************************************************************** -// -//! Saves the Initial Vector (IV) registers to a user-defined location. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32IVData is pointer to the location that stores the IV data. -//! -//! This function stores the IV for use with authenticated encryption and -//! decryption operations. It is assumed that the AES_CTRL_SAVE_CONTEXT -//! bit is set in the AES_CTRL register. -//! -//! \return None. -// -//***************************************************************************** -void -AESIVRead(uint32_t ui32Base, uint32_t *pui32IVData) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Wait for the output context to be ready. - // - while((AES_CTRL_SVCTXTRDY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - // Read the tag data. - // - pui32IVData[0] = HWREG((ui32Base + AES_O_IV_IN_0)); - pui32IVData[1] = HWREG((ui32Base + AES_O_IV_IN_1)); - pui32IVData[2] = HWREG((ui32Base + AES_O_IV_IN_2)); - pui32IVData[3] = HWREG((ui32Base + AES_O_IV_IN_3)); -} - -//***************************************************************************** -// -//! Saves the tag registers to a user-defined location. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32TagData is pointer to the location that stores the tag data. -//! -//! This function stores the tag data for use authenticated encryption and -//! decryption operations. It is assumed that the AES_CTRL_SAVE_CONTEXT -//! bit is set in the AES_CTRL register. -//! -//! \return None. -// -//***************************************************************************** -void -AESTagRead(uint32_t ui32Base, uint32_t *pui32TagData) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Wait for the output context to be ready. - // - while((AES_CTRL_SVCTXTRDY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - // Read the tag data. - // - pui32TagData[0] = HWREG((ui32Base + AES_O_TAG_OUT_0)); - pui32TagData[1] = HWREG((ui32Base + AES_O_TAG_OUT_1)); - pui32TagData[2] = HWREG((ui32Base + AES_O_TAG_OUT_2)); - pui32TagData[3] = HWREG((ui32Base + AES_O_TAG_OUT_3)); -} - -//***************************************************************************** -// -//! Used to set the write crypto data length in the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui64Length is the crypto data length in bytes. -//! -//! This function stores the cryptographic data length in blocks for all modes. -//! Data lengths up to (2^61 - 1) bytes are allowed. For GCM, any value up -//! to (2^36 - 2) bytes are allowed because a 32-bit block counter is used. -//! For basic modes (ECB/CBC/CTR/ICM/CFB128), zero can be programmed into the -//! length field, indicating that the length is infinite. -//! -//! When this function is called, the engine is triggered to start using -//! this context. -//! -//! \note This length does not include the authentication-only data used in -//! some modes. Use the AESAuthLengthSet() function to specify the -//! authentication data length. -//! -//! \return None -// -//***************************************************************************** -void -AESLengthSet(uint32_t ui32Base, uint64_t ui64Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register by shifting the 64-bit ui64Length. - // - HWREG(ui32Base + AES_O_C_LENGTH_0) = (uint32_t)(ui64Length); - HWREG(ui32Base + AES_O_C_LENGTH_1) = (uint32_t)(ui64Length >> 32); -} - -//***************************************************************************** -// -//! Sets the authentication data length in the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Length is the length in bytes. -//! -//! This function is only used to write the authentication data length in the -//! combined modes (GCM or CCM) and XTS mode. Supported AAD lengths for CCM -//! are from 0 to (2^16 - 28) bytes. For GCM, any value up to (2^32 - 1) can -//! be used. For XTS mode, this register is used to load j. Loading of j is -//! only required if j != 0. j represents the sequential number of the 128-bit -//! blocks inside the data unit. Consequently, j must be multiplied by 16 -//! when passed to this function, thereby placing the block number in -//! bits [31:4] of the register. -//! -//! When this function is called, the engine is triggered to start using -//! this context for GCM and CCM. -//! -//! \return None -// -//***************************************************************************** -void -AESAuthLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length into the register. - // - HWREG(ui32Base + AES_O_AUTH_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers without blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Dest is a pointer to an array of words of data. -//! -//! This function reads a block of either plaintext or ciphertext out of the -//! AES module. If the output data is not ready, the function returns -//! false. If the read completed successfully, the function returns true. -//! A block is 16 bytes or 4 words. -//! -//! \return true or false. -// -//***************************************************************************** -bool -AESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Check if the output is ready before reading the data. If it not ready, - // return false. - // - if((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - return(false); - } - - // - // Read a block of data from the data registers - // - pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); - pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); - pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); - pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); - - // - // Read successful, return true. - // - return(true); -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers with blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Dest is a pointer to an array of words. -//! -//! This function reads a block of either plaintext or ciphertext out of the -//! AES module. If the output is not ready, the function waits until it is -//! ready. A block is 16 bytes or 4 words. -//! -//! \return None. -// -//***************************************************************************** -void -AESDataRead(uint32_t ui32Base, uint32_t *pui32Dest) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Wait for the output to be ready before reading the data. - // - while((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - // Read a block of data from the data registers - // - pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); - pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); - pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); - pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Src is a pointer to an array of words of data. -//! -//! This function writes a block of either plaintext or ciphertext into the -//! AES module. If the input is not ready, the function returns false. If the -//! write completed successfully, the function returns true. A block is 16 -//! bytes or 4 words. -//! -//! \return True or false. -// -//***************************************************************************** -bool -AESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Check if the input is ready. If not, then return false. - // - if(!(AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL)))) - { - return(false); - } - - // - // Write a block of data into the data registers. - // - HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; - HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; - HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; - HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; - - // - // Write successful, return true. - // - return(true); -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers with blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Src is a pointer to an array of bytes. -//! -//! This function writes a block of either plaintext or ciphertext into the -//! AES module. If the input is not ready, the function waits until it is -//! ready before performing the write. A block is 16 bytes or 4 words. -//! -//! \return None. -// -//***************************************************************************** -void -AESDataWrite(uint32_t ui32Base, uint32_t *pui32Src) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Wait for input ready. - // - while((AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - // Write a block of data into the data registers. - // - HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; - HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; - HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; - HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; -} - -//***************************************************************************** -// -//! Used to process(transform) blocks of data, either encrypt or decrypt it. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Src is a pointer to the memory location where the input data -//! is stored. The data must be padded to the 16-byte boundary. -//! \param pui32Dest is a pointer to the memory location output is written. -//! The space for written data must be rounded up to the 16-byte boundary. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! -//! This function iterates the encryption or decryption mechanism number over -//! the data length. Before calling this function, ensure that the AES -//! module is properly configured the key, data size, mode, etc. Only ECB, -//! CBC, CTR, ICM, CFB, XTS and F8 operating modes should be used. The data -//! is processed in 4-word (16-byte) blocks. -//! -//! \note This function only supports values of \e ui32Length less than 2^32, -//! because the memory size is restricted to between 0 to 2^32 bytes. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, uint32_t *pui32Dest, - uint32_t ui32Length) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register first, which triggers the engine to start - // using this context. - // - AESLengthSet(AES_BASE, (uint64_t)ui32Length); - - // - // Now loop until the blocks are written. - // - for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui32Src + (ui32Count / 4)); - - // - // Read the data registers. - // - AESDataRead(ui32Base, pui32Dest + (ui32Count / 4)); - } - - // - // Return true to indicate successful completion of the function. - // - return(true); -} - -//***************************************************************************** -// -//! Used to authenticate blocks of data by generating a hash tag. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Src is a pointer to the memory location where the input data -//! is stored. The data must be padded to the 16-byte boundary. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! \param pui32Tag is a pointer to a 4-word array where the hash tag is -//! written. -//! -//! This function processes data to produce a hash tag that can be used tor -//! authentication. Before calling this function, ensure that the AES -//! module is properly configured the key, data size, mode, etc. Only -//! CBC-MAC and F9 modes should be used. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataAuth(uint32_t ui32Base, uint32_t *pui32Src, uint32_t ui32Length, - uint32_t *pui32Tag) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register first, which triggers the engine to start - // using this context. - // - AESLengthSet(ui32Base, (uint64_t)ui32Length); - - // - // Now loop until the blocks are written. - // - for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui32Src + (ui32Count / 4)); - } - - // - // Read the hash tag value. - // - AESTagRead(ui32Base, pui32Tag); - - // - // Return true to indicate successful completion of the function. - // - return(true); -} - -//***************************************************************************** -// -//! Processes and authenticates blocks of data, either encrypt it or decrypts -//! it. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Src is a pointer to the memory location where the input data -//! is stored. The data must be padded to the 16-byte boundary. -//! \param pui32Dest is a pointer to the memory location output is written. -//! The space for written data must be rounded up to the 16-byte boundary. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! \param pui32AuthSrc is a pointer to the memory location where the -//! additional authentication data is stored. The data must be padded to the -//! 16-byte boundary. -//! \param ui32AuthLength is the length of the additional authentication -//! data in bytes. -//! \param pui32Tag is a pointer to a 4-word array where the hash tag is -//! written. -//! -//! This function encrypts or decrypts blocks of data in addition to -//! authentication data. A hash tag is also produced. Before calling this -//! function, ensure that the AES module is properly configured the key, -//! data size, mode, etc. Only CCM and GCM modes should be used. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataProcessAuth(uint32_t ui32Base, uint32_t *pui32Src, - uint32_t *pui32Dest, uint32_t ui32Length, - uint32_t *pui32AuthSrc, uint32_t ui32AuthLength, - uint32_t *pui32Tag) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Set the data length. - // - AESLengthSet(ui32Base, (uint64_t)ui32Length); - - // - // Set the additional authentication data length. - // - AESAuthLengthSet(ui32Base, ui32AuthLength); - - // - // Now loop until the authentication data blocks are written. - // - for(ui32Count = 0; ui32Count < ui32AuthLength; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui32AuthSrc + (ui32Count / 4)); - } - - // - // Now loop until the data blocks are written. - // - for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui32Src + (ui32Count / 4)); - - // - // - // Read the data registers. - // - AESDataRead(ui32Base, pui32Dest + (ui32Count / 4)); - } - - // - // Read the hash tag value. - // - AESTagRead(ui32Base, pui32Tag); - - // - // Return true to indicate successful completion of the function. - // - return(true); -} - -//***************************************************************************** -// -//! Returns the current AES module interrupt status. -//! -//! \param ui32Base is the base address of the AES module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! \return Returns a bit mask of the interrupt sources, which is a logical OR -//! of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt. -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -// -//***************************************************************************** -uint32_t -AESIntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Status, ui32Enable, ui32Temp; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Read the IRQ status register and return the value. - // - ui32Status = HWREG(ui32Base + AES_O_IRQSTATUS); - if(bMasked) - { - ui32Enable = HWREG(ui32Base + AES_O_IRQENABLE); - ui32Temp = HWREG(ui32Base + AES_O_DMAMIS); - return((ui32Status & ui32Enable) | - (((ui32Temp & 0x00000001) << 16) | - ((ui32Temp & 0x00000002) << 18) | - ((ui32Temp & 0x0000000c) << 15))); - } - else - { - ui32Temp = HWREG(ui32Base + AES_O_DMARIS); - return(ui32Status | - (((ui32Temp & 0x00000001) << 16) | - ((ui32Temp & 0x00000002) << 18) | - ((ui32Temp & 0x0000000c) << 15))); - } -} - -//***************************************************************************** -// -//! Enables AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to enable. -//! -//! This function enables the interrupts in the AES module. The -//! \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note Interrupts that have been previously been enabled are not disabled -//! when this function is called. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || - (ui32IntFlags == AES_INT_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DATA_IN) || - (ui32IntFlags == AES_INT_DATA_OUT) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - // - // Set the flags. - // - HWREG(ui32Base + AES_O_DMAIM) |= (((ui32IntFlags & 0x00010000) >> 16) | - ((ui32IntFlags & 0x00060000) >> 15) | - ((ui32IntFlags & 0x00080000) >> 18)); - HWREG(ui32Base + AES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; -} - -//***************************************************************************** -// -//! Disables AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. -//! -//! This function disables the interrupt sources in the AES module. The -//! \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note The DMA done interrupts are the only interrupts that can be cleared. -//! The remaining interrupts can be disabled instead using AESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || - (ui32IntFlags == AES_INT_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DATA_IN) || - (ui32IntFlags == AES_INT_DATA_OUT) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - // - // Clear the flags. - // - HWREG(ui32Base + AES_O_DMAIM) &= ~(((ui32IntFlags & 0x00010000) >> 16) | - ((ui32IntFlags & 0x00060000) >> 15) | - ((ui32IntFlags & 0x00080000) >> 18)); - HWREG(ui32Base + AES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); -} - -//***************************************************************************** -// -//! Clears AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. -//! -//! This function clears the interrupt sources in the AES module. The -//! \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note Only the DMA done interrupts can be cleared. The remaining -//! interrupts should be disabled with AESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - HWREG(ui32Base + AES_O_DMAIC) = (((ui32IntFlags & 0x00010000) >> 16) | - ((ui32IntFlags & 0x00060000) >> 15) | - ((ui32IntFlags & 0x00080000) >> 18)); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled AES interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables AES interrupts on the interrupt controller; specific AES -//! interrupt sources must be enabled using AESIntEnable(). The interrupt -//! handler being registered must clear the source of the interrupt using -//! AESIntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() is used to enable AES interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_AES0_TM4C129, pfnHandler); - - // - // Enable the interrupt - // - IntEnable(INT_AES0_TM4C129); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_AES0_TM4C129); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_AES0_TM4C129); -} - -//***************************************************************************** -// -//! Enables uDMA requests for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Flags is a bit mask of the uDMA requests to be enabled. -//! -//! This function enables the uDMA request sources in the AES module. -//! The \e ui32Flags parameter is the logical OR of any of the following: -//! -//! - \b AES_DMA_DATA_IN -//! - \b AES_DMA_DATA_OUT -//! - \b AES_DMA_CONTEXT_IN -//! - \b AES_DMA_CONTEXT_OUT -//! -//! \return None. -// -//***************************************************************************** -void -AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Flags == AES_DMA_DATA_IN) || - (ui32Flags == AES_DMA_DATA_OUT) || - (ui32Flags == AES_DMA_CONTEXT_IN) || - (ui32Flags == AES_DMA_CONTEXT_OUT)); - - // - // Set the flags in the current register value. - // - HWREG(ui32Base + AES_O_SYSCONFIG) |= ui32Flags; -} - -//***************************************************************************** -// -//! Disables uDMA requests for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Flags is a bit mask of the uDMA requests to be disabled. -//! -//! This function disables the uDMA request sources in the AES module. -//! The \e ui32Flags parameter is the logical OR of any of the -//! following: -//! -//! - \b AES_DMA_DATA_IN -//! - \b AES_DMA_DATA_OUT -//! - \b AES_DMA_CONTEXT_IN -//! - \b AES_DMA_CONTEXT_OUT -//! -//! \return None. -// -//***************************************************************************** -void -AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Flags == AES_DMA_DATA_IN) || - (ui32Flags == AES_DMA_DATA_OUT) || - (ui32Flags == AES_DMA_CONTEXT_IN) || - (ui32Flags == AES_DMA_CONTEXT_OUT)); - - // - // Clear the flags in the current register value. - // - HWREG(ui32Base + AES_O_SYSCONFIG) &= ~ui32Flags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/aes.h b/bsp/tm4c129x-dk/libraries/driverlib/aes.h deleted file mode 100644 index 6cf44780ddccafbdc1bd63f4e75ab6e8b322f2a7..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/aes.h +++ /dev/null @@ -1,218 +0,0 @@ -//***************************************************************************** -// -// aes.h - Defines and Macros for the AES module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_AES_H__ -#define __DRIVERLIB_AES_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used to specify the operation direction in the -// ui32Config argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_DIR_ENCRYPT 0x00000004 -#define AES_CFG_DIR_DECRYPT 0x00000000 - -//***************************************************************************** -// -// The following defines are used to specify the key size in the ui32Config -// argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_KEY_SIZE_128BIT 0x00000008 -#define AES_CFG_KEY_SIZE_192BIT 0x00000010 -#define AES_CFG_KEY_SIZE_256BIT 0x00000018 - -//***************************************************************************** -// -// The following defines are used to specify the mode of operation in the -// ui32Config argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_MODE_M 0x2007fe60 -#define AES_CFG_MODE_ECB 0x00000000 -#define AES_CFG_MODE_CBC 0x00000020 -#define AES_CFG_MODE_CTR 0x00000040 -#define AES_CFG_MODE_ICM 0x00000200 -#define AES_CFG_MODE_CFB 0x00000400 -#define AES_CFG_MODE_XTS_TWEAKJL \ - 0x00000800 -#define AES_CFG_MODE_XTS_K2IJL \ - 0x00001000 -#define AES_CFG_MODE_XTS_K2ILJ0 \ - 0x00001800 -#define AES_CFG_MODE_F8 0x00002000 -#define AES_CFG_MODE_F9 0x20004000 -#define AES_CFG_MODE_CBCMAC 0x20008000 -#define AES_CFG_MODE_GCM_HLY0ZERO \ - 0x20010000 -#define AES_CFG_MODE_GCM_HLY0CALC \ - 0x20020040 -#define AES_CFG_MODE_GCM_HY0CALC \ - 0x20030040 -#define AES_CFG_MODE_CCM 0x20040040 - -//***************************************************************************** -// -// The following defines are used to specify the counter width in the -// ui32Config argument in the AESConfig function. It is only required to -// be defined when using CTR, CCM, or GCM modes. Only one length is permitted. -// -//***************************************************************************** -#define AES_CFG_CTR_WIDTH_32 0x00000000 -#define AES_CFG_CTR_WIDTH_64 0x00000080 -#define AES_CFG_CTR_WIDTH_96 0x00000100 -#define AES_CFG_CTR_WIDTH_128 0x00000180 - -//***************************************************************************** -// -// The following defines are used to define the width of the length field for -// CCM operation through the ui32Config argument in the AESConfig function. -// This value is also known as L. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_CCM_L_1 0x00000000 -#define AES_CFG_CCM_L_2 0x00080000 -#define AES_CFG_CCM_L_3 0x00100000 -#define AES_CFG_CCM_L_4 0x00180000 -#define AES_CFG_CCM_L_5 0x00200000 -#define AES_CFG_CCM_L_6 0x00280000 -#define AES_CFG_CCM_L_7 0x00300000 -#define AES_CFG_CCM_L_8 0x00380000 - -//***************************************************************************** -// -// The following defines are used to define the length of the authentication -// field for CCM operations through the ui32Config argument in the AESConfig -// function. This value is also known as M. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_CCM_M_4 0x00400000 -#define AES_CFG_CCM_M_6 0x00800000 -#define AES_CFG_CCM_M_8 0x00c00000 -#define AES_CFG_CCM_M_10 0x01000000 -#define AES_CFG_CCM_M_12 0x01400000 -#define AES_CFG_CCM_M_14 0x01800000 -#define AES_CFG_CCM_M_16 0x01c00000 - -//***************************************************************************** -// -// Interrupt flags for use with the AESIntEnable, AESIntDisable, and -// AESIntStatus functions. -// -//***************************************************************************** -#define AES_INT_CONTEXT_IN 0x00000001 -#define AES_INT_CONTEXT_OUT 0x00000008 -#define AES_INT_DATA_IN 0x00000002 -#define AES_INT_DATA_OUT 0x00000004 -#define AES_INT_DMA_CONTEXT_IN 0x00010000 -#define AES_INT_DMA_CONTEXT_OUT 0x00080000 -#define AES_INT_DMA_DATA_IN 0x00020000 -#define AES_INT_DMA_DATA_OUT 0x00040000 - -//***************************************************************************** -// -// Defines used when enabling and disabling DMA requests in the -// AESEnableDMA and AESDisableDMA functions. -// -//***************************************************************************** -#define AES_DMA_DATA_IN 0x00000020 -#define AES_DMA_DATA_OUT 0x00000040 -#define AES_DMA_CONTEXT_IN 0x00000080 -#define AES_DMA_CONTEXT_OUT 0x00000100 - -//***************************************************************************** -// -// Function prototypes. -// -//***************************************************************************** -extern void AESAuthLengthSet(uint32_t ui32Base, uint32_t ui32Length); -extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void AESDataRead(uint32_t ui32Base, uint32_t *pui32Dest); -extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest); -extern bool AESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, - uint32_t *pui32Dest, uint32_t ui32Length); -extern bool AESDataAuth(uint32_t ui32Base, uint32_t *pui32Src, - uint32_t ui32Length, uint32_t *pui32Tag); -extern bool AESDataProcessAuth(uint32_t ui32Base, uint32_t *pui32Src, - uint32_t *pui32Dest, uint32_t ui32Length, - uint32_t *pui32AuthSrc, - uint32_t ui32AuthLength, uint32_t *pui32Tag); -extern void AESDataWrite(uint32_t ui32Base, uint32_t *pui32Src); -extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src); -extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); -extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); -extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked); -extern void AESIntUnregister(uint32_t ui32Base); -extern void AESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata); -extern void AESIVRead(uint32_t ui32Base, uint32_t *pui32IVdata); -extern void AESKey1Set(uint32_t ui32Base, uint32_t *pui32Key, - uint32_t ui32Keysize); -extern void AESKey2Set(uint32_t ui32Base, uint32_t *pui32Key, - uint32_t ui32Keysize); -extern void AESKey3Set(uint32_t ui32Base, uint32_t *pui32Key); -extern void AESLengthSet(uint32_t ui32Base, uint64_t ui64Length); -extern void AESReset(uint32_t ui32Base); -extern void AESTagRead(uint32_t ui32Base, uint32_t *pui32TagData); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_AES_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/can.c b/bsp/tm4c129x-dk/libraries/driverlib/can.c deleted file mode 100644 index d53584585c4ceb31c5b7c3afbf6279f402ccda94..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/can.c +++ /dev/null @@ -1,2117 +0,0 @@ -//***************************************************************************** -// -// can.c - Driver for the CAN module. -// -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup can_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_can.h" -#include "inc/hw_ints.h" -#include "inc/hw_nvic.h" -#include "inc/hw_memmap.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/can.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -// This is the maximum number that can be stored as an 11bit Message -// identifier. -// -//***************************************************************************** -#define CAN_MAX_11BIT_MSG_ID 0x7ff - -//***************************************************************************** -// -// The maximum CAN bit timing divisor is 19. -// -//***************************************************************************** -#define CAN_MAX_BIT_DIVISOR 19 - -//***************************************************************************** -// -// The minimum CAN bit timing divisor is 4. -// -//***************************************************************************** -#define CAN_MIN_BIT_DIVISOR 4 - -//***************************************************************************** -// -// The maximum CAN pre-divisor is 1024. -// -//***************************************************************************** -#define CAN_MAX_PRE_DIVISOR 1024 - -//***************************************************************************** -// -// The minimum CAN pre-divisor is 1. -// -//***************************************************************************** -#define CAN_MIN_PRE_DIVISOR 1 - -//***************************************************************************** -// -// Converts a set of CAN bit timing values into the value that needs to be -// programmed into the CAN_BIT register to achieve those timings. -// -//***************************************************************************** -#define CAN_BIT_VALUE(seg1, seg2, sjw) \ - ((((seg1 - 1) << CAN_BIT_TSEG1_S) & \ - CAN_BIT_TSEG1_M) | \ - (((seg2 - 1) << CAN_BIT_TSEG2_S) & \ - CAN_BIT_TSEG2_M) | \ - (((sjw - 1) << CAN_BIT_SJW_S) & \ - CAN_BIT_SJW_M)) - -//***************************************************************************** -// -// This table is used by the CANBitRateSet() API as the register defaults for -// the bit timing values. -// -//***************************************************************************** -static const uint16_t g_ui16CANBitValues[] = -{ - CAN_BIT_VALUE(2, 1, 1), // 4 clocks/bit - CAN_BIT_VALUE(3, 1, 1), // 5 clocks/bit - CAN_BIT_VALUE(3, 2, 2), // 6 clocks/bit - CAN_BIT_VALUE(4, 2, 2), // 7 clocks/bit - CAN_BIT_VALUE(4, 3, 3), // 8 clocks/bit - CAN_BIT_VALUE(5, 3, 3), // 9 clocks/bit - CAN_BIT_VALUE(5, 4, 4), // 10 clocks/bit - CAN_BIT_VALUE(6, 4, 4), // 11 clocks/bit - CAN_BIT_VALUE(6, 5, 4), // 12 clocks/bit - CAN_BIT_VALUE(7, 5, 4), // 13 clocks/bit - CAN_BIT_VALUE(7, 6, 4), // 14 clocks/bit - CAN_BIT_VALUE(8, 6, 4), // 15 clocks/bit - CAN_BIT_VALUE(8, 7, 4), // 16 clocks/bit - CAN_BIT_VALUE(9, 7, 4), // 17 clocks/bit - CAN_BIT_VALUE(9, 8, 4), // 18 clocks/bit - CAN_BIT_VALUE(10, 8, 4) // 19 clocks/bit -}; - -//***************************************************************************** -// -//! \internal -//! Checks a CAN base address. -//! -//! \param ui32Base is the base address of the CAN controller. -//! -//! This function determines if a CAN controller base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_CANBaseValid(uint32_t ui32Base) -{ - return((ui32Base == CAN0_BASE) || (ui32Base == CAN1_BASE)); -} -#endif - -//***************************************************************************** -// -//! Returns the CAN controller interrupt number. -//! -//! \param ui32Base is the base address of the selected CAN controller -//! -//! This function returns the interrupt number for the CAN module with the base -//! address passed in the \e ui32Base parameter. -//! -//! \return Returns a CAN interrupt number or 0 if the interrupt does not -//! exist. -// -//***************************************************************************** -static uint_fast8_t -_CANIntNumberGet(uint32_t ui32Base) -{ - uint_fast8_t ui8Int; - - ASSERT((ui32Base == CAN0_BASE) || (ui32Base == CAN1_BASE)); - - ui8Int = 0; - - // - // Find the valid interrupt number for this CAN controller. - // - if(CLASS_IS_TM4C123) - { - if(ui32Base == CAN0_BASE) - { - ui8Int = INT_CAN0_TM4C123; - } - else if(ui32Base == CAN1_BASE) - { - ui8Int = INT_CAN1_TM4C123; - } - } - else if(CLASS_IS_TM4C129) - { - if(ui32Base == CAN0_BASE) - { - ui8Int = INT_CAN0_TM4C129; - } - else if(ui32Base == CAN1_BASE) - { - ui8Int = INT_CAN1_TM4C129; - } - } - - return(ui8Int); -} - -//***************************************************************************** -// -//! \internal -//! Copies data from a buffer to the CAN Data registers. -//! -//! \param pui8Data is a pointer to the data to be written out to the CAN -//! controller's data registers. -//! \param pui32Register is an uint32_t pointer to the first register of the -//! CAN controller's data registers. For example, in order to use the IF1 -//! register set on CAN controller 0, the value would be: \b CAN0_BASE \b + -//! \b CAN_O_IF1DA1. -//! \param iSize is the number of bytes to copy into the CAN controller. -//! -//! This function takes the steps necessary to copy data from a contiguous -//! buffer in memory into the non-contiguous data registers used by the CAN -//! controller. This function is rarely used outside of the CANMessageSet() -//! function. -//! -//! \return None. -// -//***************************************************************************** -static void -_CANDataRegWrite(uint8_t *pui8Data, uint32_t *pui32Register, uint32_t ui32Size) -{ - uint32_t ui32Idx, ui32Value; - - // - // Loop always copies 1 or 2 bytes per iteration. - // - for(ui32Idx = 0; ui32Idx < ui32Size; ) - { - // - // Write out the data 16 bits at a time since this is how the registers - // are aligned in memory. - // - ui32Value = pui8Data[ui32Idx++]; - - // - // Only write the second byte if needed otherwise the value is zero. - // - if(ui32Idx < ui32Size) - { - ui32Value |= (pui8Data[ui32Idx++] << 8); - } - - HWREG(pui32Register++) = ui32Value; - } -} - -//***************************************************************************** -// -//! \internal -//! Copies data from a buffer to the CAN Data registers. -//! -//! \param pui8Data is a pointer to the location to store the data read from -//! the CAN controller's data registers. -//! \param pui32Register is an uint32_t pointer to the first register of the -//! CAN controller's data registers. For example, in order to use the IF1 -//! register set on CAN controller 1, the value would be: \b CAN0_BASE \b + -//! \b CAN_O_IF1DA1. -//! \param iSize is the number of bytes to copy from the CAN controller. -//! -//! This function takes the steps necessary to copy data to a contiguous buffer -//! in memory from the non-contiguous data registers used by the CAN -//! controller. This function is rarely used outside of the CANMessageGet() -//! function. -//! -//! \return None. -// -//***************************************************************************** -static void -_CANDataRegRead(uint8_t *pui8Data, uint32_t *pui32Register, uint32_t ui32Size) -{ - uint32_t ui32Idx, ui32Value; - - // - // Loop always copies 1 or 2 bytes per iteration. - // - for(ui32Idx = 0; ui32Idx < ui32Size; ) - { - // - // Read out the data 16 bits at a time since this is how the registers - // are aligned in memory. - // - ui32Value = HWREG(pui32Register++); - - // - // Store the first byte. - // - pui8Data[ui32Idx++] = (uint8_t)ui32Value; - - // - // Only read the second byte if needed. - // - if(ui32Idx < ui32Size) - { - pui8Data[ui32Idx++] = (uint8_t)(ui32Value >> 8); - } - } -} - -//***************************************************************************** -// -//! Initializes the CAN controller after reset. -//! -//! \param ui32Base is the base address of the CAN controller. -//! -//! After reset, the CAN controller is left in the disabled state. However, -//! the memory used for message objects contains undefined values and must be -//! cleared prior to enabling the CAN controller the first time. This prevents -//! unwanted transmission or reception of data before the message objects are -//! configured. This function must be called before enabling the controller -//! the first time. -//! -//! \return None. -// -//***************************************************************************** -void -CANInit(uint32_t ui32Base) -{ - uint32_t ui32Msg; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - - // - // Place CAN controller in init state, regardless of previous state. This - // puts controller in idle, and allow the message object RAM to be - // programmed. - // - HWREG(ui32Base + CAN_O_CTL) = CAN_CTL_INIT; - - // - // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) - { - } - - // - // Clear the message value bit in the arbitration register. This indicates - // the message is not valid and is a "safe" condition to leave the message - // object. The same arb reg is used to program all the message objects. - // - HWREG(ui32Base + CAN_O_IF1CMSK) = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB | - CAN_IF1CMSK_CONTROL); - HWREG(ui32Base + CAN_O_IF1ARB2) = 0; - HWREG(ui32Base + CAN_O_IF1MCTL) = 0; - - // - // Loop through to program all 32 message objects - // - for(ui32Msg = 1; ui32Msg <= 32; ui32Msg++) - { - // - // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) - { - } - - // - // Initiate programming the message object - // - HWREG(ui32Base + CAN_O_IF1CRQ) = ui32Msg; - } - - // - // Make sure that the interrupt and new data flags are updated for the - // message objects. - // - HWREG(ui32Base + CAN_O_IF1CMSK) = (CAN_IF1CMSK_NEWDAT | - CAN_IF1CMSK_CLRINTPND); - - // - // Loop through to program all 32 message objects - // - for(ui32Msg = 1; ui32Msg <= 32; ui32Msg++) - { - // - // Wait for busy bit to clear. - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) - { - } - - // - // Initiate programming the message object - // - HWREG(ui32Base + CAN_O_IF1CRQ) = ui32Msg; - } - - // - // Acknowledge any pending status interrupts. - // - HWREG(ui32Base + CAN_O_STS); -} - -//***************************************************************************** -// -//! Enables the CAN controller. -//! -//! \param ui32Base is the base address of the CAN controller to enable. -//! -//! Enables the CAN controller for message processing. Once enabled, the -//! controller automatically transmits any pending frames, and processes any -//! received frames. The controller can be stopped by calling CANDisable(). -//! Prior to calling CANEnable(), CANInit() must have been called to -//! initialize the controller and the CAN bus clock must be configured by -//! calling CANBitTimingSet(). -//! -//! \return None. -// -//***************************************************************************** -void -CANEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - - // - // Clear the init bit in the control register. - // - HWREG(ui32Base + CAN_O_CTL) &= ~CAN_CTL_INIT; -} - -//***************************************************************************** -// -//! Disables the CAN controller. -//! -//! \param ui32Base is the base address of the CAN controller to disable. -//! -//! Disables the CAN controller for message processing. When disabled, the -//! controller no longer automatically processes data on the CAN bus. The -//! controller can be restarted by calling CANEnable(). The state of the CAN -//! controller and the message objects in the controller are left as they were -//! before this call was made. -//! -//! \return None. -// -//***************************************************************************** -void -CANDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - - // - // Set the init bit in the control register. - // - HWREG(ui32Base + CAN_O_CTL) |= CAN_CTL_INIT; -} - -//***************************************************************************** -// -//! Reads the current settings for the CAN controller bit timing. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param psClkParms is a pointer to a structure to hold the timing -//! parameters. -//! -//! This function reads the current configuration of the CAN controller bit -//! clock timing and stores the resulting information in the structure -//! supplied by the caller. Refer to CANBitTimingSet() for the meaning of the -//! values that are returned in the structure pointed to by \e psClkParms. -//! -//! \return None. -// -//***************************************************************************** -void -CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms) -{ - uint32_t ui32BitReg; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT(psClkParms); - - // - // Read out all the bit timing values from the CAN controller registers. - // - ui32BitReg = HWREG(ui32Base + CAN_O_BIT); - - // - // Set the phase 2 segment. - // - psClkParms->ui32Phase2Seg = - ((ui32BitReg & CAN_BIT_TSEG2_M) >> CAN_BIT_TSEG2_S) + 1; - - // - // Set the phase 1 segment. - // - psClkParms->ui32SyncPropPhase1Seg = - ((ui32BitReg & CAN_BIT_TSEG1_M) >> CAN_BIT_TSEG1_S) + 1; - - // - // Set the synchronous jump width. - // - psClkParms->ui32SJW = ((ui32BitReg & CAN_BIT_SJW_M) >> CAN_BIT_SJW_S) + 1; - - // - // Set the pre-divider for the CAN bus bit clock. - // - psClkParms->ui32QuantumPrescaler = - ((ui32BitReg & CAN_BIT_BRP_M) | - ((HWREG(ui32Base + CAN_O_BRPE) & CAN_BRPE_BRPE_M) << 6)) + 1; -} - -//***************************************************************************** -// -//! Sets the CAN bit timing values to a nominal setting based on a desired -//! bit rate. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param ui32SourceClock is the system clock for the device in Hz. -//! \param ui32BitRate is the desired bit rate. -//! -//! This function sets the CAN bit timing for the bit rate passed in the -//! \e ui32BitRate parameter based on the \e ui32SourceClock parameter. -//! Because the CAN clock is based off of the system clock, the calling -//! function must pass in the source clock rate either by retrieving it from -//! SysCtlClockGet() or using a specific value in Hz. The CAN bit timing is -//! calculated assuming a minimal amount of propagation delay, which works for -//! most cases where the network length is short. If tighter timing -//! requirements or longer network lengths are needed, then the -//! CANBitTimingSet() function is available for full customization of all of -//! the CAN bit timing values. Because not all bit rates can be matched -//! exactly, the bit rate is set to the value closest to the desired bit rate -//! without being higher than the \e ui32BitRate value. -//! -//! \note On some devices the source clock is fixed at 8MHz so the -//! \e ui32SourceClock must be set to 8000000. -//! -//! \return This function returns the bit rate that the CAN controller was -//! configured to use or it returns 0 to indicate that the bit rate was not -//! changed because the requested bit rate was not valid. -//! -//***************************************************************************** -uint32_t -CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, - uint32_t ui32BitRate) -{ - uint32_t ui32DesiredRatio; - uint32_t ui32CANBits; - uint32_t ui32PreDivide; - uint32_t ui32RegValue; - uint16_t ui16CANCTL; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT(ui32SourceClock); - ASSERT(ui32BitRate); - - // - // Calculate the desired clock rate. - // - ui32DesiredRatio = ui32SourceClock / ui32BitRate; - - // - // Make sure that the ratio of CAN bit rate to processor clock is not too - // small or too large. - // - ASSERT(ui32DesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)); - ASSERT(ui32DesiredRatio >= (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR)); - - // - // Make sure that the Desired Ratio is not too large. This enforces the - // requirement that the bit rate is larger than requested. - // - if((ui32SourceClock / ui32DesiredRatio) > ui32BitRate) - { - ui32DesiredRatio += 1; - } - - // - // Check all possible values to find a matching value. - // - while(ui32DesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)) - { - // - // Loop through all possible CAN bit divisors. - // - for(ui32CANBits = CAN_MAX_BIT_DIVISOR; - ui32CANBits >= CAN_MIN_BIT_DIVISOR; ui32CANBits--) - { - // - // For a given CAN bit divisor save the pre divisor. - // - ui32PreDivide = ui32DesiredRatio / ui32CANBits; - - // - // If the calculated divisors match the desired clock ratio then - // return these bit rate and set the CAN bit timing. - // - if((ui32PreDivide * ui32CANBits) == ui32DesiredRatio) - { - // - // Start building the bit timing value by adding the bit timing - // in time quanta. - // - ui32RegValue = g_ui16CANBitValues[ui32CANBits - - CAN_MIN_BIT_DIVISOR]; - - // - // To set the bit timing register, the controller must be - // placed in init mode (if not already), and also configuration - // change bit enabled. The state of the register must be - // saved so it can be restored. - // - ui16CANCTL = HWREG(ui32Base + CAN_O_CTL); - HWREG(ui32Base + CAN_O_CTL) = ui16CANCTL | CAN_CTL_INIT | - CAN_CTL_CCE; - - // - // Now add in the pre-scalar on the bit rate. - // - ui32RegValue |= ((ui32PreDivide - 1) & CAN_BIT_BRP_M); - - // - // Set the clock bits in the and the lower bits of the - // pre-scalar. - // - HWREG(ui32Base + CAN_O_BIT) = ui32RegValue; - - // - // Set the divider upper bits in the extension register. - // - HWREG(ui32Base + CAN_O_BRPE) = ((ui32PreDivide - 1) >> 6) & - CAN_BRPE_BRPE_M; - - // - // Restore the saved CAN Control register. - // - HWREG(ui32Base + CAN_O_CTL) = ui16CANCTL; - - // - // Return the computed bit rate. - // - return(ui32SourceClock / (ui32PreDivide * ui32CANBits)); - } - } - - // - // Move the divisor up one and look again. Only in rare cases are - // more than 2 loops required to find the value. - // - ui32DesiredRatio++; - } - - // - // A valid combination could not be found, so return 0 to indicate that the - // bit rate was not changed. - // - return(0); -} - -//***************************************************************************** -// -//! Configures the CAN controller bit timing. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param psClkParms points to the structure with the clock parameters. -//! -//! Configures the various timing parameters for the CAN bus bit timing: -//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and -//! the Synchronization Jump Width. The values for Propagation and Phase -//! Buffer 1 segments are derived from the combination -//! \e psClkParms->ui32SyncPropPhase1Seg parameter. Phase Buffer 2 is -//! determined from the \e psClkParms->ui32Phase2Seg parameter. These two -//! parameters, along with \e psClkParms->ui32SJW are based in units of bit -//! time quanta. The actual quantum time is determined by the -//! \e psClkParms->ui32QuantumPrescaler value, which specifies the divisor for -//! the CAN module clock. -//! -//! The total bit time, in quanta, is the sum of the two Seg parameters, -//! as follows: -//! -//! bit_time_q = ui32SyncPropPhase1Seg + ui32Phase2Seg + 1 -//! -//! Note that the Sync_Seg is always one quantum in duration, and is added -//! to derive the correct duration of Prop_Seg and Phase1_Seg. -//! -//! The equation to determine the actual bit rate is as follows: -//! -//! CAN Clock / -//! ((\e ui32SyncPropPhase1Seg + \e ui32Phase2Seg + 1) * -//! (\e ui32QuantumPrescaler)) -//! -//! Thus with \e ui32SyncPropPhase1Seg = 4, \e ui32Phase2Seg = 1, -//! \e ui32QuantumPrescaler = 2 and an 8 MHz CAN clock, the bit rate is -//! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec. -//! -//! \return None. -// -//***************************************************************************** -void -CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms) -{ - uint32_t ui32BitReg, ui32SavedInit; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT(psClkParms); - - // - // The phase 1 segment must be in the range from 2 to 16. - // - ASSERT((psClkParms->ui32SyncPropPhase1Seg >= 2) && - (psClkParms->ui32SyncPropPhase1Seg <= 16)); - - // - // The phase 2 segment must be in the range from 1 to 8. - // - ASSERT((psClkParms->ui32Phase2Seg >= 1) && - (psClkParms->ui32Phase2Seg <= 8)); - - // - // The synchronous jump windows must be in the range from 1 to 4. - // - ASSERT((psClkParms->ui32SJW >= 1) && (psClkParms->ui32SJW <= 4)); - - // - // The CAN clock pre-divider must be in the range from 1 to 1024. - // - ASSERT((psClkParms->ui32QuantumPrescaler <= 1024) && - (psClkParms->ui32QuantumPrescaler >= 1)); - - // - // To set the bit timing register, the controller must be placed in init - // mode (if not already), and also configuration change bit enabled. State - // of the init bit must be saved so it can be restored at the end. - // - ui32SavedInit = HWREG(ui32Base + CAN_O_CTL); - HWREG(ui32Base + CAN_O_CTL) = ui32SavedInit | CAN_CTL_INIT | CAN_CTL_CCE; - - // - // Set the bit fields of the bit timing register according to the parms. - // - ui32BitReg = (((psClkParms->ui32Phase2Seg - 1) << CAN_BIT_TSEG2_S) & - CAN_BIT_TSEG2_M); - ui32BitReg |= (((psClkParms->ui32SyncPropPhase1Seg - 1) << - CAN_BIT_TSEG1_S) & CAN_BIT_TSEG1_M); - ui32BitReg |= ((psClkParms->ui32SJW - 1) << CAN_BIT_SJW_S) & CAN_BIT_SJW_M; - ui32BitReg |= (psClkParms->ui32QuantumPrescaler - 1) & CAN_BIT_BRP_M; - HWREG(ui32Base + CAN_O_BIT) = ui32BitReg; - - // - // Set the divider upper bits in the extension register. - // - HWREG(ui32Base + CAN_O_BRPE) = - ((psClkParms->ui32QuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M; - - // - // Clear the config change bit, and restore the init bit. - // - ui32SavedInit &= ~CAN_CTL_CCE; - - // - // If Init was not set before, then clear it. - // - if(ui32SavedInit & CAN_CTL_INIT) - { - ui32SavedInit &= ~CAN_CTL_INIT; - } - - HWREG(ui32Base + CAN_O_CTL) = ui32SavedInit; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the CAN controller. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled CAN interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables CAN interrupts on the interrupt controller; specific CAN -//! interrupt sources must be enabled using CANIntEnable(). The interrupt -//! handler being registered must clear the source of the interrupt using -//! CANIntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() is used to enable CAN interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint_fast8_t ui8IntNumber; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - - // - // Get the actual interrupt number for this CAN controller. - // - ui8IntNumber = _CANIntNumberGet(ui32Base); - ASSERT(ui8IntNumber != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui8IntNumber, pfnHandler); - - // - // Enable the Ethernet interrupt. - // - IntEnable(ui8IntNumber); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the CAN controller. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -CANIntUnregister(uint32_t ui32Base) -{ - uint_fast8_t ui8IntNumber; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - - // - // Get the actual interrupt number for this CAN controller. - // - ui8IntNumber = _CANIntNumberGet(ui32Base); - ASSERT(ui8IntNumber != 0); - - // - // Disable the CAN interrupt. - // - IntDisable(ui8IntNumber); - - // - // Register the interrupt handler. - // - IntUnregister(ui8IntNumber); -} - -//***************************************************************************** -// -//! Enables individual CAN controller interrupt sources. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables specific interrupt sources of the CAN controller. -//! Only enabled sources cause a processor interrupt. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b CAN_INT_ERROR - a controller error condition has occurred -//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has -//! been detected -//! - \b CAN_INT_MASTER - allow CAN controller to generate interrupts -//! -//! In order to generate any interrupts, \b CAN_INT_MASTER must be enabled. -//! Further, for any particular transaction from a message object to generate -//! an interrupt, that message object must have interrupts enabled (see -//! CANMessageSet()). \b CAN_INT_ERROR generates an interrupt if the -//! controller enters the ``bus off'' condition, or if the error counters reach -//! a limit. \b CAN_INT_STATUS generates an interrupt under quite a few -//! status conditions and may provide more interrupts than the application -//! needs to handle. When an interrupt occurs, use CANIntStatus() to determine -//! the cause. -//! -//! \return None. -// -//***************************************************************************** -void -CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT((ui32IntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0); - - // - // Enable the specified interrupts. - // - HWREG(ui32Base + CAN_O_CTL) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual CAN controller interrupt sources. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! Disables the specified CAN controller interrupt sources. Only enabled -//! interrupt sources can cause a processor interrupt. -//! -//! The \e ui32IntFlags parameter has the same definition as in the -//! CANIntEnable() function. -//! -//! \return None. -// -//***************************************************************************** -void -CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT((ui32IntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0); - - // - // Disable the specified interrupts. - // - HWREG(ui32Base + CAN_O_CTL) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Returns the current CAN controller interrupt status. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param eIntStsReg indicates which interrupt status register to read -//! -//! This function returns the value of one of two interrupt status registers. -//! The interrupt status register read is determined by the \e eIntStsReg -//! parameter, which can have one of the following values: -//! -//! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt -//! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message -//! objects -//! -//! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register -//! and indicates the cause of the interrupt. The value returned is -//! \b CAN_INT_INTID_STATUS if the cause is a status interrupt. In this case, -//! the status register is read with the CANStatusGet() function. -//! Calling this function to read the status also clears the status -//! interrupt. If the value of the interrupt register is in the range 1-32, -//! then this indicates the number of the highest priority message object that -//! has an interrupt pending. The message object interrupt can be cleared by -//! using the CANIntClear() function, or by reading the message using -//! CANMessageGet() in the case of a received message. The interrupt handler -//! can read the interrupt status again to make sure all pending interrupts are -//! cleared before returning from the interrupt. -//! -//! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects -//! have pending interrupts. This value can be used to discover all of the -//! pending interrupts at once, as opposed to repeatedly reading the interrupt -//! register by using \b CAN_INT_STS_CAUSE. -//! -//! \return Returns the value of one of the interrupt status registers. -// -//***************************************************************************** -uint32_t -CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg) -{ - uint32_t ui32Status; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - - // - // See which status the caller is looking for. - // - switch(eIntStsReg) - { - // - // The caller wants the global interrupt status for the CAN controller - // specified by ui32Base. - // - case CAN_INT_STS_CAUSE: - { - ui32Status = HWREG(ui32Base + CAN_O_INT); - break; - } - - // - // The caller wants the current message status interrupt for all - // messages. - // - case CAN_INT_STS_OBJECT: - { - // - // Read and combine both 16 bit values into one 32bit status. - // - ui32Status = (HWREG(ui32Base + CAN_O_MSG1INT) & - CAN_MSG1INT_INTPND_M); - ui32Status |= (HWREG(ui32Base + CAN_O_MSG2INT) << 16); - break; - } - - // - // Request was for unknown status so just return 0. - // - default: - { - ui32Status = 0; - break; - } - } - - // - // Return the interrupt status value - // - return(ui32Status); -} - -//***************************************************************************** -// -//! Clears a CAN interrupt source. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param ui32IntClr is a value indicating which interrupt source to clear. -//! -//! This function can be used to clear a specific interrupt source. The -//! \e ui32IntClr parameter must be one of the following values: -//! -//! - \b CAN_INT_INTID_STATUS - Clears a status interrupt. -//! - 1-32 - Clears the specified message object interrupt -//! -//! It is not necessary to use this function to clear an interrupt. This -//! function is only used if the application wants to clear an interrupt -//! source without taking the normal interrupt action. -//! -//! Normally, the status interrupt is cleared by reading the controller status -//! using CANStatusGet(). A specific message object interrupt is normally -//! cleared by reading the message object using CANMessageGet(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr) -{ - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT((ui32IntClr == CAN_INT_INTID_STATUS) || - ((ui32IntClr >= 1) && (ui32IntClr <= 32))); - - if(ui32IntClr == CAN_INT_INTID_STATUS) - { - // - // Simply read and discard the status to clear the interrupt. - // - HWREG(ui32Base + CAN_O_STS); - } - else - { - // - // Wait to be sure that this interface is not busy. - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) - { - } - - // - // Only change the interrupt pending state by setting only the - // CAN_IF1CMSK_CLRINTPND bit. - // - HWREG(ui32Base + CAN_O_IF1CMSK) = CAN_IF1CMSK_CLRINTPND; - - // - // Send the clear pending interrupt command to the CAN controller. - // - HWREG(ui32Base + CAN_O_IF1CRQ) = ui32IntClr & CAN_IF1CRQ_MNUM_M; - - // - // Wait to be sure that this interface is not busy. - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) - { - } - } -} - -//***************************************************************************** -// -//! Sets the CAN controller automatic retransmission behavior. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param bAutoRetry enables automatic retransmission. -//! -//! This function enables or disables automatic retransmission of messages with -//! detected errors. If \e bAutoRetry is \b true, then automatic -//! retransmission is enabled, otherwise it is disabled. -//! -//! \return None. -// -//***************************************************************************** -void -CANRetrySet(uint32_t ui32Base, bool bAutoRetry) -{ - uint32_t ui32CtlReg; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - - ui32CtlReg = HWREG(ui32Base + CAN_O_CTL); - - // - // Conditionally set the DAR bit to enable/disable auto-retry. - // - if(bAutoRetry) - { - // - // Clearing the DAR bit tells the controller to not disable the - // auto-retry of messages which were not transmitted or received - // correctly. - // - ui32CtlReg &= ~CAN_CTL_DAR; - } - else - { - // - // Setting the DAR bit tells the controller to disable the auto-retry - // of messages which were not transmitted or received correctly. - // - ui32CtlReg |= CAN_CTL_DAR; - } - - HWREG(ui32Base + CAN_O_CTL) = ui32CtlReg; -} - -//***************************************************************************** -// -//! Returns the current setting for automatic retransmission. -//! -//! \param ui32Base is the base address of the CAN controller. -//! -//! This function reads the current setting for automatic retransmission in the -//! CAN controller and returns it to the caller. -//! -//! \return Returns \b true if automatic retransmission is enabled, \b false -//! otherwise. -// -//***************************************************************************** -bool -CANRetryGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - - // - // Read the disable automatic retry setting from the CAN controller. - // - if(HWREG(ui32Base + CAN_O_CTL) & CAN_CTL_DAR) - { - // - // Automatic data retransmission is not enabled. - // - return(false); - } - - // - // Automatic data retransmission is enabled. - // - return(true); -} - -//***************************************************************************** -// -//! Reads one of the controller status registers. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param eStatusReg is the status register to read. -//! -//! This function reads a status register of the CAN controller and returns it -//! to the caller. -//! The different status registers are: -//! -//! - \b CAN_STS_CONTROL - the main controller status -//! - \b CAN_STS_TXREQUEST - bit mask of objects pending transmission -//! - \b CAN_STS_NEWDAT - bit mask of objects with new data -//! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration -//! -//! When reading the main controller status register, a pending status -//! interrupt is cleared. This parameter is used in the interrupt -//! handler for the CAN controller if the cause is a status interrupt. The -//! controller status register fields are as follows: -//! -//! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition -//! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96 -//! - \b CAN_STATUS_EPASS - CAN controller is in the error passive state -//! - \b CAN_STATUS_RXOK - a message was received successfully (independent of -//! any message filtering). -//! - \b CAN_STATUS_TXOK - a message was successfully transmitted -//! - \b CAN_STATUS_LEC_MSK - mask of last error code bits (3 bits) -//! - \b CAN_STATUS_LEC_NONE - no error -//! - \b CAN_STATUS_LEC_STUFF - stuffing error detected -//! - \b CAN_STATUS_LEC_FORM - a format error occurred in the fixed format part -//! of a message -//! - \b CAN_STATUS_LEC_ACK - a transmitted message was not acknowledged -//! - \b CAN_STATUS_LEC_BIT1 - dominant level detected when trying to send in -//! recessive mode -//! - \b CAN_STATUS_LEC_BIT0 - recessive level detected when trying to send in -//! dominant mode -//! - \b CAN_STATUS_LEC_CRC - CRC error in received message -//! -//! The remaining status registers consist of 32-bit-wide bit maps to the -//! message objects. They can be used to quickly obtain information about the -//! status of all the message objects without needing to query each one. They -//! contain the following information: -//! -//! - \b CAN_STS_TXREQUEST - if a message object's TXRQST bit is set, a -//! transmission is pending on that object. The application can use this -//! information to determine which objects are still waiting to send a -//! message. -//! - \b CAN_STS_NEWDAT - if a message object's NEWDAT bit is set, a new -//! message has been received in that object, and has not yet been picked up -//! by the host application -//! - \b CAN_STS_MSGVAL - if a message object's MSGVAL bit is set, the object -//! has a valid configuration programmed. The host application can use this -//! information to determine which message objects are empty/unused. -//! -//! \return Returns the value of the status register. -// -//***************************************************************************** -uint32_t -CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg) -{ - uint32_t ui32Status; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - - switch(eStatusReg) - { - // - // Just return the global CAN status register since that is what was - // requested. - // - case CAN_STS_CONTROL: - { - ui32Status = HWREG(ui32Base + CAN_O_STS); - HWREG(ui32Base + CAN_O_STS) = ~(CAN_STS_RXOK | CAN_STS_TXOK | - CAN_STS_LEC_M); - break; - } - - // - // Combine the Transmit status bits into one 32bit value. - // - case CAN_STS_TXREQUEST: - { - ui32Status = HWREG(ui32Base + CAN_O_TXRQ1); - ui32Status |= HWREG(ui32Base + CAN_O_TXRQ2) << 16; - break; - } - - // - // Combine the New Data status bits into one 32bit value. - // - case CAN_STS_NEWDAT: - { - ui32Status = HWREG(ui32Base + CAN_O_NWDA1); - ui32Status |= HWREG(ui32Base + CAN_O_NWDA2) << 16; - break; - } - - // - // Combine the Message valid status bits into one 32bit value. - // - case CAN_STS_MSGVAL: - { - ui32Status = HWREG(ui32Base + CAN_O_MSG1VAL); - ui32Status |= HWREG(ui32Base + CAN_O_MSG2VAL) << 16; - break; - } - - // - // Unknown CAN status requested so return 0. - // - default: - { - ui32Status = 0; - break; - } - } - return(ui32Status); -} - -//***************************************************************************** -// -//! Reads the CAN controller error counter register. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param pui32RxCount is a pointer to storage for the receive error counter. -//! \param pui32TxCount is a pointer to storage for the transmit error counter. -//! -//! This function reads the error counter register and returns the transmit and -//! receive error counts to the caller along with a flag indicating if the -//! controller receive counter has reached the error passive limit. The values -//! of the receive and transmit error counters are returned through the -//! pointers provided as parameters. -//! -//! After this call, \e *pui32RxCount holds the current receive error count -//! and \e *pui32TxCount holds the current transmit error count. -//! -//! \return Returns \b true if the receive error count has reached the error -//! passive limit, and \b false if the error count is below the error passive -//! limit. -// -//***************************************************************************** -bool -CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, - uint32_t *pui32TxCount) -{ - uint32_t ui32CANError; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - - // - // Read the current count of transmit/receive errors. - // - ui32CANError = HWREG(ui32Base + CAN_O_ERR); - - // - // Extract the error numbers from the register value. - // - *pui32RxCount = (ui32CANError & CAN_ERR_REC_M) >> CAN_ERR_REC_S; - *pui32TxCount = (ui32CANError & CAN_ERR_TEC_M) >> CAN_ERR_TEC_S; - - if(ui32CANError & CAN_ERR_RP) - { - return(true); - } - return(false); -} - -//***************************************************************************** -// -//! Configures a message object in the CAN controller. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param ui32ObjID is the object number to configure (1-32). -//! \param psMsgObject is a pointer to a structure containing message object -//! settings. -//! \param eMsgType indicates the type of message for this object. -//! -//! This function is used to configure any one of the 32 message objects in the -//! CAN controller. A message object can be configured to be any type of CAN -//! message object as well as to use automatic transmission and reception. -//! This call also allows the message object to be configured to generate -//! interrupts on completion of message receipt or transmission. The -//! message object can also be configured with a filter/mask so that actions -//! are only taken when a message that meets certain parameters is seen on the -//! CAN bus. -//! -//! The \e eMsgType parameter must be one of the following values: -//! -//! - \b MSG_OBJ_TYPE_TX - CAN transmit message object. -//! - \b MSG_OBJ_TYPE_TX_REMOTE - CAN transmit remote request message object. -//! - \b MSG_OBJ_TYPE_RX - CAN receive message object. -//! - \b MSG_OBJ_TYPE_RX_REMOTE - CAN receive remote request message object. -//! - \b MSG_OBJ_TYPE_RXTX_REMOTE - CAN remote frame receive remote, then -//! transmit message object. -//! -//! The message object pointed to by \e psMsgObject must be populated by the -//! caller, as follows: -//! -//! - \e ui32MsgID - contains the message ID, either 11 or 29 bits. -//! - \e ui32MsgIDMask - mask of bits from \e ui32MsgID that must match if -//! identifier filtering is enabled. -//! - \e ui32Flags -//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to enable interrupt on transmission. -//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt. -//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the -//! identifier mask specified by \e ui32MsgIDMask. -//! - \e ui32MsgLen - the number of bytes in the message data. This parameter -//! must be non-zero even for a remote frame; it must match the expected -//! bytes of data in the responding data frame. -//! - \e pui8MsgData - points to a buffer containing up to 8 bytes of data for -//! a data frame. -//! -//! \b Example: To send a data frame or remote frame (in response to a remote -//! request), take the following steps: -//! -//! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX. -//! -# Set \e psMsgObject->ui32MsgID to the message ID. -//! -# Set \e psMsgObject->ui32Flags. Make sure to set -//! \b MSG_OBJ_TX_INT_ENABLE to allow an interrupt to be generated when the -//! message is sent. -//! -# Set \e psMsgObject->ui32MsgLen to the number of bytes in the data frame. -//! -# Set \e psMsgObject->pui8MsgData to point to an array containing the -//! bytes to send in the message. -//! -# Call this function with \e ui32ObjID set to one of the 32 object -//! buffers. -//! -//! \b Example: To receive a specific data frame, take the following steps: -//! -//! -# Set \e eMsgObjType to \b MSG_OBJ_TYPE_RX. -//! -# Set \e psMsgObject->ui32MsgID to the full message ID, or a partial mask -//! to use partial ID matching. -//! -# Set \e psMsgObject->ui32MsgIDMask bits that are used for masking -//! during comparison. -//! -# Set \e psMsgObject->ui32Flags as follows: -//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to be interrupted when the data -//! frame is received. -//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier-based -//! filtering. -//! -# Set \e psMsgObject->ui32MsgLen to the number of bytes in the expected -//! data frame. -//! -# The buffer pointed to by \e psMsgObject->pui8MsgData is not used by this -//! call as no data is present at the time of the call. -//! -# Call this function with \e ui32ObjID set to one of the 32 object -//! buffers. -//! -//! If you specify a message object buffer that already contains a message -//! definition, it is overwritten. -//! -//! \return None. -// -//***************************************************************************** -void -CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, - tCANMsgObject *psMsgObject, tMsgObjType eMsgType) -{ - uint16_t ui16CmdMaskReg; - uint16_t ui16MaskReg0, ui16MaskReg1; - uint16_t ui16ArbReg0, ui16ArbReg1; - uint16_t ui16MsgCtrl; - bool bTransferData; - bool bUseExtendedID; - - bTransferData = 0; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0)); - ASSERT((eMsgType == MSG_OBJ_TYPE_TX) || - (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || - (eMsgType == MSG_OBJ_TYPE_RX) || - (eMsgType == MSG_OBJ_TYPE_RX_REMOTE) || - (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || - (eMsgType == MSG_OBJ_TYPE_RXTX_REMOTE)); - - // - // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) - { - } - - // - // See if we need to use an extended identifier or not. - // - if((psMsgObject->ui32MsgID > CAN_MAX_11BIT_MSG_ID) || - (psMsgObject->ui32Flags & MSG_OBJ_EXTENDED_ID)) - { - bUseExtendedID = 1; - } - else - { - bUseExtendedID = 0; - } - - // - // This is always a write to the Message object as this call is setting a - // message object. This call always sets all size bits so it sets - // both data bits. The call uses the CONTROL register to set control - // bits so this bit needs to be set as well. - // - ui16CmdMaskReg = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_DATAA | - CAN_IF1CMSK_DATAB | CAN_IF1CMSK_CONTROL); - - // - // Initialize the values to a known state before filling them in based on - // the type of message object that is being configured. - // - ui16ArbReg0 = 0; - ui16ArbReg1 = 0; - ui16MsgCtrl = 0; - ui16MaskReg0 = 0; - ui16MaskReg1 = 0; - - switch(eMsgType) - { - // - // Transmit message object. - // - case MSG_OBJ_TYPE_TX: - { - // - // Set the TXRQST bit and the reset the rest of the register. - // - ui16MsgCtrl |= CAN_IF1MCTL_TXRQST; - ui16ArbReg1 = CAN_IF1ARB2_DIR; - bTransferData = 1; - break; - } - - // - // Transmit remote request message object - // - case MSG_OBJ_TYPE_TX_REMOTE: - { - // - // Set the TXRQST bit and the reset the rest of the register. - // - ui16MsgCtrl |= CAN_IF1MCTL_TXRQST; - ui16ArbReg1 = 0; - break; - } - - // - // Receive message object. - // - case MSG_OBJ_TYPE_RX: - { - // - // This clears the DIR bit along with everything else. The TXRQST - // bit was cleared by defaulting ui16MsgCtrl to 0. - // - ui16ArbReg1 = 0; - break; - } - - // - // Receive remote request message object. - // - case MSG_OBJ_TYPE_RX_REMOTE: - { - // - // The DIR bit is set to one for remote receivers. The TXRQST bit - // was cleared by defaulting ui16MsgCtrl to 0. - // - ui16ArbReg1 = CAN_IF1ARB2_DIR; - - // - // Set this object so that it only indicates that a remote frame - // was received and allow for software to handle it by sending back - // a data frame. - // - ui16MsgCtrl = CAN_IF1MCTL_UMASK; - - // - // Use the full Identifier by default. - // - ui16MaskReg0 = 0xffff; - ui16MaskReg1 = 0x1fff; - - // - // Make sure to send the mask to the message object. - // - ui16CmdMaskReg |= CAN_IF1CMSK_MASK; - break; - } - - // - // Remote frame receive remote, with auto-transmit message object. - // - case MSG_OBJ_TYPE_RXTX_REMOTE: - { - // - // Oddly the DIR bit is set to one for remote receivers. - // - ui16ArbReg1 = CAN_IF1ARB2_DIR; - - // - // Set this object to auto answer if a matching identifier is seen. - // - ui16MsgCtrl = CAN_IF1MCTL_RMTEN | CAN_IF1MCTL_UMASK; - - // - // The data to be returned needs to be filled in. - // - bTransferData = 1; - break; - } - - // - // This case never happens due to the ASSERT statement at the - // beginning of this function. - // - default: - { - return; - } - } - - // - // Configure the Mask Registers. - // - if(psMsgObject->ui32Flags & MSG_OBJ_USE_ID_FILTER) - { - if(bUseExtendedID) - { - // - // Set the 29 bits of Identifier mask that were requested. - // - ui16MaskReg0 = psMsgObject->ui32MsgIDMask & CAN_IF1MSK1_IDMSK_M; - ui16MaskReg1 = ((psMsgObject->ui32MsgIDMask >> 16) & - CAN_IF1MSK2_IDMSK_M); - } - else - { - // - // Lower 16 bit are unused so set them to zero. - // - ui16MaskReg0 = 0; - - // - // Put the 11 bit Mask Identifier into the upper bits of the field - // in the register. - // - ui16MaskReg1 = ((psMsgObject->ui32MsgIDMask << 2) & - CAN_IF1MSK2_IDMSK_M); - } - } - - // - // If the caller wants to filter on the extended ID bit then set it. - // - if((psMsgObject->ui32Flags & MSG_OBJ_USE_EXT_FILTER) == - MSG_OBJ_USE_EXT_FILTER) - { - ui16MaskReg1 |= CAN_IF1MSK2_MXTD; - } - - // - // The caller wants to filter on the message direction field. - // - if((psMsgObject->ui32Flags & MSG_OBJ_USE_DIR_FILTER) == - MSG_OBJ_USE_DIR_FILTER) - { - ui16MaskReg1 |= CAN_IF1MSK2_MDIR; - } - - if(psMsgObject->ui32Flags & - (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER | - MSG_OBJ_USE_EXT_FILTER)) - { - // - // Set the UMASK bit to enable using the mask register. - // - ui16MsgCtrl |= CAN_IF1MCTL_UMASK; - - // - // Set the MASK bit so that this gets transferred to the Message - // Object. - // - ui16CmdMaskReg |= CAN_IF1CMSK_MASK; - } - - // - // Set the Arb bit so that this gets transferred to the Message object. - // - ui16CmdMaskReg |= CAN_IF1CMSK_ARB; - - // - // Configure the Arbitration registers. - // - if(bUseExtendedID) - { - // - // Set the 29 bit version of the Identifier for this message object. - // - ui16ArbReg0 |= psMsgObject->ui32MsgID & CAN_IF1ARB1_ID_M; - ui16ArbReg1 |= (psMsgObject->ui32MsgID >> 16) & CAN_IF1ARB2_ID_M; - - // - // Mark the message as valid and set the extended ID bit. - // - ui16ArbReg1 |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD; - } - else - { - // - // Set the 11 bit version of the Identifier for this message object. - // The lower 18 bits are set to zero. - // - ui16ArbReg1 |= (psMsgObject->ui32MsgID << 2) & CAN_IF1ARB2_ID_M; - - // - // Mark the message as valid. - // - ui16ArbReg1 |= CAN_IF1ARB2_MSGVAL; - } - - // - // Set the data length since this is set for all transfers. This is also a - // single transfer and not a FIFO transfer so set EOB bit. - // - ui16MsgCtrl |= (psMsgObject->ui32MsgLen & CAN_IF1MCTL_DLC_M); - - // - // Mark this as the last entry if this is not the last entry in a FIFO. - // - if((psMsgObject->ui32Flags & MSG_OBJ_FIFO) == 0) - { - ui16MsgCtrl |= CAN_IF1MCTL_EOB; - } - - // - // Enable transmit interrupts if they should be enabled. - // - if(psMsgObject->ui32Flags & MSG_OBJ_TX_INT_ENABLE) - { - ui16MsgCtrl |= CAN_IF1MCTL_TXIE; - } - - // - // Enable receive interrupts if they should be enabled. - // - if(psMsgObject->ui32Flags & MSG_OBJ_RX_INT_ENABLE) - { - ui16MsgCtrl |= CAN_IF1MCTL_RXIE; - } - - // - // Write the data out to the CAN Data registers if needed. - // - if(bTransferData) - { - _CANDataRegWrite(psMsgObject->pui8MsgData, - (uint32_t *)(ui32Base + CAN_O_IF1DA1), - psMsgObject->ui32MsgLen); - } - - // - // Write out the registers to program the message object. - // - HWREG(ui32Base + CAN_O_IF1CMSK) = ui16CmdMaskReg; - HWREG(ui32Base + CAN_O_IF1MSK1) = ui16MaskReg0; - HWREG(ui32Base + CAN_O_IF1MSK2) = ui16MaskReg1; - HWREG(ui32Base + CAN_O_IF1ARB1) = ui16ArbReg0; - HWREG(ui32Base + CAN_O_IF1ARB2) = ui16ArbReg1; - HWREG(ui32Base + CAN_O_IF1MCTL) = ui16MsgCtrl; - - // - // Transfer the message object to the message object specified by - // ui32ObjID. - // - HWREG(ui32Base + CAN_O_IF1CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; -} - -//***************************************************************************** -// -//! Reads a CAN message from one of the message object buffers. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param ui32ObjID is the object number to read (1-32). -//! \param psMsgObject points to a structure containing message object fields. -//! \param bClrPendingInt indicates whether an associated interrupt should be -//! cleared. -//! -//! This function is used to read the contents of one of the 32 message objects -//! in the CAN controller and return it to the caller. The data returned is -//! stored in the fields of the caller-supplied structure pointed to by -//! \e psMsgObject. The data consists of all of the parts of a CAN message, -//! plus some control and status information. -//! -//! Normally, this function is used to read a message object that has received -//! and stored a CAN message with a certain identifier. However, this function -//! could also be used to read the contents of a message object in order to -//! load the fields of the structure in case only part of the structure must -//! be changed from a previous setting. -//! -//! When using CANMessageGet(), all of the same fields of the structure are -//! populated in the same way as when the CANMessageSet() function is used, -//! with the following exceptions: -//! -//! \e psMsgObject->ui32Flags: -//! -//! - \b MSG_OBJ_NEW_DATA indicates if this data is new since the last time it -//! was read -//! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on -//! this message object and not read by the host before being overwritten. -//! -//! \return None. -// -//***************************************************************************** -void -CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, - tCANMsgObject *psMsgObject, bool bClrPendingInt) -{ - uint16_t ui16CmdMaskReg; - uint16_t ui16MaskReg0, ui16MaskReg1; - uint16_t ui16ArbReg0, ui16ArbReg1; - uint16_t ui16MsgCtrl; - - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0)); - - // - // This is always a read to the Message object as this call is setting a - // message object. - // - ui16CmdMaskReg = (CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB | - CAN_IF1CMSK_CONTROL | CAN_IF1CMSK_MASK | - CAN_IF1CMSK_ARB); - - // - // Clear a pending interrupt and new data in a message object. - // - if(bClrPendingInt) - { - ui16CmdMaskReg |= CAN_IF1CMSK_CLRINTPND; - } - - // - // Set up the request for data from the message object. - // - HWREG(ui32Base + CAN_O_IF2CMSK) = ui16CmdMaskReg; - - // - // Transfer the message object to the message object specified by - // ui32ObjID. - // - HWREG(ui32Base + CAN_O_IF2CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; - - // - // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY) - { - } - - // - // Read out the IF Registers. - // - ui16MaskReg0 = HWREG(ui32Base + CAN_O_IF2MSK1); - ui16MaskReg1 = HWREG(ui32Base + CAN_O_IF2MSK2); - ui16ArbReg0 = HWREG(ui32Base + CAN_O_IF2ARB1); - ui16ArbReg1 = HWREG(ui32Base + CAN_O_IF2ARB2); - ui16MsgCtrl = HWREG(ui32Base + CAN_O_IF2MCTL); - - psMsgObject->ui32Flags = MSG_OBJ_NO_FLAGS; - - // - // Determine if this is a remote frame by checking the TXRQST and DIR bits. - // - if((!(ui16MsgCtrl & CAN_IF1MCTL_TXRQST) && - (ui16ArbReg1 & CAN_IF1ARB2_DIR)) || - ((ui16MsgCtrl & CAN_IF1MCTL_TXRQST) && - (!(ui16ArbReg1 & CAN_IF1ARB2_DIR)))) - { - psMsgObject->ui32Flags |= MSG_OBJ_REMOTE_FRAME; - } - - // - // Get the identifier out of the register, the format depends on size of - // the mask. - // - if(ui16ArbReg1 & CAN_IF1ARB2_XTD) - { - // - // Set the 29 bit version of the Identifier for this message object. - // - psMsgObject->ui32MsgID = (((ui16ArbReg1 & CAN_IF1ARB2_ID_M) << 16) | - ui16ArbReg0); - - psMsgObject->ui32Flags |= MSG_OBJ_EXTENDED_ID; - } - else - { - // - // The Identifier is an 11 bit value. - // - psMsgObject->ui32MsgID = (ui16ArbReg1 & CAN_IF1ARB2_ID_M) >> 2; - } - - // - // Indicate that we lost some data. - // - if(ui16MsgCtrl & CAN_IF1MCTL_MSGLST) - { - psMsgObject->ui32Flags |= MSG_OBJ_DATA_LOST; - } - - // - // Set the flag to indicate if ID masking was used. - // - if(ui16MsgCtrl & CAN_IF1MCTL_UMASK) - { - if(ui16ArbReg1 & CAN_IF1ARB2_XTD) - { - // - // The Identifier Mask is assumed to also be a 29 bit value. - // - psMsgObject->ui32MsgIDMask = - ((ui16MaskReg1 & CAN_IF1MSK2_IDMSK_M) << 16) | ui16MaskReg0; - - // - // If this is a fully specified Mask and a remote frame then don't - // set the MSG_OBJ_USE_ID_FILTER because the ID was not really - // filtered. - // - if((psMsgObject->ui32MsgIDMask != 0x1fffffff) || - ((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)) - { - psMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER; - } - } - else - { - // - // The Identifier Mask is assumed to also be an 11 bit value. - // - psMsgObject->ui32MsgIDMask = - (ui16MaskReg1 & CAN_IF1MSK2_IDMSK_M) >> 2; - - // - // If this is a fully specified Mask and a remote frame then don't - // set the MSG_OBJ_USE_ID_FILTER because the ID was not really - // filtered. - // - if((psMsgObject->ui32MsgIDMask != 0x7ff) || - ((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)) - { - psMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER; - } - } - - // - // Indicate if the extended bit was used in filtering. - // - if(ui16MaskReg1 & CAN_IF1MSK2_MXTD) - { - psMsgObject->ui32Flags |= MSG_OBJ_USE_EXT_FILTER; - } - - // - // Indicate if direction filtering was enabled. - // - if(ui16MaskReg1 & CAN_IF1MSK2_MDIR) - { - psMsgObject->ui32Flags |= MSG_OBJ_USE_DIR_FILTER; - } - } - - // - // Set the interrupt flags. - // - if(ui16MsgCtrl & CAN_IF1MCTL_TXIE) - { - psMsgObject->ui32Flags |= MSG_OBJ_TX_INT_ENABLE; - } - if(ui16MsgCtrl & CAN_IF1MCTL_RXIE) - { - psMsgObject->ui32Flags |= MSG_OBJ_RX_INT_ENABLE; - } - - // - // See if there is new data available. - // - if(ui16MsgCtrl & CAN_IF1MCTL_NEWDAT) - { - // - // Get the amount of data needed to be read. - // - psMsgObject->ui32MsgLen = (ui16MsgCtrl & CAN_IF1MCTL_DLC_M); - - // - // Don't read any data for a remote frame, there is nothing valid in - // that buffer anyway. - // - if((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0) - { - // - // Read out the data from the CAN registers. - // - _CANDataRegRead(psMsgObject->pui8MsgData, - (uint32_t *)(ui32Base + CAN_O_IF2DA1), - psMsgObject->ui32MsgLen); - } - - // - // Now clear out the new data flag. - // - HWREG(ui32Base + CAN_O_IF2CMSK) = CAN_IF1CMSK_NEWDAT; - - // - // Transfer the message object to the message object specified by - // ui32ObjID. - // - HWREG(ui32Base + CAN_O_IF2CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; - - // - // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY) - { - } - - // - // Indicate that there is new data in this message. - // - psMsgObject->ui32Flags |= MSG_OBJ_NEW_DATA; - } - else - { - // - // Along with the MSG_OBJ_NEW_DATA not being set the amount of data - // needs to be set to zero if none was available. - // - psMsgObject->ui32MsgLen = 0; - } -} - -//***************************************************************************** -// -//! Clears a message object so that it is no longer used. -//! -//! \param ui32Base is the base address of the CAN controller. -//! \param ui32ObjID is the message object number to disable (1-32). -//! -//! This function frees the specified message object from use. Once a message -//! object has been ``cleared,'' it no longer automatically sends or receives -//! messages, nor does it generate interrupts. -//! -//! \return None. -// -//***************************************************************************** -void -CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID) -{ - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT((ui32ObjID >= 1) && (ui32ObjID <= 32)); - - // - // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) - { - } - - // - // Clear the message value bit in the arbitration register. This indicates - // the message is not valid. - // - HWREG(ui32Base + CAN_O_IF1CMSK) = CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB; - HWREG(ui32Base + CAN_O_IF1ARB1) = 0; - HWREG(ui32Base + CAN_O_IF1ARB2) = 0; - - // - // Initiate programming the message object - // - HWREG(ui32Base + CAN_O_IF1CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/can.h b/bsp/tm4c129x-dk/libraries/driverlib/can.h deleted file mode 100644 index 199721906b02823c2111652952dc1eda006b3099..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/can.h +++ /dev/null @@ -1,449 +0,0 @@ -//***************************************************************************** -// -// can.h - Defines and Macros for the CAN controller. -// -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_CAN_H__ -#define __DRIVERLIB_CAN_H__ - -//***************************************************************************** -// -//! \addtogroup can_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Miscellaneous defines for Message ID Types -// -//***************************************************************************** - -//***************************************************************************** -// -// These are the flags used by the tCANMsgObject.ui32Flags value when calling -// the CANMessageSet() and CANMessageGet() functions. -// -//***************************************************************************** - -// -//! This indicates that transmit interrupts are enabled. -// -#define MSG_OBJ_TX_INT_ENABLE 0x00000001 - -// -//! This indicates that receive interrupts are enabled. -// -#define MSG_OBJ_RX_INT_ENABLE 0x00000002 - -// -//! This indicates that a message object is using an extended identifier. -// -#define MSG_OBJ_EXTENDED_ID 0x00000004 - -// -//! This indicates that a message object is using filtering based on the -//! object's message identifier. -// -#define MSG_OBJ_USE_ID_FILTER 0x00000008 - -// -//! This indicates that new data was available in the message object. -// -#define MSG_OBJ_NEW_DATA 0x00000080 - -// -//! This indicates that data was lost since this message object was last -//! read. -// -#define MSG_OBJ_DATA_LOST 0x00000100 - -// -//! This indicates that a message object uses or is using filtering -//! based on the direction of the transfer. If the direction filtering is -//! used, then ID filtering must also be enabled. -// -#define MSG_OBJ_USE_DIR_FILTER (0x00000010 | MSG_OBJ_USE_ID_FILTER) - -// -//! This indicates that a message object uses or is using message -//! identifier filtering based on the extended identifier. If the extended -//! identifier filtering is used, then ID filtering must also be enabled. -// -#define MSG_OBJ_USE_EXT_FILTER (0x00000020 | MSG_OBJ_USE_ID_FILTER) - -// -//! This indicates that a message object is a remote frame. -// -#define MSG_OBJ_REMOTE_FRAME 0x00000040 - -// -//! This indicates that this message object is part of a FIFO structure and -//! not the final message object in a FIFO. -// -#define MSG_OBJ_FIFO 0x00000200 - -// -//! This indicates that a message object has no flags set. -// -#define MSG_OBJ_NO_FLAGS 0x00000000 - -//***************************************************************************** -// -//! This define is used with the flag values to allow checking only status -//! flags and not configuration flags. -// -//***************************************************************************** -#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) - -//***************************************************************************** -// -//! The structure used for encapsulating all the items associated with a CAN -//! message object in the CAN controller. -// -//***************************************************************************** -typedef struct -{ - // - //! The CAN message identifier used for 11 or 29 bit identifiers. - // - uint32_t ui32MsgID; - - // - //! The message identifier mask used when identifier filtering is enabled. - // - uint32_t ui32MsgIDMask; - - // - //! This value holds various status flags and settings specified by - //! tCANObjFlags. - // - uint32_t ui32Flags; - - // - //! This value is the number of bytes of data in the message object. - // - uint32_t ui32MsgLen; - - // - //! This is a pointer to the message object's data. - // - uint8_t *pui8MsgData; -} -tCANMsgObject; - -//***************************************************************************** -// -//! This structure is used for encapsulating the values associated with setting -//! up the bit timing for a CAN controller. The structure is used when calling -//! the CANGetBitTiming and CANSetBitTiming functions. -// -//***************************************************************************** -typedef struct -{ - // - //! This value holds the sum of the Synchronization, Propagation, and Phase - //! Buffer 1 segments, measured in time quanta. The valid values for this - //! setting range from 2 to 16. - // - uint32_t ui32SyncPropPhase1Seg; - - // - //! This value holds the Phase Buffer 2 segment in time quanta. The valid - //! values for this setting range from 1 to 8. - // - uint32_t ui32Phase2Seg; - - // - //! This value holds the Resynchronization Jump Width in time quanta. The - //! valid values for this setting range from 1 to 4. - // - uint32_t ui32SJW; - - // - //! This value holds the CAN_CLK divider used to determine time quanta. - //! The valid values for this setting range from 1 to 1023. - // - uint32_t ui32QuantumPrescaler; -} -tCANBitClkParms; - -//***************************************************************************** -// -//! This data type is used to identify the interrupt status register. This is -//! used when calling the CANIntStatus() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the CAN interrupt status information. - // - CAN_INT_STS_CAUSE, - - // - //! Read a message object's interrupt status. - // - CAN_INT_STS_OBJECT -} -tCANIntStsReg; - -//***************************************************************************** -// -//! This data type is used to identify which of several status registers to -//! read when calling the CANStatusGet() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the full CAN controller status. - // - CAN_STS_CONTROL, - - // - //! Read the full 32-bit mask of message objects with a transmit request - //! set. - // - CAN_STS_TXREQUEST, - - // - //! Read the full 32-bit mask of message objects with new data available. - // - CAN_STS_NEWDAT, - - // - //! Read the full 32-bit mask of message objects that are enabled. - // - CAN_STS_MSGVAL -} -tCANStsReg; - -//***************************************************************************** -// -// These definitions are used to specify interrupt sources to CANIntEnable() -// and CANIntDisable(). -// -//***************************************************************************** -// -//! This flag is used to allow a CAN controller to generate error -//! interrupts. -// -#define CAN_INT_ERROR 0x00000008 - -// -//! This flag is used to allow a CAN controller to generate status -//! interrupts. -// -#define CAN_INT_STATUS 0x00000004 - -// -//! This flag is used to allow a CAN controller to generate any CAN -//! interrupts. If this is not set, then no interrupts are generated -//! by the CAN controller. -// -#define CAN_INT_MASTER 0x00000002 - -//***************************************************************************** -// -//! This definition is used to determine the type of message object that is -//! set up via a call to the CANMessageSet() API. -// -//***************************************************************************** -typedef enum -{ - // - //! Transmit message object. - // - MSG_OBJ_TYPE_TX, - - // - //! Transmit remote request message object - // - MSG_OBJ_TYPE_TX_REMOTE, - - // - //! Receive message object. - // - MSG_OBJ_TYPE_RX, - - // - //! Receive remote request message object. - // - MSG_OBJ_TYPE_RX_REMOTE, - - // - //! Remote frame receive remote, with auto-transmit message object. - // - MSG_OBJ_TYPE_RXTX_REMOTE -} -tMsgObjType; - -//***************************************************************************** -// -// The following enumeration contains all error or status indicators that can -// be returned when calling the CANStatusGet() function. -// -//***************************************************************************** -// -//! CAN controller has entered a Bus Off state. -// -#define CAN_STATUS_BUS_OFF 0x00000080 - -// -//! CAN controller error level has reached warning level. -// -#define CAN_STATUS_EWARN 0x00000040 - -// -//! CAN controller error level has reached error passive level. -// -#define CAN_STATUS_EPASS 0x00000020 - -// -//! A message was received successfully since the last read of this status. -// -#define CAN_STATUS_RXOK 0x00000010 - -// -//! A message was transmitted successfully since the last read of this -//! status. -// -#define CAN_STATUS_TXOK 0x00000008 - -// -//! This is the mask for the last error code field. -// -#define CAN_STATUS_LEC_MSK 0x00000007 - -// -//! There was no error. -// -#define CAN_STATUS_LEC_NONE 0x00000000 - -// -//! A bit stuffing error has occurred. -// -#define CAN_STATUS_LEC_STUFF 0x00000001 - -// -//! A formatting error has occurred. -// -#define CAN_STATUS_LEC_FORM 0x00000002 - -// -//! An acknowledge error has occurred. -// -#define CAN_STATUS_LEC_ACK 0x00000003 - -// -//! The bus remained a bit level of 1 for longer than is allowed. -// -#define CAN_STATUS_LEC_BIT1 0x00000004 - -// -//! The bus remained a bit level of 0 for longer than is allowed. -// -#define CAN_STATUS_LEC_BIT0 0x00000005 - -// -//! A CRC error has occurred. -// -#define CAN_STATUS_LEC_CRC 0x00000006 - -// -//! This is the mask for the CAN Last Error Code (LEC). -// -#define CAN_STATUS_LEC_MASK 0x00000007 - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms); -extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms); -extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, - uint32_t ui32BitRate); -extern void CANDisable(uint32_t ui32Base); -extern void CANEnable(uint32_t ui32Base); -extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, - uint32_t *pui32TxCount); -extern void CANInit(uint32_t ui32Base); -extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr); -extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg); -extern void CANIntUnregister(uint32_t ui32Base); -extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID); -extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, - tCANMsgObject *psMsgObject, bool bClrPendingInt); -extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, - tCANMsgObject *psMsgObject, tMsgObjType eMsgType); -extern bool CANRetryGet(uint32_t ui32Base); -extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry); -extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_CAN_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/comp.c b/bsp/tm4c129x-dk/libraries/driverlib/comp.c deleted file mode 100644 index 6f03b7c01a75f8c8bce5feff761634adf7c00d48..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/comp.c +++ /dev/null @@ -1,452 +0,0 @@ -//***************************************************************************** -// -// comp.c - Driver for the analog comparator. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup comp_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_comp.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "driverlib/comp.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -//! Configures a comparator. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator to configure. -//! \param ui32Config is the configuration of the comparator. -//! -//! This function configures a comparator. The \e ui32Config parameter is the -//! result of a logical OR operation between the \b COMP_TRIG_xxx, -//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. -//! -//! The \b COMP_TRIG_xxx term can take on the following values: -//! -//! - \b COMP_TRIG_NONE to have no trigger to the ADC. -//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high. -//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low. -//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low. -//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes -//! high. -//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low -//! or high. -//! -//! The \b COMP_INT_xxx term can take on the following values: -//! -//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is -//! high. -//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is -//! low. -//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes -//! low. -//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes -//! high. -//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes -//! low or high. -//! -//! The \b COMP_ASRCP_xxx term can take on the following values: -//! -//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference -//! voltage. -//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this -//! the same as \b COMP_ASRCP_PIN for the comparator 0). -//! - \b COMP_ASRCP_REF to use the internally generated voltage as the -//! reference voltage. -//! -//! The \b COMP_OUTPUT_xxx term can take on the following values: -//! -//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator -//! to a device pin. -//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to -//! a device pin. -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Configure this comparator. - // - HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACCTL0) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the internal reference voltage. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Ref is the desired reference voltage. -//! -//! This function sets the internal reference voltage value. The voltage is -//! specified as one of the following values: -//! -//! - \b COMP_REF_OFF to turn off the reference voltage -//! - \b COMP_REF_0V to set the reference voltage to 0 V -//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V -//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V -//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V -//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V -//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V -//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V -//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V -//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V -//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V -//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V -//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V -//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V -//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V -//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V -//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V -//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V -//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V -//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V -//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V -//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V -//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V -//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V -//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V -//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V -//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V -//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V -//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - - // - // Set the voltage reference voltage as requested. - // - HWREG(ui32Base + COMP_O_ACREFCTL) = ui32Ref; -} - -//***************************************************************************** -// -//! Gets the current comparator output value. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! -//! This function retrieves the current value of the comparator output. -//! -//! \return Returns \b true if the comparator output is high and \b false if -//! the comparator output is low. -// -//***************************************************************************** -bool -ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Return the appropriate value based on the comparator's present output - // value. - // - if(HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACSTAT0) & - COMP_ACSTAT0_OVAL) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the comparator interrupt. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! \param pfnHandler is a pointer to the function to be called when the -//! comparator interrupt occurs. -//! -//! This function sets the handler to be called when the comparator interrupt -//! occurs and enables the interrupt in the interrupt controller. It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! ComparatorIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp, - void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_COMP0_TM4C123 + ui32Comp, pfnHandler); - - // - // Enable the interrupt in the interrupt controller. - // - IntEnable(INT_COMP0_TM4C123 + ui32Comp); - - // - // Enable the comparator interrupt. - // - HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp; -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a comparator interrupt. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! -//! This function clears the handler to be called when a comparator interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Disable the comparator interrupt. - // - HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp); - - // - // Disable the interrupt in the interrupt controller. - // - IntDisable(INT_COMP0_TM4C123 + ui32Comp); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_COMP0_TM4C123 + ui32Comp); -} - -//***************************************************************************** -// -//! Enables the comparator interrupt. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! -//! This function enables generation of an interrupt from the specified -//! comparator. Only enabled comparator interrupts can be reflected -//! to the processor. -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Enable the comparator interrupt. - // - HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp; -} - -//***************************************************************************** -// -//! Disables the comparator interrupt. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! -//! This function disables generation of an interrupt from the specified -//! comparator. Only enabled comparator interrupts can be reflected -//! to the processor. -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Disable the comparator interrupt. - // - HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the comparator. Either the -//! raw or the masked interrupt status can be returned. -//! -//! \return \b true if the interrupt is asserted and \b false if it is not -//! asserted. -// -//***************************************************************************** -bool -ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(((HWREG(ui32Base + COMP_O_ACMIS) >> ui32Comp) & 1) ? true : - false); - } - else - { - return(((HWREG(ui32Base + COMP_O_ACRIS) >> ui32Comp) & 1) ? true : - false); - } -} - -//***************************************************************************** -// -//! Clears a comparator interrupt. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! -//! The comparator interrupt is cleared, so that it no longer asserts. This -//! function must be called in the interrupt handler to keep the handler from -//! being called again immediately upon exit. Note that for a level-triggered -//! interrupt, the interrupt cannot be cleared until it stops asserting. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Clear the interrupt. - // - HWREG(ui32Base + COMP_O_ACMIS) = 1 << ui32Comp; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/comp.h b/bsp/tm4c129x-dk/libraries/driverlib/comp.h deleted file mode 100644 index 2f95df09c95c553890292737e821e50463ae0aa2..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/comp.h +++ /dev/null @@ -1,141 +0,0 @@ -//***************************************************************************** -// -// comp.h - Prototypes for the analog comparator driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_COMP_H__ -#define __DRIVERLIB_COMP_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ComparatorConfigure() as the ui32Config -// parameter. For each group (in other words, COMP_TRIG_xxx, COMP_INT_xxx, and -// so on), one of the values may be selected and combined together with values -// from the other groups via a logical OR. -// -//***************************************************************************** -#define COMP_TRIG_NONE 0x00000000 // No ADC trigger -#define COMP_TRIG_HIGH 0x00000880 // Trigger when high -#define COMP_TRIG_LOW 0x00000800 // Trigger when low -#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge -#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge -#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges -#define COMP_INT_HIGH 0x00000010 // Interrupt when high -#define COMP_INT_LOW 0x00000000 // Interrupt when low -#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge -#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge -#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges -#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal -#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted - -//***************************************************************************** -// -// Values that can be passed to ComparatorSetRef() as the ui32Ref parameter. -// -//***************************************************************************** -#define COMP_REF_OFF 0x00000000 // Turn off the internal reference -#define COMP_REF_0V 0x00000300 // Internal reference of 0V -#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V -#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V -#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V -#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V -#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V -#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V -#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V -#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V -#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V -#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V -#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V -#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V -#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V -#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V -#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V -#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V -#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V -#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V -#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V -#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V -#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V -#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V -#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V -#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V -#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V -#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V -#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, - uint32_t ui32Config); -extern void ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref); -extern bool ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp); -extern void ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp, - void (*pfnHandler)(void)); -extern void ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp); -extern void ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp); -extern void ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp); -extern bool ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp, - bool bMasked); -extern void ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_COMP_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/cpu.c b/bsp/tm4c129x-dk/libraries/driverlib/cpu.c deleted file mode 100644 index 0cddffc3405aeb707727a4df209dc4fd23cb2554..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/cpu.c +++ /dev/null @@ -1,457 +0,0 @@ -//***************************************************************************** -// -// cpu.c - Instruction wrappers for special CPU instructions needed by the -// drivers. -// -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#include -#include "driverlib/cpu.h" - -//***************************************************************************** -// -// Wrapper function for the CPSID instruction. Returns the state of PRIMASK -// on entry. -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -uint32_t __attribute__((naked)) -CPUcpsid(void) -{ - uint32_t ui32Ret; - - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " bx lr\n" - : "=r" (ui32Ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ui32Ret); -} -#endif -#if defined(ewarm) -uint32_t -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - mrs r0, PRIMASK; - cpsid i; - bx lr -} -#endif -#if defined(ccs) -uint32_t -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function returning the state of PRIMASK (indicating whether -// interrupts are enabled or disabled). -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -uint32_t __attribute__((naked)) -CPUprimask(void) -{ - uint32_t ui32Ret; - - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " bx lr\n" - : "=r" (ui32Ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ui32Ret); -} -#endif -#if defined(ewarm) -uint32_t -CPUprimask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUprimask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - mrs r0, PRIMASK; - bx lr -} -#endif -#if defined(ccs) -uint32_t -CPUprimask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK -// on entry. -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -uint32_t __attribute__((naked)) -CPUcpsie(void) -{ - uint32_t ui32Ret; - - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " bx lr\n" - : "=r" (ui32Ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ui32Ret); -} -#endif -#if defined(ewarm) -uint32_t -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - mrs r0, PRIMASK; - cpsie i; - bx lr -} -#endif -#if defined(ccs) -uint32_t -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function for the WFI instruction. -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -void __attribute__((naked)) -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" wfi\n" - " bx lr\n"); -} -#endif -#if defined(ewarm) -void -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" wfi\n"); -} -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm void -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - wfi; - bx lr -} -#endif -#if defined(ccs) -void -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" wfi\n"); -} -#endif - -//***************************************************************************** -// -// Wrapper function for writing the BASEPRI register. -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -void __attribute__((naked)) -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n" - " bx lr\n"); -} -#endif -#if defined(ewarm) -void -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n"); -} -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm void -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // - // Set the BASEPRI register - // - msr BASEPRI, r0; - bx lr -} -#endif -#if defined(ccs) -void -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n"); -} -#endif - -//***************************************************************************** -// -// Wrapper function for reading the BASEPRI register. -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -uint32_t __attribute__((naked)) -CPUbasepriGet(void) -{ - uint32_t ui32Ret; - - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n" - " bx lr\n" - : "=r" (ui32Ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ui32Ret); -} -#endif -#if defined(ewarm) -uint32_t -CPUbasepriGet(void) -{ - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUbasepriGet(void) -{ - // - // Read BASEPRI - // - mrs r0, BASEPRI; - bx lr -} -#endif -#if defined(ccs) -uint32_t -CPUbasepriGet(void) -{ - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif diff --git a/bsp/tm4c129x-dk/libraries/driverlib/cpu.h b/bsp/tm4c129x-dk/libraries/driverlib/cpu.h deleted file mode 100644 index 11a07e88d030918eb71449214275f1598a7c19db..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/cpu.h +++ /dev/null @@ -1,75 +0,0 @@ -//***************************************************************************** -// -// cpu.h - Prototypes for the CPU instruction wrapper functions. -// -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_CPU_H__ -#define __DRIVERLIB_CPU_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern uint32_t CPUcpsid(void); -extern uint32_t CPUcpsie(void); -extern uint32_t CPUprimask(void); -extern void CPUwfi(void); -extern uint32_t CPUbasepriGet(void); -extern void CPUbasepriSet(uint32_t ui32NewBasepri); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_CPU_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/crc.c b/bsp/tm4c129x-dk/libraries/driverlib/crc.c deleted file mode 100644 index 55bd4d60484cf2e24aa7a37a87165600daff6225..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/crc.c +++ /dev/null @@ -1,311 +0,0 @@ -//***************************************************************************** -// -// crc.c - Driver for the CRC module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup crc_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ccm.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "driverlib/crc.h" -#include "driverlib/debug.h" - - -//***************************************************************************** -// -//! Set the configuration of CRC functionality with the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32CRCConfig is the configuration of the CRC engine. -//! -//! This function configures the operation of the CRC engine within the EC -//! module. The configuration is specified with the \e ui32CRCConfig argument. -//! It is the logical OR of any of the following options: -//! -//! CRC Initialization Value -//! - \b CRC_CFG_INIT_SEED - Initialize with seed value -//! - \b CRC_CFG_INIT_0 - Initialize to all '0s' -//! - \b CRC_CFG_INIT_1 - Initialize to all '1s' -//! -//! Input Data Size -//! - \b CRC_CFG_SIZE_8BIT - Input data size of 8 bits -//! - \b CRC_CFG_SIZE_32BIT - Input data size of 32 bits -//! -//! Post Process Reverse/Inverse -//! - \b CRC_CFG_RESINV - Result inverse enable -//! - \b CRC_CFG_OBR - Output reverse enable -//! -//! Input Bit Reverse -//! - \b CRC_CFG_IBR - Bit reverse enable -//! -//! Endian Control -//! - \b CRC_CFG_ENDIAN_SBHW - Swap byte in half-word -//! - \b CRC_CFG_ENDIAN_SHW - Swap half-word -//! -//! Operation Type -//! - \b CRC_CFG_TYPE_P8005 - Polynomial 0x8005 -//! - \b CRC_CFG_TYPE_P1021 - Polynomial 0x1021 -//! - \b CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7 -//! - \b CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41 -//! - \b CRC_CFG_TYPE_TCPCHKSUM - TCP checksum -//! -//! \return None. -// -//***************************************************************************** -void -CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == CCM0_BASE); - ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) || - (ui32CRCConfig & CRC_CFG_INIT_0) || - (ui32CRCConfig & CRC_CFG_INIT_1) || - (ui32CRCConfig & CRC_CFG_SIZE_8BIT) || - (ui32CRCConfig & CRC_CFG_SIZE_32BIT) || - (ui32CRCConfig & CRC_CFG_RESINV) || - (ui32CRCConfig & CRC_CFG_OBR) || - (ui32CRCConfig & CRC_CFG_IBR) || - (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) || - (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) || - (ui32CRCConfig & CRC_CFG_TYPE_P8005) || - (ui32CRCConfig & CRC_CFG_TYPE_P1021) || - (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) || - (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) || - (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM)); - - // - // Write the control register with the configuration. - // - HWREG(ui32Base + CCM_O_CRCCTRL) = ui32CRCConfig; -} - -//***************************************************************************** -// -//! Write the seed value for CRC operations in the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32Seed is the seed value. -//! -//! This function writes the seed value for use with CRC operations in the -//! EC module. This value is the start value for CRC operations. If this -//! value is not written, then the residual seed from the previous operation -//! is used as the starting value. -//! -//! \note The seed must be written only if \b CRC_CFG_INIT_SEED is -//! set with the CRCConfigSet() function. -// -//***************************************************************************** -void -CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == CCM0_BASE); - - // - // Write the seed value to the seed register. - // - HWREG(ui32Base + CCM_O_CRCSEED) = ui32Seed; -} - -//***************************************************************************** -// -//! Write data into the EC module for CRC operations. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32Data is the data to be written. -//! -//! This function writes either 8 or 32 bits of data into the EC module for -//! CRC operations. The distinction between 8 and 32 bits of data is made -//! when the \b CRC_CFG_SIZE_8BIT or \b CRC_CFG_SIZE_32BIT flag -//! is set using the CRCConfigSet() function. -//! -//! When writing 8 bits of data, ensure the data is in the least significant -//! byte position. The remaining bytes should be written with zero. For -//! example, when writing 0xAB, \e ui32Data should be 0x000000AB. -//! -//! \return None -// -//***************************************************************************** -void -CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == CCM0_BASE); - - // - // Write the data - // - HWREG(ui32Base + CCM_O_CRCDIN) = ui32Data; -} - -//***************************************************************************** -// -//! Reads the result of a CRC operation in the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param bPPResult is \b true to read the post-processed result, or \b false -//! to read the unmodified result. -//! -//! This function reads either the unmodified CRC result or the post -//! processed CRC result from the EC module. The post-processing options -//! are selectable through \b CRC_CFG_RESINV and \b CRC_CFG_OBR -//! parameters in the CRCConfigSet() function. -//! -//! \return The CRC result. -// -//***************************************************************************** -uint32_t -CRCResultRead(uint32_t ui32Base, bool bPPResult) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == CCM0_BASE); - - // - // Depending on the value of bPPResult, read the appropriate register and - // return value. - // - if(bPPResult) - { - return(HWREG(ui32Base + CCM_O_CRCRSLTPP)); - } - else - { - return(HWREG(ui32Base + CCM_O_CRCSEED)); - } -} - -//***************************************************************************** -// -//! Process data to generate a CRC with the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param pui32DataIn is a pointer to an array of data that is processed. -//! \param ui32DataLength is the number of data items that are processed -//! to produce the CRC. -//! \param bPPResult is \b true to read the post-processed result, or \b false -//! to read the unmodified result. -//! -//! This function processes an array of data to produce a CRC result. -//! -//! The data in the array pointed to be \e pui32DataIn is either an array -//! of bytes or an array or words depending on the selection of the input -//! data size options \b CRC_CFG_SIZE_8BIT and -//! \b CRC_CFG_SIZE_32BIT. -//! -//! This function returns either the unmodified CRC result or the -//! post- processed CRC result from the EC module. The post-processing -//! options are selectable through \b CRC_CFG_RESINV and -//! \b CRC_CFG_OBR parameters. -//! -//! \return The CRC result. -// -//***************************************************************************** -uint32_t -CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn, - uint32_t ui32DataLength, bool bPPResult) -{ - uint8_t *pui8DataIn; - - // - // Check the arguments. - // - ASSERT(ui32Base == CCM0_BASE); - - // - // See if the CRC is operating in 8-bit or 32-bit mode. - // - if(HWREG(ui32Base + CCM_O_CRCCTRL) & CCM_CRCCTRL_SIZE) - { - // - // The CRC is operating in 8-bit mode, so create an 8-bit pointer to - // the data. - // - pui8DataIn = (uint8_t *)pui32DataIn; - - // - // Loop through the input data. - // - while(ui32DataLength--) - { - // - // Write the next data byte. - // - HWREG(ui32Base + CCM_O_CRCDIN) = *pui8DataIn++; - } - } - else - { - // - // The CRC is operating in 32-bit mode, so loop through the input data. - // - while(ui32DataLength--) - { - // - // Write the next data word. - // - HWREG(ui32Base + CCM_O_CRCDIN) = *pui32DataIn++; - } - } - - // - // Return the result. - // - return(CRCResultRead(ui32Base, bPPResult)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/crc.h b/bsp/tm4c129x-dk/libraries/driverlib/crc.h deleted file mode 100644 index 7d33e84cb627ac88c55c8e5f22938346d19200fb..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/crc.h +++ /dev/null @@ -1,101 +0,0 @@ -//***************************************************************************** -// -// crc.h - Defines and Macros for CRC module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_CRC_H__ -#define __DRIVERLIB_CRC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used in the ui32Config argument of the -// ECConfig function. -// -//***************************************************************************** -#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed -#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s' -#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s' -#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size -#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size -#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable -#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable -#define CRC_CFG_IBR 0x00000080 // Bit reverse enable -#define CRC_CFG_ENDIAN_SBHW 0x00000020 // Swap byte in half-word -#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word -#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005 -#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021 -#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7 -#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41 -#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum - -//***************************************************************************** -// -// Function prototypes. -// -//***************************************************************************** -#if 0 -extern void ECClockGatingReqest(uint32_t ui32Base, uint32_t ui32ECIP, - bool bGate); -#endif -extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig); -extern uint32_t CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn, - uint32_t ui32DataLength, bool bPPResult); -extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data); -extern uint32_t CRCResultRead(uint32_t ui32Base, bool bPPResult); -extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_CRC_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/debug.h b/bsp/tm4c129x-dk/libraries/driverlib/debug.h deleted file mode 100644 index fd2e3afba11f1edc743bfda0ef78afa4dff31a4a..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/debug.h +++ /dev/null @@ -1,70 +0,0 @@ -//***************************************************************************** -// -// debug.h - Macros for assisting debug of the driver library. -// -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_DEBUG_H__ -#define __DRIVERLIB_DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, uint32_t ui32Line); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) do \ - { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } \ - while(0) -#else -#define ASSERT(expr) -#endif - -#endif // __DRIVERLIB_DEBUG_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/des.c b/bsp/tm4c129x-dk/libraries/driverlib/des.c deleted file mode 100644 index 1b6e86a2a8473413e5625e3a782976d85b1bbc02..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/des.c +++ /dev/null @@ -1,807 +0,0 @@ -//***************************************************************************** -// -// des.c - Driver for the DES data transformation. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup des_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_des.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/des.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -//! Resets the DES Module. -//! -//! \param ui32Base is the base address of the DES module. -//! -//! This function performs a soft-reset sequence of the DES module. -//! -//! \return None. -// -//***************************************************************************** -void -DESReset(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Trigger the soft reset. - // - HWREG(ui32Base + DES_O_SYSCONFIG) |= DES_SYSCONFIG_SOFTRESET; - - // - // Wait for the reset to finish. - // - while((HWREG(ui32Base + DES_O_SYSSTATUS) & - DES_SYSSTATUS_RESETDONE) == 0) - { - } -} - -//***************************************************************************** -// -//! Configures the DES module for operation. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Config is the configuration of the DES module. -//! -//! This function configures the DES module for operation. -//! -//! The \e ui32Config parameter is a bit-wise OR of a number of configuration -//! flags. The valid flags are grouped below based on their function. -//! -//! The direction of the operation is specified with one of the following two -//! flags. Only one is permitted. -//! -//! - \b DES_CFG_DIR_ENCRYPT - Encryption -//! - \b DES_CFG_DIR_DECRYPT - Decryption -//! -//! The operational mode of the DES engine is specified with one of the -//! following flags. Only one is permitted. -//! -//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode -//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode -//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode -//! -//! The selection of single DES or triple DES is specified with one of the -//! following two flags. Only one is permitted. -//! -//! - \b DES_CFG_SINGLE - Single DES -//! - \b DES_CFG_TRIPLE - Triple DES -//! -//! \return None. -// -//***************************************************************************** -void -DESConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Backup the save context field. - // - ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT); - - // - // Write the control register. - // - HWREG(ui32Base + DES_O_CTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the key used for DES operations. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Key is a pointer to an array that holds the key -//! -//! This function sets the key used for DES operations. -//! -//! \e pui32Key should be 64 bits long (2 words) if single DES is being used or -//! 192 bits (6 words) if triple DES is being used. -//! -//! \return None. -// -//***************************************************************************** -void -DESKeySet(uint32_t ui32Base, uint32_t *pui32Key) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Write the first part of the key. - // - HWREG(ui32Base + DES_O_KEY1_L) = pui32Key[0]; - HWREG(ui32Base + DES_O_KEY1_H) = pui32Key[1]; - - // - // If we are performing tripe DES, then write the key registers for - // the second and third rounds. - // - if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE) - { - HWREG(ui32Base + DES_O_KEY2_L) = pui32Key[2]; - HWREG(ui32Base + DES_O_KEY2_H) = pui32Key[3]; - HWREG(ui32Base + DES_O_KEY3_L) = pui32Key[4]; - HWREG(ui32Base + DES_O_KEY3_H) = pui32Key[5]; - } -} - -//***************************************************************************** -// -//! Sets the initialization vector in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32IVdata is a pointer to an array of 64 bits (2 words) of data to -//! be written into the initialization vectors registers. -//! -//! This function sets the initialization vector in the DES module. It returns -//! true if the registers were successfully written. If the context registers -//! cannot be written at the time the function was called, then false is -//! returned. -//! -//! \return True or false. -// -//***************************************************************************** -bool -DESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Check to see if context registers can be overwritten. If not, return - // false. - // - if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0) - { - return(false); - } - - // - // Write the initialization vector registers. - // - HWREG(ui32Base + DES_O_IV_L) = pui32IVdata[0]; - HWREG(ui32Base + DES_O_IV_H) = pui32IVdata[1]; - - // - // Return true to indicate the write was successful. - // - return(true); -} - -//***************************************************************************** -// -//! Sets the crytographic data length in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Length is the length of the data in bytes. -//! -//! This function writes the cryptographic data length into the DES module. -//! When this register is written, the engine is triggered to start using this -//! context. -//! -//! \note Data lengths up to (2^32 - 1) bytes are allowed. -//! -//! \return None. -// -//***************************************************************************** -void -DESLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Write the length register. - // - HWREG(ui32Base + DES_O_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Dest is a pointer to an array of 2 words. -//! -//! This function returns true if the data was ready when the function was -//! called. If the data was not ready, false is returned. -//! -//! \return True or false. -// -//***************************************************************************** -bool -DESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Check to see if the data is ready to be read. - // - if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) - { - return(false); - } - - // - // Read two words of data from the data registers. - // - pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); - pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); - - // - // Return true to indicate a successful write. - // - return(true); -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers with blocking. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Dest is a pointer to an array of bytes. -//! -//! This function waits until the DES module is finished and encrypted or -//! decrypted data is ready. The output data is then stored in the pui32Dest -//! array. -//! -//! \return None -// -//***************************************************************************** -void -DESDataRead(uint32_t ui32Base, uint32_t *pui32Dest) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Wait for data output to be ready. - // - while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0) - { - } - - // - // Read two words of data from the data registers. - // - pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); - pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Src is a pointer to an array of 2 words. -//! -//! This function returns false if the DES module is not ready to accept -//! data. It returns true if the data was written successfully. -//! -//! \return true or false. -// -//***************************************************************************** -bool -DESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Check if the DES module is ready to encrypt or decrypt data. If it - // is not, return false. - // - if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL)))) - { - return(false); - } - - // - // Write the data. - // - HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; - HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; - - // - // Return true to indicate a successful write. - // - return(true); -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Src is a pointer to an array of bytes. -//! -//! This function waits until the DES module is ready before writing the -//! data contained in the pui32Src array. -//! -//! \return None. -// -//***************************************************************************** -void -DESDataWrite(uint32_t ui32Base, uint32_t *pui32Src) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Wait for the input ready bit to go high. - // - while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0) - { - } - - // - // Write the data. - // - HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; - HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; -} - -//***************************************************************************** -// -//! Processes blocks of data through the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Src is a pointer to an array of words that contains the -//! source data for processing. -//! \param pui32Dest is a pointer to an array of words consisting of the -//! processed data. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! It must be a multiple of eight. -//! -//! This function takes the data contained in the pui32Src array and processes -//! it using the DES engine. The resulting data is stored in the -//! pui32Dest array. The function blocks until all of the data has been -//! processed. If processing is successful, the function returns true. -//! -//! \note This functions assumes that the DES module has been configured, -//! and initialization values and keys have been written. -//! -//! \return true or false. -// -//***************************************************************************** -bool -DESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, uint32_t *pui32Dest, - uint32_t ui32Length) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Length % 8) == 0); - - // - // Write the length register first. This triggers the engine to start - // using this context. - // - HWREG(ui32Base + DES_O_LENGTH) = ui32Length; - - // - // Now loop until the blocks are written. - // - for(ui32Count = 0; ui32Count < (ui32Length / 4); ui32Count += 2) - { - // - // Check if the input ready is fine - // - while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) - { - } - - // - // Write the block data. - // - DESDataWriteNonBlocking(ui32Base, pui32Src + ui32Count); - - // - // Wait for the output ready - // - while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) - { - } - - // - // Read the processed data block. - // - DESDataReadNonBlocking(ui32Base, pui32Dest + ui32Count); - } - - // - // Return true to indicate the process was successful. - // - return(true); -} - -//***************************************************************************** -// -//! Returns the current interrupt status of the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function gets the current interrupt status of the DES module. -//! The value returned is a logical OR of the following values: -//! -//! - \b DES_INT_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DATA_IN - Data input interrupt -//! - \b DES_INT_DATA_OUT_INT - Data output interrupt -//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \return A bit mask of the current interrupt status. -// -//***************************************************************************** -uint32_t -DESIntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Status, ui32Enable; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Read the status register and return the value. - // - ui32Status = HWREG(ui32Base + DES_O_IRQSTATUS); - if(bMasked) - { - ui32Enable = HWREG(ui32Base + DES_O_IRQENABLE); - return((ui32Status & ui32Enable) | - (HWREG(ui32Base + DES_O_DMAMIS) << 16)); - } - else - { - return(ui32Status | (HWREG(ui32Base + DES_O_DMARIS) << 16)); - } -} - -//***************************************************************************** -// -//! Enables interrupts in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32IntFlags is a bit mask of the interrupts to be enabled. -//! -//! \e ui32IntFlags should be a logical OR of one or more of the following -//! values: -//! -//! - \b DES_INT_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DATA_IN - Data input interrupt -//! - \b DES_INT_DATA_OUT - Data output interrupt -//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \return None. -// -//***************************************************************************** -void -DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DATA_IN) || - (ui32IntFlags & DES_INT_DATA_OUT) || - (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_OUT)); - - // - // Enable the interrupts from the flags. - // - HWREG(ui32Base + DES_O_DMAIM) |= (ui32IntFlags & 0x00070000) >> 16; - HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; -} - -//***************************************************************************** -// -//! Disables interrupts in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. -//! -//! This function disables interrupt sources in the DES module. -//! \e ui32IntFlags should be a logical OR of one or more of the following -//! values: -//! -//! - \b DES_INT_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DATA_IN - Data input interrupt -//! - \b DES_INT_DATA_OUT - Data output interrupt -//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \return None. -// -//***************************************************************************** -void -DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DATA_IN) || - (ui32IntFlags & DES_INT_DATA_OUT) || - (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_OUT)); - - // - // Clear the interrupts from the flags. - // - HWREG(ui32Base + DES_O_DMAIM) &= ~((ui32IntFlags & 0x00070000) >> 16); - HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); -} - -//***************************************************************************** -// -//! Clears interrupts in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. -//! -//! This function disables interrupt sources in the DES module. -//! \e ui32IntFlags should be a logical OR of one or more of the following -//! values: -//! -//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt -//! -//! \note The DMA done interrupts are the only interrupts that can be cleared. -//! The remaining interrupts can be disabled instead using DESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_OUT)); - - HWREG(ui32Base + DES_O_DMAIC) = (ui32IntFlags & 0x00070000) >> 16; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled DES interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables DES interrupts on the interrupt controller; specific DES -//! interrupt sources must be enabled using DESIntEnable(). The interrupt -//! handler being registered must clear the source of the interrupt using -//! DESIntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() should be used to enable DES interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -DESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_DES0_TM4C129, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(INT_DES0_TM4C129); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -DESIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_DES0_TM4C129); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_DES0_TM4C129); -} - -//***************************************************************************** -// -//! Enables DMA request sources in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Flags is a bit mask of the DMA requests to be enabled. -//! -//! This function enables DMA request sources in the DES module. The -//! \e ui32Flags parameter should be the logical OR of any of the following: -//! -//! - \b DES_DMA_CONTEXT_IN - Context In -//! - \b DES_DMA_DATA_OUT - Data Out -//! - \b DES_DMA_DATA_IN - Data In -//! -//! \return None. -// -//***************************************************************************** -void -DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || - (ui32Flags & DES_DMA_DATA_OUT) || - (ui32Flags & DES_DMA_DATA_IN)); - - // - // Set the data in and data out DMA request enable bits. - // - HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags; -} - -//***************************************************************************** -// -//! Disables DMA request sources in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Flags is a bit mask of the DMA requests to be disabled. -//! -//! This function disables DMA request sources in the DES module. The -//! \e ui32Flags parameter should be the logical OR of any of the following: -//! -//! - \b DES_DMA_CONTEXT_IN - Context In -//! - \b DES_DMA_DATA_OUT - Data Out -//! - \b DES_DMA_DATA_IN - Data In -//! -//! \return None. -// -//***************************************************************************** -void -DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || - (ui32Flags & DES_DMA_DATA_OUT) || - (ui32Flags & DES_DMA_DATA_IN)); - - // - // Disable the DMA sources. - // - HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/des.h b/bsp/tm4c129x-dk/libraries/driverlib/des.h deleted file mode 100644 index 9f6c8d1853959681827a5f30bcedbc3b93e3c28a..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/des.h +++ /dev/null @@ -1,140 +0,0 @@ -//***************************************************************************** -// -// des.h - Defines and Macros for the DES module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_DES_H__ -#define __DRIVERLIB_DES_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used to specify the direction with the -// ui32Config argument in the DESConfig() function. Only one is permitted. -// -//***************************************************************************** -#define DES_CFG_DIR_DECRYPT 0x00000000 -#define DES_CFG_DIR_ENCRYPT 0x00000004 - -//***************************************************************************** -// -// The following defines are used to specify the operational with the -// ui32Config argument in the DESConfig() function. Only one is permitted. -// -//***************************************************************************** -#define DES_CFG_MODE_ECB 0x00000000 -#define DES_CFG_MODE_CBC 0x00000010 -#define DES_CFG_MODE_CFB 0x00000020 - -//***************************************************************************** -// -// The following defines are used to select between single DES and triple DES -// with the ui32Config argument in the DESConfig() function. Only one is -// permitted. -// -//***************************************************************************** -#define DES_CFG_SINGLE 0x00000000 -#define DES_CFG_TRIPLE 0x00000008 - -//***************************************************************************** -// -// The following defines are used with the DESIntEnable(), DESIntDisable() and -// DESIntStatus() functions. -// -//***************************************************************************** -#define DES_INT_CONTEXT_IN 0x00000001 -#define DES_INT_DATA_IN 0x00000002 -#define DES_INT_DATA_OUT 0x00000004 -#define DES_INT_DMA_CONTEXT_IN 0x00010000 -#define DES_INT_DMA_DATA_IN 0x00020000 -#define DES_INT_DMA_DATA_OUT 0x00040000 - -//***************************************************************************** -// -// The following defines are used with the DESEnableDMA() and DESDisableDMA() -// functions. -// -//***************************************************************************** -#define DES_DMA_CONTEXT_IN 0x00000080 -#define DES_DMA_DATA_OUT 0x00000040 -#define DES_DMA_DATA_IN 0x00000020 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void DESDataRead(uint32_t ui32Base, uint32_t *pui32Dest); -extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest); -extern bool DESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, - uint32_t *pui32Dest, uint32_t ui32Length); -extern void DESDataWrite(uint32_t ui32Base, uint32_t *pui32Src); -extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src); -extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); -extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); -extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked); -extern void DESIntUnregister(uint32_t ui32Base); -extern bool DESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata); -extern void DESKeySet(uint32_t ui32Base, uint32_t *pui32Key); -extern void DESLengthSet(uint32_t ui32Base, uint32_t ui32Length); -extern void DESReset(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_DES_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/eeprom.c b/bsp/tm4c129x-dk/libraries/driverlib/eeprom.c deleted file mode 100644 index 6daae87be0b81ddb569d6bc3e69e6e05621eca57..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/eeprom.c +++ /dev/null @@ -1,1156 +0,0 @@ -//***************************************************************************** -// -// eeprom.c - Driver for programming the on-chip EEPROM. -// -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#include -#include -#include "inc/hw_eeprom.h" -#include "inc/hw_flash.h" -#include "inc/hw_ints.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/flash.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" -#include "driverlib/eeprom.h" - -//***************************************************************************** -// -//! \addtogroup eeprom_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// Useful macros to extract the number of EEPROM blocks available on the target -// device and the total EEPROM storage in bytes from the EESIZE register. -// -//***************************************************************************** -#define BLOCKS_FROM_EESIZE(x) (((x) & EEPROM_EESIZE_BLKCNT_M) >> \ - EEPROM_EESIZE_BLKCNT_S) -#define SIZE_FROM_EESIZE(x) ((((x) & EEPROM_EESIZE_WORDCNT_M) >> \ - EEPROM_EESIZE_WORDCNT_S) * 4) - -//***************************************************************************** -// -// Useful macro to extract the offset from a linear address. -// -//***************************************************************************** -#define OFFSET_FROM_ADDR(x) (((x) >> 2) & 0x0F) - -//***************************************************************************** -// -// The key value required to initiate a mass erase. -// -//***************************************************************************** -#define EEPROM_MASS_ERASE_KEY ((uint32_t)0xE37B << EEPROM_EEDBGME_KEY_S) - -//***************************************************************************** -// -// This function implements a workaround for a bug in Blizzard rev A silicon. -// It ensures that only the 1KB flash sector containing a given EEPROM address -// is erased if an erase/copy operation is required as a result of a following -// EEPROM write. -// -//***************************************************************************** -static void -_EEPROMSectorMaskSet(uint32_t ui32Address) -{ - uint32_t ui32Mask; - - // - // Determine which page contains the passed EEPROM address. The 2KB EEPROM - // is implemented in 16KB of flash with each 1KB sector of flash holding - // values for 32 consecutive EEPROM words (or 128 bytes). - // - ui32Mask = ~(1 << (ui32Address >> 7)); - - SysCtlDelay(10); - HWREG(0x400FD0FC) = 3; - SysCtlDelay(10); - HWREG(0x400AE2C0) = ui32Mask; - SysCtlDelay(10); - HWREG(0x400FD0FC) = 0; - SysCtlDelay(10); -} - -//***************************************************************************** -// -// Clear the FSM sector erase mask to ensure that any following main array -// flash erase operations operate as expected. -// -//***************************************************************************** -static void -_EEPROMSectorMaskClear(void) -{ - SysCtlDelay(10); - HWREG(0x400FD0FC) = 3; - SysCtlDelay(10); - HWREG(0x400AE2C0) = 0; - SysCtlDelay(10); - HWREG(0x400FD0FC) = 0; - SysCtlDelay(10); -} - -//***************************************************************************** -// -// Block until the EEPROM peripheral is not busy. -// -//***************************************************************************** -static void -_EEPROMWaitForDone(void) -{ - // - // Is the EEPROM still busy? - // - while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) - { - // - // Spin while EEPROM is busy. - // - } -} - -//***************************************************************************** -// -//! Performs any necessary recovery in case of power failures during write. -//! -//! This function \b must be called after SysCtlPeripheralEnable() and before -//! the EEPROM is accessed. It is used to check for errors in the EEPROM state -//! such as from power failure during a previous write operation. The function -//! detects these errors and performs as much recovery as possible. -//! -//! If \b EEPROM_INIT_ERROR is returned, the EEPROM was unable to recover its -//! state. If power is stable when this occurs, this indicates a fatal -//! error and is likely an indication that the EEPROM memory has exceeded its -//! specified lifetime write/erase specification. If the supply voltage is -//! unstable when this return code is observed, retrying the operation once the -//! voltage is stabilized may clear the error. -//! -//! Failure to call this function after a reset may lead to incorrect operation -//! or permanent data loss if the EEPROM is later written. -//! -//! \return Returns \b EEPROM_INIT_OK if no errors were detected or \b -//! EEPROM_INIT_ERROR if the EEPROM peripheral cannot currently recover from -//! an interrupted write or erase operation. -// -//***************************************************************************** -uint32_t -EEPROMInit(void) -{ - uint32_t ui32Status; - - // - // Insert a small delay (6 cycles + call overhead) to guard against the - // possibility that this function is called immediately after the EEPROM - // peripheral is enabled. Without this delay, there is a slight chance - // that the first EEPROM register read will fault if you are using a - // compiler with a ridiculously good optimizer! - // - SysCtlDelay(2); - - // - // Make sure the EEPROM has finished any ongoing processing. - // - _EEPROMWaitForDone(); - - // - // Read the EESUPP register to see if any errors have been reported. - // - ui32Status = HWREG(EEPROM_EESUPP); - - // - // Did an error of some sort occur during initialization? - // - if(ui32Status & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY)) - { - return(EEPROM_INIT_ERROR); - } - - // - // Perform a second EEPROM reset. - // - SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0); - - // - // Wait for the EEPROM to complete its reset processing once again. - // - SysCtlDelay(2); - _EEPROMWaitForDone(); - - // - // Read EESUPP once again to determine if any error occurred. - // - ui32Status = HWREG(EEPROM_EESUPP); - - // - // Was an error reported following the second reset? - // - if(ui32Status & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY)) - { - return(EEPROM_INIT_ERROR); - } - - // - // The EEPROM does not indicate that any error occurred. - // - return(EEPROM_INIT_OK); -} - - -//***************************************************************************** -// -//! Determines the size of the EEPROM. -//! -//! This function returns the size of the EEPROM in bytes. -//! -//! \return Returns the total number of bytes in the EEPROM. -// -//***************************************************************************** -uint32_t -EEPROMSizeGet(void) -{ - // - // Return the size of the EEPROM in bytes. - // - return(SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); -} - -//***************************************************************************** -// -//! Determines the number of blocks in the EEPROM. -//! -//! This function may be called to determine the number of blocks in the -//! EEPROM. Each block is the same size and the number of bytes of storage -//! contained in a block may be determined by dividing the size of the device, -//! obtained via a call to the EEPROMSizeGet() function, by the number of -//! blocks returned by this function. -//! -//! \return Returns the total number of blocks in the device EEPROM. -// -//***************************************************************************** -uint32_t -EEPROMBlockCountGet(void) -{ - // - // Extract the number of blocks and return it to the caller. - // -#ifdef EEPROM_SIZE_LIMIT - // - // If a size limit has been specified, fake the number of blocks to match. - // - return(EEPROM_SIZE_LIMIT / 48); -#else - // - // Return the actual number of blocks supported by the hardware. - // - return(BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); -#endif -} - -//***************************************************************************** -// -//! Reads data from the EEPROM. -//! -//! \param pui32Data is a pointer to storage for the data read from the EEPROM. -//! This pointer must point to at least \e ui32Count bytes of available memory. -//! \param ui32Address is the byte address within the EEPROM from which data is -//! to be read. This value must be a multiple of 4. -//! \param ui32Count is the number of bytes of data to read from the EEPROM. -//! This value must be a multiple of 4. -//! -//! This function may be called to read a number of words of data from a -//! word-aligned address within the EEPROM. Data read is copied into the -//! buffer pointed to by the \e pui32Data parameter. -//! -//! \return None. -// -//***************************************************************************** -void -EEPROMRead(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count) -{ - // - // Check parameters in a debug build. - // - ASSERT(pui32Data); - ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT((ui32Address + ui32Count) <= - SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT((ui32Address & 3) == 0); - ASSERT((ui32Count & 3) == 0); - - // - // Set the block and offset appropriately to read the first word. - // - HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address); - HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address); - - // - // Convert the byte count to a word count. - // - ui32Count /= 4; - - // - // Read each word in turn. - // - while(ui32Count) - { - // - // Read the next word through the autoincrementing register. - // - *pui32Data = HWREG(EEPROM_EERDWRINC); - - // - // Move on to the next word. - // - pui32Data++; - ui32Count--; - - // - // Do we need to move to the next block? This is the case if the - // offset register has just wrapped back to 0. Note that we only - // write the block register if we have more data to read. If this - // register is written, the hardware expects a read or write operation - // next. If a mass erase is requested instead, the mass erase will - // fail. - // - if(ui32Count && (HWREG(EEPROM_EEOFFSET) == 0)) - { - HWREG(EEPROM_EEBLOCK) += 1; - } - } -} - -//***************************************************************************** -// -//! Writes data to the EEPROM. -//! -//! \param pui32Data points to the first word of data to write to the EEPROM. -//! \param ui32Address defines the byte address within the EEPROM that the data -//! is to be written to. This value must be a multiple of 4. -//! \param ui32Count defines the number of bytes of data that is to be written. -//! This value must be a multiple of 4. -//! -//! This function may be called to write data into the EEPROM at a given -//! word-aligned address. The call is synchronous and returns only after -//! all data has been written or an error occurs. -//! -//! \return Returns 0 on success or non-zero values on failure. Failure codes -//! are logical OR combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, -//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING. -// -//***************************************************************************** -uint32_t -EEPROMProgram(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count) -{ - uint32_t ui32Status; - - // - // Check parameters in a debug build. - // - ASSERT(pui32Data); - ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT((ui32Address + ui32Count) <= - SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT((ui32Address & 3) == 0); - ASSERT((ui32Count & 3) == 0); - - // - // Make sure the EEPROM is idle before we start. - // - do - { - // - // Read the status. - // - ui32Status = HWREG(EEPROM_EEDONE); - } - while(ui32Status & EEPROM_EEDONE_WORKING); - - // - // Set the block and offset appropriately to program the first word. - // - HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address); - HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address); - - // - // Convert the byte count to a word count. - // - ui32Count /= 4; - - // - // Write each word in turn. - // - while(ui32Count) - { - // - // This is a workaround for a silicon problem on Blizzard rev A. We - // need to do this before every word write to ensure that we don't - // have problems in multi-word writes that span multiple flash sectors. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskSet(ui32Address); - } - - // - // Write the next word through the autoincrementing register. - // - HWREG(EEPROM_EERDWRINC) = *pui32Data; - - // - // Wait a few cycles. In some cases, the WRBUSY bit is not set - // immediately and this prevents us from dropping through the polling - // loop before the bit is set. - // - SysCtlDelay(10); - - // - // Wait for the write to complete. - // - do - { - // - // Read the status. - // - ui32Status = HWREG(EEPROM_EEDONE); - } - while(ui32Status & EEPROM_EEDONE_WORKING); - - // - // Make sure we completed the write without errors. Note that we - // must check this per-word because write permission can be set per - // block resulting in only a section of the write not being performed. - // - if(ui32Status & EEPROM_EEDONE_NOPERM) - { - // - // An error was reported that would prevent the values from - // being written correctly. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskClear(); - } - return(ui32Status); - } - - // - // Move on to the next word. - // - pui32Data++; - ui32Count--; - - // - // Do we need to move to the next block? This is the case if the - // offset register has just wrapped back to 0. Note that we only - // write the block register if we have more data to read. If this - // register is written, the hardware expects a read or write operation - // next. If a mass erase is requested instead, the mass erase will - // fail. - // - if(ui32Count && (HWREG(EEPROM_EEOFFSET) == 0)) - { - HWREG(EEPROM_EEBLOCK) += 1; - } - } - - // - // Clear the sector protection bits to prevent possible problems when - // programming the main flash array later. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskClear(); - } - - // - // Return the current status to the caller. - // - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -//! Writes a word to the EEPROM. -//! -//! \param ui32Data is the word to write to the EEPROM. -//! \param ui32Address defines the byte address within the EEPROM to which the -//! data is to be written. This value must be a multiple of 4. -//! -//! This function is intended to allow EEPROM programming under interrupt -//! control. It may be called to start the process of writing a single word of -//! data into the EEPROM at a given word-aligned address. The call is -//! asynchronous and returns immediately without waiting for the write to -//! complete. Completion of the operation is signaled by means of an -//! interrupt from the EEPROM module. The EEPROM peripheral shares a single -//! interrupt vector with the flash memory subsystem, \b INT_FLASH. -//! -//! \return Returns status and error information in the form of a logical OR -//! combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, -//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE and \b EEPROM_RC_WORKING. Flags -//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING are -//! expected in normal operation and do not indicate an error. -// -//***************************************************************************** -uint32_t -EEPROMProgramNonBlocking(uint32_t ui32Data, uint32_t ui32Address) -{ - // - // Check parameters in a debug build. - // - ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT((ui32Address & 3) == 0); - - // - // This is a workaround for a silicon problem on Blizzard rev A. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskSet(ui32Address); - } - - // - // Set the block and offset appropriately to program the desired word. - // - HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address); - HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address); - - // - // Write the new word using the auto-incrementing register just in case - // the caller wants to write follow-on words using direct register access - // - HWREG(EEPROM_EERDWRINC) = ui32Data; - - // - // Return the current status to the caller. - // - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -//! Erases the EEPROM and returns it to the factory default condition. -//! -//! This function completely erases the EEPROM and removes any and -//! all access protection on its blocks, leaving the device in the factory -//! default condition. After this operation, all EEPROM words contain the -//! value 0xFFFFFFFF and all blocks are accessible for both read and write -//! operations in all CPU modes. No passwords are active. -//! -//! The function is synchronous and does not return until the erase operation -//! has completed. -//! -//! \return Returns 0 on success or non-zero values on failure. Failure codes -//! are logical OR combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, -//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING. -// -//***************************************************************************** -uint32_t -EEPROMMassErase(void) -{ - // - // This is a workaround for a silicon problem on Blizzard rev A. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskClear(); - } - - // - // Start the mass erase processing - // - HWREG(EEPROM_EEDBGME) = EEPROM_MASS_ERASE_KEY | EEPROM_EEDBGME_ME; - - // - // Wait for completion. - // - _EEPROMWaitForDone(); - - // - // Reset the peripheral. This is required so that all protection - // mechanisms and passwords are reset now that the EEPROM data has been - // scrubbed. - // - SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0); - - // - // Wait for completion again. - // - SysCtlDelay(2); - _EEPROMWaitForDone(); - - // - // Pass any error codes back to the caller. - // - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -//! Returns the current protection level for an EEPROM block. -//! -//! \param ui32Block is the block number for which the protection level is to -//! be queried. -//! -//! This function returns the current protection settings for a given -//! EEPROM block. If block 0 is currently locked, it must be unlocked prior -//! to calling this function to query the protection setting for other blocks. -//! -//! \return Returns one of \b EEPROM_PROT_RW_LRO_URW, \b EEPROM_PROT_NA_LNA_URW -//! or \b EEPROM_PROT_RO_LNA_URO optionally OR-ed with -//! \b EEPROM_PROT_SUPERVISOR_ONLY. -// -//***************************************************************************** -uint32_t -EEPROMBlockProtectGet(uint32_t ui32Block) -{ - // - // Parameter validity check. - // - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - - // - // Set the current block. - // - HWREG(EEPROM_EEBLOCK) = ui32Block; - - // - // Return the protection flags for this block. - // - return(HWREG(EEPROM_EEPROT)); -} - -//***************************************************************************** -// -//! Set the current protection options for an EEPROM block. -//! -//! \param ui32Block is the block number for which the protection options are -//! to be set. -//! \param ui32Protect consists of one of the values \b EEPROM_PROT_RW_LRO_URW, -//! \b EEPROM_PROT_NA_LNA_URW or \b EEPROM_PROT_RO_LNA_URO optionally ORed with -//! \b EEPROM_PROT_SUPERVISOR_ONLY. -//! -//! This function sets the protection settings for a given EEPROM block -//! assuming no protection settings have previously been written. Note that -//! protection settings applied to block 0 have special meaning and control -//! access to the EEPROM peripheral as a whole. Protection settings applied to -//! blocks numbered 1 and above are layered above any protection set on block 0 -//! such that the effective protection on each block is the logical OR of the -//! protection flags set for block 0 and for the target block. This protocol -//! allows global protection options to be set for the whole device via block -//! 0 and more restrictive protection settings to be set on a block-by-block -//! basis. -//! -//! The protection flags indicate access permissions as follow: -//! -//! \b EEPROM_PROT_SUPERVISOR_ONLY restricts access to the block to threads -//! running in supervisor mode. If clear, both user and supervisor threads -//! can access the block. -//! -//! \b EEPROM_PROT_RW_LRO_URW provides read/write access to the block if no -//! password is set or if a password is set and the block is unlocked. If the -//! block is locked, only read access is permitted. -//! -//! \b EEPROM_PROT_NA_LNA_URW provides neither read nor write access unless -//! a password is set and the block is unlocked. If the block is unlocked, -//! both read and write access are permitted. -//! -//! \b EEPROM_PROT_RO_LNA_URO provides read access to the block if no password -//! is set or if a password is set and the block is unlocked. If the block is -//! password protected and locked, neither read nor write access is permitted. -//! -//! \return Returns a logical OR combination of \b EEPROM_RC_WRBUSY, \b -//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b -//! EEPROM_RC_WORKING to indicate status and error conditions. -// -//***************************************************************************** -uint32_t -EEPROMBlockProtectSet(uint32_t ui32Block, uint32_t ui32Protect) -{ - // - // Parameter validity check. - // - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - - // - // Set the current block. - // - HWREG(EEPROM_EEBLOCK) = ui32Block; - - // - // Set the protection options for this block. - // - HWREG(EEPROM_EEPROT) = ui32Protect; - - // - // Wait for the write to complete. - // - while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) - { - // - // Still working. - // - } - - // - // Pass any error codes back to the caller. - // - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -//! Sets the password used to protect an EEPROM block. -//! -//! \param ui32Block is the EEPROM block number for which the password is to be -//! set. -//! \param pui32Password points to an array of uint32_t values comprising -//! the password to set. Each element may be any 32-bit value other than -//! 0xFFFFFFFF. This array must contain the number of elements given by the -//! \e ui32Count parameter. -//! \param ui32Count provides the number of uint32_ts in the \e ui32Password. -//! Valid values are 1, 2 and 3. -//! -//! This function allows the password used to unlock an EEPROM block to be -//! set. Valid passwords may be either 32, 64 or 96 bits comprising words -//! with any value other than 0xFFFFFFFF. The password may only be set once. -//! Any further attempts to set the password result in an error. Once the -//! password is set, the block remains unlocked until EEPROMBlockLock() is -//! called for that block or block 0, or a reset occurs. -//! -//! If a password is set on block 0, this affects locking of the peripheral as -//! a whole. When block 0 is locked, all other EEPROM blocks are inaccessible -//! until block 0 is unlocked. Once block 0 is unlocked, other blocks -//! become accessible according to any passwords set on those blocks and the -//! protection set for that block via a call to EEPROMBlockProtectSet(). -//! -//! \return Returns a logical OR combination of \b EEPROM_RC_WRBUSY, \b -//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b -//! EEPROM_RC_WORKING to indicate status and error conditions. -// -//***************************************************************************** -uint32_t -EEPROMBlockPasswordSet(uint32_t ui32Block, uint32_t *pui32Password, - uint32_t ui32Count) -{ - uint32_t ui32Reg; - - // - // Check parameters in a debug build. - // - ASSERT(pui32Password); - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT(ui32Count <= 3); - - // - // Set the block number whose password we are about to write. - // - HWREG(EEPROM_EEBLOCK) = ui32Block; - - // - // Start with the first password word. - // - ui32Reg = EEPROM_EEPASS0; - - // - // Write the password. - // - while(ui32Count) - { - // - // Start the process of writing the password. - // - HWREG(ui32Reg) = *pui32Password; - - // - // Update values in preparation for writing the next word. - // - pui32Password++; - ui32Reg += 4; - ui32Count--; - - // - // Wait for the last word write to complete or an error to be reported. - // - while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) - { - // - // Still working. - // - } - } - - // - // Return the final write status. - // - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -//! Locks a password-protected EEPROM block. -//! -//! \param ui32Block is the EEPROM block number which is to be locked. -//! -//! This function locks an EEPROM block that has previously been protected by -//! writing a password. Access to the block once it is locked is determined -//! by the protection settings applied via a previous call to the -//! EEPROMBlockProtectSet() function. If no password has previously been set -//! for the block, this function has no effect. -//! -//! Locking block 0 has the effect of making all other blocks in the EEPROM -//! inaccessible. -//! -//! \return Returns the lock state for the block on exit, 1 if unlocked (as -//! would be the case if no password was set) or 0 if locked. -//! -//***************************************************************************** -uint32_t -EEPROMBlockLock(uint32_t ui32Block) -{ - // - // Check parameters in a debug build. - // - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - - // - // Select the block we are going to lock. - // - HWREG(EEPROM_EEBLOCK) = ui32Block; - - // - // Lock the block. - // - HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF; - - // - // Return the current lock state. - // - return(HWREG(EEPROM_EEUNLOCK)); -} - -//***************************************************************************** -// -//! Unlocks a password-protected EEPROM block. -//! -//! \param ui32Block is the EEPROM block number which is to be unlocked. -//! \param pui32Password points to an array of uint32_t values containing -//! the password for the block. Each element must match the password -//! originally set via a call to EEPROMBlockPasswordSet(). -//! \param ui32Count provides the number of elements in the \e pui32Password -//! array and must match the value originally passed to -//! EEPROMBlockPasswordSet(). Valid values are 1, 2 and 3. -//! -//! This function unlocks an EEPROM block that has previously been protected by -//! writing a password. Access to the block once it is unlocked is determined -//! by the protection settings applied via a previous call to the -//! EEPROMBlockProtectSet() function. -//! -//! To successfully unlock an EEPROM block, the password provided must match -//! the password provided on the original call to EEPROMBlockPasswordSet(). If -//! an incorrect password is provided, the block remains locked. -//! -//! Unlocking block 0 has the effect of making all other blocks in the device -//! accessible according to their own access protection settings. When block -//! 0 is locked, all other EEPROM blocks are inaccessible. -//! -//! \return Returns the lock state for the block on exit, 1 if unlocked or 0 if -//! locked. -//! -//***************************************************************************** -uint32_t -EEPROMBlockUnlock(uint32_t ui32Block, uint32_t *pui32Password, - uint32_t ui32Count) -{ - // - // Check parameters in a debug build. - // - ASSERT(pui32Password); - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT(ui32Count <= 3); - - // - // Set the block that we are trying to unlock. - // - HWREG(EEPROM_EEBLOCK) = ui32Block; - - // - // Write the unlock register with 0xFFFFFFFF to reset the unlock - // sequence just in case a short password was previously used to try to - // unlock the block. - // - HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF; - - // - // We need to write the password words in the opposite order when unlocking - // compared to locking so start at the end of the array. - // - pui32Password += (ui32Count - 1); - - // - // Write the supplied password to unlock the block. - // - while(ui32Count) - { - HWREG(EEPROM_EEUNLOCK) = *pui32Password--; - ui32Count--; - } - - // - // Let the caller know if their password worked. - // - return(HWREG(EEPROM_EEUNLOCK)); -} - -//***************************************************************************** -// -//! Hides an EEPROM block until the next reset. -//! -//! \param ui32Block is the EEPROM block number which is to be hidden. -//! -//! This function hides an EEPROM block other than block 0. Once hidden, a -//! block is completely inaccessible until the next reset. This mechanism -//! allows initialization code to have access to data which is to be hidden -//! from the rest of the application. Unlike applications using passwords, an -//! application making using of block hiding need not contain any embedded -//! passwords which could be found through disassembly. -//! -//! \return None. -//! -//***************************************************************************** -void -EEPROMBlockHide(uint32_t ui32Block) -{ - // - // Check parameters in a debug build. - // - ASSERT(!ui32Block); - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - - // - // Hide the requested block. - // - HWREG(EEPROM_EEHIDE) = (1 << ui32Block); -} - -//***************************************************************************** -// -//! Enables the EEPROM interrupt. -//! -//! \param ui32IntFlags indicates which EEPROM interrupt source to enable. -//! This must be \b EEPROM_INT_PROGRAM currently. -//! -//! This function enables the EEPROM interrupt. When enabled, an interrupt -//! is generated when any EEPROM write or erase operation completes. The -//! EEPROM peripheral shares a single interrupt vector with the flash memory -//! subsystem, \b INT_FLASH. This function is provided as a convenience but -//! the EEPROM interrupt can also be enabled using a call to FlashIntEnable() -//! passing FLASH_INT_EEPROM in the \e ui32IntFlags parameter. -//! -//! \return None. -//! -//***************************************************************************** -void -EEPROMIntEnable(uint32_t ui32IntFlags) -{ - // - // Look for valid interrupt sources. - // - ASSERT(ui32IntFlags == EEPROM_INT_PROGRAM); - - // - // Enable interrupts from the EEPROM module. - // - HWREG(EEPROM_EEINT) |= EEPROM_EEINT_INT; - - // - // Enable the EEPROM interrupt in the flash controller module. - // - HWREG(FLASH_FCIM) |= FLASH_FCRIS_ERIS; -} - -//***************************************************************************** -// -//! Disables the EEPROM interrupt. -//! -//! \param ui32IntFlags indicates which EEPROM interrupt source to disable. -//! This must be \b EEPROM_INT_PROGRAM currently. -//! -//! This function disables the EEPROM interrupt and prevents calls to the -//! interrupt vector when any EEPROM write or erase operation completes. The -//! EEPROM peripheral shares a single interrupt vector with the flash memory -//! subsystem, \b INT_FLASH. This function is provided as a convenience but -//! the EEPROM interrupt can also be disabled using a call to FlashIntDisable() -//! passing FLASH_INT_EEPROM in the \e ui32IntFlags parameter. -//! -//! \return None. -//! -//***************************************************************************** -void -EEPROMIntDisable(uint32_t ui32IntFlags) -{ - // - // Look for valid interrupt sources. - // - ASSERT(ui32IntFlags == EEPROM_INT_PROGRAM); - - // - // Disable the EEPROM interrupt in the flash controller module. - // - HWREG(FLASH_FCIM) &= ~FLASH_FCIM_EMASK; - - // - // Disable interrupts from the EEPROM module. - // - HWREG(EEPROM_EEINT) &= ~EEPROM_EEINT_INT; -} - -//***************************************************************************** -// -//! Reports the state of the EEPROM interrupt. -//! -//! \param bMasked determines whether the masked or unmasked state of the -//! interrupt is to be returned. If bMasked is \b true, the masked state is -//! returned, otherwise the unmasked state is returned. -//! -//! This function allows an application to query the state of the EEPROM -//! interrupt. If active, the interrupt may be cleared by calling -//! EEPROMIntClear(). -//! -//! \return Returns \b EEPROM_INT_PROGRAM if an interrupt is being signaled or -//! 0 otherwise. -// -//***************************************************************************** -uint32_t -EEPROMIntStatus(bool bMasked) -{ - if(bMasked) - { - // - // If asked for the masked interrupt status, we check to see if the - // relevant interrupt is pending in the flash controller then return - // the appropriate EEPROM flag if it is. - // - return((HWREG(FLASH_FCMISC) & FLASH_FCMISC_EMISC) ? - EEPROM_INT_PROGRAM : 0); - } - else - { - // - // If asked for the unmasked interrupt status, infer that an interrupt - // is pending if the WORKING bit of the EEDONE register is clear. The - // actual interrupt fires on the high to low transition of this bit - // but we don't have access to an unmasked interrupt status for the - // EEPROM because it's handled via the flash controller so we have to - // make do with this instead. - // - return((HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) ? - 0 : EEPROM_INT_PROGRAM); - } -} - -//***************************************************************************** -// -//! Clears the EEPROM interrupt. -//! -//! \param ui32IntFlags indicates which interrupt sources to clear. Currently, -//! the only valid value is \b EEPROM_INT_PROGRAM. -//! -//! This function allows an application to clear the EEPROM interrupt. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -//! -//***************************************************************************** -void -EEPROMIntClear(uint32_t ui32IntFlags) -{ - // - // Clear the flash interrupt. - // - HWREG(FLASH_FCMISC) = FLASH_FCMISC_EMISC; - - // - // Clear the sector protection bits to prevent possible problems when - // programming the main flash array later. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskClear(); - } -} - -//***************************************************************************** -// -//! Returns status on the last EEPROM program or erase operation. -//! -//! This function returns the current status of the last program or erase -//! operation performed by the EEPROM. It is intended to provide error -//! information to applications programming or setting EEPROM protection -//! options under interrupt control. -//! -//! \return Returns 0 if the last program or erase operation completed without -//! any errors. If an operation is ongoing or an error occurred, the return -//! value is a logical OR combination of \b EEPROM_RC_WRBUSY, \b -//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b -//! EEPROM_RC_WORKING. -//! -//***************************************************************************** -uint32_t -EEPROMStatusGet(void) -{ - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/eeprom.h b/bsp/tm4c129x-dk/libraries/driverlib/eeprom.h deleted file mode 100644 index 0336010e0694e2258c7ee6a63bdfa1173b1418fd..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/eeprom.h +++ /dev/null @@ -1,284 +0,0 @@ -//***************************************************************************** -// -// eeprom.h - Prototypes for the EEPROM driver. -// -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_EEPROM_H__ -#define __DRIVERLIB_EEPROM_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup eeprom_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// Values returned by EEPROMInit. -// -//***************************************************************************** - -// -//! This value may be returned from a call to EEPROMInit(). It indicates that -//! no previous write operations were interrupted by a reset event and that the -//! EEPROM peripheral is ready for use. -// -#define EEPROM_INIT_OK 0 - -// -//! This value may be returned from a call to EEPROMInit(). It indicates that -//! a previous data or protection write operation was interrupted by a reset -//! event and that the EEPROM peripheral was unable to clean up after the -//! problem. This situation may be resolved with another reset or may be fatal -//! depending upon the cause of the problem. For example, if the voltage to -//! the part is unstable, retrying once the voltage has stabilized may clear -//! the error. -// -#define EEPROM_INIT_ERROR 2 - -//***************************************************************************** -// -// Error indicators returned by various EEPROM API calls. These will be ORed -// together into the final return code. -// -//***************************************************************************** - -// -//! This return code bit indicates that an attempt was made to read from -//! the EEPROM while a write operation was in progress. -// -#define EEPROM_RC_WRBUSY 0x00000020 - -// -//! This return code bit indicates that an attempt was made to write a -//! value but the destination permissions disallow write operations. This -//! may be due to the destination block being locked, access protection set -//! to prohibit writes or an attempt to write a password when one is already -//! written. -// -#define EEPROM_RC_NOPERM 0x00000010 - -// -//! This return code bit indicates that the EEPROM programming state machine -//! is currently copying to or from the internal copy buffer to make room for -//! a newly written value. It is provided as a status indicator and does not -//! indicate an error. -// -#define EEPROM_RC_WKCOPY 0x00000008 - -// -//! This return code bit indicates that the EEPROM programming state machine -//! is currently erasing the internal copy buffer. It is provided as a -//! status indicator and does not indicate an error. -// -#define EEPROM_RC_WKERASE 0x00000004 - -// -//! This return code bit indicates that the EEPROM programming state machine -//! is currently working. No new write operations should be attempted until -//! this bit is clear. -// -#define EEPROM_RC_WORKING 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to EEPROMBlockProtectSet() in the ui32Protect -// parameter, and returned by EEPROMBlockProtectGet(). -// -//***************************************************************************** - -// -//! This bit may be ORed with the protection option passed to -//! EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet(). It -//! restricts EEPROM access to threads running in supervisor mode and prevents -//! access to an EEPROM block when the CPU is in user mode. -// -#define EEPROM_PROT_SUPERVISOR_ONLY 0x00000008 - -// -//! This value may be passed to EEPROMBlockProtectSet() or returned from -//! EEPROMBlockProtectGet(). It indicates that the block should offer -//! read/write access when no password is set or when a password is set and -//! the block is unlocked, and read-only access when a password is set but -//! the block is locked. -// -#define EEPROM_PROT_RW_LRO_URW 0x00000000 - -// -//! This value may be passed to EEPROMBlockProtectSet() or returned from -//! EEPROMBlockProtectGet(). It indicates that the block should offer neither -//! read nor write access unless it is protected by a password and unlocked. -// -#define EEPROM_PROT_NA_LNA_URW 0x00000001 - -// -//! This value may be passed to EEPROMBlockProtectSet() or returned from -//! EEPROMBlockProtectGet(). It indicates that the block should offer -//! read-only access when no password is set or when a password is set and the -//! block is unlocked. When a password is set and the block is locked, neither -//! read nor write access is permitted. -// -#define EEPROM_PROT_RO_LNA_URO 0x00000002 - -//***************************************************************************** -// -//! This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is -//! returned by EEPROMIntStatus() if an EEPROM interrupt is currently being -//! signaled. -// -//***************************************************************************** -#define EEPROM_INT_PROGRAM 0x00000004 - -//***************************************************************************** -// -//! Returns the EEPROM block number containing a given offset address. -//! -//! \param ui32Addr is the linear, byte address of the EEPROM location whose -//! block number is to be returned. This is a zero-based offset from the start -//! of the EEPROM storage. -//! -//! This macro may be used to translate an EEPROM address offset into a -//! block number suitable for use in any of the driver's block protection -//! functions. The address provided is expressed as a byte offset from the -//! base of the EEPROM. -//! -//! \return Returns the zero-based block number which contains the passed -//! address. -// -//***************************************************************************** -#define EEPROMBlockFromAddr(ui32Addr) ((ui32Addr) >> 6) - -//***************************************************************************** -// -//! Returns the offset address of the first word in an EEPROM block. -//! -//! \param ui32Block is the index of the EEPROM block whose first word address -//! is to be returned. -//! -//! This macro may be used to determine the address of the first word in a -//! given EEPROM block. The address returned is expressed as a byte offset -//! from the base of EEPROM storage. -//! -//! \return Returns the address of the first word in the given EEPROM block. -// -//***************************************************************************** -#define EEPROMAddrFromBlock(ui32Block) ((ui32Block) << 6) - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern uint32_t EEPROMInit(void); -extern uint32_t EEPROMSizeGet(void); -extern uint32_t EEPROMBlockCountGet(void); -extern void EEPROMRead(uint32_t *pui32Data, uint32_t ui32Address, - uint32_t ui32Count); -extern uint32_t EEPROMProgram(uint32_t *pui32Data, - uint32_t ui32Address, - uint32_t ui32Count); -extern uint32_t EEPROMProgramNonBlocking(uint32_t ui32Data, - uint32_t ui32Address); -extern uint32_t EEPROMStatusGet(void); -extern uint32_t EEPROMMassErase(void); -extern uint32_t EEPROMBlockProtectGet(uint32_t ui32Block); -extern uint32_t EEPROMBlockProtectSet(uint32_t ui32Block, - uint32_t ui32Protect); -extern uint32_t EEPROMBlockPasswordSet(uint32_t ui32Block, - uint32_t *pui32Password, - uint32_t ui32Count); -extern uint32_t EEPROMBlockLock(uint32_t ui32Block); -extern uint32_t EEPROMBlockUnlock(uint32_t ui32Block, - uint32_t *pui32Password, - uint32_t ui32Count); -extern void EEPROMBlockHide(uint32_t ui32Block); -extern void EEPROMIntEnable(uint32_t ui32IntFlags); -extern void EEPROMIntDisable(uint32_t ui32IntFlags); -extern uint32_t EEPROMIntStatus(bool bMasked); -extern void EEPROMIntClear(uint32_t ui32IntFlags); - -#ifndef DEPRECATED -//***************************************************************************** -// -// The following definitions appeared in previous revisions of this file -// but have been deprecated and should not be used by applications. -// -//***************************************************************************** - -// -// This value used to be one of those which could be returned from a call to -// EEPROMInit(). It transpires that it is was incorrect and has been removed -// after EEPROMInit() was reworked for TivaWare 2.1. -// -#define EEPROM_INIT_RETRY 1 - -// -// This return code is not available from any Tiva part and has been removed. -// -#define EEPROM_RC_INVPL 0x00000100 - -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_EEPROM_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/emac.c b/bsp/tm4c129x-dk/libraries/driverlib/emac.c deleted file mode 100644 index 8c238d299e04d722c471785ea0f0f70e0bb984c0..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/emac.c +++ /dev/null @@ -1,4983 +0,0 @@ -//***************************************************************************** -// -// emac.c - Driver for the Integrated Ethernet Controller on Snowflake-class -// Tiva devices. -// -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup emac_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_emac.h" -#include "driverlib/debug.h" -#include "driverlib/emac.h" -#include "driverlib/sysctl.h" -#include "driverlib/interrupt.h" -#include "driverlib/sw_crc.h" - -//***************************************************************************** -// -// Combined defines used in parameter validity checks. -// -//***************************************************************************** - -//***************************************************************************** -// -// Combined valid configuration flags. -// -//***************************************************************************** -#define VALID_CONFIG_FLAGS (EMAC_CONFIG_USE_MACADDR1 | \ - EMAC_CONFIG_SA_INSERT | \ - EMAC_CONFIG_SA_REPLACE | \ - EMAC_CONFIG_2K_PACKETS | \ - EMAC_CONFIG_STRIP_CRC | \ - EMAC_CONFIG_JABBER_DISABLE | \ - EMAC_CONFIG_JUMBO_ENABLE | \ - EMAC_CONFIG_IF_GAP_MASK | \ - EMAC_CONFIG_CS_DISABLE | \ - EMAC_CONFIG_100MBPS | \ - EMAC_CONFIG_RX_OWN_DISABLE | \ - EMAC_CONFIG_LOOPBACK | \ - EMAC_CONFIG_FULL_DUPLEX | \ - EMAC_CONFIG_CHECKSUM_OFFLOAD | \ - EMAC_CONFIG_RETRY_DISABLE | \ - EMAC_CONFIG_AUTO_CRC_STRIPPING | \ - EMAC_CONFIG_BO_MASK | \ - EMAC_CONFIG_DEFERRAL_CHK_ENABLE | \ - EMAC_CONFIG_PREAMBLE_MASK) - -//***************************************************************************** -// -// Combined valid frame filter flags. -// -//***************************************************************************** -#define VALID_FRMFILTER_FLAGS (EMAC_FRMFILTER_RX_ALL | \ - EMAC_FRMFILTER_VLAN | \ - EMAC_FRMFILTER_HASH_AND_PERFECT | \ - EMAC_FRMFILTER_SADDR | \ - EMAC_FRMFILTER_INV_SADDR | \ - EMAC_FRMFILTER_PASS_NO_PAUSE | \ - EMAC_FRMFILTER_PASS_ALL_CTRL | \ - EMAC_FRMFILTER_PASS_ADDR_CTRL | \ - EMAC_FRMFILTER_BROADCAST | \ - EMAC_FRMFILTER_PASS_MULTICAST | \ - EMAC_FRMFILTER_INV_DADDR | \ - EMAC_FRMFILTER_HASH_MULTICAST | \ - EMAC_FRMFILTER_HASH_UNICAST | \ - EMAC_FRMFILTER_PROMISCUOUS) - -//***************************************************************************** -// -// Combined valid maskable interrupts. -// -//***************************************************************************** -#define EMAC_MASKABLE_INTS (EMAC_INT_EARLY_RECEIVE | \ - EMAC_INT_BUS_ERROR | \ - EMAC_INT_EARLY_TRANSMIT | \ - EMAC_INT_RX_WATCHDOG | \ - EMAC_INT_RX_STOPPED | \ - EMAC_INT_RX_NO_BUFFER | \ - EMAC_INT_RECEIVE | \ - EMAC_INT_TX_UNDERFLOW | \ - EMAC_INT_RX_OVERFLOW | \ - EMAC_INT_TX_JABBER | \ - EMAC_INT_TX_NO_BUFFER | \ - EMAC_INT_TX_STOPPED | \ - EMAC_INT_TRANSMIT | \ - EMAC_INT_NORMAL_INT | \ - EMAC_INT_ABNORMAL_INT | \ - EMAC_INT_PHY) - -//***************************************************************************** -// -// Combined valid normal interrupts. -// -//***************************************************************************** -#define EMAC_NORMAL_INTS (EMAC_INT_TRANSMIT | \ - EMAC_INT_RECEIVE | \ - EMAC_INT_EARLY_RECEIVE | \ - EMAC_INT_TX_NO_BUFFER) - -//***************************************************************************** -// -// Combined valid abnormal interrupts. -// -//***************************************************************************** -#define EMAC_ABNORMAL_INTS (EMAC_INT_TX_STOPPED | \ - EMAC_INT_TX_JABBER | \ - EMAC_INT_RX_OVERFLOW | \ - EMAC_INT_TX_UNDERFLOW | \ - EMAC_INT_RX_NO_BUFFER | \ - EMAC_INT_RX_STOPPED | \ - EMAC_INT_RX_WATCHDOG | \ - EMAC_INT_EARLY_TRANSMIT | \ - EMAC_INT_BUS_ERROR) - -//***************************************************************************** -// -// Interrupt sources reported via the DMARIS register but which are not -// masked (or enabled) via the DMAIM register. -// -//***************************************************************************** -#define EMAC_NON_MASKED_INTS (EMAC_DMARIS_LPI | \ - EMAC_DMARIS_TT | \ - EMAC_DMARIS_PMT | \ - EMAC_DMARIS_MMC) - -//***************************************************************************** -// -// The number of MAC addresses the module can store for filtering purposes. -// -//***************************************************************************** -#define NUM_MAC_ADDR 4 - -//***************************************************************************** -// -// Macros aiding access to the MAC address registers. -// -//***************************************************************************** -#define MAC_ADDR_OFFSET (EMAC_O_ADDR1L - EMAC_O_ADDR0L) -#define EMAC_O_ADDRL(n) (EMAC_O_ADDR0L + (MAC_ADDR_OFFSET * (n))) -#define EMAC_O_ADDRH(n) (EMAC_O_ADDR0H + (MAC_ADDR_OFFSET * (n))) - -//***************************************************************************** -// -// A structure used to help in choosing the correct clock divisor for the MII -// based on the current system clock rate. -// -//***************************************************************************** -static const struct -{ - uint32_t ui32SysClockMax; - uint32_t ui32Divisor; -} -g_pi16MIIClockDiv[] = -{ - { 64000000, EMAC_MIIADDR_CR_35_60 }, - { 104000000, EMAC_MIIADDR_CR_60_100 }, - { 150000000, EMAC_MIIADDR_CR_100_150 } -}; - -//***************************************************************************** -// -// The number of clock divisors in the above table. -// -//***************************************************************************** -#define NUM_CLOCK_DIVISORS (sizeof(g_pi16MIIClockDiv) / \ - sizeof(g_pi16MIIClockDiv[0])) - -//***************************************************************************** -// -// The define for accessing PHY registers in the MMD address space. -// -//***************************************************************************** -#define DEV_ADDR(x) ((x & 0xF000) >> 12) -#define REG_ADDR(x) ((x & 0x0FFF)) - -//***************************************************************************** -// -//! Initializes the Ethernet MAC and sets bus-related DMA parameters. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param ui32SysClk is the current system clock frequency in Hertz. -//! \param ui32BusConfig defines the bus operating mode for the Ethernet MAC -//! DMA controller. -//! \param ui32RxBurst is the maximum receive burst size in words. -//! \param ui32TxBurst is the maximum transmit burst size in words. -//! \param ui32DescSkipSize is the number of 32-bit words to skip between -//! two unchained DMA descriptors. Values in the range 0 to 31 are valid. -//! -//! This function sets bus-related parameters for the Ethernet MAC DMA -//! engines. It must be called after EMACPHYConfigSet() and called again -//! after any subsequent call to EMACPHYConfigSet(). -//! -//! The \e ui32BusConfig parameter is the logical OR of various fields. The -//! first sets the DMA channel priority weight: -//! -//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_1 -//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_2 -//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_3 -//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_4 -//! -//! The second field sets the receive and transmit priorities used when -//! arbitrating between the Rx and Tx DMA. The priorities are Rx:Tx unless -//! \b EMAC_BCONFIG_TX_PRIORITY is also specified, in which case they become -//! Tx:Rx. The priority provided here is ignored if -//! \b EMAC_BCONFIG_PRIORITY_FIXED is specified. -//! -//! - \b EMAC_BCONFIG_PRIORITY_1_1 -//! - \b EMAC_BCONFIG_PRIORITY_2_1 -//! - \b EMAC_BCONFIG_PRIORITY_3_1 -//! - \b EMAC_BCONFIG_PRIORITY_4_1 -//! -//! The following additional flags may also be defined: -//! -//! - \b EMAC_BCONFIG_TX_PRIORITY indicates that the transmit DMA should be -//! higher priority in all arbitration for the system-side bus. If this is not -//! defined, the receive DMA has higher priority. -//! - \b EMAC_BCONFIG_ADDR_ALIGNED works in tandem with -//! \b EMAC_BCONFIG_FIXED_BURST to control address alignment of AHB bursts. -//! When both flags are specified, all bursts are aligned to the start address -//! least significant bits. If \b EMAC_BCONFIG_FIXED_BURST is not specified, -//! the first burst is unaligned but subsequent bursts are aligned to the -//! address. -//! - \b EMAC_BCONFIG_ALT_DESCRIPTORS indicates that the DMA engine should -//! use the alternate descriptor format as defined in type -//! \b tEMACDMADescriptor. If absent, the basic descriptor type is used. -//! Alternate descriptors are required if using IEEE 1588-2008 advanced -//! timestamping, VLAN or TCP/UDP/ICMP CRC insertion features. Note that, -//! for clarity, emac.h does not contain type definitions for the basic -//! descriptor type. Please see the part datasheet for information on basic -//! descriptor structures. -//! - \b EMAC_BCONFIG_PRIORITY_FIXED indicates that a fixed priority scheme -//! should be employed when arbitrating between the transmit and receive DMA -//! for system-side bus access. In this case, the receive channel always has -//! priority unless \b EMAC_BCONFIG_TX_PRIORITY is set, in which case the -//! transmit channel has priority. If \b EMAC_BCONFIG_PRIORITY_FIXED is not -//! specified, a weighted round-robin arbitration scheme is used with the -//! weighting defined using \b EMAC_BCONFIG_PRIORITY_1_1, -//! \b EMAC_BCONFIG_PRIORITY_2_1, \b EMAC_BCONFIG_PRIORITY_3_1 or -//! \b EMAC_BCONFIG_PRIORITY_4_1, and \b EMAC_BCONFIG_TX_PRIORITY. -//! - \b EMAC_BCONFIG_FIXED_BURST indicates that fixed burst transfers should -//! be used. -//! - \b EMAC_BCONFIG_MIXED_BURST indicates that the DMA engine should use -//! mixed burst types depending on the length of data to be transferred -//! across the system bus. -//! -//! The \e ui32RxBurst and \e ui32TxBurst parameters indicate the maximum -//! number of words that the relevant DMA should transfer in a single -//! transaction. Valid values are 1, 2, 4, 8, 16 and 32. Any other value -//! results in undefined behavior. -//! -//! The \e ui32DescSkipSize parameter is used when the descriptor lists are -//! using ring mode (where descriptors are contiguous in memory with the last -//! descriptor marked with the \b END_OF_RING flag) rather than chained mode -//! (where each descriptor includes a field that points to the next descriptor -//! in the list). In ring mode, the hardware uses the \e ui32DescSkipSize to -//! skip past any application-defined fields after the end of the hardware- -//! defined descriptor fields. The parameter value indicates the number of -//! 32-bit words to skip after the last field of the hardware-defined -//! descriptor to get to the first field of the next descriptor. When using -//! arrays of either the \b tEMACDMADescriptor or \b tEMACAltDMADescriptor -//! types defined for this driver, \e ui32DescSkipSize must be set to 1 to skip -//! the \e pvNext pointer added to the end of each of these structures. -//! Applications may modify these structure definitions to include their own -//! application-specific data and modify \e ui32DescSkipSize appropriately if -//! desired. -//! -//! \return None. -// -//***************************************************************************** -void -EMACInit(uint32_t ui32Base, uint32_t ui32SysClk, uint32_t ui32BusConfig, - uint32_t ui32RxBurst, uint32_t ui32TxBurst, uint32_t ui32DescSkipSize) -{ - uint32_t ui32Val, ui32Div; - - // - // Parameter sanity checks. - // - ASSERT(ui32DescSkipSize < 32); - ASSERT(ui32TxBurst < (32 * 8)); - ASSERT(ui32RxBurst < (32 * 8)); - - // - // Make sure that the DMA software reset is clear before continuing. - // - while(HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & EMAC_DMABUSMOD_SWR) - { - } - - // - // Set common flags. Note that this driver assumes we are always using - // 8 word descriptors so we need to OR in EMAC_DMABUSMOD_ATDS here. - // - ui32Val = (ui32BusConfig | (ui32DescSkipSize << EMAC_DMABUSMOD_DSL_S) | - EMAC_DMABUSMOD_ATDS); - - // - // Do we need to use the 8X burst length multiplier? - // - if((ui32TxBurst > 32) || (ui32RxBurst > 32)) - { - // - // Divide both burst lengths by 8 and set the 8X burst length - // multiplier. - // - ui32Val |= EMAC_DMABUSMOD_8XPBL; - ui32TxBurst >>= 3; - ui32RxBurst >>= 3; - - // - // Sanity check - neither burst length should have become zero. If - // they did, this indicates that the values passed are invalid. - // - ASSERT(ui32RxBurst); - ASSERT(ui32TxBurst); - } - - // - // Are the receive and transmit burst lengths the same? - // - if(ui32RxBurst == ui32TxBurst) - { - // - // Yes - set up to use a single burst length. - // - ui32Val |= (ui32TxBurst << EMAC_DMABUSMOD_PBL_S); - } - else - { - // - // No - we need to use separate burst lengths for each. - // - ui32Val |= (EMAC_DMABUSMOD_USP | - (ui32TxBurst << EMAC_DMABUSMOD_PBL_S) | - (ui32RxBurst << EMAC_DMABUSMOD_RPBL_S)); - } - - // - // Finally, write the bus mode register. - // - HWREG(ui32Base + EMAC_O_DMABUSMOD) = ui32Val; - - // - // Default the MII CSR clock divider based on the fastest system clock. - // - ui32Div = g_pi16MIIClockDiv[NUM_CLOCK_DIVISORS - 1].ui32Divisor; - - // - // Find the MII CSR clock divider to use based on the current system clock. - // - for(ui32Val = 0; ui32Val < NUM_CLOCK_DIVISORS; ui32Val++) - { - if(ui32SysClk <= g_pi16MIIClockDiv[ui32Val].ui32SysClockMax) - { - ui32Div = g_pi16MIIClockDiv[ui32Val].ui32Divisor; - break; - } - } - - // - // Set the MII CSR clock speed. - // - HWREG(ui32Base + EMAC_O_MIIADDR) = ((HWREG(ui32Base + EMAC_O_MIIADDR) & - ~EMAC_MIIADDR_CR_M) | ui32Div); - - // - // Disable all the MMC interrupts as these are enabled by default at reset. - // - HWREG(ui32Base + EMAC_O_MMCRXIM) = 0xFFFFFFFF; - HWREG(ui32Base + EMAC_O_MMCTXIM) = 0xFFFFFFFF; -} - -//***************************************************************************** -// -//! Resets the Ethernet MAC. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! -//! This function performs a reset of the Ethernet MAC by resetting all logic -//! and returning all registers to their default values. The function returns -//! only after the hardware indicates that the reset has completed. -//! -//! \note To ensure that the reset completes, the selected PHY clock must be -//! enabled when this function is called. If the PHY clock is absent, this -//! function does not return. -//! -//! \return None. -// -//***************************************************************************** -void -EMACReset(uint32_t ui32Base) -{ - // - // Reset the Ethernet MAC. - // - HWREG(ui32Base + EMAC_O_DMABUSMOD) |= EMAC_DMABUSMOD_SWR; - - // - // Wait for the reset to complete. - // - while(HWREG(ui32Base + EMAC_O_DMABUSMOD) & EMAC_DMABUSMOD_SWR) - { - } -} - -//***************************************************************************** -// -//! Selects the Ethernet PHY in use. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param ui32Config selects the PHY in use and, when using the internal -//! PHY, allows various various PHY parameters to be configured. -//! -//! This function must be called prior to EMACInit() and EMACConfigSet() to -//! select the Ethernet PHY to be used. If the internal PHY is selected, the -//! function also allows configuration of various PHY parameters. Note that -//! the Ethernet MAC is reset during this function call because parameters used -//! by this function are latched by the hardware only on a MAC reset. The call -//! sequence to select and configure the PHY, therefore, must be as follows: -//! -//! \verbatim -//! // Enable and reset the MAC. -//! SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0); -//! SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0); -//! if() -//! { -//! // Enable and reset the internal PHY. -//! SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0); -//! SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0); -//! } -//! -//! // Ensure the MAC is completed its reset. -//! while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0)) -//! { -//! } -//! -//! // Set the PHY type and configuration options. -//! EMACPHYConfigSet(EMAC0_BASE, ); -//! -//! // Initialize and configure the MAC. -//! EMACInit(EMAC0_BASE, , , -//! , , ); -//! EMACConfigSet(EMAC0_BASE, ); -//! \endverbatim -//! -//! The \e ui32Config parameter must specify one of the following values: -//! -//! - \b EMAC_PHY_TYPE_INTERNAL selects the internal Ethernet PHY. -//! - \b EMAC_PHY_TYPE_EXTERNAL_MII selects an external PHY connected via the -//! MII interface. -//! - \b EMAC_PHY_TYPE_EXTERNAL_RMII selects an external PHY connected via the -//! RMII interface. -//! -//! If \b EMAC_PHY_TYPE_INTERNAL is selected, the following flags may be ORed -//! into \e ui32Config to control various PHY features and modes. These flags -//! are ignored if an external PHY is selected. -//! -//! - \b EMAC_PHY_INT_NIB_TXERR_DET_DIS disables odd nibble transmit error -//! detection (sets the default value of PHY register MR10, bit 1). -//! - \b EMAC_PHY_INT_RX_ER_DURING_IDLE enables receive error detection during -//! idle (sets the default value of PHY register MR10, bit 2). -//! - \b EMAC_PHY_INT_ISOLATE_MII_LLOSS ties the MII outputs low if no link is -//! established in 100B-T and full duplex modes (sets the default value of PHY -//! register MR10, bit 3). -//! - \b EMAC_PHY_INT_LINK_LOSS_RECOVERY enables link loss recovery (sets the -//! default value of PHY register MR9, bit 7). -//! - \b EMAC_PHY_INT_TDRRUN enables execution of the TDR procedure after a link -//! down event (sets the default value of PHY register MR9, bit 8). -//! - \b EMAC_PHY_INT_LD_ON_RX_ERR_COUNT enables link down if the receiver -//! error count reaches 32 within a 10-us interval (sets the default value of -//! PHY register MR11 bit 3). -//! - \b EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT enables link down if the MTL3 error -//! count reaches 20 in a 10 us-interval (sets the default value of PHY register -//! MR11 bit 2). -//! - \b EMAC_PHY_INT_LD_ON_LOW_SNR enables link down if the low SNR threshold -//! is crossed 20 times in a 10 us-interval (sets the default value of PHY -//! register MR11 bit 1). -//! - \b EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY enables link down if energy detector -//! indicates Energy Loss (sets the default value of PHY register MR11 bit 0). -//! - \b EMAC_PHY_INT_POLARITY_SWAP inverts the polarity on both TPTD and TPRD -//! pairs (sets the default value of PHY register MR11 bit 5). -//! - \b EMAC_PHY_INT_MDI_SWAP swaps the MDI pairs putting receive on the TPTD -//! pair and transmit on TPRD (sets the default value of PHY register MR11 bit -//! 6). -//! - \b EMAC_PHY_INT_ROBUST_MDIX enables robust auto MDI-X resolution (sets the -//! default value of PHY register MR9 bit 5). -//! - \b EMAC_PHY_INT_FAST_MDIX enables fast auto-MDI/MDIX resolution (sets the -//! default value of PHY register MR9 bit 6). -//! - \b EMAC_PHY_INT_MDIX_EN enables auto-MDI/MDIX crossover (sets the -//! default value of PHY register MR9 bit 14). -//! - \b EMAC_PHY_INT_FAST_RXDV_DETECT enables fast RXDV detection (set the -//! default value of PHY register MR9 bit 1). -//! - \b EMAC_PHY_INT_FAST_L_UP_DETECT enables fast link-up time during parallel -//! detection (sets the default value of PHY register MR10 bit 6) -//! - \b EMAC_PHY_INT_EXT_FULL_DUPLEX forces full-duplex while working with a -//! link partner in forced 100B-TX (sets the default value of PHY register -//! MR10 bit 5). -//! - \b EMAC_PHY_INT_FAST_AN_80_50_35 enables fast auto-negotiation using -//! break link, link fail inhibit and wait timers set to 80, 50 and 35 -//! respectively (sets the default value of PHY register MR9 bits [4:2] to -//! 3b100). -//! - \b EMAC_PHY_INT_FAST_AN_120_75_50 enables fast auto-negotiation using -//! break link, link fail inhibit and wait timers set to 120, 75 and 50 -//! respectively (sets the default value of PHY register MR9 bits [4:2] to -//! 3b101). -//! - \b EMAC_PHY_INT_FAST_AN_140_150_100 enables fast auto-negotiation using -//! break link, link fail inhibit and wait timers set to 140, 150 and 100 -//! respectively (sets the default value of PHY register MR9 bits [4:2] to -//! 3b110). -//! - \b EMAC_PHY_FORCE_10B_T_HALF_DUPLEX disables auto-negotiation and forces -//! operation in 10Base-T, half duplex mode (sets the default value of PHY -//! register MR9 bits [13:11] to 3b000). -//! - \b EMAC_PHY_FORCE_10B_T_FULL_DUPLEX disables auto-negotiation and forces -//! operation in 10Base-T, full duplex mode (sets the default value of PHY -//! register MR9 bits [13:11] to 3b001). -//! - \b EMAC_PHY_FORCE_100B_T_HALF_DUPLEX disables auto-negotiation and forces -//! operation in 100Base-T, half duplex mode (sets the default value of PHY -//! register MR9 bits [13:11] to 3b010). -//! - \b EMAC_PHY_FORCE_100B_T_FULL_DUPLEX disables auto-negotiation and forces -//! operation in 100Base-T, full duplex mode (sets the default value of PHY -//! register MR9 bits [13:11] to 3b011). -//! - \b EMAC_PHY_AN_10B_T_HALF_DUPLEX enables auto-negotiation and advertises -//! 10Base-T, half duplex mode (sets the default value of PHY register MR9 bits -//! [13:11] to 3b100). -//! - \b EMAC_PHY_AN_10B_T_FULL_DUPLEX enables auto-negotiation and advertises -//! 10Base-T half or full duplex modes (sets the default value of PHY register -//! MR9 bits [13:11] to 3b101). -//! - \b EMAC_PHY_AN_100B_T_HALF_DUPLEX enables auto-negotiation and advertises -//! 10Base-T half or full duplex, and 100Base-T half duplex modes (sets the -//! default value of PHY register MR9 bits [13:11] to 3b110). -//! - \b EMAC_PHY_AN_100B_T_FULL_DUPLEX enables auto-negotiation and advertises -//! 10Base-T half or full duplex, and 100Base-T half or full duplex modes (sets -//! the default value of PHY register MR9 bits [13:11] to 3b111). -//! - \b EMAC_PHY_INT_HOLD prevents the PHY from transmitting energy on the -//! line. -//! -//! As a side effect of this function, the Ethernet MAC is reset so any -//! previous MAC configuration is lost. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Write the Ethernet PHY configuration to the peripheral configuration - // register. - // - HWREG(ui32Base + EMAC_O_PC) = ui32Config; - - // - // If using the internal PHY, reset it to ensure that new configuration is - // latched there. - // - if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL) - { - SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0); - while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EPHY0)) - { - // - // Wait for the PHY reset to complete. - // - } - - // - // Delay a bit longer to ensure that the PHY reset has completed. - // - SysCtlDelay(10000); - } - - // - // If using an external RMII PHY, we must set 2 bits in the Ethernet MAC - // Clock Configuration Register. - // - if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_EXTERNAL_RMII) - { - // - // Select and enable the external clock from the RMII PHY. - // - HWREG(EMAC0_BASE + EMAC_O_CC) |= EMAC_CC_CLKEN; - } - else - { - // - // Disable the external clock. - // - HWREG(EMAC0_BASE + EMAC_O_CC) &= ~EMAC_CC_CLKEN; - } - - // - // Reset the MAC regardless of whether the PHY connection changed or not. - // - EMACReset(EMAC0_BASE); - - SysCtlDelay(1000); -} - -//***************************************************************************** -// -//! Configures basic Ethernet MAC operation parameters. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param ui32Config provides various flags and values configuring the MAC. -//! \param ui32ModeFlags provides configuration relating to the transmit and -//! receive DMA engines. -//! \param ui32RxMaxFrameSize sets the maximum receive frame size above which -//! an error is reported. -//! -//! This function is called to configure basic operating parameters for the -//! MAC and its DMA engines. -//! -//! The \e ui32Config parameter is the logical OR of various fields and -//! flags. The first field determines which MAC address is used during -//! insertion or replacement for all transmitted frames. Valid options are -//! -//! - \b EMAC_CONFIG_USE_MACADDR1 and -//! - \b EMAC_CONFIG_USE_MACADDR0 -//! -//! The interframe gap between transmitted frames is controlled using one of -//! the following values: -//! -//! - \b EMAC_CONFIG_IF_GAP_96BITS -//! - \b EMAC_CONFIG_IF_GAP_88BITS -//! - \b EMAC_CONFIG_IF_GAP_80BITS -//! - \b EMAC_CONFIG_IF_GAP_72BITS -//! - \b EMAC_CONFIG_IF_GAP_64BITS -//! - \b EMAC_CONFIG_IF_GAP_56BITS -//! - \b EMAC_CONFIG_IF_GAP_48BITS -//! - \b EMAC_CONFIG_IF_GAP_40BITS -//! -//! The number of bytes of preamble added to the beginning of every transmitted -//! frame is selected using one of the following values: -//! -//! - \b EMAC_CONFIG_7BYTE_PREAMBLE -//! - \b EMAC_CONFIG_5BYTE_PREAMBLE -//! - \b EMAC_CONFIG_3BYTE_PREAMBLE -//! -//! The back-off limit determines the range of the random time that the MAC -//! delays after a collision and before attempting to retransmit a frame. One -//! of the following values must be used to select this limit. In each case, -//! the retransmission delay in terms of 512 bit time slots, is the lower of -//! (2 ** N) and a random number between 0 and the selected backoff-limit. -//! -//! - \b EMAC_CONFIG_BO_LIMIT_1024 -//! - \b EMAC_CONFIG_BO_LIMIT_256 -//! - \b EMAC_CONFIG_BO_LIMIT_16 -//! - \b EMAC_CONFIG_BO_LIMIT_2 -//! -//! Control over insertion or replacement of the source address in all -//! transmitted frames is provided by using one of the following fields: -//! -//! - \b EMAC_CONFIG_SA_INSERT causes the MAC address (0 or 1 depending -//! on whether \b EMAC_CONFIG_USE_MACADDR0 or \b EMAC_CONFIG_USE_MACADDR1 -//! was specified) to be inserted into all transmitted frames. -//! - \b EMAC_CONFIG_SA_REPLACE causes the MAC address to be replaced with -//! the selected address in all transmitted frames. -//! - \b EMAC_CONFIG_SA_FROM_DESCRIPTOR causes control of source address -//! insertion or deletion to be controlled by fields in the DMA transmit -//! descriptor, allowing control on a frame-by-frame basis. -//! -//! Whether the interface attempts to operate in full- or half-duplex mode is -//! controlled by one of the following flags: -//! -//! - \b EMAC_CONFIG_FULL_DUPLEX -//! - \b EMAC_CONFIG_HALF_DUPLEX -//! -//! The following additional flags may also be specified: -//! -//! - \b EMAC_CONFIG_2K_PACKETS enables IEEE802.3as support for 2K packets. -//! When specified, the MAC considers all frames up to 2000 bytes in length as -//! normal packets. When \b EMAC_CONFIG_JUMBO_ENABLE is not specified, all -//! frames larger than 2000 bytes are treated as Giant frames. This flag is -//! ignored if \b EMAC_CONFIG_JUMBO_ENABLE is specified. -//! - \b EMAC_CONFIG_STRIP_CRC causes the 4-byte CRC of all Ethernet type -//! frames to be stripped and dropped before the frame is forwarded to the -//! application. -//! - \b EMAC_CONFIG_JABBER_DISABLE disables the jabber timer on the -//! transmitter and enables frames of up to 16384 bytes to be transmitted. If -//! this flag is absent, the MAC does not allow more than 2048 (or 10240 if -//! \b EMAC_CONFIG_JUMBO_ENABLE is specified) bytes to be sent in any one -//! frame. -//! - \b EMAC_CONFIG_JUMBO_ENABLE enables Jumbo Frames, allowing frames of -//! up to 9018 (or 9022 if using VLAN tagging) to be handled without reporting -//! giant frame errors. -//! - \b EMAC_CONFIG_100MBPS forces the MAC to communicate with the PHY using -//! 100Mbps signaling. If this option is not specified, the MAC uses 10Mbps -//! signaling. This speed setting is important when using an external RMII -//! PHY where the selected rate must match the PHY's setting which may have -//! been made as a result of auto-negotiation. When using the internal PHY -//! or an external MII PHY, the signaling rate is controlled by the PHY- -//! provided transmit and receive clocks. -//! - \b EMAC_CONFIG_CS_DISABLE disables Carrier Sense during transmission -//! when operating in half-duplex mode. -//! - \b EMAC_CONFIG_RX_OWN_DISABLE disables reception of transmitted frames -//! when operating in half-duplex mode. -//! - \b EMAC_CONFIG_LOOPBACK enables internal loopback. -//! - \b EMAC_CONFIG_CHECKSUM_OFFLOAD enables IPv4 header checksum checking -//! and IPv4 or IPv6 TCP, UPD or ICMP payload checksum checking. The results -//! of the checksum calculations are reported via status fields in the DMA -//! receive descriptors. -//! - \b EMAC_CONFIG_RETRY_DISABLE disables retransmission in cases where -//! half-duplex mode is in use and a collision occurs. This condition causes -//! the current frame to be ignored and a frame abort to be reported in the -//! transmit frame status. -//! - \b EMAC_CONFIG_AUTO_CRC_STRIPPING strips the last 4 bytes (frame check -//! sequence) from all Ether type frames before forwarding the frames to the -//! application. -//! - \b EMAC_CONFIG_DEFERRAL_CHK_ENABLE enables transmit deferral checking -//! in half-duplex mode. When enabled, the transmitter reports an error if it -//! is unable to transmit a frame for more than 24288 bit times (or 155680 -//! bit times in Jumbo frame mode) due to an active carrier sense signal on -//! the MII. -//! -//! The \e ui32ModeFlags parameter sets operating parameters related to the -//! internal MAC FIFOs. It comprises a logical OR of the following fields. -//! The first selects the transmit FIFO threshold. Transmission of a frame -//! begins when this amount of data or a full frame exists in the transmit -//! FIFO. This field is ignored if \b EMAC_MODE_TX_STORE_FORWARD is -//! included. One of the following must be specified: -//! -//! - \b EMAC_MODE_TX_THRESHOLD_16_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_24_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_32_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_40_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_64_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_128_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_192_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_256_BYTES -//! -//! The second field controls the receive FIFO threshold. DMA transfers of -//! received data begin either when the receive FIFO contains a full frame -//! or this number of bytes. This field is ignored if -//! \b EMAC_MODE_RX_STORE_FORWARD is included. One of the following must be -//! specified: -//! -//! - \b EMAC_MODE_RX_THRESHOLD_64_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_32_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_96_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_128_BYTES -//! -//! The following additional flags may be specified: -//! -//! - \b EMAC_MODE_KEEP_BAD_CRC causes frames with TCP/IP checksum errors -//! to be forwarded to the application if those frames do not have any errors -//! (including FCS errors) in the Ethernet framing. In these cases, the frames -//! have errors only in the payload. If this flag is not specified, all frames -//! with any detected error are discarded unless \b EMAC_MODE_RX_ERROR_FRAMES -//! is also specified. -//! - \b EMAC_MODE_RX_STORE_FORWARD causes the receive DMA to read frames -//! from the FIFO only after the complete frame has been written to it. If -//! this mode is enabled, the receive threshold is ignored. -//! - \b EMAC_MODE_RX_FLUSH_DISABLE disables the flushing of received frames -//! in cases where receive descriptors or buffers are unavailable. -//! - \b EMAC_MODE_TX_STORE_FORWARD causes the transmitter to start -//! transmitting a frame only after the whole frame has been written to the -//! transmit FIFO. If this mode is enabled, the transmit threshold is ignored. -//! - \b EMAC_MODE_RX_ERROR_FRAMES causes all frames other than runt error -//! frames to be forwarded to the receive DMA regardless of any errors detected -//! in the frames. -//! - \b EMAC_MODE_RX_UNDERSIZED_FRAMES causes undersized frames (frames -//! shorter than 64 bytes but with no errors) to the application. If this -//! option is not selected, all undersized frames are dropped by the receiver -//! unless it has already started transferring them to the receive FIFO due to -//! the receive threshold setting. -//! - \b EMAC_MODE_OPERATE_2ND_FRAME enables the transmit DMA to operate on a -//! second frame while waiting for the previous frame to be transmitted and -//! associated status and timestamps to be reported. If absent, the transmit -//! DMA works on a single frame at any one time, waiting for that frame to be -//! transmitted and its status to be received before moving on to the next -//! frame. -//! -//! The \e ui32RxMaxFrameSize parameter may be used to override the default -//! setting for the maximum number of bytes that can be received in a frame -//! before that frame is flagged as being in error. If the parameter is set -//! to 0, the default hardware settings are applied. If non-zero, any frame -//! received which is longer than the \e ui32RxMaxFrameSize, regardless of -//! whether the MAC is configured for normal or Jumbo frame operation, is -//! flagged as an error. -//! -//! \return None. -// -//***************************************************************************** -void -EMACConfigSet(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32ModeFlags, - uint32_t ui32RxMaxFrameSize) -{ - // - // Parameter sanity check. Note that we allow TX_ENABLED and RX_ENABLED - // here because we'll mask them off before writing the value and this - // makes back-to-back EMACConfigGet/EMACConfigSet calls work without the - // caller needing to explicitly remove these bits from the parameter. - // - ASSERT((ui32Config & ~(VALID_CONFIG_FLAGS | EMAC_CONFIG_TX_ENABLED | - EMAC_CONFIG_RX_ENABLED)) == 0); - ASSERT(!ui32RxMaxFrameSize || ((ui32RxMaxFrameSize < 0x4000) && - (ui32RxMaxFrameSize > 1522))); - - // - // Set the configuration flags as specified. Note that we unconditionally - // OR in the EMAC_CFG_PS bit here since this implementation supports only - // MII and RMII interfaces to the PHYs. - // - HWREG(ui32Base + EMAC_O_CFG) = - ((HWREG(ui32Base + EMAC_O_CFG) & ~VALID_CONFIG_FLAGS) | ui32Config | - EMAC_CFG_PS); - - // - // Set the maximum receive frame size. If 0 is passed, this implies - // that the default maximum frame size should be used so just turn off - // the override. - // - if(ui32RxMaxFrameSize) - { - HWREG(ui32Base + EMAC_O_WDOGTO) = ui32RxMaxFrameSize | EMAC_WDOGTO_PWE; - } - else - { - HWREG(ui32Base + EMAC_O_WDOGTO) &= ~EMAC_WDOGTO_PWE; - } - - // - // Set the operating mode register. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) = ui32ModeFlags; -} - -//***************************************************************************** -// -//! Returns the Ethernet MAC's current basic configuration parameters. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param pui32Config points to storage that is written with Ethernet MAC -//! configuration. -//! \param pui32Mode points to storage that is written with Ethernet MAC mode -//! information. -//! \param pui32RxMaxFrameSize points to storage that is written with the -//! maximum receive frame size. -//! -//! This function is called to query the basic operating parameters for the -//! MAC and its DMA engines. -//! -//! The \e pui32Config parameter is written with the logical OR of various -//! fields and flags. The first field describes which MAC address is used -//! during insertion or replacement for all transmitted frames. Valid options -//! are -//! -//! - \b EMAC_CONFIG_USE_MACADDR1 -//! - \b EMAC_CONFIG_USE_MACADDR0 -//! -//! The interframe gap between transmitted frames is given using one of the -//! following values: -//! -//! - \b EMAC_CONFIG_IF_GAP_96BITS -//! - \b EMAC_CONFIG_IF_GAP_88BITS -//! - \b EMAC_CONFIG_IF_GAP_80BITS -//! - \b EMAC_CONFIG_IF_GAP_72BITS -//! - \b EMAC_CONFIG_IF_GAP_64BITS -//! - \b EMAC_CONFIG_IF_GAP_56BITS -//! - \b EMAC_CONFIG_IF_GAP_48BITS -//! - \b EMAC_CONFIG_IF_GAP_40BITS -//! -//! The number of bytes of preamble added to the beginning of every transmitted -//! frame is described using one of the following values: -//! -//! - \b EMAC_CONFIG_7BYTE_PREAMBLE -//! - \b EMAC_CONFIG_5BYTE_PREAMBLE -//! - \b EMAC_CONFIG_3BYTE_PREAMBLE -//! -//! The back-off limit determines the range of the random time that the MAC -//! delays after a collision and before attempting to retransmit a frame. One -//! of the following values provides the currently selected limit. In each -//! case the retransmission delay in terms of 512 bit time slots, is the -//! lower of (2 ** N) and a random number between 0 and the reported -//! backoff-limit. -//! -//! - \b EMAC_CONFIG_BO_LIMIT_1024 -//! - \b EMAC_CONFIG_BO_LIMIT_256 -//! - \b EMAC_CONFIG_BO_LIMIT_16 -//! - \b EMAC_CONFIG_BO_LIMIT_2 -//! -//! Handling of insertion or replacement of the source address in all -//! transmitted frames is described by one of the following fields: -//! -//! - \b EMAC_CONFIG_SA_INSERT causes the MAC address (0 or 1 depending -//! on whether \b EMAC_CONFIG_USE_MACADDR0 or \b EMAC_CONFIG_USE_MACADDR1 -//! was specified) to be inserted into all transmitted frames. -//! - \b EMAC_CONFIG_SA_REPLACE causes the MAC address to be replaced with -//! the selected address in all transmitted frames. -//! - \b EMAC_CONFIG_SA_FROM_DESCRIPTOR causes control of source address -//! insertion or deletion to be controlled by fields in the DMA transmit -//! descriptor, allowing control on a frame-by-frame basis. -//! -//! Whether the interface attempts to operate in full- or half-duplex mode is -//! reported by one of the following flags: -//! -//! - \b EMAC_CONFIG_FULL_DUPLEX -//! - \b EMAC_CONFIG_HALF_DUPLEX -//! -//! The following additional flags may also be included: -//! -//! - \b EMAC_CONFIG_2K_PACKETS indicates that IEEE802.3as support for 2K -//! packets is enabled. When present, the MAC considers all frames up to 2000 -//! bytes in length as normal packets. When \b EMAC_CONFIG_JUMBO_ENABLE is -//! not reported, all frames larger than 2000 bytes are treated as Giant -//! frames. The value of this flag should be ignored if -//! \b EMAC_CONFIG_JUMBO_ENABLE is also reported. -//! - \b EMAC_CONFIG_STRIP_CRC indicates that the 4-byte CRC of all Ethernet -//! type frames is being stripped and dropped before the frame is forwarded to -//! the application. -//! - \b EMAC_CONFIG_JABBER_DISABLE indicates that the the jabber timer on the -//! transmitter is disabled, allowing frames of up to 16384 bytes to be -//! transmitted. If this flag is absent, the MAC does not allow more than 2048 -//! (or 10240 if \b EMAC_CONFIG_JUMBO_ENABLE is reported) bytes to be sent in -//! any one frame. -//! - \b EMAC_CONFIG_JUMBO_ENABLE indicates that Jumbo Frames of up to 9018 -//! (or 9022 if using VLAN tagging) are enabled. -//! - \b EMAC_CONFIG_CS_DISABLE indicates that Carrier Sense is disabled -//! during transmission when operating in half-duplex mode. -//! - \b EMAC_CONFIG_100MBPS indicates that the MAC is using 100Mbps -//! signaling to communicate with the PHY. -//! - \b EMAC_CONFIG_RX_OWN_DISABLE indicates that reception of transmitted -//! frames is disabled when operating in half-duplex mode. -//! - \b EMAC_CONFIG_LOOPBACK indicates that internal loopback is enabled. -//! - \b EMAC_CONFIG_CHECKSUM_OFFLOAD indicates that IPv4 header checksum -//! checking and IPv4 or IPv6 TCP, UPD or ICMP payload checksum checking is -//! enabled. The results of the checksum calculations are reported via status -//! fields in the DMA receive descriptors. -//! - \b EMAC_CONFIG_RETRY_DISABLE indicates that retransmission is disabled -//! in cases where half-duplex mode is in use and a collision occurs. This -//! condition causes the current frame to be ignored and a frame abort to be -//! reported in the transmit frame status. -//! - \b EMAC_CONFIG_AUTO_CRC_STRIPPING indicates that the last 4 bytes -//! (frame check sequence) from all Ether type frames are being stripped before -//! frames are forwarded to the application. -//! - \b EMAC_CONFIG_DEFERRAL_CHK_ENABLE indicates that transmit deferral -//! checking is disabled in half-duplex mode. When enabled, the transmitter -//! reports an error if it is unable to transmit a frame for more than 24288 -//! bit times (or 155680 bit times in Jumbo frame mode) due to an active -//! carrier sense signal on the MII. -//! - \b EMAC_CONFIG_TX_ENABLED indicates that the MAC transmitter is -//! currently enabled. -//! - \b EMAC_CONFIG_RX_ENABLED indicates that the MAC receiver is -//! currently enabled. -//! -//! The \e pui32ModeFlags parameter is written with operating parameters -//! related to the internal MAC FIFOs. It comprises a logical OR of the -//! following fields. The first field reports the transmit FIFO threshold. -//! Transmission of a frame begins when this amount of data or a full frame -//! exists in the transmit FIFO. This field should be ignored if -//! \b EMAC_MODE_TX_STORE_FORWARD is also reported. One of the following -//! values is reported: -//! -//! - \b EMAC_MODE_TX_THRESHOLD_16_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_24_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_32_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_40_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_64_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_128_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_192_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_256_BYTES -//! -//! The second field reports the receive FIFO threshold. DMA transfers of -//! received data begin either when the receive FIFO contains a full frame -//! or this number of bytes. This field should be ignored if -//! \b EMAC_MODE_RX_STORE_FORWARD is included. One of the following values -//! is reported: -//! -//! - \b EMAC_MODE_RX_THRESHOLD_64_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_32_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_96_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_128_BYTES -//! -//! The following additional flags may be included: -//! -//! - \b EMAC_MODE_KEEP_BAD_CRC indicates that frames with TCP/IP checksum -//! errors are being forwarded to the application if those frames do not have -//! any errors (including FCS errors) in the Ethernet framing. In these cases, -//! the frames have errors only in the payload. If this flag is not reported, -//! all frames with any detected error are discarded unless -//! \b EMAC_MODE_RX_ERROR_FRAMES is also reported. -//! - \b EMAC_MODE_RX_STORE_FORWARD indicates that the receive DMA is -//! configured to read frames from the FIFO only after the complete frame has -//! been written to it. If this mode is enabled, the receive threshold is -//! ignored. -//! - \b EMAC_MODE_RX_FLUSH_DISABLE indicates that the flushing of received -//! frames is disabled in cases where receive descriptors or buffers are -//! unavailable. -//! - \b EMAC_MODE_TX_STORE_FORWARD indicates that the transmitter is -//! configured to transmit a frame only after the whole frame has been written -//! to the transmit FIFO. If this mode is enabled, the transmit threshold is -//! ignored. -//! - \b EMAC_MODE_RX_ERROR_FRAMES indicates that all frames other than runt -//! error frames are being forwarded to the receive DMA regardless of any -//! errors detected in the frames. -//! - \b EMAC_MODE_RX_UNDERSIZED_FRAMES indicates that undersized frames -//! (frames shorter than 64 bytes but with no errors) are being forwarded to -//! the application. If this option is not reported, all undersized frames are -//! dropped by the receiver unless it has already started transferring them to -//! the receive FIFO due to the receive threshold setting. -//! - \b EMAC_MODE_OPERATE_2ND_FRAME indicates that the transmit DMA is -//! configured to operate on a second frame while waiting for the previous -//! frame to be transmitted and associated status and timestamps to be reported. -//! If absent, the transmit DMA works on a single frame at any one time, -//! waiting for that frame to be transmitted and its status to be received -//! before moving on to the next frame. -//! - \b EMAC_MODE_TX_DMA_ENABLED indicates that the transmit DMA engine is -//! currently enabled. -//! - \b EMAC_MODE_RX_DMA_ENABLED indicates that the receive DMA engine is -//! currently enabled. -//! -//! The \e pui32RxMaxFrameSize is written with the currently configured maximum -//! receive packet size. Packets larger than this are flagged as being in -//! error. -//! -//! \return None. -// -//***************************************************************************** -void -EMACConfigGet(uint32_t ui32Base, uint32_t *pui32Config, uint32_t *pui32Mode, - uint32_t *pui32RxMaxFrameSize) -{ - uint32_t ui32Value; - - // - // Parameter sanity check. - // - ASSERT(pui32Mode); - ASSERT(pui32Config); - ASSERT(pui32RxMaxFrameSize); - - // - // Return the mode information from the operation mode register. - // - *pui32Mode = HWREG(ui32Base + EMAC_O_DMAOPMODE); - - // - // Return the current configuration flags from the EMAC_O_CFG register. - // - *pui32Config = (HWREG(ui32Base + EMAC_O_CFG) & - (VALID_CONFIG_FLAGS | EMAC_CONFIG_TX_ENABLED | - EMAC_CONFIG_RX_ENABLED)); - - // - // Get the receive packet size watchdog value. - // - ui32Value = HWREG(ui32Base + EMAC_O_WDOGTO); - if(ui32Value & EMAC_WDOGTO_PWE) - { - // - // The watchdog is enables so the maximum packet length can be read - // from the watchdog timeout register. - // - *pui32RxMaxFrameSize = ui32Value & EMAC_WDOGTO_WTO_M; - } - else - { - // - // The maximum packet size override found in the watchdog timer - // register is not enabled so the maximum packet size is determined - // by whether or not jumbo frame mode is enabled. - // - if(HWREG(ui32Base + EMAC_O_CFG) & EMAC_CFG_JFEN) - { - // - // Jumbo frames are enabled so the watchdog kicks in at 10240 - // bytes. - // - *pui32RxMaxFrameSize = 10240; - } - else - { - // - // Jumbo frames are not enabled so the watchdog kicks in at - // 2048 bytes. - // - *pui32RxMaxFrameSize = 2048; - } - } -} - -//***************************************************************************** -// -//! Sets the MAC address of the Ethernet controller. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param ui32Index is the zero-based index of the MAC address to set. -//! \param pui8MACAddr is the pointer to the array of MAC-48 address octets. -//! -//! This function programs the IEEE-defined MAC-48 address specified in -//! \e pui8MACAddr into the Ethernet controller. This address is used by the -//! Ethernet controller for hardware-level filtering of incoming Ethernet -//! packets (when promiscuous mode is not enabled). Index 0 is used to hold -//! the local node's MAC address which is inserted into all transmitted -//! packets. -//! -//! The controller may support several Ethernet MAC address slots, each of which -//! may be programmed independently and used to filter incoming packets. The -//! number of MAC addresses that the hardware supports may be queried using a -//! call to EMACNumAddrGet(). The value of the \e ui32Index parameter must -//! lie in the range from 0 to (number of MAC addresses - 1) inclusive. -//! -//! The MAC-48 address is defined as 6 octets, illustrated by the following -//! example address. The numbers are shown in hexadecimal format. -//! -//! AC-DE-48-00-00-80 -//! -//! In this representation, the first three octets (AC-DE-48) are the -//! Organizationally Unique Identifier (OUI). This is a number assigned by -//! the IEEE to an organization that requests a block of MAC addresses. The -//! last three octets (00-00-80) are a 24-bit number managed by the OUI owner -//! to uniquely identify a piece of hardware within that organization that is -//! to be connected to the Ethernet. -//! -//! In this representation, the octets are transmitted from left to right, -//! with the ``AC'' octet being transmitted first and the ``80'' octet being -//! transmitted last. Within an octet, the bits are transmitted LSB to MSB. -//! For this address, the first bit to be transmitted would be ``0'', the LSB -//! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of -//! ``80''. -//! -//! The address passed to this function in the \e pui8MACAddr array is -//! ordered with the first byte to be transmitted in the first array entry. -//! For example, the address given above could be represented using the -//! following array: -//! -//! uint8_t g_pui8MACAddr[] = { 0xAC, 0xDE, 0x48, 0x00, 0x00, 0x80 }; -//! -//! If the MAC address set by this function is currently enabled, it remains -//! enabled following this call. Similarly, any filter configured for -//! the MAC address remains unaffected by a change in the address. -//! -//! \return None. -// -//***************************************************************************** -void -EMACAddrSet(uint32_t ui32Base, uint32_t ui32Index, const uint8_t *pui8MACAddr) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Index < NUM_MAC_ADDR); - ASSERT(pui8MACAddr); - - // - // Set the high 2 bytes of the MAC address. Note that we must set the - // registers in this order since the address is latched internally - // on the write to EMAC_O_ADDRL. - // - HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) = - ((HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & 0xFFFF0000) | - pui8MACAddr[4] | (pui8MACAddr[5] << 8)); - - // - // Set the first 4 bytes of the MAC address - // - HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)) = - (pui8MACAddr[0] | (pui8MACAddr[1] << 8) | (pui8MACAddr[2] << 16) | - (pui8MACAddr[3] << 24)); -} - -//***************************************************************************** -// -//! Gets one of the MAC addresses stored in the Ethernet controller. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Index is the zero-based index of the MAC address to return. -//! \param pui8MACAddr is the pointer to the location in which to store the -//! array of MAC-48 address octets. -//! -//! This function reads the currently programmed MAC address into the -//! \e pui8MACAddr buffer. The \e ui32Index parameter defines which of the -//! hardware's MAC addresses to return. The number of MAC addresses supported -//! by the controller may be queried using a call to EMACNumAddrGet(). -//! Index 0 refers to the MAC address of the local node. Other indices are -//! used to define MAC addresses when filtering incoming packets. -//! -//! The address is written to the pui8MACAddr array ordered with the first byte -//! to be transmitted in the first array entry. For example, if the address -//! is written in its usual form with the Organizationally Unique Identifier -//! (OUI) shown first as: -//! -//! AC-DE-48-00-00-80 -//! -//! the data is returned with 0xAC in the first byte of the array, 0xDE in -//! the second, 0x48 in the third and so on. -//! -//! \return None. -// -//***************************************************************************** -void -EMACAddrGet(uint32_t ui32Base, uint32_t ui32Index, uint8_t *pui8MACAddr) -{ - uint32_t ui32Val; - - // - // Parameter sanity check. - // - ASSERT(ui32Index < NUM_MAC_ADDR); - ASSERT(pui8MACAddr); - - // - // Get the first 4 bytes of the MAC address. - // - ui32Val = HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)); - pui8MACAddr[0] = ui32Val & 0xFF; - pui8MACAddr[1] = (ui32Val >> 8) & 0xFF; - pui8MACAddr[2] = (ui32Val >> 16) & 0xFF; - pui8MACAddr[3] = (ui32Val >> 24) & 0xFF; - - // - // Get the last 2 bytes of the MAC address. - // - ui32Val = HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)); - pui8MACAddr[4] = ui32Val & 0xFF; - pui8MACAddr[5] = (ui32Val >> 8) & 0xFF; -} - -//***************************************************************************** -// -//! Returns the number of MAC addresses supported by the Ethernet controller. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! -//! This function may be used to determine the number of MAC addresses that the -//! given controller supports. MAC address slots may be used when performing -//! perfect (rather than hash table) filtering of packets. -//! -//! \return Returns the number of supported MAC addresses. -// -//***************************************************************************** -uint32_t -EMACNumAddrGet(uint32_t ui32Base) -{ - // - // The only Ethernet controller on Snowflake supports 4 MAC addresses. - // - return(NUM_MAC_ADDR); -} - -//***************************************************************************** -// -//! Sets filtering parameters associated with one of the configured MAC -//! addresses. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Index is the index of the MAC address slot for which the filter -//! is to be set. -//! \param ui32Config sets the filter parameters for the given MAC address. -//! -//! This function sets filtering parameters associated with one of the MAC -//! address slots that the controller supports. This configuration is used -//! when perfect filtering (rather than hash table filtering) is selected. -//! -//! Valid values for \e ui32Index are from 1 to (number of MAC address -//! slots - 1). The number of supported MAC address slots may be found by -//! calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does -//! not have filtering parameters associated with it. -//! -//! The \e ui32Config parameter determines how the given MAC address is used -//! when filtering incoming Ethernet frames. It is comprised of a logical OR -//! of the fields: -//! -//! - \b EMAC_FILTER_ADDR_ENABLE indicates that this MAC address is enabled -//! and should be used when performing perfect filtering. If this flag is -//! absent, the MAC address at the given index is disabled and is not used -//! in filtering. -//! - \b EMAC_FILTER_SOURCE_ADDR indicates that the MAC address at the given -//! index is compared to the source address of incoming frames while -//! performing perfect filtering. If absent, the MAC address is compared -//! against the destination address. -//! - \b EMAC_FILTER_MASK_BYTE_6 indicates that the MAC should ignore the -//! sixth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_5 indicates that the MAC should ignore the -//! fifth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_4 indicates that the MAC should ignore the -//! fourth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_3 indicates that the MAC should ignore the -//! third byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_2 indicates that the MAC should ignore the -//! second byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_1 indicates that the MAC should ignore the -//! first byte of the source or destination address when filtering. -//! -//! \return None. -// -//***************************************************************************** -void -EMACAddrFilterSet(uint32_t ui32Base, uint32_t ui32Index, uint32_t ui32Config) -{ - uint32_t ui32Val; - - // - // Parameter sanity check. - // - ASSERT(ui32Index < NUM_MAC_ADDR); - ASSERT((ui32Config & ~(EMAC_FILTER_BYTE_MASK_M | - EMAC_FILTER_ADDR_ENABLE | - EMAC_FILTER_SOURCE_ADDR)) == 0); - ASSERT(ui32Index); - - // - // Set the filter configuration for a particular MAC address. - // - HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) = - (HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & 0xFFFF) | ui32Config; - - // - // Read and rewrite the low half of the MAC address register to ensure - // that the upper half's data is latched. - // - ui32Val = HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)); - HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)) = ui32Val; -} - -//***************************************************************************** -// -//! Gets filtering parameters associated with one of the configured MAC -//! addresses. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Index is the index of the MAC address slot for which the filter -//! is to be queried. -//! -//! This function returns filtering parameters associated with one of the MAC -//! address slots that the controller supports. This configuration is used -//! when perfect filtering (rather than hash table filtering) is selected. -//! -//! Valid values for \e ui32Index are from 1 to (number of MAC address -//! slots - 1). The number of supported MAC address slots may be found by -//! calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does -//! not have filtering parameters associated with it. -//! -//! \return Returns the filter configuration as the logical OR of the -//! following labels: -//! -//! - \b EMAC_FILTER_ADDR_ENABLE indicates that this MAC address is enabled -//! and is used when performing perfect filtering. If this flag is absent, -//! the MAC address at the given index is disabled and is not used in -//! filtering. -//! - \b EMAC_FILTER_SOURCE_ADDR indicates that the MAC address at the given -//! index is compared to the source address of incoming frames while performing -//! perfect filtering. If absent, the MAC address is compared against the -//! destination address. -//! - \b EMAC_FILTER_MASK_BYTE_6 indicates that the MAC ignores the -//! sixth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_5 indicates that the MAC ignores the -//! fifth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_4 indicates that the MAC ignores the -//! fourth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_3 indicates that the MAC ignores the -//! third byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_2 indicates that the MAC ignores the -//! second byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_1 indicates that the MAC ignores the -//! first byte of the source or destination address when filtering. -// -//***************************************************************************** -uint32_t -EMACAddrFilterGet(uint32_t ui32Base, uint32_t ui32Index) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Index < NUM_MAC_ADDR); - ASSERT(ui32Index); - - // - // Read and return the filter settings for the requested MAC address slot. - // - return(HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & - (EMAC_FILTER_BYTE_MASK_M | EMAC_FILTER_ADDR_ENABLE | - EMAC_FILTER_SOURCE_ADDR)); -} - -//***************************************************************************** -// -//! Sets options related to Ethernet frame filtering. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32FilterOpts is a logical OR of flags defining the required MAC -//! address filtering options. -//! -//! This function allows various filtering options to be defined and allows -//! an application to control which frames are received based on various -//! criteria related to the frame source and destination MAC addresses or VLAN -//! tagging. -//! -//! The \e ui32FilterOpts parameter is a logical OR of any of the following -//! flags: -//! -//! - \b EMAC_FRMFILTER_RX_ALL configures the MAC to pass all received frames -//! regardless of whether or not they pass any address filter that is -//! configured. The receive status word in the relevant DMA descriptor is -//! updated to indicate whether the configured filter passed or failed for -//! the frame. -//! - \b EMAC_FRMFILTER_VLAN configures the MAC to drop any frames that do -//! not pass the VLAN tag comparison. -//! - \b EMAC_FRMFILTER_HASH_AND_PERFECT configures the MAC to filter frames -//! based on both any perfect filters set and the hash filter if enabled using -//! \b EMAC_FRMFILTER_HASH_UNICAST or \b EMAC_FRMFILTER_HASH_MULTICAST. In -//! this case, only if both filters fail is the packet rejected. If this -//! option is absent, only one of the filter types is used, as controlled by -//! \b EMAC_FRMFILTER_HASH_UNICAST and \b EMAC_FRMFILTER_HASH_MULTICAST -//! for unicast and multicast frames respectively. -//! - \b EMAC_FRMFILTER_SADDR configures the MAC to drop received frames -//! when the source address field in the frame does not match the values -//! programmed into the enabled SA registers. -//! - \b EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering. -//! When this option is specified, frames for which the SA does not match the -//! SA registers are marked as passing the source address filter. -//! - \b EMAC_FRMFILTER_BROADCAST configures the MAC to discard all incoming -//! broadcast frames. -//! - \b EMAC_FRMFILTER_PASS_MULTICAST configures the MAC to pass all -//! incoming frames with multicast destinations addresses. -//! - \b EMAC_FRMFILTER_INV_DADDR inverts the sense of the destination -//! address filtering for both unicast and multicast frames. -//! - \b EMAC_FRMFILTER_HASH_MULTICAST enables destination address filtering -//! of received multicast frames using the hash table. If absent, perfect -//! destination address filtering is used. If used in conjunction with \b -//! EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter -//! should be used for incoming multicast packets along with the perfect -//! filter. -//! - \b EMAC_FRMFILTER_HASH_UNICAST enables destination address filtering -//! of received unicast frames using the hash table. If absent, perfect -//! destination address filtering is used. If used in conjunction with \b -//! EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter -//! should be used for incoming unicast packets along with the perfect filter. -//! - \b EMAC_FRMFILTER_PROMISCUOUS configures the MAC to operate in -//! promiscuous mode where all received frames are passed to the application -//! and the SA and DA filter status bits of the descriptor receive status word -//! are always cleared. -//! -//! Control frame filtering may be configured by ORing one of the following -//! values into \e ui32FilterOpts: -//! -//! - \b EMAC_FRMFILTER_PASS_NO_CTRL prevents any control frame from reaching -//! the application. -//! - \b EMAC_FRMFILTER_PASS_NO_PAUSE passes all control frames other than -//! PAUSE even if they fail the configured address filter. -//! - \b EMAC_FRMFILTER_PASS_ALL_CTRL passes all control frames, including -//! PAUSE even if they fail the configured address filter. -//! - \b EMAC_FRMFILTER_PASS_ADDR_CTRL passes all control frames only if they -//! pass the configured address filter. -//! -//! \return None. -// -//***************************************************************************** -void -EMACFrameFilterSet(uint32_t ui32Base, uint32_t ui32FilterOpts) -{ - ASSERT((ui32FilterOpts & ~VALID_FRMFILTER_FLAGS) == 0); - - // - // Set the Ethernet MAC frame filter according to the flags passed. - // - HWREG(ui32Base + EMAC_O_FRAMEFLTR) = - ((HWREG(ui32Base + EMAC_O_FRAMEFLTR) & ~VALID_FRMFILTER_FLAGS) | - ui32FilterOpts); -} - -//***************************************************************************** -// -//! Returns the current Ethernet frame filtering settings. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be called to retrieve the frame filtering configuration -//! set using a prior call to EMACFrameFilterSet(). -//! -//! \return Returns a value comprising the logical OR of various flags -//! indicating the frame filtering options in use. Possible flags are: -//! -//! - \b EMAC_FRMFILTER_RX_ALL indicates that the MAC to is configured to -//! pass all received frames regardless of whether or not they pass any -//! address filter that is configured. The receive status word in the -//! relevant DMA descriptor is updated to indicate whether the configured -//! filter passed or failed for the frame. -//! - \b EMAC_FRMFILTER_VLAN indicates that the MAC is configured to drop any -//! frames which do not pass the VLAN tag comparison. -//! - \b EMAC_FRMFILTER_HASH_AND_PERFECT indicates that the MAC is configured -//! to pass frames if they match either the hash filter or the perfect filter. -//! If this flag is absent, frames passing based on the result of a single -//! filter, the perfect filter if \b EMAC_FRMFILTER_HASH_MULTICAST or -//! \b EMAC_FRMFILTER_HASH_UNICAST are clear or the hash filter otherwise. -//! - \b EMAC_FRMFILTER_SADDR indicates that the MAC is configured to drop -//! received frames when the source address field in the frame does not match -//! the values programmed into the enabled SA registers. -//! - \b EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering. -//! When this option is specified, frames for which the SA does not match the -//! SA registers are marked as passing the source address filter. -//! - \b EMAC_FRMFILTER_BROADCAST indicates that the MAC is configured to -//! discard all incoming broadcast frames. -//! - \b EMAC_FRMFILTER_PASS_MULTICAST indicates that the MAC is configured -//! to pass all incoming frames with multicast destinations addresses. -//! - \b EMAC_FRMFILTER_INV_DADDR indicates that the sense of the destination -//! address filtering for both unicast and multicast frames is inverted. -//! - \b EMAC_FRMFILTER_HASH_MULTICAST indicates that destination address -//! filtering of received multicast frames is enabled using the hash table. If -//! absent, perfect destination address filtering is used. If used in -//! conjunction with \b EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates -//! that the hash filter should be used for incoming multicast packets along -//! with the perfect filter. -//! - \b EMAC_FRMFILTER_HASH_UNICAST indicates that destination address -//! filtering of received unicast frames is enabled using the hash table. If -//! absent, perfect destination address filtering is used. If used in -//! conjunction with \b EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates -//! that the hash filter should be used for incoming unicast packets along with -//! the perfect filter. -//! - \b EMAC_FRMFILTER_PROMISCUOUS indicates that the MAC is configured to -//! operate in promiscuous mode where all received frames are passed to the -//! application and the SA and DA filter status bits of the descriptor receive -//! status word are always cleared. -//! -//! Control frame filtering configuration is indicated by one of the following -//! values which may be extracted from the returned value using the mask -//! \b EMAC_FRMFILTER_PASS_MASK: -//! -//! - \b EMAC_FRMFILTER_PASS_NO_CTRL prevents any control frame from reaching -//! the application. -//! - \b EMAC_FRMFILTER_PASS_NO_PAUSE passes all control frames other than -//! PAUSE even if they fail the configured address filter. -//! - \b EMAC_FRMFILTER_PASS_ALL_CTRL passes all control frames, including -//! PAUSE even if they fail the configured address filter. -//! - \b EMAC_FRMFILTER_PASS_ADDR_CTRL passes all control frames only if they -//! pass the configured address filter. -// -//***************************************************************************** -uint32_t -EMACFrameFilterGet(uint32_t ui32Base) -{ - // - // Return the current MAC frame filter setting. - // - return(HWREG(ui32Base + EMAC_O_FRAMEFLTR) & VALID_FRMFILTER_FLAGS); -} - -//***************************************************************************** -// -//! Sets the MAC address hash filter table. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32HashHi is the upper 32 bits of the current 64-bit hash filter -//! table to set. -//! \param ui32HashLo is the lower 32 bits of the current 64-bit hash filter -//! table to set. -//! -//! This function may be used to set the current 64-bit hash filter table -//! used by the MAC to filter incoming packets when hash filtering is enabled. -//! Hash filtering is enabled by passing \b EMAC_FRMFILTER_HASH_UNICAST -//! and/or \b EMAC_FRMFILTER_HASH_MULTICAST in the \e ui32FilterOpts parameter -//! to EMACFrameFilterSet(). The current hash filter may be retrieved -//! by calling EMACHashFilterGet(). -//! -//! Hash table filtering allows many different MAC addresses to be filtered -//! simultaneously at the cost of some false-positive results (in the form of -//! packets passing the filter when their MAC address was not one of those -//! required). A CRC of the packet source or destination MAC address is -//! calculated and the bottom 6 bits are used as a bit index into the 64-bit -//! hash filter table. If the bit in the hash table is set, the filter is -//! considered to have passed. If the bit is clear, the filter fails and the -//! packet is rejected (assuming normal rather than inverse filtering is -//! configured). -//! -//! \return None. -// -//***************************************************************************** -void -EMACHashFilterSet(uint32_t ui32Base, uint32_t ui32HashHi, uint32_t ui32HashLo) -{ - // Set the hash table with the values provided. - HWREG(ui32Base + EMAC_O_HASHTBLL) = ui32HashLo; - HWREG(ui32Base + EMAC_O_HASHTBLH) = ui32HashHi; -} - -//***************************************************************************** -// -//! Returns the current MAC address hash filter table. -//! -//! \param ui32Base is the base address of the controller. -//! \param pui32HashHi points to storage to be written with the upper 32 bits -//! of the current 64-bit hash filter table. -//! \param pui32HashLo points to storage to be written with the lower 32 bits -//! of the current 64-bit hash filter table. -//! -//! This function may be used to retrieve the current 64-bit hash filter table -//! from the MAC prior to making changes and setting the new hash filter via a -//! call to EMACHashFilterSet(). -//! -//! Hash table filtering allows many different MAC addresses to be filtered -//! simultaneously at the cost of some false-positive results in the form of -//! packets passing the filter when their MAC address was not one of those -//! required. A CRC of the packet source or destination MAC address is -//! calculated and the bottom 6 bits are used as a bit index into the 64-bit -//! hash filter table. If the bit in the hash table is set, the filter is -//! considered to have passed. If the bit is clear, the filter fails and the -//! packet is rejected (assuming normal rather than inverse filtering is -//! configured). -//! -//! \return None. -// -//***************************************************************************** -void -EMACHashFilterGet(uint32_t ui32Base, uint32_t *pui32HashHi, - uint32_t *pui32HashLo) -{ - ASSERT(pui32HashHi); - ASSERT(pui32HashLo); - - // - // Get the current hash table values. - // - *pui32HashLo = HWREG(ui32Base + EMAC_O_HASHTBLL); - *pui32HashHi = HWREG(ui32Base + EMAC_O_HASHTBLH); -} - -//***************************************************************************** -// -//! Returns the bit number to set in the MAC hash filter corresponding to a -//! given MAC address. -//! -//! \param pui8MACAddr points to a buffer containing the 6-byte MAC address -//! for which the hash filter bit is to be determined. -//! -//! This function may be used to determine which bit in the MAC address hash -//! filter to set to describe a given 6-byte MAC address. The returned value is -//! a 6-bit number where bit 5 indicates which of the two hash table words is -//! affected and the bottom 5 bits indicate the bit number to set within that -//! word. For example, if 0x22 (100010b) is returned, this indicates that bit -//! 2 of word 1 (\e ui32HashHi as passed to EMACHashFilterSet()) must be set -//! to describe the passed MAC address. -//! -//! \return Returns the bit number to set in the MAC hash table to describe the -//! passed MAC address. -// -//***************************************************************************** -uint32_t -EMACHashFilterBitCalculate(uint8_t *pui8MACAddr) -{ - uint32_t ui32CRC, ui32Mask, ui32Loop; - - // - // Parameter sanity check. - // - ASSERT(pui8MACAddr); - - // - // Calculate the CRC for the MAC address. - // - ui32CRC = Crc32(0xFFFFFFFF, pui8MACAddr, 6); - ui32CRC ^= 0xFFFFFFFF; - - // - // Determine the hash bit to use from the calculated CRC. This is the - // top 6 bits of the reversed CRC (or the bottom 6 bits of the calculated - // CRC with the bit order of those 6 bits reversed). - // - ui32Mask = 0; - - // - // Reverse the order of the bottom 6 bits of the calculated CRC. - // - for(ui32Loop = 0; ui32Loop < 6; ui32Loop++) - { - ui32Mask <<= 1; - ui32Mask |= (ui32CRC & 1); - ui32CRC >>= 1; - } - - // - // Return the final hash table bit index. - // - return(ui32Mask); -} - -//***************************************************************************** -// -//! Sets the receive interrupt watchdog timer period. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param ui8Timeout is the desired timeout expressed as a number of 256 -//! system clock periods. -//! -//! This function configures the receive interrupt watchdog timer. -//! The \e uiTimeout parameter specifies the number of 256 system clock periods -//! that elapse before the timer expires. In cases where the DMA has -//! transferred a frame using a descriptor that has -//! \b DES1_RX_CTRL_DISABLE_INT set, the watchdog causes a receive -//! interrupt to be generated when it times out. The watchdog timer is reset -//! whenever a packet is transferred to memory using a DMA descriptor that -//! does not disable the receive interrupt. -//! -//! To disable the receive interrupt watchdog function, set \e ui8Timeout to 0. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout) -{ - // - // Set the receive interrupt watchdog timeout period. - // - HWREG(ui32Base + EMAC_O_RXINTWDT) = (uint32_t)ui8Timeout; -} - -//***************************************************************************** -// -//! Returns the current Ethernet MAC status. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! -//! This function returns information on the current status of all the main -//! modules in the MAC transmit and receive data paths. -//! -//! \return Returns the current MAC status as a logical OR of any of the -//! following flags: -//! -//! - \b EMAC_STATUS_TX_NOT_EMPTY -//! - \b EMAC_STATUS_TX_WRITING_FIFO -//! - \b EMAC_STATUS_TX_PAUSED -//! - \b EMAC_STATUS_MAC_NOT_IDLE -//! - \b EMAC_STATUS_RWC_ACTIVE -//! - \b EMAC_STATUS_RPE_ACTIVE -//! -//! The transmit frame controller status can be extracted from the returned -//! value by ANDing with \b EMAC_STATUS_TFC_STATE_MASK and is one of the -//! following: -//! -//! - \b EMAC_STATUS_TFC_STATE_IDLE -//! - \b EMAC_STATUS_TFC_STATE_WAITING -//! - \b EMAC_STATUS_TFC_STATE_PAUSING -//! - \b EMAC_STATUS_TFC_STATE_WRITING -//! -//! The transmit FIFO read controller status can be extracted from the returned -//! value by ANDing with \b EMAC_STATUS_TRC_STATE_MASK and is one of the -//! following: -//! -//! - \b EMAC_STATUS_TRC_STATE_IDLE -//! - \b EMAC_STATUS_TRC_STATE_READING -//! - \b EMAC_STATUS_TRC_STATE_WAITING -//! - \b EMAC_STATUS_TRC_STATE_STATUS -//! -//! The current receive FIFO levels can be extracted from the returned value -//! by ANDing with \b EMAC_STATUS_RX_FIFO_LEVEL_MASK and is one of the -//! following: -//! -//! - \b EMAC_STATUS_RX_FIFO_EMPTY indicating that the FIFO is empty. -//! - \b EMAC_STATUS_RX_FIFO_BELOW indicating that the FIFO fill level is -//! below the flow-control deactivate threshold. -//! - \b EMAC_STATUS_RX_FIFO_ABOVE indicating that the FIFO fill level is -//! above the flow-control activate threshold. -//! - \b EMAC_STATUS_RX_FIFO_FULL indicating that the FIFO is full. -//! -//! The current receive FIFO state can be extracted from the returned value -//! by ANDing with \b EMAC_STATUS_RX_FIFO_STATE_MASK and is one of the -//! following: -//! -//! - \b EMAC_STATUS_RX_FIFO_IDLE -//! - \b EMAC_STATUS_RX_FIFO_READING -//! - \b EMAC_STATUS_RX_FIFO_STATUS -//! - \b EMAC_STATUS_RX_FIFO_FLUSHING -// -//***************************************************************************** -uint32_t -EMACStatusGet(uint32_t ui32Base) -{ - // - // Read and return the MAC status register content. - // - return(HWREG(ui32Base + EMAC_O_STATUS)); -} - -//***************************************************************************** -// -//! Orders the MAC DMA controller to attempt to acquire the next transmit -//! descriptor. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! -//! This function must be called to restart the transmitter if it has been -//! suspended due to the current transmit DMA descriptor being owned by the -//! host. Once the application writes new values to the descriptor and marks -//! it as being owned by the MAC DMA, this function causes the hardware to -//! attempt to acquire the descriptor and start transmission of the new -//! data. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTxDMAPollDemand(uint32_t ui32Base) -{ - // - // Any write to the MACTXPOLLD register causes the transmit DMA to attempt - // to resume. - // - HWREG(ui32Base + EMAC_O_TXPOLLD) = 0; -} - -//***************************************************************************** -// -//! Orders the MAC DMA controller to attempt to acquire the next receive -//! descriptor. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! -//! This function must be called to restart the receiver if it has been -//! suspended due to the current receive DMA descriptor being owned by the -//! host. Once the application reads any data from the descriptor and marks -//! it as being owned by the MAC DMA, this function causes the hardware to -//! attempt to acquire the descriptor before writing the next received packet -//! into its buffer(s). -//! -//! \return None. -// -//***************************************************************************** -void -EMACRxDMAPollDemand(uint32_t ui32Base) -{ - // - // Any write to the MACRXPOLLD register causes the receive DMA to attempt - // to resume. - // - HWREG(ui32Base + EMAC_O_RXPOLLD) = 0; -} - -//***************************************************************************** -// -//! Sets the DMA receive descriptor list pointer. -//! -//! \param ui32Base is the base address of the controller. -//! \param pDescriptor points to the first DMA descriptor in the list to -//! be passed to the receive DMA engine. -//! -//! This function sets the Ethernet MAC's receive DMA descriptor list pointer. -//! The \e pDescriptor pointer must point to one or more descriptor -//! structures. -//! -//! When multiple descriptors are provided, they can be either chained or -//! unchained. Chained descriptors are indicated by setting the -//! \b DES0_TX_CTRL_CHAINED or \b DES1_RX_CTRL_CHAINED bit in the relevant -//! word of the transmit or receive descriptor. If this bit is clear, -//! unchained descriptors are assumed. -//! -//! Chained descriptors use a link pointer in each descriptor to -//! point to the next descriptor in the chain. -//! -//! Unchained descriptors are assumed to be contiguous in memory with a -//! consistent offset between the start of one descriptor and the next. -//! If unchained descriptors are used, the \e pvLink field in the descriptor -//! becomes available to store a second buffer pointer, allowing each -//! descriptor to point to two buffers rather than one. In this case, -//! the \e ui32DescSkipSize parameter to EMACInit() must previously have -//! been set to the number of words between the end of one descriptor and -//! the start of the next. This value must be 0 in cases where a packed array -//! of \b tEMACDMADescriptor structures is used. If the application wishes to -//! add new state fields to the end of the descriptor structure, the skip size -//! should be set to accommodate the newly sized structure. -//! -//! Applications are responsible for initializing all descriptor fields -//! appropriately before passing the descriptor list to the hardware. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRxDMADescriptorListSet(uint32_t ui32Base, tEMACDMADescriptor *pDescriptor) -{ - // - // Parameter sanity check. - // - ASSERT(pDescriptor); - ASSERT(((uint32_t)pDescriptor & 3) == 0); - - // - // Write the supplied address to the MACRXDLADDR register. - // - HWREG(ui32Base + EMAC_O_RXDLADDR) = (uint32_t)pDescriptor; -} - -//***************************************************************************** -// -//! Returns a pointer to the start of the DMA receive descriptor list. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function returns a pointer to the head of the Ethernet MAC's receive -//! DMA descriptor list. This value corresponds to the pointer originally set -//! using a call to EMACRxDMADescriptorListSet(). -//! -//! \return Returns a pointer to the start of the DMA receive descriptor list. -// -//***************************************************************************** -tEMACDMADescriptor * -EMACRxDMADescriptorListGet(uint32_t ui32Base) -{ - // - // Return the current receive DMA descriptor list pointer. - // - return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_RXDLADDR)); -} - -//***************************************************************************** -// -//! Returns the current DMA receive descriptor pointer. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function returns a pointer to the current Ethernet receive descriptor -//! read by the DMA. -//! -//! \return Returns a pointer to the start of the current receive DMA -//! descriptor. -// -//***************************************************************************** -tEMACDMADescriptor * -EMACRxDMACurrentDescriptorGet(uint32_t ui32Base) -{ - // - // Return the address of the current receive descriptor written by the DMA. - // - return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_HOSRXDESC)); -} - -//***************************************************************************** -// -//! Returns the current DMA receive buffer pointer. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be called to determine which buffer the receive DMA -//! engine is currently writing to. -//! -//! \return Returns the receive buffer address currently being written by -//! the DMA engine. -// -//***************************************************************************** -uint8_t * -EMACRxDMACurrentBufferGet(uint32_t ui32Base) -{ - // - // Return the receive buffer address currently being written by the DMA. - // - return((uint8_t *)HWREG(ui32Base + EMAC_O_HOSRXBA)); -} - -//***************************************************************************** -// -//! Sets the DMA transmit descriptor list pointer. -//! -//! \param ui32Base is the base address of the controller. -//! \param pDescriptor points to the first DMA descriptor in the list to -//! be passed to the transmit DMA engine. -//! -//! This function sets the Ethernet MAC's transmit DMA descriptor list pointer. -//! The \e pDescriptor pointer must point to one or more descriptor -//! structures. -//! -//! When multiple descriptors are provided, they can be either chained or -//! unchained. Chained descriptors are indicated by setting the -//! \b DES0_TX_CTRL_CHAINED or \b DES1_RX_CTRL_CHAINED bit in the relevant -//! word of the transmit or receive descriptor. If this bit is clear, -//! unchained descriptors are assumed. -//! -//! Chained descriptors use a link pointer in each descriptor to -//! point to the next descriptor in the chain. -//! -//! Unchained descriptors are assumed to be contiguous in memory with a -//! consistent offset between the start of one descriptor and the next. -//! If unchained descriptors are used, the \e pvLink field in the descriptor -//! becomes available to store a second buffer pointer, allowing each -//! descriptor to point to two buffers rather than one. In this case, -//! the \e ui32DescSkipSize parameter to EMACInit() must previously have -//! been set to the number of words between the end of one descriptor and -//! the start of the next. This value must be 0 in cases where a packed array -//! of \b tEMACDMADescriptor structures is used. If the application wishes to -//! add new state fields to the end of the descriptor structure, the skip size -//! should be set to accommodate the newly sized structure. -//! -//! Applications are responsible for initializing all descriptor fields -//! appropriately before passing the descriptor list to the hardware. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTxDMADescriptorListSet(uint32_t ui32Base, tEMACDMADescriptor *pDescriptor) -{ - // - // Parameter sanity check. - // - ASSERT(pDescriptor); - ASSERT(((uint32_t)pDescriptor & 3) == 0); - - // - // Write the supplied address to the MACTXDLADDR register. - // - HWREG(ui32Base + EMAC_O_TXDLADDR) = (uint32_t)pDescriptor; -} - -//***************************************************************************** -// -//! Returns a pointer to the start of the DMA transmit descriptor list. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function returns a pointer to the head of the Ethernet MAC's transmit -//! DMA descriptor list. This value corresponds to the pointer originally set -//! using a call to EMACTxDMADescriptorListSet(). -//! -//! \return Returns a pointer to the start of the DMA transmit descriptor list. -// -//***************************************************************************** -tEMACDMADescriptor * -EMACTxDMADescriptorListGet(uint32_t ui32Base) -{ - // - // Return the current transmit DMA descriptor list pointer. - // - return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_TXDLADDR)); -} - -//***************************************************************************** -// -//! Returns the current DMA transmit descriptor pointer. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function returns a pointer to the current Ethernet transmit descriptor -//! read by the DMA. -//! -//! \return Returns a pointer to the start of the current transmit DMA -//! descriptor. -// -//***************************************************************************** -tEMACDMADescriptor * -EMACTxDMACurrentDescriptorGet(uint32_t ui32Base) -{ - // - // Return the address of the current transmit descriptor read by the DMA. - // - return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_HOSTXDESC)); -} - -//***************************************************************************** -// -//! Returns the current DMA transmit buffer pointer. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be called to determine which buffer the transmit DMA -//! engine is currently reading from. -//! -//! \return Returns the transmit buffer address currently being read by the -//! DMA engine. -// -//***************************************************************************** -uint8_t * -EMACTxDMACurrentBufferGet(uint32_t ui32Base) -{ - // - // Return the transmit buffer address currently being read by the DMA. - // - return((uint8_t *)HWREG(ui32Base + EMAC_O_HOSTXBA)); -} - -//***************************************************************************** -// -//! Returns the current states of the Ethernet MAC transmit and receive DMA -//! engines. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be used to query the current states of the transmit and -//! receive DMA engines. The return value contains two fields, one providing -//! the transmit state and the other the receive state. Macros -//! \b EMAC_TX_DMA_STATE() and \b EMAC_RX_DMA_STATE() may be used to -//! extract these fields from the returned value. Alternatively, masks -//! \b EMAC_DMA_TXSTAT_MASK and \b EMAC_DMA_RXSTAT_MASK may be used -//! directly to mask out the individual states from the returned value. -//! -//! \return Returns the states of the transmit and receive DMA engines. These -//! states are ORed together into a single word containing one of: -//! -//! - \b EMAC_DMA_TXSTAT_STOPPED indicating that the transmit engine is -//! stopped. -//! - \b EMAC_DMA_TXSTAT_RUN_FETCH_DESC indicating that the transmit engine -//! is fetching the next descriptor. -//! - \b EMAC_DMA_TXSTAT_RUN_WAIT_STATUS indicating that the transmit engine -//! is waiting for status from the MAC. -//! - \b EMAC_DMA_TXSTAT_RUN_READING indicating that the transmit engine is -//! currently transferring data from memory to the MAC transmit FIFO. -//! - \b EMAC_DMA_TXSTAT_RUN_CLOSE_DESC indicating that the transmit engine -//! is closing the descriptor after transmission of the buffer data. -//! - \b EMAC_DMA_TXSTAT_TS_WRITE indicating that the transmit engine is -//! currently writing timestamp information to the descriptor. -//! - \b EMAC_DMA_TXSTAT_SUSPENDED indicating that the transmit engine is -//! suspended due to the next descriptor being unavailable (owned by the host) -//! or a transmit buffer underflow. -//! -//! and one of: -//! -//! - \b EMAC_DMA_RXSTAT_STOPPED indicating that the receive engine is -//! stopped. -//! - \b EMAC_DMA_RXSTAT_RUN_FETCH_DESC indicating that the receive engine -//! is fetching the next descriptor. -//! - \b EMAC_DMA_RXSTAT_RUN_WAIT_PACKET indicating that the receive engine -//! is waiting for the next packet. -//! - \b EMAC_DMA_RXSTAT_SUSPENDED indicating that the receive engine is -//! suspended due to the next descriptor being unavailable. -//! - \b EMAC_DMA_RXSTAT_RUN_CLOSE_DESC indicating that the receive engine -//! is closing the descriptor after receiving a buffer of data. -//! - \b EMAC_DMA_RXSTAT_TS_WRITE indicating that the transmit engine is -//! currently writing timestamp information to the descriptor. -//! - \b EMAC_DMA_RXSTAT_RUN_RECEIVING indicating that the receive engine is -//! currently transferring data from the MAC receive FIFO to memory. -//! -//! Additionally, a DMA bus error may be signaled using \b EMAC_DMA_ERROR. -//! If this flag is present, the source of the error is identified using one -//! of the following values which may be extracted from the return value using -//! \b EMAC_DMA_ERR_MASK: -//! -//! - \b EMAC_DMA_ERR_RX_DATA_WRITE indicates that an error occurred when -//! writing received data to memory. -//! - \b EMAC_DMA_ERR_TX_DATA_READ indicates that an error occurred when -//! reading data from memory for transmission. -//! - \b EMAC_DMA_ERR_RX_DESC_WRITE indicates that an error occurred when -//! writing to the receive descriptor. -//! - \b EMAC_DMA_ERR_TX_DESC_WRITE indicates that an error occurred when -//! writing to the transmit descriptor. -//! - \b EMAC_DMA_ERR_RX_DESC_READ indicates that an error occurred when -//! reading the receive descriptor. -//! - \b EMAC_DMA_ERR_TX_DESC_READ indicates that an error occurred when -//! reading the transmit descriptor. -// -//***************************************************************************** -uint32_t -EMACDMAStateGet(uint32_t ui32Base) -{ - // - // Return the status of the DMA channels. - // - return(HWREG(ui32Base + EMAC_O_DMARIS) & - (EMAC_DMARIS_FBI | EMAC_DMARIS_AE_M | EMAC_DMARIS_RS_M | - EMAC_DMARIS_TS_M)); -} - -//***************************************************************************** -// -//! Flushes the Ethernet controller transmit FIFO. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function flushes any data currently held in the Ethernet transmit -//! FIFO. Data that has already been passed to the MAC for transmission is -//! transmitted, possibly resulting in a transmit underflow or runt frame -//! transmission. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTxFlush(uint32_t ui32Base) -{ - // - // Check to make sure that the FIFO is not already empty. - // - if(HWREG(ui32Base + EMAC_O_STATUS) & EMAC_STATUS_TXFE) - { - // - // Flush the transmit FIFO since it is not currently empty. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_FTF; - - // - // Wait for the flush to complete. - // - while(HWREG(ui32Base + EMAC_O_DMAOPMODE) & EMAC_DMAOPMODE_FTF) - { - } - } -} - -//***************************************************************************** -// -//! Enables the Ethernet controller transmitter. -//! -//! \param ui32Base is the base address of the controller. -//! -//! When starting operations on the Ethernet interface, this function should -//! be called to enable the transmitter after all configuration has been -//! completed. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTxEnable(uint32_t ui32Base) -{ - // - // Enable the MAC transmit path in the opmode register. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_ST; - - // - // Enable transmission in the MAC configuration register. - // - HWREG(ui32Base + EMAC_O_CFG) |= EMAC_CFG_TE; -} - -//***************************************************************************** -// -//! Disables the Ethernet controller transmitter. -//! -//! \param ui32Base is the base address of the controller. -//! -//! When terminating operations on the Ethernet interface, this function should -//! be called. This function disables the transmitter. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTxDisable(uint32_t ui32Base) -{ - // - // Disable transmission in the MAC configuration register. - // - HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_TE; - - // - // Disable the MAC transmit path in the opmode register. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_ST; -} - -//***************************************************************************** -// -//! Enables the Ethernet controller receiver. -//! -//! \param ui32Base is the base address of the controller. -//! -//! When starting operations on the Ethernet interface, this function should -//! be called to enable the receiver after all configuration has been -//! completed. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRxEnable(uint32_t ui32Base) -{ - // - // Enable the MAC receive path. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_SR; - - // - // Enable receive in the MAC configuration register. - // - HWREG(ui32Base + EMAC_O_CFG) |= EMAC_CFG_RE; -} - -//***************************************************************************** -// -//! Disables the Ethernet controller receiver. -//! -//! \param ui32Base is the base address of the controller. -//! -//! When terminating operations on the Ethernet interface, this function should -//! be called. This function disables the receiver. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRxDisable(uint32_t ui32Base) -{ - // - // Disable reception in the MAC configuration register. - // - HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_RE; - - // - // Disable the MAC receive path. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_SR; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for an Ethernet interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled Ethernet interrupts occur. -//! -//! This function sets the handler to be called when the Ethernet interrupt -//! occurs. This function enables the global interrupt in the interrupt -//! controller; specific Ethernet interrupts must be enabled via -//! EMACIntEnable(). It is the interrupt handler's responsibility to clear -//! the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -EMACIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(pfnHandler != 0); - - // - // Register the interrupt handler. - // - IntRegister(INT_EMAC0_TM4C129, pfnHandler); - - // - // Enable the Ethernet interrupt. - // - IntEnable(INT_EMAC0_TM4C129); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for an Ethernet interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function unregisters the interrupt handler. This function disables -//! the global interrupt in the interrupt controller so that the interrupt -//! handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -EMACIntUnregister(uint32_t ui32Base) -{ - // - // Disable the interrupt. - // - IntDisable(INT_EMAC0_TM4C129); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_EMAC0_TM4C129); -} - -//***************************************************************************** -// -//! Enables individual Ethernet MAC interrupt sources. -//! -//! \param ui32Base is the base address of the Ethernet MAC. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated Ethernet MAC interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state. -//! Software must read and write the appropriate PHY registers to enable and -//! disable particular notifications. -//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the -//! first data buffer of a packet. -//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and -//! that the DMA engine has been disabled. -//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has -//! been fully written from memory into the MAC transmit FIFO. -//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than -//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. -//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered -//! the stopped state. -//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire -//! a buffer. The receive process is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACRxDMAPollDemand(). -//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed -//! and all requested status has been written to the appropriate DMA receive -//! descriptor. -//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an -//! underflow during transmission. The transmit process is suspended. -//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced -//! during reception. -//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and -//! enter the Stopped state. -//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, -//! acquire a buffer. Transmission is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACTxDMAPollDemand(). -//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. -//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has -//! completed and that all requested status has been updated in the descriptor. -//! -//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and -//! \b EMAC_INT_ABNORMAL_INT are enabled automatically by the driver if any -//! of their constituent sources are enabled. Applications do not need to -//! explicitly enable these bits. -//! -//! \note Timestamp-related interrupts from the IEEE 1588 module must be -//! enabled independently by using a call to EMACTimestampTargetIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -EMACIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Parameter sanity check. - // - ASSERT((ui32IntFlags & ~EMAC_MASKABLE_INTS) == 0); - - // - // Enable the normal interrupt if any of its individual sources are - // enabled. - // - if(ui32IntFlags & EMAC_NORMAL_INTS) - { - ui32IntFlags |= EMAC_INT_NORMAL_INT; - } - - // - // Similarly, enable the abnormal interrupt if any of its individual - // sources are enabled. - // - if(ui32IntFlags & EMAC_ABNORMAL_INTS) - { - ui32IntFlags |= EMAC_INT_ABNORMAL_INT; - } - - // - // Set the MAC DMA interrupt mask appropriately if any of the sources - // we've been asked to enable are found in that register. - // - if(ui32IntFlags & ~EMAC_INT_PHY) - { - HWREG(ui32Base + EMAC_O_DMAIM) |= ui32IntFlags & ~EMAC_INT_PHY; - } - - // - // Enable the PHY interrupt if we've been asked to do this. - // - if(ui32IntFlags & EMAC_INT_PHY) - { - HWREG(ui32Base + EMAC_O_EPHYIM) |= EMAC_EPHYIM_INT; - } -} - -//***************************************************************************** -// -//! Disables individual Ethernet MAC interrupt sources. -//! -//! \param ui32Base is the base address of the Ethernet MAC. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated Ethernet MAC interrupt sources. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state. -//! Software must read and write the appropriate PHY registers to enable and -//! disable particular notifications. -//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the -//! first data buffer of a packet. -//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and -//! that the DMA engine has been disabled. -//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has -//! been fully written from memory into the MAC transmit FIFO. -//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than -//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. -//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered -//! the stopped state. -//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire -//! a buffer. The receive process is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACRxDMAPollDemand(). -//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed -//! and all requested status has been written to the appropriate DMA receive -//! descriptor. -//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an -//! underflow during transmission. The transmit process is suspended. -//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced -//! during reception. -//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and -//! enter the Stopped state. -//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, -//! acquire a buffer. Transmission is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACTxDMAPollDemand(). -//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. -//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has -//! completed and that all requested status has been updated in the descriptor. -//! - \b EMAC_INT_TIMESTAMP indicates that an interrupt from the timestamp -//! module has occurred. This precise source of the interrupt can be -//! determined by calling EMACTimestampIntStatus(), which also clears this -//! bit. -//! -//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and -//! \b EMAC_INT_ABNORMAL_INT are disabled automatically by the driver if none -//! of their constituent sources are enabled. Applications do not need to -//! explicitly disable these bits. -//! -//! \note Timestamp-related interrupts from the IEEE 1588 module must be -//! disabled independently by using a call to EMACTimestampTargetIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -EMACIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - uint32_t ui32Mask; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT((ui32IntFlags & ~EMAC_MASKABLE_INTS) == 0); - - // - // Get the current interrupt mask. - // - ui32Mask = HWREG(ui32Base + EMAC_O_DMAIM); - - // - // Clear the requested bits. - // - ui32Mask &= ~(ui32IntFlags & ~EMAC_INT_PHY); - - // - // If none of the normal interrupt sources are enabled, disable the - // normal interrupt. - // - if(!(ui32Mask & EMAC_NORMAL_INTS)) - { - ui32Mask &= ~EMAC_INT_NORMAL_INT; - } - - // - // Similarly, if none of the abnormal interrupt sources are enabled, - // disable the abnormal interrupt. - // - if(!(ui32Mask & EMAC_ABNORMAL_INTS)) - { - ui32Mask &= ~EMAC_INT_ABNORMAL_INT; - } - - // - // Write the new mask back to the hardware. - // - HWREG(ui32Base + EMAC_O_DMAIM) = ui32Mask; - - // - // Disable the PHY interrupt if we've been asked to do this. - // - if(ui32IntFlags & EMAC_INT_PHY) - { - HWREG(ui32Base + EMAC_O_EPHYIM) &= ~EMAC_EPHYIM_INT; - } -} - -//***************************************************************************** -// -//! Gets the current Ethernet MAC interrupt status. -//! -//! \param ui32Base is the base address of the Ethernet MAC. -//! \param bMasked is \b true to return the masked interrupt status or \b false -//! to return the unmasked status. -//! -//! This function returns the interrupt status for the Ethernet MAC. Either -//! the raw interrupt status or the status of interrupts that are allowed -//! to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status as the logical OR of any of -//! the following: -//! -//! - \b EMAC_INT_PHY indicates that the PHY interrupt has occurred. -//! Software must read the relevant PHY interrupt status register to determine -//! the cause. -//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the -//! first data buffer of a packet. -//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and -//! that the DMA engine has been disabled. The cause of the error can be -//! determined by calling EMACDMAStateGet(). -//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has -//! been fully written from memory into the MAC transmit FIFO. -//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than -//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. -//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered -//! the stopped state. -//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire -//! a buffer. The receive process is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACRxDMAPollDemand(). -//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed -//! and all requested status has been written to the appropriate DMA receive -//! descriptor. -//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an -//! underflow during transmission. The transmit process is suspended. -//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced -//! during reception. -//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and -//! enter the Stopped state. -//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, -//! acquire a buffer. Transmission is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACTxDMAPollDemand(). -//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. -//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has -//! completed and that all requested status has been updated in the descriptor. -//! - \b EMAC_INT_NORMAL_INT is a summary interrupt comprising the logical -//! OR of the masked state of \b EMAC_INT_TRANSMIT, \b EMAC_INT_RECEIVE, -//! \b EMAC_INT_TX_NO_BUFFER and \b EMAC_INT_EARLY_RECEIVE. -//! - \b EMAC_INT_ABNORMAL_INT is a summary interrupt comprising the logical -//! OR of the masked state of \b EMAC_INT_TX_STOPPED, \b EMAC_INT_TX_JABBER, -//! \b EMAC_INT_RX_OVERFLOW, \b EMAC_INT_TX_UNDERFLOW, -//! \b EMAC_INT_RX_NO_BUFFER, \b EMAC_INT_RX_STOPPED, -//! \b EMAC_INT_RX_WATCHDOG, \b EMAC_INT_EARLY_TRANSMIT and -//! \b EMAC_INT_BUS_ERROR. -// -//***************************************************************************** -uint32_t -EMACIntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Val, ui32PHYStat; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Get the unmasked interrupt status and clear any unwanted status fields. - // - ui32Val = HWREG(ui32Base + EMAC_O_DMARIS); - ui32Val &= ~(EMAC_DMARIS_AE_M | EMAC_DMARIS_TS_M | EMAC_DMARIS_RS_M); - - // - // This peripheral doesn't have a masked interrupt status register - // so perform the masking manually. Note that only the bottom 16 bits - // of the register can be masked so make sure we take this into account. - // - if(bMasked) - { - ui32Val &= (EMAC_NON_MASKED_INTS | HWREG(ui32Base + EMAC_O_DMAIM)); - } - - // - // Read the PHY interrupt status. - // - if(bMasked) - { - ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYMISC); - } - else - { - ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYRIS); - } - - // - // If the PHY interrupt is reported, add the appropriate flag to the - // return value. - // - if(ui32PHYStat & EMAC_EPHYMISC_INT) - { - ui32Val |= EMAC_INT_PHY; - } - - return(ui32Val); -} - -//***************************************************************************** -// -//! Clears individual Ethernet MAC interrupt sources. -//! -//! \param ui32Base is the base address of the Ethernet MAC. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared. -//! -//! This function disables the indicated Ethernet MAC interrupt sources. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state. -//! Software must read and write the appropriate PHY registers to enable, -//! disable and clear particular notifications. -//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the -//! first data buffer of a packet. -//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and -//! that the DMA engine has been disabled. -//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has -//! been fully written from memory into the MAC transmit FIFO. -//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than -//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. -//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered -//! the stopped state. -//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire -//! a buffer. The receive process is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACRxDMAPollDemand(). -//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed -//! and all requested status has been written to the appropriate DMA receive -//! descriptor. -//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an -//! underflow during transmission. The transmit process is suspended. -//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced -//! during reception. -//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and -//! enter the Stopped state. -//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, -//! acquire a buffer. Transmission is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACTxDMAPollDemand(). -//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. -//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has -//! completed and that all requested status has been updated in the descriptor. -//! -//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and -//! \b EMAC_INT_ABNORMAL_INT are cleared automatically by the driver if any -//! of their constituent sources are cleared. Applications do not need to -//! explicitly clear these bits. -//! -//! \return None. -// -//***************************************************************************** -void -EMACIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Mask in the normal interrupt if one of the sources it relates to is - // specified. - // - if(ui32IntFlags & EMAC_NORMAL_INTS) - { - ui32IntFlags |= EMAC_INT_NORMAL_INT; - } - - // - // Similarly, mask in the abnormal interrupt if one of the sources it - // relates to is specified. - // - if(ui32IntFlags & EMAC_ABNORMAL_INTS) - { - ui32IntFlags |= EMAC_INT_ABNORMAL_INT; - } - - // - // Clear the maskable interrupt sources. We write exactly the value passed - // (with the summary sources added if necessary) but remember that only - // the bottom 17 bits of the register are actually clearable. Only do - // this if some bits are actually set that refer to the DMA interrupt - // sources. - // - if(ui32IntFlags & ~EMAC_INT_PHY) - { - HWREG(ui32Base + EMAC_O_DMARIS) = (ui32IntFlags & ~EMAC_INT_PHY); - } - - // - // Clear the PHY interrupt if we've been asked to do this. - // - if(ui32IntFlags & EMAC_INT_PHY) - { - HWREG(ui32Base + EMAC_O_EPHYMISC) |= EMAC_EPHYMISC_INT; - } -} - -//***************************************************************************** -// -//! Writes to the PHY register. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui8RegAddr is the address of the PHY register to be accessed. -//! \param ui16Data is the data to be written to the PHY register. -//! -//! This function writes the \e ui16Data value to the PHY register specified by -//! \e ui8RegAddr. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr, - uint16_t ui16Data) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - - // - // Make sure the MII is idle. - // - while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) - { - } - - // - // Write the value provided. - // - HWREG(ui32Base + EMAC_O_MIIDATA) = ui16Data; - - // - // Tell the MAC to write the given PHY register. - // - HWREG(ui32Base + EMAC_O_MIIADDR) = - ((HWREG(ui32Base + EMAC_O_MIIADDR) & - EMAC_MIIADDR_CR_M) | (ui8RegAddr << EMAC_MIIADDR_MII_S) | - (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIW | - EMAC_MIIADDR_MIIB); - - // - // Wait for the write to complete. - // - while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) - { - } -} - -//***************************************************************************** -// -//! Reads from a PHY register. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui8RegAddr is the address of the PHY register to be accessed. -//! -//! This function returns the contents of the PHY register specified by -//! \e ui8RegAddr. -//! -//! \return Returns the 16-bit value read from the PHY. -// -//***************************************************************************** -uint16_t -EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr) -{ - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - ASSERT(ui32Base == EMAC0_BASE); - - // - // Make sure the MII is idle. - // - while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) - { - } - - // - // Tell the MAC to read the given PHY register. - // - HWREG(ui32Base + EMAC_O_MIIADDR) = - ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) | - (ui8RegAddr << EMAC_MIIADDR_MII_S) | - (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB); - - // - // Wait for the read to complete. - // - while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) - { - } - - // - // Return the result. - // - return(HWREG(ui32Base + EMAC_O_MIIDATA) & EMAC_MIIDATA_DATA_M); -} - -//***************************************************************************** -// -//! Reads from an extended PHY register. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui16RegAddr is the address of the PHY extended register to be -//! accessed. -//! -//! When using the internal PHY or when connected to an external PHY -//! supporting extended registers, this function returns the contents of the -//! extended PHY register specified by \e ui16RegAddr. -//! -//! \return Returns the 16-bit value read from the PHY. -// -//***************************************************************************** -uint16_t -EMACPHYExtendedRead(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr) -{ - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - ASSERT(ui32Base == EMAC0_BASE); - - // - // Set the address of the register we're about to read. - // - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x001F); - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16RegAddr); - - // - // Read the extended register value. - // - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x401F); - return(EMACPHYRead(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR)); -} - -//***************************************************************************** -// -//! Writes a value to an extended PHY register. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui16RegAddr is the address of the PHY extended register to be -//! accessed. -//! \param ui16Value is the value to write to the register. -//! -//! When using the internal PHY or when connected to an external PHY -//! supporting extended registers, this function allows a value to be written -//! to the extended PHY register specified by \e ui16RegAddr. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYExtendedWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr, uint16_t ui16Value) -{ - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - ASSERT(ui32Base == EMAC0_BASE); - - // - // Set the address of the register we're about to write. - // - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x001F); - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16RegAddr); - - // - // Write the extended register. - // - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x401F); - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16Value); -} - -//***************************************************************************** -// -//! Powers off the Ethernet PHY. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to power down. -//! -//! This function powers off the Ethernet PHY, reducing the current -//! consumption of the device. While in the powered-off state, the Ethernet -//! controller is unable to connect to Ethernet. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYPowerOff(uint32_t ui32Base, uint8_t ui8PhyAddr) -{ - // - // Set the PWRDN bit and clear the ANEN bit in the PHY, putting it into - // its low power mode. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_BMCR, - (EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_BMCR) & - ~EPHY_BMCR_ANEN) | EPHY_BMCR_PWRDWN); -} - -//***************************************************************************** -// -//! Powers on the Ethernet PHY. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to power up. -//! -//! This function powers on the Ethernet PHY, enabling it return to normal -//! operation. By default, the PHY is powered on, so this function is only -//! called if EMACPHYPowerOff() has previously been called. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYPowerOn(uint32_t ui32Base, uint8_t ui8PhyAddr) -{ - // - // Clear the PWRDN bit and set the ANEGEN bit in the PHY, putting it into - // normal operating mode. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_BMCR, - (EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_BMCR) & - ~EPHY_BMCR_PWRDWN) | EPHY_BMCR_ANEN); -} - -//***************************************************************************** -// -//! Configures the Ethernet MAC's IEEE 1588 timestamping options. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Config contains flags selecting particular configuration -//! options. -//! \param ui32SubSecondInc is the number that the IEEE 1588 subsecond clock -//! should increment on each tick. -//! -//! This function is used to configure the operation of the Ethernet MAC's -//! internal timestamping clock. This clock is used to timestamp incoming -//! and outgoing packets and as an accurate system time reference when -//! IEEE 1588 Precision Time Protocol is in use. -//! -//! The \e ui32Config parameter contains a collection of flags selecting the -//! desired options. Valid flags are: -//! -//! One of the following to determine whether IEEE 1588 version 1 or version 2 -//! packet format is to be processed: -//! -//! - \b EMAC_TS_PTP_VERSION_2 -//! - \b EMAC_TS_PTP_VERSION_1 -//! -//! One of the following to determine how the IEEE 1588 clock's subsecond -//! value should be interpreted and handled: -//! -//! - \b EMAC_TS_DIGITAL_ROLLOVER causes the clock's subsecond value to roll -//! over at 0x3BA9C9FF (999999999 decimal). In this mode, it can be considered -//! as a nanosecond counter with each digit representing 1 ns. -//! - \b EMAC_TS_BINARY_ROLLOVER causes the clock's subsecond value to roll -//! over at 0x7FFFFFFF. In this mode, the subsecond value counts 0.465 ns -//! periods. -//! -//! One of the following to enable or disable MAC address filtering. When -//! enabled, PTP frames are filtered unless the destination MAC address matches -//! any of the currently programmed MAC addresses. -//! -//! - \b EMAC_TS_MAC_FILTER_ENABLE -//! - \b EMAC_TS_MAC_FILTER_DISABLE -//! -//! One of the following to determine how the clock is updated: -//! - \b EMAC_TS_UPDATE_COARSE causes the IEEE 1588 clock to advance by -//! the value supplied in the \e ui32SubSecondInc parameter on each main -//! oscillator clock cycle. -//! - \b EMAC_TS_UPDATE_FINE selects the fine update method which causes the -//! IEEE 1588 clock to advance by the the value supplied in the -//! \e ui32SubSecondInc parameter each time a carry is generated from the -//! addend accumulator register. -//! -//! One of the following to determine which IEEE 1588 messages are timestamped: -//! -//! - \b EMAC_TS_SYNC_FOLLOW_DREQ_DRESP timestamps SYNC, Follow_Up, Delay_Req -//! and Delay_Resp messages. -//! - \b EMAC_TS_SYNC_ONLY timestamps only SYNC messages. -//! - \b EMAC_TS_DELAYREQ_ONLY timestamps only Delay_Req messages. -//! - \b EMAC_TS_ALL timestamps all IEEE 1588 messages. -//! - \b EMAC_TS_SYNC_PDREQ_PDRESP timestamps only SYNC, Pdelay_Req and -//! Pdelay_Resp messages. -//! - \b EMAC_TS_DREQ_PDREQ_PDRESP timestamps only Delay_Req, Pdelay_Req and -//! Pdelay_Resp messages. -//! - \b EMAC_TS_SYNC_DELAYREQ timestamps only Delay_Req messages. -//! - \b EMAC_TS_PDREQ_PDRESP timestamps only Pdelay_Req and Pdelay_Resp -//! messages. -//! -//! Optional, additional flags are: -//! -//! - \b EMAC_TS_PROCESS_IPV4_UDP processes PTP packets encapsulated in UDP -//! over IPv4 packets. If absent, the MAC ignores these frames. -//! - \b EMAC_TS_PROCESS_IPV6_UDP processes PTP packets encapsulated in UDP -//! over IPv6 packets. If absent, the MAC ignores these frames. -//! - \b EMAC_TS_PROCESS_ETHERNET processes PTP packets encapsulated directly -//! in Ethernet frames. If absent, the MAC ignores these frames. -//! - \b EMAC_TS_ALL_RX_FRAMES enables timestamping for all frames received -//! by the MAC, regardless of type. -//! -//! The \e ui32SubSecondInc controls the rate at which the timestamp clock's -//! subsecond count increments. Its meaning depends on which of \b -//! EMAC_TS_DIGITAL_ROLLOVER or \b EMAC_TS_BINARY_ROLLOVER and -//! \b EMAC_TS_UPDATE_FINE or \b EMAC_TS_UPDATE_COARSE were included -//! in \e ui32Config. -//! -//! The timestamp second counter is incremented each time the subsecond counter -//! rolls over. In digital rollover mode, the subsecond counter acts as a -//! simple 31-bit counter, rolling over to 0 after reaching 0x7FFFFFFF. In -//! this case, each lsb of the subsecond counter represents 0.465 ns (assuming -//! the definition of 1 second resolution for the seconds counter). When -//! binary rollover mode is selected, the subsecond counter acts as a -//! nanosecond counter and rolls over to 0 after reaching 999,999,999 making -//! each lsb represent 1 nanosecond. -//! -//! In coarse update mode, the timestamp subsecond counter is incremented by -//! \e ui32SubSecondInc on each main oscillator clock tick. Setting -//! \e ui32SubSecondInc to the main oscillator clock period in either 1 ns or -//! 0.465 ns units ensures that the time stamp, read as seconds and -//! subseconds, increments at the same rate as the main oscillator clock. For -//! example, if the main oscillator is 25 MHz, \e ui32SubSecondInc is set to 40 -//! if digital rollover mode is selected or (40 / 0.465) = 86 in binary -//! rollover mode. -//! -//! In fine update mode, the subsecond increment value must be set according -//! to the desired accuracy of the recovered IEEE 1588 clock which must be -//! lower than the system clock rate. Fine update mode is typically used when -//! synchronizing the local clock to the IEEE 1588 master clock. The subsecond -//! counter is incremented by \e ui32SubSecondInc counts each time a 32-bit -//! accumulator register generates a carry. The accumulator register is -//! incremented by the addend value on each main oscillator tick and this -//! addend value is modified to allow fine control over the rate of change of -//! the timestamp counter. The addend value is calculated using the ratio of -//! the main oscillator clock rate and the desired IEEE 1588 clock rate and the -//! \e ui32SubSecondInc value is set to correspond to the desired IEEE 1588 -//! clock rate. As an example, using digital rollover mode and a 25-MHz -//! main oscillator clock with a desired IEEE 1588 clock accuracy of 12.5 MHz, -//! we would set \e ui32SubSecondInc to the 12.5-MHz clock period of 80 ns and -//! set the initial addend value to 0x80000000 to generate a carry on every -//! second system clock. -//! -//! \sa EMACTimestampAddendSet() -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32SubSecondInc) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Ensure that the PTP module clock is enabled. - // - HWREG(ui32Base + EMAC_O_CC) |= EMAC_CC_PTPCEN; - - // - // Write the subsecond increment value. - // - HWREG(ui32Base + EMAC_O_SUBSECINC) = ((ui32SubSecondInc << - EMAC_SUBSECINC_SSINC_S) & - EMAC_SUBSECINC_SSINC_M); - - // - // Set the timestamp configuration. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Returns the current IEEE 1588 timestamping configuration. -//! -//! \param ui32Base is the base address of the controller. -//! \param pui32SubSecondInc points to storage that is written with the -//! current subsecond increment value for the IEEE 1588 clock. -//! -//! This function may be used to retreive the current MAC timestamping -//! configuration. -//! -//! \sa EMACTimestampConfigSet() -//! -//! \return Returns the current timestamping configuration as a logical OR of -//! the following flags: -//! -//! - \b EMAC_TS_PTP_VERSION_2 indicates that the MAC is processing PTP -//! version 2 messages. If this flag is absent, PTP version 1 messages are -//! expected. -//! - \b EMAC_TS_DIGITAL_ROLLOVER causes the clock's subsecond value to roll -//! over at 0x3BA9C9FF (999999999 decimal). In this mode, it can be considered -//! as a nanosecond counter with each digit representing 1 ns. If this flag is -//! absent, the subsecond value rolls over at 0x7FFFFFFF, effectively counting -//! increments of 0.465 ns. -//! - \b EMAC_TS_MAC_FILTER_ENABLE indicates that incoming PTP messages -//! are filtered using any of the configured MAC addresses. Messages with a -//! destination address programmed into the MAC address filter are passed, -//! others are discarded. If this flag is absent, the MAC address is ignored. -//! - \b EMAC_TS_UPDATE_FINE implements the fine update method that causes the -//! IEEE 1588 clock to advance by the the value returned in the -//! \e *pui32SubSecondInc parameter each time a carry is generated from the -//! addend accumulator register. If this flag is absent, the coarse update -//! method is in use and the clock is advanced by the \e *pui32SubSecondInc -//! value on each system clock tick. -//! - \b EMAC_TS_SYNC_ONLY indicates that timestamps are only generated for -//! SYNC messages. -//! - \b EMAC_TS_DELAYREQ_ONLY indicates that timestamps are only generated -//! for Delay_Req messages. -//! - \b EMAC_TS_ALL indicates that timestamps are generated for all -//! IEEE 1588 messages. -//! - \b EMAC_TS_SYNC_PDREQ_PDRESP timestamps only SYNC, Pdelay_Req and -//! Pdelay_Resp messages. -//! - \b EMAC_TS_DREQ_PDREQ_PDRESP indicates that timestamps are only -//! generated for Delay_Req, Pdelay_Req and Pdelay_Resp messages. -//! - \b EMAC_TS_SYNC_DELAYREQ indicates that timestamps are only generated -//! for Delay_Req messages. -//! - \b EMAC_TS_PDREQ_PDRESP indicates that timestamps are only generated -//! for Pdelay_Req and Pdelay_Resp messages. -//! - \b EMAC_TS_PROCESS_IPV4_UDP indicates that PTP packets encapsulated in -//! UDP over IPv4 packets are being processed. If absent, the MAC ignores -//! these frames. -//! - \b EMAC_TS_PROCESS_IPV6_UDP indicates that PTP packets encapsulated in -//! UDP over IPv6 packets are being processed. If absent, the MAC ignores -//! these frames. -//! - \b EMAC_TS_PROCESS_ETHERNET indicates that PTP packets encapsulated -//! directly in Ethernet frames are being processd. If absent, the MAC ignores -//! these frames. -//! - \b EMAC_TS_ALL_RX_FRAMES indicates that timestamping is enabled for all -//! frames received by the MAC, regardless of type. -//! -//! If \b EMAC_TS_ALL_RX_FRAMES and none of the options specifying subsets -//! of PTP packets to timestamp are set, the MAC is configured to timestamp -//! SYNC, Follow_Up, Delay_Req and Delay_Resp messages only. -// -//***************************************************************************** -uint32_t -EMACTimestampConfigGet(uint32_t ui32Base, uint32_t *pui32SubSecondInc) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pui32SubSecondInc); - - // - // Read the current subsecond increment value. - // - *pui32SubSecondInc = (HWREG(ui32Base + EMAC_O_SUBSECINC) & - EMAC_SUBSECINC_SSINC_M) >> EMAC_SUBSECINC_SSINC_S; - - // - // Return the current timestamp configuration. - // - return(HWREG(ui32Base + EMAC_O_TIMSTCTRL)); -} - -//***************************************************************************** -// -//! Enables packet timestamping and starts the system clock running. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to enable the system clock used to timestamp -//! Ethernet frames and to enable that timestamping. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampEnable(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Enable IEEE 1588 timestamping. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSEN; - - // - // If necessary, initialize the timestamping system. This bit self-clears - // once the system time is loaded. Only do this if initialization is not - // currently ongoing. - // - if(!(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSINIT)) - { - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSINIT; - } -} - -//***************************************************************************** -// -//! Disables packet timestamping and stops the system clock. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to stop the system clock used to timestamp -//! Ethernet frames and to disable timestamping. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampDisable(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Disable IEEE 1588 timestamping. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) &= ~EMAC_TIMSTCTRL_TSEN; -} - -//***************************************************************************** -// -//! Sets the current system time. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Seconds is the seconds value of the new system clock setting. -//! \param ui32SubSeconds is the subseconds value of the new system clock -//! setting. -//! -//! This function may be used to set the current system time. The system -//! clock is set to the value passed in the \e ui32Seconds and -//! \e ui32SubSeconds parameters. -//! -//! The meaning of \e ui32SubSeconds depends on the current system time -//! configuration. If EMACTimestampConfigSet() was previously called with -//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the -//! \e ui32SubSeconds value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was -//! specified instead, a \e ui32SubSeconds bit represents 0.46 ns. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampSysTimeSet(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32SubSeconds) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the new time to the system time update registers. - // - HWREG(ui32Base + EMAC_O_TIMSECU) = ui32Seconds; - HWREG(ui32Base + EMAC_O_TIMNANOU) = ui32SubSeconds; - - // - // Wait for any previous update to complete. - // - while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSINIT) - { - // - // Spin for a while. - // - } - - // - // Force the system clock to reset. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSINIT; -} - -//***************************************************************************** -// -//! Gets the current system time. -//! -//! \param ui32Base is the base address of the controller. -//! \param pui32Seconds points to storage for the current seconds value. -//! \param pui32SubSeconds points to storage for the current subseconds value. -//! -//! This function may be used to get the current system time. -//! -//! The meaning of \e ui32SubSeconds depends on the current system time -//! configuration. If EMACTimestampConfigSet() was previously called with -//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the -//! \e ui32SubSeconds value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was -//! specified instead, a \e ui32SubSeconds bit represents 0.46 ns. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampSysTimeGet(uint32_t ui32Base, uint32_t *pui32Seconds, - uint32_t *pui32SubSeconds) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pui32Seconds); - ASSERT(pui32SubSeconds); - - // - // Read the two-part system time from the seconds and nanoseconds - // registers. We do this in a way that should guard against us reading - // the registers across a nanosecond wrap. - // - do - { - *pui32Seconds = HWREG(ui32Base + EMAC_O_TIMSEC); - *pui32SubSeconds = HWREG(ui32Base + EMAC_O_TIMNANO); - } - while(*pui32SubSeconds > HWREG(ui32Base + EMAC_O_TIMNANO)); -} - -//***************************************************************************** -// -//! Adjusts the current system time upwards or downwards by a given amount. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Seconds is the seconds value of the time update to apply. -//! \param ui32SubSeconds is the subseconds value of the time update to apply. -//! \param bInc defines the direction of the update. -//! -//! This function may be used to adjust the current system time either upwards -//! or downwards by a given amount. The size of the adjustment is given by -//! the \e ui32Seconds and \e ui32SubSeconds parameter and the direction -//! by the \e bInc parameter. When \e bInc is \e true, the system time is -//! advanced by the interval given. When it is \e false, the time is retarded -//! by the interval. -//! -//! The meaning of \e ui32SubSeconds depends on the current system time -//! configuration. If EMACTimestampConfigSet() was previously called with -//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the -//! subsecond value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was -//! specified instead, a subsecond bit represents 0.46 ns. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampSysTimeUpdate(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32SubSeconds, bool bInc) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the new time to the system time update registers. - // - HWREG(ui32Base + EMAC_O_TIMSECU) = ui32Seconds; - HWREG(ui32Base + EMAC_O_TIMNANOU) = ui32SubSeconds | - (bInc ? 0 : EMAC_TIMNANOU_ADDSUB); - - // - // Wait for any previous update to complete. - // - while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSUPDT) - { - // - // Spin for a while. - // - } - - // - // Force the system clock to update by the value provided. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSUPDT; -} - -//***************************************************************************** -// -//! Adjusts the system time update rate when using the fine correction method. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Increment is the number to add to the accumulator register on -//! each tick of the 25-MHz main oscillator. -//! -//! This function is used to control the rate of update of the system time -//! when in fine update mode. Fine correction mode is selected if -//! \e EMAC_TS_UPDATE_FINE is supplied in the \e ui32Config parameter passed -//! to a previous call to EMACTimestampConfigSet(). Fine update mode is -//! typically used when synchronizing the local clock to the IEEE 1588 master -//! clock. The subsecond counter is incremented by the number passed to -//! EMACTimestampConfigSet() in the \e ui32SubSecondInc parameter each time a -//! 32-bit accumulator register generates a carry. The accumulator register is -//! incremented by the "addend" value on each main oscillator tick, and this -//! addend value is modified to allow fine control over the rate of change of -//! the timestamp counter. The addend value is calculated using the ratio of -//! the main oscillator clock rate and the desired IEEE 1588 clock rate and the -//! \e ui32SubSecondInc value is set to correspond to the desired IEEE 1588 -//! clock rate. -//! -//! As an example, using digital rollover mode and a 25-MHz main oscillator -//! clock with a desired IEEE 1588 clock accuracy of 12.5 MHz, and having made -//! a previous call to EMACTimestampConfigSet() with \e ui32SubSecondInc set to -//! the 12.5-MHz clock period of 80 ns, the initial \e ui32Increment value -//! would be set to 0x80000000 to generate a carry on every second main -//! oscillator tick. Because the system time updates each time the accumulator -//! overflows, small changes in the \e ui32Increment value can be used to very -//! finely control the system time rate. -//! -//! \return None. -//! -//! \sa EMACTimestampConfigSet() -// -//***************************************************************************** -void -EMACTimestampAddendSet(uint32_t ui32Base, uint32_t ui32Increment) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - HWREG(ui32Base + EMAC_O_TIMADD) = ui32Increment; - - // - // Wait for any previous update to complete. - // - while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_ADDREGUP) - { - // - // Spin for a while. - // - } - - // - // Force the system clock to update by the value provided. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_ADDREGUP; -} - -//***************************************************************************** -// -//! Sets the target system time at which the next Ethernet timer interrupt is -//! generated. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Seconds is the second value of the desired target time. -//! \param ui32SubSeconds is the subseconds value of the desired target time. -//! -//! This function may be used to schedule an interrupt at some future time. -//! The time reference for the function is the IEEE 1588 time as returned by -//! EMACTimestampSysTimeGet(). To generate an interrupt when the system -//! time exceeds a given value, call this function to set the desired time, -//! then EMACTimestampTargetIntEnable() to enable the interrupt. When the -//! system time increments past the target time, an Ethernet interrupt with -//! status \b EMAC_INT_TIMESTAMP is generated. -//! -//! The accuracy of the interrupt timing depends on the Ethernet timer -//! update frequency and the subsecond increment value currently in use. The -//! interrupt is generated on the first timer increment that causes the -//! system time to be greater than or equal to the target time set. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampTargetSet(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32SubSeconds) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Wait for any previous write to complete. - // - while(HWREG(ui32Base + EMAC_O_TARGNANO) & EMAC_TARGNANO_TRGTBUSY) - { - } - - // - // Write the new target time. - // - HWREG(ui32Base + EMAC_O_TARGSEC) = ui32Seconds; - HWREG(ui32Base + EMAC_O_TARGNANO) = ui32SubSeconds; -} - -//***************************************************************************** -// -//! Enables the Ethernet system time interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be used after EMACTimestampTargetSet() to schedule an -//! interrupt at some future time. The time reference for the function is -//! the IEEE 1588 time as returned by EMACTimestampSysTimeGet(). To generate -//! an interrupt when the system time exceeds a given value, call this function -//! to set the desired time, then EMACTimestampTargetIntEnable() to enable the -//! interrupt. When the system time increments past the target time, an -//! Ethernet interrupt with status \b EMAC_INT_TIMESTAMP is generated. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampTargetIntEnable(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Set the bit to enable the timestamp target interrupt. This bit clears - // automatically when the interrupt fires after which point, you must - // set a new target time and re-enable the interrupts. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_INTTRIG; -} - -//***************************************************************************** -// -//! Disables the Ethernet system time interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be used to disable any pending Ethernet system time -//! interrupt previously scheduled using calls to EMACTimestampTargetSet() -//! and EMACTimestampTargetIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampTargetIntDisable(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Clear the bit to disable the timestamp target interrupt. This bit - // clears automatically when the interrupt fires, so it only must be - // disabled if you want to cancel a previously-set interrupt. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) &= ~EMAC_TIMSTCTRL_INTTRIG; -} - -//***************************************************************************** -// -//! Reads the status of the Ethernet system time interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! -//! When an Ethernet interrupt occurs and \b EMAC_INT_TIMESTAMP is reported -//! bu EMACIntStatus(), this function must be called to read and clear the -//! timer interrupt status. -//! -//! \return The return value is the logical OR of the values -//! \b EMAC_TS_INT_TS_SEC_OVERFLOW and \b EMAC_TS_INT_TARGET_REACHED. -//! -//! - \b EMAC_TS_INT_TS_SEC_OVERFLOW indicates that the second counter in the -//! hardware timer has rolled over. -//! - \b EMAC_TS_INT_TARGET_REACHED indicates that the system time incremented -//! past the value set in an earlier call to EMACTimestampTargetSet(). When -//! this occurs, a new target time may be set and the interrupt re-enabled -//! using calls to EMACTimestampTargetSet() and -//! EMACTimestampTargetIntEnable(). -// -//***************************************************************************** -uint32_t -EMACTimestampIntStatus(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Return the current interrupt status from the timestamp module. - // - return(HWREG(ui32Base + EMAC_O_TIMSTAT)); -} - -//***************************************************************************** -// -//! Configures the Ethernet MAC PPS output in simple mode. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32FreqConfig determines the frequency of the output generated on -//! the PPS pin. -//! -//! This function configures the Ethernet MAC PPS (Pulse Per Second) engine to -//! operate in its simple mode which allows the generation of a few, fixed -//! frequencies and pulse widths on the PPS pin. If more complex pulse -//! train generation is required, the MAC also provides a command-based -//! PPS control mode that can be selected by calling -//! EMACTimestampPPSCommandModeSet(). -//! -//! The \e ui32FreqConfig parameter may take one of the following values: -//! -//! - \b EMAC_PPS_SINGLE_PULSE generates a single high pulse on the PPS -//! output once per second. The pulse width is the same as the system clock -//! period. -//! - \b EMAC_PPS_1HZ generates a 1Hz signal on the PPS output. This option -//! is not available if the system time subsecond counter is currently -//! configured to operate in binary rollover mode. -//! - \b EMAC_PPS_2HZ, \b EMAC_PPS_4HZ, \b EMAC_PPS_8HZ, -//! \b EMAC_PPS_16HZ, \b EMAC_PPS_32HZ, \b EMAC_PPS_64HZ, -//! \b EMAC_PPS_128HZ, \b EMAC_PPS_256HZ, \b EMAC_PPS_512HZ, -//! \b EMAC_PPS_1024HZ, \b EMAC_PPS_2048HZ, \b EMAC_PPS_4096HZ, -//! \b EMAC_PPS_8192HZ, \b EMAC_PPS_16384HZ generate the requested -//! frequency on the PPS output in both binary and digital rollover modes. -//! - \b EMAC_PPS_32768HZ generates a 32KHz signal on the PPS output. This -//! option is not available if the system time subsecond counter is currently -//! configured to operate in digital rollover mode. -//! -//! Except when \b EMAC_PPS_SINGLE_PULSE is specified, the signal generated -//! on PPS has a duty cycle of 50% when binary rollover mode is used for the -//! system time subsecond count. In digital mode, the output frequency -//! averages the value requested and is resynchronized each second. For -//! example, if \b EMAC_PPS_4HZ is selected in digital rollover mode, the -//! output generates three clocks with 50 percent duty cycle and 268 ms -//! period followed by a fourth clock of 195 ms period, 134 ms low and 61 ms high. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampPPSSimpleModeSet(uint32_t ui32Base, uint32_t ui32FreqConfig) -{ - bool bDigital; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Are we currently running the clock in digital or binary rollover mode? - // - bDigital = (HWREG(ui32Base + EMAC_O_TIMSTCTRL) & - EMAC_TS_DIGITAL_ROLLOVER) ? true : false; - - // - // Weed out some unsupported frequencies. The hardware can't produce a - // 1Hz output when we are in binary rollover mode and can't produce a - // 32KHz output when we are digital rollover mode. - // - ASSERT(bDigital || (ui32FreqConfig != EMAC_PPS_1HZ)); - ASSERT(!bDigital || (ui32FreqConfig != EMAC_PPS_32768HZ)); - - // - // Adjust the supplied frequency if we are currently in binary update mode - // where the control value generates an output that is twice as fast as - // in digital mode. - // - if((ui32FreqConfig != EMAC_PPS_SINGLE_PULSE) && !bDigital) - { - ui32FreqConfig--; - } - - // - // Write the frequency control value to the PPS control register, clearing - // the PPSEN0 bit to ensure that the PPS engine is in simple mode and not - // waiting for a command. We also clear the TRGMODS0 field to revert to - // the default operation of the target time registers. - // - HWREG(ui32Base + EMAC_O_PPSCTRL) = ui32FreqConfig; -} - -//***************************************************************************** -// -//! Configures the Ethernet MAC PPS output in command mode. - -//! \param ui32Base is the base address of the controller. -//! \param ui32Config determines how the system target time is used. -//! -//! The simple mode of operation offered by the PPS (Pulse Per Second) engine -//! may be too restrictive for some applications. The second mode, however, -//! allows complex pulse trains to be generated using commands that tell the -//! engine to send individual pulses or start and stop trains if pulses. In -//! this mode, the pulse width and period may be set arbitrarily based on -//! ticks of the clock used to update the system time. Commands are triggered -//! at specific times using the target time last set using a call to -//! EMACTimestampTargetSet(). -//! -//! The \e ui32Config parameter may be used to control whether the target -//! time is used to trigger commands only or can also generate an interrupt -//! to the CPU. Valid values are: -//! -//! - \b EMAC_PPS_TARGET_INT configures the target time to only raise -//! an interrupt and not to trigger any pending PPS command. -//! - \b EMAC_PPS_TARGET_PPS configures the target time to trigger a pending -//! PPS command but not raise an interrupt. -//! - \b EMAC_PPS_TARGET_BOTH configures the target time to trigger any -//! pending PPS command and also raise an interrupt. -//! -//! To use command mode, an application must call this function to enable the -//! mode, then call: -//! -//! - EMACTimestampPPSPeriodSet() to set the desired pulse width and period -//! then -//! - EMACTimestampTargetSet() to set the time at which the next command is -//! executed, and finally -//! - EMACTimestampPPSCommand() to send a command to cause the pulse or -//! pulse train to be started at the required time. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampPPSCommandModeSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(!(ui32Config & (EMAC_PPS_TARGET_INT | EMAC_PPS_TARGET_PPS | - EMAC_PPS_TARGET_BOTH))); - - // - // Wait for any previous command write to complete. - // - while(HWREG(ui32Base + EMAC_O_PPSCTRL) & EMAC_PPSCTRL_PPSCTRL_M) - { - // - // Wait a bit. - // - } - - // - // Write the configuration value to the PPS control register, setting the - // PPSEN0 bit to ensure that the PPS engine is in command mode and - // clearing the command in the PPSCTRL field. - // - HWREG(ui32Base + EMAC_O_PPSCTRL) = (EMAC_PPSCTRL_PPSEN0 | ui32Config); -} - -//***************************************************************************** -// -//! Sends a command to control the PPS output from the Ethernet MAC. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8Cmd identifies the command to be sent. -//! -//! This function may be used to send a command to the MAC PPS (Pulse Per -//! Second) controller when it is operating in command mode. Command mode -//! is selected by calling EMACTimestampPPSCommandModeSet(). Valid -//! commands are as follow: -//! -//! - \b EMAC_PPS_COMMAND_NONE indicates no command. -//! - \b EMAC_PPS_COMMAND_START_SINGLE indicates that a single high pulse -//! should be generated when the system time reaches the current target time. -//! - \b EMAC_PPS_COMMAND_START_TRAIN indicates that a train of pulses -//! should be started when the system time reaches the current target time. -//! - \b EMAC_PPS_COMMAND_CANCEL_START cancels any pending start command if -//! the system time has not yet reached the programmed target time. -//! - \b EMAC_PPS_COMMAND_STOP_AT_TIME indicates that the current pulse -//! train should be stopped when the system time reaches the current target -//! time. -//! - \b EMAC_PPS_COMMAND_STOP_NOW indicates that the current pulse train -//! should be stopped immediately. -//! - \b EMAC_PPS_COMMAND_CANCEL_STOP cancels any pending stop command if -//! the system time has not yet reached the programmed target time. -//! -//! In all cases, the width of the pulses generated is governed by the -//! \e ui32Width parameter passed to EMACTimestampPPSPeriodSet(). If a -//! command starts a train of pulses, the period of the pulses is governed -//! by the \e ui32Period parameter passed to the same function. -//! Target times associated with PPS commands are set by calling -//! EMACTimestampTargetSet(). -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampPPSCommand(uint32_t ui32Base, uint8_t ui8Cmd) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Wait for any previous command write to complete. - // - while(HWREG(ui32Base + EMAC_O_PPSCTRL) & EMAC_PPSCTRL_PPSCTRL_M) - { - // - // Wait a bit. - // - } - - // - // Write the command to the PPS control register. - // - HWREG(ui32Base + EMAC_O_PPSCTRL) = (EMAC_PPSCTRL_PPSEN0 | ui8Cmd); -} - -//***************************************************************************** -// -//! Sets the period and width of the pulses on the Ethernet MAC PPS output. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Period is the period of the PPS output expressed in terms of -//! system time update ticks. -//! \param ui32Width is the width of the high portion of the PPS output -//! expressed in terms of system time update ticks. -//! -//! This function may be used to control the period and duty cycle of the -//! signal output on the Ethernet MAC PPS pin when the PPS generator is -//! operating in command mode and a command to send one or more pulses has been -//! executed. Command mode is selected by calling -//! EMACTimestampPPSCommandModeSet(). -//! -//! In simple mode, the PPS output signal frequency is controlled by the -//! \e ui32FreqConfig parameter passed to EMACTimestampPPSSimpleModeSet(). -//! -//! The \e ui32Period and \e ui32Width parameters are expressed in terms of -//! system time update ticks. When the system time is operating in coarse -//! update mode, each tick is equivalent to the system clock. In fine update -//! mode, a tick occurs every time the 32-bit system time accumulator overflows -//! and this, in turn, is determined by the value passed to the function -//! EMACTimestampAddendSet(). Regardless of the tick source, each tick -//! increments the actual system time, queried using EMACTimestampSysTimeGet() -//! by the subsecond increment value passed in the \e ui32SubSecondInc to -//! EMACTimestampConfigSet(). -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampPPSPeriodSet(uint32_t ui32Base, uint32_t ui32Period, - uint32_t ui32Width) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the desired PPS period and pulse width. - // - HWREG(ui32Base + EMAC_O_PPS0INTVL) = ui32Period; - HWREG(ui32Base + EMAC_O_PPS0WIDTH) = ui32Width; -} - -//***************************************************************************** -// -//! Sets options related to reception of VLAN-tagged frames. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui16Tag is the IEEE 802.1Q VLAN tag expected for incoming frames. -//! \param ui32Config determines how the receiver handles VLAN-tagged frames. -//! -//! This function configures the receiver's handling of IEEE 802.1Q VLAN -//! tagged frames. Incoming tagged frames are filtered using either a perfect -//! filter or a hash filter. When hash filtering is disabled, VLAN frames -//! tagged with the value of \e ui16Tag pass the filter and all others are -//! rejected. The tag comparison may involve all 16 bits or only the 12-bit -//! VLAN ID portion of the tag. -//! -//! The \e ui32Config parameter is a logical OR of the following values: -//! -//! - \b EMAC_VLAN_RX_HASH_ENABLE enables hash filtering for VLAN tags. If -//! this flag is absent, perfect filtering using the tag supplied in \e ui16Tag -//! is performed. The hash filter may be set using EMACVLANHashFilterSet(), -//! and EMACVLANHashFilterBitCalculate() may be used to determine which bits -//! to set in the filter for given VLAN tags. -//! - \b EMAC_VLAN_RX_SVLAN_ENABLE causes the receiver to recognize S-VLAN -//! (Type = 0x88A8) frames as valid VLAN-tagged frames. If absent, only -//! frames with type 0x8100 are considered valid VLAN frames. -//! - \b EMAC_VLAN_RX_INVERSE_MATCH causes the receiver to pass all VLAN -//! frames for which the tags do not match the supplied \e ui16Tag value. If -//! this flag is absent, only tagged frames matching \e ui16Tag are passed. -//! - \b EMAC_VLAN_RX_12BIT_TAG causes the receiver to compare only the -//! bottom 12 bits of \e ui16Tag when performing either perfect or hash -//! filtering of VLAN frames. If this flag is absent, all 16 bits of the frame -//! tag are examined when filtering. If this flag is set and \e ui16Tag has -//! all bottom 12 bits clear, the receiver passes all frames with types -//! 0x8100 or 0x88A8 regardless of the tag values they contain. -//! -//! \note To ensure that VLAN frames that fail the tag filter are dropped -//! by the MAC, EMACFrameFilterSet() must be called with the \b -//! EMAC_FRMFILTER_VLAN flag set in the \e ui32FilterOpts parameter. If -//! this flag is not set, failing VLAN packets are received by the -//! application, but bit 10 of RDES0 (\b EMAC_FRMFILTER_VLAN) is clear -//! indicating that the packet did not match the current VLAG tag filter. -//! -//! \sa EMACVLANRxConfigGet() -//! -//! \return None -// -//***************************************************************************** -void -EMACVLANRxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the VLAN tag register. - // - HWREG(ui32Base + EMAC_O_VLANTG) = - ui32Config | (((uint32_t)ui16Tag) << EMAC_VLANTG_VL_S); -} - -//***************************************************************************** -// -//! Returns the currently-set options related to reception of VLAN-tagged -//! frames. -//! -//! \param ui32Base is the base address of the controller. -//! \param pui16Tag points to storage which is written with the currently -//! configured VLAN tag used for perfect filtering. -//! -//! This function returns information on how the receiver is currently -//! handling IEEE 802.1Q VLAN-tagged frames. -//! -//! \sa EMACVLANRxConfigSet() -//! -//! \return Returns flags defining how VLAN-tagged frames are handled. The -//! value is a logical OR of the following flags: -//! -//! - \b EMAC_VLAN_RX_HASH_ENABLE indicates that hash filtering is enabled -//! for VLAN tags. If this flag is absent, perfect filtering using the tag -//! returned in \e *pui16Tag is performed. -//! - \b EMAC_VLAN_RX_SVLAN_ENABLE indicates that the receiver recognizes -//! S-VLAN (Type = 0x88A8) frames as valid VLAN-tagged frames. If absent, only -//! frames with type 0x8100 are considered valid VLAN frames. -//! - \b EMAC_VLAN_RX_INVERSE_MATCH indicates that the receiver passes all -//! VLAN frames for which the tags do not match the \e *pui16Tag value. If -//! this flag is absent, only tagged frames matching \e *pui16Tag are passed. -//! - \b EMAC_VLAN_RX_12BIT_TAG indicates that the receiver is comparing only -//! the bottom 12 bits of \e *pui16Tag when performing either perfect or hash -//! filtering of VLAN frames. If this flag is absent, all 16 bits of the frame -//! tag are examined when filtering. If this flag is set and \e *pui16Tag has -//! all bottom 12 bits clear, the receiver passes all frames with types -//! 0x8100 or 0x88A8 regardless of the tag values they contain. -// -//***************************************************************************** -uint32_t -EMACVLANRxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag) -{ - uint32_t ui32Value; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pui16Tag); - - // - // Read the VLAN tag register. - // - ui32Value = HWREG(ui32Base + EMAC_O_VLANTG); - - // - // Extract the VLAN tag from the register. - // - *pui16Tag = (ui32Value & EMAC_VLANTG_VL_M) >> EMAC_VLANTG_VL_S; - - // - // Return the configuration flags. - // - return(ui32Value & ~EMAC_VLANTG_VL_M); -} - -//***************************************************************************** -// -//! Sets options related to transmission of VLAN-tagged frames. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui16Tag is the VLAN tag to be used when inserting or replacing tags -//! in transmitted frames. -//! \param ui32Config determines the VLAN-related processing performed by -//! the transmitter. -//! -//! This function is used to configure transmitter options relating to -//! IEEE 802.1Q VLAN tagging. The transmitter may be set to insert tagging -//! into untagged frames or replace existing tags with new values. -//! -//! The \e ui16Tag parameter contains the VLAN tag to be used in outgoing -//! tagged frames. The \e ui32Config parameter is a logical OR of the -//! following labels: -//! -//! - \b EMAC_VLAN_TX_SVLAN uses the S-VLAN type (0x88A8) when inserting or -//! replacing tags in transmitted frames. If this label is absent, C-VLAN -//! type (0x8100) is used. -//! - \b EMAC_VLAN_TX_USE_VLC informs the transmitter that the VLAN tag -//! handling should be defined by the VLAN control (VLC) value provided in -//! this function call. If this tag is absent, VLAN handling is controlled -//! by fields in the transmit descriptor. -//! -//! If \b EMAC_VLAN_TX_USE_VLC is set, one of the following four labels -//! must also be included to define the transmit VLAN tag handling: -//! -//! - \b EMAC_VLAN_TX_VLC_NONE instructs the transmitter to perform no VLAN -//! tag insertion, deletion or replacement. -//! - \b EMAC_VLAN_TX_VLC_DELETE instructs the transmitter to remove VLAN -//! tags from all transmitted frames that contain them. As a result, bytes -//! 13, 14, 15 and 16 are removed from all frames with types 0x8100 or 0x88A8. -//! - \b EMAC_VLAN_TX_VLC_INSERT instructs the transmitter to insert a VLAN -//! type and tag into all outgoing frames regardless of whether or not they -//! already contain a VLAN tag. -//! - \b EMAC_VLAN_TX_VLC_REPLACE instructs the transmitter to replace the -//! VLAN tag in all frames of type 0x8100 or 0x88A8 with the value provided to -//! this function in the \e ui16Tag parameter. -//! -//! \return None -// -//***************************************************************************** -void -EMACVLANTxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the VLAN Tag Inclusion or Replacement register. - // - HWREG(ui32Base + EMAC_O_VLNINCREP) = - ui32Config | ((uint32_t)ui16Tag << EMAC_VLNINCREP_VLT_S); -} - -//***************************************************************************** -// -//! Returns currently-selected options related to transmission of VLAN-tagged -//! frames. -//! -//! \param ui32Base is the base address of the controller. -//! \param pui16Tag points to storage that is written with the VLAN tag -//! currently being used for insertion or replacement. -//! -//! This function returns information on the current settings related to VLAN -//! tagging of transmitted frames. -//! -//! \sa EMACVLANTxConfigSet() -//! -//! \return Returns flags describing the current VLAN configuration relating -//! to frame transmission. The return value is a logical OR of the following -//! values: -//! -//! - \b EMAC_VLAN_TX_SVLAN indicates that the S-VLAN type (0x88A8) is -//! being used when inserting or replacing tags in transmitted frames. If -//! this label is absent, C-VLAN type (0x8100) is being used. -//! - \b EMAC_VLAN_TX_USE_VLC indicates that the transmitter is processing -//! VLAN frames according to the VLAN control (VLC) value returned here. If -//! this tag is absent, VLAN handling is controlled by fields in the transmit -//! descriptor. -//! -//! If \b EMAC_VLAN_TX_USE_VLC is returned, one of the following four labels -//! is also included to define the transmit VLAN tag handling. Note that this -//! value may be extracted from the return value using the mask \b -//! EMAC_VLAN_TX_VLC_MASK. -//! -//! - \b EMAC_VLAN_TX_VLC_NONE indicates that the transmitter is not -//! performing VLAN tag insertion, deletion or replacement. -//! - \b EMAC_VLAN_TX_VLC_DELETE indicates that the transmitter is removing -//! VLAN tags from all transmitted frames which contain them. -//! - \b EMAC_VLAN_TX_VLC_INSERT indicates that the transmitter is inserting -//! a VLAN type and tag into all outgoing frames regardless of whether or not -//! they already contain a VLAN tag. -//! - \b EMAC_VLAN_TX_VLC_REPLACE indicates that the transmitter is replacing -//! the VLAN tag in all transmitted frames of type 0x8100 or 0x88A8 with the -//! value returned in \e *pui16Tag. -// -//***************************************************************************** -uint32_t -EMACVLANTxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag) -{ - uint32_t ui32Value; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pui16Tag); - - // - // Read the VLAN Tag Inclusion or Replacement register. - // - ui32Value = HWREG(ui32Base + EMAC_O_VLNINCREP); - - // - // Extract the tag. - // - *pui16Tag = (uint16_t)((ui32Value & EMAC_VLNINCREP_VLT_M) >> - EMAC_VLNINCREP_VLT_S); - - // - // Return the configuration flags. - // - return(ui32Value & ~EMAC_VLNINCREP_VLT_M); -} - -//***************************************************************************** -// -//! Returns the bit number to set in the VLAN hash filter corresponding to a -//! given tag. -//! -//! \param ui16Tag is the VLAN tag for which the hash filter bit number is to -//! be determined. -//! -//! This function may be used to determine which bit in the VLAN hash filter -//! to set to describe a given 12- or 16-bit VLAN tag. The returned value is -//! a 4-bit value indicating the bit number to set within the 16-bit VLAN -//! hash filter. For example, if 0x02 is returned, this indicates that bit -//! 2 of the hash filter must be set to pass the supplied VLAN tag. -//! -//! \return Returns the bit number to set in the VLAN hash filter to describe -//! the passed tag. -// -//***************************************************************************** -uint32_t -EMACVLANHashFilterBitCalculate(uint16_t ui16Tag) -{ - uint32_t ui32CRC, ui32Mask, ui32Loop; - - // - // Calculate the CRC for the MAC address. - // - ui32CRC = Crc32(0xFFFFFFFF, (uint8_t *)&ui16Tag, 2); - ui32CRC ^= 0xFFFFFFFF; - - // - // Determine the hash bit to use from the calculated CRC. This is the - // top 4 bits of the reversed CRC (or the bottom 4 bits of the calculated - // CRC with the bit order of those 4 bits reversed). - // - ui32Mask = 0; - - // - // Reverse the order of the bottom 4 bits of the calculated CRC. - // - for(ui32Loop = 0; ui32Loop < 4; ui32Loop++) - { - ui32Mask <<= 1; - ui32Mask |= (ui32CRC & 1); - ui32CRC >>= 1; - } - - // - // Return the final hash filter bit index. - // - return(ui32Mask); -} - -//***************************************************************************** -// -//! Sets the hash filter used to control reception of VLAN-tagged frames. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Hash is the hash filter value to set. -//! -//! This function allows the VLAG tag hash filter to be set. By using hash -//! filtering, several different VLAN tags can be filtered very easily at the -//! cost of some false positive results that must be removed by software. -//! -//! The hash filter value passed in \e ui32Hash may be built up by calling -//! EMACVLANHashFilterBitCalculate() for each VLAN tag that is to pass the -//! filter and then set each of the bits for which the numbers are returned by -//! that function. Care must be taken when clearing bits in the hash filter -//! due to the fact that there is a many-to-one correspondence between VLAN -//! tags and hash filter bits. -//! -//! \return None -// -//***************************************************************************** -void -EMACVLANHashFilterSet(uint32_t ui32Base, uint32_t ui32Hash) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the VLAN Hash Table register. - // - HWREG(ui32Base + EMAC_O_VLANHASH) = ui32Hash; -} - -//***************************************************************************** -// -//! Returns the current value of the hash filter used to control reception of -//! VLAN-tagged frames. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function allows the current VLAN tag hash filter value to be returned. -//! Additional VLAN tags may be added to this filter by setting the appropriate -//! bits, determined by calling EMACVLANHashFilterBitCalculate(), and then -//! calling EMACVLANHashFilterSet() to set the new filter value. -//! -//! \return Returns the current value of the VLAN hash filter. -// -//***************************************************************************** -uint32_t -EMACVLANHashFilterGet(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Return the VLAN Hash Table register. - // - return(HWREG(ui32Base + EMAC_O_VLANHASH)); -} - -//***************************************************************************** -// -//! Sets values defining up to four frames used to trigger a remote wake-up. -//! -//! \param ui32Base is the base address of the controller. -//! \param pFilter points to the structure containing remote wake-up frame -//! filter information. -//! -//! This function may be used to define up to four different frames that -//! are considered by the Ethernet MAC to be remote wake-up signals. The -//! data passed to the function describes a wake-up frame in terms of a CRC -//! calculated on up to 31 payload bytes in the frame. The actual bytes used -//! in the CRC calculation are defined by means of a bit mask where a ``1'' -//! indicates that a byte in the frame should contribute to the CRC -//! calculation and a ``0'' indicates that the byte should be skipped, as well -//! as an offset from the start of the frame to the payload byte that represents -//! the first byte in the 31-byte CRC-checked sequence. -//! -//! The \e pFilter parameter points to a structure containing the information -//! necessary to set up the filters. This structure contains the following -//! fields, each of which is replicated 4 times, once for each possible wake-up -//! frame: -//! -//! - \b pui32ByteMask defines whether a given byte in the chosen 31-byte -//! sequence within the frame should contribute to the CRC calculation or not. -//! A 1 indicates that the byte should contribute to the calculation, a 0 -//! causes the byte to be skipped. -//! - \b pui8Command contains flags defining whether this filter is enabled -//! and, if so, whether it refers to unicast or multicast packets. Valid -//! values are one of \b EMAC_RWU_FILTER_MULTICAST or \b -//! EMAC_RWU_FILTER_UNICAST ORed with one of \b EMAC_RWU_FILTER_ENABLE or -//! \b EMAC_RWU_FILTER_DISABLE. -//! - \b pui8Offset defines the zero-based index of the byte within the frame -//! at which CRC checking defined by \b pui32ByteMask begins. -//! Alternatively, this value can be thought of as the number of bytes in the -//! frame that the MAC skips before accumulating the CRC based on the pattern -//! in \b pui32ByteMask. -//! - \b pui16CRC provides the value of the calculated CRC for a valid remote -//! wake-up frame. If the incoming frame is processed according to the filter -//! values provided and the final CRC calculation equals this value, the -//! frame is considered to be a valid remote wake-up frame. -//! -//! Note that this filter uses CRC16 rather than CRC32 as used in frame -//! checksums. The required CRC uses a direct algorithm with polynomial 0x8005, -//! initial seed value 0xFFFF, no final XOR and reversed data order. CRCs -//! for use in this function may be determined using the online calculator -//! found at http://www.zorc.breitbandkatze.de/crc.html. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRemoteWakeUpFrameFilterSet(uint32_t ui32Base, - const tEMACWakeUpFrameFilter *pFilter) -{ - uint32_t *pui32Data; - uint32_t ui32Loop; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pFilter); - - // - // Make sure that the internal register counter for the frame filter - // is reset. This bit automatically resets after 1 clock cycle. - // - HWREG(ui32Base + EMAC_O_PMTCTLSTAT) |= EMAC_PMTCTLSTAT_WUPFRRST; - - // - // Get a word pointer to the supplied structure. - // - pui32Data = (uint32_t *)pFilter; - - // - // Write the 8 words of the wake-up filter definition to the hardware. - // - for(ui32Loop = 0; ui32Loop < 8; ui32Loop++) - { - // - // Write a word of the filter definition. - // - HWREG(ui32Base + EMAC_O_RWUFF) = pui32Data[ui32Loop]; - } -} - -//***************************************************************************** -// -//! Returns the current remote wake-up frame filter configuration. -//! -//! \param ui32Base is the base address of the controller. -//! \param pFilter points to the structure that is written with the current -//! remote wake-up frame filter information. -//! -//! This function may be used to read the current wake-up frame filter -//! settings. The data returned by the function describes wake-up frames in -//! terms of a CRC calculated on up to 31 payload bytes in the frame. The -//! actual bytes used in the CRC calculation are defined by means of a bit mask -//! where a ``1'' indicates that a byte in the frame should contribute to the -//! CRC calculation and a ``0'' indicates that the byte should be skipped, and -//! an offset from the start of the frame to the payload byte that represents -//! the first byte in the 31-byte CRC-checked sequence. -//! -//! The \e pFilter parameter points to storage that is written with a -//! structure containing the information defining the frame filters. This -//! structure contains the following fields, each of which is replicated 4 -//! times, once for each possible wake-up frame: -//! -//! - \b pui32ByteMask defines whether a given byte in the chosen 31-byte -//! sequence within the frame should contribute to the CRC calculation or not. -//! A 1 indicates that the byte should contribute to the calculation, a 0 -//! causes the byte to be skipped. -//! - \b pui8Command contains flags defining whether this filter is enabled -//! and, if so, whether it refers to unicast or multicast packets. Valid -//! values are one of \b EMAC_RWU_FILTER_MULTICAST or \b -//! EMAC_RWU_FILTER_UNICAST ORed with one of \b EMAC_RWU_FILTER_ENABLE or -//! \b EMAC_RWU_FILTER_DISABLE. -//! - \b pui8Offset defines the zero-based index of the byte within the frame -//! at which CRC checking defined by \b pui32ByteMask begins. -//! Alternatively, this value can be thought of as the number of bytes in the -//! frame that the MAC skips before accumulating the CRC based on the pattern -//! in \b pui32ByteMask. -//! - \b pui16CRC provides the value of the calculated CRC for a valid remote -//! wake-up frame. If the incoming frame is processed according to the filter -//! values provided and the final CRC calculation equals this value, the -//! frame is considered to be a valid remote wake-up frame. -//! -//! Note that this filter uses CRC16 rather than CRC32 as used in frame -//! checksums. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRemoteWakeUpFrameFilterGet(uint32_t ui32Base, - tEMACWakeUpFrameFilter *pFilter) -{ - uint32_t *pui32Data; - uint32_t ui32Loop; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pFilter); - - // - // Make sure that the internal register counter for the frame filter - // is reset. This bit automatically resets after 1 clock cycle. - // - HWREG(ui32Base + EMAC_O_PMTCTLSTAT) |= EMAC_PMTCTLSTAT_WUPFRRST; - - // - // Get a word pointer to the supplied structure. - // - pui32Data = (uint32_t *)pFilter; - - // - // Read the 8 words of the wake-up filter definition from the hardware. - // - for(ui32Loop = 0; ui32Loop < 8; ui32Loop++) - { - // - // Read a word of the filter definition. - // - pui32Data[ui32Loop] = HWREG(ui32Base + EMAC_O_RWUFF); - } -} - -//***************************************************************************** -// -//! Sets the Ethernet MAC remote wake-up configuration. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Flags defines which types of frame should trigger a remote -//! wake-up and allows the MAC to be put into power-down mode. -//! -//! This function allows the MAC's remote wake-up features to be configured, -//! determining which types of frame should trigger a wake-up event and -//! allowing an application to place the MAC in power-down mode. In this -//! mode, the MAC ignores all received frames until one matching a -//! configured remote wake-up frame is received, at which point the MAC -//! automatically exits power-down mode and continues to receive frames. -//! -//! The \e ui32Flags parameter is a logical OR of the following flags: -//! -//! - \b EMAC_PMT_GLOBAL_UNICAST_ENABLE instructs the MAC to wake up when any -//! unicast frame matching the MAC destination address filter is received. -//! - \b EMAC_PMT_WAKEUP_PACKET_ENABLE instructs the MAC to wake up when any -//! received frame matches the remote wake-up filter configured via a call -//! to EMACRemoteWakeUpFrameFilterSet(). -//! - \b EMAC_PMT_MAGIC_PACKET_ENABLE instructs the MAC to wake up when a -//! standard Wake-on-LAN "magic packet" is received. The magic packet contains -//! 6 bytes of 0xFF followed immediately by 16 repetitions of the destination -//! MAC address. -//! - \b EMAC_PMT_POWER_DOWN instructs the MAC to enter power-down mode and -//! wait for an incoming frame matching the remote wake-up frames as described -//! by other flags and via the remote wake-up filter. This flag should only -//! set set if at least one other flag is specified to configure a wake-up -//! frame type. -//! -//! When the MAC is in power-down mode, software may exit the mode by calling -//! this function with the \b EMAC_PMT_POWER_DOWN flag absent from \e ui32Flags. -//! If a configured wake-up frame is received while in power-down mode, the -//! \b EMAC_INT_POWER_MGMNT interrupt is signaled and may be cleared by reading -//! the status using EMACPowerManagementStatusGet(). -//! -//! \note While it is possible to gate the clock to the MAC while it is in -//! power-down mode, doing so prevents the reading of the registers required -//! to determine the interrupt status and also prevents power-down mode from -//! exiting via another call to this function. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPowerManagementControlSet(uint32_t ui32Base, uint32_t ui32Flags) -{ - uint32_t ui32Value; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(~(ui32Flags & ~(EMAC_PMT_GLOBAL_UNICAST_ENABLE | - EMAC_PMT_WAKEUP_PACKET_ENABLE | - EMAC_PMT_MAGIC_PACKET_ENABLE | - EMAC_PMT_POWER_DOWN))); - - // - // Read the control/status register, clear all the bits we can set, mask - // in the new values then rewrite the new register value. - // - ui32Value = HWREG(ui32Base + EMAC_O_PMTCTLSTAT); - ui32Value &= ~(EMAC_PMTCTLSTAT_GLBLUCAST | EMAC_PMTCTLSTAT_WUPFREN | - EMAC_PMTCTLSTAT_MGKPKTEN | EMAC_PMTCTLSTAT_PWRDWN); - ui32Value |= ui32Flags; - HWREG(ui32Base + EMAC_O_PMTCTLSTAT) = ui32Value; -} - -//***************************************************************************** -// -//! Queries the current Ethernet MAC remote wake-up configuration. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function allows the MAC's remote wake-up settings to be queried. -//! These settings determine which types of frame should trigger a remote -//! wake-up event -//! -//! \return Returns a logical OR of the following flags: -//! -//! - \b EMAC_PMT_GLOBAL_UNICAST_ENABLE indicates that the MAC wakes up when -//! any unicast frame matching the MAC destination address filter is received. -//! - \b EMAC_PMT_WAKEUP_PACKET_ENABLE indicates that the MAC wakes up when any -//! received frame matches the remote wake-up filter configured via a call -//! to EMACRemoteWakeUpFrameFilterSet(). -//! - \b EMAC_PMT_MAGIC_PACKET_ENABLE indicates that the MAC wakes up when a -//! standard Wake-on-LAN "magic packet" is received. The magic packet contains -//! 6 bytes of 0xFF followed immediately by 16 repetitions of the destination -//! MAC address. -//! - \b EMAC_PMT_POWER_DOWN indicates that the MAC is currently in power-down -//! mode and is waiting for an incoming frame matching the remote wake-up -//! frames as described by other returned flags and via the remote wake-up -//! filter. -// -//***************************************************************************** -uint32_t -EMACPowerManagementControlGet(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Read the control/status register and mask off the control bits to return - // them to the caller. - // - return(HWREG(ui32Base + EMAC_O_PMTCTLSTAT) & - (EMAC_PMTCTLSTAT_GLBLUCAST | EMAC_PMTCTLSTAT_WUPFREN | - EMAC_PMTCTLSTAT_MGKPKTEN | EMAC_PMTCTLSTAT_PWRDWN)); -} - -//***************************************************************************** -// -//! Queries the current Ethernet MAC remote wake-up status. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function returns information on the remote wake-up state of the -//! Ethernet MAC. If the MAC has been woken up since the last call, the -//! returned value indicates the type of received frame that caused the MAC -//! to exit power-down state. -//! -//! \return Returns a logical OR of the following flags: -//! -//! - \b EMAC_PMT_POWER_DOWN indicates that the MAC is currently in power-down -//! mode. -//! - \b EMAC_PMT_WAKEUP_PACKET_RECEIVED indicates that the MAC exited -//! power-down mode due to a remote wake-up frame being received. This -//! function call clears this flag. -//! - \b EMAC_PMT_MAGIC_PACKET_RECEIVED indicates that the MAC exited -//! power-down mode due to a wake-on-LAN magic packet being received. This -//! function call clears this flag. -// -//***************************************************************************** -uint32_t -EMACPowerManagementStatusGet(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Read the control/status register and mask off the status bits to return - // them to the caller. - // - return(HWREG(ui32Base + EMAC_O_PMTCTLSTAT) & - (EMAC_PMTCTLSTAT_WUPRX | EMAC_PMTCTLSTAT_MGKPRX | - EMAC_PMTCTLSTAT_PWRDWN)); -} - -//***************************************************************************** -// -//! Enables the wake-on-LAN feature of the MAC controller. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to enable the wake-on-LAN feature of the MAC -//! controller. It is done by first checking if the transmit path is idle and -//! disabling the trasnmitter and the transmit DMA controller. Then it checks -//! if any data from the network is being actively received and if not then it -//! disables the receive DMA controller. -//! -//! \return None. -// -//***************************************************************************** -void -EMACWoLEnter(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Check if the Transmit interrupt bit is clear. - // - while(HWREG(ui32Base + EMAC_O_DMARIS) == EMAC_DMARIS_TI) - { - } - - // - // Disable transmission in the MAC configuration register. - // - HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_TE; - - // - // Disable the MAC transmit path in the opmode register. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_ST; - - // - // Check if the Receive FIFO is empty. - // - while((HWREG(ui32Base + EMAC_O_STATUS) & EMAC_STATUS_RX_FIFO_LEVEL_MASK) == - EMAC_STATUS_RX_FIFO_EMPTY) - { - } - - // - // Disable the MAC receive path. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_SR; -} - -//***************************************************************************** -// -//! Configures the LPI timers and control register. -//! -//! \param ui32Base is the base address of the controller. -//! \param bLPIConfig is state of LPI trasnmit automate bit. -//! \param ui16LPILSTimer is the value of LS timer in milli-seconds. -//! \param ui16LPITWTimer is the value of TW timer in micro-seconds. -//! -//! This function is used to configure the LPI timer and control registers when -//! the link is established as EEE mode or when the link is lost. When the link -//! is established as EEE, then \e ui16LPILSTimer is programmed as the link -//! status timer value and \e ui16LPITWTimer is programmed as the transmit wait -//! timer value. The parameter \e bLPIConfig is used to decide if the transmit -//! path must be automated or should be under user control. -//! -//! \return None. -// -//***************************************************************************** -void -EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig, uint16_t ui16LPILSTimer, - uint16_t ui16LPITWTimer) -{ - uint32_t ui32TimerValue; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - ui32TimerValue = ((ui16LPILSTimer << EMAC_LPITIMERCTL_LST_S) & - EMAC_LPITIMERCTL_LST_M); - ui32TimerValue |= ui16LPITWTimer & EMAC_LPITIMERCTL_TWT_M; - - // - // Update the LPI Timer. - // - HWREG(ui32Base + EMAC_O_LPITIMERCTL) = ui32TimerValue; - - // - // Configure the LPI Control registers. - // - if(bLPIConfig) - { - HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_LPITXA; - } - else - { - HWREG(ui32Base + EMAC_O_LPICTLSTAT) = 0x0; - } -} - -//***************************************************************************** -// -//! Enables the transmit path for LPI mode entry. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to enable the transmit path in LPI mode when there -//! is no more data to be transmitted by the MAC controller. -//! -//! \return None. -// -//***************************************************************************** -void -EMACLPIEnter(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_LPIEN; -} - -//***************************************************************************** -// -//! Returns the status of the LPI link. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be used to read the status of the transmit and receive -//! path when the link is configured in LPI mode. -//! -//! \return Returns the lower 16 bits of the LPI Control and Status register. -// -//***************************************************************************** -uint16_t -EMACLPIStatus(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Configure the LPI Control registers. - // - return(HWREG(ui32Base + EMAC_O_LPICTLSTAT) & 0xFFFF); -} - -//***************************************************************************** -// -//! Sets the link status of the external PHY. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to set the link status of the external PHY when the -//! link is established in EEE mode. -//! -//! \return None. -// -//***************************************************************************** -void -EMACLPILinkSet(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Configure the LPI Control registers. - // - HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_PLS; -} - -//***************************************************************************** -// -//! Clears the link status of the external PHY. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to clear the link status of the external PHY when the -//! link is lost due to a disconnect or EEE mode link is not established. -//! -//! \return None. -// -//***************************************************************************** -void -EMACLPILinkClear(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Configure the LPI Control registers. - // - HWREG(ui32Base + EMAC_O_LPICTLSTAT) &= ~(EMAC_LPICTLSTAT_PLS); -} - -//***************************************************************************** -// -//! Writes a value to an extended PHY register in MMD address space. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui16RegAddr is the address of the PHY extended register to be -//! accessed. -//! \param ui16Value is the value to write to the register. -//! -//! When uhen connected to an external PHY supporting extended registers in MMD -//! address space, this function allows a value to be written to the MMD -//! register specified by \e ui16RegAddr. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr, - uint16_t ui16Data) -{ - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - - // - // Set the address of the register we're about to write. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, DEV_ADDR(ui16RegAddr)); - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_ADDAR, REG_ADDR(ui16RegAddr)); - - // - // Write the extended register value. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, - (0x4000 | DEV_ADDR(ui16RegAddr))); - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, ui16Data); -} - -//***************************************************************************** -// -//! Reads from an extended PHY register in MMD address space. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui16RegAddr is the address of the PHY extended register to be -//! accessed. -//! -//! When connected to an external PHY supporting extended registers, this -//! this function returns the contents of the MMD register specified by -//! \e ui16RegAddr. -//! -//! \return Returns the 16-bit value read from the PHY. -// -//***************************************************************************** -uint16_t -EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr) -{ - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - - // - // Set the address of the register we're about to read. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, DEV_ADDR(ui16RegAddr)); - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_ADDAR, REG_ADDR(ui16RegAddr)); - - // - // Read the extended register value. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, - (0x4000 | DEV_ADDR(ui16RegAddr))); - return(EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_ADDAR)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/emac.h b/bsp/tm4c129x-dk/libraries/driverlib/emac.h deleted file mode 100644 index f82919c8c0b971ef3abfe82119b74b8a320d7d93..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/emac.h +++ /dev/null @@ -1,1041 +0,0 @@ -//***************************************************************************** -// -// emac.h - Defines and Macros for the Ethernet module on Snowflake-class -// devices. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_EMAC_H__ -#define __DRIVERLIB_EMAC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup emac_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// The physical address of the internal PHY. This should be in hw_emac.h. -// -//***************************************************************************** -#define EMAC_PHY_ADDR 0 - -//***************************************************************************** -// -// Helper Macros for Ethernet Processing -// -//***************************************************************************** -// -// htonl/ntohl - Big endian/little endian byte swapping macros for 32-bit -// values. -// -//***************************************************************************** -#ifndef htonl - #define htonl(a) \ - ((((a) >> 24) & 0x000000ff) | \ - (((a) >> 8) & 0x0000ff00) | \ - (((a) << 8) & 0x00ff0000) | \ - (((a) << 24) & 0xff000000)) -#endif - -#ifndef ntohl - #define ntohl(a) htonl((a)) -#endif - -//***************************************************************************** -// -// htons/ntohs - Big endian/little endian byte swapping macros for 16-bit -// values. -// -//***************************************************************************** -#ifndef htons - #define htons(a) \ - ((((a) >> 8) & 0x00ff) | \ - (((a) << 8) & 0xff00)) -#endif - -#ifndef ntohs - #define ntohs(a) htons((a)) -#endif - -//***************************************************************************** -// -// Forward reference to the Ethernet DMA descriptor structure. -// -//***************************************************************************** -typedef struct tEMACDMADescriptor tEMACDMADescriptor; - -//***************************************************************************** -// -//! A union used to describe the two overlapping fields forming the third -//! word of the Ethernet DMA descriptor. -// -//***************************************************************************** -typedef union -{ - // - //! When DMA descriptors are used in chained mode, this field is used to - //! provide a link to the next descriptor. - // - tEMACDMADescriptor *pLink; - - // - //! When the DMA descriptors are unchained, this field may be used to point - //! to a second buffer containing data for transmission or providing - //! storage for a received frame. - // - void *pvBuffer2; -} -tEMACDES3; - -//***************************************************************************** -// -//! A structure defining a single Ethernet DMA buffer descriptor. -// -//***************************************************************************** -struct tEMACDMADescriptor -{ - // - //! The first DMA descriptor word contains various control and status bits - //! depending upon whether the descriptor is in the transmit or receive - //! queue. Bit 31 is always the ``OWN'' bit which, when set, indicates - //! that the hardware has control of the descriptor. - // - volatile uint32_t ui32CtrlStatus; - - // - //! The second descriptor word contains information on the size of the - //! buffer or buffers attached to the descriptor and various additional - //! control bits. - // - volatile uint32_t ui32Count; - - // - //! The third descriptor word contains a pointer to the buffer containing - //! data to transmit or into which received data should be written. This - //! pointer must refer to a buffer in internal SRAM. Pointers to flash or - //! EPI-connected memory may not be used and will result in the MAC - //! reporting a bus error. - // - void *pvBuffer1; - - // - //! The fourth descriptor word contains either a pointer to the next - //! descriptor in the ring or a pointer to a second data buffer. The - //! meaning of the word is controlled by the ``CHAINED'' control bit which - //! appears in the first word of the transmit descriptor or the second - //! word of the receive descriptor. - //! - tEMACDES3 DES3; - - // - //! The fifth descriptor word is reserved for transmit descriptors but - //! used to report extended status in a receive descriptor. - // - volatile uint32_t ui32ExtRxStatus; - - // - //! The sixth descriptor word is reserved for both transmit and receive - //! descriptors. - // - uint32_t ui32Reserved; - - // - //! The seventh descriptor word contains the low 32 bits of the 64-bit - //! timestamp captured for transmitted or received data. The value is set - //! only when the transmitted or received data contains the end of a - //! packet. Availability of the timestamp is indicated via a status bit - //! in the first descriptor word. - // - volatile uint32_t ui32IEEE1588TimeLo; - - // - //! The eighth descriptor word contains the high 32 bits of the 64-bit - //! timestamp captured for transmitted or received data. - // - volatile uint32_t ui32IEEE1588TimeHi; -}; - -//***************************************************************************** -// -// Fields found in the DES0 word of the transmit descriptor (ui32CtrlStatus in -// tEMACDMADescriptor) -// -//***************************************************************************** -#define DES0_TX_CTRL_OWN 0x80000000 -#define DES0_TX_CTRL_INTERRUPT 0x40000000 -#define DES0_TX_CTRL_LAST_SEG 0x20000000 -#define DES0_TX_CTRL_FIRST_SEG 0x10000000 - -// -// This value indicates that the MAC should not append a CRC to transmitted -// packets. If used with DES0_TX_CTRL_REPLACE_CRC, the last 4 bytes of the -// packet passed to the transmitter are replaced with a newly calculated CRC. -// If DES0_TX_CTRL_REPLACE_CRC is not specified, it is assumed that packets -// transmitted have valid CRCs precomputed and included in the frame data. -// -// If DES0_TX_CTRL_DISABLE_CRC is not specified, the MAC will calculate the -// CRC for all frames transmitted and append this value as the 4-byte FCS -// after the last data byte in the frame. -// -#define DES0_TX_CTRL_DISABLE_CRC 0x08000000 -#define DES0_TX_CTRL_DISABLE_PADDING 0x04000000 -#define DES0_TX_CTRL_ENABLE_TS 0x02000000 - -// -// This value is only valid if used alongside DES0_TX_CTRL_DISABLE_CRC. When -// specified, the MAC will replace the last 4 bytes of a transmitted frame -// with a newly calculated CRC. -// -#define DES0_TX_CTRL_REPLACE_CRC 0x01000000 -#define DES0_TX_CTRL_CHKSUM_M 0x00C00000 -#define DES0_TX_CTRL_NO_CHKSUM 0x00000000 -#define DES0_TX_CTRL_IP_HDR_CHKSUM 0x00400000 -#define DES0_TX_CTRL_IP_HDR_PAY_CHKSUM 0x00800000 -#define DES0_TX_CTRL_IP_ALL_CKHSUMS 0x00C00000 -#define DES0_TX_CTRL_END_OF_RING 0x00200000 -#define DES0_TX_CTRL_CHAINED 0x00100000 -#define DES0_TX_CTRL_VLAN_M 0x000C0000 -#define DES0_TX_CTRL_VLAN_NONE 0x00000000 -#define DES0_TX_CTRL_VLAN_REMOVE 0x00040000 -#define DES0_TX_CTRL_VLAN_INSERT 0x00080000 -#define DES0_TX_CTRL_VLAN_REPLACE 0x000C0000 -#define DES0_TX_STAT_TS_CAPTURED 0x00020000 -#define DES0_TX_STAT_IPH_ERR 0x00010000 -#define DES0_TX_STAT_ERR 0x00008000 -#define DES0_TX_STAT_JABBER_TO 0x00004000 -#define DES0_TX_STAT_FLUSHED 0x00002000 -#define DES0_TX_STAT_PAYLOAD_ERR 0x00001000 -#define DES0_TX_STAT_CARRIER_LOST 0x00000800 -#define DES0_TX_STAT_NO_CARRIER 0x00000400 -#define DES0_TX_STAT_TX_L_COLLISION 0x00000200 -#define DES0_TX_STAT_E_COLLISION 0x00000100 -#define DES0_TX_STAT_VLAN_FRAME 0x00000080 -#define DES0_TX_STAT_COL_COUNT_M 0x00000078 -#define DES0_TX_STAT_COL_COUNT_S 3 -#define DES0_TX_STAT_E_DEFERRAL 0x00000004 -#define DES0_TX_STAT_UNDERFLOW 0x00000002 -#define DES0_TX_STAT_DEFERRED 0x00000001 - -//***************************************************************************** -// -// Fields found in the DES1 word of the transmit descriptor (ui32Count in -// tEMACDMADescriptor) -// -//***************************************************************************** -#define DES1_TX_CTRL_SADDR_MAC1 0x80000000 -#define DES1_TX_CTRL_SADDR_M 0x60000000 -#define DES1_TX_CTRL_SADDR_NONE 0x00000000 -#define DES1_TX_CTRL_SADDR_INSERT 0x20000000 -#define DES1_TX_CTRL_SADDR_REPLACE 0x40000000 -#define DES1_TX_CTRL_BUFF2_SIZE_M 0x1FFF0000 -#define DES1_TX_CTRL_BUFF1_SIZE_M 0x00001FFF -#define DES1_TX_CTRL_BUFF2_SIZE_S 16 -#define DES1_TX_CTRL_BUFF1_SIZE_S 0 - -//***************************************************************************** -// -// Fields found in the DES0 word of the receive descriptor (ui32CtrlStatus in -// tEMACDMADescriptor) -// -//***************************************************************************** -#define DES0_RX_CTRL_OWN 0x80000000 -#define DES0_RX_STAT_DEST_ADDR_FAIL 0x40000000 -#define DES0_RX_STAT_FRAME_LENGTH_M 0x3FFF0000 -#define DES0_RX_STAT_FRAME_LENGTH_S 16 -#define DES0_RX_STAT_ERR 0x00008000 -#define DES0_RX_STAT_DESCRIPTOR_ERR 0x00004000 -#define DES0_RX_STAT_SRC_ADDR_FAIL 0x00002000 -#define DES0_RX_STAT_LENGTH_ERR 0x00001000 -#define DES0_RX_STAT_OVERFLOW 0x00000800 -#define DES0_RX_STAT_VLAN_TAG 0x00000400 -#define DES0_RX_STAT_FIRST_DESC 0x00000200 -#define DES0_RX_STAT_LAST_DESC 0x00000100 -#define DES0_RX_STAT_TS_AVAILABLE 0x00000080 -#define DES0_RX_STAT_RX_L_COLLISION 0x00000040 -#define DES0_RX_STAT_FRAME_TYPE 0x00000020 -#define DES0_RX_STAT_WDOG_TIMEOUT 0x00000010 -#define DES0_RX_STAT_RX_ERR 0x00000008 -#define DES0_RX_STAT_DRIBBLE_ERR 0x00000004 -#define DES0_RX_STAT_CRC_ERR 0x00000002 -#define DES0_RX_STAT_MAC_ADDR 0x00000001 -#define DES0_RX_STAT_EXT_AVAILABLE 0x00000001 - -//***************************************************************************** -// -// Fields found in the DES1 word of the receive descriptor (ui32Count in -// tEMACDMADescriptor) -// -//***************************************************************************** -#define DES1_RX_CTRL_DISABLE_INT 0x80000000 -#define DES1_RX_CTRL_BUFF2_SIZE_M 0x1FFF0000 -#define DES1_RX_CTRL_BUFF2_SIZE_S 16 -#define DES1_RX_CTRL_END_OF_RING 0x00008000 -#define DES1_RX_CTRL_CHAINED 0x00004000 -#define DES1_RX_CTRL_BUFF1_SIZE_M 0x00001FFF -#define DES1_RX_CTRL_BUFF1_SIZE_S 0 - -//***************************************************************************** -// -// Fields found in the DES4 word of the receive descriptor (ui32ExtRxStatus in -// tEMACDMADescriptor) -// -//***************************************************************************** -#define DES4_RX_STAT_TS_DROPPED 0x00004000 -#define DES4_RX_STAT_PTP_VERSION2 0x00002000 -#define DES4_RX_STAT_PTP_TYPE_ETH 0x00001000 -#define DES4_RX_STAT_PTP_TYPE_UDP 0x00000000 -#define DES4_RX_STAT_PTP_MT_M 0x00000F00 -#define DES4_RX_STAT_PTP_MT_NONE 0x00000000 -#define DES4_RX_STAT_PTP_MT_SYNC 0x00000100 -#define DES4_RX_STAT_PTP_MT_FOLLOW_UP 0x00000200 -#define DES4_RX_STAT_PTP_MT_DELAY_REQ 0x00000300 -#define DES4_RX_STAT_PTP_MT_DELAY_RESP 0x00000400 -#define DES4_RX_STAT_PTP_MT_PDELAY_REQ 0x00000500 -#define DES4_RX_STAT_PTP_MT_PDELAY_RESP 0x00000600 -#define DES4_RX_STAT_PTP_MT_PDELAY_RFU 0x00000700 -#define DES4_RX_STAT_PTP_MT_ANNOUNCE 0x00000800 -#define DES4_RX_STAT_PTP_MT_SIGNALLING 0x00000A00 -#define DES4_RX_STAT_PTP_MT_RESERVED 0x00000F00 -#define DES4_RX_STAT_IPV6 0x00000080 -#define DES4_RX_STAT_IPV4 0x00000040 -#define DES4_RX_STAT_IP_CHK_BYPASSED 0x00000020 -#define DES4_RX_STAT_IP_PAYLOAD_ERR 0x00000010 -#define DES4_RX_STAT_IP_HEADER_ERR 0x00000008 -#define DES4_RX_STAT_PAYLOAD_M 0x00000007 -#define DES4_RX_STAT_PAYLOAD_UNKNOWN 0x00000000 -#define DES4_RX_STAT_PAYLOAD_UDP 0x00000001 -#define DES4_RX_STAT_PAYLOAD_TCP 0x00000002 -#define DES4_RX_STAT_PAYLOAD_ICMP 0x00000003 - -//***************************************************************************** -// -// Values used in the ui32BusConfig parameter to EMACInit(). -// -//*************************************************************************** -#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_M 0x30000000 -#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_1 0x00000000 -#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_2 0x10000000 -#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_3 0x20000000 -#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_4 0x30000000 -#define EMAC_BCONFIG_TX_PRIORITY 0x08000000 -#define EMAC_BCONFIG_ADDR_ALIGNED 0x02000000 -#define EMAC_BCONFIG_PRIORITY_M 0x0000C000 -#define EMAC_BCONFIG_PRIORITY_1_1 (0 << 14) -#define EMAC_BCONFIG_PRIORITY_2_1 (1 << 14) -#define EMAC_BCONFIG_PRIORITY_3_1 (2 << 14) -#define EMAC_BCONFIG_PRIORITY_4_1 (3 << 14) -#define EMAC_BCONFIG_PRIORITY_FIXED 0x00000002 -#define EMAC_BCONFIG_FIXED_BURST 0x00010000 -#define EMAC_BCONFIG_MIXED_BURST 0x04000000 - -//***************************************************************************** -// -// Options used in the ui32Config parameter to EMACPHYConfigSet(). -// -//***************************************************************************** -#define EMAC_PHY_TYPE_INTERNAL 0x00000000 -#define EMAC_PHY_TYPE_EXTERNAL_MII 0x80000000 -#define EMAC_PHY_TYPE_EXTERNAL_RMII 0xC0000000 -#define EMAC_PHY_INT_NIB_TXERR_DET_DIS 0x01000000 -#define EMAC_PHY_INT_RX_ER_DURING_IDLE 0x00800000 -#define EMAC_PHY_INT_ISOLATE_MII_LLOSS 0x00400000 -#define EMAC_PHY_INT_LINK_LOSS_RECOVERY 0x00200000 -#define EMAC_PHY_INT_TDRRUN 0x00100000 -#define EMAC_PHY_INT_LD_ON_RX_ERR_COUNT 0x00040000 -#define EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT 0x00020000 -#define EMAC_PHY_INT_LD_ON_LOW_SNR 0x00010000 -#define EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY 0x00008000 -#define EMAC_PHY_INT_POLARITY_SWAP 0x00004000 -#define EMAC_PHY_INT_MDI_SWAP 0x00002000 -#define EMAC_PHY_INT_ROBUST_MDIX 0x00001000 -#define EMAC_PHY_INT_FAST_MDIX 0x00000800 -#define EMAC_PHY_INT_MDIX_EN 0x00000400 -#define EMAC_PHY_INT_FAST_RXDV_DETECT 0x00000200 -#define EMAC_PHY_INT_FAST_L_UP_DETECT 0x00000100 -#define EMAC_PHY_INT_EXT_FULL_DUPLEX 0x00000080 -#define EMAC_PHY_INT_FAST_AN_80_50_35 0x00000040 -#define EMAC_PHY_INT_FAST_AN_120_75_50 0x00000050 -#define EMAC_PHY_INT_FAST_AN_140_150_100 0x00000060 -#define EMAC_PHY_FORCE_10B_T_HALF_DUPLEX 0x00000000 -#define EMAC_PHY_FORCE_10B_T_FULL_DUPLEX 0x00000002 -#define EMAC_PHY_FORCE_100B_T_HALF_DUPLEX 0x00000004 -#define EMAC_PHY_FORCE_100B_T_FULL_DUPLEX 0x00000006 -#define EMAC_PHY_AN_10B_T_HALF_DUPLEX 0x00000008 -#define EMAC_PHY_AN_10B_T_FULL_DUPLEX 0x0000000A -#define EMAC_PHY_AN_100B_T_HALF_DUPLEX 0x0000000C -#define EMAC_PHY_AN_100B_T_FULL_DUPLEX 0x0000000E -#define EMAC_PHY_INT_HOLD 0x00000001 - -#define EMAC_PHY_TYPE_MASK 0xC0000000 - -//***************************************************************************** -// -// Options used in the ui32Config parameter to EMACConfigSet(). -// -//***************************************************************************** -#define EMAC_CONFIG_USE_MACADDR1 0x40000000 -#define EMAC_CONFIG_USE_MACADDR0 0x00000000 -#define EMAC_CONFIG_SA_FROM_DESCRIPTOR 0x00000000 -#define EMAC_CONFIG_SA_INSERT 0x20000000 -#define EMAC_CONFIG_SA_REPLACE 0x30000000 -#define EMAC_CONFIG_2K_PACKETS 0x08000000 -#define EMAC_CONFIG_STRIP_CRC 0x02000000 -#define EMAC_CONFIG_JABBER_DISABLE 0x00400000 -#define EMAC_CONFIG_JUMBO_ENABLE 0x00100000 -#define EMAC_CONFIG_IF_GAP_MASK 0x000E0000 -#define EMAC_CONFIG_IF_GAP_96BITS (0x0 << 17) -#define EMAC_CONFIG_IF_GAP_88BITS (0x1 << 17) -#define EMAC_CONFIG_IF_GAP_80BITS (0x2 << 17) -#define EMAC_CONFIG_IF_GAP_72BITS (0x3 << 17) -#define EMAC_CONFIG_IF_GAP_64BITS (0x4 << 17) -#define EMAC_CONFIG_IF_GAP_56BITS (0x5 << 17) -#define EMAC_CONFIG_IF_GAP_48BITS (0x6 << 17) -#define EMAC_CONFIG_IF_GAP_40BITS (0x7 << 17) -#define EMAC_CONFIG_CS_DISABLE 0x00010000 -#define EMAC_CONFIG_100MBPS 0x00004000 -#define EMAC_CONFIG_10MBPS 0x00000000 -#define EMAC_CONFIG_RX_OWN_DISABLE 0x00002000 -#define EMAC_CONFIG_LOOPBACK 0x00001000 -#define EMAC_CONFIG_FULL_DUPLEX 0x00000800 -#define EMAC_CONFIG_HALF_DUPLEX 0x00000000 -#define EMAC_CONFIG_CHECKSUM_OFFLOAD 0x00000400 -#define EMAC_CONFIG_RETRY_DISABLE 0x00000200 -#define EMAC_CONFIG_AUTO_CRC_STRIPPING 0x00000080 -#define EMAC_CONFIG_BO_MASK 0x00000060 -#define EMAC_CONFIG_BO_LIMIT_1024 (0x0 << 5) -#define EMAC_CONFIG_BO_LIMIT_256 (0x1 << 5) -#define EMAC_CONFIG_BO_LIMIT_16 (0x2 << 5) -#define EMAC_CONFIG_BO_LIMIT_2 (0x3 << 5) -#define EMAC_CONFIG_DEFERRAL_CHK_ENABLE 0x00000010 -#define EMAC_CONFIG_PREAMBLE_MASK 0x00000003 -#define EMAC_CONFIG_7BYTE_PREAMBLE 0x00000000 -#define EMAC_CONFIG_5BYTE_PREAMBLE 0x00000001 -#define EMAC_CONFIG_3BYTE_PREAMBLE 0x00000002 - -//***************************************************************************** -// -// Options used in the ui32ModeFlags parameter to EMACConfigSet(). -// -//***************************************************************************** -#define EMAC_MODE_KEEP_BAD_CRC 0x04000000 -#define EMAC_MODE_RX_STORE_FORWARD 0x02000000 -#define EMAC_MODE_RX_FLUSH_DISABLE 0x01000000 -#define EMAC_MODE_TX_STORE_FORWARD 0x00200000 -#define EMAC_MODE_TX_THRESHOLD_16_BYTES (7 << 14) -#define EMAC_MODE_TX_THRESHOLD_24_BYTES (6 << 14) -#define EMAC_MODE_TX_THRESHOLD_32_BYTES (5 << 14) -#define EMAC_MODE_TX_THRESHOLD_40_BYTES (4 << 14) -#define EMAC_MODE_TX_THRESHOLD_64_BYTES (0 << 14) -#define EMAC_MODE_TX_THRESHOLD_128_BYTES (1 << 14) -#define EMAC_MODE_TX_THRESHOLD_192_BYTES (2 << 14) -#define EMAC_MODE_TX_THRESHOLD_256_BYTES (3 << 14) -#define EMAC_MODE_RX_ERROR_FRAMES 0x00000080 -#define EMAC_MODE_RX_UNDERSIZED_FRAMES 0x00000040 -#define EMAC_MODE_RX_THRESHOLD_64_BYTES (0 << 3) -#define EMAC_MODE_RX_THRESHOLD_32_BYTES (1 << 3) -#define EMAC_MODE_RX_THRESHOLD_96_BYTES (2 << 3) -#define EMAC_MODE_RX_THRESHOLD_128_BYTES (3 << 3) -#define EMAC_MODE_OPERATE_2ND_FRAME 0x00000002 - -//***************************************************************************** -// -// These two values may be returned by EMACConfigGet() in the *pui32Config -// parameter. The transmitter and receiver are, however, enabled and disabled -// using independent functions, EMACTxEnable/Disable() and -// EMACRxEnable/Disable(). -// -//***************************************************************************** -#define EMAC_CONFIG_TX_ENABLED 0x00000008 -#define EMAC_CONFIG_RX_ENABLED 0x00000004 - -//***************************************************************************** -// -// These two values may be returned by EMACConfigGet() in the *pui32Mode -// parameter. The transmit and receive DMA channels are, however, enabled and -// disabled using independent functions, EMACTxEnable/Disable() and -// EMACRxEnable/Disable(). -// -//***************************************************************************** -#define EMAC_MODE_TX_DMA_ENABLED 0x00002000 -#define EMAC_MODE_RX_DMA_ENABLED 0x00000002 - -//***************************************************************************** -// -// These values may be passed to EMACFrameFilterSet() in the ui32FilterOpts -// parameter, and are returned by EMACFrameFilterGet(). -// -//***************************************************************************** -#define EMAC_FRMFILTER_RX_ALL 0x80000000 -#define EMAC_FRMFILTER_VLAN 0x00010000 -#define EMAC_FRMFILTER_HASH_AND_PERFECT 0x00000400 -#define EMAC_FRMFILTER_SADDR 0x00000200 -#define EMAC_FRMFILTER_INV_SADDR 0x00000100 -#define EMAC_FRMFILTER_PASS_MASK (0x03 << 6) -#define EMAC_FRMFILTER_PASS_NO_CTRL (0x00 << 6) -#define EMAC_FRMFILTER_PASS_NO_PAUSE (0x01 << 6) -#define EMAC_FRMFILTER_PASS_ALL_CTRL (0x02 << 6) -#define EMAC_FRMFILTER_PASS_ADDR_CTRL (0x03 << 6) -#define EMAC_FRMFILTER_BROADCAST 0x00000020 -#define EMAC_FRMFILTER_PASS_MULTICAST 0x00000010 -#define EMAC_FRMFILTER_INV_DADDR 0x00000008 -#define EMAC_FRMFILTER_HASH_MULTICAST 0x00000004 -#define EMAC_FRMFILTER_HASH_UNICAST 0x00000002 -#define EMAC_FRMFILTER_PROMISCUOUS 0x00000001 - -//***************************************************************************** -// -// Values which may be returned by EMACStatusGet(). -// -//***************************************************************************** -#define EMAC_STATUS_TX_NOT_EMPTY 0x01000000 -#define EMAC_STATUS_TX_WRITING_FIFO 0x00400000 -#define EMAC_STATUS_TRC_STATE_MASK 0x00300000 -#define EMAC_STATUS_TRC_STATE_IDLE (0x00 << 20) -#define EMAC_STATUS_TRC_STATE_READING (0x01 << 20) -#define EMAC_STATUS_TRC_STATE_WAITING (0x02 << 20) -#define EMAC_STATUS_TRC_STATE_STATUS (0x03 << 20) -#define EMAC_STATUS_TX_PAUSED 0x00080000 -#define EMAC_STATUS_TFC_STATE_MASK 0x00060000 -#define EMAC_STATUS_TFC_STATE_IDLE (0x00 << 17) -#define EMAC_STATUS_TFC_STATE_WAITING (0x01 << 17) -#define EMAC_STATUS_TFC_STATE_PAUSING (0x02 << 17) -#define EMAC_STATUS_TFC_STATE_WRITING (0x03 << 17) -#define EMAC_STATUS_MAC_NOT_IDLE 0x00010000 -#define EMAC_STATUS_RX_FIFO_LEVEL_MASK 0x00000300 -#define EMAC_STATUS_RX_FIFO_EMPTY (0x00 << 8) -#define EMAC_STATUS_RX_FIFO_BELOW (0x01 << 8) -#define EMAC_STATUS_RX_FIFO_ABOVE (0x02 << 8) -#define EMAC_STATUS_RX_FIFO_FULL (0x03 << 8) -#define EMAC_STATUS_RX_FIFO_STATE_MASK 0x00000060 -#define EMAC_STATUS_RX_FIFO_IDLE (0x00 << 5) -#define EMAC_STATUS_RX_FIFO_READING (0x01 << 5) -#define EMAC_STATUS_RX_FIFO_STATUS (0x02 << 5) -#define EMAC_STATUS_RX_FIFO_FLUSHING (0x03 << 5) -#define EMAC_STATUS_RWC_ACTIVE 0x00000010 -#define EMAC_STATUS_RPE_ACTIVE 0x00000001 - -//***************************************************************************** -// -// Values which may be returned by EMACDMAStateGet(). -// -//***************************************************************************** -#define EMAC_DMA_TXSTAT_MASK (0x07 << 20) -#define EMAC_DMA_TXSTAT_STOPPED (0x00 << 20) -#define EMAC_DMA_TXSTAT_RUN_FETCH_DESC (0x01 << 20) -#define EMAC_DMA_TXSTAT_RUN_WAIT_STATUS (0x02 << 20) -#define EMAC_DMA_TXSTAT_RUN_READING (0x03 << 20) -#define EMAC_DMA_TXSTAT_RUN_CLOSE_DESC (0x07 << 20) -#define EMAC_DMA_TXSTAT_TS_WRITE (0x04 << 20) -#define EMAC_DMA_TXSTAT_SUSPENDED (0x06 << 20) - -#define EMAC_DMA_RXSTAT_MASK (0x07 << 17) -#define EMAC_DMA_RXSTAT_STOPPED (0x00 << 17) -#define EMAC_DMA_RXSTAT_RUN_FETCH_DESC (0x01 << 17) -#define EMAC_DMA_RXSTAT_RUN_WAIT_PACKET (0x03 << 17) -#define EMAC_DMA_RXSTAT_SUSPENDED (0x04 << 17) -#define EMAC_DMA_RXSTAT_RUN_CLOSE_DESC (0x05 << 17) -#define EMAC_DMA_RXSTAT_TS_WRITE (0x06 << 17) -#define EMAC_DMA_RXSTAT_RUN_RECEIVING (0x07 << 17) - -#define EMAC_TX_DMA_STATE(x) ((x) & EMAC_DMA_TXSTAT_MASK) -#define EMAC_RX_DMA_STATE(x) ((x) & EMAC_DMA_RXSTAT_MASK) - -#define EMAC_DMA_ERROR 0x00002000 -#define EMAC_DMA_ERR_MASK 0x03800000 -#define EMAC_DMA_ERR_RX_DATA_WRITE 0x00000000 -#define EMAC_DMA_ERR_TX_DATA_READ 0x01800000 -#define EMAC_DMA_ERR_RX_DESC_WRITE 0x02000000 -#define EMAC_DMA_ERR_TX_DESC_WRITE 0x02800000 -#define EMAC_DMA_ERR_RX_DESC_READ 0x03000000 -#define EMAC_DMA_ERR_TX_DESC_READ 0x03800000 - -//***************************************************************************** -// -// Values which may be ORed together in the ui32Config parameter passed to -// EMACAddrFilterSet and which may be returned by EMACAddrFilterGet. -// -//***************************************************************************** -#define EMAC_FILTER_ADDR_ENABLE 0x80000000 -#define EMAC_FILTER_SOURCE_ADDR 0x40000000 -#define EMAC_FILTER_MASK_BYTE_6 0x20000000 -#define EMAC_FILTER_MASK_BYTE_5 0x10000000 -#define EMAC_FILTER_MASK_BYTE_4 0x08000000 -#define EMAC_FILTER_MASK_BYTE_3 0x04000000 -#define EMAC_FILTER_MASK_BYTE_2 0x03000000 -#define EMAC_FILTER_MASK_BYTE_1 0x01000000 - -#define EMAC_FILTER_BYTE_MASK_M 0x3F000000 -#define EMAC_FILTER_BYTE_MASK_S 24 - -//***************************************************************************** -// -// Flags passed to EMACTimestampConfigSet or returned from -// EMACTimestampConfigGet. -// -//***************************************************************************** -#define EMAC_TS_MAC_FILTER_ENABLE 0x00040000 -#define EMAC_TS_MAC_FILTER_DISABLE 0x00000000 -#define EMAC_TS_SYNC_FOLLOW_DREQ_DRESP 0x00000000 -#define EMAC_TS_SYNC_ONLY 0x00004000 -#define EMAC_TS_DELAYREQ_ONLY 0x0000C000 -#define EMAC_TS_ALL 0x00010000 -#define EMAC_TS_SYNC_PDREQ_PDRESP 0x00014000 -#define EMAC_TS_DREQ_PDREQ_PDRESP 0x0001C000 -#define EMAC_TS_SYNC_DELAYREQ 0x00020000 -#define EMAC_TS_PDREQ_PDRESP 0x00030000 -#define EMAC_TS_PROCESS_IPV4_UDP 0x00002000 -#define EMAC_TS_PROCESS_IPV6_UDP 0x00001000 -#define EMAC_TS_PROCESS_ETHERNET 0x00000800 -#define EMAC_TS_PTP_VERSION_2 0x00000400 -#define EMAC_TS_PTP_VERSION_1 0x00000000 -#define EMAC_TS_DIGITAL_ROLLOVER 0x00000200 -#define EMAC_TS_BINARY_ROLLOVER 0x00000000 -#define EMAC_TS_ALL_RX_FRAMES 0x00000100 -#define EMAC_TS_UPDATE_FINE 0x00000002 -#define EMAC_TS_UPDATE_COARSE 0x00000000 - -//***************************************************************************** -// -// Some register bit definitions relating to external PHYs. These are not -// relevant (or available) when using the internal Ethernet PHY but having -// the definitions here helps when using an external MII or RMII PHY. -// -//***************************************************************************** -#define EPHY_SCR_INPOL_EXT 0x00000008 -#define EPHY_SCR_TINT_EXT 0x00000004 -#define EPHY_SCR_INTEN_EXT 0x00000002 -#define EPHY_SCR_INTOE_EXT 0x00000001 - -//***************************************************************************** -// -// These interrupt sources may be passed to EMACIntEnable() and -// EMACIntDisable() to enable or disable various Ethernet interrupt sources. -// -//***************************************************************************** -// -// Note that interrupts relating to timestamping and power management must be -// independently enabled via calls to functions EMACTimestampTargetIntEnable -// and EMACPowerManagementControlSet. -// -// EMAC_INT_PHY is deliberately set to a reserved bit in the MAC interrupt -// register. We handle the fact that the PHY interrupt is controlled via an -// independent register within the code. If we didn't do this, the app would -// have to enable the MAC interrupt then enable the PHY interrupt via a -// different API (since they share a vector). To further complicate matters, -// they would have to call EMACIntStatus() and then, if it returned 0, -// read the PHY interrupt status to see that it fired. This would be nasty -// and unfriendly so we hide it inside DriverLib. -// -//***************************************************************************** -#define EMAC_INT_PHY 0x80000000 -#define EMAC_INT_EARLY_RECEIVE 0x00004000 -#define EMAC_INT_BUS_ERROR 0x00002000 -#define EMAC_INT_EARLY_TRANSMIT 0x00000400 -#define EMAC_INT_RX_WATCHDOG 0x00000200 -#define EMAC_INT_RX_STOPPED 0x00000100 -#define EMAC_INT_RX_NO_BUFFER 0x00000080 -#define EMAC_INT_RECEIVE 0x00000040 -#define EMAC_INT_TX_UNDERFLOW 0x00000020 -#define EMAC_INT_RX_OVERFLOW 0x00000010 -#define EMAC_INT_TX_JABBER 0x00000008 -#define EMAC_INT_TX_NO_BUFFER 0x00000004 -#define EMAC_INT_TX_STOPPED 0x00000002 -#define EMAC_INT_TRANSMIT 0x00000001 - -// -// These interrupt sources are summary indicators. They are readable -// using EMACIntStatus() and must be cleared using EMACIntClear(). They -// may be enabled or disabled independently of the group of interrupts that -// they are derived from but offer merely a simple way to be informed of a -// normal or abnormal condition requiring software attention. -// -// EMAC_INT_NORMAL_INT is the logical OR of the masked state of -// EMAC_INT_TRANSMIT | EMAC_INT_RECEIVE | EMAC_INT_TX_NO_BUFFER | -// EMAC_INT_EARLY_RECEIVE. -// -// EMAC_INT_ABNORMAL_INT is the logical OR of the masked state of -// EMAC_INT_TX_STOPPED | EMAC_INT_TX_JABBER | EMAC_INT_RX_OVERFLOW | -// EMAC_INT_TX_UNDERFLOW | EMAC_INT_RX_NO_BUFFER | EMAC_INT_RX_STOPPED | -// EMAC_INT_RX_WATCHDOG | EMAC_INT_EARLY_TRANSMIT | EMAC_INT_BUS_ERROR. -// -#define EMAC_INT_NORMAL_INT 0x00010000 -#define EMAC_INT_ABNORMAL_INT 0x00008000 - -// -// This interrupt source is readable using EMACIntStatus but must -// be cleared by calling the EMACEEEStatus(). -// -#define EMAC_INT_LPI 0x40000000 - -// -// This interrupt source is readable using EMACIntStatus but must -// be cleared by calling the EMACTimestampIntStatus(). -// -#define EMAC_INT_TIMESTAMP 0x20000000 - -// -// Interrupt sources which may be returned from EMACTimestampIntStatus(). -// -#define EMAC_TS_INT_TARGET_REACHED 0x00000002 -#define EMAC_TS_INT_TS_SEC_OVERFLOW 0x00000001 - -// -// This interrupt source is readable using EMACIntStatus but must -// be cleared by calling EMACPowerManagementStatusGet(). -// -#define EMAC_INT_POWER_MGMNT 0x10000000 - -//***************************************************************************** -// -// Configuration flags that may be passed in the ui32FreqConfig parameter to -// EMACTimestampPPSSimpleModeSet(). -// -//***************************************************************************** -#define EMAC_PPS_SINGLE_PULSE 0x00000000 -#define EMAC_PPS_1HZ 0x00000001 -#define EMAC_PPS_2HZ 0x00000002 -#define EMAC_PPS_4HZ 0x00000003 -#define EMAC_PPS_8HZ 0x00000004 -#define EMAC_PPS_16HZ 0x00000005 -#define EMAC_PPS_32HZ 0x00000006 -#define EMAC_PPS_64HZ 0x00000007 -#define EMAC_PPS_128HZ 0x00000008 -#define EMAC_PPS_256HZ 0x00000009 -#define EMAC_PPS_512HZ 0x0000000A -#define EMAC_PPS_1024HZ 0x0000000B -#define EMAC_PPS_2048HZ 0x0000000C -#define EMAC_PPS_4096HZ 0x0000000D -#define EMAC_PPS_8192HZ 0x0000000E -#define EMAC_PPS_16384HZ 0x0000000F -#define EMAC_PPS_32768HZ 0x00000010 - -//***************************************************************************** -// -// Configuration flags that may be passed in the ui32Config parameter to -// EMACTimestampPPSCommandModeSet(). -// -//***************************************************************************** -#define EMAC_PPS_TARGET_INT 0x00000000 -#define EMAC_PPS_TARGET_PPS 0x00000060 -#define EMAC_PPS_TARGET_BOTH 0x00000040 - -//***************************************************************************** -// -// Commands which may be passed to EMACTimestampPPSCmd. -// -//***************************************************************************** -#define EMAC_PPS_COMMAND_NONE 0x00 -#define EMAC_PPS_COMMAND_START_SINGLE 0x01 -#define EMAC_PPS_COMMAND_START_TRAIN 0x02 -#define EMAC_PPS_COMMAND_CANCEL_START 0x03 -#define EMAC_PPS_COMMAND_STOP_AT_TIME 0x04 -#define EMAC_PPS_COMMAND_STOP_NOW 0x05 -#define EMAC_PPS_COMMAND_CANCEL_STOP 0x06 - -//***************************************************************************** -// -// Values which may be passed to EMACVLANRxConfigSet in the ui32Config -// parameter and which may be returned from EMACVLANRxConfigGet. -// -//***************************************************************************** -#define EMAC_VLAN_RX_HASH_ENABLE 0x00080000 -#define EMAC_VLAN_RX_HASH_DISABLE 0x00000000 -#define EMAC_VLAN_RX_SVLAN_ENABLE 0x00040000 -#define EMAC_VLAN_RX_SVLAN_DISABLE 0x00000000 -#define EMAC_VLAN_RX_NORMAL_MATCH 0x00000000 -#define EMAC_VLAN_RX_INVERSE_MATCH 0x00020000 -#define EMAC_VLAN_RX_12BIT_TAG 0x00010000 -#define EMAC_VLAN_RX_16BIT_TAG 0x00000000 - -//***************************************************************************** -// -// Values which may be passed to EMACVLANTxConfigSet in the ui32Config -// parameter and which may be returned from EMACVLANTxConfigGet. -// -//***************************************************************************** -#define EMAC_VLAN_TX_CVLAN 0x00000000 -#define EMAC_VLAN_TX_SVLAN 0x00080000 -#define EMAC_VLAN_TX_USE_VLC 0x00040000 -#define EMAC_VLAN_TX_VLC_NONE 0x00000000 -#define EMAC_VLAN_TX_VLC_DELETE 0x00010000 -#define EMAC_VLAN_TX_VLC_INSERT 0x00020000 -#define EMAC_VLAN_TX_VLC_REPLACE 0x00030000 - -#define EMAC_VLAN_TX_VLC_MASK 0x00030000 - -#define EMAC_RWU_FILTER_ENABLE 1 -#define EMAC_RWU_FILTER_DISABLE 0 -#define EMAC_RWU_FILTER_MULTICAST 8 -#define EMAC_RWU_FILTER_UNICAST 0 - -//***************************************************************************** -// -// The following structure fields must be packed. -// -//***************************************************************************** -#ifdef ewarm -#pragma pack(1) -#endif - -//***************************************************************************** -// -//! This structure defines up to 4 filters that can be used to define specific -//! frames which will cause the MAC to wake up from sleep mode. -// -//***************************************************************************** -typedef struct -{ - // - //! A byte mask for each filter defining which bytes from a sequence of - //! 31 (bit 31 must be clear in each mask) are used to filter incoming - //! packets. A 1 indicates that the relevant byte is used to update the - //! CRC16 for the filter, a 0 indicates that the byte is ignored. - // - uint32_t pui32ByteMask[4]; - - // - //! Defines whether each filter is enabled and, if so, whether it filters - //! multicast or unicast frames. Valid values are one of - //! EMAC_RWU_FILTER_ENABLE or EMAC_RWU_FILTER_DISABLE ORed with one of - //! EMAC_RWU_FILTER_UNICAST or EMAC_RWU_FILTER_MULTICAST. - // - uint8_t pui8Command[4]; - - // - //! Determines the byte offset within the frame at which the filter starts - //! examining bytes. The minimum value for each offset is 12. The first - //! byte of a frame is offset 0. - // - uint8_t pui8Offset[4]; - - // - //! The CRC16 value that is expected for each filter if it passes. The - //! CRC is calculated using all bytes indicated by the filter's mask. - // - uint16_t pui16CRC[4]; -} -#if defined(ccs) || \ - defined(codered) || \ - defined(gcc) || \ - defined(rvmdk) || \ - defined(__ARMCC_VERSION) || \ - defined(sourcerygxx) -__attribute__ ((packed)) tEMACWakeUpFrameFilter; -#else -tEMACWakeUpFrameFilter; -#endif - -//***************************************************************************** -// -// Turn off structure packing again. -// -//***************************************************************************** -#ifdef ewarm -#pragma pack() -#endif - -//***************************************************************************** -// -// Values which may be ORed together and used in the ui32Flags parameter to -// EMACPowerManagementControlSet. These may also returned be from a call to -// EMACPowerManagementControlGet. -// -//***************************************************************************** -#define EMAC_PMT_GLOBAL_UNICAST_ENABLE 0x00000200 -#define EMAC_PMT_WAKEUP_PACKET_ENABLE 0x00000004 -#define EMAC_PMT_MAGIC_PACKET_ENABLE 0x00000002 -#define EMAC_PMT_POWER_DOWN 0x00000001 - -//***************************************************************************** -// -// Values which may be ORed together and returned from a call to -// EMACPowerManagementStatusGet. This call will also return -// EMAC_PMT_POWER_DOWN if the MAC is in power-down mode. -// -//***************************************************************************** -#define EMAC_PMT_WAKEUP_PACKET_RECEIVED 0x00000040 -#define EMAC_PMT_MAGIC_PACKET_RECEIVED 0x00000020 - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Public function prototypes. -// -//***************************************************************************** -extern void EMACInit(uint32_t ui32Base, uint32_t ui32SysClk, - uint32_t ui32BusConfig, uint32_t ui32RxBurst, - uint32_t ui32TxBurst, uint32_t ui32DescSkipSize); -extern void EMACReset(uint32_t ui32Base); -extern void EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void EMACConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32ModeFlags, - uint32_t ui32RxMaxFrameSize); -extern void EMACFrameFilterSet(uint32_t ui32Base, uint32_t ui32FilterOpts); -extern uint32_t EMACFrameFilterGet(uint32_t ui32Base); -extern void EMACHashFilterSet(uint32_t ui32Base, uint32_t ui32HashHi, - uint32_t ui32HashLo); -extern void EMACHashFilterGet(uint32_t ui32Base, uint32_t *pui32HashHi, - uint32_t *pui32HashLo); -extern uint32_t EMACHashFilterBitCalculate(uint8_t *pui8MACAddr); -extern void EMACTxDMAPollDemand(uint32_t ui32Base); -extern void EMACRxDMAPollDemand(uint32_t ui32Base); -extern void EMACRxDMADescriptorListSet(uint32_t ui32Base, - tEMACDMADescriptor *pDescriptor); -extern tEMACDMADescriptor *EMACRxDMADescriptorListGet(uint32_t ui32Base); -extern tEMACDMADescriptor *EMACRxDMACurrentDescriptorGet(uint32_t ui32Base); -extern uint8_t *EMACRxDMACurrentBufferGet(uint32_t ui32Base); -extern void EMACTxDMADescriptorListSet(uint32_t ui32Base, - tEMACDMADescriptor *pDescriptor); -extern tEMACDMADescriptor *EMACTxDMADescriptorListGet(uint32_t ui32Base); -extern tEMACDMADescriptor *EMACTxDMACurrentDescriptorGet(uint32_t ui32Base); -extern uint8_t *EMACTxDMACurrentBufferGet(uint32_t ui32Base); -extern void EMACConfigGet(uint32_t ui32Base, uint32_t *pui32Config, - uint32_t *pui32Mode, uint32_t *pui32RxMaxFrameSize); -extern void EMACAddrSet(uint32_t ui32Base, uint32_t ui32Index, - const uint8_t *pui8MACAddr); -extern void EMACAddrGet(uint32_t ui32Base, uint32_t ui32Index, - uint8_t *pui8MACAddr); -extern uint32_t EMACNumAddrGet(uint32_t ui32Base); -extern void EMACAddrFilterSet(uint32_t ui32Base, uint32_t ui32Index, - uint32_t ui32Config); -extern uint32_t EMACAddrFilterGet(uint32_t ui32Base, uint32_t ui32Index); -extern void EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout); -extern uint32_t EMACStatusGet(uint32_t ui32Base); -extern uint32_t EMACDMAStateGet(uint32_t ui32Base); -extern void EMACTxFlush(uint32_t ui32Base); -extern void EMACTxEnable(uint32_t ui32Base); -extern void EMACTxDisable(uint32_t ui32Base); -extern void EMACRxEnable(uint32_t ui32Base); -extern void EMACRxDisable(uint32_t ui32Base); -extern void EMACIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void EMACIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t EMACIntStatus(uint32_t ui32Base, bool bMasked); -extern void EMACIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void EMACIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void EMACIntUnregister(uint32_t ui32Base); -extern void EMACPHYWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint8_t ui8RegAddr, uint16_t ui16Data); -extern void EMACPHYExtendedWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr, uint16_t ui16Data); -extern uint16_t EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint8_t ui8RegAddr); -extern uint16_t EMACPHYExtendedRead(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr); -extern void EMACPHYPowerOff(uint32_t ui32Base, uint8_t ui8PhyAddr); -extern void EMACPHYPowerOn(uint32_t ui32Base, uint8_t ui8PhyAddr); -extern void EMACTimestampConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32SubSecondInc); -extern uint32_t EMACTimestampConfigGet(uint32_t ui32Base, - uint32_t *pui32SubSecondInc); -extern void EMACTimestampAddendSet(uint32_t ui32Base, uint32_t ui32Seconds); -extern void EMACTimestampEnable(uint32_t ui32Base); -extern void EMACTimestampDisable(uint32_t ui32Base); -extern void EMACTimestampSysTimeSet(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32SubSeconds); -extern void EMACTimestampSysTimeGet(uint32_t ui32Base, uint32_t *pui32Seconds, - uint32_t *pui32SubSeconds); -extern void EMACTimestampSysTimeUpdate(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32SubSeconds, bool bInc); -extern void EMACTimestampTargetSet(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32Nanoseconds); -extern void EMACTimestampTargetIntEnable(uint32_t ui32Base); -extern void EMACTimestampTargetIntDisable(uint32_t ui32Base); -extern uint32_t EMACTimestampIntStatus(uint32_t ui32Base); -extern void EMACTimestampPPSSimpleModeSet(uint32_t ui32Base, - uint32_t ui32FreqConfig); -extern void EMACTimestampPPSCommandModeSet(uint32_t ui32Base, - uint32_t ui32Config); -extern void EMACTimestampPPSCommand(uint32_t ui32Base, uint8_t ui8Cmd); -extern void EMACTimestampPPSPeriodSet(uint32_t ui32Base, uint32_t ui32Period, - uint32_t ui32Width); -extern void EMACVLANRxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, - uint32_t ui32Config); -extern uint32_t EMACVLANRxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag); -extern void EMACVLANTxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, - uint32_t ui32Config); -extern uint32_t EMACVLANTxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag); -extern uint32_t EMACVLANHashFilterBitCalculate(uint16_t ui16Tag); -extern void EMACVLANHashFilterSet(uint32_t ui32Base, uint32_t ui32Hash); -extern uint32_t EMACVLANHashFilterGet(uint32_t ui32Base); -extern void EMACRemoteWakeUpFrameFilterSet(uint32_t ui32Base, - const tEMACWakeUpFrameFilter *pFilter); -extern void EMACRemoteWakeUpFrameFilterGet(uint32_t ui32Base, - tEMACWakeUpFrameFilter *pFilter); -extern void EMACPowerManagementControlSet(uint32_t ui32Base, - uint32_t ui32Flags); -extern uint32_t EMACPowerManagementControlGet(uint32_t ui32Base); -extern uint32_t EMACPowerManagementStatusGet(uint32_t ui32Base); -extern void EMACWoLEnter(uint32_t ui32Base); -extern void EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig, - uint16_t ui16LPILSTimer, uint16_t ui16LPITWTimer); -extern void EMACLPIEnter(uint32_t ui32Base); -extern uint16_t EMACLPIStatus(uint32_t ui32Base); -extern void EMACLPILinkSet(uint32_t ui32Base); -extern void EMACLPILinkClear(uint32_t ui32Base); -extern void EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr, uint16_t ui16Data); -extern uint16_t EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr); -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_EMAC_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/epi.c b/bsp/tm4c129x-dk/libraries/driverlib/epi.c deleted file mode 100644 index c85a02621e8aff6e210bcbdcb3b1181b5395b656..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/epi.c +++ /dev/null @@ -1,2187 +0,0 @@ -//***************************************************************************** -// -// epi.c - Driver for the EPI module. -// -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#include -#include -#include "inc/hw_epi.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/epi.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -//! \addtogroup epi_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// Helper masks for chip select configuration options. -// -//***************************************************************************** -#define EPI_HB8_CS_MASK (EPI_HB8_MODE_FIFO | EPI_HB8_RDWAIT_3 | \ - EPI_HB8_WRWAIT_3 | EPI_HB8_RDHIGH | \ - EPI_HB8_WRHIGH | EPI_HB8_ALE_HIGH) - -#define EPI_HB16_CS_MASK (EPI_HB8_CS_MASK | EPI_HB16_BURST_TRAFFIC) - -//***************************************************************************** -// -// Ensure that erratum workaround inline functions have a public version -// available in exactly one object module (this one). -// -//***************************************************************************** - -//***************************************************************************** -// -//! Safely writes a word to the EPI 0x10000000 address space. -//! -//! \param pui32Addr is the address which is to be written. -//! \param ui32Value is the 32-bit word to write. -//! -//! This function must be used when writing words to EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return None. -// -//***************************************************************************** -extern void EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value); - -//***************************************************************************** -// -//! Safely reads a word from the EPI 0x10000000 address space. -//! -//! \param pui32Addr is the address which is to be read. -//! -//! This function must be used when reading words from EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return The 32-bit word stored at address \e pui32Addr. -// -//***************************************************************************** -extern uint32_t EPIWorkaroundWordRead(uint32_t *pui32Addr); - -//***************************************************************************** -// -//! Safely writes a half-word to the EPI 0x10000000 address space. -//! -//! \param pui16Addr is the address which is to be written. -//! \param ui16Value is the 16-bit half-word to write. -//! -//! This function must be used when writing half-words to EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return None. -// -//***************************************************************************** -extern void EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value); - -//***************************************************************************** -// -//! Safely reads a half-word from the EPI 0x10000000 address space. -//! -//! \param pui16Addr is the address which is to be read. -//! -//! This function must be used when reading half-words from EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return The 16-bit word stored at address \e pui16Addr. -// -//***************************************************************************** -extern uint16_t EPIWorkaroundHWordRead(uint16_t *pui16Addr); - -//***************************************************************************** -// -//! Safely writes a byte to the EPI 0x10000000 address space. -//! -//! \param pui8Addr is the address which is to be written. -//! \param ui8Value is the 8-bit byte to write. -//! -//! This function must be used when writing bytes to EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return None. -// -//***************************************************************************** -extern void EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value); - -//***************************************************************************** -// -//! Safely reads a byte from the EPI 0x10000000 address space. -//! -//! \param pui8Addr is the address which is to be read. -//! -//! This function must be used when reading bytes from EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return The 8-bit byte stored at address \e pui8Addr. -// -//***************************************************************************** -extern uint8_t EPIWorkaroundByteRead(uint8_t *pui8Addr); - -//***************************************************************************** -// -//! Sets the usage mode of the EPI module. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Mode is the usage mode of the EPI module. -//! -//! This functions sets the operating mode of the EPI module. The parameter -//! \e ui32Mode must be one of the following: -//! -//! - \b EPI_MODE_GENERAL - use for general-purpose mode operation -//! - \b EPI_MODE_SDRAM - use with SDRAM device -//! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface -//! - \b EPI_MODE_HB16 - use with host-bus 16-bit interface -//! - \b EPI_MODE_DISABLE - disable the EPI module -//! -//! Selection of any of the above modes enables the EPI module, except -//! for \b EPI_MODE_DISABLE, which is used to disable the module. -//! -//! \return None. -// -//***************************************************************************** -void -EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT((ui32Mode == EPI_MODE_GENERAL) || - (ui32Mode == EPI_MODE_SDRAM) || - (ui32Mode == EPI_MODE_HB8) || - (ui32Mode == EPI_MODE_HB16) || - (ui32Mode == EPI_MODE_DISABLE)); - - // - // Write the mode word to the register. - // - HWREG(ui32Base + EPI_O_CFG) = ui32Mode; -} - -//***************************************************************************** -// -//! Sets the clock divider for the EPI module's CS0n/CS1n. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Divider is the value of the clock divider to be applied to -//! the external interface (0-65535). -//! -//! This function sets the clock divider(s) that is used to determine the -//! clock rate of the external interface. The \e ui32Divider value is used to -//! derive the EPI clock rate from the system clock based on the following -//! formula. -//! -//! EPIClk = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2)) -//! -//! For example, a divider value of 1 results in an EPI clock rate of half -//! the system clock, value of 2 or 3 yields one quarter of the system clock -//! and a value of 4 results in one sixth of the system clock rate. -//! -//! In cases where a dual chip select mode is in use and different clock rates -//! are required for each chip select, the \e ui32Divider parameter must -//! contain two dividers. The lower 16 bits define the divider to be used with -//! CS0n and the upper 16 bits define the divider for CS1n. -//! -//! \return None. -// -//***************************************************************************** -void -EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Write the divider value to the register. - // - HWREG(ui32Base + EPI_O_BAUD) = ui32Divider; -} - -//***************************************************************************** -// -//! Sets the clock divider for the specified CS in the EPI module. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select to modify and has a valid range of 0-3. -//! \param ui32Divider is the value of the clock divider to be applied to -//! the external interface (0-65535). -//! -//! This function sets the clock divider(s) for the specified CS that is used -//! to determine the clock rate of the external interface. The \e ui32Divider -//! value is used to derive the EPI clock rate from the system clock based on -//! the following formula. -//! -//! EPIClk = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2)) -//! -//! For example, a divider value of 1 results in an EPI clock rate of half -//! the system clock, value of 2 or 3 yields one quarter of the system clock -//! and a value of 4 results in one sixth of the system clock rate. -//! -//! \note The availability of CS2n and CS3n varies based on the Tiva part -//! in use. Please consult the data sheet to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIDividerCSSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Divider) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Write the divider value to the register bitfield. - // - if(ui32CS < 2) - { - ui32Reg = HWREG(ui32Base + EPI_O_BAUD) & ~(0xffff << (16 * ui32CS)); - ui32Reg |= ((ui32Divider & 0xffff) << (16 * ui32CS)); - HWREG(ui32Base + EPI_O_BAUD) = ui32Reg; - } - else - { - ui32Reg = (HWREG(ui32Base + EPI_O_BAUD2) & - ~(0xffff << (16 * (ui32CS - 2)))); - ui32Reg |= ((ui32Divider & 0xffff) << (16 * (ui32CS - 2))); - HWREG(ui32Base + EPI_O_BAUD2) = ui32Reg; - } -} - -//***************************************************************************** -// -//! Sets the transfer count for uDMA transmit operations on EPI. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Count is the number of units to transmit by uDMA to WRFIFO. -//! -//! This function is used to help configure the EPI uDMA transmit operations. -//! A non-zero transmit count in combination with a FIFO threshold trigger -//! asserts an EPI uDMA transmit. -//! -//! Note that, although the EPI peripheral can handle counts of up to 65535, -//! a single uDMA transfer has a maximum length of 1024 units so \e ui32Count -//! should be set to values less than or equal to 1024. -//! -//! \note The availability of the EPI DMA TX count varies based on the -//! Tiva part in use. Please consult the data sheet to determine if this -//! feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Count <= 1024); - - // - // Assign the DMA TX count value provided. - // - HWREG(ui32Base + EPI_O_DMATXCNT) = ui32Count & 0xffff; -} - -//***************************************************************************** -// -//! Configures the SDRAM mode of operation. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Config is the SDRAM interface configuration. -//! \param ui32Refresh is the refresh count in core clocks (0-2047). -//! -//! This function is used to configure the SDRAM interface, when the SDRAM -//! mode is chosen with the function EPIModeSet(). The parameter -//! \e ui32Config is the logical OR of several sets of choices: -//! -//! The processor core frequency must be specified with one of the following: -//! -//! - \b EPI_SDRAM_CORE_FREQ_0_15 defines core clock as 0 MHz < clk <= 15 MHz -//! - \b EPI_SDRAM_CORE_FREQ_15_30 defines core clock as 15 MHz < clk <= 30 MHz -//! - \b EPI_SDRAM_CORE_FREQ_30_50 defines core clock as 30 MHz < clk <= 50 MHz -//! - \b EPI_SDRAM_CORE_FREQ_50_100 defines core clock as 50 MHz < clk <= -//! 100 MHz -//! -//! The low power mode is specified with one of the following: -//! -//! - \b EPI_SDRAM_LOW_POWER enter low power, self-refresh state. -//! - \b EPI_SDRAM_FULL_POWER normal operating state. -//! -//! The SDRAM device size is specified with one of the following: -//! -//! - \b EPI_SDRAM_SIZE_64MBIT size is a 64 Mbit device (8 MB). -//! - \b EPI_SDRAM_SIZE_128MBIT size is a 128 Mbit device (16 MB). -//! - \b EPI_SDRAM_SIZE_256MBIT size is a 256 Mbit device (32 MB). -//! - \b EPI_SDRAM_SIZE_512MBIT size is a 512 Mbit device (64 MB). -//! -//! The parameter \e ui16Refresh sets the refresh counter in units of core -//! clock ticks. It is an 11-bit value with a range of 0 - 2047 counts. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigSDRAMSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32Refresh) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Refresh < 2048); - - // - // Fill in the refresh count field of the configuration word. - // - ui32Config &= ~EPI_SDRAMCFG_RFSH_M; - ui32Config |= ui32Refresh << EPI_SDRAMCFG_RFSH_S; - - // - // Write the SDRAM configuration register. - // - HWREG(ui32Base + EPI_O_SDRAMCFG) = ui32Config; -} - -//***************************************************************************** -// -//! Configures the interface for Host-bus 8 operation. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Config is the interface configuration. -//! \param ui32MaxWait is the maximum number of external clocks to wait -//! if a FIFO ready signal is holding off the transaction, 0-255. -//! -//! This function is used to configure the interface when used in host-bus 8 -//! operation as chosen with the function EPIModeSet(). The parameter -//! \e ui32Config is the logical OR of the following: -//! -//! - Host-bus 8 submode, select one of: -//! - \b EPI_HB8_MODE_ADMUX sets data and address muxed, AD[7:0] -//! - \b EPI_HB8_MODE_ADDEMUX sets up data and address separate, D[7:0] -//! - \b EPI_HB8_MODE_SRAM as \b EPI_HB8_MODE_ADDEMUX, but uses address -//! switch for multiple reads instead of OEn strobing, D[7:0] -//! - \b EPI_HB8_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO -//! empty, D[7:0] -//! -//! - \b EPI_HB8_USE_TXEMPTY enables TXEMPTY signal with FIFO -//! - \b EPI_HB8_USE_RXFULL enables RXFULL signal with FIFO -//! - \b EPI_HB8_WRHIGH sets active high write strobe, otherwise it is -//! active low -//! - \b EPI_HB8_RDHIGH sets active high read strobe, otherwise it is -//! active low -//! -//! - Write wait state when \b EPI_HB8_BAUD is used, select one of: -//! - \b EPI_HB8_WRWAIT_0 sets write wait state to 2 EPI clocks (default) -//! - \b EPI_HB8_WRWAIT_1 sets write wait state to 4 EPI clocks -//! - \b EPI_HB8_WRWAIT_2 sets write wait state to 6 EPI clocks -//! - \b EPI_HB8_WRWAIT_3 sets write wait state to 8 EPI clocks -//! -//! - Read wait state when \b EPI_HB8_BAUD is used, select one of: -//! - \b EPI_HB8_RDWAIT_0 sets read wait state to 2 EPI clocks (default) -//! - \b EPI_HB8_RDWAIT_1 sets read wait state to 4 EPI clocks -//! - \b EPI_HB8_RDWAIT_2 sets read wait state to 6 EPI clocks -//! - \b EPI_HB8_RDWAIT_3 sets read wait state to 8 EPI clocks -//! -//! - \b EPI_HB8_WORD_ACCESS - use Word Access mode to route bytes to the -//! correct byte lanes allowing data to be stored in bits [31:8]. If absent, -//! all data transfers use bits [7:0]. -//! -//! - \b EPI_HB8_CLOCK_GATE_IDLE sets the EPI clock to be held low when no data -//! is available to read or write -//! - \b EPI_HB8_CLOCK_INVERT inverts the EPI clock -//! - \b EPI_HB8_IN_READY_EN sets EPIS032 as a ready/stall signal, active high -//! - \b EPI_HB8_IN_READY_EN_INVERT sets EPIS032 as ready/stall signal, active -//! low -//! - \b EPI_HB8_ALE_HIGH sets the address latch active high (default) -//! - \b EPI_HB8_ALE_LOW sets address latch active low -//! - \b EPI_HB8_CSBAUD use different baud rates when accessing devices on each -//! chip select. CS0n uses the baud rate specified by the lower 16 bits -//! of the divider passed to EPIDividerSet() and CS1n uses the divider passed -//! in the upper 16 bits. If this option is absent, both chip selects use -//! the baud rate resulting from the divider in the lower 16 bits of the -//! parameter passed to EPIDividerSet(). -//! -//! In addition, some parts support CS2n and CS3n for a total of 4 chip -//! selects. If \b EPI_HB8_CSBAUD is configured, EPIDividerCSSet() should be -//! used to to configure the divider for CS2n and CS3n. They both also use the -//! lower 16 bits passed to EPIDividerSet() if this option is absent. -//! -//! The use of \b EPI_HB8_CSBAUD also allows for unique chip select -//! configurations. CS0n, CS1n, CS2n, and CS3n can each be configured by -//! calling EPIConfigHB8CSSet() if \b EPI_HB8_CSBAUD is used. Otherwise, the -//! configuration provided in \e ui32Config is used for all chip selects -//! enabled. -//! -//! - Chip select configuration, select one of: -//! - \b EPI_HB8_CSCFG_CS sets EPIS030 to operate as a chip select signal. -//! - \b EPI_HB8_CSCFG_ALE sets EPIS030 to operate as an address latch -//! (ALE). -//! - \b EPI_HB8_CSCFG_DUAL_CS sets EPIS030 to operate as CS0n and EPIS027 -//! as CS1n with the asserted chip select determined from the most -//! significant address bit for the respective external address map. -//! - \b EPI_HB8_CSCFG_ALE_DUAL_CS sets EPIS030 as an address latch (ALE), -//! EPIS027 as CS0n and EPIS026 as CS1n with the asserted chip select -//! determined from the most significant address bit for the respective -//! external address map. -//! - \b EPI_HB8_CSCFG_ALE_SINGLE_CS sets EPIS030 to operate as an address -//! latch (ALE) and EPIS027 is used as a chip select. -//! - \b EPI_HB8_CSCFG_QUAD_CS sets EPIS030 as CS0n, EPIS027 as CS1n, -//! EPIS034 as CS2n and EPIS033 as CS3n. -//! - \b EPI_HB8_CSCFG_ALE_QUAD_CS sets EPIS030 as an address latch (ALE), -//! EPIS026 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033 as CS3n. -//! \note Dual or quad chip select configurations cannot be used with -//! EPI_HB8_MODE_SRAM. -//! -//! The parameter \e ui32MaxWait is used if the FIFO mode is chosen. If a -//! FIFO is used aint32_t with RXFULL or TXEMPTY ready signals, then this -//! parameter determines the maximum number of clocks to wait when the -//! transaction is being held off by by the FIFO using one of these ready -//! signals. A value of 0 means to wait forever. -//! -//! \note Availability of configuration options varies based on the Tiva -//! part in use. Please consult the data sheet to determine if the features -//! desired are available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB8Set(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32MaxWait) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32MaxWait < 256); - - // - // Determine the CS and word access modes. - // - HWREG(ui32Base + EPI_O_HB8CFG2) = - ((ui32Config & EPI_HB8_CSBAUD) ? EPI_HB8CFG2_CSBAUD : 0) | - ((ui32Config & EPI_HB8_CSCFG_MASK) << 15); - - // - // Fill in the max wait field of the configuration word. - // - ui32Config &= ~EPI_HB8CFG_MAXWAIT_M; - ui32Config |= ui32MaxWait << EPI_HB8CFG_MAXWAIT_S; - - // - // Write the main HostBus8 configuration register. - // - HWREG(ui32Base + EPI_O_HB8CFG) = ui32Config; -} - -//***************************************************************************** -// -//! Configures the interface for Host-bus 16 operation. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Config is the interface configuration. -//! \param ui32MaxWait is the maximum number of external clocks to wait -//! if a FIFO ready signal is holding off the transaction. -//! -//! This function is used to configure the interface when used in Host-bus 16 -//! operation as chosen with the function EPIModeSet(). The parameter -//! \e ui32Config is the logical OR of the following: -//! - Host-bus 16 submode, select one of: -//! - \b EPI_HB16_MODE_ADMUX sets data and address muxed, AD[15:0]. -//! - \b EPI_HB16_MODE_ADDEMUX sets up data and address as separate, -//! D[15:0]. -//! - \b EPI_HB16_MODE_SRAM sets as \b EPI_HB16_MODE_ADDEMUX but uses -//! address switch for multiple reads instead of OEn strobing, D[15:0]. -//! - \b EPI_HB16_MODE_FIFO addes XFIFO controls with sense of XFIFO full -//! and XFIFO empty, D[15:0]. This submode uses no address or ALE. -//! -//! - \b EPI_HB16_USE_TXEMPTY enables TXEMPTY signal with FIFO. -//! - \b EPI_HB16_USE_RXFULL enables RXFULL signal with FIFO. -//! - \b EPI_HB16_WRHIGH use active high write strobe, otherwise it is -//! active low. -//! - \b EPI_HB16_RDHIGH use active high read strobe, otherwise it is -//! active low. -//! - Write wait state, select one of: -//! - \b EPI_HB16_WRWAIT_0 sets write wait state to 2 EPI clocks. -//! - \b EPI_HB16_WRWAIT_1 sets write wait state to 4 EPI clocks. -//! - \b EPI_HB16_WRWAIT_2 sets write wait state to 6 EPI clocks. -//! - \b EPI_HB16_WRWAIT_3 sets write wait state to 8 EPI clocks. -//! -//! - Read wait state, select one of: -//! - \b EPI_HB16_RDWAIT_0 sets read wait state to 2 EPI clocks. -//! - \b EPI_HB16_RDWAIT_1 sets read wait state to 4 EPI clocks. -//! - \b EPI_HB16_RDWAIT_2 sets read wait state to 6 EPI clocks. -//! - \b EPI_HB16_RDWAIT_3 sets read wait state to 8 EPI clocks. -//! -//! - \b EPI_HB16_WORD_ACCESS use Word Access mode to route bytes to the -//! correct byte lanes allowing data to be stored in bits [31:16]. If -//! absent, all data transfers use bits [15:0]. -//! -//! \note \b EPI_HB16_WORD_ACCESS is not available on all parts. Please -//! consult the data sheet to determine if this feature is available. -//! -//! - \b EPI_HB16_CLOCK_GATE_IDLE holds the EPI clock low when no data is -//! available to read or write. -//! - \b EPI_HB16_CLOCK_INVERT inverts the EPI clock. -//! - \b EPI_HB16_IN_READY_EN sets EPIS032 as a ready/stall signal, active -//! high. -//! - \b EPI_HB16_IN_READY_EN_INVERTED sets EPIS032 as ready/stall signal, -//! active low. -//! - Address latch logic, select one of: -//! - \b EPI_HB16_ALE_HIGH sets the address latch active high (default). -//! - \b EPI_HB16_ALE_LOW sets address latch active low. -//! -//! - \b EPI_HB16_BURST_TRAFFIC enables burst traffic. Only valid with -//! \b EPI_HB16_MODE_ADMUX and a chip select configuration that utilizes an -//! ALE. -//! - \b EPI_HB16_BSEL enables byte selects. In this mode, two EPI signals -//! operate as byte selects allowing 8-bit transfers. If this flag is not -//! specified, data must be read and written using only 16-bit transfers. -//! - \b EPI_HB16_CSBAUD use different baud rates when accessing devices -//! on each chip select. CS0n uses the baud rate specified by the lower 16 -//! bits of the divider passed to EPIDividerSet() and CS1n uses the divider -//! passed in the upper 16 bits. If this option is absent, both chip selects -//! use the baud rate resulting from the divider in the lower 16 bits of the -//! parameter passed to EPIDividerSet(). -//! -//! In addition, some parts support CS2n and CS3n for a total of 4 chip -//! selects. If \b EPI_HB16_CSBAUD is configured, EPIDividerCSSet() should be -//! used to to configure the divider for CS2n and CS3n. They both also use the -//! lower 16 bits passed to EPIDividerSet() if this option is absent. -//! -//! The use of \b EPI_HB16_CSBAUD also allows for unique chip select -//! configurations. CS0n, CS1n, CS2n, and CS3n can each be configured by -//! calling EPIConfigHB16CSSet() if \b EPI_HB16_CSBAUD is used. Otherwise, the -//! configuration provided in \e ui32Config is used for all chip selects. -//! -//! - Chip select configuration, select one of: -//! - \b EPI_HB16_CSCFG_CS sets EPIS030 to operate as a chip select signal. -//! - \b EPI_HB16_CSCFG_ALE sets EPIS030 to operate as an address latch -//! (ALE). -//! - \b EPI_HB16_CSCFG_DUAL_CS sets EPIS030 to operate as CS0n and EPIS027 -//! as CS1n with the asserted chip select determined from the most -//! significant address bit for the respective external address map. -//! - \b EPI_HB16_CSCFG_ALE_DUAL_CS sets EPIS030 as an address latch (ALE), -//! EPIS027 as CS0n and EPIS026 as CS1n with the asserted chip select -//! determined from the most significant address bit for the respective -//! external address map. -//! - \b EPI_HB16_CSCFG_ALE_SINGLE_CS sets EPIS030 to operate as an address -//! latch (ALE) and EPIS027 is used as a chip select. -//! - \b EPI_HB16_CSCFG_QUAD_CS sets EPIS030 as CS0n, EPIS027 as CS1n, -//! EPIS034 as CS2n and EPIS033 as CS3n. -//! - \b EPI_HB16_CSCFG_ALE_QUAD_CS sets EPIS030 as an address latch -//! (ALE), EPIS026 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033 -//! as CS3n. -//! \note Dual or quad chip select configurations cannot be used with -//! EPI_HB16_MODE_SRAM. -//! -//! The parameter \e ui32MaxWait is used if the FIFO mode is chosen. If a -//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this -//! parameter determines the maximum number of clocks to wait when the -//! transaction is being held off by by the FIFO using one of these ready -//! signals. A value of 0 means to wait forever. -//! -//! \note Availability of configuration options varies based on the Tiva -//! part in use. Please consult the data sheet to determine if the features -//! desired are available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB16Set(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32MaxWait) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32MaxWait < 256); - - // - // Determine the CS and word access modes. - // - HWREG(ui32Base + EPI_O_HB16CFG2) = - ((ui32Config & EPI_HB16_CSBAUD) ? EPI_HB16CFG2_CSBAUD : 0) | - ((ui32Config & EPI_HB16_CSCFG_MASK) << 15); - - // - // Fill in the max wait field of the configuration word. - // - ui32Config &= ~EPI_HB16CFG_MAXWAIT_M; - ui32Config |= ui32MaxWait << EPI_HB16CFG_MAXWAIT_S; - - // - // Write the main HostBus16 configuration register. - // - HWREG(ui32Base + EPI_O_HB16CFG) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the individual chip select configuration for the Host-bus 8 interface. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select value to configure. -//! \param ui32Config is the configuration settings. -//! -//! This function is used to configure individual chip select settings for the -//! Host-bus 8 interface mode. EPIConfigHB8Set() must have been setup with -//! the \b EPI_HB8_CSBAUD flag for the individual chip select configuration -//! option to be available. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The parameter \e ui32Config is the logical OR of the -//! following: -//! -//! - Host-bus 8 submode, select one of: -//! - \b EPI_HB8_MODE_ADMUX sets data and address muxed, AD[7:0]. -//! - \b EPI_HB8_MODE_ADDEMUX sets up data and address separate, D[7:0]. -//! - \b EPI_HB8_MODE_SRAM as \b EPI_HB8_MODE_ADDEMUX, but uses address -//! switch for multiple reads instead of OEn strobing, D[7:0]. -//! - \b EPI_HB8_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO -//! empty, D[7:0]. This is only available for CS0n and CS1n. -//! -//! - \b EPI_HB8_WRHIGH sets active high write strobe, otherwise it is -//! active low. -//! - \b EPI_HB8_RDHIGH sets active high read strobe, otherwise it is -//! active low. -//! - Write wait state when \b EPI_HB8_BAUD is used, select one of: -//! - \b EPI_HB8_WRWAIT_0 sets write wait state to 2 EPI clocks (default). -//! - \b EPI_HB8_WRWAIT_1 sets write wait state to 4 EPI clocks. -//! - \b EPI_HB8_WRWAIT_2 sets write wait state to 6 EPI clocks. -//! - \b EPI_HB8_WRWAIT_3 sets write wait state to 8 EPI clocks. -//! - Read wait state when \b EPI_HB8_BAUD is used, select one of: -//! - \b EPI_HB8_RDWAIT_0 sets read wait state to 2 EPI clocks (default). -//! - \b EPI_HB8_RDWAIT_1 sets read wait state to 4 EPI clocks. -//! - \b EPI_HB8_RDWAIT_2 sets read wait state to 6 EPI clocks. -//! - \b EPI_HB8_RDWAIT_3 sets read wait state to 8 EPI clocks. -//! - \b EPI_HB8_ALE_HIGH sets the address latch active high (default). -//! - \b EPI_HB8_ALE_LOW sets address latch active low. -//! -//! \note The availability of a unique chip select configuration within -//! Host-bus 8 interface mode varies based on the Tiva part in use. -//! Please consult the data sheet to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB8CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) -{ - uint32_t ui32Offset, ui32Reg; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB8CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB8CFG3 + ((ui32CS - 2) << 2); - } - - // - // Preserve the bits that will not be modified. - // - ui32Reg = HWREG(ui32Base + ui32Offset) & ~EPI_HB8_CS_MASK; - - // - // Write the target chip select HostBus8 configuration fields. - // - HWREG(ui32Base + ui32Offset) = (ui32Reg | ui32Config); -} - -//***************************************************************************** -// -//! Sets the individual chip select configuration for the Host-bus 16 -//! interface. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select value to configure. -//! \param ui32Config is the configuration settings. -//! -//! This function is used to configure individual chip select settings for the -//! Host-bus 16 interface mode. EPIConfigHB16Set() must have been set up with -//! the \b EPI_HB16_CSBAUD flag for the individual chip select configuration -//! option to be available. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The parameter \e ui32Config is the logical OR the -//! following: -//! -//! - Host-bus 16 submode, select one of: -//! - \b EPI_HB16_MODE_ADMUX sets data and address muxed, AD[15:0]. -//! - \b EPI_HB16_MODE_ADDEMUX sets up data and address separate, D[15:0]. -//! - \b EPI_HB16_MODE_SRAM same as \b EPI_HB8_MODE_ADDEMUX, but uses -//! address switch for multiple reads instead of OEn strobing, D[15:0]. -//! - \b EPI_HB16_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO -//! empty, D[15:0]. This feature is only available on CS0n and CS1n. -//! - \b EPI_HB16_WRHIGH sets active high write strobe, otherwise it is -//! active low. -//! - \b EPI_HB16_RDHIGH sets active high read strobe, otherwise it is -//! active low. -//! - Write wait state when \b EPI_HB16_BAUD is used, select one of: -//! - \b EPI_HB16_WRWAIT_0 sets write wait state to 2 EPI clocks (default). -//! - \b EPI_HB16_WRWAIT_1 sets write wait state to 4 EPI clocks. -//! - \b EPI_HB16_WRWAIT_2 sets write wait state to 6 EPI clocks. -//! - \b EPI_HB16_WRWAIT_3 sets write wait state to 8 EPI clocks. -//! - Read wait state when \b EPI_HB16_BAUD is used, select one of: -//! - \b EPI_HB16_RDWAIT_0 sets read wait state to 2 EPI clocks (default). -//! - \b EPI_HB16_RDWAIT_1 sets read wait state to 4 EPI clocks. -//! - \b EPI_HB16_RDWAIT_2 sets read wait state to 6 EPI clocks. -//! - \b EPI_HB16_RDWAIT_3 sets read wait state to 8 EPI clocks. -//! - \b EPI_HB16_ALE_HIGH sets the address latch active high (default). -//! - \b EPI_HB16_ALE_LOW sets address latch active low. -//! - \b EPI_HB16_BURST_TRAFFIC enables burst traffic. Only valid with -//! \b EPI_HB16_MODE_ADMUX and a chip select configuration that utilizes an -//! ALE. -//! -//! \note The availability of the unique chip select configuration within the -//! Host-bus 16 interface mode varies based on the Tiva part in use. -//! Please consult the data sheet to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB16CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) -{ - uint32_t ui32Offset, ui32Reg; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); - } - - // - // Preserve the bits that will not be modified. - // - ui32Reg = HWREG(ui32Base + ui32Offset) & ~EPI_HB16_CS_MASK; - - // - // Write the target chip select HostBus16 configuration fields. - // - HWREG(ui32Base + ui32Offset) = (ui32Reg | ui32Config); -} - -//***************************************************************************** -// -//! Sets the individual chip select timing settings for the Host-bus 8 -//! interface. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select value to configure. -//! \param ui32Config is the configuration settings. -//! -//! This function is used to set individual chip select timings for the -//! Host-bus 8 interface mode. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The parameter \e ui32Config is the logical OR of the -//! following: -//! -//! - Input ready stall delay, select one of: -//! - \b EPI_HB8_IN_READY_DELAY_1 sets the stall on input ready (EPIS032) -//! to start 1 EPI clock after signaled. -//! - \b EPI_HB8_IN_READY_DELAY_2 sets the stall on input ready (EPIS032) -//! to start 2 EPI clocks after signaled. -//! - \b EPI_HB8_IN_READY_DELAY_3 sets the stall on input ready (EPIS032) -//! to start 3 EPI clocks after signaled. -//! -//! - Host bus transfer delay, select one of: -//! - \b EPI_HB8_CAP_WIDTH_1 defines the inter-transfer capture width to -//! create a delay of 1 EPI clock. -//! - \b EPI_HB8_CAP_WIDTH_2 defines the inter-transfer capture width -//! to create a delay of 2 EPI clocks. -//! -//! - \b EPI_HB8_WRWAIT_MINUS_DISABLE disables the additional write wait state -//! reduction. -//! - \b EPI_HB8_WRWAIT_MINUS_ENABLE enables a 1 EPI clock write wait state -//! reduction. -//! - \b EPI_HB8_RDWAIT_MINUS_DISABLE disables the additional read wait state -//! reduction. -//! - \b EPI_HB8_RDWAIT_MINUS_ENABLE enables a 1 EPI clock read wait state -//!reduction. -//! -//! \note The availability of unique chip select timings within Host-bus 8 -//! interface mode varies based on the Tiva part in use. Please consult -//! the data sheet to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB8TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Write the target chip select HostBus8 timing register. - // - HWREG(ui32Base + (EPI_O_HB8TIME + (ui32CS << 2))) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the individual chip select timing settings for the Host-bus 16 -//! interface. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select value to configure. -//! \param ui32Config is the configuration settings. -//! -//! This function is used to set individual chip select timings for the -//! Host-bus 16 interface mode. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The parameter \e ui32Config is the logical OR of the -//! following: -//! -//! - Input ready stall delay, select one of: -//! - \b EPI_HB16_IN_READY_DELAY_1 sets the stall on input ready (EPIS032) -//! to start 1 EPI clock after signaled. -//! - \b EPI_HB16_IN_READY_DELAY_2 sets the stall on input ready (EPIS032) -//! to start 2 EPI clocks after signaled. -//! - \b EPI_HB16_IN_READY_DELAY_3 sets the stall on input ready (EPIS032) -//! to start 3 EPI clocks after signaled. -//! -//! - PSRAM size limitation, select one of: -//! - \b EPI_HB16_PSRAM_NO_LIMIT defines no row size limitation. -//! - \b EPI_HB16_PSRAM_128 defines the PSRAM row size to 128 bytes. -//! - \b EPI_HB16_PSRAM_256 defines the PSRAM row size to 256 bytes. -//! - \b EPI_HB16_PSRAM_512 defines the PSRAM row size to 512 bytes. -//! - \b EPI_HB16_PSRAM_1024 defines the PSRAM row size to 1024 bytes. -//! - \b EPI_HB16_PSRAM_2048 defines the PSRAM row size to 2048 bytes. -//! - \b EPI_HB16_PSRAM_4096 defines the PSRAM row size to 4096 bytes. -//! - \b EPI_HB16_PSRAM_8192 defines the PSRAM row size to 8192 bytes. -//! -//! - Host bus transfer delay, select one of: -//! - \b EPI_HB16_CAP_WIDTH_1 defines the inter-transfer capture width to -//! create a delay of 1 EPI clock -//! - \b EPI_HB16_CAP_WIDTH_2 defines the inter-transfer capture width -//! to create a delay of 2 EPI clocks. -//! -//! - Write wait state timing reduction, select one of: -//! - \b EPI_HB16_WRWAIT_MINUS_DISABLE disables the additional write wait -//! state reduction. -//! - \b EPI_HB16_WRWAIT_MINUS_ENABLE enables a 1 EPI clock write wait -//! state reduction. -//! -//! - Read wait state timing reduction, select one of: -//! - \b EPI_HB16_RDWAIT_MINUS_DISABLE disables the additional read wait -//! state reduction. -//! - \b EPI_HB16_RDWAIT_MINUS_ENABLE enables a 1 EPI clock read wait state -//! reduction. -//! -//! \note The availability of unique chip select timings within Host-bus 16 -//! interface mode varies based on the Tiva part in use. Please consult -//! the data sheet to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB16TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Write the target chip select HostBus16 timing register. - // - HWREG(ui32Base + (EPI_O_HB16TIME + (ui32CS << 2))) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the PSRAM configuration register. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select target. -//! \param ui32CR is the PSRAM configuration register value. -//! -//! This function sets the PSRAM's configuration register by using the PSRAM -//! configuration register enable signal. The Host-bus 16 interface mode -//! should be configured prior to calling this function. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The parameter \e ui32CR value is determined by -//! consulting the PSRAM's data sheet. -//! -//! \note The availability of PSRAM support varies based on the Tiva part -//! in use. Please consult the data sheet to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIPSRAMConfigRegSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32CR) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); - } - - // - // Setup for the PSRAM configuration register write. Only 21 bits are - // valid on a write. - // - HWREG(ui32Base + EPI_O_HBPSRAM) = (ui32CR & 0x1fffff); - - // - // Set the PSRAM configuration register write enable. - // - HWREG(ui32Base + ui32Offset) |= EPI_HB16CFG_WRCRE; -} - -//***************************************************************************** -// -//! Requests a configuration register read from the PSRAM. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select target. -//! -//! This function requests a read of the PSRAM's configuration register. The -//! Host-bus 16 interface mode should be configured prior to calling this -//! function. -//! The EPIPSRAMConfigRegGet() and EPIPSRAMConfigRegGetNonBlocking() can -//! be used to retrieve the configuration register value. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. -//! -//! \note The availability of PSRAM support varies based on the Tiva part -//! in use. Please consult the data sheet to determine if this feature is -//! available. -//! -//! \return none. -// -//***************************************************************************** -void -EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); - } - - // - // Set the PSRAM configuration register read enable. - // - HWREG(ui32Base + ui32Offset) |= EPI_HB16CFG_RDCRE; -} - -//***************************************************************************** -// -//! Retrieves the contents of the EPI PSRAM configuration register. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select target. -//! \param pui32CR is the provided storage used to hold the register value. -//! -//! This function copies the contents of the EPI PSRAM configuration register -//! to the provided storage if the PSRAM read configuration register enable -//! is no longer asserted. Otherwise the provided storage is not modified. -//! -//! The Host-bus 16 interface mode should be set up and EPIPSRAMConfigRegRead() -//! should be called prior to calling this function. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The \e pui32CR parameter is a pointer to provided -//! storage used to hold the register value. -//! -//! \note The availability of PSRAM support varies based on the Tiva part -//! in use. Please consult the data sheet to determine if this feature is -//! available. -//! -//! \return \b true if the value was copied to the provided storage and -//! \b false if it was not. -// -//***************************************************************************** -bool -EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base, uint32_t ui32CS, - uint32_t *pui32CR) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); - } - - // - // Verify PSRAM read enable is not asserted. - // - if(HWREG(ui32Base + ui32Offset) & EPI_HB16CFG_RDCRE) - { - return(false); - } - - // - // Copy the PSRAM configuration register value to the provided storage. - // Only the lower 16 bits are valid on a read. - // - *pui32CR = HWREG(ui32Base + EPI_O_HBPSRAM) & 0xffff; - - // - // Notify caller the provided storage holds the EPI PSRAM configuration - // register contents. - // - return(true); -} - -//***************************************************************************** -// -//! Retrieves the contents of the EPI PSRAM configuration register. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select target. -//! -//! This function retrieves the EPI PSRAM configuration register. The register -//! is read once the EPI PSRAM configuration register read enable signal is -//! de-asserted. -//! -//! The Host-bus 16 interface mode should be set up and EPIPSRAMConfigRegRead() -//! should be called prior to calling this function. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. -//! -//! \note The availability of PSRAM support varies based on the Tiva part -//! in use. Please consult the data sheet to determine if this feature is -//! available. -//! -//! \return none. -// -//***************************************************************************** -uint32_t -EPIPSRAMConfigRegGet(uint32_t ui32Base, uint32_t ui32CS) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); - } - - // - // Wait for PSRAM read enable to deassert if necessary. - // - while(HWREG(ui32Base + ui32Offset) & EPI_HB16CFG_RDCRE) - { - } - - // - // Return the EPI PSRAM configuration register contents. - // Only the lower 16 bits are valid on a read. - // - return(HWREG(ui32Base + EPI_O_HBPSRAM) & 0xffff); -} - -//***************************************************************************** -// -//! Configures the interface for general-purpose mode operation. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Config is the interface configuration. -//! \param ui32FrameCount is the frame size in clocks, if the frame signal -//! is used (0-15). -//! \param ui32MaxWait is currently not used. -//! -//! This function is used to configure the interface when used in -//! general-purpose operation as chosen with the function EPIModeSet(). The -//! parameter \e ui32Config is the logical OR of the following: -//! -//! - \b EPI_GPMODE_CLKPIN interface clock as output on a pin. -//! - \b EPI_GPMODE_CLKGATE clock is stopped when there is no transaction, -//! otherwise it is free-running. -//! - \b EPI_GPMODE_FRAME50 framing signal is 50/50 duty cycle, otherwise it -//! is a pulse. -//! - \b EPI_GPMODE_WRITE2CYCLE a two-cycle write is used, otherwise a -//! single-cycle write is used. -//! - Address bus size, select one of: -//! - \b EPI_GPMODE_ASIZE_NONE sets no address bus. -//! - \b EPI_GPMODE_ASIZE_4 sets an address bus size of 4 bits. -//! - \b EPI_GPMODE_ASIZE_12 sets an address bus size of 12 bits. -//! - \b EPI_GPMODE_ASIZE_20 sets an address bus size of 20 bits. -//! - Data bus size, select one of: -//! - \b EPI_GPMODE_DSIZE_8 sets a data bus size of 8 bits. -//! - \b EPI_GPMODE_DSIZE_16 sets a data bus size of 16 bits. -//! - \b EPI_GPMODE_DSIZE_24 sets a data bus size of 24 bits. -//! - \b EPI_GPMODE_DSIZE_32 sets a data bus size of 32 bits. -//! -//! The parameter \e ui32FrameCount is the number of clocks used to form the -//! framing signal, if the framing signal is used. The behavior depends on -//! whether the frame signal is a pulse or a 50/50 duty cycle. -//! -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigGPModeSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32FrameCount, uint32_t ui32MaxWait) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32FrameCount < 16); - ASSERT(ui32MaxWait < 256); - - // - // Fill in the frame count field of the configuration word. - // - ui32Config &= ~EPI_GPCFG_FRMCNT_M; - ui32Config |= ui32FrameCount << EPI_GPCFG_FRMCNT_S; - - // - // Write the non-moded configuration register. - // - HWREG(ui32Base + EPI_O_GPCFG) = ui32Config; -} - -//***************************************************************************** -// -//! Configures the address map for the external interface. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Map is the address mapping configuration. -//! -//! This function is used to configure the address mapping for the external -//! interface, which then determines the base address of the external memory or -//! device within the processor peripheral and/or memory space. -//! -//! The parameter \e ui32Map is the logical OR of the following: -//! -//! - Peripheral address space size, select one of: -//! - \b EPI_ADDR_PER_SIZE_256B sets the peripheral address space to 256 -//! bytes. -//! - \b EPI_ADDR_PER_SIZE_64KB sets the peripheral address space to 64 -//! Kbytes. -//! - \b EPI_ADDR_PER_SIZE_16MB sets the peripheral address space to 16 -//! Mbytes. -//! - \b EPI_ADDR_PER_SIZE_256MB sets the peripheral address space to 256 -//! Mbytes. -//! - Peripheral base address, select one of: -//! - \b EPI_ADDR_PER_BASE_NONE sets the peripheral base address to none. -//! - \b EPI_ADDR_PER_BASE_A sets the peripheral base address to -//! 0xA0000000. -//! - \b EPI_ADDR_PER_BASE_C sets the peripheral base address to -//! 0xC0000000. -//! - RAM address space, select one of: -//! - \b EPI_ADDR_RAM_SIZE_256B sets the RAM address space to 256 bytes. -//! - \b EPI_ADDR_RAM_SIZE_64KB sets the RAM address space to 64 Kbytes. -//! - \b EPI_ADDR_RAM_SIZE_16MB sets the RAM address space to 16 Mbytes. -//! - \b EPI_ADDR_RAM_SIZE_256MB sets the RAM address space to 256 Mbytes. -//! - RAM base address, select one of: -//! - \b EPI_ADDR_RAM_BASE_NONE sets the RAM space address to none. -//! - \b EPI_ADDR_RAM_BASE_6 sets the RAM space address to 0x60000000. -//! - \b EPI_ADDR_RAM_BASE_8 sets the RAM space address to 0x80000000. -//! - \b EPI_ADDR_RAM_QUAD_MODE maps CS0n to 0x60000000, CS1n to 0x80000000, -//! CS2n to 0xA0000000, and CS3n to 0xC0000000. -//! - \b EPI_ADDR_CODE_SIZE_256B sets an external code size of 256 bytes, range -//! 0x00 to 0xFF. -//! - \b EPI_ADDR_CODE_SIZE_64KB sets an external code size of 64 Kbytes, range -//! 0x0000 to 0xFFFF. -//! - \b EPI_ADDR_CODE_SIZE_16MB sets an external code size of 16 Mbytes, range -//! 0x000000 to 0xFFFFFF. -//! - \b EPI_ADDR_CODE_SIZE_256MB sets an external code size of 256 Mbytes, -//! range 0x0000000 to 0xFFFFFFF. -//! - \b EPI_ADDR_CODE_BASE_NONE sets external code base to not mapped. -//! - \b EPI_ADDR_CODE_BASE_1 sets external code base to 0x10000000. -//! -//! \note The availability of \b EPI_ADDR_RAM_QUAD_MODE and \b EPI_ADDR_CODE_* -//! varies based on the Tiva part in use. Please consult the data sheet -//! to determine if these features are available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIAddressMapSet(uint32_t ui32Base, uint32_t ui32Map) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Map < 0x1000); - - // - // Set the value of the address mapping register. - // - HWREG(ui32Base + EPI_O_ADDRMAP) = ui32Map; -} - -//***************************************************************************** -// -//! Configures a non-blocking read transaction. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Channel is the read channel (0 or 1). -//! \param ui32DataSize is the size of the data items to read. -//! \param ui32Address is the starting address to read. -//! -//! This function is used to configure a non-blocking read channel for a -//! transaction. Two channels are available that can be used in a ping-pong -//! method for continuous reading. It is not necessary to use both channels -//! to perform a non-blocking read. -//! -//! The parameter \e ui8DataSize is one of \b EPI_NBCONFIG_SIZE_8, -//! \b EPI_NBCONFIG_SIZE_16, or \b EPI_NBCONFIG_SIZE_32 for 8-bit, 16-bit, -//! or 32-bit sized data transfers. -//! -//! The parameter \e ui32Address is the starting address for the read, relative -//! to the external device. The start of the device is address 0. -//! -//! Once configured, the non-blocking read is started by calling -//! EPINonBlockingReadStart(). If the addresses to be read from the device -//! are in a sequence, it is not necessary to call this function multiple -//! times. Until it is changed, the EPI module stores the last address -//! that was used for a non-blocking read (per channel). -//! -//! \return None. -// -//***************************************************************************** -void -EPINonBlockingReadConfigure(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32DataSize, uint32_t ui32Address) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Channel < 2); - ASSERT(ui32DataSize < 4); - ASSERT(ui32Address < 0x20000000); - - // - // Compute the offset needed to select the correct channel regs. - // - ui32Offset = ui32Channel * (EPI_O_RSIZE1 - EPI_O_RSIZE0); - - // - // Write the data size register for the channel. - // - HWREG(ui32Base + EPI_O_RSIZE0 + ui32Offset) = ui32DataSize; - - // - // Write the starting address register for the channel. - // - HWREG(ui32Base + EPI_O_RADDR0 + ui32Offset) = ui32Address; -} - -//***************************************************************************** -// -//! Starts a non-blocking read transaction. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Channel is the read channel (0 or 1). -//! \param ui32Count is the number of items to read (1-4095). -//! -//! This function starts a non-blocking read that was previously configured -//! with the function EPINonBlockingReadConfigure(). Once this function is -//! called, the EPI module begins reading data from the external device -//! into the read FIFO. The EPI stops reading when the FIFO fills up -//! and resumes reading when the application drains the FIFO, until the -//! total specified count of data items has been read. -//! -//! Once a read transaction is completed and the FIFO drained, another -//! transaction can be started from the next address by calling this -//! function again. -//! -//! \return None. -// -//***************************************************************************** -void -EPINonBlockingReadStart(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Count) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Channel < 2); - ASSERT(ui32Count < 4096); - - // - // Compute the offset needed to select the correct channel regs. - // - ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); - - // - // Write to the read count register. - // - HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset) = ui32Count; -} - -//***************************************************************************** -// -//! Stops a non-blocking read transaction. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Channel is the read channel (0 or 1). -//! -//! This function cancels a non-blocking read transaction that is already -//! in progress. -//! -//! \return None. -// -//***************************************************************************** -void -EPINonBlockingReadStop(uint32_t ui32Base, uint32_t ui32Channel) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Channel < 2); - - // - // Compute the offset needed to select the correct channel regs. - // - ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); - - // - // Write a 0 to the read count register, which cancels the transaction. - // - HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset) = 0; -} - -//***************************************************************************** -// -//! Get the count remaining for a non-blocking transaction. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Channel is the read channel (0 or 1). -//! -//! This function gets the remaining count of items for a non-blocking read -//! transaction. -//! -//! \return The number of items remaining in the non-blocking read transaction. -// -//***************************************************************************** -uint32_t -EPINonBlockingReadCount(uint32_t ui32Base, uint32_t ui32Channel) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Channel < 2); - - // - // Compute the offset needed to select the correct channel regs. - // - ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); - - // - // Read the count remaining and return the value to the caller. - // - return(HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset)); -} - -//***************************************************************************** -// -//! Get the count of items available in the read FIFO. -//! -//! \param ui32Base is the EPI module base address. -//! -//! This function gets the number of items that are available to read in -//! the read FIFO. The read FIFO is filled by a non-blocking read transaction -//! which is configured by the functions EPINonBlockingReadConfigure() and -//! EPINonBlockingReadStart(). -//! -//! \return The number of items available to read in the read FIFO. -// -//***************************************************************************** -uint32_t -EPINonBlockingReadAvail(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Read the FIFO count and return it to the caller. - // - return(HWREG(ui32Base + EPI_O_RFIFOCNT)); -} - -//***************************************************************************** -// -//! Read available data from the read FIFO, as 32-bit data items. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Count is the maximum count of items to read. -//! \param pui32Buf is the caller supplied buffer where the read data is -//! stored. -//! -//! This function reads 32-bit data items from the read FIFO and stores -//! the values in a caller-supplied buffer. The function reads and stores -//! data from the FIFO until there is no more data in the FIFO or the maximum -//! count is reached as specified in the parameter \e ui32Count. The actual -//! count of items is returned. -//! -//! \return The number of items read from the FIFO. -// -//***************************************************************************** -uint32_t -EPINonBlockingReadGet32(uint32_t ui32Base, uint32_t ui32Count, - uint32_t *pui32Buf) -{ - uint32_t ui32CountRead = 0; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Count < 4096); - ASSERT(pui32Buf); - - // - // Read from the FIFO while there are any items to read and - // the caller's specified count is not exceeded. - // - while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--) - { - // - // Read from the FIFO and store in the caller supplied buffer. - // - *pui32Buf = HWREG(ui32Base + EPI_O_READFIFO0); - - // - // Update the caller's buffer pointer and the count of items read. - // - pui32Buf++; - ui32CountRead++; - } - - // - // Return the count of items read to the caller. - // - return(ui32CountRead); -} - -//***************************************************************************** -// -//! Read available data from the read FIFO, as 16-bit data items. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Count is the maximum count of items to read. -//! \param pui16Buf is the caller-supplied buffer where the read data is -//! stored. -//! -//! This function reads 16-bit data items from the read FIFO and stores -//! the values in a caller-supplied buffer. The function reads and stores -//! data from the FIFO until there is no more data in the FIFO or the maximum -//! count is reached as specified in the parameter \e ui32Count. The actual -//! count of items is returned. -//! -//! \return The number of items read from the FIFO. -// -//***************************************************************************** -uint32_t -EPINonBlockingReadGet16(uint32_t ui32Base, uint32_t ui32Count, - uint16_t *pui16Buf) -{ - uint32_t ui32CountRead = 0; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Count < 4096); - ASSERT(pui16Buf); - - // - // Read from the FIFO while there are any items to read, and - // the caller's specified count is not exceeded. - // - while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--) - { - // - // Read from the FIFO and store in the caller-supplied buffer. - // - *pui16Buf = (uint16_t)HWREG(ui32Base + EPI_O_READFIFO0); - - // - // Update the caller's buffer pointer and the count of items read. - // - pui16Buf++; - ui32CountRead++; - } - - // - // Return the count of items read to the caller. - // - return(ui32CountRead); -} - -//***************************************************************************** -// -//! Read available data from the read FIFO, as 8-bit data items. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Count is the maximum count of items to read. -//! \param pui8Buf is the caller-supplied buffer where the read data is -//! stored. -//! -//! This function reads 8-bit data items from the read FIFO and stores -//! the values in a caller-supplied buffer. The function reads and stores -//! data from the FIFO until there is no more data in the FIFO or the maximum -//! count is reached as specified in the parameter \e ui32Count. The actual -//! count of items is returned. -//! -//! \return The number of items read from the FIFO. -// -//***************************************************************************** -uint32_t -EPINonBlockingReadGet8(uint32_t ui32Base, uint32_t ui32Count, - uint8_t *pui8Buf) -{ - uint32_t ui32CountRead = 0; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Count < 4096); - ASSERT(pui8Buf); - - // - // Read from the FIFO while there are any items to read, and - // the caller's specified count is not exceeded. - // - while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--) - { - // - // Read from the FIFO and store in the caller supplied buffer. - // - *pui8Buf = (uint8_t)HWREG(ui32Base + EPI_O_READFIFO0); - - // - // Update the caller's buffer pointer and the count of items read. - // - pui8Buf++; - ui32CountRead++; - } - - // - // Return the count of items read to the caller. - // - return(ui32CountRead); -} - -//***************************************************************************** -// -//! Configures the read FIFO. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Config is the FIFO configuration. -//! -//! This function configures the FIFO trigger levels and error -//! generation. The parameter \e ui32Config is the logical OR of the -//! following: -//! -//! - \b EPI_FIFO_CONFIG_WTFULLERR enables an error interrupt when a write is -//! attempted and the write FIFO is full -//! - \b EPI_FIFO_CONFIG_RSTALLERR enables an error interrupt when a read is -//! stalled due to an interleaved write or other reason -//! - FIFO TX trigger level, select one of: -//! - \b EPI_FIFO_CONFIG_TX_EMPTY sets the FIFO TX trigger level to empty. -//! - \b EPI_FIFO_CONFIG_TX_1_4 sets the FIFO TX trigger level to 1/4. -//! - \b EPI_FIFO_CONFIG_TX_1_2 sets the FIFO TX trigger level to 1/2. -//! - \b EPI_FIFO_CONFIG_TX_3_4 sets the FIFO TX trigger level to 3/4. -//! - FIFO RX trigger level, select one of: -//! - \b EPI_FIFO_CONFIG_RX_1_8 sets the FIFO RX trigger level to 1/8. -//! - \b EPI_FIFO_CONFIG_RX_1_4 sets the FIFO RX trigger level to 1/4. -//! - \b EPI_FIFO_CONFIG_RX_1_2 sets the FIFO RX trigger level to 1/2. -//! - \b EPI_FIFO_CONFIG_RX_3_4 sets the FIFO RX trigger level to 3/4. -//! - \b EPI_FIFO_CONFIG_RX_7_8 sets the FIFO RX trigger level to 7/8. -//! - \b EPI_FIFO_CONFIG_RX_FULL sets the FIFO RX trigger level to full. -//! -//! \return None. -// -//***************************************************************************** -void -EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Config == (ui32Config & 0x00030077)); - - // - // Load the configuration into the FIFO config reg. - // - HWREG(ui32Base + EPI_O_FIFOLVL) = ui32Config; -} - -//***************************************************************************** -// -//! Reads the number of empty slots in the write transaction FIFO. -//! -//! \param ui32Base is the EPI module base address. -//! -//! This function returns the number of slots available in the transaction -//! FIFO. It can be used in a polling method to avoid attempting a write -//! that would stall. -//! -//! \return The number of empty slots in the transaction FIFO. -// -//***************************************************************************** -uint32_t -EPIWriteFIFOCountGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Read the FIFO count and return it to the caller. - // - return(HWREG(ui32Base + EPI_O_WFIFOCNT)); -} - -//***************************************************************************** -// -//! Enables EPI interrupt sources. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! This function enables the specified EPI sources to generate interrupts. -//! The \e ui32IntFlags parameter can be the logical OR of any of the following -//! values: -//! -//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level. -//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level. -//! - \b EPI_INT_ERR interrupt when an error condition occurs. -//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes. -//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes. -//! -//! \return Returns None. -// -//***************************************************************************** -void -EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32IntFlags < 17); - - // - // Write the interrupt flags mask to the mask register. - // - HWREG(ui32Base + EPI_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables EPI interrupt sources. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! -//! This function disables the specified EPI sources for interrupt -//! generation. The \e ui32IntFlags parameter can be the logical OR of any of -//! the following values: -//! -//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level. -//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level. -//! - \b EPI_INT_ERR interrupt when an error condition occurs. -//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes. -//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes. -//! -//! \return Returns None. -// -//***************************************************************************** -void -EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32IntFlags < 17); - - // - // Write the interrupt flags mask to the mask register. - // - HWREG(ui32Base + EPI_O_IM) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets the EPI interrupt status. -//! -//! \param ui32Base is the EPI module base address. -//! \param bMasked is set \b true to get the masked interrupt status, or -//! \b false to get the raw interrupt status. -//! -//! This function returns the EPI interrupt status. It can return either -//! the raw or masked interrupt status. -//! -//! \return Returns the masked or raw EPI interrupt status, as a bit field -//! of any of the following values: -//! -//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level. -//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level. -//! - \b EPI_INT_ERR interrupt when an error condition occurs. -//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes. -//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes. -// -//***************************************************************************** -uint32_t -EPIIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + EPI_O_MIS)); - } - else - { - return(HWREG(ui32Base + EPI_O_RIS)); - } -} - -//***************************************************************************** -// -//! Gets the EPI error interrupt status. -//! -//! \param ui32Base is the EPI module base address. -//! -//! This function returns the error status of the EPI. If the return value of -//! the function EPIIntStatus() has the flag \b EPI_INT_ERR set, then this -//! function can be used to determine the cause of the error. -//! -//! \return Returns a bit mask of error flags, which can be the logical -//! OR of any of the following: -//! -//! - \b EPI_INT_ERR_WTFULL occurs when a write stalled when the transaction -//! FIFO was full -//! - \b EPI_INT_ERR_RSTALL occurs when a read stalled -//! - \b EPI_INT_ERR_TIMEOUT occurs when the external clock enable held -//! off a transaction longer than the configured maximum wait time -// -//***************************************************************************** -uint32_t -EPIIntErrorStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Read the error status and return to caller. - // - return(HWREG(ui32Base + EPI_O_EISC)); -} - -//***************************************************************************** -// -//! Clears pending EPI error sources. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32ErrFlags is a bit mask of the error sources to be cleared. -//! -//! This function clears the specified pending EPI errors. The \e ui32ErrFlags -//! parameter can be the logical OR of any of the following values: -//! -//! - \b EPI_INT_ERR_DMAWRIC clears the EPI_INT_DMA_TX_DONE as an interrupt -//! source -//! - \b EPI_INT_ERR_DMARDIC clears the EPI_INT_DMA_RX_DONE as an interrupt -//! source -//! - \b EPI_INT_ERR_WTFULL occurs when a write stalled when the transaction -//! FIFO was full -//! - \b EPI_INT_ERR_RSTALL occurs when a read stalled -//! - \b EPI_INT_ERR_TIMEOUT occurs when the external clock enable held -//! off a transaction longer than the configured maximum wait time -//! -//! \return Returns None. -// -//***************************************************************************** -void -EPIIntErrorClear(uint32_t ui32Base, uint32_t ui32ErrFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32ErrFlags < 0x20); - - // - // Write the error flags to the register to clear the pending errors. - // - HWREG(ui32Base + EPI_O_EISC) = ui32ErrFlags; -} - -//***************************************************************************** -// -//! Returns the interrupt number for a given EPI base address. -//! -//! \param ui32Base is the base address of the EPI module. -//! -//! This function returns the interrupt number for the EPI module with the base -//! address passed in the \e ui32Base parameter. -//! -//! \return Returns the EPI interrupt number or 0 if the interrupt does not -//! exist. -// -//***************************************************************************** -static uint32_t -_EPIIntNumberGet(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // By default, assume EPI is not supported. - // - ui32Int = 0; - - if(CLASS_IS_TM4C129) - { - ui32Int = INT_EPI0_TM4C129; - } - - return(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the EPI module. -//! -//! \param ui32Base is the EPI module base address. -//! \param pfnHandler is a pointer to the function to be called when the -//! interrupt is activated. -//! -//! This sets and enables the handler to be called when the EPI module -//! generates an interrupt. Specific EPI interrupts must still be enabled -//! with the EPIIntEnable() function. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -EPIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(pfnHandler); - - // - // Get the interrupt number for the EPI interface. - // - ui32Int = _EPIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the EPI interface interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Removes a registered interrupt handler for the EPI module. -//! -//! \param ui32Base is the EPI module base address. -//! -//! This function disables and clears the handler to be called when the -//! EPI interrupt occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -EPIIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Get the interrupt number for the EPI interface. - // - ui32Int = _EPIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the EPI interface interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/epi.h b/bsp/tm4c129x-dk/libraries/driverlib/epi.h deleted file mode 100644 index fc26a81469d0da841d97a5daab6468f522f94d1f..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/epi.h +++ /dev/null @@ -1,762 +0,0 @@ -//***************************************************************************** -// -// epi.h - Prototypes and macros for the EPI module. -// -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_EPI_H__ -#define __DRIVERLIB_EPI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to EPIModeSet() -// -//***************************************************************************** -#define EPI_MODE_GENERAL 0x00000010 -#define EPI_MODE_SDRAM 0x00000011 -#define EPI_MODE_HB8 0x00000012 -#define EPI_MODE_HB16 0x00000013 -#define EPI_MODE_DISABLE 0x00000000 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigSDRAMSet() -// -//***************************************************************************** -#define EPI_SDRAM_CORE_FREQ_0_15 \ - 0x00000000 -#define EPI_SDRAM_CORE_FREQ_15_30 \ - 0x40000000 -#define EPI_SDRAM_CORE_FREQ_30_50 \ - 0x80000000 -#define EPI_SDRAM_CORE_FREQ_50_100 \ - 0xC0000000 -#define EPI_SDRAM_LOW_POWER 0x00000200 -#define EPI_SDRAM_FULL_POWER 0x00000000 -#define EPI_SDRAM_SIZE_64MBIT 0x00000000 -#define EPI_SDRAM_SIZE_128MBIT 0x00000001 -#define EPI_SDRAM_SIZE_256MBIT 0x00000002 -#define EPI_SDRAM_SIZE_512MBIT 0x00000003 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigGPModeSet() -// -//***************************************************************************** -#define EPI_GPMODE_CLKPIN 0x80000000 -#define EPI_GPMODE_CLKGATE 0x40000000 -#define EPI_GPMODE_FRAME50 0x04000000 -#define EPI_GPMODE_WRITE2CYCLE 0x00080000 -#define EPI_GPMODE_ASIZE_NONE 0x00000000 -#define EPI_GPMODE_ASIZE_4 0x00000010 -#define EPI_GPMODE_ASIZE_12 0x00000020 -#define EPI_GPMODE_ASIZE_20 0x00000030 -#define EPI_GPMODE_DSIZE_8 0x00000000 -#define EPI_GPMODE_DSIZE_16 0x00000001 -#define EPI_GPMODE_DSIZE_24 0x00000002 -#define EPI_GPMODE_DSIZE_32 0x00000003 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigHB8ModeSet() -// -//***************************************************************************** -#define EPI_HB8_USE_TXEMPTY 0x00800000 -#define EPI_HB8_USE_RXFULL 0x00400000 -#define EPI_HB8_WRHIGH 0x00200000 -#define EPI_HB8_RDHIGH 0x00100000 -#define EPI_HB8_ALE_HIGH 0x00080000 -#define EPI_HB8_ALE_LOW 0x00000000 -#define EPI_HB8_WRWAIT_0 0x00000000 -#define EPI_HB8_WRWAIT_1 0x00000040 -#define EPI_HB8_WRWAIT_2 0x00000080 -#define EPI_HB8_WRWAIT_3 0x000000C0 -#define EPI_HB8_RDWAIT_0 0x00000000 -#define EPI_HB8_RDWAIT_1 0x00000010 -#define EPI_HB8_RDWAIT_2 0x00000020 -#define EPI_HB8_RDWAIT_3 0x00000030 -#define EPI_HB8_MODE_ADMUX 0x00000000 -#define EPI_HB8_MODE_ADDEMUX 0x00000001 -#define EPI_HB8_MODE_SRAM 0x00000002 -#define EPI_HB8_MODE_FIFO 0x00000003 -#define EPI_HB8_WORD_ACCESS 0x00000100 -#define EPI_HB8_CSCFG_ALE 0x00000000 -#define EPI_HB8_CSCFG_CS 0x00000200 -#define EPI_HB8_CSCFG_DUAL_CS 0x00000400 -#define EPI_HB8_CSCFG_ALE_DUAL_CS \ - 0x00000600 -#define EPI_HB8_CSCFG_ALE_SINGLE_CS \ - 0x00001000 -#define EPI_HB8_CSCFG_QUAD_CS 0x00001200 -#define EPI_HB8_CSCFG_ALE_QUAD_CS \ - 0x00001400 -#define EPI_HB8_CSBAUD 0x00000800 -#define EPI_HB8_CLOCK_GATE 0x80000000 -#define EPI_HB8_CLOCK_GATE_IDLE \ - 0x40000000 -#define EPI_HB8_CLOCK_INVERT 0x20000000 -#define EPI_HB8_IN_READY_EN 0x10000000 -#define EPI_HB8_IN_READY_EN_INVERT \ - 0x18000000 -#define EPI_HB8_CSCFG_MASK 0x00001600 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigHB16ModeSet() -// -//***************************************************************************** -#define EPI_HB16_USE_TXEMPTY 0x00800000 -#define EPI_HB16_USE_RXFULL 0x00400000 -#define EPI_HB16_WRHIGH 0x00200000 -#define EPI_HB16_RDHIGH 0x00100000 -#define EPI_HB16_WRWAIT_0 0x00000000 -#define EPI_HB16_WRWAIT_1 0x00000040 -#define EPI_HB16_WRWAIT_2 0x00000080 -#define EPI_HB16_WRWAIT_3 0x000000C0 -#define EPI_HB16_RDWAIT_0 0x00000000 -#define EPI_HB16_RDWAIT_1 0x00000010 -#define EPI_HB16_RDWAIT_2 0x00000020 -#define EPI_HB16_RDWAIT_3 0x00000030 -#define EPI_HB16_MODE_ADMUX 0x00000000 -#define EPI_HB16_MODE_ADDEMUX 0x00000001 -#define EPI_HB16_MODE_SRAM 0x00000002 -#define EPI_HB16_MODE_FIFO 0x00000003 -#define EPI_HB16_BSEL 0x00000004 -#define EPI_HB16_WORD_ACCESS 0x00000100 -#define EPI_HB16_CSCFG_ALE 0x00000000 -#define EPI_HB16_CSCFG_CS 0x00000200 -#define EPI_HB16_CSCFG_DUAL_CS 0x00000400 -#define EPI_HB16_CSCFG_ALE_DUAL_CS \ - 0x00000600 -#define EPI_HB16_CSCFG_ALE_SINGLE_CS \ - 0x00001000 -#define EPI_HB16_CSCFG_QUAD_CS 0x00001200 -#define EPI_HB16_CSCFG_ALE_QUAD_CS \ - 0x00001400 -#define EPI_HB16_CLOCK_GATE 0x80000000 -#define EPI_HB16_CLOCK_GATE_IDLE \ - 0x40000000 -#define EPI_HB16_CLOCK_INVERT 0x20000000 -#define EPI_HB16_IN_READY_EN 0x10000000 -#define EPI_HB16_IN_READY_EN_INVERTED \ - 0x18000000 -#define EPI_HB16_ALE_HIGH 0x00080000 -#define EPI_HB16_ALE_LOW 0x00000000 -#define EPI_HB16_BURST_TRAFFIC 0x00010000 -#define EPI_HB16_CSBAUD 0x00000800 -#define EPI_HB16_CSCFG_MASK 0x00001600 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigHB8TimingSet(). -// -//***************************************************************************** -#define EPI_HB8_IN_READY_DELAY_1 \ - 0x01000000 -#define EPI_HB8_IN_READY_DELAY_2 \ - 0x02000000 -#define EPI_HB8_IN_READY_DELAY_3 \ - 0x03000000 -#define EPI_HB8_CAP_WIDTH_1 0x00001000 -#define EPI_HB8_CAP_WIDTH_2 0x00002000 -#define EPI_HB8_WRWAIT_MINUS_DISABLE \ - 0x00000000 -#define EPI_HB8_WRWAIT_MINUS_ENABLE \ - 0x00000010 -#define EPI_HB8_RDWAIT_MINUS_DISABLE \ - 0x00000000 -#define EPI_HB8_RDWAIT_MINUS_ENABLE \ - 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigHB16TimingSet(). -// -//***************************************************************************** -#define EPI_HB16_IN_READY_DELAY_1 \ - 0x01000000 -#define EPI_HB16_IN_READY_DELAY_2 \ - 0x02000000 -#define EPI_HB16_IN_READY_DELAY_3 \ - 0x03000000 -#define EPI_HB16_PSRAM_NO_LIMIT 0x00000000 -#define EPI_HB16_PSRAM_128 0x00010000 -#define EPI_HB16_PSRAM_256 0x00020000 -#define EPI_HB16_PSRAM_512 0x00030000 -#define EPI_HB16_PSRAM_1024 0x00040000 -#define EPI_HB16_PSRAM_2048 0x00050000 -#define EPI_HB16_PSRAM_4096 0x00060000 -#define EPI_HB16_PSRAM_8192 0x00070000 -#define EPI_HB16_CAP_WIDTH_1 0x00001000 -#define EPI_HB16_CAP_WIDTH_2 0x00002000 -#define EPI_HB16_WRWAIT_MINUS_DISABLE \ - 0x00000000 -#define EPI_HB16_WRWAIT_MINUS_ENABLE \ - 0x00000008 -#define EPI_HB16_RDWAIT_MINUS_DISABLE \ - 0x00000000 -#define EPI_HB16_RDWAIT_MINUS_ENABLE \ - 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to EPIAddressMapSet(). -// -//***************************************************************************** -#define EPI_ADDR_PER_SIZE_256B 0x00000000 -#define EPI_ADDR_PER_SIZE_64KB 0x00000040 -#define EPI_ADDR_PER_SIZE_16MB 0x00000080 -#define EPI_ADDR_PER_SIZE_256MB 0x000000C0 -#define EPI_ADDR_PER_BASE_NONE 0x00000000 -#define EPI_ADDR_PER_BASE_A 0x00000010 -#define EPI_ADDR_PER_BASE_C 0x00000020 -#define EPI_ADDR_RAM_SIZE_256B 0x00000000 -#define EPI_ADDR_RAM_SIZE_64KB 0x00000004 -#define EPI_ADDR_RAM_SIZE_16MB 0x00000008 -#define EPI_ADDR_RAM_SIZE_256MB 0x0000000C -#define EPI_ADDR_RAM_BASE_NONE 0x00000000 -#define EPI_ADDR_RAM_BASE_6 0x00000001 -#define EPI_ADDR_RAM_BASE_8 0x00000002 -#define EPI_ADDR_QUAD_MODE 0x00000033 -#define EPI_ADDR_CODE_SIZE_256B 0x00000000 -#define EPI_ADDR_CODE_SIZE_64KB 0x00000400 -#define EPI_ADDR_CODE_SIZE_16MB 0x00000800 -#define EPI_ADDR_CODE_SIZE_256MB \ - 0x00000C00 -#define EPI_ADDR_CODE_BASE_NONE 0x00000000 -#define EPI_ADDR_CODE_BASE_1 0x00000100 - -//***************************************************************************** -// -// Values that can be passed to EPINonBlockingReadConfigure() -// -//***************************************************************************** -#define EPI_NBCONFIG_SIZE_8 1 -#define EPI_NBCONFIG_SIZE_16 2 -#define EPI_NBCONFIG_SIZE_32 3 - -//***************************************************************************** -// -// Values that can be passed to EPIFIFOConfig() -// -//***************************************************************************** -#define EPI_FIFO_CONFIG_WTFULLERR \ - 0x00020000 -#define EPI_FIFO_CONFIG_RSTALLERR \ - 0x00010000 -#define EPI_FIFO_CONFIG_TX_EMPTY \ - 0x00000000 -#define EPI_FIFO_CONFIG_TX_1_4 0x00000020 -#define EPI_FIFO_CONFIG_TX_1_2 0x00000030 -#define EPI_FIFO_CONFIG_TX_3_4 0x00000040 -#define EPI_FIFO_CONFIG_RX_1_8 0x00000001 -#define EPI_FIFO_CONFIG_RX_1_4 0x00000002 -#define EPI_FIFO_CONFIG_RX_1_2 0x00000003 -#define EPI_FIFO_CONFIG_RX_3_4 0x00000004 -#define EPI_FIFO_CONFIG_RX_7_8 0x00000005 -#define EPI_FIFO_CONFIG_RX_FULL 0x00000006 - -//***************************************************************************** -// -// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned -// as flags from EPIIntStatus() -// -//***************************************************************************** -#define EPI_INT_DMA_TX_DONE 0x00000010 -#define EPI_INT_DMA_RX_DONE 0x00000008 -#define EPI_INT_TXREQ 0x00000004 -#define EPI_INT_RXREQ 0x00000002 -#define EPI_INT_ERR 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to EPIIntErrorClear(), or returned as flags from -// EPIIntErrorStatus() -// -//***************************************************************************** -#define EPI_INT_ERR_DMAWRIC 0x00000010 -#define EPI_INT_ERR_DMARDIC 0x00000008 -#define EPI_INT_ERR_WTFULL 0x00000004 -#define EPI_INT_ERR_RSTALL 0x00000002 -#define EPI_INT_ERR_TIMEOUT 0x00000001 - -#ifdef rvmdk -//***************************************************************************** -// -// Keil case. -// -//***************************************************************************** -inline void -EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value) -{ - uint32_t ui32Scratch; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the write we're actually interested in. - // - STR ui32Value, [pui32Addr] - - // - // Read from SRAM to ensure that we don't have an EPI write followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } -} - -inline uint32_t -EPIWorkaroundWordRead(uint32_t *pui32Addr) -{ - uint32_t ui32Value, ui32Scratch; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the read we're actually interested in. - // - LDR ui32Value, [pui32Addr] - - // - // Read from SRAM to ensure that we don't have an EPI read followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } - - return(ui32Value); -} - -inline void -EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value) -{ - uint32_t ui32Scratch; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the write we're actually interested in. - // - STRH ui16Value, [pui16Addr] - - // - // Read from SRAM to ensure that we don't have an EPI write followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } -} - -inline uint16_t -EPIWorkaroundHWordRead(uint16_t *pui16Addr) -{ - uint32_t ui32Scratch; - uint16_t ui16Value; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the read we're actually interested in. - // - LDRH ui16Value, [pui16Addr] - - // - // Read from SRAM to ensure that we don't have an EPI read followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } - - return(ui16Value); -} - -inline void -EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value) -{ - uint32_t ui32Scratch; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the write we're actually interested in. - // - STRB ui8Value, [pui8Addr] - - // - // Read from SRAM to ensure that we don't have an EPI write followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } -} - -inline uint8_t -EPIWorkaroundByteRead(uint8_t *pui8Addr) -{ - uint32_t ui32Scratch; - uint8_t ui8Value; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the read we're actually interested in. - // - LDRB ui8Value, [pui8Addr] - - // - // Read from SRAM to ensure that we don't have an EPI read followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } - - return(ui8Value); -} -#endif - -#ifdef ccs -//***************************************************************************** -// -// Code Composer Studio versions of these functions can be found in separate -// source file epi_workaround_ccs.s. -// -//***************************************************************************** -extern void EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value); -extern uint32_t EPIWorkaroundWordRead(uint32_t *pui32Addr); -extern void EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value); -extern uint16_t EPIWorkaroundHWordRead(uint16_t *pui16Addr); -extern void EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value); -extern uint8_t EPIWorkaroundByteRead(uint8_t *pui8Addr); - -#endif - -#if (defined gcc) || (defined ewarm) || (defined sourcerygxx) || \ - (defined codered) -//***************************************************************************** -// -// GCC-based toolchain and IAR case. -// -//***************************************************************************** -inline void -EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value) -{ - volatile register uint32_t ui32Scratch; - - __asm volatile ( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " STR %[value],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui32Addr), [value] "r" (ui32Value) - ); - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; -} - -inline uint32_t -EPIWorkaroundWordRead(uint32_t *pui32Addr) -{ - volatile register uint32_t ui32Data, ui32Scratch; - - // - // ui32Scratch is not used other than to add a padding read following the - // "real" read. - // - - __asm volatile( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " LDR %[ret],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [ret] "=r" (ui32Data), - [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui32Addr) - ); - - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; - - return(ui32Data); -} - -inline void -EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value) -{ - volatile register uint32_t ui32Scratch; - - __asm volatile ( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " STRH %[value],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui16Addr), [value] "r" (ui16Value) - ); - - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; -} - -inline uint16_t -EPIWorkaroundHWordRead(uint16_t *pui16Addr) -{ - register uint16_t ui16Data; - register uint32_t ui32Scratch; - - // - // ui32Scratch is not used other than to add a padding read following the - // "real" read. - // - - __asm volatile( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " LDRH %[ret],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [ret] "=r" (ui16Data), - [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui16Addr) - ); - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; - - return(ui16Data); -} - -inline void -EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value) -{ - volatile register uint32_t ui32Scratch; - - __asm volatile ( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " STRB %[value],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui8Addr), [value] "r" (ui8Value) - ); - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; -} - -inline uint8_t -EPIWorkaroundByteRead(uint8_t *pui8Addr) -{ - register uint8_t ui8Data; - register uint32_t ui32Scratch; - - // - // ui32Scratch is not used other than to add a padding read following the - // "real" read. - // - - __asm volatile( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " LDRB %[ret],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [ret] "=r" (ui8Data), - [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui8Addr) - ); - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; - - return(ui8Data); -} -#endif - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode); -extern void EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider); -extern void EPIDividerCSSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Divider); -extern void EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count); -extern void EPIConfigGPModeSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32FrameCount, uint32_t ui32MaxWait); -extern void EPIConfigHB8Set(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32MaxWait); -extern void EPIConfigHB16Set(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32MaxWait); -extern void EPIConfigHB8CSSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Config); -extern void EPIConfigHB16CSSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Config); -extern void EPIConfigHB8TimingSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Config); -extern void EPIConfigHB16TimingSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Config); -extern void EPIPSRAMConfigRegSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32CR); -extern void EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS); -extern bool EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base, - uint32_t ui32CS, - uint32_t *pui32CR); -extern uint32_t EPIPSRAMConfigRegGet(uint32_t ui32Base, uint32_t ui32CS); -extern void EPIConfigSDRAMSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32Refresh); -extern void EPIAddressMapSet(uint32_t ui32Base, uint32_t ui32Map); -extern void EPINonBlockingReadConfigure(uint32_t ui32Base, - uint32_t ui32Channel, - uint32_t ui32DataSize, - uint32_t ui32Address); -extern void EPINonBlockingReadStart(uint32_t ui32Base, - uint32_t ui32Channel, - uint32_t ui32Count); -extern void EPINonBlockingReadStop(uint32_t ui32Base, - uint32_t ui32Channel); -extern uint32_t EPINonBlockingReadCount(uint32_t ui32Base, - uint32_t ui32Channel); -extern uint32_t EPINonBlockingReadAvail(uint32_t ui32Base); -extern uint32_t EPINonBlockingReadGet32(uint32_t ui32Base, - uint32_t ui32Count, - uint32_t *pui32Buf); -extern uint32_t EPINonBlockingReadGet16(uint32_t ui32Base, - uint32_t ui32Count, - uint16_t *pui16Buf); -extern uint32_t EPINonBlockingReadGet8(uint32_t ui32Base, - uint32_t ui32Count, - uint8_t *pui8Buf); -extern void EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config); -extern uint32_t EPIWriteFIFOCountGet(uint32_t ui32Base); -extern void EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t EPIIntStatus(uint32_t ui32Base, bool bMasked); -extern uint32_t EPIIntErrorStatus(uint32_t ui32Base); -extern void EPIIntErrorClear(uint32_t ui32Base, uint32_t ui32ErrFlags); -extern void EPIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void EPIIntUnregister(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_EPI_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/flash.c b/bsp/tm4c129x-dk/libraries/driverlib/flash.c deleted file mode 100644 index 158176a766cd4031be9a3883928388d519ab5780..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/flash.c +++ /dev/null @@ -1,977 +0,0 @@ -//***************************************************************************** -// -// flash.c - Driver for programming the on-chip flash. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup flash_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_flash.h" -#include "inc/hw_ints.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/flash.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -// An array that maps the specified memory bank to the appropriate Flash -// Memory Protection Program Enable (FMPPE) register. -// -//***************************************************************************** -static const uint32_t g_pui32FMPPERegs[] = -{ - FLASH_FMPPE0, - FLASH_FMPPE1, - FLASH_FMPPE2, - FLASH_FMPPE3, - FLASH_FMPPE4, - FLASH_FMPPE5, - FLASH_FMPPE6, - FLASH_FMPPE7, - FLASH_FMPPE8, - FLASH_FMPPE9, - FLASH_FMPPE10, - FLASH_FMPPE11, - FLASH_FMPPE12, - FLASH_FMPPE13, - FLASH_FMPPE14, - FLASH_FMPPE15, -}; - -//***************************************************************************** -// -// An array that maps the specified memory bank to the appropriate Flash -// Memory Protection Read Enable (FMPRE) register. -// -//***************************************************************************** -static const uint32_t g_pui32FMPRERegs[] = -{ - FLASH_FMPRE0, - FLASH_FMPRE1, - FLASH_FMPRE2, - FLASH_FMPRE3, - FLASH_FMPRE4, - FLASH_FMPRE5, - FLASH_FMPRE6, - FLASH_FMPRE7, - FLASH_FMPRE8, - FLASH_FMPRE9, - FLASH_FMPRE10, - FLASH_FMPRE11, - FLASH_FMPRE12, - FLASH_FMPRE13, - FLASH_FMPRE14, - FLASH_FMPRE15, -}; - -//***************************************************************************** -// -//! Erases a block of flash. -//! -//! \param ui32Address is the start address of the flash block to be erased. -//! -//! This function erases a block of the on-chip flash. After erasing, the -//! block is filled with 0xFF bytes. Read-only and execute-only blocks cannot -//! be erased. -//! -//! The flash block size is device-class dependent. All TM4C123x devices use -//! 1-KB blocks but TM4C129x devices use 16-KB blocks. Please consult the -//! device datasheet to determine the block size in use. -//! -//! This function does not return until the block has been erased. -//! -//! \return Returns 0 on success, or -1 if an invalid block address was -//! specified or the block is write-protected. -// -//***************************************************************************** -int32_t -FlashErase(uint32_t ui32Address) -{ - // - // Check the arguments. - // - ASSERT(!(ui32Address & (FLASH_ERASE_SIZE - 1))); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | - FLASH_FCMISC_ERMISC); - - // - // Erase the block. - // - HWREG(FLASH_FMA) = ui32Address; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE; - - // - // Wait until the block has been erased. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE) - { - } - - // - // Return an error if an access violation or erase error occurred. - // - if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | - FLASH_FCRIS_ERRIS)) - { - return(-1); - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Programs flash. -//! -//! \param pui32Data is a pointer to the data to be programmed. -//! \param ui32Address is the starting address in flash to be programmed. Must -//! be a multiple of four. -//! \param ui32Count is the number of bytes to be programmed. Must be a -//! multiple of four. -//! -//! This function programs a sequence of words into the on-chip flash. -//! Because the flash is programmed one word at a time, the starting address -//! and byte count must both be multiples of four. It is up to the caller to -//! verify the programmed contents, if such verification is required. -//! -//! This function does not return until the data has been programmed. -//! -//! \return Returns 0 on success, or -1 if a programming error is encountered. -// -//***************************************************************************** -int32_t -FlashProgram(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count) -{ - // - // Check the arguments. - // - ASSERT(!(ui32Address & 3)); - ASSERT(!(ui32Count & 3)); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | - FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC); - - // - // Loop over the words to be programmed. - // - while(ui32Count) - { - // - // Set the address of this block of words. - // - HWREG(FLASH_FMA) = ui32Address & ~(0x7f); - - // - // Loop over the words in this 32-word block. - // - while(((ui32Address & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) && - (ui32Count != 0)) - { - // - // Write this word into the write buffer. - // - HWREG(FLASH_FWBN + (ui32Address & 0x7c)) = *pui32Data++; - ui32Address += 4; - ui32Count -= 4; - } - - // - // Program the contents of the write buffer into flash. - // - HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF; - - // - // Wait until the write buffer has been programmed. - // - while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF) - { - } - } - - // - // Return an error if an access violation occurred. - // - if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | - FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS)) - { - return(-1); - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Gets the protection setting for a block of flash. -//! -//! \param ui32Address is the start address of the flash block to be queried. -//! -//! This function gets the current protection for the specified block of flash. -//! Refer to the device data sheet to determine the granularity for each -//! protection option. A block can be read/write, read-only, or execute-only. -//! Read/write blocks can be read, executed, erased, and programmed. Read-only -//! blocks can be read and executed. Execute-only blocks can only be executed; -//! processor and debugger data reads are not allowed. -//! -//! \return Returns the protection setting for this block. See -//! FlashProtectSet() for possible values. -// -//***************************************************************************** -tFlashProtection -FlashProtectGet(uint32_t ui32Address) -{ - uint32_t ui32FMPRE, ui32FMPPE; - uint32_t ui32Bank; - - // - // Check the argument. - // - ASSERT(!(ui32Address & (FLASH_PROTECT_SIZE - 1))); - - // - // Calculate the Flash Bank from Base Address, and mask off the Bank - // from ui32Address for subsequent reference. - // - ui32Bank = (((ui32Address / FLASH_PROTECT_SIZE) / 32) % 4); - ui32Address &= ((FLASH_PROTECT_SIZE * 32) - 1); - - // - // Read the appropriate flash protection registers for the specified - // flash bank. - // - ui32FMPRE = HWREG(g_pui32FMPRERegs[ui32Bank]); - ui32FMPPE = HWREG(g_pui32FMPPERegs[ui32Bank]); - - // - // Check the appropriate protection bits for the block of memory that - // is specified by the address. - // - switch((((ui32FMPRE >> (ui32Address / FLASH_PROTECT_SIZE)) & 0x1) << 1) | - ((ui32FMPPE >> (ui32Address / FLASH_PROTECT_SIZE)) & 0x1)) - { - // - // This block is marked as execute only (that is, it can not be erased - // or programmed, and the only reads allowed are via the instruction - // fetch interface). - // - case 0: - case 1: - { - return(FlashExecuteOnly); - } - - // - // This block is marked as read only (that is, it can not be erased or - // programmed). - // - case 2: - { - return(FlashReadOnly); - } - - // - // This block is read/write; it can be read, erased, and programmed. - // - case 3: - default: - { - return(FlashReadWrite); - } - } -} - -//***************************************************************************** -// -//! Sets the protection setting for a block of flash. -//! -//! \param ui32Address is the start address of the flash block to be protected. -//! \param eProtect is the protection to be applied to the block. Can be one -//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. -//! -//! This function sets the protection for the specified block of flash. Refer -//! to the device data sheet to determine the granularity for each protection -//! option. Blocks that are read/write can be made read-only or execute-only. -//! Blocks that are read-only can be made execute-only. Blocks that are -//! execute-only cannot have their protection modified. Attempts to make the -//! block protection less stringent (that is, read-only to read/write) -//! result in a failure (and are prevented by the hardware). -//! -//! Changes to the flash protection are maintained only until the next reset. -//! This protocol allows the application to be executed in the desired flash -//! protection environment to check for inappropriate flash access (via the -//! flash interrupt). To make the flash protection permanent, use the -//! FlashProtectSave() function. -//! -//! \return Returns 0 on success, or -1 if an invalid address or an invalid -//! protection was specified. -// -//***************************************************************************** -int32_t -FlashProtectSet(uint32_t ui32Address, tFlashProtection eProtect) -{ - uint32_t ui32ProtectRE, ui32ProtectPE; - uint32_t ui32Bank; - - // - // Check the argument. - // - ASSERT(!(ui32Address & (FLASH_PROTECT_SIZE - 1))); - ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) || - (eProtect == FlashExecuteOnly)); - - // - // Convert the address into a block number. - // - ui32Address /= FLASH_PROTECT_SIZE; - - // - // ui32Address contains a "raw" block number. Derive the Flash Bank from - // the "raw" block number, and convert ui32Address to a "relative" - // block number. - // - ui32Bank = ((ui32Address / 32) % 4); - ui32Address %= 32; - - // - // Get the current protection for the specified flash bank. - // - ui32ProtectRE = HWREG(g_pui32FMPRERegs[ui32Bank]); - ui32ProtectPE = HWREG(g_pui32FMPPERegs[ui32Bank]); - - // - // Set the protection based on the requested protection. - // - switch(eProtect) - { - // - // Make this block execute only. - // - case FlashExecuteOnly: - { - // - // Turn off the read and program bits for this block. - // - ui32ProtectRE &= ~(0x1 << ui32Address); - ui32ProtectPE &= ~(0x1 << ui32Address); - - // - // We're done handling this protection. - // - break; - } - - // - // Make this block read only. - // - case FlashReadOnly: - { - // - // The block can not be made read only if it is execute only. - // - if(((ui32ProtectRE >> ui32Address) & 0x1) != 0x1) - { - return(-1); - } - - // - // Make this block read only. - // - ui32ProtectPE &= ~(0x1 << ui32Address); - - // - // We're done handling this protection. - // - break; - } - - // - // Make this block read/write. - // - case FlashReadWrite: - default: - { - // - // The block can not be made read/write if it is not already - // read/write. - // - if((((ui32ProtectRE >> ui32Address) & 0x1) != 0x1) || - (((ui32ProtectPE >> ui32Address) & 0x1) != 0x1)) - { - return(-1); - } - - // - // The block is already read/write, so there is nothing to do. - // - return(0); - } - } - - // - // Set the new protection for the specified flash bank. - // - HWREG(g_pui32FMPRERegs[ui32Bank]) = ui32ProtectRE; - HWREG(g_pui32FMPPERegs[ui32Bank]) = ui32ProtectPE; - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Saves the flash protection settings. -//! -//! This function makes the currently programmed flash protection settings -//! permanent. This operation is non-reversible; a chip reset or power cycle -//! does not change the flash protection. -//! -//! This function does not return until the protection has been saved. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashProtectSave(void) -{ - uint32_t ui32Temp; - - // - // Save the entire bank of 8 flash protection registers. - // - for(ui32Temp = 0; ui32Temp < 8; ui32Temp++) - { - // - // Tell the flash controller to write the flash protection register. - // - HWREG(FLASH_FMA) = ui32Temp; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Gets the user registers. -//! -//! \param pui32User0 is a pointer to the location to store USER Register 0. -//! \param pui32User1 is a pointer to the location to store USER Register 1. -//! -//! This function reads the contents of user registers 0 and 1, and -//! stores them in the specified locations. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1) -{ - // - // Verify that the pointers are valid. - // - ASSERT(pui32User0 != 0); - ASSERT(pui32User1 != 0); - - // - // Get and store the current value of the user registers. - // - *pui32User0 = HWREG(FLASH_USERREG0); - *pui32User1 = HWREG(FLASH_USERREG1); - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Sets the user registers. -//! -//! \param ui32User0 is the value to store in USER Register 0. -//! \param ui32User1 is the value to store in USER Register 1. -//! -//! This function sets the contents of the user registers 0 and 1 to -//! the specified values. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashUserSet(uint32_t ui32User0, uint32_t ui32User1) -{ - // - // Save the new values into the user registers. - // - HWREG(FLASH_USERREG0) = ui32User0; - HWREG(FLASH_USERREG1) = ui32User1; - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Gets all the user registers. -//! -//! \param pui32User0 is a pointer to the location to store USER Register 0. -//! \param pui32User1 is a pointer to the location to store USER Register 1. -//! \param pui32User2 is a pointer to the location to store USER Register 2. -//! \param pui32User3 is a pointer to the location to store USER Register 3. -//! -//! This function reads the contents of user registers 0, 1, 2 and 3, and -//! stores them in the specified locations. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashAllUserRegisterGet(uint32_t *pui32User0, uint32_t *pui32User1, - uint32_t *pui32User2, uint32_t *pui32User3) -{ - // - // Verify that the pointers are valid. - // - ASSERT(pui32User0 != 0); - ASSERT(pui32User1 != 0); - ASSERT(pui32User2 != 0); - ASSERT(pui32User3 != 0); - - // - // Get and store the current value of the user registers. - // - *pui32User0 = HWREG(FLASH_USERREG0); - *pui32User1 = HWREG(FLASH_USERREG1); - *pui32User2 = HWREG(FLASH_USERREG2); - *pui32User3 = HWREG(FLASH_USERREG3); - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Sets the user registers 0 to 3 -//! -//! \param ui32User0 is the value to store in USER Register 0. -//! \param ui32User1 is the value to store in USER Register 1. -//! \param ui32User2 is the value to store in USER Register 2. -//! \param ui32User3 is the value to store in USER Register 3. -//! -//! This function sets the contents of the user registers 0, 1, 2 and 3 to -//! the specified values. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashAllUserRegisterSet(uint32_t ui32User0, uint32_t ui32User1, - uint32_t ui32User2, uint32_t ui32User3) -{ - // - // Save the new values into the user registers. - // - HWREG(FLASH_USERREG0) = ui32User0; - HWREG(FLASH_USERREG1) = ui32User1; - HWREG(FLASH_USERREG2) = ui32User2; - HWREG(FLASH_USERREG3) = ui32User3; - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Saves the user registers 0 and 1. -//! -//! This function makes the currently programmed user register 0 and 1 settings -//! permanent. This operation is non-reversible; a chip reset or power cycle -//! does not change the flash protection. -//! -//! This function does not return until the protection has been saved. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashUserSave(void) -{ - // - // Setting the MSB of FMA will trigger a permanent save of a USER - // register. Bit 0 will indicate User 0 (0) or User 1 (1). - // - HWREG(FLASH_FMA) = 0x80000000; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - - // - // Tell the flash controller to write the USER1 Register. - // - HWREG(FLASH_FMA) = 0x80000001; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Saves the user registers. -//! -//! This function makes the currently programmed user register 0, 1, 2 and 3 -//! settings permanent. This operation is non-reversible; a chip reset or -//! power cycle does not change the flash protection. -//! -//! This function does not return until the protection has been saved. -//! -//! \note To ensure data integrity of the user registers, the commits should -//! not be interrupted with a power loss. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashAllUserRegisterSave(void) -{ - uint32_t ui32Index; - - // - // Setting the MSB of FMA will trigger a permanent save of a USER Register. - // The 2 least signigicant bits, specify the exact User Register to save. - // The value of the least significant bits for - // USER Register 0 is 00, - // USER Register 1 is 01, - // USER Register 2 is 10 and - // USER Register 3 is 11. - // - for(ui32Index = 0; ui32Index < 4; ui32Index++) - { - // - // Tell the flash controller to commit a USER Register. - // - HWREG(FLASH_FMA) = (0x80000000 + ui32Index); - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the flash interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the flash -//! interrupt occurs. -//! -//! This function sets the handler to be called when the flash interrupt -//! occurs. The flash controller can generate an interrupt when an invalid -//! flash access occurs, such as trying to program or erase a read-only block, -//! or trying to read from an execute-only block. It can also generate an -//! interrupt when a program or erase operation has completed. The interrupt -//! is automatically enabled when the handler is registered. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_FLASH_TM4C123, pfnHandler); - - // - // Enable the flash interrupt. - // - IntEnable(INT_FLASH_TM4C123); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the flash interrupt. -//! -//! This function clears the handler to be called when the flash interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(INT_FLASH_TM4C123); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_FLASH_TM4C123); -} - -//***************************************************************************** -// -//! Enables individual flash controller interrupt sources. -//! -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! The ui32IntFlags parameter can be the logical OR of any of the following -//! values: -//! -//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted -//! on a block of flash that is marked as read-only or execute-only. -//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes. -//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of -//! the EEPROM interrupt can be determined by reading the EEDONE register. -//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during -//! the flash operation and the operation was terminated. -//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that -//! contains a 0 to a 1. -//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails. -//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails. -//! -//! This function enables the indicated flash controller interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntEnable(uint32_t ui32IntFlags) -{ - // - // Enable the specified interrupts. - // - HWREG(FLASH_FCIM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual flash controller interrupt sources. -//! -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! The ui32IntFlags parameter can be the logical OR of any of the following -//! values: -//! -//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted -//! on a block of flash that is marked as read-only or execute-only. -//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes. -//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of -//! the EEPROM interrupt can be determined by reading the EEDONE register. -//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during -//! the flash operation and the operation was terminated. -//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that -//! contains a 0 to a 1. -//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails. -//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails. -//! -//! This function disables the indicated flash controller interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntDisable(uint32_t ui32IntFlags) -{ - // - // Disable the specified interrupts. - // - HWREG(FLASH_FCIM) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the flash controller. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b FLASH_INT_ACCESS, \b FLASH_INT_PROGRAM, \b FLASH_INT_EEPROM, -//! FLASH_INT_VOLTAGE_ERR, FLASH_INT_DATA_ERR, FLASH_INT_ERASE_ERR, and -//! FLASH_INT_PROGRAM_ERR. -// -//***************************************************************************** -uint32_t -FlashIntStatus(bool bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(FLASH_FCMISC)); - } - else - { - return(HWREG(FLASH_FCRIS)); - } -} - -//***************************************************************************** -// -//! Clears flash controller interrupt sources. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared. -//! -//! The specified flash controller interrupt sources are cleared, so that they -//! no longer assert. The -//! ui32IntFlags parameter can be the logical OR of any of the following -//! values: -//! -//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted -//! on a block of flash that is marked as read-only or execute-only. -//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes. -//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of -//! the EEPROM interrupt can be determined by reading the EEDONE register. -//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during -//! the flash operation and the operation was terminated. -//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that -//! contains a 0 to a 1. -//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails. -//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails. -//! -//! This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntClear(uint32_t ui32IntFlags) -{ - // - // Clear the flash interrupt. - // - HWREG(FLASH_FCMISC) = ui32IntFlags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/flash.h b/bsp/tm4c129x-dk/libraries/driverlib/flash.h deleted file mode 100644 index 0d20ab1c4822249475ac65fe54a8aa102651d1db..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/flash.h +++ /dev/null @@ -1,122 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_FLASH_H__ -#define __DRIVERLIB_FLASH_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and -// returned from FlashIntStatus(). -// -//***************************************************************************** -#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask -#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask -#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask -#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask -#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask -#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask -#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern int32_t FlashErase(uint32_t ui32Address); -extern int32_t FlashProgram(uint32_t *pui32Data, uint32_t ui32Address, - uint32_t ui32Count); -extern tFlashProtection FlashProtectGet(uint32_t ui32Address); -extern int32_t FlashProtectSet(uint32_t ui32Address, - tFlashProtection eProtect); -extern int32_t FlashProtectSave(void); -extern int32_t FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1); -extern int32_t FlashUserSet(uint32_t ui32User0, uint32_t ui32User1); -extern int32_t FlashAllUserRegisterGet(uint32_t *pui32User0, - uint32_t *pui32User1, - uint32_t *pui32User2, - uint32_t *pui32User3); -extern int32_t FlashAllUserRegisterSet(uint32_t ui32User0, - uint32_t ui32User1, - uint32_t ui32User2, - uint32_t ui32User3); -extern int32_t FlashUserSave(void); -extern int32_t FlashAllUserRegisterSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(uint32_t ui32IntFlags); -extern void FlashIntDisable(uint32_t ui32IntFlags); -extern uint32_t FlashIntStatus(bool bMasked); -extern void FlashIntClear(uint32_t ui32IntFlags); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_FLASH_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/fpu.c b/bsp/tm4c129x-dk/libraries/driverlib/fpu.c deleted file mode 100644 index 8e0d793da6ee5633eeec5d4176b47e14bdfe287e..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/fpu.c +++ /dev/null @@ -1,300 +0,0 @@ -//***************************************************************************** -// -// fpu.c - Routines for manipulating the floating-point unit in the Cortex-M -// processor. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup fpu_api -//! @{ -// -//***************************************************************************** - -#include -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "driverlib/fpu.h" - -//***************************************************************************** -// -//! Enables the floating-point unit. -//! -//! This function enables the floating-point unit, allowing the floating-point -//! instructions to be executed. This function must be called prior to -//! performing any hardware floating-point operations; failure to do so results -//! in a NOCP usage fault. -//! -//! \return None. -// -//***************************************************************************** -void -FPUEnable(void) -{ - // - // Enable the coprocessors used by the floating-point unit. - // - HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & - ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | - NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); -} - -//***************************************************************************** -// -//! Disables the floating-point unit. -//! -//! This function disables the floating-point unit, preventing floating-point -//! instructions from executing (generating a NOCP usage fault instead). -//! -//! \return None. -// -//***************************************************************************** -void -FPUDisable(void) -{ - // - // Disable the coprocessors used by the floating-point unit. - // - HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & - ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | - NVIC_CPAC_CP10_DIS | NVIC_CPAC_CP11_DIS); -} - -//***************************************************************************** -// -//! Enables the stacking of floating-point registers. -//! -//! This function enables the stacking of floating-point registers s0-s15 when -//! an interrupt is handled. When enabled, space is reserved on the stack for -//! the floating-point context and the floating-point state is saved into this -//! stack space. Upon return from the interrupt, the floating-point context is -//! restored. -//! -//! If the floating-point registers are not stacked, floating-point -//! instructions cannot be safely executed in an interrupt handler because the -//! values of s0-s15 are not likely to be preserved for the interrupted code. -//! On the other hand, stacking the floating-point registers increases the -//! stacking operation from 8 words to 26 words, also increasing the interrupt -//! response latency. -//! -//! \return None. -// -//***************************************************************************** -void -FPUStackingEnable(void) -{ - // - // Enable automatic state preservation for the floating-point unit, and - // disable lazy state preservation (meaning that the floating-point state - // is always stacked when floating-point instructions are used). - // - HWREG(NVIC_FPCC) = (HWREG(NVIC_FPCC) & ~NVIC_FPCC_LSPEN) | NVIC_FPCC_ASPEN; -} - -//***************************************************************************** -// -//! Enables the lazy stacking of floating-point registers. -//! -//! This function enables the lazy stacking of floating-point registers s0-s15 -//! when an interrupt is handled. When lazy stacking is enabled, space is -//! reserved on the stack for the floating-point context, but the -//! floating-point state is not saved. If a floating-point instruction is -//! executed from within the interrupt context, the floating-point context is -//! first saved into the space reserved on the stack. On completion of the -//! interrupt handler, the floating-point context is only restored if it was -//! saved (as the result of executing a floating-point instruction). -//! -//! This method provides a compromise between fast interrupt response (because -//! the floating-point state is not saved on interrupt entry) and the ability -//! to use floating-point in interrupt handlers (because the floating-point -//! state is saved if floating-point instructions are used). -//! -//! \return None. -// -//***************************************************************************** -void -FPULazyStackingEnable(void) -{ - // - // Enable automatic and lazy state preservation for the floating-point - // unit. - // - HWREG(NVIC_FPCC) |= NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN; -} - -//***************************************************************************** -// -//! Disables the stacking of floating-point registers. -//! -//! This function disables the stacking of floating-point registers s0-s15 when -//! an interrupt is handled. When floating-point context stacking is disabled, -//! floating-point operations performed in an interrupt handler destroy the -//! floating-point context of the main thread of execution. -//! -//! \return None. -// -//***************************************************************************** -void -FPUStackingDisable(void) -{ - // - // Disable automatic and lazy state preservation for the floating-point - // unit. - // - HWREG(NVIC_FPCC) &= ~(NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN); -} - -//***************************************************************************** -// -//! Selects the format of half-precision floating-point values. -//! -//! \param ui32Mode is the format for half-precision floating-point value, -//! which is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE. -//! -//! This function selects between the IEEE half-precision floating-point -//! representation and the Cortex-M processor alternative representation. The -//! alternative representation has a larger range but does not have a way to -//! encode infinity (positive or negative) or NaN (quiet or signaling). The -//! default setting is the IEEE format. -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -void -FPUHalfPrecisionModeSet(uint32_t ui32Mode) -{ - // - // Set the half-precision floating-point format. - // - HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_AHP)) | ui32Mode; -} - -//***************************************************************************** -// -//! Selects the NaN mode. -//! -//! \param ui32Mode is the mode for NaN results; which is either -//! \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT. -//! -//! This function selects the handling of NaN results during floating-point -//! computations. NaNs can either propagate (the default), or they can return -//! the default NaN. -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -void -FPUNaNModeSet(uint32_t ui32Mode) -{ - // - // Set the NaN mode. - // - HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_DN)) | ui32Mode; -} - -//***************************************************************************** -// -//! Selects the flush-to-zero mode. -//! -//! \param ui32Mode is the flush-to-zero mode; which is either -//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN. -//! -//! This function enables or disables the flush-to-zero mode of the -//! floating-point unit. When disabled (the default), the floating-point unit -//! is fully IEEE compliant. When enabled, values close to zero are treated as -//! zero, greatly improving the execution speed at the expense of some accuracy -//! (as well as IEEE compliance). -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -void -FPUFlushToZeroModeSet(uint32_t ui32Mode) -{ - // - // Set the flush-to-zero mode. - // - HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_FZ)) | ui32Mode; -} - -//***************************************************************************** -// -//! Selects the rounding mode for floating-point results. -//! -//! \param ui32Mode is the rounding mode. -//! -//! This function selects the rounding mode for floating-point results. After -//! a floating-point operation, the result is rounded toward the specified -//! value. The default mode is \b FPU_ROUND_NEAREST. -//! -//! The following rounding modes are available (as specified by \e ui32Mode): -//! -//! - \b FPU_ROUND_NEAREST - round toward the nearest value -//! - \b FPU_ROUND_POS_INF - round toward positive infinity -//! - \b FPU_ROUND_NEG_INF - round toward negative infinity -//! - \b FPU_ROUND_ZERO - round toward zero -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -void -FPURoundingModeSet(uint32_t ui32Mode) -{ - // - // Set the rounding mode. - // - HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_RMODE_M)) | ui32Mode; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/fpu.h b/bsp/tm4c129x-dk/libraries/driverlib/fpu.h deleted file mode 100644 index c96d69a7346c4a42762498f7a40cbdba60313f18..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/fpu.h +++ /dev/null @@ -1,113 +0,0 @@ -//***************************************************************************** -// -// fpu.h - Prototypes for the floatint point manipulation routines. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_FPU_H__ -#define __DRIVERLIB_FPU_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FPUHalfPrecisionSet as the ui32Mode parameter. -// -//***************************************************************************** -#define FPU_HALF_IEEE 0x00000000 -#define FPU_HALF_ALTERNATE 0x04000000 - -//***************************************************************************** -// -// Values that can be passed to FPUNaNModeSet as the ui32Mode parameter. -// -//***************************************************************************** -#define FPU_NAN_PROPAGATE 0x00000000 -#define FPU_NAN_DEFAULT 0x02000000 - -//***************************************************************************** -// -// Values that can be passed to FPUFlushToZeroModeSet as the ui32Mode -// parameter. -// -//***************************************************************************** -#define FPU_FLUSH_TO_ZERO_DIS 0x00000000 -#define FPU_FLUSH_TO_ZERO_EN 0x01000000 - -//***************************************************************************** -// -// Values that can be passed to FPURoundingModeSet as the ui32Mode parameter. -// -//***************************************************************************** -#define FPU_ROUND_NEAREST 0x00000000 -#define FPU_ROUND_POS_INF 0x00400000 -#define FPU_ROUND_NEG_INF 0x00800000 -#define FPU_ROUND_ZERO 0x00c00000 - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void FPUEnable(void); -extern void FPUDisable(void); -extern void FPUStackingEnable(void); -extern void FPULazyStackingEnable(void); -extern void FPUStackingDisable(void); -extern void FPUHalfPrecisionModeSet(uint32_t ui32Mode); -extern void FPUNaNModeSet(uint32_t ui32Mode); -extern void FPUFlushToZeroModeSet(uint32_t ui32Mode); -extern void FPURoundingModeSet(uint32_t ui32Mode); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_FPU_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/gpio.c b/bsp/tm4c129x-dk/libraries/driverlib/gpio.c deleted file mode 100644 index 5e55dd7f1c38a1a0732cf4b986d2adf133bb72a7..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/gpio.c +++ /dev/null @@ -1,2622 +0,0 @@ -//***************************************************************************** -// -// gpio.c - API for GPIO ports -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup gpio_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_gpio.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/gpio.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -// A mapping of GPIO port address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32GPIOIntMapBlizzard[][2] = -{ - { GPIO_PORTA_BASE, INT_GPIOA_TM4C123 }, - { GPIO_PORTA_AHB_BASE, INT_GPIOA_TM4C123 }, - { GPIO_PORTB_BASE, INT_GPIOB_TM4C123 }, - { GPIO_PORTB_AHB_BASE, INT_GPIOB_TM4C123 }, - { GPIO_PORTC_BASE, INT_GPIOC_TM4C123 }, - { GPIO_PORTC_AHB_BASE, INT_GPIOC_TM4C123 }, - { GPIO_PORTD_BASE, INT_GPIOD_TM4C123 }, - { GPIO_PORTD_AHB_BASE, INT_GPIOD_TM4C123 }, - { GPIO_PORTE_BASE, INT_GPIOE_TM4C123 }, - { GPIO_PORTE_AHB_BASE, INT_GPIOE_TM4C123 }, - { GPIO_PORTF_BASE, INT_GPIOF_TM4C123 }, - { GPIO_PORTF_AHB_BASE, INT_GPIOF_TM4C123 }, - { GPIO_PORTG_BASE, INT_GPIOG_TM4C123 }, - { GPIO_PORTG_AHB_BASE, INT_GPIOG_TM4C123 }, - { GPIO_PORTH_BASE, INT_GPIOH_TM4C123 }, - { GPIO_PORTH_AHB_BASE, INT_GPIOH_TM4C123 }, - { GPIO_PORTJ_BASE, INT_GPIOJ_TM4C123 }, - { GPIO_PORTJ_AHB_BASE, INT_GPIOJ_TM4C123 }, - { GPIO_PORTK_BASE, INT_GPIOK_TM4C123 }, - { GPIO_PORTL_BASE, INT_GPIOL_TM4C123 }, - { GPIO_PORTM_BASE, INT_GPIOM_TM4C123 }, - { GPIO_PORTN_BASE, INT_GPION_TM4C123 }, - { GPIO_PORTP_BASE, INT_GPIOP0_TM4C123 }, - { GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C123 }, -}; -static const uint_fast32_t g_ui32GPIOIntMapBlizzardRows = - sizeof(g_ppui32GPIOIntMapBlizzard) / sizeof(g_ppui32GPIOIntMapBlizzard[0]); - -static const uint32_t g_ppui32GPIOIntMapSnowflake[][2] = -{ - { GPIO_PORTA_BASE, INT_GPIOA_TM4C129 }, - { GPIO_PORTA_AHB_BASE, INT_GPIOA_TM4C129 }, - { GPIO_PORTB_BASE, INT_GPIOB_TM4C129 }, - { GPIO_PORTB_AHB_BASE, INT_GPIOB_TM4C129 }, - { GPIO_PORTC_BASE, INT_GPIOC_TM4C129 }, - { GPIO_PORTC_AHB_BASE, INT_GPIOC_TM4C129 }, - { GPIO_PORTD_BASE, INT_GPIOD_TM4C129 }, - { GPIO_PORTD_AHB_BASE, INT_GPIOD_TM4C129 }, - { GPIO_PORTE_BASE, INT_GPIOE_TM4C129 }, - { GPIO_PORTE_AHB_BASE, INT_GPIOE_TM4C129 }, - { GPIO_PORTF_BASE, INT_GPIOF_TM4C129 }, - { GPIO_PORTF_AHB_BASE, INT_GPIOF_TM4C129 }, - { GPIO_PORTG_BASE, INT_GPIOG_TM4C129 }, - { GPIO_PORTG_AHB_BASE, INT_GPIOG_TM4C129 }, - { GPIO_PORTH_BASE, INT_GPIOH_TM4C129 }, - { GPIO_PORTH_AHB_BASE, INT_GPIOH_TM4C129 }, - { GPIO_PORTJ_BASE, INT_GPIOJ_TM4C129 }, - { GPIO_PORTJ_AHB_BASE, INT_GPIOJ_TM4C129 }, - { GPIO_PORTK_BASE, INT_GPIOK_TM4C129 }, - { GPIO_PORTL_BASE, INT_GPIOL_TM4C129 }, - { GPIO_PORTM_BASE, INT_GPIOM_TM4C129 }, - { GPIO_PORTN_BASE, INT_GPION_TM4C129 }, - { GPIO_PORTP_BASE, INT_GPIOP0_TM4C129 }, - { GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C129 }, - { GPIO_PORTR_BASE, INT_GPIOR_TM4C129 }, - { GPIO_PORTS_BASE, INT_GPIOS_TM4C129 }, - { GPIO_PORTT_BASE, INT_GPIOT_TM4C129 }, -}; -static const uint_fast32_t g_ui32GPIOIntMapSnowflakeRows = - (sizeof(g_ppui32GPIOIntMapSnowflake) / - sizeof(g_ppui32GPIOIntMapSnowflake[0])); - -//***************************************************************************** -// -// The base addresses of all the GPIO modules. Both the APB and AHB apertures -// are provided. -// -//***************************************************************************** -static const uint32_t g_pui32GPIOBaseAddrs[] = -{ - GPIO_PORTA_BASE, GPIO_PORTA_AHB_BASE, - GPIO_PORTB_BASE, GPIO_PORTB_AHB_BASE, - GPIO_PORTC_BASE, GPIO_PORTC_AHB_BASE, - GPIO_PORTD_BASE, GPIO_PORTD_AHB_BASE, - GPIO_PORTE_BASE, GPIO_PORTE_AHB_BASE, - GPIO_PORTF_BASE, GPIO_PORTF_AHB_BASE, - GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE, - GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE, - GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE, - GPIO_PORTK_BASE, GPIO_PORTK_BASE, - GPIO_PORTL_BASE, GPIO_PORTL_BASE, - GPIO_PORTM_BASE, GPIO_PORTM_BASE, - GPIO_PORTN_BASE, GPIO_PORTN_BASE, - GPIO_PORTP_BASE, GPIO_PORTP_BASE, - GPIO_PORTQ_BASE, GPIO_PORTQ_BASE, - GPIO_PORTR_BASE, GPIO_PORTR_BASE, - GPIO_PORTS_BASE, GPIO_PORTS_BASE, - GPIO_PORTT_BASE, GPIO_PORTT_BASE, -}; - -//***************************************************************************** -// -//! \internal -//! Checks a GPIO base address. -//! -//! \param ui32Port is the base address of the GPIO port. -//! -//! This function determines if a GPIO port base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_GPIOBaseValid(uint32_t ui32Port) -{ - return((ui32Port == GPIO_PORTA_BASE) || - (ui32Port == GPIO_PORTA_AHB_BASE) || - (ui32Port == GPIO_PORTB_BASE) || - (ui32Port == GPIO_PORTB_AHB_BASE) || - (ui32Port == GPIO_PORTC_BASE) || - (ui32Port == GPIO_PORTC_AHB_BASE) || - (ui32Port == GPIO_PORTD_BASE) || - (ui32Port == GPIO_PORTD_AHB_BASE) || - (ui32Port == GPIO_PORTE_BASE) || - (ui32Port == GPIO_PORTE_AHB_BASE) || - (ui32Port == GPIO_PORTF_BASE) || - (ui32Port == GPIO_PORTF_AHB_BASE) || - (ui32Port == GPIO_PORTG_BASE) || - (ui32Port == GPIO_PORTG_AHB_BASE) || - (ui32Port == GPIO_PORTH_BASE) || - (ui32Port == GPIO_PORTH_AHB_BASE) || - (ui32Port == GPIO_PORTJ_BASE) || - (ui32Port == GPIO_PORTJ_AHB_BASE) || - (ui32Port == GPIO_PORTK_BASE) || - (ui32Port == GPIO_PORTL_BASE) || - (ui32Port == GPIO_PORTM_BASE) || - (ui32Port == GPIO_PORTN_BASE) || - (ui32Port == GPIO_PORTP_BASE) || - (ui32Port == GPIO_PORTQ_BASE) || - (ui32Port == GPIO_PORTR_BASE) || - (ui32Port == GPIO_PORTS_BASE) || - (ui32Port == GPIO_PORTT_BASE)); -} -#endif - -//***************************************************************************** -// -//! Gets the GPIO interrupt number. -//! -//! \param ui32Port is the base address of the GPIO port. -//! -//! Given a GPIO base address, this function returns the corresponding -//! interrupt number. -//! -//! \return Returns a GPIO interrupt number, or 0 if \e ui32Port is invalid. -// -//***************************************************************************** -static uint32_t -_GPIOIntNumberGet(uint32_t ui32Port) -{ - uint_fast32_t ui32Idx, ui32Rows; - const uint32_t (*ppui32GPIOIntMap)[2]; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - ppui32GPIOIntMap = g_ppui32GPIOIntMapBlizzard; - ui32Rows = g_ui32GPIOIntMapBlizzardRows; - - if(CLASS_IS_TM4C129) - { - ppui32GPIOIntMap = g_ppui32GPIOIntMapSnowflake; - ui32Rows = g_ui32GPIOIntMapSnowflakeRows; - } - - // - // Loop through the table that maps I2C base addresses to interrupt - // numbers. - // - for(ui32Idx = 0; ui32Idx < ui32Rows; ui32Idx++) - { - // - // See if this base address matches. - // - if(ppui32GPIOIntMap[ui32Idx][0] == ui32Port) - { - // - // Return the corresponding interrupt number. - // - return(ppui32GPIOIntMap[ui32Idx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Sets the direction and mode of the specified pin(s). -//! -//! \param ui32Port is the base address of the GPIO port -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! \param ui32PinIO is the pin direction and/or mode. -//! -//! This function configures the specified pin(s) on the selected GPIO port -//! as either input or output under software control, or it configures the -//! pin to be under hardware control. -//! -//! The parameter \e ui32PinIO is an enumerated data type that can be one of -//! the following values: -//! -//! - \b GPIO_DIR_MODE_IN -//! - \b GPIO_DIR_MODE_OUT -//! - \b GPIO_DIR_MODE_HW -//! -//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as a -//! software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin is -//! programmed as a software controlled output, and \b GPIO_DIR_MODE_HW -//! specifies that the pin is placed under hardware control. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note GPIOPadConfigSet() must also be used to configure the corresponding -//! pad(s) in order for them to propagate the signal to/from the GPIO. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, uint32_t ui32PinIO) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT((ui32PinIO == GPIO_DIR_MODE_IN) || - (ui32PinIO == GPIO_DIR_MODE_OUT) || - (ui32PinIO == GPIO_DIR_MODE_HW)); - - // - // Set the pin direction and mode. - // - HWREG(ui32Port + GPIO_O_DIR) = ((ui32PinIO & 1) ? - (HWREG(ui32Port + GPIO_O_DIR) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_DIR) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_AFSEL) = ((ui32PinIO & 2) ? - (HWREG(ui32Port + GPIO_O_AFSEL) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_AFSEL) & - ~(ui8Pins))); -} - -//***************************************************************************** -// -//! Gets the direction and mode of a pin. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pin is the pin number. -//! -//! This function gets the direction and control mode for a specified pin on -//! the selected GPIO port. The pin can be configured as either an input or -//! output under software control, or it can be under hardware control. The -//! type of control and direction are returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIODirModeSet(). -// -//***************************************************************************** -uint32_t -GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin) -{ - uint32_t ui32Dir, ui32AFSEL; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT(ui8Pin < 8); - - // - // Convert from a pin number to a bit position. - // - ui8Pin = 1 << ui8Pin; - - // - // Return the pin direction and mode. - // - ui32Dir = HWREG(ui32Port + GPIO_O_DIR); - ui32AFSEL = HWREG(ui32Port + GPIO_O_AFSEL); - return(((ui32Dir & ui8Pin) ? 1 : 0) | ((ui32AFSEL & ui8Pin) ? 2 : 0)); -} - -//***************************************************************************** -// -//! Sets the interrupt type for the specified pin(s). -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! \param ui32IntType specifies the type of interrupt trigger mechanism. -//! -//! This function sets up the various interrupt trigger mechanisms for the -//! specified pin(s) on the selected GPIO port. -//! -//! One of the following flags can be used to define the \e ui32IntType -//! parameter: -//! -//! - \b GPIO_FALLING_EDGE sets detection to edge and trigger to falling -//! - \b GPIO_RISING_EDGE sets detection to edge and trigger to rising -//! - \b GPIO_BOTH_EDGES sets detection to both edges -//! - \b GPIO_LOW_LEVEL sets detection to low level -//! - \b GPIO_HIGH_LEVEL sets detection to high level -//! -//! In addition to the above flags, the following flag can be OR'd in to the -//! \e ui32IntType parameter: -//! -//! - \b GPIO_DISCRETE_INT sets discrete interrupts for each pin on a GPIO -//! port. -//! -//! The \b GPIO_DISCRETE_INT is not available on all devices or all GPIO ports, -//! consult the data sheet to ensure that the device and the GPIO port supports -//! discrete interrupts. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note In order to avoid any spurious interrupts, the user must ensure that -//! the GPIO inputs remain stable for the duration of this function. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, - uint32_t ui32IntType) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT(((ui32IntType & 0xF) == GPIO_FALLING_EDGE) || - ((ui32IntType & 0xF) == GPIO_RISING_EDGE) || - ((ui32IntType & 0xF) == GPIO_BOTH_EDGES) || - ((ui32IntType & 0xF) == GPIO_LOW_LEVEL) || - ((ui32IntType & 0xF) == GPIO_HIGH_LEVEL)); - ASSERT(((ui32IntType & 0x000F0000) == 0) || - (((ui32IntType & 0x000F0000) == GPIO_DISCRETE_INT) && - ((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)))); - - // - // Set the pin interrupt type. - // - HWREG(ui32Port + GPIO_O_IBE) = ((ui32IntType & 1) ? - (HWREG(ui32Port + GPIO_O_IBE) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_IBE) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_IS) = ((ui32IntType & 2) ? - (HWREG(ui32Port + GPIO_O_IS) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_IS) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_IEV) = ((ui32IntType & 4) ? - (HWREG(ui32Port + GPIO_O_IEV) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_IEV) & ~(ui8Pins))); - - // - // Set or clear the discrete interrupt feature. This is not available - // on all parts or ports but is safe to write in all cases. - // - HWREG(ui32Port + GPIO_O_SI) = ((ui32IntType & 0x10000) ? - (HWREG(ui32Port + GPIO_O_SI) | 0x01) : - (HWREG(ui32Port + GPIO_O_SI) & ~(0x01))); -} - -//***************************************************************************** -// -//! Gets the interrupt type for a pin. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pin is the pin number. -//! -//! This function gets the interrupt type for a specified pin on the selected -//! GPIO port. The pin can be configured as a falling-edge, rising-edge, or -//! both-edges detected interrupt, or it can be configured as a low-level or -//! high-level detected interrupt. The type of interrupt detection mechanism -//! is returned and can include the \b GPIO_DISCRETE_INT flag. -//! -//! \return Returns one of the flags described for GPIOIntTypeSet(). -// -//***************************************************************************** -uint32_t -GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin) -{ - uint32_t ui32IBE, ui32IS, ui32IEV, ui32SI; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT(ui8Pin < 8); - - // - // Convert from a pin number to a bit position. - // - ui8Pin = 1 << ui8Pin; - - // - // Return the pin interrupt type. - // - ui32IBE = HWREG(ui32Port + GPIO_O_IBE); - ui32IS = HWREG(ui32Port + GPIO_O_IS); - ui32IEV = HWREG(ui32Port + GPIO_O_IEV); - ui32SI = HWREG(ui32Port + GPIO_O_SI); - return(((ui32IBE & ui8Pin) ? 1 : 0) | ((ui32IS & ui8Pin) ? 2 : 0) | - ((ui32IEV & ui8Pin) ? 4 : 0) | (ui32SI & 0x01) ? 0x10000 : 0); -} - -//***************************************************************************** -// -//! Sets the pad configuration for the specified pin(s). -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! \param ui32Strength specifies the output drive strength. -//! \param ui32PinType specifies the pin type. -//! -//! This function sets the drive strength and type for the specified pin(s) -//! on the selected GPIO port. For pin(s) configured as input ports, the -//! pad is configured as requested, but the only real effect on the input -//! is the configuration of the pull-up or pull-down termination. -//! -//! The parameter \e ui32Strength can be one of the following values: -//! -//! - \b GPIO_STRENGTH_2MA -//! - \b GPIO_STRENGTH_4MA -//! - \b GPIO_STRENGTH_8MA -//! - \b GPIO_STRENGTH_8MA_SC -//! - \b GPIO_STRENGTH_6MA -//! - \b GPIO_STRENGTH_10MA -//! - \b GPIO_STRENGTH_12MA -//! -//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive -//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with -//! slew control. -//! -//! Some Tiva devices also support output drive strengths of 6, 10, and 12 -//! mA. -//! -//! The parameter \e ui32PinType can be one of the following values: -//! -//! - \b GPIO_PIN_TYPE_STD -//! - \b GPIO_PIN_TYPE_STD_WPU -//! - \b GPIO_PIN_TYPE_STD_WPD -//! - \b GPIO_PIN_TYPE_OD -//! - \b GPIO_PIN_TYPE_ANALOG -//! - \b GPIO_PIN_TYPE_WAKE_HIGH -//! - \b GPIO_PIN_TYPE_WAKE_LOW -//! -//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* -//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD -//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an analog -//! input. -//! -//! The \b GPIO_PIN_TYPE_WAKE_* settings specify the pin to be used as a -//! hibernation wake source. The pin sense level can be high or low. These -//! settings are only available on some Tiva devices. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, - uint32_t ui32Strength, uint32_t ui32PinType) -{ - uint8_t ui8Bit; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT((ui32Strength == GPIO_STRENGTH_2MA) || - (ui32Strength == GPIO_STRENGTH_4MA) || - (ui32Strength == GPIO_STRENGTH_6MA) || - (ui32Strength == GPIO_STRENGTH_8MA) || - (ui32Strength == GPIO_STRENGTH_8MA_SC) || - (ui32Strength == GPIO_STRENGTH_10MA) || - (ui32Strength == GPIO_STRENGTH_12MA)); - ASSERT((ui32PinType == GPIO_PIN_TYPE_STD) || - (ui32PinType == GPIO_PIN_TYPE_STD_WPU) || - (ui32PinType == GPIO_PIN_TYPE_STD_WPD) || - (ui32PinType == GPIO_PIN_TYPE_OD) || - (ui32PinType == GPIO_PIN_TYPE_WAKE_LOW) || - (ui32PinType == GPIO_PIN_TYPE_WAKE_HIGH) || - (ui32PinType == GPIO_PIN_TYPE_ANALOG)); - - - // - // Set the GPIO peripheral configuration register first as required. This - // register only appears in TM4E111 and later device classes, but is a - // harmless write on older devices. Walk pins 0-7 and clear or set the - // provided PC[EDMn] encoding. - // - for(ui8Bit = 0; ui8Bit < 8; ui8Bit++) - { - if(ui8Pins & (1 << ui8Bit)) - { - HWREG(ui32Port + GPIO_O_PC) = (HWREG(ui32Port + GPIO_O_PC) & - ~(0x3 << (2 * ui8Bit))); - HWREG(ui32Port + GPIO_O_PC) |= (((ui32Strength >> 5) & 0x3) << - (2 * ui8Bit)); - } - } - - // - // Set the output drive strength. - // - HWREG(ui32Port + GPIO_O_DR2R) = ((ui32Strength & 1) ? - (HWREG(ui32Port + GPIO_O_DR2R) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_DR2R) & - ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_DR4R) = ((ui32Strength & 2) ? - (HWREG(ui32Port + GPIO_O_DR4R) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_DR4R) & - ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_DR8R) = ((ui32Strength & 4) ? - (HWREG(ui32Port + GPIO_O_DR8R) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_DR8R) & - ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_SLR) = ((ui32Strength & 8) ? - (HWREG(ui32Port + GPIO_O_SLR) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_SLR) & - ~(ui8Pins))); - - // - // Set the 12-mA drive select register. This register only appears in - // TM4E111 and later device classes, but is a harmless write on older - // devices. - // - HWREG(ui32Port + GPIO_O_DR12R) = ((ui32Strength & 0x10) ? - (HWREG(ui32Port + GPIO_O_DR12R) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_DR12R) & - ~(ui8Pins))); - - // - // Set the pin type. - // - HWREG(ui32Port + GPIO_O_ODR) = ((ui32PinType & 1) ? - (HWREG(ui32Port + GPIO_O_ODR) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_ODR) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_PUR) = ((ui32PinType & 2) ? - (HWREG(ui32Port + GPIO_O_PUR) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_PUR) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_PDR) = ((ui32PinType & 4) ? - (HWREG(ui32Port + GPIO_O_PDR) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_PDR) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_DEN) = ((ui32PinType & 8) ? - (HWREG(ui32Port + GPIO_O_DEN) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_DEN) & ~(ui8Pins))); - - // - // Set the wake pin enable register and the wake level register. These - // registers only appear in TM4E111 and later device classes, but are - // harmless writes on older devices. - // - HWREG(ui32Port + GPIO_O_WAKELVL) = ((ui32PinType & 0x200) ? - (HWREG(ui32Port + GPIO_O_WAKELVL) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_WAKELVL) & - ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_WAKEPEN) = ((ui32PinType & 0x300) ? - (HWREG(ui32Port + GPIO_O_WAKEPEN) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_WAKEPEN) & - ~(ui8Pins))); - - // - // Set the analog mode select register. - // - HWREG(ui32Port + GPIO_O_AMSEL) = - ((ui32PinType == GPIO_PIN_TYPE_ANALOG) ? - (HWREG(ui32Port + GPIO_O_AMSEL) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_AMSEL) & ~(ui8Pins))); -} - -//***************************************************************************** -// -//! Gets the pad configuration for a pin. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pin is the pin number. -//! \param pui32Strength is a pointer to storage for the output drive strength. -//! \param pui32PinType is a pointer to storage for the output drive type. -//! -//! This function gets the pad configuration for a specified pin on the -//! selected GPIO port. The values returned in \e pui32Strength and -//! \e pui32PinType correspond to the values used in GPIOPadConfigSet(). This -//! function also works for pin(s) configured as input pin(s); however, the -//! only meaningful data returned is whether the pin is terminated with a -//! pull-up or down resistor. -//! -//! \return None -// -//***************************************************************************** -void -GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, - uint32_t *pui32Strength, uint32_t *pui32PinType) -{ - uint32_t ui32PinType, ui32Strength; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT(ui8Pin < 8); - - // - // Convert from a pin number to a bit position. - // - ui8Pin = (1 << ui8Pin); - - // - // Get the drive strength for this pin. - // - ui32Strength = ((HWREG(ui32Port + GPIO_O_DR2R) & ui8Pin) ? 1 : 0); - ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR4R) & ui8Pin) ? 2 : 0); - ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR8R) & ui8Pin) ? 4 : 0); - ui32Strength |= ((HWREG(ui32Port + GPIO_O_SLR) & ui8Pin) ? 8 : 0); - ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR12R) & ui8Pin) ? 0x10 : 0); - ui32Strength |= (((HWREG(ui32Port + GPIO_O_PC) >> - (2 * ui8Pin)) & 0x3) << 5); - *pui32Strength = ui32Strength; - - // - // Get the pin type. - // - ui32PinType = ((HWREG(ui32Port + GPIO_O_ODR) & ui8Pin) ? 1 : 0); - ui32PinType |= ((HWREG(ui32Port + GPIO_O_PUR) & ui8Pin) ? 2 : 0); - ui32PinType |= ((HWREG(ui32Port + GPIO_O_PDR) & ui8Pin) ? 4 : 0); - ui32PinType |= ((HWREG(ui32Port + GPIO_O_DEN) & ui8Pin) ? 8 : 0); - if(HWREG(ui32Port + GPIO_O_WAKEPEN) & ui8Pin) - { - ui32PinType |= ((HWREG(ui32Port + GPIO_O_WAKELVL) & ui8Pin) ? - 0x200 : 0x100); - } - *pui32PinType = ui32PinType; -} - -//***************************************************************************** -// -//! Enables the specified GPIO interrupts. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to enable. -//! -//! This function enables the indicated GPIO interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. -//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. -//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. -//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. -//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. -//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. -//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. -//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. -//! - \b GPIO_INT_DMA - interrupt due to DMA activity on this GPIO module. -//! -//! \note If this call is being used to enable summary interrupts on GPIO port -//! P or Q (GPIOIntTypeSet() with GPIO_DISCRETE_INT not enabled), then all -//! individual interrupts for these ports must be enabled in the GPIO module -//! using GPIOIntEnable() and all but the interrupt for pin 0 must be disabled -//! in the NVIC using the IntDisable() function. The summary interrupts for -//! the ports are routed to the INT_GPIOP0 or INT_GPIOQ0 which must be enabled -//! to handle the interrupt. If this is not done then any individual GPIO pin -//! interrupts that are left enabled also trigger the individual interrupts. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Enable the interrupts. - // - HWREG(ui32Port + GPIO_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables the specified GPIO interrupts. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. -//! -//! This function disables the indicated GPIO interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. -//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. -//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. -//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. -//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. -//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. -//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. -//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. -//! - \b GPIO_INT_DMA - interrupt due to DMA activity on this GPIO module. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Disable the interrupts. - // - HWREG(ui32Port + GPIO_O_IM) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets interrupt status for the specified GPIO port. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status is returned. -//! -//! \return Returns the current interrupt status for the specified GPIO module. -//! The value returned is the logical OR of the \b GPIO_INT_* values that are -//! currently active. -// -//***************************************************************************** -uint32_t -GPIOIntStatus(uint32_t ui32Port, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Return the interrupt status. - // - if(bMasked) - { - return(HWREG(ui32Port + GPIO_O_MIS)); - } - else - { - return(HWREG(ui32Port + GPIO_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the specified interrupt sources. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. -//! -//! Clears the interrupt for the specified interrupt source(s). -//! -//! The \e ui32IntFlags parameter is the logical OR of the \b GPIO_INT_* -//! values. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Clear the interrupts. - // - HWREG(ui32Port + GPIO_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a GPIO port. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling -//! function. -//! -//! This function ensures that the interrupt handler specified by -//! \e pfnIntHandler is called when an interrupt is detected from the selected -//! GPIO port. This function also enables the corresponding GPIO interrupt -//! in the interrupt controller; individual pin interrupts and interrupt -//! sources must be enabled with GPIOIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ui32Int = _GPIOIntNumberGet(ui32Port); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnIntHandler); - - // - // Enable the GPIO interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Removes an interrupt handler for a GPIO port. -//! -//! \param ui32Port is the base address of the GPIO port. -//! -//! This function unregisters the interrupt handler for the specified -//! GPIO port. This function also disables the corresponding -//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts -//! and interrupt sources must be disabled with GPIOIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntUnregister(uint32_t ui32Port) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ui32Int = _GPIOIntNumberGet(ui32Port); - - ASSERT(ui32Int != 0); - - // - // Disable the GPIO interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for an individual pin of a GPIO port. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui32Pin is the pin whose interrupt is to be registered. -//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling -//! function. -//! -//! This function ensures that the interrupt handler specified by -//! \e pfnIntHandler is called when an interrupt is detected from the selected -//! pin of a GPIO port. This function also enables the corresponding GPIO pin -//! interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin, - void (*pfnIntHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)); - ASSERT((ui32Pin > 0) && (ui32Pin < 8)); - ASSERT(pfnIntHandler != 0); - - // - // Get the interrupt number associated with the specified GPIO. - // - ui32Int = _GPIOIntNumberGet(ui32Port); - - // - // Register the interrupt handler. - // - IntRegister((ui32Int + ui32Pin), pfnIntHandler); - - // - // Enable the GPIO pin interrupt. - // - IntEnable(ui32Int + ui32Pin); -} - -//***************************************************************************** -// -//! Removes an interrupt handler for an individual pin of a GPIO port. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui32Pin is the pin whose interrupt is to be unregistered. -//! -//! This function unregisters the interrupt handler for the specified pin of a -//! GPIO port. This function also disables the corresponding GPIO pin -//! interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)); - ASSERT((ui32Pin > 0) && (ui32Pin < 8)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ui32Int = _GPIOIntNumberGet(ui32Port); - - // - // Disable the GPIO pin interrupt. - // - IntDisable(ui32Int + ui32Pin); - - // - // UnRegister the interrupt handler. - // - IntUnregister(ui32Int + ui32Pin); -} - -//***************************************************************************** -// -//! Reads the values present of the specified pin(s). -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The values at the specified pin(s) are read, as specified by \e ui8Pins. -//! Values are returned for both input and output pin(s), and the value -//! for pin(s) that are not specified by \e ui8Pins are set to 0. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return Returns a bit-packed byte providing the state of the specified -//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents -//! GPIO port pin 1, and so on. Any bit that is not specified by \e ui8Pins -//! is returned as a 0. Bits 31:8 should be ignored. -// -//***************************************************************************** -int32_t -GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Return the pin value(s). - // - return(HWREG(ui32Port + (GPIO_O_DATA + (ui8Pins << 2)))); -} - -//***************************************************************************** -// -//! Writes a value to the specified pin(s). -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! \param ui8Val is the value to write to the pin(s). -//! -//! Writes the corresponding bit values to the output pin(s) specified by -//! \e ui8Pins. Writing to a pin configured as an input pin has no effect. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Write the pins. - // - HWREG(ui32Port + (GPIO_O_DATA + (ui8Pins << 2))) = ui8Val; -} - -//***************************************************************************** -// -//! Configures pin(s) for use as analog-to-digital converter inputs. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The analog-to-digital converter input pins must be properly configured for -//! the analog-to-digital peripheral to function correctly. This function -//! provides the proper configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an ADC input; it -//! only configures an ADC input pin for proper operation. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for analog operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_ANALOG); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as a CAN device. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The CAN pins must be properly configured for the CAN peripherals to -//! function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a CAN pin; it only -//! configures a CAN pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the CAN -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as an analog comparator input. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The analog comparator input pins must be properly configured for the analog -//! comparator to function correctly. This function provides the proper -//! configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an analog -//! comparator input; it only configures an analog comparator pin for proper -//! operation. Note that a GPIOPinConfigure() function call is also required -//! to properly configure a pin for the analog comparator function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for analog operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_ANALOG); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as an analog comparator output. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The analog comparator output pins must be properly configured for the analog -//! comparator to function correctly. This function provides the proper -//! configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return None. -// -//***************************************************************************** -void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as an clock to be output from the device. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The system control output pin must be properly configured for the DIVSCLK to -//! function correctly. This function provides the proper configuration for -//! those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return None. -// -//***************************************************************************** -void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the external peripheral interface. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The external peripheral interface pins must be properly configured for the -//! external peripheral interface to function correctly. This function -//! provides a typical configuration for those pin(s); other configurations may -//! work as well depending upon the board setup (for example, using the on-chip -//! pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an external -//! peripheral interface pin; it only configures an external peripheral -//! interface pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the -//! external peripheral interface function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the Ethernet peripheral as LED signals. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The Ethernet peripheral provides four signals that can be used to drive -//! an LED (for example, for link status/activity). This function provides a -//! typical configuration for the pins. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an Ethernet LED -//! pin; it only configures an Ethernet LED pin for proper operation. Note -//! that a GPIOPinConfigure() function call is also required to properly -//! configure the pin for the Ethernet LED function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the Ethernet peripheral as MII signals. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The Ethernet peripheral on some parts provides a set of MII signals that -//! are used to connect to an external PHY. This function provides a typical -//! configuration for the pins. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an Ethernet MII -//! pin; it only configures an Ethernet MII pin for proper operation. Note -//! that a GPIOPinConfigure() function call is also required to properly -//! configure the pin for the Ethernet MII function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as GPIO inputs. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! GPIO inputs. This function provides the proper configuration for those -//! pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as GPIO outputs. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! GPIO outputs. This function provides the proper configuration for those -//! pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); - - // - // Make the pin(s) be outputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as GPIO open drain outputs. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! GPIO outputs. This function provides the proper configuration for those -//! pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); - - // - // Make the pin(s) be outputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as an Hibernate RTC Clock. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The hibernate output pin must be properly configured for the RTCCLK to -//! function correctly. This function provides the proper configuration for the -//! RTC Clock to be output from the device. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return None. -// -//***************************************************************************** -void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin for use as SDA by the I2C peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin. -//! -//! The I2C pins must be properly configured for the I2C peripheral to function -//! correctly. This function provides the proper configuration for the SDA -//! pin. -//! -//! The pin is specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an I2C SDA pin; it -//! only configures an I2C SDA pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the I2C SDA function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for open-drain operation with a weak pull-up. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); -} - -//***************************************************************************** -// -//! Configures pin for use as SCL by the I2C peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin. -//! -//! The I2C pins must be properly configured for the I2C peripheral to function -//! correctly. This function provides the proper configuration for the SCL -//! pin. -//! -//! The pin is specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an I2C SCL pin; it -//! only configures an I2C SCL pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the I2C SCL function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the LCD Controller. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The LCD controller pins must be properly configured for the LCD controller -//! to function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an LCD pin; it only -//! configures an LCD pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the LCD -//! controller function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation and beefed up drive. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the 1-Wire module. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The 1-Wire pin must be properly configured for the 1-Wire peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a 1-Wire pin; it -//! only configures a 1-Wire pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the 1-Wire function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the PWM peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The PWM pins must be properly configured for the PWM peripheral to function -//! correctly. This function provides a typical configuration for those -//! pin(s); other configurations may work as well depending upon the board -//! setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a PWM pin; it only -//! configures a PWM pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the PWM -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the QEI peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The QEI pins must be properly configured for the QEI peripheral to function -//! correctly. This function provides a typical configuration for those -//! pin(s); other configurations may work as well depending upon the board -//! setup (for example, not using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a QEI pin; it only -//! configures a QEI pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the QEI -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation with a weak pull-up. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_STD_WPU); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the SSI peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The SSI pins must be properly configured for the SSI peripheral to function -//! correctly. This function provides a typical configuration for those -//! pin(s); other configurations may work as well depending upon the board -//! setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a SSI pin; it only -//! configures a SSI pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the SSI -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the Timer peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The CCP pins must be properly configured for the timer peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a timer pin; it -//! only configures a timer pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the CCP function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the Trace peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The Trace pins must be properly configured for the Trace peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a trace pin; it -//! only configures a trace pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the Trace function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the UART peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The UART pins must be properly configured for the UART peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a UART pin; it -//! only configures a UART pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the UART function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the USB peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! USB analog pins must be properly configured for the USB peripheral to -//! function correctly. This function provides the proper configuration for -//! any USB analog pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a USB pin; it only -//! configures a USB pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the USB -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for analog operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_ANALOG); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the USB peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! USB digital pins must be properly configured for the USB peripheral to -//! function correctly. This function provides a typical configuration for -//! the digital USB pin(s); other configurations may work as well depending -//! upon the board setup (for example, using the on-chip pull-ups). -//! -//! This function should only be used with EPEN and PFAULT pins as all other -//! USB pins are analog in nature or are not used in devices without OTG -//! functionality. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a USB pin; it only -//! configures a USB pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the USB -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as a hibernate wake-on-high source. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! hibernate wake-high inputs. This function provides the proper -//! configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for wake-high operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_WAKE_HIGH); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as a hibernate wake-on-low source. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! hibernate wake-low inputs. This function provides the proper -//! configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for wake-high operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_WAKE_LOW); -} - -//***************************************************************************** -// -//! Retrieves the wake pins status. -//! -//! \param ui32Port is the base address of the GPIO port. -//! -//! This function returns the GPIO wake pin status values. The returned -//! bitfield shows low or high pin state via a value of 0 or 1. -//! -//! \note This function is not available on all devices, consult the data sheet -//! to ensure that the device you are using supports GPIO wake pins. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return Returns the wake pin status. -// -//***************************************************************************** -uint32_t -GPIOPinWakeStatus(uint32_t ui32Port) -{ - return(HWREG(ui32Port + GPIO_O_WAKESTAT)); -} - -//***************************************************************************** -// -//! Configures the alternate function of a GPIO pin. -//! -//! \param ui32PinConfig is the pin configuration value, specified as only one -//! of the \b GPIO_P??_??? values. -//! -//! This function configures the pin mux that selects the peripheral function -//! associated with a particular GPIO pin. Only one peripheral function at a -//! time can be associated with a GPIO pin, and each peripheral function should -//! only be associated with a single GPIO pin at a time (despite the fact that -//! many of them can be associated with more than one GPIO pin). To fully -//! configure a pin, a GPIOPinType*() function should also be called. -//! -//! The available mappings are supplied on a per-device basis in -//! pin_map.h. The \b PART_ defines controls which set of -//! defines are included so that they match the device that is being used. -//! For example, \b PART_TM4C129XNCZAD must be defined in order to get the -//! correct pin mappings for the TM4C129XNCZAD device. -//! -//! \note If the same signal is assigned to two different GPIO port -//! pins, the signal is assigned to the port with the lowest letter and the -//! assignment to the higher letter port is ignored. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinConfigure(uint32_t ui32PinConfig) -{ - uint32_t ui32Base, ui32Shift; - - // - // Check the argument. - // - ASSERT(((ui32PinConfig >> 16) & 0xff) < 18); - ASSERT(((ui32PinConfig >> 8) & 0xe3) == 0); - - // - // Extract the base address index from the input value. - // - ui32Base = (ui32PinConfig >> 16) & 0xff; - - // - // Get the base address of the GPIO module, selecting either the APB or the - // AHB aperture as appropriate. - // - if(HWREG(SYSCTL_GPIOHBCTL) & (1 << ui32Base)) - { - ui32Base = g_pui32GPIOBaseAddrs[(ui32Base << 1) + 1]; - } - else - { - ui32Base = g_pui32GPIOBaseAddrs[ui32Base << 1]; - } - - // - // Extract the shift from the input value. - // - ui32Shift = (ui32PinConfig >> 8) & 0xff; - - // - // Write the requested pin muxing value for this GPIO pin. - // - HWREG(ui32Base + GPIO_O_PCTL) = ((HWREG(ui32Base + GPIO_O_PCTL) & - ~(0xf << ui32Shift)) | - ((ui32PinConfig & 0xf) << ui32Shift)); -} - -//***************************************************************************** -// -//! Enables a GPIO pin as a trigger to start a DMA transaction. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! This function enables a GPIO pin to be used as a trigger to start a uDMA -//! transaction. Any GPIO pin can be configured to be an external trigger for -//! the uDMA. The GPIO pin still generates interrupts if the interrupt is -//! enabled for the selected pin. -//! -//! \return None. -// -//***************************************************************************** -void -GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pin as a DMA trigger. - // - HWREG(ui32Port + GPIO_O_DMACTL) |= ui8Pins; -} - -//***************************************************************************** -// -//! Disables a GPIO pin as a trigger to start a DMA transaction. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! This function disables a GPIO pin from being used as a trigger to start a -//! uDMA transaction. This function can be used to disable this feature if it -//! was enabled via a call to GPIODMATriggerEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pin as a DMA trigger. - // - HWREG(ui32Port + GPIO_O_DMACTL) &= (~ui8Pins); -} - -//***************************************************************************** -// -//! Enables a GPIO pin as a trigger to start an ADC capture. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! This function enables a GPIO pin to be used as a trigger to start an ADC -//! sequence. Any GPIO pin can be configured to be an external trigger for an -//! ADC sequence. The GPIO pin still generates interrupts if the interrupt is -//! enabled for the selected pin. To enable the use of a GPIO pin to trigger -//! the ADC module, the ADCSequenceConfigure() function must be called with the -//! \b ADC_TRIGGER_EXTERNAL parameter. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pin as a DMA trigger. - // - HWREG(ui32Port + GPIO_O_ADCCTL) |= ui8Pins; -} - -//***************************************************************************** -// -//! Disable a GPIO pin as a trigger to start an ADC capture. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! This function disables a GPIO pin to be used as a trigger to start an ADC -//! sequence. This function can be used to disable this feature if it was -//! enabled via a call to GPIOADCTriggerEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pin as a DMA trigger. - // - HWREG(ui32Port + GPIO_O_ADCCTL) &= (~ui8Pins); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/gpio.h b/bsp/tm4c129x-dk/libraries/driverlib/gpio.h deleted file mode 100644 index 47b0dd71b478835f794379db97eba341d911d68a..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/gpio.h +++ /dev/null @@ -1,204 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_GPIO_H__ -#define __DRIVERLIB_GPIO_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ui8Pins argument to -// several of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter, -// and returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level -#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter, -// and returned by GPIOPadConfigGet in the *pui32Strength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_6MA 0x00000065 // 6mA drive strength -#define GPIO_STRENGTH_8MA 0x00000066 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000006E // 8mA drive with slew rate control -#define GPIO_STRENGTH_10MA 0x00000075 // 10mA drive strength -#define GPIO_STRENGTH_12MA 0x00000077 // 12mA drive strength - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter, -// and returned by GPIOPadConfigGet in the *pui32PadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator -#define GPIO_PIN_TYPE_WAKE_HIGH 0x00000208 // Hibernate wake, high -#define GPIO_PIN_TYPE_WAKE_LOW 0x00000108 // Hibernate wake, low - -//***************************************************************************** -// -// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions -// in the ui32IntFlags parameter. -// -//***************************************************************************** -#define GPIO_INT_PIN_0 0x00000001 -#define GPIO_INT_PIN_1 0x00000002 -#define GPIO_INT_PIN_2 0x00000004 -#define GPIO_INT_PIN_3 0x00000008 -#define GPIO_INT_PIN_4 0x00000010 -#define GPIO_INT_PIN_5 0x00000020 -#define GPIO_INT_PIN_6 0x00000040 -#define GPIO_INT_PIN_7 0x00000080 -#define GPIO_INT_DMA 0x00000100 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, - uint32_t ui32PinIO); -extern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin); -extern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, - uint32_t ui32IntType); -extern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin); -extern void GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, - uint32_t ui32Strength, uint32_t ui32PadType); -extern void GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, - uint32_t *pui32Strength, uint32_t *pui32PadType); -extern void GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags); -extern void GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags); -extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked); -extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags); -extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void)); -extern void GPIOIntUnregister(uint32_t ui32Port); -extern void GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin, - void (*pfnIntHandler)(void)); -extern void GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin); -extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val); -extern void GPIOPinConfigure(uint32_t ui32PinConfig); -extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins); -extern uint32_t GPIOPinWakeStatus(uint32_t ui32Port); -extern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_GPIO_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/hibernate.c b/bsp/tm4c129x-dk/libraries/driverlib/hibernate.c deleted file mode 100644 index a3715783871f145029f7724f525a32d00e195ef9..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/hibernate.c +++ /dev/null @@ -1,2553 +0,0 @@ -//***************************************************************************** -// -// hibernate.c - Driver for the Hibernation module -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup hibernate_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include -#include "inc/hw_hibernate.h" -#include "inc/hw_ints.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/hibernate.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" - -//***************************************************************************** -// -// The delay in microseconds for writing to the Hibernation module registers. -// -//***************************************************************************** -#define DELAY_USECS 95 - -//***************************************************************************** -// -// The number of processor cycles to execute one pass of the delay loop. -// -//***************************************************************************** -#define LOOP_CYCLES 3 - -//***************************************************************************** -// -// A macro used to determine whether the target part supports Wake from IO -// pins. -// -//***************************************************************************** -#define HIBERNATE_WAKE_IO CLASS_IS_TM4C129 - -//***************************************************************************** -// -// A macro used to determine whether the target part supports Wake from IO -// pins. -// -//***************************************************************************** -#define HIBERNATE_CLOCK_OUTPUT CLASS_IS_TM4C129 - -//***************************************************************************** -// -//! \internal -//! -//! Polls until the write complete (WRC) bit in the hibernate control register -//! is set. -//! -//! \param None. -//! -//! The Hibernation module provides an indication when any write is completed. -//! This mechanism is used to pace writes to the module. This function merely -//! polls this bit and returns as soon as it is set. At this point, it is safe -//! to perform another write to the module. -//! -//! \return None. -// -//***************************************************************************** -static void -_HibernateWriteComplete(void) -{ - // - // Spin until the write complete bit is set. - // - while(!(HWREG(HIB_CTL) & HIB_CTL_WRC)) - { - } -} - -//***************************************************************************** -// -//! Enables the Hibernation module for operation. -//! -//! \param ui32HibClk is the rate of the clock supplied to the Hibernation -//! module. -//! -//! This function enables the Hibernation module for operation. This function -//! should be called before any of the Hibernation module features are used. -//! -//! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet() for TM4C123x -//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, -//! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the -//! variable call holding the return value of SysCtlClockFreqSet()). -//! -//! \return None. -// -//***************************************************************************** -void -HibernateEnableExpClk(uint32_t ui32HibClk) -{ - // - // Turn on the clock enable bit. - // - HWREG(HIB_CTL) |= HIB_CTL_CLK32EN; - - // - // Wait for write complete following register load (above). - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables the Hibernation module for operation. -//! -//! This function disables the Hibernation module. After this function is -//! called, none of the Hibernation module features are available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateDisable(void) -{ - // - // Turn off the clock enable bit. - // - HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Configures the clock input for the Hibernation module. -//! -//! \param ui32Config is one of the possible configuration options for the -//! clock input listed below. -//! -//! This function is used to configure the clock input for the Hibernation -//! module. The \e ui32Config parameter can be one of the following values: -//! -//! - \b HIBERNATE_OSC_DISABLE specifies that the internal oscillator -//! is powered off. This option is used when an externally supplied oscillator -//! is connected to the XOSC0 pin or to save power when the LFIOSC is used in -//! devices that have an LFIOSC in the Hibernation module. -//! - \b HIBERNATE_OSC_HIGHDRIVE specifies a higher drive strength when a 24-pF -//! filter capacitor is used with a crystal. -//! - \b HIBERNATE_OSC_LOWDRIVE specifies a lower drive strength when a 12-pF -//! filter capacitor is used with a crystal. -//! -//! On some devices, there is an option to use an internal low frequency -//! oscillator (LFIOSC) as the clock source for the Hibernation module. -//! Because of the low accuracy of this oscillator, this option should not be -//! used when the system requires a real time counter. Adding the -//! \b HIBERNATE_OSC_LFIOSC value enables the LFIOSC as the clock source to -//! the Hibernation module. -//! -//! - \b HIBERNATE_OSC_LFIOSC enables the Hibernation module's internal low -//! frequency oscillator as the clock to the Hibernation module. -//! -//! This \e ui32Config also configures how the clock output from the -//! hibernation is used to clock other peripherals in the system. The ALT -//! clock settings allow clocking a subset of the peripherals. See the -//! hibernate section in the datasheet to determine which peripherals can be -//! clocked by the ALT clock outputs from the Hibernation module. -//! The \e ui32Config parameter can have any combination of the following -//! values: -//! -//! - \b HIBERNATE_OUT_SYSCLK enables the hibernate clock output to the system -//! clock. -//! -//! The \b HIBERNATE_OSC_DISABLE option is used to disable and power down the -//! internal oscillator if an external clock source or no clock source is used -//! instead of a 32.768-kHz crystal. In the case where an external crystal is -//! used, either the \b HIBERNATE_OSC_HIGHDRIVE or \b HIBERNATE_OSC_LOWDRIVE is -//! used. These settings optimizes the oscillator drive strength to match the -//! size of the filter capacitor that is used with the external crystal -//! circuit. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateClockConfig(uint32_t ui32Config) -{ - uint32_t ui32HIBCtl; - - ASSERT((ui32Config & ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | - HIBERNATE_OSC_DISABLE)) == 0); - - ui32HIBCtl = HWREG(HIB_CTL); - - // - // Clear the current configuration bits. - // - ui32HIBCtl &= ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | - HIBERNATE_OSC_LFIOSC | HIBERNATE_OSC_DISABLE); - - // - // Set the new configuration bits. - // - ui32HIBCtl |= ui32Config & (HIBERNATE_OSC_HIGHDRIVE | - HIBERNATE_OSC_LOWDRIVE | - HIBERNATE_OSC_LFIOSC | - HIBERNATE_OSC_DISABLE); - - // - // Must be sure that the 32KHz clock is enabled if the hibernate is about - // to switch to it. - // - if(ui32Config & HIBERNATE_OSC_LFIOSC) - { - ui32HIBCtl |= HIB_CTL_CLK32EN; - } - - // - // Set the hibernation clocking configuration. - // - HWREG(HIB_CTL) = ui32HIBCtl; - - // - // Wait for write completion - // - _HibernateWriteComplete(); - - // - // Write the output clock configuration for devices that support - // controlling the output clocks from the hibernate module. - // - if(HIBERNATE_CLOCK_OUTPUT) - { - HWREG(HIB_CC) = ui32Config & (HIBERNATE_OUT_SYSCLK | - HIBERNATE_OUT_ALT1CLK); - } -} - -//***************************************************************************** -// -//! Enables the RTC feature of the Hibernation module. -//! -//! This function enables the RTC in the Hibernation module. The RTC can be -//! used to wake the processor from hibernation at a certain time, or to -//! generate interrupts at certain times. This function must be called before -//! using any of the RTC features of the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCEnable(void) -{ - // - // Turn on the RTC enable bit. - // - HWREG(HIB_CTL) |= HIB_CTL_RTCEN; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables the RTC feature of the Hibernation module. -//! -//! This function disables the RTC in the Hibernation module. After calling -//! this function, the RTC features of the Hibernation module are not -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCDisable(void) -{ - // - // Turn off the RTC enable bit. - // - HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Forces the Hibernation module to initiate a check of the battery voltage. -//! -//! This function forces the Hibernation module to initiate a check of the -//! battery voltage immediately rather than waiting for the next check interval -//! to pass. After calling this function, the application should call the -//! HibernateBatCheckDone() function and wait for the function to return a zero -//! value before calling the HibernateIntStatus() to check if the return code -//! has the \b HIBERNATE_INT_LOW_BAT set. If \b HIBERNATE_INT_LOW_BAT is set, -//! the battery level is low. The application can also enable the -//! \b HIBERNATE_INT_LOW_BAT interrupt and wait for an interrupt to indicate -//! that the battery level is low. -//! -//! \note A hibernation request is held off if a battery check is in progress. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateBatCheckStart(void) -{ - // - // Initiated a forced battery check. - // - HWREG(HIB_CTL) |= HIB_CTL_BATCHK; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Determines whether or not a forced battery check has completed. -//! -//! This function determines whether the forced battery check initiated by a -//! call to the HibernateBatCheckStart() function has completed. This function -//! returns a non-zero value until the battery level check has completed. Once -//! this function returns a value of zero, the Hibernation module has completed -//! the battery check and the HibernateIntStatus() function can be used to -//! check if the battery was low by checking if the value returned has the -//! \b HIBERNATE_INT_LOW_BAT set. -//! -//! \return The value is zero when the battery level check has completed or -//! non-zero if the check is still in process. -// -//***************************************************************************** -uint32_t -HibernateBatCheckDone(void) -{ - // - // Read the current state of the battery check. - // - return(HWREG(HIB_CTL) & HIB_CTL_BATCHK); -} - -//***************************************************************************** -// -//! Configures the wake conditions for the Hibernation module. -//! -//! \param ui32WakeFlags specifies which conditions should be used for waking. -//! -//! This function enables the conditions under which the Hibernation module -//! wakes. The \e ui32WakeFlags parameter is the logical OR of any combination -//! of the following: -//! -//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. -//! - \b HIBERNATE_WAKE_RTC - wake when the RTC match occurs. -//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernate due to a low-battery -//! level being detected. -//! - \b HIBERNATE_WAKE_GPIO - wake when a GPIO pin is asserted. -//! - \b HIBERNATE_WAKE_RESET - wake when a reset pin is asserted. -//! -//! If the \b HIBERNATE_WAKE_GPIO flag is set, then one of the GPIO -//! configuration functions GPIOPinTypeWakeHigh() or GPIOPinTypeWakeLow() must -//! be called to properly configure and enable a GPIO as a wake source for -//! hibernation. -//! -//! \note The \b HIBERNATE_WAKE_GPIO and \b HIBERNATE_WAKE_RESET parameters are -//! only available on some Tiva devices. -//! -//! \note On some Tiva devices a tamper event acts as a wake source for the -//! Hibernation module. Refer the function \b HibernateTamperEventsConfig() to -//! wake from hibernation on a tamper event. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateWakeSet(uint32_t ui32WakeFlags) -{ - // - // Check the arguments. - // - ASSERT(!(ui32WakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | - HIBERNATE_WAKE_GPIO | HIBERNATE_WAKE_RESET | - HIBERNATE_WAKE_LOW_BAT))); - - // - // Set the specified wake flags in the control register. - // - HWREG(HIB_CTL) = (ui32WakeFlags | (HWREG(HIB_CTL) & - ~(HIBERNATE_WAKE_PIN | - HIBERNATE_WAKE_RTC | - HIBERNATE_WAKE_LOW_BAT))); - - // - // Wait for write completion - // - _HibernateWriteComplete(); - - // - // Write the hibernate IO register if requested. - // - if(HIBERNATE_WAKE_IO) - { - // - // If the reset or GPIOs are begin used as a wake source then the - // the VDD3ON needs to be set to allow the pads to remained - // powered. - // - if((ui32WakeFlags & (HIBERNATE_WAKE_RESET | HIBERNATE_WAKE_GPIO)) && - ((HWREG(HIB_CTL) & HIB_CTL_VDD3ON) == 0)) - { - // - // Make sure that VDD3ON mode is enabled so that the pads can - // retain their state. - // - HWREG(HIB_CTL) |= HIB_CTL_VDD3ON; - - // - // Wait for write completion - // - _HibernateWriteComplete(); - } - - // - // Set the requested flags. - // - HWREG(HIB_IO) = (ui32WakeFlags >> 16) | HIB_IO_WUUNLK; - - // - // Spin until the write complete bit is set. - // - while((HWREG(HIB_IO) & HIB_IO_IOWRC) == 0) - { - } - - // - // Clear the write unlock bit. - // - HWREG(HIB_IO) &= ~HIB_IO_WUUNLK; - } -} - -//***************************************************************************** -// -//! Gets the currently configured wake conditions for the Hibernation module. -//! -//! This function returns the flags representing the wake configuration for the -//! Hibernation module. The return value is a combination of the following -//! flags: -//! -//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted -//! - \b HIBERNATE_WAKE_RTC - wake when the RTC matches occurs -//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernation due to a low-battery -//! level being detected -//! - \b HIBERNATE_WAKE_GPIO - wake when a GPIO pin is asserted -//! - \b HIBERNATE_WAKE_RESET - wake when a reset pin is asserted -//! -//! \note The \b HIBERNATE_WAKE_LOW_BAT, \b HIBERNATE_WAKE_GPIO, and -//! \b HIBERNATE_WAKE_RESET parameters are only available on some Tiva devices. -//! -//! \note On some Tiva devices a tamper event acts as a wake source for the -//! Hibernation module. Refer the function \b HibernateTamperEventsConfig() to -//! wake from hibernation on a tamper event. -//! -//! \return Returns flags indicating the configured wake conditions. -// -//***************************************************************************** -uint32_t -HibernateWakeGet(void) -{ - uint32_t ui32Ctrl; - - // - // Read the wake bits from the control register and return those bits to - // the caller. - // - if(HIBERNATE_WAKE_IO) - { - ui32Ctrl = HWREG(HIB_CTL); - return((ui32Ctrl & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | - HIBERNATE_WAKE_LOW_BAT)) | - ((HWREG(HIB_IO) << 16) & (HIBERNATE_WAKE_RESET | - HIBERNATE_WAKE_GPIO))); - } - else - { - return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | - HIBERNATE_WAKE_LOW_BAT)); - } -} - -//***************************************************************************** -// -//! Configures the low-battery detection. -//! -//! \param ui32LowBatFlags specifies behavior of low-battery detection. -//! -//! This function enables the low-battery detection and whether hibernation is -//! allowed if a low battery is detected. If low-battery detection is enabled, -//! then a low-battery condition is indicated in the raw interrupt status -//! register, which can be enabled to trigger an interrupt. Optionally, -//! hibernation can be aborted if a low battery condition is detected. -//! -//! The \e ui32LowBatFlags parameter is one of the following values: -//! -//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low-battery condition -//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low-battery condition and abort -//! hibernation if low-battery is detected -//! -//! The other setting in the \e ui32LowBatFlags allows the caller to set one of -//! the following voltage level trigger values : -//! -//! - \b HIBERNATE_LOW_BAT_1_9V - voltage low level is 1.9 V -//! - \b HIBERNATE_LOW_BAT_2_1V - voltage low level is 2.1 V -//! - \b HIBERNATE_LOW_BAT_2_3V - voltage low level is 2.3 V -//! - \b HIBERNATE_LOW_BAT_2_5V - voltage low level is 2.5 V -//! -//! \b Example: Abort hibernate if the voltage level is below 2.1 V. -//! -//! \verbatim -//! HibernateLowBatSet(HIBERNATE_LOW_BAT_ABORT | HIBERNATE_LOW_BAT_2_1V); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -HibernateLowBatSet(uint32_t ui32LowBatFlags) -{ - // - // Check the arguments. - // - ASSERT(!(ui32LowBatFlags & - ~(HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT))); - - // - // Set the low-battery detect and abort bits in the control register, - // according to the parameter. - // - HWREG(HIB_CTL) = (ui32LowBatFlags | - (HWREG(HIB_CTL) & ~(HIB_CTL_VBATSEL_M | - HIBERNATE_LOW_BAT_ABORT))); - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Gets the currently configured low-battery detection behavior. -//! -//! This function returns a value representing the currently configured low -//! battery detection behavior. -//! -//! The return value is a combination of the values described in the -//! HibernateLowBatSet() function. -//! -//! \return Returns a value indicating the configured low-battery detection. -// -//***************************************************************************** -uint32_t -HibernateLowBatGet(void) -{ - // - // Read the supported low bat bits from the control register and return - // those bits to the caller. - // - return(HWREG(HIB_CTL) & (HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT)); -} - -//***************************************************************************** -// -//! Sets the value of the real time clock (RTC) counter. -//! -//! \param ui32RTCValue is the new value for the RTC. -//! -//! This function sets the value of the RTC. The RTC counter contains the -//! count in seconds when a 32.768kHz clock source is in use. The RTC must be -//! enabled by calling HibernateRTCEnable() before calling this function. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCSet(uint32_t ui32RTCValue) -{ - // - // Load register requires unlock. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Write the new RTC value to the RTC load register. - // - HWREG(HIB_RTCLD) = ui32RTCValue; - - // - // Wait for write completion - // - _HibernateWriteComplete(); - - // - // Unlock. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Gets the value of the real time clock (RTC) counter. -//! -//! This function gets the value of the RTC and returns it to the caller. -//! -//! \return Returns the value of the RTC counter in seconds. -// -//***************************************************************************** -uint32_t -HibernateRTCGet(void) -{ - // - // Return the value of the RTC counter register to the caller. - // - return(HWREG(HIB_RTCC)); -} - -//***************************************************************************** -// -//! Sets the value of the RTC match register. -//! -//! \param ui32Match is the index of the match register. -//! \param ui32Value is the value for the match register. -//! -//! This function sets a match register for the RTC. The Hibernation -//! module can be configured to wake from hibernation, and/or generate an -//! interrupt when the value of the RTC counter is the same as the match -//! register. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCMatchSet(uint32_t ui32Match, uint32_t ui32Value) -{ - ASSERT(ui32Match == 0); - - // - // Write the new match value to the match register. - // - HWREG(HIB_RTCM0) = ui32Value; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Gets the value of the requested RTC match register. -//! -//! \param ui32Match is the index of the match register. -//! -//! This function gets the value of the match register for the RTC. The only -//! value that can be used with the \e ui32Match parameter is zero, other -//! values are reserved for future use. -//! -//! \return Returns the value of the requested match register. -// -//***************************************************************************** -uint32_t -HibernateRTCMatchGet(uint32_t ui32Match) -{ - ASSERT(ui32Match == 0); - - // - // Return the value of the match register to the caller. - // - return(HWREG(HIB_RTCM0)); -} - -//***************************************************************************** -// -//! Sets the value of the RTC sub second match register. -//! -//! \param ui32Match is the index of the match register. -//! \param ui32Value is the value for the sub second match register. -//! -//! This function sets the sub second match register for the RTC in 1/32768 -//! of a second increments. The Hibernation module can be configured to wake -//! from hibernation, and/or generate an interrupt when the value of the RTC -//! counter is the same as the match combined with the sub second match -//! register. The only value that can be used with the \e ui32Match -//! parameter is zero, other values are reserved for future use. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCSSMatchSet(uint32_t ui32Match, uint32_t ui32Value) -{ - ASSERT(ui32Match == 0); - - // - // Write the new sub second match value to the sub second match register. - // - HWREG(HIB_RTCSS) = ui32Value << HIB_RTCSS_RTCSSM_S; - - // - // Wait for write complete to be signaled on later devices. - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Returns the value of the requested RTC sub second match register. -//! -//! \param ui32Match is the index of the match register. -//! -//! This function returns the current value of the sub second match register -//! for the RTC. The value returned is in 1/32768 second increments. The only -//! value that can be used with the \e ui32Match parameter is zero, other -//! values are reserved for future use. -//! -//! \return Returns the value of the requested sub section match register. -// -//***************************************************************************** -uint32_t -HibernateRTCSSMatchGet(uint32_t ui32Match) -{ - ASSERT(ui32Match == 0); - - // - // Read the current second RTC count. - // - return(HWREG(HIB_RTCSS) >> HIB_RTCSS_RTCSSM_S); -} - -//***************************************************************************** -// -//! Returns the current value of the RTC sub second count. -//! -//! This function returns the current value of the sub second count for the RTC -//! in 1/32768 of a second increments. The only value that can be used with -//! the \e ui32Match parameter is zero, other values are reserved for future -//! use. -//! -//! \return The current RTC sub second count in 1/32768 seconds. -// -//***************************************************************************** -uint32_t -HibernateRTCSSGet(void) -{ - // - // Read the current second RTC count. - // - return(HWREG(HIB_RTCSS) & HIB_RTCSS_RTCSSC_M); -} - -//***************************************************************************** -// -//! Sets the value of the RTC pre-divider trim register. -//! -//! \param ui32Trim is the new value for the pre-divider trim register. -//! -//! This function sets the value of the pre-divider trim register. The input -//! time source is divided by the pre-divider to achieve a one-second clock -//! rate. Once every 64 seconds, the value of the pre-divider trim register is -//! applied to the pre-divider to allow fine-tuning of the RTC rate, in order -//! to make corrections to the rate. The software application can make -//! adjustments to the pre-divider trim register to account for variations in -//! the accuracy of the input time source. The nominal value is 0x7FFF, and it -//! can be adjusted up or down in order to fine-tune the RTC rate. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCTrimSet(uint32_t ui32Trim) -{ - // - // Check the arguments. - // - ASSERT(ui32Trim < 0x10000); - - // - // Write the new trim value to the trim register. - // - HWREG(HIB_RTCT) = ui32Trim; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Gets the value of the RTC pre-divider trim register. -//! -//! This function gets the value of the pre-divider trim register. This -//! function can be used to get the current value of the trim register prior -//! to making an adjustment by using the HibernateRTCTrimSet() function. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -HibernateRTCTrimGet(void) -{ - // - // Return the value of the trim register to the caller. - // - return(HWREG(HIB_RTCT)); -} - -//***************************************************************************** -// -//! Stores data in the battery-backed memory of the Hibernation module. -//! -//! \param pui32Data points to the data that the caller wants to store in the -//! memory of the Hibernation module. -//! \param ui32Count is the count of 32-bit words to store. -//! -//! Stores a set of data in the Hibernation module battery-backed memory. -//! This memory is preserved when the power to the processor is turned off -//! and can be used to store application state information that is needed when -//! the processor wakes. Up to 16 32-bit words can be stored in the -//! battery-backed memory. The data can be restored by calling the -//! HibernateDataGet() function. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateDataSet(uint32_t *pui32Data, uint32_t ui32Count) -{ - uint32_t ui32Idx; - - // - // Check the arguments. - // - ASSERT(ui32Count <= 64); - ASSERT(pui32Data != 0); - - // - // Loop through all the words to be stored, storing one at a time. - // - for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++) - { - // - // Write a word to the battery-backed storage area. - // - HWREG(HIB_DATA + (ui32Idx * 4)) = pui32Data[ui32Idx]; - - // - // Wait for write completion - // - _HibernateWriteComplete(); - } -} - -//***************************************************************************** -// -//! Reads a set of data from the battery-backed memory of the Hibernation -//! module. -//! -//! \param pui32Data points to a location where the data that is read from the -//! Hibernation module is stored. -//! \param ui32Count is the count of 32-bit words to read. -//! -//! This function retrieves a set of data from the Hibernation module -//! battery-backed memory that was previously stored with the -//! HibernateDataSet() function. The caller must ensure that \e pui32Data -//! points to a large enough memory block to hold all the data that is read -//! from the battery-backed memory. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateDataGet(uint32_t *pui32Data, uint32_t ui32Count) -{ - uint32_t ui32Idx; - - // - // Check the arguments. - // - ASSERT(ui32Count <= 64); - ASSERT(pui32Data != 0); - - // - // Loop through all the words to be restored, reading one at a time. - // - for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++) - { - // - // Read a word from the battery-backed storage area. No delay is - // required between reads. - // - pui32Data[ui32Idx] = HWREG(HIB_DATA + (ui32Idx * 4)); - } -} - -//***************************************************************************** -// -//! Requests hibernation mode. -//! -//! This function requests the Hibernation module to disable the external -//! regulator, thus removing power from the processor and all peripherals. The -//! Hibernation module remains powered from the battery or auxiliary power -//! supply. -//! -//! The Hibernation module re-enables the external regulator when one of -//! the configured wake conditions occurs (such as RTC match or external -//! \b WAKE pin). When the power is restored, the processor goes through a -//! power-on reset although the Hibernation module is not reset. The processor -//! can retrieve saved state information with the HibernateDataGet() function. -//! Prior to calling the function to request hibernation mode, the conditions -//! for waking must have already been set by using the HibernateWakeSet() -//! function. -//! -//! Note that this function may return because some time may elapse before the -//! power is actually removed, or it may not be removed at all. For this -//! reason, the processor continues to execute instructions for some time, -//! and the caller should be prepared for this function to return. There are -//! various reasons why the power may not be removed. For example, if the -//! HibernateLowBatSet() function was used to configure an abort if low -//! battery is detected, then the power is not removed if the battery -//! voltage is too low. There may be other reasons related to the external -//! circuit design, that a request for hibernation may not actually occur. -//! -//! For all these reasons, the caller must be prepared for this function to -//! return. The simplest way to handle it is to just enter an infinite loop -//! and wait for the power to be removed. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRequest(void) -{ - // - // Set the bit in the control register to cut main power to the processor. - // - HWREG(HIB_CTL) |= HIB_CTL_HIBREQ; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Enables interrupts for the Hibernation module. -//! -//! \param ui32IntFlags is the bit mask of the interrupts to be enabled. -//! -//! This function enables the specified interrupt sources from the Hibernation -//! module. -//! -//! The \e ui32IntFlags parameter must be the logical OR of any combination of -//! the following: -//! -//! - \b HIBERNATE_INT_WR_COMPLETE - write complete interrupt -//! - \b HIBERNATE_INT_PIN_WAKE - wake from pin interrupt -//! - \b HIBERNATE_INT_LOW_BAT - low-battery interrupt -//! - \b HIBERNATE_INT_RTC_MATCH_0 - RTC match 0 interrupt -//! - \b HIBERNATE_INT_VDDFAIL - supply failure interrupt. -//! - \b HIBERNATE_INT_RESET_WAKE - wake from reset pin interrupt -//! - \b HIBERNATE_INT_GPIO_WAKE - wake from GPIO pin or reset pin interrupt. -//! -//! \note The \b HIBERNATE_INT_RESET_WAKE, \b HIBERNATE_INT_GPIO_WAKE, and -//! \b HIBERNATE_INT_VDDFAIL settings are not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you are using to -//! determine if these interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateIntEnable(uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | - HIBERNATE_INT_VDDFAIL | - HIBERNATE_INT_RESET_WAKE | - HIBERNATE_INT_GPIO_WAKE | - HIBERNATE_INT_RTC_MATCH_0 | - HIBERNATE_INT_WR_COMPLETE))); - - // - // Set the specified interrupt mask bits. - // - HWREG(HIB_IM) |= ui32IntFlags; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables interrupts for the Hibernation module. -//! -//! \param ui32IntFlags is the bit mask of the interrupts to be disabled. -//! -//! This function disables the specified interrupt sources from the -//! Hibernation module. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to the HibernateIntEnable() function. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateIntDisable(uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | - HIBERNATE_INT_VDDFAIL | - HIBERNATE_INT_RESET_WAKE | - HIBERNATE_INT_GPIO_WAKE | - HIBERNATE_INT_RTC_MATCH_0 | - HIBERNATE_INT_WR_COMPLETE))); - - // - // Clear the specified interrupt mask bits. - // - HWREG(HIB_IM) &= ~ui32IntFlags; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Returns the hibernate module interrupt number. -//! -//! This function returns the interrupt number for the hibernate module. -//! -//! \return Returns a hibernate interrupt number or 0 if the interrupt does not -//! exist. -// -//***************************************************************************** -static uint32_t -_HibernateIntNumberGet(void) -{ - uint32_t ui32Int; - - // - // Find the valid interrupt number for the hibernate module. - // - if(CLASS_IS_TM4C129) - { - ui32Int = INT_HIBERNATE_TM4C129; - } - else - { - ui32Int = INT_HIBERNATE_TM4C123; - } - - return(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the Hibernation module interrupt. -//! -//! \param pfnHandler points to the function to be called when a hibernation -//! interrupt occurs. -//! -//! This function registers the interrupt handler in the system interrupt -//! controller. The interrupt is enabled at the global level, but individual -//! interrupt sources must still be enabled with a call to -//! HibernateIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateIntRegister(void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Get the interrupt number for the Hibernate module. - // - ui32Int = _HibernateIntNumberGet(); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the hibernate module interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the Hibernation module interrupt. -//! -//! This function unregisters the interrupt handler in the system interrupt -//! controller. The interrupt is disabled at the global level, and the -//! interrupt handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateIntUnregister(void) -{ - uint32_t ui32Int; - - // - // Get the interrupt number for the Hibernate module. - // - ui32Int = _HibernateIntNumberGet(); - - ASSERT(ui32Int != 0); - - // - // Disable the hibernate interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Gets the current interrupt status of the Hibernation module. -//! -//! \param bMasked is false to retrieve the raw interrupt status, and true to -//! retrieve the masked interrupt status. -//! -//! This function returns the interrupt status of the Hibernation module. The -//! caller can use this function to determine the cause of a hibernation -//! interrupt. Either the masked or raw interrupt status can be returned. -//! -//! \note A wake from reset pin also signals a wake from GPIO pin with the -//! value returned being HIBERNATE_INT_GPIO_WAKE | HIBERNATE_INT_RESET_WAKE. -//! Hence a wake from reset pin should take priority over wake from GPIO pin. -//! -//! \return Returns the interrupt status as a bit field with the values as -//! described in the HibernateIntEnable() function. -// -//***************************************************************************** -uint32_t -HibernateIntStatus(bool bMasked) -{ - // - // Read and return the Hibernation module raw or masked interrupt status. - // - if(bMasked == true) - { - return(HWREG(HIB_MIS)); - } - else - { - return(HWREG(HIB_RIS)); - } -} - -//***************************************************************************** -// -//! Clears pending interrupts from the Hibernation module. -//! -//! \param ui32IntFlags is the bit mask of the interrupts to be cleared. -//! -//! This function clears the specified interrupt sources. This function must -//! be called within the interrupt handler or else the handler is called again -//! upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to the HibernateIntEnable() function. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -HibernateIntClear(uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | - HIBERNATE_INT_VDDFAIL | - HIBERNATE_INT_RESET_WAKE | - HIBERNATE_INT_GPIO_WAKE | - HIBERNATE_INT_RTC_MATCH_0 | - HIBERNATE_INT_WR_COMPLETE))); - - // - // Write the specified interrupt bits into the interrupt clear register. - // - HWREG(HIB_IC) |= ui32IntFlags; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Checks to see if the Hibernation module is already powered up. -//! -//! This function queries the control register to determine if the module is -//! already active. This function can be called at a power-on reset to help -//! determine if the reset is due to a wake from hibernation or a cold start. -//! If the Hibernation module is already active, then it does not need to be -//! re-enabled, and its status can be queried immediately. -//! -//! The software application should also use the HibernateIntStatus() function -//! to read the raw interrupt status to determine the cause of the wake. The -//! HibernateDataGet() function can be used to restore state. These -//! combinations of functions can be used by the software to determine if the -//! processor is waking from hibernation and the appropriate action to take as -//! a result. -//! -//! \return Returns \b true if the module is already active, and \b false if -//! not. -// -//***************************************************************************** -uint32_t -HibernateIsActive(void) -{ - // - // Read the control register, and return true if the module is enabled. - // - return(HWREG(HIB_CTL) & HIB_CTL_CLK32EN ? 1 : 0); -} - -//***************************************************************************** -// -//! Enables GPIO retention after wake from hibernation. -//! -//! This function enables the GPIO pin state to be maintained during -//! hibernation and remain active even when waking from hibernation. The GPIO -//! module itself is reset upon entering hibernation and no longer controls the -//! output pins. To maintain the current output level after waking from -//! hibernation, the GPIO module must be reconfigured and then the -//! HibernateGPIORetentionDisable() function must be called to return control -//! of the GPIO pin to the GPIO module. -//! -//! \note The hibernation GPIO retention setting is not available on all -//! Tiva devices. Please consult the data sheet to determine if the -//! device you are using supports this feature in the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateGPIORetentionEnable(void) -{ - // - // Enable power to the pads and enable GPIO retention during hibernate. - // - HWREG(HIB_CTL) |= HIB_CTL_VDD3ON | HIB_CTL_RETCLR; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables GPIO retention after wake from hibernation. -//! -//! This function disables the retention of the GPIO pin state during -//! hibernation and allows the GPIO pins to be controlled by the system. If -//! the HibernateGPIORetentionEnable() function is called before entering -//! hibernation, this function must be called after returning from hibernation -//! to allow the GPIO pins to be controlled by GPIO module. -//! -//! \note The hibernate GPIO retention setting is not available on all -//! Tiva devices. Please consult the data sheet to determine if the -//! device you are using supports this feature in the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateGPIORetentionDisable(void) -{ - // - // Reset the GPIO configuration after waking from hibernate and disable - // the hibernate power to the pads. - // - HWREG(HIB_CTL) &= ~(HIB_CTL_RETCLR | HIB_CTL_VDD3ON); - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Returns the current setting for GPIO retention. -//! -//! This function returns the current setting for GPIO retention in the -//! hibernate module. -//! -//! \note The hibernation GPIO retention setting is not available on all -//! Tiva devices. Please consult the data sheet to determine if the -//! device you are using supports this feature in the Hibernation module. -//! -//! \return Returns true if GPIO retention is enabled and false if GPIO -//! retention is disabled. -// -//***************************************************************************** -bool -HibernateGPIORetentionGet(void) -{ - // - // Read the current GPIO retention configuration. - // - if((HWREG(HIB_CTL) & (HIB_CTL_RETCLR | HIB_CTL_VDD3ON)) == - (HIB_CTL_RETCLR | HIB_CTL_VDD3ON)) - { - return(true); - } - return(false); -} - -//***************************************************************************** -// -//! Configures the Hibernation module's internal counter mode. -//! -//! \param ui32Config is the configuration to use for the Hibernation module's -//! counter. -//! -//! This function configures the Hibernate module's counter mode to operate -//! as a standard RTC counter or to operate in a calendar mode. The -//! \e ui32Config parameter is used to provide the configuration for -//! the counter and must include only one of the following values: -//! -//! - \b HIBERNATE_COUNTER_24HR specifies 24-hour calendar mode. -//! - \b HIBERNATE_COUNTER_12HR specifies 12-hour AM/PM calendar mode. -//! - \b HIBERNATE_COUNTER_RTC specifies RTC counter mode. -//! -//! The HibernateCalendar functions can only be called when either -//! \b HIBERNATE_COUNTER_24HR or \b HIBERNATE_COUNTER_12HR is specified. -//! -//! \b Example: Configure hibernate counter to 24-hour calendar mode. -//! -//! \verbatim -//! -//! // -//! // Configure the hibernate module counter to 24-hour calendar mode. -//! // -//! HibernateCounterMode(HIBERNATE_COUNTER_24HR); -//! -//! \endverbatim -//! -//! \note The hibernate calendar mode is not available on all Tiva -//! devices. Please consult the data sheet to determine if the device you are -//! using supports this feature in the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateCounterMode(uint32_t ui32Config) -{ - // - // Set the requested configuration. - // - HWREG(HIB_CALCTL) = ui32Config; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -// Internal function to parse the time structure to set the calendar fields. -// -//***************************************************************************** -static void -_HibernateCalendarSet(uint32_t ui32Reg, struct tm *psTime) -{ - uint32_t ui32Time, ui32Date; - - ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN); - - // - // Minutes and seconds are consistent in all modes. - // - ui32Time = (((psTime->tm_min << HIB_CALLD0_MIN_S) & HIB_CALLD0_MIN_M) | - ((psTime->tm_sec << HIB_CALLD0_SEC_S) & HIB_CALLD0_SEC_M)); - - // - // 24 Hour time is used directly for Calendar set. - // - if(HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) - { - ui32Time |= (psTime->tm_hour << HIB_CALLD0_HR_S); - - // - // for Calendar match, if it is every hour, AMPM bit should be clear - // - if((ui32Reg == HIB_CALM0) && (psTime->tm_hour == 0xFF) ) - { - // - // clear AMPM bit - // - ui32Time &= ~HIB_CAL0_AMPM; - } - } - else - { - // - // In AM/PM time hours have to be capped at 12. - // If the hours are all 1s, it means the match for the hour is - // always true. We need to set 1F in the hw field. - // - if(psTime->tm_hour == 0xFF) - { - // - // Match every hour. - // - ui32Time |= HIB_CALLD0_HR_M; - } - else if(psTime->tm_hour >= 12) - { - // - // Need to set the PM bit if it is noon or later. - // - ui32Time |= (((psTime->tm_hour - 12) << HIB_CALLD0_HR_S) | - HIB_CAL0_AMPM); - } - else - { - // - // All other times are normal and AM. - // - ui32Time |= (psTime->tm_hour << HIB_CALLD0_HR_S); - } - } - - // - // Create the date in the correct register format. - // - if(ui32Reg == HIB_CAL0) - { - // - // We must add 1 to the month, since the time structure lists - // the month from 0 to 11 and the HIB lists it from 1 to 12. - // - ui32Date = ((psTime->tm_mday << HIB_CAL1_DOM_S) | - ((psTime->tm_mon + 1) << HIB_CAL1_MON_S) | - (psTime->tm_wday << HIB_CAL1_DOW_S) | - ((psTime->tm_year - 100) << HIB_CAL1_YEAR_S)); - } - else - { - // - // Wday, month and year are not included in the match - // Functionality. - // - if(psTime->tm_mday == 0xFF) - { - // - // program 0 to match every day - // - ui32Date = 0 << HIB_CAL1_DOM_M; - } - else - { - ui32Date = (psTime->tm_mday << HIB_CAL1_DOM_S); - } - } - - // - // Load register requires unlock. - // - if(ui32Reg == HIB_CAL0) - { - // - // Unlock the hibernate counter load registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - } - - // - // Set the requested time and date. - // - if(ui32Reg == HIB_CAL0) - { - HWREG(HIB_CALLD0) = ui32Time; - _HibernateWriteComplete(); - HWREG(HIB_CALLD1) = ui32Date; - _HibernateWriteComplete(); - } - else - { - HWREG(HIB_CALM0) = ui32Time; - _HibernateWriteComplete(); - HWREG(HIB_CALM1) = ui32Date; - _HibernateWriteComplete(); - } - - // - // Load register requires unlock. - // - if(ui32Reg == HIB_CAL0) - { - // - // Lock the hibernate counter load registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); - } -} - -//***************************************************************************** -// -//! Sets the Hibernation module's date and time in calendar mode. -//! -//! \param psTime is the structure that holds the information for the current -//! date and time. -//! -//! This function uses the \e psTime parameter to set the current date and -//! time when the Hibernation module is in calendar mode. Regardless of -//! whether 24-hour or 12-hour mode is in use, the \e psTime structure uses a -//! 24-hour representation of the time. This function can only be called when -//! the hibernate counter is configured in calendar mode using the -//! HibernateCounterMode() function with one of the calendar modes. -//! -//! \note The hibernate calendar mode is not available on all Tiva -//! devices. Please consult the data sheet to determine if the device you are -//! using supports this feature in the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateCalendarSet(struct tm *psTime) -{ - // - // Load a new date/time. - // - _HibernateCalendarSet(HIB_CAL0, psTime); -} - -//***************************************************************************** -// -//! Returns the Hibernation module's date and time in calendar mode. -//! -//! \param psTime is the structure that is filled with the current date and -//! time. -//! -//! This function returns the current date and time in the structure provided -//! by the \e psTime parameter. Regardless of the calendar mode, the -//! \e psTime parameter uses a 24-hour representation of the time. This -//! function can only be called when the Hibernation module is configured in -//! calendar mode using the HibernateCounterMode() function with one of the -//! calendar modes. -//! -//! The only case where this function fails and returns a non-zero value is -//! when the function detects that the counter is passing from the last second -//! of the day to the first second of the next day. This exception must be -//! handled in the application by waiting at least one second before calling -//! again to get the updated calendar information. -//! -//! \note The hibernate calendar mode is not available on all Tiva -//! devices. Please consult the data sheet to determine if the device you are -//! using supports this feature in the Hibernation module. -//! -//! \return Returns zero if the time and date were read successfully and -//! returns a non-zero value if the \e psTime structure was not updated. -// -//***************************************************************************** -int -HibernateCalendarGet(struct tm *psTime) -{ - uint32_t ui32Date, ui32Time; - - ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN); - - // - // Wait for the value to be valid, this should never be more than a few - // loops and should never hang. - // - do - { - ui32Date = HWREG(HIB_CAL1); - } - while((ui32Date & HIB_CAL1_VALID) == 0); - - // - // Wait for the value to be valid, this should never be more than a few - // loops and should never hang. - // - do - { - ui32Time = HWREG(HIB_CAL0); - } - while((ui32Time & HIB_CAL0_VALID) == 0); - - // - // The date changed after reading the time so fail this call and let the - // application call again since it knows how int32_t to wait until another - // second passes. - // - if(ui32Date != HWREG(HIB_CAL1)) - { - return(-1); - } - - // - // Populate the date and time fields in the psTime structure. - // We must subtract 1 from the month, since the time structure lists - // the month from 0 to 11 and the HIB lists it from 1 to 12. - // - psTime->tm_min = (ui32Time & HIB_CAL0_MIN_M) >> HIB_CAL0_MIN_S; - psTime->tm_sec = (ui32Time & HIB_CAL0_SEC_M) >> HIB_CAL0_SEC_S; - psTime->tm_mon = (((ui32Date & HIB_CAL1_MON_M) >> HIB_CAL1_MON_S) - 1); - psTime->tm_mday = (ui32Date & HIB_CAL1_DOM_M) >> HIB_CAL1_DOM_S; - psTime->tm_wday = (ui32Date & HIB_CAL1_DOW_M) >> HIB_CAL1_DOW_S; - psTime->tm_year = ((ui32Date & HIB_CAL1_YEAR_M) >> HIB_CAL1_YEAR_S) + 100; - psTime->tm_hour = (ui32Time & HIB_CAL0_HR_M) >> HIB_CAL0_HR_S; - - // - // Fix up the hour in the non-24-hour mode and the time is in PM. - // - if(((HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) == 0) && - (ui32Time & HIB_CAL0_AMPM)) - { - psTime->tm_hour += 12; - } - - return(0); -} - -//***************************************************************************** -// -//! Sets the Hibernation module's date and time match value in calendar mode. -//! -//! \param ui32Index indicates which match register to access. -//! \param psTime is the structure that holds all of the information to set -//! the current date and time match values. -//! -//! This function uses the \e psTime parameter to set the current date and time -//! match value in the Hibernation module's calendar. Regardless of the mode, -//! the \e psTime parameter uses a 24-hour clock representation of time. -//! This function can only be called when the Hibernation module is -//! configured in calendar mode using the HibernateCounterMode() -//! function. The \e ui32Index value is reserved for future use and should -//! always be zero. -//! Calendar match can be enabled for every day, every hour, every minute or -//! every second, setting any of these fields to 0xFF causes a match for -//! that field. For example, setting the day of month field to 0xFF -//! results in a calendar match daily at the same time. -//! -//! \note The hibernate calendar mode is not available on all Tiva -//! devices. Please consult the data sheet to determine if the device you are -//! using supports this feature in the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateCalendarMatchSet(uint32_t ui32Index, struct tm *psTime) -{ - // - // Set the Match value. - // - _HibernateCalendarSet(HIB_CALM0, psTime); -} - -//***************************************************************************** -// -//! Returns the Hibernation module's date and time match value in calendar -//! mode. -//! -//! \param ui32Index indicates which match register to access. -//! \param psTime is the structure to fill with the current date and time -//! match value. -//! -//! This function returns the current date and time match value in the -//! structure provided by the \e psTime parameter. Regardless of the mode, the -//! \e psTime parameter uses a 24-hour clock representation of time. -//! This function can only be called when the Hibernation module is configured -//! in calendar mode using the HibernateCounterMode() function. -//! The \e ui32Index value is reserved for future use and should always be -//! zero. -//! -//! \note The hibernate calendar mode is not available on all Tiva -//! devices. Please consult the data sheet to determine if the device you are -//! using supports this feature in the Hibernation module. -//! -//! \return Returns zero if the time and date match value were read -//! successfully and returns a non-zero value if the psTime structure was not -//! updated. -// -//***************************************************************************** -void -HibernateCalendarMatchGet(uint32_t ui32Index, struct tm *psTime) -{ - uint32_t ui32Date, ui32Time; - - ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN); - - // - // Get the date field. - // - ui32Date = HWREG(HIB_CALM1); - - // - // Get the time field. - // - ui32Time = HWREG(HIB_CALM0); - - // - // Populate the date and time fields in the psTime structure. - // - if((ui32Time & HIB_CAL0_MIN_M) == HIB_CAL0_MIN_M) - { - // - // Match every minute - // - psTime->tm_min = 0xFF; - } - else - { - psTime->tm_min = (ui32Time & HIB_CAL0_MIN_M) >> HIB_CAL0_MIN_S; - } - - if((ui32Time & HIB_CAL0_SEC_M) == HIB_CAL0_SEC_M) - { - // - // Match every second - // - psTime->tm_sec = 0xFF; - } - else - { - psTime->tm_sec = (ui32Time & HIB_CAL0_SEC_M) >> HIB_CAL0_SEC_S; - } - - if((ui32Time & HIB_CAL0_HR_M) == HIB_CAL0_HR_M) - { - // - // Match every hour - // - psTime->tm_hour = 0xFF; - } - else - { - psTime->tm_hour = (ui32Time & HIB_CAL0_HR_M) >> HIB_CAL0_HR_S; - } - - if((ui32Date & HIB_CAL1_DOM_M) == 0) - { - // - // Match every day - // - psTime->tm_mday = 0xFF; - } - else - { - psTime->tm_mday = (ui32Date & HIB_CAL1_DOM_M) >> HIB_CAL1_DOM_S; - } - - // - // Fix up the hour in the non-24-hour mode and the time is in PM. - // - if(((HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) == 0) && - (ui32Time & HIB_CAL0_AMPM)) - { - psTime->tm_hour += 12; - } -} - -//***************************************************************************** -// -//! Configures the tamper feature event response. -//! -//! \param ui32Config specifies the configuration options for tamper events. -//! -//! This function is used to configure the event response options for the -//! tamper feature. The \e ui32Config parameter provides a combination of the -//! \b HIBERNATE_TAMPER_EVENTS_* features to set these options. The -//! application should choose from the following set of defines to determine -//! what happens to the system when a tamper event occurs: -//! -//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_ALL_HIB_MEM all of the Hibernation -//! module's battery-backed RAM is cleared due to a tamper event -//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_HIGH_HIB_MEM the upper half of the -//! Hibernation module's battery-backed RAM is cleared due to a tamper event -//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_LOW_HIB_MEM the lower half of the -//! Hibernation module's battery-backed RAM is cleared due to a tamper event -//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_NO_HIB_MEM the Hibernation module's -//! battery-backed RAM is not changed due to a tamper event -//! - \b HIBERNATE_TAMPER_EVENTS_HIB_WAKE a tamper event wakes the MCU from -//! hibernation -//! - \b HIBERNATE_TAMPER_EVENTS_NO_HIB_WAKE a tamper event does not wake the -//! MCU from hibernation -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperEventsConfig(uint32_t ui32Config) -{ - uint32_t ui32Temp; - - // - // Mask out the on-event configuration options. - // - ui32Temp = (HWREG(HIB_TPCTL) & ~HIB_TPCTL_MEMCLR_M); - - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Set the on-event configuration. - // - HWREG(HIB_TPCTL) = (ui32Temp | ui32Config); - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Enables the tamper feature. -//! -//! This function is used to enable the tamper feature functionality. This -//! function should only be called after the global configuration is set with -//! a call to HibernateTamperEventsConfig() and the tamper inputs have been -//! configured with a call to HibernateTamperIOEnable(). -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperEnable(void) -{ - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Set the tamper enable bit. - // - HWREG(HIB_TPCTL) |= HIB_TPCTL_TPEN; - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables the tamper feature. -//! -//! This function is used to disable the tamper feature functionality. All -//! other configuration settings are left unmodified, allowing a call to -//! HibernateTamperEnable() to quickly enable the tamper feature with its -//! previous configuration. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperDisable(void) -{ - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Clear the tamper enable bit. - // - HWREG(HIB_TPCTL) &= ~HIB_TPCTL_TPEN; - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Configures an input to the tamper feature. -//! -//! \param ui32Input is the tamper input to configure. -//! \param ui32Config holds the configuration options for a given input to the -//! tamper feature. -//! -//! This function is used to configure an input to the tamper feature. The -//! \e ui32Input parameter specifies the tamper signal to configure and has a -//! valid range of 0-3. The \e ui32Config parameter provides the set of tamper -//! features in the \b HIBERNATE_TAMPER_IO_* values. The values that are valid -//! in the \e ui32Config parameter are: -//! -//! - \b HIBERNATE_TAMPER_IO_MATCH_SHORT configures the trigger to match after -//! 2 hibernation clocks -//! - \b HIBERNATE_TAMPER_IO_MATCH_LONG configures the trigger to match after -//! 3071 hibernation clocks -//! - \b HIBERNATE_TAMPER_IO_WPU_ENABLED turns on an internal weak pull up -//! - \b HIBERNATE_TAMPER_IO_WPU_DISABLED turns off an internal weak pull up -//! - \b HIBERNATE_TAMPER_IO_TRIGGER_HIGH sets the tamper event to active high -//! - \b HIBERNATE_TAMPER_IO_TRIGGER_LOW sets the tamper event to active low -//! -//! \note None of the GPIO API functions are needed to configure the tamper -//! pins. The tamper pins configured by using this function overrides any -//! configuration by GPIO APIs. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config) -{ - uint32_t ui32Temp, ui32Mask; - - // - // Verify parameters. - // - ASSERT(ui32Input < 4); - - // - // Read the current tamper I/O configuration. - // - ui32Temp = HWREG(HIB_TPIO); - - // - // Mask out configuration options for the requested input. - // - ui32Mask = (ui32Temp & (~((HIB_TPIO_GFLTR0 | HIB_TPIO_PUEN0 | - HIB_TPIO_LEV0 | HIB_TPIO_EN0) << - (ui32Input << 3)))); - - // - // Set tamper I/O configuration for the requested input. - // - ui32Temp = (ui32Mask | ((ui32Config | HIB_TPIO_EN0) << (ui32Input << 3))); - - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Write to the register. - // - HWREG(HIB_TPIO) = ui32Temp; - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables an input to the tamper feature. -//! -//! \param ui32Input is the tamper input to disable. -//! -//! This function is used to disable an input to the tamper feature. The -//! \e ui32Input parameter specifies the tamper signal to disable and has a -//! valid range of 0-3. -//! -//! \note None of the GPIO API functions are needed to configure the tamper -//! pins. The tamper pins configured by using this function overrides any -//! configuration by GPIO APIs. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperIODisable(uint32_t ui32Input) -{ - // - // Verify parameters. - // - ASSERT(ui32Input < 4); - - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Clear the I/O enable bit. - // - HWREG(HIB_TPIO) &= ((~HIB_TPIO_EN0) << (ui32Input << 3)); - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Clears the tamper feature events. -//! -//! This function is used to clear all tamper events. This function always -//! clears the tamper feature event state indicator along with all tamper log -//! entries. Logged event data should be retrieved with -//! HibernateTamperEventsGet() prior to requesting a event clear. -//! -//! HibernateTamperEventsClear() should be called prior to clearing the system -//! control NMI that resulted from the tamper event. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperEventsClear(void) -{ - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Set the tamper event clear bit. - // - HWREG(HIB_TPCTL) |= HIB_TPCTL_TPCLR; - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Clears the tamper feature events without Unlock and Lock. -//! -//! This function is used to clear all tamper events without unlock/locking -//! the tamper control registers, so API HibernateTamperUnLock() should be -//! called before this function, and API HibernateTamperLock() should be -//! called after to ensure that tamper control registers are locked. -//! -//! This function doesn't block until the write is complete. -//! Therefore, care must be taken to ensure the next immediate write will -//! occure only after the write complete bit is set. -//! -//! This function is used to implement a software workaround in NMI interrupt -//! handler to fix an issue when a new tamper event could be missed during -//! the clear of current tamper event. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperEventsClearNoLock(void) -{ - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Set the tamper event clear bit. - // - HWREG(HIB_TPCTL) |= HIB_TPCTL_TPCLR; - -} - -//***************************************************************************** -// -//! Unlock temper registers. -//! -//! This function is used to unlock the temper control registers. This -//! function should be only used before calling API -//! HibernateTamperEventsClearNoLock(). -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperUnLock(void) -{ - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Lock temper registers. -//! -//! This function is used to lock the temper control registers. This -//! function should be used after calling API -//! HibernateTamperEventsClearNoLock(). -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperLock(void) -{ - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Returns the current tamper feature status. -//! -//! This function is used to return the tamper feature status. This function -//! returns one of the values from this group of options: -//! -//! - \b HIBERNATE_TAMPER_STATUS_INACTIVE indicates tamper detection is -//! disabled -//! - \b HIBERNATE_TAMPER_STATUS_ACTIVE indicates tamper detection is enabled -//! and ready -//! - \b HIBERNATE_TAMPER_STATUS_EVENT indicates tamper event was detected -//! -//! In addition, one of the values is included from this group: -//! -//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_INACTIVE indicates the external -//! oscillator is not active -//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE indicates the external -//! oscillator is active -//! -//! And one of the values is included from this group: -//! -//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED indicates the external -//! oscillator signal has transitioned from valid to invalid -//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID indicates the external -//! oscillator is providing a valid signal -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return Returns a combination of the \b HIBERNATE_TAMPER_STATUS_* values. -// -//***************************************************************************** -uint32_t -HibernateTamperStatusGet(void) -{ - uint32_t ui32Status, ui32Reg; - - // - // Retrieve the raw register value. - // - ui32Reg = HWREG(HIB_TPSTAT); - - // - // Setup the oscillator status indicators. - // - ui32Status = (ui32Reg & (HIB_TPSTAT_XOSCST | HIB_TPSTAT_XOSCFAIL)); - ui32Status |= ((ui32Reg & HIB_TPSTAT_XOSCST) ? 0 : - HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE); - ui32Status |= ((ui32Reg & HIB_TPSTAT_XOSCFAIL) ? 0 : - HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID); - - // - // Retrieve the tamper status indicators. - // - ui32Status |= ((ui32Reg & HIB_TPSTAT_STATE_M) << 3); - - // - // The HW shows "disabled" with a zero value, use bit[0] as a flag - // for this purpose. - // - if((ui32Reg & HIB_TPSTAT_STATE_M) == 0) - { - ui32Status |= HIBERNATE_TAMPER_STATUS_INACTIVE; - } - - // - // Return the API status flags. - // - return(ui32Status); -} - -//***************************************************************************** -// -//! Returns a tamper log entry. -//! -//! \param ui32Index is the index of the log entry to return. -//! \param pui32RTC is a pointer to the memory to store the logged RTC data. -//! \param pui32Event is a pointer to the memory to store the logged tamper -//! event. -//! -//! This function is used to return a tamper log entry from the hibernate -//! feature. The \e ui32Index specifies the zero-based index of the log entry -//! to query and has a valid range of 0-3. -//! -//! When this function returns, the \e pui32RTC value contains the time value -//! and \e pui32Event parameter contains the tamper I/O event that triggered -//! this log. -//! -//! The format of the returned \e pui32RTC data is dependent on the -//! configuration of the RTC within the Hibernation module. If the RTC is -//! configured for counter mode, the returned data contains counted seconds -//! from the RTC enable. If the RTC is configured for calendar mode, the data -//! returned is formatted as follows: -//! -//! \verbatim -//! +----------------------------------------------------------------------+ -//! | 31:26 | 25:22 | 21:17 | 16:12 | 11:6 | 5:0 | -//! +----------------------------------------------------------------------+ -//! | year | month | day of month | hours | minutes | seconds | -//! +----------------------------------------------------------------------+ -//! \endverbatim -//! -//! The data returned in the \e pui32Events parameter could include any of the -//! following flags: -//! -//! - \b HIBERNATE_TAMPER_EVENT_0 indicates a tamper event was triggered on I/O -//! signal 0 -//! - \b HIBERNATE_TAMPER_EVENT_1 indicates a tamper event was triggered on I/O -//! signal 1 -//! - \b HIBERNATE_TAMPER_EVENT_2 indicates a tamper event was triggered on I/O -//! signal 2 -//! - \b HIBERNATE_TAMPER_EVENT_3 indicates a tamper event was triggered on I/O -//! signal 3 -//! - \b HIBERNATE_TAMPER_EVENT_XOSC indicates an external oscillator failure -//! triggered the tamper event -//! -//! \note Tamper event logs are not consumed when read and remain available -//! until cleared. Events are only logged if unused log space is available. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return Returns \b true if the \e pui32RTC and \e pui32Events were updated -//! successfully and returns \b false if the values were not updated. -// -//***************************************************************************** -bool -HibernateTamperEventsGet(uint32_t ui32Index, uint32_t *pui32RTC, - uint32_t *pui32Event) -{ - uint32_t ui32Reg; - - // - // Verify parameters. - // - ASSERT(pui32RTC); - ASSERT(pui32Event); - ASSERT(ui32Index < 4); - - // - // Retrieve the event log data for the requested index if available. - // - ui32Reg = HWREG(HIB_TPLOG0 + ((ui32Index << 3) + 4)); - if(ui32Reg == 0) - { - // - // No event data is available for this index. - // - return(false); - } - - // - // Store the event data in the provided location. - // - *pui32Event = ui32Reg; - - // - // Retrieve the calendar information. - // - *pui32RTC = HWREG(HIB_TPLOG0 + (ui32Index << 3)); - - // - // Convert the hour to 24hr mode if the Calendar is enabled - // and in 24hr mode. - // - if((HWREG(HIB_CALCTL) & (HIB_CALCTL_CALEN | HIB_CALCTL_CAL24)) == - (HIB_CALCTL_CALEN | HIB_CALCTL_CAL24)) - { - if(HWREG(HIB_CAL0) & HIB_CAL0_AMPM) - { - // - // Add 12 hour since it is PM - // - ui32Reg = ((*pui32RTC & 0X0001f000) + (12<<12)) & 0X0001f000; - *pui32RTC &= ~0X0001f000; - *pui32RTC |= ui32Reg; - } - } - - // - // Return success. - // - return(true); -} - -//***************************************************************************** -// -//! Attempts to recover the external oscillator. -//! -//! This function is used to attempt to recover the external oscillator after a -//! \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED status is reported. This -//! function must not be called if the external oscillator is not used as -//! the hibernation clock input. HibernateTamperExtOscValid() should be called -//! before calling this function. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperExtOscRecover(void) -{ - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Set the XOSCFAIL clear bit. - // - HWREG(HIB_TPSTAT) |= HIB_TPSTAT_XOSCFAIL; - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Reports if the external oscillator signal is active and stable. -//! -//! This function should be used to verify the external oscillator is active -//! and valid before attempting to recover from a -//! \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED status by calling -//! HibernateTamperExtOscRecover(). -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return Returns \b true if the external oscillator is both active and -//! stable, otherwise a \b false indicator is returned. -// -//***************************************************************************** -bool -HibernateTamperExtOscValid(void) -{ - if(HibernateTamperStatusGet() & (HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE | - HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID)) - { - return(true); - } - - return(false); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/hibernate.h b/bsp/tm4c129x-dk/libraries/driverlib/hibernate.h deleted file mode 100644 index 80633b950c143869d10a00c4610720bdf58230f7..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/hibernate.h +++ /dev/null @@ -1,257 +0,0 @@ -//***************************************************************************** -// -// hibernate.h - API definition for the Hibernation module. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_HIBERNATE_H__ -#define __DRIVERLIB_HIBERNATE_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Macros need to configure wake events for HibernateWakeSet() -// -//***************************************************************************** -#define HIBERNATE_WAKE_PIN 0x00000010 -#define HIBERNATE_WAKE_RTC 0x00000008 -#define HIBERNATE_WAKE_LOW_BAT 0x00000200 -#define HIBERNATE_WAKE_GPIO 0x00000010 -#define HIBERNATE_WAKE_RESET 0x00100010 -#define HIBERNATE_WAKE_TAMPER 0x08000010 - -//***************************************************************************** -// -// Macros needed to configure low battery detect for HibernateLowBatSet() -// -//***************************************************************************** -#define HIBERNATE_LOW_BAT_DETECT \ - 0x00000020 -#define HIBERNATE_LOW_BAT_ABORT 0x000000A0 -#define HIBERNATE_LOW_BAT_1_9V 0x00000000 -#define HIBERNATE_LOW_BAT_2_1V 0x00002000 -#define HIBERNATE_LOW_BAT_2_3V 0x00004000 -#define HIBERNATE_LOW_BAT_2_5V 0x00006000 - -//***************************************************************************** -// -// Macros defining interrupt source bits for the interrupt functions. -// -//***************************************************************************** -#define HIBERNATE_INT_VDDFAIL 0x00000080 -#define HIBERNATE_INT_RESET_WAKE \ - 0x00000040 -#define HIBERNATE_INT_GPIO_WAKE 0x00000020 -#define HIBERNATE_INT_WR_COMPLETE \ - 0x00000010 -#define HIBERNATE_INT_PIN_WAKE 0x00000008 -#define HIBERNATE_INT_LOW_BAT 0x00000004 -#define HIBERNATE_INT_RTC_MATCH_0 \ - 0x00000001 - -//***************************************************************************** -// -// Macros defining oscillator configuration options for the -// HibernateClockConfig() function. -// -//***************************************************************************** -#define HIBERNATE_OSC_LFIOSC 0x00080000 -#define HIBERNATE_OSC_LOWDRIVE 0x00000000 -#define HIBERNATE_OSC_HIGHDRIVE 0x00020000 -#define HIBERNATE_OSC_DISABLE 0x00010000 -#define HIBERNATE_OUT_WRSTALL 0x20000000 -#define HIBERNATE_OUT_SYSCLK 0x00000001 -#define HIBERNATE_OUT_ALT1CLK 0x00000002 - -//***************************************************************************** -// -// The following defines are used with the HibernateCounterMode() API. -// -//***************************************************************************** -#define HIBERNATE_COUNTER_RTC 0x00000000 -#define HIBERNATE_COUNTER_12HR 0x00000001 -#define HIBERNATE_COUNTER_24HR 0x00000005 - -//***************************************************************************** -// -// Tamper event configuration options used with HibernateTamperEventsConfig(). -// -//***************************************************************************** -#define HIBERNATE_TAMPER_EVENTS_NO_HIB_WAKE \ - 0x00000000 -#define HIBERNATE_TAMPER_EVENTS_HIB_WAKE \ - 0x00000800 -#define HIBERNATE_TAMPER_EVENTS_NO_ERASE_HIB_MEM \ - 0x00000000 -#define HIBERNATE_TAMPER_EVENTS_ERASE_LOW_HIB_MEM \ - 0x00000100 -#define HIBERNATE_TAMPER_EVENTS_ERASE_HIGH_HIB_MEM \ - 0x00000200 -#define HIBERNATE_TAMPER_EVENTS_ERASE_ALL_HIB_MEM \ - 0x00000300 - -//***************************************************************************** -// -// Status flags returned by the HibernateTamperStatus() function. -// -//***************************************************************************** -#define HIBERNATE_TAMPER_STATUS_INACTIVE \ - 0x00000010 -#define HIBERNATE_TAMPER_STATUS_ACTIVE \ - 0x00000020 -#define HIBERNATE_TAMPER_STATUS_EVENT \ - 0x00000040 -#define HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE \ - 0x00000008 -#define HIBERNATE_TAMPER_STATUS_EXT_OSC_INACTIVE \ - 0x00000002 -#define HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID \ - 0x00000004 -#define HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED \ - 0x00000001 - -//***************************************************************************** -// -// Configuration options used with HibernateTamperIOEnable(). -// -//***************************************************************************** -#define HIBERNATE_TAMPER_IO_TRIGGER_LOW \ - 0x00000000 -#define HIBERNATE_TAMPER_IO_TRIGGER_HIGH \ - 0x00000002 -#define HIBERNATE_TAMPER_IO_WPU_DISABLED \ - 0x00000000 -#define HIBERNATE_TAMPER_IO_WPU_ENABLED \ - 0x00000004 -#define HIBERNATE_TAMPER_IO_MATCH_SHORT \ - 0x00000000 -#define HIBERNATE_TAMPER_IO_MATCH_LONG \ - 0x00000008 - -//***************************************************************************** -// -// Tamper log event flags. -// -//***************************************************************************** -#define HIBERNATE_TAMPER_EVENT_0 \ - 0x00000001 -#define HIBERNATE_TAMPER_EVENT_1 \ - 0x00000002 -#define HIBERNATE_TAMPER_EVENT_2 \ - 0x00000004 -#define HIBERNATE_TAMPER_EVENT_3 \ - 0x00000008 -#define HIBERNATE_TAMPER_EVENT_EXT_OSC \ - 0x00010000 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void HibernateGPIORetentionEnable(void); -extern void HibernateGPIORetentionDisable(void); -extern bool HibernateGPIORetentionGet(void); -extern void HibernateEnableExpClk(uint32_t ui32HibClk); -extern void HibernateDisable(void); -extern void HibernateRTCEnable(void); -extern void HibernateRTCDisable(void); -extern void HibernateWakeSet(uint32_t ui32WakeFlags); -extern uint32_t HibernateWakeGet(void); -extern void HibernateLowBatSet(uint32_t ui32LowBatFlags); -extern uint32_t HibernateLowBatGet(void); -extern void HibernateRTCSet(uint32_t ui32RTCValue); -extern uint32_t HibernateRTCGet(void); -extern void HibernateRTCMatchSet(uint32_t ui32Match, uint32_t ui32Value); -extern uint32_t HibernateRTCMatchGet(uint32_t ui32Match); -extern void HibernateRTCTrimSet(uint32_t ui32Trim); -extern uint32_t HibernateRTCTrimGet(void); -extern void HibernateDataSet(uint32_t *pui32Data, uint32_t ui32Count); -extern void HibernateDataGet(uint32_t *pui32Data, uint32_t ui32Count); -extern void HibernateRequest(void); -extern void HibernateIntEnable(uint32_t ui32IntFlags); -extern void HibernateIntDisable(uint32_t ui32IntFlags); -extern void HibernateIntRegister(void (*pfnHandler)(void)); -extern void HibernateIntUnregister(void); -extern uint32_t HibernateIntStatus(bool bMasked); -extern void HibernateIntClear(uint32_t ui32IntFlags); -extern uint32_t HibernateIsActive(void); -extern void HibernateRTCSSMatchSet(uint32_t ui32Match, uint32_t ui32Value); -extern uint32_t HibernateRTCSSMatchGet(uint32_t ui32Match); -extern uint32_t HibernateRTCSSGet(void); -extern void HibernateClockConfig(uint32_t ui32Config); -extern void HibernateBatCheckStart(void); -extern uint32_t HibernateBatCheckDone(void); -extern void HibernateCounterMode(uint32_t ui32Config); -extern void HibernateCalendarSet(struct tm *psTime); -extern int HibernateCalendarGet(struct tm *psTime); -extern void HibernateCalendarMatchSet(uint32_t ui32Index, struct tm *psTime); -extern void HibernateCalendarMatchGet(uint32_t ui32Index, struct tm *psTime); -extern void HibernateTamperEnable(void); -extern void HibernateTamperEventsConfig(uint32_t ui32Config); -extern bool HibernateTamperEventsGet(uint32_t ui32Index, uint32_t *pui32RTC, - uint32_t *pui32Event); -extern void HibernateTamperEventsClear(void); -extern void HibernateTamperEventsClearNoLock(void); -extern void HibernateTamperUnLock(void); -extern void HibernateTamperLock(void); -extern void HibernateTamperDisable(void); -extern void HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config); -extern void HibernateTamperIODisable(uint32_t ui32Input); -extern uint32_t HibernateTamperStatusGet(void); -extern void HibernateTamperExtOscRecover(void); -extern bool HibernateTamperExtOscValid(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_HIBERNATE_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/i2c.c b/bsp/tm4c129x-dk/libraries/driverlib/i2c.c deleted file mode 100644 index 37aa1d764b8fc618048fe56ab3d89ebfeb049e79..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/i2c.c +++ /dev/null @@ -1,2193 +0,0 @@ -//***************************************************************************** -// -// i2c.c - Driver for Inter-IC (I2C) bus block. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup i2c_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_i2c.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/i2c.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -// A mapping of I2C base address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32I2CIntMap[][2] = -{ - { I2C0_BASE, INT_I2C0_TM4C123 }, - { I2C1_BASE, INT_I2C1_TM4C123 }, - { I2C2_BASE, INT_I2C2_TM4C123 }, - { I2C3_BASE, INT_I2C3_TM4C123 }, - { I2C4_BASE, INT_I2C4_TM4C123 }, - { I2C5_BASE, INT_I2C5_TM4C123 }, -}; - -static const int_fast8_t g_i8I2CIntMapRows = - sizeof(g_ppui32I2CIntMap) / sizeof(g_ppui32I2CIntMap[0]); - -static const uint32_t g_ppui32I2CIntMapSnowflake[][2] = -{ - { I2C0_BASE, INT_I2C0_TM4C129 }, - { I2C1_BASE, INT_I2C1_TM4C129 }, - { I2C2_BASE, INT_I2C2_TM4C129 }, - { I2C3_BASE, INT_I2C3_TM4C129 }, - { I2C4_BASE, INT_I2C4_TM4C129 }, - { I2C5_BASE, INT_I2C5_TM4C129 }, - { I2C6_BASE, INT_I2C6_TM4C129 }, - { I2C7_BASE, INT_I2C7_TM4C129 }, - { I2C8_BASE, INT_I2C8_TM4C129 }, - { I2C9_BASE, INT_I2C9_TM4C129 }, -}; -static const int_fast8_t g_i8I2CIntMapSnowflakeRows = - sizeof(g_ppui32I2CIntMapSnowflake) / sizeof(g_ppui32I2CIntMapSnowflake[0]); - -//***************************************************************************** -// -//! \internal -//! Checks an I2C base address. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function determines if a I2C module base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_I2CBaseValid(uint32_t ui32Base) -{ - return((ui32Base == I2C0_BASE) || (ui32Base == I2C1_BASE) || - (ui32Base == I2C2_BASE) || (ui32Base == I2C3_BASE) || - (ui32Base == I2C4_BASE) || (ui32Base == I2C5_BASE) || - (ui32Base == I2C6_BASE) || (ui32Base == I2C7_BASE) || - (ui32Base == I2C8_BASE) || (ui32Base == I2C9_BASE)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Gets the I2C interrupt number. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! Given a I2C base address, this function returns the corresponding -//! interrupt number. -//! -//! \return Returns an I2C interrupt number, or 0 if \e ui32Base is invalid. -// -//***************************************************************************** -static uint32_t -_I2CIntNumberGet(uint32_t ui32Base) -{ - int_fast8_t i8Idx, i8Rows; - const uint32_t (*ppui32I2CIntMap)[2]; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - ppui32I2CIntMap = g_ppui32I2CIntMap; - i8Rows = g_i8I2CIntMapRows; - - if(CLASS_IS_TM4C129) - { - ppui32I2CIntMap = g_ppui32I2CIntMapSnowflake; - i8Rows = g_i8I2CIntMapSnowflakeRows; - } - - // - // Loop through the table that maps I2C base addresses to interrupt - // numbers. - // - for(i8Idx = 0; i8Idx < i8Rows; i8Idx++) - { - // - // See if this base address matches. - // - if(ppui32I2CIntMap[i8Idx][0] == ui32Base) - { - // - // Return the corresponding interrupt number. - // - return(ppui32I2CIntMap[i8Idx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Initializes the I2C Master block. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32I2CClk is the rate of the clock supplied to the I2C module. -//! \param bFast set up for fast data transfers. -//! -//! This function initializes operation of the I2C Master block by configuring -//! the bus speed for the master and enabling the I2C Master block. -//! -//! If the parameter \e bFast is \b true, then the master block is set up to -//! transfer data at 400 Kbps; otherwise, it is set up to transfer data at -//! 100 Kbps. If Fast Mode Plus (1 Mbps) is desired, software should manually -//! write the I2CMTPR after calling this function. For High Speed (3.4 Mbps) -//! mode, a specific command is used to switch to the faster clocks after the -//! initial communication with the slave is done at either 100 Kbps or -//! 400 Kbps. -//! -//! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet() for TM4C123x -//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, -//! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the -//! variable call holding the return value of SysCtlClockFreqSet()). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, - bool bFast) -{ - uint32_t ui32SCLFreq; - uint32_t ui32TPR; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Must enable the device before doing anything else. - // - I2CMasterEnable(ui32Base); - - // - // Get the desired SCL speed. - // - if(bFast == true) - { - ui32SCLFreq = 400000; - } - else - { - ui32SCLFreq = 100000; - } - - // - // Compute the clock divider that achieves the fastest speed less than or - // equal to the desired speed. The numerator is biased to favor a larger - // clock divider so that the resulting clock is always less than or equal - // to the desired clock, never greater. - // - ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / - (2 * 10 * ui32SCLFreq)) - 1; - HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; - - // - // Check to see if this I2C peripheral is High-Speed enabled. If yes, also - // choose the fastest speed that is less than or equal to 3.4 Mbps. - // - if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS) - { - ui32TPR = ((ui32I2CClk + (2 * 3 * 3400000) - 1) / - (2 * 3 * 3400000)) - 1; - HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR; - } -} - -//***************************************************************************** -// -//! Initializes the I2C Slave block. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8SlaveAddr 7-bit slave address -//! -//! This function initializes operation of the I2C Slave block by configuring -//! the slave address and enabling the I2C Slave block. -//! -//! The parameter \e ui8SlaveAddr is the value that is compared against the -//! slave address sent by an I2C master. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Must enable the device before doing anything else. - // - I2CSlaveEnable(ui32Base); - - // - // Set up the slave address. - // - HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; -} - -//***************************************************************************** -// -//! Sets the I2C slave address. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8AddrNum determines which slave address is set. -//! \param ui8SlaveAddr is the 7-bit slave address -//! -//! This function writes the specified slave address. The \e ui32AddrNum field -//! dictates which slave address is configured. For example, a value of 0 -//! configures the primary address and a value of 1 configures the secondary. -//! -//! \note Not all Tiva devices support a secondary address. Please -//! consult the device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8AddrNum > 1)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Determine which slave address is being set. - // - switch(ui8AddrNum) - { - // - // Set up the primary slave address. - // - case 0: - { - HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; - break; - } - - // - // Set up and enable the secondary slave address. - // - case 1: - { - HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr; - break; - } - } -} - -//***************************************************************************** -// -//! Enables the I2C Master block. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function enables operation of the I2C Master block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master block. - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE; -} - -//***************************************************************************** -// -//! Enables the I2C Slave block. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This fucntion enables operation of the I2C Slave block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the clock to the slave block. - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE; - - // - // Enable the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; -} - -//***************************************************************************** -// -//! Disables the I2C master block. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function disables operation of the I2C master block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master block. - // - HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE); -} - -//***************************************************************************** -// -//! Disables the I2C slave block. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function disables operation of the I2C slave block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = 0; - - // - // Disable the clock to the slave block. - // - HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the I2C module. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param pfnHandler is a pointer to the function to be called when the -//! I2C interrupt occurs. -//! -//! This function sets the handler to be called when an I2C interrupt occurs. -//! This function enables the global interrupt in the interrupt controller; -//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and -//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's -//! responsibility to clear the interrupt source via I2CMasterIntClear() and -//! I2CSlaveIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the I2C port. - // - ui32Int = _I2CIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the I2C interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the I2C module. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function clears the handler to be called when an I2C interrupt -//! occurs. This function also masks off the interrupt in the interrupt r -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -I2CIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the I2C port. - // - ui32Int = _I2CIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables the I2C Master interrupt. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function enables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) = 1; -} - -//***************************************************************************** -// -//! Enables individual I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated I2C Master interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b I2C_MASTER_INT_RX_FIFO_FULL - RX FIFO Full interrupt -//! - \b I2C_MASTER_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt -//! - \b I2C_MASTER_INT_RX_FIFO_REQ - RX FIFO Request interrupt -//! - \b I2C_MASTER_INT_TX_FIFO_REQ - TX FIFO Request interrupt -//! - \b I2C_MASTER_INT_ARB_LOST - Arbitration Lost interrupt -//! - \b I2C_MASTER_INT_STOP - Stop Condition interrupt -//! - \b I2C_MASTER_INT_START - Start Condition interrupt -//! - \b I2C_MASTER_INT_NACK - Address/Data NACK interrupt -//! - \b I2C_MASTER_INT_TX_DMA_DONE - TX DMA Complete interrupt -//! - \b I2C_MASTER_INT_RX_DMA_DONE - RX DMA Complete interrupt -//! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt -//! - \b I2C_MASTER_INT_DATA - Data interrupt -//! -//! \note Not all Tiva devices support all of the listed interrupt -//! sources. Please consult the device data sheet to determine if these -//! features are supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Enables the I2C Slave interrupt. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function enables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA; -} - -//***************************************************************************** -// -//! Enables individual I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated I2C Slave interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b I2C_SLAVE_INT_RX_FIFO_FULL - RX FIFO Full interrupt -//! - \b I2C_SLAVE_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt -//! - \b I2C_SLAVE_INT_RX_FIFO_REQ - RX FIFO Request interrupt -//! - \b I2C_SLAVE_INT_TX_FIFO_REQ - TX FIFO Request interrupt -//! - \b I2C_SLAVE_INT_TX_DMA_DONE - TX DMA Complete interrupt -//! - \b I2C_SLAVE_INT_RX_DMA_DONE - RX DMA Complete interrupt -//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt -//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt -//! - \b I2C_SLAVE_INT_DATA - Data interrupt -//! -//! \note Not all Tiva devices support the all of the listed interrupts. -//! Please consult the device data sheet to determine if these features are -//! supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables the I2C Master interrupt. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function disables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) = 0; -} - -//***************************************************************************** -// -//! Disables individual I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated I2C Master interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables the I2C Slave interrupt. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function disables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA; -} - -//***************************************************************************** -// -//! Disables individual I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated I2C Slave interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets the current I2C Master interrupt status. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -bool -I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false); - } - else - { - return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Master interrupt status. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in I2CMasterIntEnableEx(). -// -//***************************************************************************** -uint32_t -I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + I2C_O_MMIS)); - } - else - { - return(HWREG(ui32Base + I2C_O_MRIS)); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Slave interrupt status. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Slave. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -bool -I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false); - } - else - { - return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Slave interrupt status. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Slave. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in I2CSlaveIntEnableEx(). -// -//***************************************************************************** -uint32_t -I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + I2C_O_SMIS)); - } - else - { - return(HWREG(ui32Base + I2C_O_SRIS)); - } -} - -//***************************************************************************** -// -//! Clears I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! The I2C Master interrupt source is cleared, so that it no longer -//! asserts. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C master interrupt source. - // - HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC; - - // - // Workaround for I2C master interrupt clear errata for rev B Tiva - // devices. For later devices, this write is ignored and therefore - // harmless (other than the slight performance hit). - // - HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC; -} - -//***************************************************************************** -// -//! Clears I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified I2C Master interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C master interrupt source. - // - HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Clears I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! The I2C Slave interrupt source is cleared, so that it no longer asserts. -//! This function must be called in the interrupt handler to keep the interrupt -//! from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C slave interrupt source. - // - HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC; -} - -//***************************************************************************** -// -//! Clears I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified I2C Slave interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C slave interrupt source. - // - HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Sets the address that the I2C Master places on the bus. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8SlaveAddr 7-bit slave address -//! \param bReceive flag indicating the type of communication with the slave -//! -//! This function configures the address that the I2C Master places on the -//! bus when initiating a transaction. When the \e bReceive parameter is set -//! to \b true, the address indicates that the I2C Master is initiating a -//! read from the slave; otherwise the address indicates that the I2C -//! Master is initiating a write to the slave. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, - bool bReceive) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Set the address of the slave with which the master will communicate. - // - HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; -} - -//***************************************************************************** -// -//! Reads the state of the SDA and SCL pins. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function returns the state of the I2C bus by providing the real time -//! values of the SDA and SCL pins. -//! -//! \note Not all Tiva devices support this function. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return Returns the state of the bus with SDA in bit position 1 and SCL in -//! bit position 0. -// -//***************************************************************************** -uint32_t -I2CMasterLineStateGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the line state. - // - return(HWREG(ui32Base + I2C_O_MBMON)); -} - -//***************************************************************************** -// -//! Indicates whether or not the I2C Master is busy. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function returns an indication of whether or not the I2C Master is -//! busy transmitting or receiving data. -//! -//! \return Returns \b true if the I2C Master is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -bool -I2CMasterBusy(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the busy status. - // - if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! Indicates whether or not the I2C bus is busy. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function returns an indication of whether or not the I2C bus is busy. -//! This function can be used in a multi-master environment to determine if -//! another master is currently using the bus. -//! -//! \return Returns \b true if the I2C bus is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -bool -I2CMasterBusBusy(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the bus busy status. - // - if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! Controls the state of the I2C Master. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Cmd command to be issued to the I2C Master. -//! -//! This function is used to control the state of the Master send and -//! receive operations. The \e ui8Cmd parameter can be one of the following -//! values: -//! -//! - \b I2C_MASTER_CMD_SINGLE_SEND -//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE -//! - \b I2C_MASTER_CMD_BURST_SEND_START -//! - \b I2C_MASTER_CMD_BURST_SEND_CONT -//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH -//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP -//! - \b I2C_MASTER_CMD_QUICK_COMMAND -//! - \b I2C_MASTER_CMD_HS_MASTER_CODE_SEND -//! - \b I2C_MASTER_CMD_FIFO_SINGLE_SEND -//! - \b I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_START -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_CONT -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP -//! -//! \note Not all Tiva devices have an I2C FIFO and support the FIFO -//! commands. Please consult the device data sheet to determine if this -//! feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || - (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_QUICK_COMMAND) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_SEND) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_START) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_CONT) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_HS_MASTER_CODE_SEND)); - - // - // Send the command. - // - HWREG(ui32Base + I2C_O_MCS) = ui32Cmd; -} - -//***************************************************************************** -// -//! Gets the error status of the I2C Master. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function is used to obtain the error status of the Master send -//! and receive operations. -//! -//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE, -//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or -//! \b I2C_MASTER_ERR_ARB_LOST. -// -//***************************************************************************** -uint32_t -I2CMasterErr(uint32_t ui32Base) -{ - uint32_t ui32Err; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Get the raw error state - // - ui32Err = HWREG(ui32Base + I2C_O_MCS); - - // - // If the I2C master is busy, then all the other bit are invalid, and - // don't have an error to report. - // - if(ui32Err & I2C_MCS_BUSY) - { - return(I2C_MASTER_ERR_NONE); - } - - // - // Check for errors. - // - if(ui32Err & (I2C_MCS_ERROR | I2C_MCS_ARBLST)) - { - return(ui32Err & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK)); - } - else - { - return(I2C_MASTER_ERR_NONE); - } -} - -//***************************************************************************** -// -//! Transmits a byte from the I2C Master. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8Data data to be transmitted from the I2C Master. -//! -//! This function places the supplied data into I2C Master Data Register. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the byte. - // - HWREG(ui32Base + I2C_O_MDR) = ui8Data; -} - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Master. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function reads a byte of data from the I2C Master Data Register. -//! -//! \return Returns the byte received from by the I2C Master, cast as an -//! uint32_t. -// -//***************************************************************************** -uint32_t -I2CMasterDataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_MDR)); -} - -//***************************************************************************** -// -//! Sets the Master clock timeout value. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Value is the number of I2C clocks before the timeout is -//! asserted. -//! -//! This function enables and configures the clock low timeout feature in the -//! I2C peripheral. This feature is implemented as a 12-bit counter, with the -//! upper 8-bits being programmable. For example, to program a timeout of 20ms -//! with a 100-kHz SCL frequency, \e ui32Value is 0x7d. -//! -//! \note Not all Tiva devices support this function. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the timeout value. - // - HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value; -} - -//***************************************************************************** -// -//! Configures ACK override behavior of the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bEnable enables or disables ACK override. -//! -//! This function enables or disables ACK override, allowing the user -//! application to drive the value on SDA during the ACK cycle. -//! -//! \note Not all Tiva devices support this function. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable or disable based on bEnable. - // - if(bEnable) - { - HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN; - } - else - { - HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN; - } -} - -//***************************************************************************** -// -//! Writes the ACK value. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bACK chooses whether to ACK (true) or NACK (false) the transfer. -//! -//! This function puts the desired ACK value on SDA during the ACK cycle. The -//! value written is only valid when ACK override is enabled using -//! I2CSlaveACKOverride(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // ACK or NACK based on the value of bACK. - // - if(bACK) - { - HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL; - } - else - { - HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL; - } -} - -//***************************************************************************** -// -//! Gets the I2C Slave status -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function returns the action requested from a master, if any. -//! Possible values are: -//! -//! - \b I2C_SLAVE_ACT_NONE -//! - \b I2C_SLAVE_ACT_RREQ -//! - \b I2C_SLAVE_ACT_TREQ -//! - \b I2C_SLAVE_ACT_RREQ_FBR -//! - \b I2C_SLAVE_ACT_OWN2SEL -//! - \b I2C_SLAVE_ACT_QCMD -//! - \b I2C_SLAVE_ACT_QCMD_DATA -//! -//! \note Not all Tiva devices support the second I2C slave's own address -//! or the quick command function. Please consult the device data sheet to -//! determine if these features are supported. -//! -//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been -//! requested of the I2C Slave, \b I2C_SLAVE_ACT_RREQ to indicate that -//! an I2C master has sent data to the I2C Slave, \b I2C_SLAVE_ACT_TREQ -//! to indicate that an I2C master has requested that the I2C Slave send -//! data, \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent -//! data to the I2C slave and the first byte following the slave's own address -//! has been received, \b I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C -//! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick -//! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the -//! data bit was set when the quick command was received. -// -//***************************************************************************** -uint32_t -I2CSlaveStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the slave status. - // - return(HWREG(ui32Base + I2C_O_SCSR)); -} - -//***************************************************************************** -// -//! Transmits a byte from the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8Data is the data to be transmitted from the I2C Slave -//! -//! This function places the supplied data into I2C Slave Data Register. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the byte. - // - HWREG(ui32Base + I2C_O_SDR) = ui8Data; -} - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function reads a byte of data from the I2C Slave Data Register. -//! -//! \return Returns the byte received from by the I2C Slave, cast as an -//! uint32_t. -// -//***************************************************************************** -uint32_t -I2CSlaveDataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_SDR)); -} - -//***************************************************************************** -// -//! Configures the I2C transmit (TX) FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Config is the configuration of the FIFO using specified macros. -//! -//! This configures the I2C peripheral's transmit FIFO. The transmit FIFO can -//! be used by the master or slave, but not both. The following macros are -//! used to configure the TX FIFO behavior for master or slave, with or without -//! DMA: -//! -//! \b I2C_FIFO_CFG_TX_MASTER, \b I2C_FIFO_CFG_TX_SLAVE, -//! \b I2C_FIFO_CFG_TX_MASTER_DMA, \b I2C_FIFO_CFG_TX_SLAVE_DMA -//! -//! To select the trigger level, one of the following macros should be used: -//! -//! \b I2C_FIFO_CFG_TX_TRIG_1, \b I2C_FIFO_CFG_TX_TRIG_2, -//! \b I2C_FIFO_CFG_TX_TRIG_3, \b I2C_FIFO_CFG_TX_TRIG_4, -//! \b I2C_FIFO_CFG_TX_TRIG_5, \b I2C_FIFO_CFG_TX_TRIG_6, -//! \b I2C_FIFO_CFG_TX_TRIG_7, \b I2C_FIFO_CFG_TX_TRIG_8 -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear transmit configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000; - - // - // Store new transmit configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; -} - -//***************************************************************************** -// -//! Flushes the transmit (TX) FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function flushes the I2C transmit FIFO. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CTxFIFOFlush(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Flush the TX FIFO. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH; -} - -//***************************************************************************** -// -//! Configures the I2C receive (RX) FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Config is the configuration of the FIFO using specified macros. -//! -//! This configures the I2C peripheral's receive FIFO. The receive FIFO can be -//! used by the master or slave, but not both. The following macros are used -//! to configure the RX FIFO behavior for master or slave, with or without DMA: -//! -//! \b I2C_FIFO_CFG_RX_MASTER, \b I2C_FIFO_CFG_RX_SLAVE, -//! \b I2C_FIFO_CFG_RX_MASTER_DMA, \b I2C_FIFO_CFG_RX_SLAVE_DMA -//! -//! To select the trigger level, one of the following macros should be used: -//! -//! \b I2C_FIFO_CFG_RX_TRIG_1, \b I2C_FIFO_CFG_RX_TRIG_2, -//! \b I2C_FIFO_CFG_RX_TRIG_3, \b I2C_FIFO_CFG_RX_TRIG_4, -//! \b I2C_FIFO_CFG_RX_TRIG_5, \b I2C_FIFO_CFG_RX_TRIG_6, -//! \b I2C_FIFO_CFG_RX_TRIG_7, \b I2C_FIFO_CFG_RX_TRIG_8 -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear receive configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff; - - // - // Store new receive configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; -} - -//***************************************************************************** -// -//! Flushes the receive (RX) FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function flushes the I2C receive FIFO. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CRxFIFOFlush(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Flush the TX FIFO. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH; -} - -//***************************************************************************** -// -//! Gets the current FIFO status. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function retrieves the status for both the transmit (TX) and receive -//! (RX) FIFOs. The trigger level for the transmit FIFO is set using -//! I2CTxFIFOConfigSet() and for the receive FIFO using I2CTxFIFOConfigSet(). -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return Returns the FIFO status, enumerated as a bit field containing -//! \b I2C_FIFO_RX_BELOW_TRIG_LEVEL, \b I2C_FIFO_RX_FULL, \b I2C_FIFO_RX_EMPTY, -//! \b I2C_FIFO_TX_BELOW_TRIG_LEVEL, \b I2C_FIFO_TX_FULL, and -//! \b I2C_FIFO_TX_EMPTY. -// -//***************************************************************************** -uint32_t -I2CFIFOStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the contents of the FIFO status register. - // - return(HWREG(ui32Base + I2C_O_FIFOSTATUS)); -} - -//***************************************************************************** -// -//! Writes a data byte to the I2C transmit FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8Data is the data to be placed into the transmit FIFO. -//! -//! This function adds a byte of data to the I2C transmit FIFO. If there is -//! no space available in the FIFO, this function waits for space to become -//! available before returning. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Wait until there is space. - // - while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) - { - } - - // - // Place data into the FIFO. - // - HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; -} - -//***************************************************************************** -// -//! Writes a data byte to the I2C transmit FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8Data is the data to be placed into the transmit FIFO. -//! -//! This function adds a byte of data to the I2C transmit FIFO. If there is -//! no space available in the FIFO, this function returns a zero. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return The number of elements added to the I2C transmit FIFO. -// -//***************************************************************************** -uint32_t -I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // If FIFO is full, return zero. - // - if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) - { - return(0); - } - else - { - HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; - return(1); - } -} - -//***************************************************************************** -// -//! Reads a byte from the I2C receive FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function reads a byte of data from I2C receive FIFO and places it in -//! the location specified by the \e pui8Data parameter. If there is no data -//! available, this function waits until data is received before returning. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return The data byte. -// -//***************************************************************************** -uint32_t -I2CFIFODataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Wait until there is data to read. - // - while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) - { - } - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_FIFODATA)); -} - -//***************************************************************************** -// -//! Reads a byte from the I2C receive FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param pui8Data is a pointer where the read data is stored. -//! -//! This function reads a byte of data from I2C receive FIFO and places it in -//! the location specified by the \e pui8Data parameter. If there is no data -//! available, this functions returns 0. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return The number of elements read from the I2C receive FIFO. -// -//***************************************************************************** -uint32_t -I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // If nothing in the FIFO, return zero. - // - if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) - { - return(0); - } - else - { - *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA); - return(1); - } -} - -//***************************************************************************** -// -//! Set the burst length for a I2C master FIFO operation. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8Length is the length of the burst transfer. -//! -//! This function configures the burst length for a I2C Master FIFO operation. -//! The burst field is limited to 8 bits or 256 bytes. The burst length -//! applies to a single I2CMCS BURST operation meaning that it specifies the -//! burst length for only the current operation (can be TX or RX). Each burst -//! operation must configure the burst length prior to writing the BURST bit -//! in the I2CMCS using I2CMasterControl(). -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 256)); - - // - // Set the burst length. - // - HWREG(ui32Base + I2C_O_MBLEN) = ui8Length; -} - -//***************************************************************************** -// -//! Returns the current value of the burst transfer counter. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function returns the current value of the burst transfer counter that -//! is used by the FIFO mechanism. Software can use this value to determine -//! how many bytes remain in a transfer, or where in the transfer the burst -//! operation was if an error has occurred. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -I2CMasterBurstCountGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Get burst count. - // - return(HWREG(ui32Base + I2C_O_MBCNT)); -} - -//***************************************************************************** -// -//! Configures the I2C Master glitch filter. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Config is the glitch filter configuration. -//! -//! This function configures the I2C Master glitch filter. The value passed in -//! to \e ui32Config determines the sampling range of the glitch filter, which -//! is configurable between 1 and 32 system clock cycles. The default -//! configuration of the glitch filter is 0 system clock cycles, which means -//! that it's disabled. -//! -//! The \e ui32Config field should be any of the following values: -//! -//! - \b I2C_MASTER_GLITCH_FILTER_DISABLED -//! - \b I2C_MASTER_GLITCH_FILTER_1 -//! - \b I2C_MASTER_GLITCH_FILTER_2 -//! - \b I2C_MASTER_GLITCH_FILTER_3 -//! - \b I2C_MASTER_GLITCH_FILTER_4 -//! - \b I2C_MASTER_GLITCH_FILTER_8 -//! - \b I2C_MASTER_GLITCH_FILTER_16 -//! - \b I2C_MASTER_GLITCH_FILTER_32 -//! -//! \note Not all Tiva devices support this function. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Configure the glitch filter field of MTPR if it is TM4C129 - // - if(CLASS_IS_TM4C129) - { - HWREG(ui32Base + I2C_O_MTPR) |= ui32Config; - } - - // - // Configure the glitch filter if it is TM4C123 - // - if(CLASS_IS_TM4C123) - { - // - // Configure the glitch filter pulse width - // - HWREG(ui32Base + I2C_O_MCR2) |= (ui32Config >> 12); - - // - // Enable the glitch filter by setting the GFE bit - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_GFE; - } -} - -//***************************************************************************** -// -//! Enables FIFO usage for the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Config is the desired FIFO configuration of the I2C Slave. -//! -//! This function configures the I2C Slave to use the FIFO(s). This -//! function should be used in combination with I2CTxFIFOConfigSet() and/or -//! I2CRxFIFOConfigSet(), which configure the FIFO trigger level and tell -//! the FIFO hardware whether to interact with the I2C Master or Slave. The -//! application appropriate combination of \b I2C_SLAVE_TX_FIFO_ENABLE and -//! \b I2C_SLAVE_RX_FIFO_ENABLE should be passed in to the \e ui32Config -//! field. -//! -//! The Slave I2CSCSR register is write-only, so any call to I2CSlaveEnable(), -//! I2CSlaveDisable or I2CSlaveFIFOEnable() overwrites the slave configuration. -//! Therefore, application software should call I2CSlaveEnable() followed by -//! I2CSlaveFIFOEnable() with the desired FIFO configuration. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the FIFOs for the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA; -} - -//***************************************************************************** -// -//! Disable FIFO usage for the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function disables the FIFOs for the I2C Slave. After calling this -//! this function, the FIFOs are disabled, but the Slave remains active. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveFIFODisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable slave FIFOs. - // - HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; -} - -//***************************************************************************** -// -//! Enables internal loopback mode for an I2C port. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function configures an I2C port in internal loopback mode to help with -//! diagnostics and debug. In this mode, the SDA and SCL signals from master -//! and slave modules are internally connected. This allows data to be -//! transferred between the master and slave modules of the same I2C port, -//! without having to go through I/O's. I2CMasterDataPut(), I2CSlaveDataPut(), -//! I2CMasterDataGet(),I2CSlaveDataGet() can be used along with this function. -//! -//! \return None. -// -//***************************************************************************** -void I2CLoopbackEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the loopback enable bit to the register. - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_LPBK; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/i2c.h b/bsp/tm4c129x-dk/libraries/driverlib/i2c.h deleted file mode 100644 index ab7b44e4fe78a686e4b54d8c03dd53759c09fced..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/i2c.h +++ /dev/null @@ -1,362 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_I2C_H__ -#define __DRIVERLIB_I2C_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** - -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - 0x00000007 -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - 0x00000007 -#define I2C_MASTER_CMD_BURST_SEND_START \ - 0x00000003 -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - 0x00000001 -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - 0x00000005 -#define I2C_MASTER_CMD_BURST_SEND_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - 0x0000000b -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - 0x00000009 -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - 0x00000005 -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_QUICK_COMMAND \ - 0x00000027 -#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ - 0x00000013 -#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \ - 0x00000046 -#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \ - 0x00000046 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \ - 0x00000042 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \ - 0x00000040 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \ - 0x00000044 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \ - 0x0000004a -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \ - 0x00000048 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \ - 0x00000044 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \ - 0x00000004 - -//***************************************************************************** -// -// I2C Master glitch filter configuration. -// -//***************************************************************************** -#define I2C_MASTER_GLITCH_FILTER_DISABLED \ - 0 -#define I2C_MASTER_GLITCH_FILTER_1 \ - 0x00010000 -#define I2C_MASTER_GLITCH_FILTER_2 \ - 0x00020000 -#define I2C_MASTER_GLITCH_FILTER_3 \ - 0x00030000 -#define I2C_MASTER_GLITCH_FILTER_4 \ - 0x00040000 -#define I2C_MASTER_GLITCH_FILTER_8 \ - 0x00050000 -#define I2C_MASTER_GLITCH_FILTER_16 \ - 0x00060000 -#define I2C_MASTER_GLITCH_FILTER_32 \ - 0x00070000 - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 -#define I2C_MASTER_ERR_CLK_TOUT 0x00000080 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data -#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte -#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave -#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command -#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value - -//***************************************************************************** -// -// Miscellaneous I2C driver definitions. -// -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// I2C Master interrupts. -// -//***************************************************************************** -#define I2C_MASTER_INT_RX_FIFO_FULL \ - 0x00000800 // RX FIFO Full Interrupt -#define I2C_MASTER_INT_TX_FIFO_EMPTY \ - 0x00000400 // TX FIFO Empty Interrupt -#define I2C_MASTER_INT_RX_FIFO_REQ \ - 0x00000200 // RX FIFO Request Interrupt -#define I2C_MASTER_INT_TX_FIFO_REQ \ - 0x00000100 // TX FIFO Request Interrupt -#define I2C_MASTER_INT_ARB_LOST \ - 0x00000080 // Arb Lost Interrupt -#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt -#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt -#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt -#define I2C_MASTER_INT_TX_DMA_DONE \ - 0x00000008 // TX DMA Complete Interrupt -#define I2C_MASTER_INT_RX_DMA_DONE \ - 0x00000004 // RX DMA Complete Interrupt -#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt -#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt - -//***************************************************************************** -// -// I2C Slave interrupts. -// -//***************************************************************************** -#define I2C_SLAVE_INT_RX_FIFO_FULL \ - 0x00000100 // RX FIFO Full Interrupt -#define I2C_SLAVE_INT_TX_FIFO_EMPTY \ - 0x00000080 // TX FIFO Empty Interrupt -#define I2C_SLAVE_INT_RX_FIFO_REQ \ - 0x00000040 // RX FIFO Request Interrupt -#define I2C_SLAVE_INT_TX_FIFO_REQ \ - 0x00000020 // TX FIFO Request Interrupt -#define I2C_SLAVE_INT_TX_DMA_DONE \ - 0x00000010 // TX DMA Complete Interrupt -#define I2C_SLAVE_INT_RX_DMA_DONE \ - 0x00000008 // RX DMA Complete Interrupt -#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt -#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt -#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt - -//***************************************************************************** -// -// I2C Slave FIFO configuration macros. -// -//***************************************************************************** -#define I2C_SLAVE_TX_FIFO_ENABLE \ - 0x00000002 -#define I2C_SLAVE_RX_FIFO_ENABLE \ - 0x00000004 - -//***************************************************************************** -// -// I2C FIFO configuration macros. -// -//***************************************************************************** -#define I2C_FIFO_CFG_TX_MASTER 0x00000000 -#define I2C_FIFO_CFG_TX_SLAVE 0x00008000 -#define I2C_FIFO_CFG_RX_MASTER 0x00000000 -#define I2C_FIFO_CFG_RX_SLAVE 0x80000000 -#define I2C_FIFO_CFG_TX_MASTER_DMA \ - 0x00002000 -#define I2C_FIFO_CFG_TX_SLAVE_DMA \ - 0x0000a000 -#define I2C_FIFO_CFG_RX_MASTER_DMA \ - 0x20000000 -#define I2C_FIFO_CFG_RX_SLAVE_DMA \ - 0xa0000000 -#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000 -#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001 -#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002 -#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003 -#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004 -#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005 -#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006 -#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007 -#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008 -#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000 -#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000 -#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000 -#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000 -#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000 -#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000 -#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000 -#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000 -#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000 - -//***************************************************************************** -// -// I2C FIFO status. -// -//***************************************************************************** -#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \ - 0x00040000 -#define I2C_FIFO_RX_FULL 0x00020000 -#define I2C_FIFO_RX_EMPTY 0x00010000 -#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \ - 0x00000004 -#define I2C_FIFO_TX_FULL 0x00000002 -#define I2C_FIFO_TX_EMPTY 0x00000001 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); -extern void I2CIntUnregister(uint32_t ui32Base); -extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CTxFIFOFlush(uint32_t ui32Base); -extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CRxFIFOFlush(uint32_t ui32Base); -extern uint32_t I2CFIFOStatus(uint32_t ui32Base); -extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data); -extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base, - uint8_t ui8Data); -extern uint32_t I2CFIFODataGet(uint32_t ui32Base); -extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, - uint8_t *pui8Data); -extern void I2CMasterBurstLengthSet(uint32_t ui32Base, - uint8_t ui8Length); -extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base); -extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, - uint32_t ui32Config); -extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CSlaveFIFODisable(uint32_t ui32Base); -extern bool I2CMasterBusBusy(uint32_t ui32Base); -extern bool I2CMasterBusy(uint32_t ui32Base); -extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd); -extern uint32_t I2CMasterDataGet(uint32_t ui32Base); -extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data); -extern void I2CMasterDisable(uint32_t ui32Base); -extern void I2CMasterEnable(uint32_t ui32Base); -extern uint32_t I2CMasterErr(uint32_t ui32Base); -extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, - bool bFast); -extern void I2CMasterIntClear(uint32_t ui32Base); -extern void I2CMasterIntDisable(uint32_t ui32Base); -extern void I2CMasterIntEnable(uint32_t ui32Base); -extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked); -extern void I2CMasterIntEnableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CMasterIntDisableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base, - bool bMasked); -extern void I2CMasterIntClearEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value); -extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable); -extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK); -extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base); -extern void I2CMasterSlaveAddrSet(uint32_t ui32Base, - uint8_t ui8SlaveAddr, - bool bReceive); -extern uint32_t I2CSlaveDataGet(uint32_t ui32Base); -extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data); -extern void I2CSlaveDisable(uint32_t ui32Base); -extern void I2CSlaveEnable(uint32_t ui32Base); -extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr); -extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, - uint8_t ui8SlaveAddr); -extern void I2CSlaveIntClear(uint32_t ui32Base); -extern void I2CSlaveIntDisable(uint32_t ui32Base); -extern void I2CSlaveIntEnable(uint32_t ui32Base); -extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void I2CSlaveIntDisableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked); -extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, - bool bMasked); -extern uint32_t I2CSlaveStatus(uint32_t ui32Base); -extern void I2CLoopbackEnable(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_I2C_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/interrupt.c b/bsp/tm4c129x-dk/libraries/driverlib/interrupt.c deleted file mode 100644 index ebf5f95bd326d32dc15714c6b5d37a36a83c6a87..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/interrupt.c +++ /dev/null @@ -1,1060 +0,0 @@ -//***************************************************************************** -// -// interrupt.c - Driver for the NVIC Interrupt Controller. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup interrupt_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "driverlib/cpu.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -// This is a mapping between priority grouping encodings and the number of -// preemption priority bits. -// -//***************************************************************************** -static const uint32_t g_pui32Priority[] = -{ - NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, - NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, - NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number and the register that contains -// the priority encoding for that interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32Regs[] = -{ - 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, - NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, - NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13, - NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19, - NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25, - NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31, - NVIC_PRI32, NVIC_PRI33, NVIC_PRI34 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt enable for that -// interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32EnRegs[] = -{ - NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt disable for that -// interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32Dii16Regs[] = -{ - NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt pend for that interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32PendRegs[] = -{ - NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt unpend for that -// interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32UnpendRegs[] = -{ - NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4 -}; - -//***************************************************************************** -// -//! \internal -//! The default interrupt handler. -//! -//! This is the default interrupt handler for all interrupts. It simply loops -//! forever so that the system state is preserved for observation by a -//! debugger. Since interrupts must be disabled before unregistering the -//! corresponding handler, this should never be called during normal operation. -//! -//! \return None. -// -//***************************************************************************** -static void -_IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// The processor vector table. -// -// This contains a list of the handlers for the various interrupt sources in -// the system. The layout of this list is defined by the hardware; assertion -// of an interrupt causes the processor to start executing directly at the -// address given in the corresponding location in this list. -// -//***************************************************************************** -// -// Set the size of the vector table to the largest number of interrupts of -// any device -// -#undef NUM_INTERRUPTS -#define NUM_INTERRUPTS 155 -#if defined(ewarm) -#pragma data_alignment=1024 -static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; -#elif defined(sourcerygxx) -static __attribute__((section(".cs3.region-head.ram"))) -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024))); -#elif defined(ccs) || defined(DOXYGEN) -#pragma DATA_ALIGN(g_pfnRAMVectors, 1024) -#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable") -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); -#else -static __attribute__((section("vtable"))) -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(1024))); -#endif - -//***************************************************************************** -// -//! Enables the processor interrupt. -//! -//! This function allows the processor to respond to interrupts. This function -//! does not affect the set of interrupts enabled in the interrupt controller; -//! it just gates the single interrupt from the controller to the processor. -//! -//! \b Example: Enable interrupts to the processor. -//! -//! \verbatim -//! // -//! // Enable interrupts to the processor. -//! // -//! IntMasterEnable(); -//! -//! \endverbatim -//! -//! \return Returns \b true if interrupts were disabled when the function was -//! called or \b false if they were initially enabled. -// -//***************************************************************************** -bool -IntMasterEnable(void) -{ - // - // Enable processor interrupts. - // - return(CPUcpsie()); -} - -//***************************************************************************** -// -//! Disables the processor interrupt. -//! -//! This function prevents the processor from receiving interrupts. This -//! function does not affect the set of interrupts enabled in the interrupt -//! controller; it just gates the single interrupt from the controller to the -//! processor. -//! -//! \note Previously, this function had no return value. As such, it was -//! possible to include interrupt.h and call this function without -//! having included hw_types.h. Now that the return is a -//! bool, a compiler error occurs in this case. The solution -//! is to include hw_types.h before including interrupt.h. -//! -//! \b Example: Disable interrupts to the processor. -//! -//! \verbatim -//! // -//! // Disable interrupts to the processor. -//! // -//! IntMasterDisable(); -//! -//! \endverbatim -//! -//! \return Returns \b true if interrupts were already disabled when the -//! function was called or \b false if they were initially enabled. -// -//***************************************************************************** -bool -IntMasterDisable(void) -{ - // - // Disable processor interrupts. - // - return(CPUcpsid()); -} - -//***************************************************************************** -// -//! Registers a function to be called when an interrupt occurs. -//! -//! \param ui32Interrupt specifies the interrupt in question. -//! \param pfnHandler is a pointer to the function to be called. -//! -//! This function is used to specify the handler function to be called when the -//! given interrupt is asserted to the processor. The \e ui32Interrupt -//! parameter must be one of the valid \b INT_* values listed in Peripheral -//! Driver Library User's Guide and defined in the inc/hw_ints.h header file. -//! When the interrupt occurs, if it is enabled (via IntEnable()), the handler -//! function is called in interrupt context. Because the handler function can -//! preempt other code, care must be taken to protect memory or peripherals -//! that are accessed by the handler and other non-handler code. -//! -//! \note The use of this function (directly or indirectly via a peripheral -//! driver interrupt register function) moves the interrupt vector table from -//! flash to SRAM. Therefore, care must be taken when linking the application -//! to ensure that the SRAM vector table is located at the beginning of SRAM; -//! otherwise the NVIC does not look in the correct portion of memory for the -//! vector table (it requires the vector table be on a 1 kB memory alignment). -//! Normally, the SRAM vector table is so placed via the use of linker scripts. -//! See the discussion of compile-time versus run-time interrupt handler -//! registration in the introduction to this chapter. -//! -//! \b Example: Set the UART 0 interrupt handler. -//! -//! \verbatim -//! -//! // -//! // UART 0 interrupt handler. -//! // -//! void -//! UART0Handler(void) -//! { -//! // -//! // Handle interrupt. -//! // -//! } -//! -//! // -//! // Set the UART 0 interrupt handler. -//! // -//! IntRegister(INT_UART0, UART0Handler); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)) -{ - uint32_t ui32Idx, ui32Value; - - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Make sure that the RAM vector table is correctly aligned. - // - ASSERT(((uint32_t)g_pfnRAMVectors & 0x000003ff) == 0); - - // - // See if the RAM vector table has been initialized. - // - if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors) - { - // - // Copy the vector table from the beginning of FLASH to the RAM vector - // table. - // - ui32Value = HWREG(NVIC_VTABLE); - for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++) - { - g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) + - ui32Value); - } - - // - // Point the NVIC at the RAM vector table. - // - HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors; - } - - // - // Save the interrupt handler. - // - g_pfnRAMVectors[ui32Interrupt] = pfnHandler; -} - -//***************************************************************************** -// -//! Unregisters the function to be called when an interrupt occurs. -//! -//! \param ui32Interrupt specifies the interrupt in question. -//! -//! This function is used to indicate that no handler is called when the -//! given interrupt is asserted to the processor. The \e ui32Interrupt -//! parameter must be one of the valid \b INT_* values listed in Peripheral -//! Driver Library User's Guide and defined in the inc/hw_ints.h header file. -//! The interrupt source is automatically disabled (via IntDisable()) if -//! necessary. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \b Example: Reset the UART 0 interrupt handler to the default handler. -//! -//! \verbatim -//! // -//! // Reset the UART 0 interrupt handler to the default handler. -//! // -//! IntUnregister(INT_UART0); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntUnregister(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Reset the interrupt handler. - // - g_pfnRAMVectors[ui32Interrupt] = _IntDefaultHandler; -} - -//***************************************************************************** -// -//! Sets the priority grouping of the interrupt controller. -//! -//! \param ui32Bits specifies the number of bits of preemptable priority. -//! -//! This function specifies the split between preemptable priority levels and -//! sub-priority levels in the interrupt priority specification. The range of -//! the grouping values are dependent upon the hardware implementation; on -//! the Tiva C and E Series family, three bits are available for hardware -//! interrupt prioritization and therefore priority grouping values of three -//! through seven have the same effect. -//! -//! \b Example: Set the priority grouping for the interrupt controller. -//! -//! \verbatim -//! // -//! // Set the priority grouping for the interrupt controller to 2 bits. -//! // -//! IntPriorityGroupingSet(2); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntPriorityGroupingSet(uint32_t ui32Bits) -{ - // - // Check the arguments. - // - ASSERT(ui32Bits < NUM_PRIORITY); - - // - // Set the priority grouping. - // - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; -} - -//***************************************************************************** -// -//! Gets the priority grouping of the interrupt controller. -//! -//! This function returns the split between preemptable priority levels and -//! sub-priority levels in the interrupt priority specification. -//! -//! \b Example: Get the priority grouping for the interrupt controller. -//! -//! \verbatim -//! // -//! // Get the priority grouping for the interrupt controller. -//! // -//! IntPriorityGroupingGet(); -//! -//! \endverbatim -//! -//! \return The number of bits of preemptable priority. -// -//***************************************************************************** -uint32_t -IntPriorityGroupingGet(void) -{ - uint32_t ui32Loop, ui32Value; - - // - // Read the priority grouping. - // - ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; - - // - // Loop through the priority grouping values. - // - for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) - { - // - // Stop looping if this value matches. - // - if(ui32Value == g_pui32Priority[ui32Loop]) - { - break; - } - } - - // - // Return the number of priority bits. - // - return(ui32Loop); -} - -//***************************************************************************** -// -//! Sets the priority of an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt in question. -//! \param ui8Priority specifies the priority of the interrupt. -//! -//! This function is used to set the priority of an interrupt. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. The \e ui8Priority parameter specifies the interrupts -//! hardware priority level of the interrupt in the interrupt controller. -//! When multiple interrupts are asserted simultaneously, the ones with the -//! highest priority are processed before the lower priority interrupts. -//! Smaller numbers correspond to higher interrupt priorities; priority 0 is -//! the highest interrupt priority. -//! -//! \note The hardware priority mechanism only looks at the upper 3 bits of the -//! priority level, so any prioritization must be performed in those bits. The -//! remaining bits can be used to sub-prioritize the interrupt sources, and may -//! be used by the hardware priority mechanism on a future part. This -//! arrangement allows priorities to migrate to different NVIC implementations -//! without changing the gross prioritization of the interrupts. -//! -//! \b Example: Set priorities for UART 0 and USB interrupts. -//! -//! \verbatim -//! // -//! // Set the UART 0 interrupt priority to the lowest priority. -//! // -//! IntPrioritySet(INT_UART0, 0xE0); -//! -//! // -//! // Set the USB 0 interrupt priority to the highest priority. -//! // -//! IntPrioritySet(INT_USB0, 0); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); - - // - // Set the interrupt priority. - // - ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); - ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); - ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); - HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; -} - -//***************************************************************************** -// -//! Gets the priority of an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt in question. -//! -//! This function gets the priority of an interrupt. The \e ui32Interrupt -//! parameter must be one of the valid \b INT_* values listed in Peripheral -//! Driver Library User's Guide and defined in the inc/hw_ints.h header file. -//! See IntPrioritySet() for a full definition of the priority value. -//! -//! \b Example: Get the current UART 0 interrupt priority. -//! -//! \verbatim -//! // -//! // Get the current UART 0 interrupt priority. -//! // -//! IntPriorityGet(INT_UART0); -//! -//! \endverbatim -//! -//! \return Returns the interrupt priority for the given interrupt. -// -//***************************************************************************** -int32_t -IntPriorityGet(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); - - // - // Return the interrupt priority. - // - return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> - (8 * (ui32Interrupt & 3))) & 0xFF); -} - -//***************************************************************************** -// -//! Enables an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt to be enabled. -//! -//! The specified interrupt is enabled in the interrupt controller. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. Other enables for the interrupt (such as at the peripheral -//! level) are unaffected by this function. -//! -//! \b Example: Enable the UART 0 interrupt. -//! -//! \verbatim -//! // -//! // Enable the UART 0 interrupt in the interrupt controller. -//! // -//! IntEnable(INT_UART0); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntEnable(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to enable. - // - if(ui32Interrupt == FAULT_MPU) - { - // - // Enable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; - } - else if(ui32Interrupt == FAULT_BUS) - { - // - // Enable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; - } - else if(ui32Interrupt == FAULT_USAGE) - { - // - // Enable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Enable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; - } - else if(ui32Interrupt >= 16) - { - // - // Enable the general interrupt. - // - HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) = - 1 << ((ui32Interrupt - 16) & 31); - } -} - -//***************************************************************************** -// -//! Disables an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt to be disabled. -//! -//! The specified interrupt is disabled in the interrupt controller. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. Other enables for the interrupt (such as at the peripheral -//! level) are unaffected by this function. -//! -//! \b Example: Disable the UART 0 interrupt. -//! -//! \verbatim -//! // -//! // Disable the UART 0 interrupt in the interrupt controller. -//! // -//! IntDisable(INT_UART0); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntDisable(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to disable. - // - if(ui32Interrupt == FAULT_MPU) - { - // - // Disable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); - } - else if(ui32Interrupt == FAULT_BUS) - { - // - // Disable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); - } - else if(ui32Interrupt == FAULT_USAGE) - { - // - // Disable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Disable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - } - else if(ui32Interrupt >= 16) - { - // - // Disable the general interrupt. - // - HWREG(g_pui32Dii16Regs[(ui32Interrupt - 16) / 32]) = - 1 << ((ui32Interrupt - 16) & 31); - } -} - -//***************************************************************************** -// -//! Returns if a peripheral interrupt is enabled. -//! -//! \param ui32Interrupt specifies the interrupt to check. -//! -//! This function checks if the specified interrupt is enabled in the interrupt -//! controller. The \e ui32Interrupt parameter must be one of the valid -//! \b INT_* values listed in Peripheral Driver Library User's Guide and -//! defined in the inc/hw_ints.h header file. -//! -//! \b Example: Disable the UART 0 interrupt if it is enabled. -//! -//! \verbatim -//! // -//! // Disable the UART 0 interrupt if it is enabled. -//! // -//! if(IntIsEnabled(INT_UART0)) -//! { -//! IntDisable(INT_UART0); -//! } -//! \endverbatim -//! -//! \return A non-zero value if the interrupt is enabled. -// -//***************************************************************************** -uint32_t -IntIsEnabled(uint32_t ui32Interrupt) -{ - uint32_t ui32Ret; - - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Initialize the return value. - // - ui32Ret = 0; - - // - // Determine the interrupt to disable. - // - if(ui32Interrupt == FAULT_MPU) - { - // - // Check the MemManage interrupt. - // - ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_MEM; - } - else if(ui32Interrupt == FAULT_BUS) - { - // - // Check the bus fault interrupt. - // - ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_BUS; - } - else if(ui32Interrupt == FAULT_USAGE) - { - // - // Check the usage fault interrupt. - // - ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_USAGE; - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Check the System Tick interrupt. - // - ui32Ret = HWREG(NVIC_ST_CTRL) & NVIC_ST_CTRL_INTEN; - } - else if(ui32Interrupt >= 16) - { - // - // Check the general interrupt. - // - ui32Ret = HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) & - (1 << ((ui32Interrupt - 16) & 31)); - } - return(ui32Ret); -} - -//***************************************************************************** -// -//! Pends an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt to be pended. -//! -//! The specified interrupt is pended in the interrupt controller. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. Pending an interrupt causes the interrupt controller to -//! execute the corresponding interrupt handler at the next available time, -//! based on the current interrupt state priorities. For example, if called by -//! a higher priority interrupt handler, the specified interrupt handler is not -//! called until after the current interrupt handler has completed execution. -//! The interrupt must have been enabled for it to be called. -//! -//! \b Example: Pend a UART 0 interrupt. -//! -//! \verbatim -//! // -//! // Pend a UART 0 interrupt. -//! // -//! IntPendSet(INT_UART0); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntPendSet(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to pend. - // - if(ui32Interrupt == FAULT_NMI) - { - // - // Pend the NMI interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; - } - else if(ui32Interrupt == FAULT_PENDSV) - { - // - // Pend the PendSV interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Pend the SysTick interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; - } - else if(ui32Interrupt >= 16) - { - // - // Pend the general interrupt. - // - HWREG(g_pui32PendRegs[(ui32Interrupt - 16) / 32]) = - 1 << ((ui32Interrupt - 16) & 31); - } -} - -//***************************************************************************** -// -//! Un-pends an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt to be un-pended. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. -//! -//! The specified interrupt is un-pended in the interrupt controller. This -//! causes any previously generated interrupts that have not been handled -//! yet (due to higher priority interrupts or the interrupt not having been -//! enabled yet) to be discarded. -//! -//! \b Example: Un-pend a UART 0 interrupt. -//! -//! \verbatim -//! // -//! // Un-pend a UART 0 interrupt. -//! // -//! IntPendClear(INT_UART0); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntPendClear(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to unpend. - // - if(ui32Interrupt == FAULT_PENDSV) - { - // - // Unpend the PendSV interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Unpend the SysTick interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; - } - else if(ui32Interrupt >= 16) - { - // - // Unpend the general interrupt. - // - HWREG(g_pui32UnpendRegs[(ui32Interrupt - 16) / 32]) = - 1 << ((ui32Interrupt - 16) & 31); - } -} - -//***************************************************************************** -// -//! Sets the priority masking level -//! -//! \param ui32PriorityMask is the priority level that is masked. -//! -//! This function sets the interrupt priority masking level so that all -//! interrupts at the specified or lesser priority level are masked. Masking -//! interrupts can be used to globally disable a set of interrupts with -//! priority below a predetermined threshold. A value of 0 disables priority -//! masking. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 allows interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater are blocked. -//! -//! \note The hardware priority mechanism only looks at the upper 3 bits of the -//! priority level, so any prioritization must be performed in those bits. -//! -//! \b Example: Mask of interrupt priorities greater than or equal to 0x80. -//! -//! \verbatim -//! // -//! // Mask of interrupt priorities greater than or equal to 0x80. -//! // -//! IntPriorityMaskSet(0x80); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntPriorityMaskSet(uint32_t ui32PriorityMask) -{ - // - // Set the priority mask. - // - CPUbasepriSet(ui32PriorityMask); -} - -//***************************************************************************** -// -//! Gets the priority masking level -//! -//! This function gets the current setting of the interrupt priority masking -//! level. The value returned is the priority level such that all interrupts -//! of that and lesser priority are masked. A value of 0 means that priority -//! masking is disabled. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 allows interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater are blocked. -//! -//! The hardware priority mechanism only looks at the upper 3 bits of the -//! priority level, so any prioritization must be performed in those bits. -//! -//! \b Example: Get the current interrupt priority mask. -//! -//! \verbatim -//! // -//! // Get the current interrupt priority mask. -//! // -//! IntPriorityMaskGet(); -//! \endverbatim -//! -//! \return Returns the value of the interrupt priority level mask. -// -//***************************************************************************** -uint32_t -IntPriorityMaskGet(void) -{ - // - // Return the current priority mask. - // - return(CPUbasepriGet()); -} - -//***************************************************************************** -// -//! Triggers an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt to be triggered. -//! -//! This function performs a software trigger of an interrupt. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. The interrupt controller behaves as if the corresponding -//! interrupt line was asserted, and the interrupt is handled in the same -//! manner (meaning that it must be enabled in order to be processed, and the -//! processing is based on its priority with respect to other unhandled -//! interrupts). -//! -//! \return None. -// -//***************************************************************************** -void -IntTrigger(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT((ui32Interrupt >= 16) && (ui32Interrupt < NUM_INTERRUPTS)); - - // - // Trigger this interrupt. - // - HWREG(NVIC_SW_TRIG) = ui32Interrupt - 16; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/interrupt.h b/bsp/tm4c129x-dk/libraries/driverlib/interrupt.h deleted file mode 100644 index effb30c88a494db7cb7c24268d8d7f30edd99389..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/interrupt.h +++ /dev/null @@ -1,94 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_INTERRUPT_H__ -#define __DRIVERLIB_INTERRUPT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Macro to generate an interrupt priority mask based on the number of bits -// of priority supported by the hardware. -// -//***************************************************************************** -#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern bool IntMasterEnable(void); -extern bool IntMasterDisable(void); -extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)); -extern void IntUnregister(uint32_t ui32Interrupt); -extern void IntPriorityGroupingSet(uint32_t ui32Bits); -extern uint32_t IntPriorityGroupingGet(void); -extern void IntPrioritySet(uint32_t ui32Interrupt, - uint8_t ui8Priority); -extern int32_t IntPriorityGet(uint32_t ui32Interrupt); -extern void IntEnable(uint32_t ui32Interrupt); -extern void IntDisable(uint32_t ui32Interrupt); -extern uint32_t IntIsEnabled(uint32_t ui32Interrupt); -extern void IntPendSet(uint32_t ui32Interrupt); -extern void IntPendClear(uint32_t ui32Interrupt); -extern void IntPriorityMaskSet(uint32_t ui32PriorityMask); -extern uint32_t IntPriorityMaskGet(void); -extern void IntTrigger(uint32_t ui32Interrupt); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_INTERRUPT_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/lcd.c b/bsp/tm4c129x-dk/libraries/driverlib/lcd.c deleted file mode 100644 index 195d0ef0ba19590592d7e22545e3a38b3836ced5..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/lcd.c +++ /dev/null @@ -1,1805 +0,0 @@ -//***************************************************************************** -// -// lcd.c - Defines and Macros for the LCD Controller module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup lcd_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_ints.h" -#include "inc/hw_lcd.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" -#include "driverlib/lcd.h" -#include "driverlib/debug.h" - -//***************************************************************************** -// -// These are currently missing from hw_lcd.h and included here as a stopgap -// until the hardware header is updated. -// -//***************************************************************************** -#ifndef LCD_RASTRTIM0_MSBPPL_S -#define LCD_RASTRTIM0_MSBPPL_S 3 -#endif -#ifndef LCD_RASTRTIM2_MSBLPP_S -#define LCD_RASTRTIM2_MSBLPP_S 26 -#endif - -//***************************************************************************** -// -//! Configures the basic operating mode and clock rate for the LCD controller. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui8Mode specifies the basic operating mode to be used. -//! \param ui32PixClk specifies the desired LCD controller pixel or master -//! clock rate in Hz. -//! \param ui32SysClk specifies the current system clock rate in Hz. -//! -//! This function sets the basic operating mode of the LCD controller and also -//! its master clock. The \e ui8Mode parameter may be set to either \b -//! LCD_MODE_LIDD or \b LCD_MODE_RASTER. \b LCD_MODE_LIDD is used to select -//! LCD Interface Display Driver mode for character panels connected via -//! an asynchronous interface (CS, WE, OE, ALE, data) and \b LCD_MODE_RASTER -//! is used to communicate with panels via a synchronous video interface using -//! data and sync signals. Additionally, \b LCD_MODE_AUTO_UFLOW_RESTART may -//! be ORed with either of these modes to indicate that the hardware should -//! restart automatically if a data underflow occurs. -//! -//! The \e ui32PixClk parameter specifies the desired master clock for the -//! the LCD controller. In LIDD mode, this value controls the MCLK used in -//! communication with the display and valid values are between \e ui32SysClk -//! and \e ui32SysClk/255. In raster mode, \e ui32PixClk specifies the pixel -//! clock rate for the raster interface and valid values are between \e -//! ui32SysClk/2 and \e ui32SysClk/255. The actual clock rate set may differ -//! slightly from the desired rate due to the fact that only integer dividers -//! are supported. The rate set will, however, be no higher than the requested -//! value. -//! -//! The \e ui32SysClk parameter provides the current system clock rate and is -//! used to allow the LCD controller clock rate divisor to be correctly set -//! to give the desired \e ui32PixClk rate. -//! -//! \return Returns the actual LCD controller pixel clock or MCLK rate set. -// -//***************************************************************************** -uint32_t -LCDModeSet(uint32_t ui32Base, uint8_t ui8Mode, uint32_t ui32PixClk, - uint32_t ui32SysClk) -{ - uint32_t ui32Div; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui8Mode & ~(LCD_MODE_RASTER | LCD_MODE_LIDD | - LCD_MODE_AUTO_UFLOW_RESTART)) == 0); - - // - // Enable clocks to the LCD controller submodules. - // - HWREG(ui32Base + LCD_O_CLKEN) = (LCD_CLKEN_DMA | LCD_CLKEN_CORE | - LCD_CLKEN_LIDD); - - // - // Determine the clock divider to use to get as close as possible to the - // desired pixel clock. Note that we set the division up so that we - // round the divisor up and ensure that the clock used is never faster - // than the requested rate. - // - ui32Div = (ui32SysClk + (ui32PixClk - 1)) / ui32PixClk; - - // - // Check that the calculated value is valid. - // - ASSERT(ui32Div); - ASSERT(ui32Div < 256); - ASSERT(!((ui8Mode & LCD_MODE_RASTER) && (ui32Div < 2))); - - // - // Write the LCDCTL register to set the mode. - // - HWREG(ui32Base + LCD_O_CTL) = (uint32_t)ui8Mode | - (ui32Div << LCD_CTL_CLKDIV_S); - - // - // Return the selected clock rate. Finding ui32Div set to 0 should not - // happen unless someone passed pathological arguments and builds without - // the ASSERTS, but we guard against it just in case. - // - return(ui32Div ? (ui32SysClk / ui32Div) : ui32SysClk); -} - -//***************************************************************************** -// -//! Resets one or more of the LCD controller clock domains. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32Clocks defines the subset of clock domains to be reset. -//! -//! This function allows sub-modules of the LCD controller to be reset under -//! software control. The \e ui32Clocks parameter is the logical OR of the -//! following clocks: -//! -//! - \b LCD_CLOCK_MAIN causes the entire LCD controller module to be reset. -//! - \b LCD_CLOCK_DMA causes the DMA controller submodule to be reset. -//! - \b LCD_CLOCK_LIDD causes the LIDD submodule to be reset. -//! - \b LCD_CLOCK_CORE causes the core module, including the raster logic to -//! be reset. -//! -//! In all cases, LCD controller register values are preserved across these -//! resets. -//! -//! \return None. -// -//***************************************************************************** -void -LCDClockReset(uint32_t ui32Base, uint32_t ui32Clocks) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32Clocks & ~(LCD_CLOCK_MAIN | LCD_CLOCK_LIDD | LCD_CLOCK_DMA | - LCD_CLOCK_CORE))); - - // - // Reset the required LCD controller sub-module(s). - // - HWREG(LCD0_BASE + 0x70) = ui32Clocks; - - // - // Wait a while. - // - SysCtlDelay(10); - - // - // Remove software reset. - // - HWREG(LCD0_BASE + 0x70) = 0x00000000; - - // - // Wait a while. - // - SysCtlDelay(10); -} - -//***************************************************************************** -// -//! Sets the LCD controller communication parameters when in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32Config defines the display interface configuration. -//! -//! This function is used when the LCD controller is configured in LIDD -//! mode and specifies the configuration of the interface between the -//! controller and the display panel. The \e ui32Config parameter is -//! comprised of one of the following modes: -//! -//! - \b LIDD_CONFIG_SYNC_MPU68 selects Sync MPU68 mode. LCDCP = EN, LCDLP = -//! DIR, LCDFP = ALE, LCDAC = CS0, LCDMCLK = MCLK. -//! - \b LIDD_CONFIG_ASYNC_MPU68 selects Async MPU68 mode. LCDCP = EN, LCDLP = -//! DIR, LCDFP = ALE, LCDAC = CS0, LCDMCLK = CS1. -//! - \b LIDD_CONFIG_SYNC_MPU80 selects Sync MPU80 mode. LCDCP = RS, LCDLP = -//! WS, LCDFP = ALE, LCDAC = CS0, LCDMCLK = MCLK. -//! - \b LIDD_CONFIG_ASYNC_MPU80 selects Async MPU80 mode. LCDCP = RS, LCDLP = -//! WS, LCDFP = ALE, LCDAC = CS0, LCDMCLK = CS1. -//! - \b LIDD_CONFIG_ASYNC_HITACHI selects Hitachi (async) mode. LCDCP = N/C, -//! LCDLP = DIR, LCDFP = ALE, LCDAC = E0, LCDMCLK = E1. -//! -//! Additional flags may be ORed into \e ui32Config to control the polarities -//! of various control signals: -//! -//! - \b LIDD_CONFIG_INVERT_ALE - Address Latch Enable (ALE) polarity control. -//! By default, ALE is active low. If this flag is set, it becomes active -//! high. -//! - \b LIDD_CONFIG_INVERT_RS_EN - Read Strobe/Enable polarity control. By -//! default, RS is active low and Enable is active high. If this flag is set, -//! RS becomes active high and Enable active low. -//! - \b LIDD_CONFIG_INVERT_WS_DIR - Write Strobe/Direction polarity control. -//! By default, WS is active low and Direction write low/read high. If this -//! flag is set, WS becomes active high and Direction becomes write high/read -//! low. -//! - \b LIDD_CONFIG_INVERT_CS0 - Chip Select 0/Enable 0 polarity control. By -//! default, CS0 and E0 are active high. If this flag is set, they become -//! active low. -//! - \b LIDD_CONFIG_INVERT_CS1 - Chip Select 1/Enable 1 polarity control. By -//! default, CS1 and E1 are active high. If this flag is set, they become -//! active low. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32Config & ~(LIDD_CONFIG_SYNC_MPU68 | LIDD_CONFIG_ASYNC_MPU68 | - LIDD_CONFIG_SYNC_MPU80 | LIDD_CONFIG_ASYNC_MPU80 | - LIDD_CONFIG_ASYNC_HITACHI | - LIDD_CONFIG_INVERT_ALE | - LIDD_CONFIG_INVERT_RS_EN | - LIDD_CONFIG_INVERT_WS_DIR | - LIDD_CONFIG_INVERT_CS0 | LIDD_CONFIG_INVERT_CS1))); - - // - // Write the LIDD Control Register. - // - HWREG(ui32Base + LCD_O_LIDDCTL) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the LCD controller interface timing when in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select whose timings are to be set. -//! \param pTiming points to a structure containing the desired timing -//! parameters. -//! -//! This function is used in LIDD mode to set the setup, strobe and hold times -//! for the various interface control signals. Independent timings are stored -//! for each of the two supported chip selects offered by the LCD controller. -//! -//! For a definition of the timing parameters required, see the definition of -//! tLCDIDDTiming. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None -// -//***************************************************************************** -void -LCDIDDTimingSet(uint32_t ui32Base, uint32_t ui32CS, - const tLCDIDDTiming *pTiming) -{ - uint32_t ui32Val; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - ASSERT(pTiming); - ASSERT(pTiming->ui8WSSetup < 32); - ASSERT(pTiming->ui8WSDuration && (pTiming->ui8WSDuration < 64)); - ASSERT(pTiming->ui8WSHold && (pTiming->ui8WSHold < 16)); - ASSERT(pTiming->ui8RSSetup < 32); - ASSERT(pTiming->ui8RSDuration && (pTiming->ui8RSDuration < 64)); - ASSERT(pTiming->ui8RSHold && (pTiming->ui8RSHold < 16)); - ASSERT(pTiming->ui8DelayCycles && (pTiming->ui8DelayCycles < 5)); - - // - // Convert the timings provided into a value ready for the register. - // - ui32Val = - (((uint32_t)(pTiming->ui8WSSetup) << LCD_LIDDCS0CFG_WRSU_S) | - ((uint32_t)(pTiming->ui8WSDuration) << LCD_LIDDCS0CFG_WRDUR_S) | - ((uint32_t)(pTiming->ui8WSHold) << LCD_LIDDCS0CFG_WRHOLD_S) | - ((uint32_t)(pTiming->ui8RSSetup) << LCD_LIDDCS0CFG_RDSU_S) | - ((uint32_t)(pTiming->ui8RSDuration) << LCD_LIDDCS0CFG_RDDUR_S) | - ((uint32_t)(pTiming->ui8RSHold) << LCD_LIDDCS0CFG_RDHOLD_S) | - ((uint32_t)(pTiming->ui8DelayCycles - 1) << LCD_LIDDCS0CFG_GAP_S)); - - // - // Write the appropriate LCD LIDD CS configuration register. - // - if(!ui32CS) - { - HWREG(ui32Base + LCD_O_LIDDCS0CFG) = ui32Val; - } - else - { - HWREG(ui32Base + LCD_O_LIDDCS1CFG) = ui32Val; - } -} - -//***************************************************************************** -// -//! Disables internal DMA operation when the LCD controller is in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! -//! When the LCD controller is operating in LCD Interface Display Driver mode, -//! this function must be called after completion of a DMA transaction and -//! before calling LCDIDDCommandWrite(), LCDIDDDataWrite(), LCDIDDStatusRead(), -//! LCDIDDIndexedWrite(), LCDIDDIndexedRead() or LCDIDDDataRead() to disable -//! DMA mode and allow CPU-initiated transactions to the display. -//! -//! \note LIDD DMA mode is enabled automatically when LCDIDDDMAWrite() is -//! called. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDDMADisable(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Disable DMA. - // - HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMAEN; -} - -//***************************************************************************** -// -//! Writes a command to the display when the LCD controller is in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! \param ui16Cmd is the 16-bit command word to write. -//! -//! This function writes a 16-bit command word to the display when the LCD -//! controller is in LIDD mode. A command write occurs with the ALE signal -//! active. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDCommandWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Cmd) -{ - uint32_t ui32Reg; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the register to write based on the CS value supplied. - // - ui32Reg = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; - - // - // Write the command/address to the register. - // - HWREG(ui32Base + ui32Reg) = ui16Cmd; -} - -//***************************************************************************** -// -//! Writes a data value to the display when the LCD controller is in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! \param ui16Data is the 16-bit data word to write. -//! -//! This function writes a 16-bit data word to the display when the LCD -//! controller is in LIDD mode. A data write occurs with the ALE signal -//! inactive. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDDataWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Data) -{ - uint32_t ui32Reg; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the register to write based on the CS value supplied. - // - ui32Reg = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; - - // - // Write the data value to the register. - // - HWREG(ui32Base + ui32Reg) = ui16Data; -} - -//***************************************************************************** -// -//! Writes data to a given display register when the LCD controller is in LIDD -//! mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! \param ui16Addr is the address of the display register to write. -//! \param ui16Data is the data to write. -//! -//! This function writes a 16-bit data word to a register in the display when -//! the LCD controller is in LIDD mode and configured to use either the -//! Motorola (\b LIDD_CONFIG_SYNC_MPU68 or \b LIDD_CONFIG_ASYNC_MPU68) or -//! Intel (\b LIDD_CONFIG_SYNC_MPU80 or \b LIDD_CONFIG_ASYNC_MPU80) modes -//! that employ an external address latch. -//! -//! When configured in Hitachi mode (\b LIDD_CONFIG_ASYNC_HITACHI), this -//! function should not be used. In this case the functions -//! LCDIDDCommandWrite() and LCDIDDDataWrite() may be used to transfer -//! command and data bytes to the panel. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDIndexedWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Addr, - uint16_t ui16Data) -{ - uint32_t ui32Addr; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the address register to write. - // - ui32Addr = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; - - // - // Write the address. - // - HWREG(ui32Base + ui32Addr) = ui16Addr; - - // - // Determine the data register to write. - // - ui32Addr = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; - - // - // Write the data. - // - HWREG(ui32Base + ui32Addr) = ui16Data; -} - -//***************************************************************************** -// -//! Reads a status word from the display when the LCD controller is in LIDD -//! mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! -//! This function reads the 16-bit status word from the display when the LCD -//! controller is in LIDD mode. A status read occurs with the ALE signal -//! active. If the interface is configured in Hitachi mode (\b -//! LIDD_CONFIG_ASYNC_HITACHI), this operation corresponds to a command mode -//! read. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return Returns the status word read from the display panel. -// -//***************************************************************************** -uint16_t -LCDIDDStatusRead(uint32_t ui32Base, uint32_t ui32CS) -{ - uint32_t ui32Reg; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the register to read based on the CS value supplied. - // - ui32Reg = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; - - // - // Read the relevant status register. - // - return((uint16_t)HWREG(ui32Base + ui32Reg)); -} - -//***************************************************************************** -// -//! Reads a data word from the display when the LCD controller is in LIDD -//! mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! -//! This function reads the 16-bit data word from the display when the LCD -//! controller is in LIDD mode. A data read occurs with the ALE signal -//! inactive. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return Returns the status word read from the display panel. -// -//***************************************************************************** -uint16_t -LCDIDDDataRead(uint32_t ui32Base, uint32_t ui32CS) -{ - uint32_t ui32Reg; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the register to read based on the CS value supplied. - // - ui32Reg = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; - - // - // Read the relevant data register. - // - return((uint16_t)HWREG(ui32Base + ui32Reg)); -} - -//***************************************************************************** -// -//! Reads a given display register when the LCD controller is in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! \param ui16Addr is the address of the display register to read. -//! -//! This function reads a 16-bit word from a register in the display when -//! the LCD controller is in LIDD mode and configured to use either the -//! Motorola (\b LIDD_CONFIG_SYNC_MPU68 or \b LIDD_CONFIG_ASYNC_MPU68) or -//! Intel (\b LIDD_CONFIG_SYNC_MPU80 or \b LIDD_CONFIG_ASYNC_MPU80) modes -//! that employ an external address latch. -//! -//! When configured in Hitachi mode (\b LIDD_CONFIG_ASYNC_HITACHI), this -//! function should not be used. In this case, the functions -//! LCDIDDStatusRead() and LCDIDDDataRead() may be used to read status -//! and data bytes from the panel. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None. -// -//***************************************************************************** -uint16_t -LCDIDDIndexedRead(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Addr) -{ - uint32_t ui32Addr; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the address register to write. - // - ui32Addr = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; - - // - // Write the address. - // - HWREG(ui32Base + ui32Addr) = ui16Addr; - - // - // Determine the data register to read. - // - ui32Addr = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; - - // - // Return the data read. - // - return((uint16_t)HWREG(ui32Base + ui32Addr)); -} - -//***************************************************************************** -// -//! Writes a block of data to the display using DMA when the LCD controller is -//! in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! \param pui32Data is the address of the first 16-bit word to write. This -//! address must be aligned on a 32-bit word boundary. -//! \param ui32Count is the number of 16-bit words to write. This value must -//! be a multiple of 2. -//! -//! This function writes a block of 16-bit data words to the display using -//! DMA. It is only valid when the LCD controller is in LIDD mode. -//! Completion of the DMA transfer is signaled by the \b -//! LCD_INT_DMA_DONE interrupt. -//! -//! This function enables DMA mode prior to starting the transfer. The -//! caller is responsible for ensuring that any earlier DMA transfer has -//! completed before initiating another transfer. -//! -//! During the time that DMA is enabled, none of the other LCD LIDD data -//! transfer functions may be called. When the DMA transfer is complete and -//! the application wishes to use the CPU to communicate with the display, -//! LCDIDDDMADisable() must be called to disable DMA access prior to calling -//! LCDIDDCommandWrite(), LCDIDDDataWrite(), LCDIDDStatusRead(), -//! LCDIDDIndexedWrite(), LCDIDDIndexedRead() or LCDIDDDataRead(). -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDDMAWrite(uint32_t ui32Base, uint32_t ui32CS, const uint32_t *pui32Data, - uint32_t ui32Count) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - ASSERT(!((uint32_t)pui32Data & 3)); - ASSERT(!(ui32Count & 1)); - - // - // Make sure DMA is disabled so that enabling it triggers this new - // transfer. - // - HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMAEN; - - // - // Set up the transfer. Note that the ceiling register must contain the - // address of the last word which contains data we want transfered and NOT - // the first location after the data we want written. - // - HWREG(ui32Base + LCD_O_DMABAFB0) = (uint32_t)pui32Data; - HWREG(ui32Base + LCD_O_DMACAFB0) = ((uint32_t)pui32Data + - (ui32Count * 2) - 4); - - // - // Tell the controller which CS to use for the DMA transaction. - // - if(!ui32CS) - { - // - // Use CS0. - // - HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMACS; - } - else - { - // - // Use CS1. - // - HWREG(ui32Base + LCD_O_LIDDCTL) |= LCD_LIDDCTL_DMACS; - } - - // - // Enable the DMA engine and start the transaction. - // - HWREG(ui32Base + LCD_O_LIDDCTL) |= LCD_LIDDCTL_DMAEN; -} - -//***************************************************************************** -// -//! Sets the LCD controller interface timing when in raster mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32Config specifies properties of the raster interface and the -//! attached display panel. -//! \param ui8PalLoadDelay specifies the number of system clocks to wait -//! between each 16 halfword (16-bit) burst when loading the palette from -//! SRAM into the internal palette RAM of the controller. -//! -//! This function configures the basic operating mode of the raster interface -//! and specifies the type of panel that the controller is to drive. -//! -//! The \e ui32Config parameter must be defined as one of the following to -//! select the required target panel type and output pixel format: -//! -//! - \b RASTER_FMT_ACTIVE_24BPP_PACKED selects an active matrix display -//! and uses a packed 24-bit per pixel packet frame buffer where 4 pixels -//! are described within 3 consecutive 32-bit words. -//! - \b RASTER_FMT_ACTIVE_24BPP_UNPACKED selects an active matrix display -//! and uses an unpacked 24-bit per pixel packet frame buffer where each -//! 32-bit word contains a single pixel and 8 bits of padding. -//! - \b RASTER_FMT_ACTIVE_16BPP selects an active matrix display -//! and uses a 16-bit per pixel frame buffer with 2 pixels in each 32-bit -//! word. -//! - \b RASTER_FMT_ACTIVE_PALETTIZED_12BIT selects an active matrix display -//! and uses a 1, 2, 4 or 8bpp frame buffer with palette lookup. Output color -//! data is described in 12-bit format using bits 11:0 of the data bus. The -//! frame buffer pixel format is defined by the value passed in the \e ui32Type -//! parameter to LCDRasterPaletteSet(). -//! - \b RASTER_FMT_ACTIVE_PALETTIZED_16BIT selects an active matrix display -//! and uses a 1, 2, 4 or 8bpp frame buffer with palette lookup. Output color -//! data is described in 16-bit 5:6:5 format. The frame buffer pixel format is -//! defined by the value passed in the \e ui32Type parameter to -//! LCDRasterPaletteSet(). -//! - \b RASTER_FMT_PASSIVE_MONO_4PIX selects a monochrome, passive matrix -//! display that outputs 4 pixels on each pixel clock. -//! - \b RASTER_FMT_PASSIVE_MONO_8PIX selects a monochrome, passive matrix -//! display that outputs 8 pixels on each pixel clock. -//! - \b RASTER_FMT_PASSIVE_COLOR_12BIT selects a passive matrix display -//! and uses a 12bpp frame buffer. The palette is bypassed and 12-bit pixel -//! data is sent to the grayscaler for the display. -//! - \b RASTER_FMT_PASSIVE_COLOR_16BIT selects a passive matrix display -//! and uses a 16bpp frame buffer with pixels in 5:6:5 format. Only the 4 -//! most significant bits of each color component are sent to the grayscaler -//! for the display. -//! -//! Additionally, the following flags may be ORed into \e ui32Config: -//! -//! - \b RASTER_ACTVID_DURING_BLANK sets Actvid to toggle during vertical -//! blanking. -//! - \b RASTER_NIBBLE_MODE_ENABLED enables nibble mode. This parameter works -//! with \b RASTER_READ_ORDER_REVERSED to determine how 1, 2 and 4bpp pixels -//! are extracted from words read from the frame buffer. If specified, words -//! read from the frame buffer are byte swapped prior to individual pixels -//! being parsed from them. -//! - \b RASTER_LOAD_DATA_ONLY tells the controller to read only pixel data -//! from the frame buffer and to use the last palette read. No palette load -//! is performed. -//! - \b RASTER_LOAD_PALETTE_ONLY tells the controller to read only the palette -//! data from the frame buffer. -//! - \b RASTER_READ_ORDER_REVERSED when using 1, 2, 4 and 8bpp frame buffers, -//! this option reverses the order in which frame buffer words are parsed. -//! When this option is specified, the leftmost pixel in a word is taken from -//! the most significant bits. When absent, the leftmost pixel is parsed from -//! the least significant bits. -//! -//! If the LCD controller's raster engine is enabled when this function is -//! called, it is disabled as a result of the call. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint8_t ui8PalLoadDelay) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32Config & ~(RASTER_FMT_ACTIVE_24BPP_PACKED | - RASTER_FMT_ACTIVE_24BPP_UNPACKED | - RASTER_FMT_ACTIVE_PALETTIZED_12BIT | - RASTER_FMT_ACTIVE_PALETTIZED_16BIT | - RASTER_FMT_PASSIVE_MONO_4PIX | - RASTER_FMT_PASSIVE_MONO_8PIX | - RASTER_FMT_PASSIVE_PALETTIZED | - RASTER_FMT_PASSIVE_COLOR_12BIT | - RASTER_FMT_PASSIVE_COLOR_16BIT | - RASTER_ACTVID_DURING_BLANK | - RASTER_NIBBLE_MODE_ENABLED | - RASTER_LOAD_DATA_ONLY | - RASTER_LOAD_PALETTE_ONLY | - RASTER_READ_ORDER_REVERSED))); - - // - // Write the raster control register. - // - HWREG(ui32Base + LCD_O_RASTRCTL) = (ui32Config | - ((uint32_t)ui8PalLoadDelay << - LCD_RASTRCTL_REQDLY_S)); -} - -//***************************************************************************** -// -//! Sets the LCD controller interface timing when in raster mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param pTiming points to a structure containing the desired timing -//! parameters. -//! -//! This function is used in raster mode to set the panel size and sync timing -//! parameters. -//! -//! For a definition of the timing parameters required, see the definition of -//! tLCDRasterTiming. -//! -//! \return None -// -//***************************************************************************** -void -LCDRasterTimingSet(uint32_t ui32Base, const tLCDRasterTiming *pTiming) -{ - uint32_t ui32T0, ui32T1, ui32T2; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(pTiming); - ASSERT(!(pTiming->ui32Flags & ~(RASTER_TIMING_SYNCS_OPPOSITE_PIXCLK | - RASTER_TIMING_SYNCS_ON_FALLING_PIXCLK | - RASTER_TIMING_SYNCS_ON_RISING_PIXCLK | - RASTER_TIMING_ACTIVE_LOW_OE | - RASTER_TIMING_ACTIVE_LOW_PIXCLK | - RASTER_TIMING_ACTIVE_LOW_HSYNC | - RASTER_TIMING_ACTIVE_LOW_VSYNC))); - ASSERT(pTiming->ui16PanelWidth && (pTiming->ui16PanelWidth <= 2048) && - ((pTiming->ui16PanelWidth % 16) == 0)); - ASSERT(pTiming->ui16PanelHeight && (pTiming->ui16PanelHeight <= 2048)); - ASSERT(pTiming->ui16HFrontPorch && (pTiming->ui16HFrontPorch <= 1024)); - ASSERT(pTiming->ui16HBackPorch && (pTiming->ui16HBackPorch <= 1024)); - ASSERT(pTiming->ui16HSyncWidth && (pTiming->ui16HSyncWidth <= 1024)); - ASSERT(pTiming->ui8VSyncWidth && (pTiming->ui8VSyncWidth <= 64)); - - // - // Construct the values we need for the three raster timing registers. - // - ui32T0 = ((uint32_t)((pTiming->ui16HBackPorch - 1) & 0xFF) << - LCD_RASTRTIM0_HBP_S) | - ((uint32_t)((pTiming->ui16HFrontPorch - 1) & 0xFF) << - LCD_RASTRTIM0_HFP_S) | - ((uint32_t)((pTiming->ui16HSyncWidth - 1) & 0x3F) << - LCD_RASTRTIM0_HSW_S) | - (((uint32_t)((pTiming->ui16PanelWidth - 1) & 0x3F0) >> 4) << - LCD_RASTRTIM0_PPL_S) | - (((uint32_t)((pTiming->ui16PanelWidth - 1) & 0x400) >> 10) << - LCD_RASTRTIM0_MSBPPL_S); - ui32T1 = ((uint32_t)pTiming->ui8VBackPorch << LCD_RASTRTIM1_VBP_S) | - ((uint32_t)pTiming->ui8VFrontPorch << LCD_RASTRTIM1_VFP_S) | - ((uint32_t)((pTiming->ui8VSyncWidth - 1) & 0x3F) << - LCD_RASTRTIM1_VSW_S) | - ((uint32_t)(pTiming->ui16PanelHeight - 1) & 0x3FF) << - LCD_RASTRTIM1_LPP_S; - ui32T2 = pTiming->ui32Flags | - ((((pTiming->ui16HSyncWidth - 1) & 0x3C0) >> 6) << - LCD_RASTRTIM2_HSW_S) | - ((((pTiming->ui16PanelHeight - 1) & 0x400) >> 10) << - LCD_RASTRTIM2_MSBLPP_S) | - ((((pTiming->ui16HBackPorch - 1) & 0x300) >> 8) << - LCD_RASTRTIM2_MSBHBP_S) | - ((((pTiming->ui16HFrontPorch - 1) & 0x300) >> 8) << - LCD_RASTRTIM2_MSBHFP_S) | - (pTiming->ui8ACBiasLineCount << LCD_RASTRTIM2_ACBF_S); - - // - // Write the timing registers, taking care to preserve any existing value - // in the AC Bias interrupt field of RASTRTIM2. - // - HWREG(ui32Base + LCD_O_RASTRTIM0) = ui32T0; - HWREG(ui32Base + LCD_O_RASTRTIM1) = ui32T1; - HWREG(ui32Base + LCD_O_RASTRTIM2) = (HWREG(ui32Base + LCD_O_RASTRTIM2) & - LCD_RASTRTIM2_ACBI_M) | ui32T2; -} - -//***************************************************************************** -// -//! Sets the number of AC bias pin transitions per interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8Count is the number of AC bias pin transitions to count before -//! the AC bias count interrupt is asserted. Valid values are from 0 to 15. -//! -//! This function is used to set the number of AC bias transitions between -//! each AC bias count interrupt (\b LCD_INT_AC_BIAS_CNT). If \e ui8Count is -//! 0, no AC bias count interrupt is generated. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterACBiasIntCountSet(uint32_t ui32Base, uint8_t ui8Count) -{ - uint32_t ui32Val; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(ui8Count < 16); - - // - // Get the existing raster timing 2 register value and mask in the new - // AC Bias interrupt count. - // - ui32Val = HWREG(ui32Base + LCD_O_RASTRTIM2); - ui32Val &= ~LCD_RASTRTIM2_ACBI_M; - ui32Val |= ((ui8Count << LCD_RASTRTIM2_ACBI_S) & LCD_RASTRTIM2_ACBI_M); - - // - // Write the new value back to the register. - // - HWREG(ui32Base + LCD_O_RASTRTIM2) = ui32Val; -} - -//***************************************************************************** -// -//! Enables the raster output. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function enables the LCD controller raster output and starts -//! displaying the content of the current frame buffer on the attached panel. -//! Prior to enabling the raster output, LCDModeSet(), LCDRasterConfigSet(), -//! LCDDMAConfigSet(), LCDRasterTimingSet(), LCDRasterPaletteSet() and -//! LCDRasterFrameBufferSet() must have been called. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterEnable(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Reset the module prior to starting the raster. This is required to - // ensure correct operation of the raster engine. - // - LCDClockReset(ui32Base, LCD_CLOCK_MAIN); - - // - // Enable the raster engine. - // - HWREG(ui32Base + LCD_O_RASTRCTL) |= LCD_RASTRCTL_LCDEN; -} - -//***************************************************************************** -// -//! Determines whether or not the raster output is currently enabled. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be used to query whether or not the raster output is -//! currently enabled. -//! -//! \return Returns \b true if the raster is enabled or \b false if it is -//! disabled. -// -//***************************************************************************** -bool -LCDRasterEnabled(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Return the current raster engine status. - // - return((HWREG(ui32Base + LCD_O_RASTRCTL) & LCD_RASTRCTL_LCDEN) ? - true : false); -} - -//***************************************************************************** -// -//! Disables the raster output. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function disables the LCD controller raster output and stops driving -//! the attached display. -//! -//! \note Once disabled, the raster engine continues to scan data until the -//! end of the current frame. If the display is to be re-enabled, wait until -//! after the final \b LCD_INT_RASTER_FRAME_DONE has been received, indicating -//! that the raster engine has stopped. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterDisable(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Disable the raster engine. - // - HWREG(ui32Base + LCD_O_RASTRCTL) &= ~LCD_RASTRCTL_LCDEN; -} - -//***************************************************************************** -// -//! Sets the position and size of the subpanel on the raster display. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Flags may be either \b LCD_SUBPANEL_AT_TOP to show frame buffer -//! image data in the top portion of the display and default color in the -//! bottom portion, or \b LCD_SUBPANEL_AT_BOTTOM to show image data at the -//! bottom of the display and default color at the top. -//! \param ui32BottomLines defines the number of lines comprising the bottom -//! portion of the display. If \b LCD_SUBPANEL_AT_TOP is set in \e ui32Flags, -//! these lines contain the default pixel color when the subpanel is -//! enabled, otherwise they contain image data. -//! \param ui32DefaultPixel is the 24-bit RGB color to show in the portion of -//! the display not configured to show image data. -//! -//! The LCD controller provides a feature that allows a portion of the display -//! to be filled with a default color rather than image data from the frame -//! buffer. This feature reduces SRAM bandwidth requirements because no data -//! is fetched for lines containing the default color. This feature is only -//! available when the LCD controller is in raster mode and configured to drive -//! an active matrix display. -//! -//! The subpanel area containing image data from the frame buffer may be -//! positioned either at the top or bottom of the display as controlled by -//! the value of \e ui32Flags. The height of the bottom portion of the display -//! is defined by \e ui32BottomLines. -//! -//! When a subpanel is configured, the application must also reconfigure the -//! frame buffer to ensure that it contains the correct number of lines for -//! the subpanel size in use. This configuration can be achieved by calling -//! LCDRasterFrameBufferSet() with the \e ui32NumBytes parameter set -//! appropriately to describe the required number of active video lines in -//! the subpanel area. -//! -//! The subpanel display mode is not enabled using this function. To enable -//! the subpanel once it has been configured, call LCDRasterSubPanelEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterSubPanelConfigSet(uint32_t ui32Base, uint32_t ui32Flags, - uint32_t ui32BottomLines, uint32_t ui32DefaultPixel) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32Flags == LCD_SUBPANEL_AT_TOP) || - (ui32Flags == LCD_SUBPANEL_AT_BOTTOM)); - ASSERT(ui32BottomLines && (ui32BottomLines <= 2048)); - - // - // Adjust the line count into the 0-2047 range. - // - ui32BottomLines--; - - // - // Set the first subpanel configuration register, taking care to leave the - // subpanel enabled if it already was. - // - HWREG(ui32Base + LCD_O_RASTRSUBP1) = (HWREG(ui32Base + LCD_O_RASTRSUBP1) & - LCD_RASTRSUBP1_SPEN) | ui32Flags | - ((ui32DefaultPixel & 0xFFFF) << - LCD_RASTRSUBP1_DPDLSB_S) | - ((ui32BottomLines << - LCD_RASTRSUBP1_LPPT_S) & - LCD_RASTRSUBP1_LPPT_M); - - // - // Set the second subpanel configuration register. - // - HWREG(ui32Base + LCD_O_RASTRSUBP2) = - ((ui32DefaultPixel >> 16) & LCD_RASTRSUBP2_DPDMSB_M) | - (((ui32BottomLines >> LCD_RASTRSUBP1_LPPT_S) & 1) << 8); -} - -//***************************************************************************** -// -//! Enables subpanel display mode. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function enables subpanel display mode and displays a default color -//! rather than image data in the number of lines and at the position specified -//! by a previous call to LCDRasterSubPanelConfigSet(). Prior to calling -//! LCDRasterSubPanelEnable(), the frame buffer should have been reconfigured -//! to match the desired subpanel size using a call to -//! LCDRasterFrameBufferSet(). -//! -//! Subpanel display is only possible when the LCD controller is in raster -//! mode and is configured to drive an active matrix display. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterSubPanelEnable(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Enable the subpanel. - // - HWREG(ui32Base + LCD_O_RASTRSUBP1) |= LCD_RASTRSUBP1_SPEN; -} - -//***************************************************************************** -// -//! Disables subpanel display mode. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function disables subpanel display mode and reverts to showing the -//! entire frame buffer image on the display. After the subpanel is disabled, -//! the frame buffer size must be reconfigured to match the full dimensions of -//! the display area by calling LCDRasterFrameBufferSet() with an appropriate -//! value for the \e ui32NumBytes parameter. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterSubPanelDisable(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Disable the subpanel. - // - HWREG(ui32Base + LCD_O_RASTRSUBP1) &= ~LCD_RASTRSUBP1_SPEN; -} - -//***************************************************************************** -// -//! Configures the LCD controller's internal DMA engine. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Config provides flags defining the desired DMA parameters. -//! -//! This function is used to configure the DMA engine within the LCD -//! controller. This engine is responsible for performing bulk data transfers -//! to the display when in LIDD mode or for transferring palette and pixel data -//! from SRAM to the display panel when in raster mode. -//! -//! The \e ui32Config parameter is a logical OR of various flags. It must -//! contain one value from each of the following groups. -//! -//! The first group of flags set the number of words that have to be in the -//! FIFO before it signals that it is ready: -//! -//! - \b LCD_DMA_FIFORDY_8_WORDS -//! - \b LCD_DMA_FIFORDY_16_WORDS -//! - \b LCD_DMA_FIFORDY_32_WORDS -//! - \b LCD_DMA_FIFORDY_64_WORDS -//! - \b LCD_DMA_FIFORDY_128_WORDS -//! - \b LCD_DMA_FIFORDY_256_WORDS -//! - \b LCD_DMA_FIFORDY_512_WORDS -//! -//! The second group of flags set the number of 32-bit words in each DMA burst -//! transfer: -//! -//! - \b LCD_DMA_BURST_1 -//! - \b LCD_DMA_BURST_2 -//! - \b LCD_DMA_BURST_4 -//! - \b LCD_DMA_BURST_8 -//! - \b LCD_DMA_BURST_16 -//! -//! The final group of flags set internal byte lane controls and allow byte -//! swapping within the DMA engine. The label represents the output byte order -//! for an input 32-bit word ordered ``0123''. -//! -//! - \b LCD_DMA_BYTE_ORDER_0123 -//! - \b LCD_DMA_BYTE_ORDER_1023 -//! - \b LCD_DMA_BYTE_ORDER_3210 -//! - \b LCD_DMA_BYTE_ORDER_2301 -//! -//! Additionally, \b LCD_DMA_PING_PONG may be specified. This flag configures -//! the controller to operate in double-buffered mode. When data is scanned -//! out from the first frame buffer, the DMA engine immediately moves to -//! the second frame buffer and scans from there before moving back to the -//! first. If this flag is clear, the DMA engine uses a single frame buffer, -//! restarting the scan from the beginning of the buffer each time it completes -//! a frame. -//! -//! \note DMA burst size \b LCD_DMA_BURST_16 should be set when using frame -//! buffers in external, EPI-connected memory. Using a smaller burst size in -//! this case is likely to result in occasional FIFO underflows and associated -//! display glitches. -//! -//! \return None. -// -//***************************************************************************** -void -LCDDMAConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32Config & ~(LCD_DMACTL_FIFORDY_M | LCD_DMACTL_BURSTSZ_M | - LCD_DMACTL_BYTESWAP | LCD_DMACTL_BIGDEND | - LCD_DMACTL_FMODE))); - - // - // Write the DMA control register. - // - HWREG(ui32Base + LCD_O_DMACTL) = ui32Config; -} - -//***************************************************************************** -// -//! Initializes the color palette in a frame buffer. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Type specifies the type of pixel data to be held in the frame -//! buffer and also the format of the source color values passed. -//! \param pui32Addr points to the start of the frame buffer into which the -//! palette information is to be written. -//! \param pui32SrcColors points to the first color value that is to be -//! written into the frame buffer palette. -//! \param ui32Start specifies the index of the first color in the palette -//! to update. -//! \param ui32Count specifies the number of source colors to be copied into -//! the frame buffer palette. -//! -//! This function is used to initialize the color palette stored at the -//! beginning of a frame buffer. It writes the relevant pixel type into the -//! first entry of the frame buffer and copies the requested number of colors -//! from a source buffer into the palette starting at the required index, -//! optionally converting them from 24-bit color format into the 12-bit format -//! used by the LCD controller. -//! -//! \e ui32Type must be set to one of the following values to indicate the -//! type of frame buffer for which the palette is being initialized: -//! -//! - \b LCD_PALETTE_TYPE_1BPP indicates a 1 bit per pixel -//! (monochrome) frame buffer. This format requires a 2 entry palette. -//! - \b LCD_PALETTE_TYPE_2BPP indicates a 2 bit per pixel frame -//! buffer. This format requires a 4 entry palette. -//! - \b LCD_PALETTE_TYPE_4BPP indicates a 4 bit per pixel frame -//! buffer. This format requires a 4 entry palette. -//! - \b LCD_PALETTE_TYPE_8BPP indicates an 8 bit per pixel frame -//! buffer. This format requires a 256 entry palette. -//! - \b LCD_PALETTE_TYPE_DIRECT indicates a direct color (12, 16 or -//! 24 bit per pixel). The color palette is not used in these modes, but the -//! frame buffer type must still be initialized to ensure that the hardware -//! uses the correct pixel type. When this value is used, the format of the -//! pixels in the frame buffer is defined by the \e ui32Config parameter -//! previously passed to LCDRasterConfigSet(). -//! -//! Optionally, the \b LCD_PALETTE_SRC_24BIT flag may be ORed into \e ui32Type -//! to indicate that the supplied colors in the \e pui32SrcColors array are in -//! the 24-bit format as used by the TivaWare Graphics Library with one color -//! stored in each 32-bit word. In this case, the colors read from the source -//! array are converted to the 12-bit format used by the LCD controller before -//! being written into the frame buffer palette. -//! -//! If \b LCD_PALETTE_SRC_24BIT is not present, it is assumed that the -//! \e pui32SrcColors array contains 12-bit colors in the format required by -//! the LCD controller with 2 colors stored in each 32-bit word. In this case, -//! the values are copied directly into the frame buffer palette without any -//! reformatting. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterPaletteSet(uint32_t ui32Base, uint32_t ui32Type, uint32_t *pui32Addr, - const uint32_t *pui32SrcColors, uint32_t ui32Start, - uint32_t ui32Count) -{ - uint16_t *pui16Pal; - uint16_t *pui16Src; - uint32_t ui32Loop; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(ui32Start < 256); - ASSERT((ui32Start + ui32Count) <= 256); - ASSERT(pui32Addr); - ASSERT((pui32SrcColors) || (ui32Count == 0)); - ASSERT(!(ui32Type & ~(LCD_PALETTE_SRC_24BIT | LCD_PALETTE_TYPE_DIRECT | - LCD_PALETTE_TYPE_8BPP | LCD_PALETTE_TYPE_4BPP | - LCD_PALETTE_TYPE_2BPP | LCD_PALETTE_TYPE_1BPP))); - - // - // Get a pointer to the start of the palette. - // - pui16Pal = (uint16_t *)pui32Addr; - - // - // Are we converting the palette color format? - // - if(ui32Type & LCD_PALETTE_SRC_24BIT) - { - // - // Yes - loop through each of the supplied 24-bit colors converting - // and storing each. - // - ui32Loop = 0; - while(ui32Count) - { - pui16Pal[ui32Start + ui32Loop] = - PAL_FROM_RGB(pui32SrcColors[ui32Loop]); - ui32Loop++; - ui32Count--; - } - } - else - { - // - // No - loop through the supplied 12-bit colors storing each. - // - - pui16Src = (uint16_t *)pui32SrcColors; - while(ui32Count) - { - pui16Pal[ui32Start] = pui16Src[ui32Start]; - ui32Start++; - ui32Count--; - } - } - - // - // Write the pixel type into the first palette entry. - // - pui16Pal[0] &= ~(LCD_PALETTE_TYPE_8BPP | LCD_PALETTE_TYPE_DIRECT); - pui16Pal[0] |= (ui32Type & ~LCD_PALETTE_SRC_24BIT); -} - -//***************************************************************************** -// -//! Sets the LCD controller frame buffer start address and size in raster mode. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8Buffer specifies which frame buffer to configure. Valid values -//! are 0 and 1. -//! \param pui32Addr points to the first byte of the frame buffer. This -//! pointer must be aligned on a 32-bit (word) boundary. -//! \param ui32NumBytes specifies the size of the frame buffer in bytes. This -//! value must be a multiple of 4. -//! -//! This function is used to configure the position and size of one of the -//! two supported frame buffers while in raster mode. The second frame buffer -//! (configured when ui8Buffer is set to 1) is only used if the controller -//! is set to operate in ping-pong mode (by specifying the \b LCD_DMA_PING_PONG -//! configuration flag on a call to LCDDMAConfigSet()). -//! -//! The format of the frame buffer depends on the image type in use and -//! the current raster configuration settings. If \b RASTER_LOAD_DATA_ONLY -//! was specified in a previous call to LCDRasterConfigSet(), the frame buffer -//! contains only packed pixel data in the required bit depth and format. -//! In other cases, the frame buffer comprises a palette of either 8 or 128 -//! 32-bit words followed by the packed pixel data. The palette size is 8 -//! words (16 16-bit entries) for all pixel formats other than 8bpp which -//! uses a palette of 128 words (256 16-bit entries). Note that the 8 word -//! palette is still present even for 12, 16 and 24-bit formats, which do not -//! use the lookup table. -//! -//! The frame buffer size, specified using the \e ui32NumBytes parameter, must -//! be the palette size (if any) plus the size of the image bitmap required -//! for the currently configured display resolution. -//! -//! \e ui32NumBytes = (Palette Size) + ((Width * Height) * BPP) / 8) -//! -//! If \b RASTER_LOAD_DATA_ONLY is not specified, frame buffers passed to this -//! function must be initialized using a call to LCDRasterPaletteSet() prior to -//! enabling the raster output. If this is not done, the pixel format -//! identifier and color table required by the hardware is not present -//! and the results are unpredictable. -//! -//! \return None. -//***************************************************************************** -void -LCDRasterFrameBufferSet(uint32_t ui32Base, uint8_t ui8Buffer, - uint32_t *pui32Addr, uint32_t ui32NumBytes) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!((uint32_t)pui32Addr & 3)); - ASSERT(!(ui32NumBytes & 3)); - ASSERT(ui8Buffer < 2); - - // - // Are we setting the values for frame buffer 0? - // - if(!ui8Buffer) - { - // - // Yes - set the registers for frame buffer 0. - // - HWREG(ui32Base + LCD_O_DMABAFB0) = (uint32_t)pui32Addr; - HWREG(ui32Base + LCD_O_DMACAFB0) = (uint32_t)pui32Addr + - ui32NumBytes - 4; - } - else - { - // - // No - set the registers for frame buffer 1. - // - HWREG(ui32Base + LCD_O_DMABAFB1) = (uint32_t)pui32Addr; - HWREG(ui32Base + LCD_O_DMACAFB1) = (uint32_t)pui32Addr + - ui32NumBytes - 4; - } -} - -//***************************************************************************** -// -//! Enables individual LCD controller interrupt sources. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated LCD controller interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. -//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is -//! complete. -//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. -//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter -//! has decremented to zero and is is valid for passive matrix panels only. -//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded -//! but remains disabled until this interrupt is cleared. -//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The -//! internal FIFO was empty when the output logic attempted to read data to -//! send to the display. -//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. -//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been -//! signaled. -//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been -//! signaled. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST | - LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW | - LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 | - LCD_INT_RASTER_FRAME_DONE))); - - // - // Enable the interrupt sources by setting the appropriate bits in the - // mask register. - // - HWREG(ui32Base + LCD_O_IM) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual LCD controller interrupt sources. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated LCD controller interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. -//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is -//! complete. -//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. -//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter -//! has decremented to zero and is is valid for passive matrix panels only. -//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded -//! but remains disabled until this interrupt is cleared. -//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The -//! internal FIFO was empty when the output logic attempted to read data to -//! send to the display. -//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. -//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been -//! signaled. -//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been -//! signaled. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST | - LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW | - LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 | - LCD_INT_RASTER_FRAME_DONE))); - - // - // Disable the interrupt sources by clearing the appropriate bits in the - // mask register. - // - HWREG(ui32Base + LCD_O_IENC) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets the current LCD controller interrupt status. -//! -//! \param ui32Base is the base address of the controller. -//! \param bMasked is false if the raw interrupt status is required and true -//! if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the LCD controller. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status as the logical OR of any of -//! the following: -//! -//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. -//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is -//! complete. -//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. -//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter -//! has decremented to zero and is is valid for passive matrix panels only. -//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded -//! but remains disabled until this interrupt is cleared. -//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The -//! internal FIFO was empty when the output logic attempted to read data to -//! send to the display. -//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. -//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been -//! signaled. -//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been -//! signaled. -// -//***************************************************************************** -uint32_t -LCDIntStatus(uint32_t ui32Base, bool bMasked) -{ - ASSERT(ui32Base == LCD0_BASE); - - // - // Were we asked for the masked or raw interrupt status? - // - if(bMasked) - { - // - // Return the masked interrupt status. - // - return(HWREG(ui32Base + LCD_O_MISCLR)); - } - else - { - // - // Return the raw interrupts status. - // - return(HWREG(ui32Base + LCD_O_RISSET)); - } -} - -//***************************************************************************** -// -//! Clears LCD controller interrupt sources. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified LCD controller interrupt sources are cleared so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. -//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is -//! complete. -//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. -//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter -//! has decremented to zero and is is valid for passive matrix panels only. -//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded -//! but remains disabled until this interrupt is cleared. -//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The -//! internal FIFO was empty when the output logic attempted to read data to -//! send to the display. -//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. -//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been -//! signaled. -//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been -//! signaled. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -LCDIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST | - LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW | - LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 | - LCD_INT_RASTER_FRAME_DONE))); - - // - // Clear the requested interrupts. - // - HWREG(ui32Base + LCD_O_MISCLR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the LCD controller module. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param pfnHandler is a pointer to the function to be called when the LCD -//! controller interrupt occurs. -//! -//! This function registers the handler to be called when the LCD controller -//! module interrupt occurs. -//! -//! \note This function need not be called if the appropriate interrupt vector -//! is statically linked into the vector table in the application startup code. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(pfnHandler); - - // - // Register the interrupt handler. - // - IntRegister(INT_LCD0_TM4C129, pfnHandler); - - // - // Enable the interrupt in the interrupt controller. - // - IntEnable(INT_LCD0_TM4C129); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the LCD controller module. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! -//! This function unregisters the interrupt handler and disables the global LCD -//! controller interrupt in the interrupt controller. -//! -//! \note This function need not be called if the appropriate interrupt vector -//! is statically linked into the vector table in the application startup code. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Disable the interrupt in the interrupt controller. - // - IntDisable(INT_LCD0_TM4C129); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_LCD0_TM4C129); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/lcd.h b/bsp/tm4c129x-dk/libraries/driverlib/lcd.h deleted file mode 100644 index 766cf943615ac1f1634026844788fd1501d92b8c..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/lcd.h +++ /dev/null @@ -1,487 +0,0 @@ -//***************************************************************************** -// -// lcd.h - Defines and Macros for the LCD Controller module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_LCD_H__ -#define __DRIVERLIB_LCD_H__ - -//***************************************************************************** -// -//! \addtogroup lcd_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! This macro can be used to convert a 24-bit RGB color value as used by the -//! TivaWare Graphics Library into a 12-bit LCD controller color palette -//! entry. -// -//***************************************************************************** -#define PAL_FROM_RGB(ui32RGBColor) (((ui32RGBColor & 0xF0) >> 4) | \ - ((ui32RGBColor & 0xF000) >> 8) | \ - ((ui32RGBColor & 0xF00000) >> 12)) - -//***************************************************************************** -// -//! This macro can be used to convert from time in microseconds to periods of -//! the supplied clock in Hertz as required when setting up the LIDD and raster -//! timing structures. The calculation will round such that the number of -//! cycles returned represents no longer a time than specified in the -//! ui32Time_uS parameter. Values of ui32Time_uS less than or equal to -//! 4294967uS (4.29 seconds) are supported by the macro. Larger values will -//! cause arithmetic overflow and yield incorrect values. It is further -//! assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz). -// -//***************************************************************************** -#define CYCLES_FROM_TIME_US(ui32ClockFreq, ui32Time_uS) \ - (((ui32Time_uS) == 0) ? 0 : \ - (((ui32ClockFreq) / 1000000) * ((((ui32Time_uS) * 1000) - 1) / 1000)) + 1) - -//***************************************************************************** -// -//! This macro can be used to convert from time in nanoseconds to periods of -//! the supplied clock in Hertz as required when setting up the LIDD and raster -//! timing structures. The calculation will round such that the number of -//! cycles returned represents no longer a time than specified in the -//! ui32Time_nS parameter. Values of ui32Time_nS less than or equal to -//! 35791394 (35.79 milliseconds) are supported by the macro. Larger values -//! will cause arithmetic overflow and yield incorrect values. It is further -//! assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz). -// -//***************************************************************************** -#define CYCLES_FROM_TIME_NS(ui32ClockFreq, ui32Time_nS) \ - (((ui32Time_nS) == 0) ? 0 : \ - ((((((ui32ClockFreq) / 1000000) * ((ui32Time_nS) - 1)) / 1000)) + 1)) - -//***************************************************************************** -// -//! A structure containing timing parameters for the LIDD (LCD Interface -//! Display Driver) interface. This is used with the LCDIDDTimingSet function. -// -//***************************************************************************** -typedef struct -{ - // - //! Write Strobe Set-Up cycles. When performing a write access, this - //! field defines the number of MCLK cycles that Data Bus/Pad Output - //! Enable, ALE, the Direction bit, and Chip Select have to be ready before - //! the Write Strobe is asserted. Valid values are from 0 to 31. - // - uint8_t ui8WSSetup; - - // - //! Write Strobe Duration cycles. Field value defines the number of MCLK - //! cycles for which the Write Strobe is held active when performing a - //! write access. Valid values are from 1 to 63. - // - uint8_t ui8WSDuration; - - // - //! Write Strobe Hold cycles. Field value defines the number of MCLK - //! cycles for which Data Bus/Pad Output Enable, ALE, the Direction bit, - //! and Chip Select are held after the Write Strobe is deasserted when - //! performing a write access. Valid values are from 1 to 15. - // - uint8_t ui8WSHold; - - // - //! Read Strobe Set-Up cycles. When performing a read access, this field - //! defines the number of MCLK cycles that Data Bus/Pad Output Enable, ALE, - //! the Direction bit, and Chip Select have to be ready before the Read - //! Strobe is asserted. Valid values are from 0 to 31. - // - uint8_t ui8RSSetup; - - // - //! Read Strobe Duration cycles. Field value defines the number of MCLK - //! cycles for which the Read Strobe is held active when performing a read - //! access. Valid values are from 1 to 63. - // - uint8_t ui8RSDuration; - - // - //! Read Strobe Hold cycles. Field value defines the number of MCLK cycles - //! for which Data Bus/Pad Output Enable, ALE, the Direction bit, and Chip - //! Select are held after the Read Strobe is deasserted when performing a - //! read access. Valid values are from 1 to 15. - // - uint8_t ui8RSHold; - - // - //! Field value defines the number of MCLK cycles between the end of one - //! device access and the start of another device access using the same - //! Chip Select unless the two accesses are both Reads. In this case, - //! this delay is not incurred. Valid vales are from 1 to 4. - // - uint8_t ui8DelayCycles; -} -tLCDIDDTiming; - -// -// Values which can be ORed together within the ui32Flags field of the -// tLCDRasterTiming structure. -// -#define RASTER_TIMING_SYNCS_OPPOSITE_PIXCLK \ - 0x00000000 -#define RASTER_TIMING_SYNCS_ON_RISING_PIXCLK \ - 0x02000000 -#define RASTER_TIMING_SYNCS_ON_FALLING_PIXCLK \ - 0x03000000 -#define RASTER_TIMING_ACTIVE_HIGH_OE \ - 0x00000000 -#define RASTER_TIMING_ACTIVE_LOW_OE \ - 0x00800000 -#define RASTER_TIMING_ACTIVE_HIGH_PIXCLK \ - 0x00000000 -#define RASTER_TIMING_ACTIVE_LOW_PIXCLK \ - 0x00400000 -#define RASTER_TIMING_ACTIVE_HIGH_HSYNC \ - 0x00000000 -#define RASTER_TIMING_ACTIVE_LOW_HSYNC \ - 0x00200000 -#define RASTER_TIMING_ACTIVE_HIGH_VSYNC \ - 0x00000000 -#define RASTER_TIMING_ACTIVE_LOW_VSYNC \ - 0x00100000 - -// -//! A structure containing timing parameters for the raster interface. This is -//! used with the LCDRasterTimingSet function. -// -typedef struct -{ - // - //! Flags configuring the polarity and active edges of the various signals - //! in the raster interface. This field is comprised of a logical OR of - //! the labels with prefix ``RASTER_TIMING_''. - // - uint32_t ui32Flags; - - // - //! The number of pixels contained within each line on the LCD display. - //! Valid values are multiple of 16 less than or equal to 2048. - // - uint16_t ui16PanelWidth; - - // - //! The number of lines on the LCD display. Valid values are from 1 to - //! 2048. - // - uint16_t ui16PanelHeight; - - // - //! A value from 1 to 1024 that specifies the number of pixel clock periods - //! to add to the end of each line after active video has ended. - // - uint16_t ui16HFrontPorch; - - // - //! A value from 1 to 1024 that specifies the number of pixel clock periods - //! to add to the beginning of a line before active video is asserted. - // - uint16_t ui16HBackPorch; - - // - //! A value from 1 to 1024 that specifies the number of pixel clock periods - //! to pulse the line clock at the end of each line. - // - uint16_t ui16HSyncWidth; - - // - //! A value from 0 to 255 that specifies the number of line clock periods - //! to add to the end of each frame after the last active line. - // - uint8_t ui8VFrontPorch; - - // - //! A value from 0 to 255 that specifies the number of line clock periods - //! to add to the beginning of a frame before the first active line is - //! output to the display. - // - uint8_t ui8VBackPorch; - - // - //! In active mode, a value from 1 to 64 that specifies the number of - //! line clock periods to set the lcd_fp pin active at the end of each - //! frame after the vertical front porch period elapses. The number of - //! The frame clock is used as the VSYNC signal in active mode. - //! - //! In passive mode, a value from 1 to 64 that specifies the number of - //! extra line clock periods to insert after the vertical front porch - //! period has elapsed. Note that the width of lcd_fp is not affected by - //! this value in passive mode. - // - uint8_t ui8VSyncWidth; - - // - //! A value from 0 to 255 that specifies the number of line clocks to - //! count before transitioning the AC Bias pin. This pin is used to - //! periodically invert the polarity of the power supply to prevent DC - //! charge build-up within the display. - // - uint8_t ui8ACBiasLineCount; -} -tLCDRasterTiming; - -//***************************************************************************** -// -// Possible values for the ui8Mode parameter to LCDModeSet(). The label -// LCD_MODE_AUTO_UFLOW_RESTART may be ORed with either of the other two. -// -//***************************************************************************** -#define LCD_MODE_LIDD ((uint8_t)0x00) -#define LCD_MODE_RASTER ((uint8_t)0x01) -#define LCD_MODE_AUTO_UFLOW_RESTART \ - ((uint8_t)0x02) - -//***************************************************************************** -// -// Values used to construct the ui32Config parameter to LCDIDDConfigSet(). -// -//***************************************************************************** -#define LIDD_CONFIG_SYNC_MPU68 0x00000000 -#define LIDD_CONFIG_ASYNC_MPU68 0x00000001 -#define LIDD_CONFIG_SYNC_MPU80 0x00000002 -#define LIDD_CONFIG_ASYNC_MPU80 0x00000003 -#define LIDD_CONFIG_ASYNC_HITACHI \ - 0x00000004 -#define LIDD_CONFIG_INVERT_ALE 0x00000008 -#define LIDD_CONFIG_INVERT_RS_EN \ - 0x00000010 -#define LIDD_CONFIG_INVERT_WS_DIR \ - 0x00000020 -#define LIDD_CONFIG_INVERT_CS0 0x00000040 -#define LIDD_CONFIG_INVERT_CS1 0x00000080 - -//***************************************************************************** -// -// Values used to construct the ui32Config parameter to -// LCDRasterConfigSet(). Valid parameters contain one of the RASTER_FMT_xxx -// labels optionally ORed with the other flags. Only one of -// RASTER_LOAD_DATA_ONLY and RASTER_LOAD_PALETTE_ONLY may be specified (if -// neither is specified, the controller will load both palette and data when -// scanning out the frame buffer). -// -//***************************************************************************** -#define RASTER_FMT_ACTIVE_24BPP_PACKED \ - 0x02000080 -#define RASTER_FMT_ACTIVE_24BPP_UNPACKED \ - 0x06000080 -#define RASTER_FMT_ACTIVE_PALETTIZED_12BIT \ - 0x00000080 -#define RASTER_FMT_ACTIVE_PALETTIZED_16BIT \ - 0x00800080 -#define RASTER_FMT_PASSIVE_MONO_4PIX \ - 0x00000002 -#define RASTER_FMT_PASSIVE_MONO_8PIX \ - 0x00000202 -#define RASTER_FMT_PASSIVE_PALETTIZED \ - 0x00000000 -#define RASTER_FMT_PASSIVE_COLOR_12BIT \ - 0x00000000 -#define RASTER_FMT_PASSIVE_COLOR_16BIT \ - 0x01000000 -#define RASTER_ACTVID_DURING_BLANK \ - 0x08000000 -#define RASTER_NIBBLE_MODE_ENABLED \ - 0x00400000 -#define RASTER_LOAD_DATA_ONLY 0x00200000 -#define RASTER_LOAD_PALETTE_ONLY \ - 0x00100000 -#define RASTER_READ_ORDER_REVERSED \ - 0x00000100 - -//***************************************************************************** -// -// Interrupt sources for the LCD controller. These may be ORed together and -// passed to LCDIntEnable(), LCDIntDisable() and LCDIntClear(). They are also -// returned by LCDIntStatus(). -// -//***************************************************************************** -#define LCD_INT_DMA_DONE 0x00000001 -#define LCD_INT_RASTER_FRAME_DONE \ - 0x00000002 -#define LCD_INT_SYNC_LOST 0x00000004 -#define LCD_INT_AC_BIAS_CNT 0x00000008 -#define LCD_INT_UNDERFLOW 0x00000020 -#define LCD_INT_PAL_LOAD 0x00000040 -#define LCD_INT_EOF0 0x00000100 -#define LCD_INT_EOF1 0x00000200 - -//***************************************************************************** -// -// Configuration values used with LCDDMAConfigSet(). -// -//***************************************************************************** -#define LCD_DMA_FIFORDY_8_WORDS 0x00000000 -#define LCD_DMA_FIFORDY_16_WORDS \ - 0x00000100 -#define LCD_DMA_FIFORDY_32_WORDS \ - 0x00000200 -#define LCD_DMA_FIFORDY_64_WORDS \ - 0x00000300 -#define LCD_DMA_FIFORDY_128_WORDS \ - 0x00000400 -#define LCD_DMA_FIFORDY_256_WORDS \ - 0x00000500 -#define LCD_DMA_FIFORDY_512_WORDS \ - 0x00000600 -#define LCD_DMA_BURST_1 0x00000010 -#define LCD_DMA_BURST_2 0x00000010 -#define LCD_DMA_BURST_4 0x00000020 -#define LCD_DMA_BURST_8 0x00000030 -#define LCD_DMA_BURST_16 0x00000040 -#define LCD_DMA_BYTE_ORDER_0123 0x00000000 -#define LCD_DMA_BYTE_ORDER_1023 0x00000008 -#define LCD_DMA_BYTE_ORDER_3210 0x00000002 -#define LCD_DMA_BYTE_ORDER_2301 0x0000000A -#define LCD_DMA_PING_PONG 0x00000001 - -//***************************************************************************** -// -// Type values used with LCDRasterPaletteSet(). -// -//***************************************************************************** -#define LCD_PALETTE_TYPE_1BPP 0x00000000 -#define LCD_PALETTE_TYPE_2BPP 0x00001000 -#define LCD_PALETTE_TYPE_4BPP 0x00002000 -#define LCD_PALETTE_TYPE_8BPP 0x00003000 -#define LCD_PALETTE_TYPE_DIRECT 0x00004000 -#define LCD_PALETTE_SRC_24BIT 0x80000000 - -//***************************************************************************** -// -// Flags used in the ui32Clocks parameter to LCDClockReset(). -// -//***************************************************************************** -#define LCD_CLOCK_MAIN 0x00000008 -#define LCD_CLOCK_DMA 0x00000004 -#define LCD_CLOCK_LIDD 0x00000002 -#define LCD_CLOCK_CORE 0x00000001 - -//***************************************************************************** -// -// Flags used in with LCDSubPanelConfigSet(). -// -//***************************************************************************** -#define LCD_SUBPANEL_AT_TOP 0x20000000 -#define LCD_SUBPANEL_AT_BOTTOM 0x00000000 - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Function Prototypes. -// -//***************************************************************************** -extern uint32_t LCDModeSet(uint32_t ui32Base, uint8_t ui8Mode, - uint32_t ui32PixClk, uint32_t ui32SysClk); -extern void LCDClockReset(uint32_t ui32Base, uint32_t ui32Clocks); -extern void LCDIDDConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void LCDIDDTimingSet(uint32_t ui32Base, uint32_t ui32CS, - const tLCDIDDTiming *pTiming); -extern void LCDIDDDMADisable(uint32_t ui32Base); -extern void LCDIDDCommandWrite(uint32_t ui32Base, uint32_t ui32CS, - uint16_t ui16Cmd); -extern void LCDIDDDataWrite(uint32_t ui32Base, uint32_t ui32CS, - uint16_t ui16Data); -extern void LCDIDDIndexedWrite(uint32_t ui32Base, uint32_t ui32CS, - uint16_t ui16Addr, uint16_t ui16Data); -extern uint16_t LCDIDDStatusRead(uint32_t ui32Base, uint32_t ui32CS); -extern uint16_t LCDIDDDataRead(uint32_t ui32Base, uint32_t ui32CS); -extern uint16_t LCDIDDIndexedRead(uint32_t ui32Base, uint32_t ui32CS, - uint16_t ui16Addr); -extern void LCDIDDDMAWrite(uint32_t ui32Base, uint32_t ui32CS, - const uint32_t *pui32Data, uint32_t ui32Count); -extern void LCDRasterConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint8_t ui8PalLoadDelay); -extern void LCDRasterTimingSet(uint32_t ui32Base, - const tLCDRasterTiming *pTiming); -extern void LCDRasterACBiasIntCountSet(uint32_t ui32Base, uint8_t ui8Count); -extern void LCDRasterEnable(uint32_t ui32Base); -extern bool LCDRasterEnabled(uint32_t ui32Base); -extern void LCDRasterDisable(uint32_t ui32Base); -extern void LCDRasterSubPanelConfigSet(uint32_t ui32Base, uint32_t ui32Flags, - uint32_t ui32BottomLines, - uint32_t ui32DefaultPixel); -extern void LCDRasterSubPanelEnable(uint32_t ui32Base); -extern void LCDRasterSubPanelDisable(uint32_t ui32Base); -extern void LCDDMAConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void LCDRasterPaletteSet(uint32_t ui32Base, uint32_t ui32Type, - uint32_t *pui32PalAddr, - const uint32_t *pui32SrcColors, - uint32_t ui32Start, - uint32_t ui32Count); -extern void LCDRasterFrameBufferSet(uint32_t ui32Base, uint8_t ui8Buffer, - uint32_t *pui32Addr, - uint32_t ui32NumBytes); -extern void LCDIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void LCDIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t LCDIntStatus(uint32_t ui32Base, bool bMasked); -extern void LCDIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void LCDIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void LCDIntUnregister(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_LCD_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/mpu.c b/bsp/tm4c129x-dk/libraries/driverlib/mpu.c deleted file mode 100644 index 4d01f1b403cd87d6c2c2932946d2fe3fafea3c6f..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/mpu.c +++ /dev/null @@ -1,459 +0,0 @@ -//***************************************************************************** -// -// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU). -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup mpu_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/mpu.h" - -//***************************************************************************** -// -//! Enables and configures the MPU for use. -//! -//! \param ui32MPUConfig is the logical OR of the possible configurations. -//! -//! This function enables the Cortex-M memory protection unit. It also -//! configures the default behavior when in privileged mode and while handling -//! a hard fault or NMI. Prior to enabling the MPU, at least one region must -//! be set by calling MPURegionSet() or else by enabling the default region for -//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to -//! MPUEnable(). Once the MPU is enabled, a memory management fault is -//! generated for memory access violations. -//! -//! The \e ui32MPUConfig parameter should be the logical OR of any of the -//! following: -//! -//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in -//! privileged mode and when no other regions are defined. If this option -//! is not enabled, then there must be at least one valid region already -//! defined when the MPU is enabled. -//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI -//! exception handler. If this option is not enabled, then the MPU is -//! disabled while in one of these exception handlers and the default -//! memory map is applied. -//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case, -//! no default memory map is provided in privileged mode, and the MPU is not -//! enabled in the fault handlers. -//! -//! \return None. -// -//***************************************************************************** -void -MPUEnable(uint32_t ui32MPUConfig) -{ - // - // Check the arguments. - // - ASSERT(!(ui32MPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT | - MPU_CONFIG_HARDFLT_NMI))); - - // - // Set the MPU control bits according to the flags passed by the user, - // and also set the enable bit. - // - HWREG(NVIC_MPU_CTRL) = ui32MPUConfig | NVIC_MPU_CTRL_ENABLE; -} - -//***************************************************************************** -// -//! Disables the MPU for use. -//! -//! This function disables the Cortex-M memory protection unit. When the -//! MPU is disabled, the default memory map is used and memory management -//! faults are not generated. -//! -//! \return None. -// -//***************************************************************************** -void -MPUDisable(void) -{ - // - // Turn off the MPU enable bit. - // - HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE; -} - -//***************************************************************************** -// -//! Gets the count of regions supported by the MPU. -//! -//! This function is used to get the total number of regions that are supported -//! by the MPU, including regions that are already programmed. -//! -//! \return The number of memory protection regions that are available -//! for programming using MPURegionSet(). -// -//***************************************************************************** -uint32_t -MPURegionCountGet(void) -{ - // - // Read the DREGION field of the MPU type register and mask off - // the bits of interest to get the count of regions. - // - return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M) >> - NVIC_MPU_TYPE_DREGION_S); -} - -//***************************************************************************** -// -//! Enables a specific region. -//! -//! \param ui32Region is the region number to enable. -//! -//! This function is used to enable a memory protection region. The region -//! should already be configured with the MPURegionSet() function. Once -//! enabled, the memory protection rules of the region are applied and access -//! violations cause a memory management fault. -//! -//! \return None. -// -//***************************************************************************** -void -MPURegionEnable(uint32_t ui32Region) -{ - // - // Check the arguments. - // - ASSERT(ui32Region < 8); - - // - // Select the region to modify. - // - HWREG(NVIC_MPU_NUMBER) = ui32Region; - - // - // Modify the enable bit in the region attributes. - // - HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE; -} - -//***************************************************************************** -// -//! Disables a specific region. -//! -//! \param ui32Region is the region number to disable. -//! -//! This function is used to disable a previously enabled memory protection -//! region. The region remains configured if it is not overwritten with -//! another call to MPURegionSet(), and can be enabled again by calling -//! MPURegionEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -MPURegionDisable(uint32_t ui32Region) -{ - // - // Check the arguments. - // - ASSERT(ui32Region < 8); - - // - // Select the region to modify. - // - HWREG(NVIC_MPU_NUMBER) = ui32Region; - - // - // Modify the enable bit in the region attributes. - // - HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE; -} - -//***************************************************************************** -// -//! Sets up the access rules for a specific region. -//! -//! \param ui32Region is the region number to set up. -//! \param ui32Addr is the base address of the region. It must be aligned -//! according to the size of the region specified in ui32Flags. -//! \param ui32Flags is a set of flags to define the attributes of the region. -//! -//! This function sets up the protection rules for a region. The region has -//! a base address and a set of attributes including the size. The base -//! address parameter, \e ui32Addr, must be aligned according to the size, and -//! the size must be a power of 2. -//! -//! The \e ui32Flags parameter is the logical OR of all of the attributes -//! of the region. It is a combination of choices for region size, -//! execute permission, read/write permissions, disabled sub-regions, -//! and a flag to determine if the region is enabled. -//! -//! The size flag determines the size of a region and must be one of the -//! following: -//! -//! - \b MPU_RGN_SIZE_32B -//! - \b MPU_RGN_SIZE_64B -//! - \b MPU_RGN_SIZE_128B -//! - \b MPU_RGN_SIZE_256B -//! - \b MPU_RGN_SIZE_512B -//! - \b MPU_RGN_SIZE_1K -//! - \b MPU_RGN_SIZE_2K -//! - \b MPU_RGN_SIZE_4K -//! - \b MPU_RGN_SIZE_8K -//! - \b MPU_RGN_SIZE_16K -//! - \b MPU_RGN_SIZE_32K -//! - \b MPU_RGN_SIZE_64K -//! - \b MPU_RGN_SIZE_128K -//! - \b MPU_RGN_SIZE_256K -//! - \b MPU_RGN_SIZE_512K -//! - \b MPU_RGN_SIZE_1M -//! - \b MPU_RGN_SIZE_2M -//! - \b MPU_RGN_SIZE_4M -//! - \b MPU_RGN_SIZE_8M -//! - \b MPU_RGN_SIZE_16M -//! - \b MPU_RGN_SIZE_32M -//! - \b MPU_RGN_SIZE_64M -//! - \b MPU_RGN_SIZE_128M -//! - \b MPU_RGN_SIZE_256M -//! - \b MPU_RGN_SIZE_512M -//! - \b MPU_RGN_SIZE_1G -//! - \b MPU_RGN_SIZE_2G -//! - \b MPU_RGN_SIZE_4G -//! -//! The execute permission flag must be one of the following: -//! -//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code -//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code -//! -//! The read/write access permissions are applied separately for the -//! privileged and user modes. The read/write access flags must be one -//! of the following: -//! -//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode -//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access -//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only -//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write -//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access -//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only -//! -//! The region is automatically divided into 8 equally-sized sub-regions by -//! the MPU. Sub-regions can only be used in regions of size 256 bytes -//! or larger. Any of these 8 sub-regions can be disabled, allowing for -//! creation of ``holes'' in a region which can be left open, or overlaid -//! by another region with different attributes. Any of the 8 sub-regions -//! can be disabled with a logical OR of any of the following flags: -//! -//! - \b MPU_SUB_RGN_DISABLE_0 -//! - \b MPU_SUB_RGN_DISABLE_1 -//! - \b MPU_SUB_RGN_DISABLE_2 -//! - \b MPU_SUB_RGN_DISABLE_3 -//! - \b MPU_SUB_RGN_DISABLE_4 -//! - \b MPU_SUB_RGN_DISABLE_5 -//! - \b MPU_SUB_RGN_DISABLE_6 -//! - \b MPU_SUB_RGN_DISABLE_7 -//! -//! Finally, the region can be initially enabled or disabled with one of -//! the following flags: -//! -//! - \b MPU_RGN_ENABLE -//! - \b MPU_RGN_DISABLE -//! -//! As an example, to set a region with the following attributes: size of -//! 32 KB, execution enabled, read-only for both privileged and user, one -//! sub-region disabled, and initially enabled; the \e ui32Flags parameter -//! would have the following value: -//! -//! -//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO | -//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE) -//! -//! -//! \note This function writes to multiple registers and is not protected -//! from interrupts. It is possible that an interrupt which accesses a -//! region may occur while that region is in the process of being changed. -//! The safest way to handle this is to disable a region before changing it. -//! Refer to the discussion of this in the API Detailed Description section. -//! -//! \return None. -// -//***************************************************************************** -void -MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Region < 8); - ASSERT(ui32Addr == - (ui32Addr & ~0 << (((ui32Flags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1))); - - // - // Program the base address, use the region field to select the - // region at the same time. - // - HWREG(NVIC_MPU_BASE) = ui32Addr | ui32Region | NVIC_MPU_BASE_VALID; - - // - // Program the region attributes. Set the TEX field and the S, C, - // and B bits to fixed values that are suitable for all Tiva C and - // E Series memory. - // - HWREG(NVIC_MPU_ATTR) = ((ui32Flags & ~(NVIC_MPU_ATTR_TEX_M | - NVIC_MPU_ATTR_CACHEABLE)) | - NVIC_MPU_ATTR_SHAREABLE | NVIC_MPU_ATTR_BUFFRABLE); -} - -//***************************************************************************** -// -//! Gets the current settings for a specific region. -//! -//! \param ui32Region is the region number to get. -//! \param pui32Addr points to storage for the base address of the region. -//! \param pui32Flags points to the attribute flags for the region. -//! -//! This function retrieves the configuration of a specific region. The -//! meanings and format of the parameters is the same as that of the -//! MPURegionSet() function. -//! -//! This function can be used to save the configuration of a region for later -//! use with the MPURegionSet() function. The region's enable state is -//! preserved in the attributes that are saved. -//! -//! \return None. -// -//***************************************************************************** -void -MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr, uint32_t *pui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Region < 8); - ASSERT(pui32Addr); - ASSERT(pui32Flags); - - // - // Select the region to get. - // - HWREG(NVIC_MPU_NUMBER) = ui32Region; - - // - // Read and store the base address for the region. - // - *pui32Addr = HWREG(NVIC_MPU_BASE) & NVIC_MPU_BASE_ADDR_M; - - // - // Read and store the region attributes. - // - *pui32Flags = HWREG(NVIC_MPU_ATTR); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the memory management fault. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! memory management fault occurs. -//! -//! This function sets and enables the handler to be called when the MPU -//! generates a memory management fault due to a protection region access -//! violation. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -MPUIntRegister(void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(pfnHandler); - - // - // Register the interrupt handler. - // - IntRegister(FAULT_MPU, pfnHandler); - - // - // Enable the memory management fault. - // - IntEnable(FAULT_MPU); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the memory management fault. -//! -//! This function disables and clears the handler to be called when a -//! memory management fault occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -MPUIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(FAULT_MPU); - - // - // Unregister the interrupt handler. - // - IntUnregister(FAULT_MPU); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/mpu.h b/bsp/tm4c129x-dk/libraries/driverlib/mpu.h deleted file mode 100644 index 9c8377f8cef7c7c9d32e5b4ad51753ec50164736..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/mpu.h +++ /dev/null @@ -1,162 +0,0 @@ -//***************************************************************************** -// -// mpu.h - Defines and Macros for the memory protection unit. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_MPU_H__ -#define __DRIVERLIB_MPU_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Flags that can be passed to MPUEnable. -// -//***************************************************************************** -#define MPU_CONFIG_PRIV_DEFAULT 4 -#define MPU_CONFIG_HARDFLT_NMI 2 -#define MPU_CONFIG_NONE 0 - -//***************************************************************************** -// -// Flags for the region size to be passed to MPURegionSet. -// -//***************************************************************************** -#define MPU_RGN_SIZE_32B (4 << 1) -#define MPU_RGN_SIZE_64B (5 << 1) -#define MPU_RGN_SIZE_128B (6 << 1) -#define MPU_RGN_SIZE_256B (7 << 1) -#define MPU_RGN_SIZE_512B (8 << 1) - -#define MPU_RGN_SIZE_1K (9 << 1) -#define MPU_RGN_SIZE_2K (10 << 1) -#define MPU_RGN_SIZE_4K (11 << 1) -#define MPU_RGN_SIZE_8K (12 << 1) -#define MPU_RGN_SIZE_16K (13 << 1) -#define MPU_RGN_SIZE_32K (14 << 1) -#define MPU_RGN_SIZE_64K (15 << 1) -#define MPU_RGN_SIZE_128K (16 << 1) -#define MPU_RGN_SIZE_256K (17 << 1) -#define MPU_RGN_SIZE_512K (18 << 1) - -#define MPU_RGN_SIZE_1M (19 << 1) -#define MPU_RGN_SIZE_2M (20 << 1) -#define MPU_RGN_SIZE_4M (21 << 1) -#define MPU_RGN_SIZE_8M (22 << 1) -#define MPU_RGN_SIZE_16M (23 << 1) -#define MPU_RGN_SIZE_32M (24 << 1) -#define MPU_RGN_SIZE_64M (25 << 1) -#define MPU_RGN_SIZE_128M (26 << 1) -#define MPU_RGN_SIZE_256M (27 << 1) -#define MPU_RGN_SIZE_512M (28 << 1) - -#define MPU_RGN_SIZE_1G (29 << 1) -#define MPU_RGN_SIZE_2G (30 << 1) -#define MPU_RGN_SIZE_4G (31 << 1) - -//***************************************************************************** -// -// Flags for the permissions to be passed to MPURegionSet. -// -//***************************************************************************** -#define MPU_RGN_PERM_EXEC 0x00000000 -#define MPU_RGN_PERM_NOEXEC 0x10000000 -#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000 -#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000 -#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000 -#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000 -#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000 -#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000 - -//***************************************************************************** -// -// Flags for the sub-region to be passed to MPURegionSet. -// -//***************************************************************************** -#define MPU_SUB_RGN_DISABLE_0 0x00000100 -#define MPU_SUB_RGN_DISABLE_1 0x00000200 -#define MPU_SUB_RGN_DISABLE_2 0x00000400 -#define MPU_SUB_RGN_DISABLE_3 0x00000800 -#define MPU_SUB_RGN_DISABLE_4 0x00001000 -#define MPU_SUB_RGN_DISABLE_5 0x00002000 -#define MPU_SUB_RGN_DISABLE_6 0x00004000 -#define MPU_SUB_RGN_DISABLE_7 0x00008000 - -//***************************************************************************** -// -// Flags to enable or disable a region, to be passed to MPURegionSet. -// -//***************************************************************************** -#define MPU_RGN_ENABLE 1 -#define MPU_RGN_DISABLE 0 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void MPUEnable(uint32_t ui32MPUConfig); -extern void MPUDisable(void); -extern uint32_t MPURegionCountGet(void); -extern void MPURegionEnable(uint32_t ui32Region); -extern void MPURegionDisable(uint32_t ui32Region); -extern void MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr, - uint32_t ui32Flags); -extern void MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr, - uint32_t *pui32Flags); -extern void MPUIntRegister(void (*pfnHandler)(void)); -extern void MPUIntUnregister(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_MPU_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/onewire.c b/bsp/tm4c129x-dk/libraries/driverlib/onewire.c deleted file mode 100644 index 24d671f12533c6cff7f1ec4be6f2f31672a76889..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/onewire.c +++ /dev/null @@ -1,767 +0,0 @@ -//***************************************************************************** -// -// onewire.c - Driver for OneWire master module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup onewire_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_onewire.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/onewire.h" -#include "driverlib/sysctl.h" - -//***************************************************************************** -// -// A bit mask for all transaction related fields in the 1-Wire control -// register. -// -//***************************************************************************** -#define ONEWIRE_TXN_MASK (ONEWIRE_CS_OP_M | ONEWIRE_CS_SZ_M | \ - ONEWIRE_CS_BSIZE_M) - -//***************************************************************************** -// -// Left-shift value for the control register's transaction size. -// -//***************************************************************************** -#define ONEWIRE_TXN_SIZE_LSHIFT 3 - -//***************************************************************************** -// -// Left-shift value for the control register's last byte bit size. -// -//***************************************************************************** -#define ONEWIRE_TXN_BSIZE_LSHIFT \ - 16 - -//***************************************************************************** -// -//! Initializes the 1-Wire module. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param ui32InitFlags provides the initialization flags. -//! -//! This function configures and initializes the 1-Wire interface for use. -//! -//! The \e ui32InitFlags parameter is a combination of the following: -//! -//! - \b ONEWIRE_INIT_SPD_STD - standard speed bus timings -//! - \b ONEWIRE_INIT_SPD_OD - overdrive speed bus timings -//! - \b ONEWIRE_INIT_READ_STD - standard read sampling timing -//! - \b ONEWIRE_INIT_READ_LATE - late read sampling timing -//! - \b ONEWIRE_INIT_ATR - standard answer-to-reset presence detect -//! - \b ONEWIRE_INIT_NO_ATR - no answer-to-reset presence detect -//! - \b ONEWIRE_INIT_STD_POL - normal signal polarity -//! - \b ONEWIRE_INIT_ALT_POL - alternate (reverse) signal polarity -//! - \b ONEWIRE_INIT_1_WIRE_CFG - standard 1-Wire (1 data pin) setup -//! - \b ONEWIRE_INIT_2_WIRE_CFG - alternate 2-Wire (2 data pin) setup -//! -//! \return None. -// -//***************************************************************************** -void -OneWireInit(uint32_t ui32Base, uint32_t ui32InitFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - - // - // Initialize control register. - // - HWREG(ui32Base + ONEWIRE_O_CS) = ui32InitFlags; -} - -//***************************************************************************** -// -//! Issues a reset on the 1-Wire bus. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! -//! This function causes the 1-Wire module to generate a reset signal on the -//! 1-Wire bus. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireBusReset(uint32_t ui32Base) -{ - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - - // - // Issue a bus reset. - // - HWREG(ui32Base + ONEWIRE_O_CS) |= ONEWIRE_CS_RST; -} - -//***************************************************************************** -// -//! Retrieves the 1-Wire bus condition status. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! -//! This function returns the 1-Wire bus conditions reported by the 1-Wire -//! module. These conditions could be a logical OR of any of the following: -//! -//! - \b ONEWIRE_BUS_STATUS_BUSY - A read, write, or reset is active. -//! - \b ONEWIRE_BUS_STATUS_NO_SLAVE - No slave presence pulses detected. -//! - \b ONEWIRE_BUS_STATUS_STUCK - The bus is being held low by non-master. -//! -//! \return Returns the 1-Wire bus conditions if detected else zero. -// -//***************************************************************************** -uint32_t -OneWireBusStatus(uint32_t ui32Base) -{ - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - - // - // Return the status bits from control and status register. - // - return(HWREG(ui32Base + ONEWIRE_O_CS) & (ONEWIRE_CS_BUSY | - ONEWIRE_CS_NOATR | - ONEWIRE_CS_STUCK)); -} - -//***************************************************************************** -// -//! Retrieves data from the 1-Wire interface. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param pui32Data is a pointer to storage to hold the read data. -//! -//! This function reads data from the 1-Wire module once all active bus -//! operations are completed. By protocol definition, bit data defaults to -//! a 1. Thus if a slave did not signal any 0-bit data, this read returns -//! 0xffffffff. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireDataGet(uint32_t ui32Base, uint32_t *pui32Data) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT(pui32Data); - - // - // Wait for any active operations to complete. - // - while(HWREG(ui32Base + ONEWIRE_O_CS) & ONEWIRE_CS_BUSY) - { - } - - // - // Copy the data into the provided storage. - // - *pui32Data = HWREG(ui32Base + ONEWIRE_O_DATR); -} - -//***************************************************************************** -// -//! Retrieves data from the 1-Wire interface. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param pui32Data is a pointer to storage to hold the read data. -//! -//! This function reads data from the 1-Wire module if there are no active -//! operations on the bus. Otherwise it returns without reading the data from -//! the module. -//! -//! By protocol definition, bit data defaults to a 1. Thus if a slave did -//! not signal any 0-bit data, this read returns 0xffffffff. -//! -//! \return Returns \b true if a data read was performed, or \b false if the -//! bus was not idle and no data was read. -// -//***************************************************************************** -bool -OneWireDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT(pui32Data); - - // - // If the bus is busy, return without reading. - // - if(HWREG(ui32Base + ONEWIRE_O_CS) & ONEWIRE_CS_BUSY) - { - return(false); - } - - // - // Copy the data into the provided storage. - // - *pui32Data = HWREG(ui32Base + ONEWIRE_O_DATR); - - // - // Notify the caller data was read from the read register. - // - return(true); -} - -//***************************************************************************** -// -//! Clears the 1-Wire module interrupt sources. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! This function clears the specified 1-Wire interrupt sources so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupts from being triggered again immediately upon exit. The -//! \e ui32IntFlags parameter can be a logical OR of any of the following: -//! -//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. -//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a -//! combined write and read operation was set up, the interrupt signals the -//! read is done. -//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. -//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. -//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -OneWireIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA | - ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0); - - // - // Clear the requested interrupts. - // - HWREG(ui32Base + ONEWIRE_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual 1-Wire module interrupt sources. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated 1-Wire interrupt sources. The -//! \e ui32IntFlags parameter can be a logical OR of any of the following: -//! -//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. -//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a -//! combined write and read operation was set up, the interrupt signals the -//! read is done. -//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. -//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. -//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed -//! -//! \return None. -// -//***************************************************************************** -void -OneWireIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA | - ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0); - - // - // Disable the requested interrupts. - // - HWREG(ui32Base + ONEWIRE_O_IM) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Enables individual 1-Wire module interrupt sources. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated 1-Wire interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. The \e ui32IntFlags -//! parameter can be a logical OR of any of the following: -//! -//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. -//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a -//! combined write and read operation was set up, the interrupt signals the -//! read is done. -//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. -//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. -//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed -//! -//! \return None. -// -//***************************************************************************** -void -OneWireIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA | - ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0); - - // - // Enable the requested interrupts. - // - HWREG(ui32Base + ONEWIRE_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets the current 1-Wire interrupt status. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param bMasked is \b false if the raw interrupt status is required or -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the 1-Wire module. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return Returns the masked or raw 1-Wire interrupt status, as a bit field -//! of any of the following values: -//! -//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. -//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. -//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. -//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. -//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed -// -//***************************************************************************** -uint32_t -OneWireIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + ONEWIRE_O_MIS)); - } - else - { - return(HWREG(ui32Base + ONEWIRE_O_RIS)); - } -} - -//***************************************************************************** -// -//! Returns the 1-Wire controller interrupt number. -//! -//! \param ui32Base specifies the 1-Wire module base address. -//! -//! This function returns the interrupt number for the 1-Wire module with the -//! base address passed in the \e ui32Base parameter. -//! -//! \return Returns a 1-Wire interrupt number or 0 if the interrupt does not -//! exist. -// -//***************************************************************************** -static uint32_t -_OneWireIntNumberGet(uint32_t ui32Base) -{ - uint32_t ui32Int; - - ASSERT(ui32Base == ONEWIRE0_BASE); - - ui32Int = 0; - - // - // Find the valid interrupt number for the 1-Wire module. - // - if(CLASS_IS_TM4C129) - { - ui32Int = INT_ONEWIRE0_TM4C129; - } - - return(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the 1-Wire module. -//! -//! \param ui32Base is the base address of the 1-Wire module. -//! \param pfnHandler is a pointer to the function to be called when the -//! 1-Wire interrupt occurs. -//! -//! This function sets the handler to be called when a 1-Wire interrupt occurs. -//! This function enables the global interrupt in the interrupt controller; -//! specific 1-Wire interrupts must be enabled via OneWireIntEnable(). If -//! necessary, it is the interrupt handler's responsibility to clear the -//! interrupt source via OneWireIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT(pfnHandler); - - // - // Get the actual interrupt number for the 1-Wire module. - // - ui32Int = _OneWireIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the 1-Wire peripheral interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the 1-Wire module. -//! -//! \param ui32Base is the base address of the 1-Wire module. -//! -//! This function clears the handler to be called when an 1-Wire interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - - // - // Get the actual interrupt number for the 1-Wire module. - // - ui32Int = _OneWireIntNumberGet(ui32Base); - ASSERT(ui32Int != 0); - - // - // Disable the 1-Wire peripheral interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Disables 1-Wire DMA operations. -//! -//! \param ui32Base is the base address of the 1-Wire module. -//! \param ui32DMAFlags is a bit mask of the DMA features to disable. -//! -//! This function is used to disable 1-Wire DMA features that were enabled -//! by OneWireDMAEnable(). The specified 1-Wire DMA features are disabled. -//! The \e ui32DMAFlags parameter is a combination of the following: -//! -//! - \b ONEWIRE_DMA_BUS_RESET - Issue a 1-Wire bus reset before starting -//! - \b ONEWIRE_DMA_OP_READ - Read after each module transaction -//! - \b ONEWIRE_DMA_OP_MULTI_WRITE - Write after each previous write -//! - \b ONEWIRE_DMA_OP_MULTI_READ - Read after each previous read -//! - \b ONEWIRE_DMA_MODE_SG - Start DMA on enable then repeat on each -//! completion -//! - \b ONEWIRE_DMA_OP_SZ_8 - Bus read/write of 8 bits -//! - \b ONEWIRE_DMA_OP_SZ_16 - Bus read/write of 16 bits -//! - \b ONEWIRE_DMA_OP_SZ_32 - Bus read/write of 32 bits -//! -//! \return None. -// -//***************************************************************************** -void -OneWireDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT(ui32DMAFlags > 0); - - // - // Clear the transaction size bits - // - HWREG(ui32Base + ONEWIRE_O_CS) = (HWREG(ui32Base + ONEWIRE_O_CS) & - ~(ONEWIRE_TXN_MASK)); - - // - // Disable the DMA features as requested. - // - HWREG(ui32Base + ONEWIRE_O_DMA) &= ~(ui32DMAFlags & 0xff); -} - -//***************************************************************************** -// -//! Enables 1-Wire DMA operations. -//! -//! \param ui32Base is the base address of the 1-Wire module. -//! \param ui32DMAFlags is a bit mask of the DMA features to enable. -//! -//! This function enables the specified 1-Wire DMA features. The 1-Wire module -//! can be configured for write operations, read operations, small write and -//! read operations, and scatter-gather support of mixed operations. -//! -//! The \e ui32DMAFlags parameter is a combination of the following: -//! -//! - \b ONEWIRE_DMA_BUS_RESET - Issue a 1-Wire bus reset before starting -//! - \b ONEWIRE_DMA_OP_READ - Read after each module transaction -//! - \b ONEWIRE_DMA_OP_MULTI_WRITE - Write after each previous write -//! - \b ONEWIRE_DMA_OP_MULTI_READ - Read after each previous read -//! - \b ONEWIRE_DMA_MODE_SG - Start DMA on enable then repeat on each -//! completion -//! - \b ONEWIRE_DMA_OP_SZ_8 - Bus read/write of 8 bits -//! - \b ONEWIRE_DMA_OP_SZ_16 - Bus read/write of 16 bits -//! - \b ONEWIRE_DMA_OP_SZ_32 - Bus read/write of 32 bits -//! -//! \note The uDMA controller must be properly configured before DMA can be -//! used with the 1-Wire module. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT(ui32DMAFlags > 0); - - // - // set up the transaction size. - // - HWREG(ui32Base + ONEWIRE_O_CS) = ((HWREG(ui32Base + ONEWIRE_O_CS) & - ~(ONEWIRE_TXN_MASK)) | - (ui32DMAFlags >> 8)); - - // - // Enable DMA with the parameters provided. - // - HWREG(ui32Base + ONEWIRE_O_DMA) = (ui32DMAFlags & 0xf); - - // - // If a read transaction was requested, seed the write data register. This - // will trigger the DMA reads to start. This should not be done for - // scatter-gather operations. - // - if((ui32DMAFlags & (ONEWIRE_DMA_DMAOP_RDSNG | ONEWIRE_DMA_DMAOP_RDMUL)) && - !(ui32DMAFlags & ONEWIRE_DMA_SG)) - { - // - // Workaround for Snowflake DMA receive trigger errata. - // - if(CLASS_IS_TM4C129) - { - SysCtlDelay(9); - } - - // - // Write DATW to trigger DMA receive start. - // - HWREG(ui32Base + ONEWIRE_O_DATW) = 0xffffffff; - } -} - -//***************************************************************************** -// -//! Performs a 1-Wire protocol transaction on the bus. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param ui32OpMode sets the transaction type. -//! \param ui32Data is the data for a write operation. -//! \param ui32BitCnt specifies the number of valid bits (1-32) for the -//! operation. -//! -//! This function performs a 1-Wire protocol transaction, read and/or write, on -//! the bus. The application should confirm the bus is idle before starting a -//! read or write transaction. -//! -//! The \e ui32OpMode defines the activity for the bus operations and is a -//! logical OR of the following: -//! -//! - \b ONEWIRE_OP_RESET - Indicates the operation should be started with -//! a bus reset. -//! - \b ONEWIRE_OP_WRITE - A write operation -//! - \b ONEWIRE_OP_READ - A read operation -//! -//! \note If both a read and write operation are requested, the write will be -//! performed prior to the read. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireTransaction(uint32_t ui32Base, uint32_t ui32OpMode, uint32_t ui32Data, - uint32_t ui32BitCnt) -{ - uint32_t ui32Transaction; - - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT((ui32OpMode & (ONEWIRE_OP_RESET | ONEWIRE_OP_WRITE | - ONEWIRE_OP_READ)) > 0); - ASSERT((ui32BitCnt >= 1) && (ui32BitCnt <= 32)); - - // - // Read the control register and clear any transaction related - // bit fields. - // - ui32Transaction = HWREG(ui32Base + ONEWIRE_O_CS) & ~(ONEWIRE_TXN_MASK); - - // - // Add the user specified operation flags. - // - ui32Transaction |= (ui32OpMode & (ONEWIRE_OP_RESET | ONEWIRE_OP_WRITE | - ONEWIRE_OP_READ)); - - // - // set up for a read or write transaction. - // - if(ui32Transaction & (ONEWIRE_CS_OP_WR | ONEWIRE_CS_OP_RD)) - { - // - // Configure the 1-Wire module for the transaction size. This is - // specified as 1-4 bytes and the specific bit size for the last - // byte therein. - // - ui32Transaction |= ((((ui32BitCnt % 8) ? (ui32BitCnt / 8) + 1 : - (ui32BitCnt / 8)) - 1) << - ONEWIRE_TXN_SIZE_LSHIFT); - ui32Transaction |= ((ui32BitCnt % 8) << ONEWIRE_TXN_BSIZE_LSHIFT); - - // - // Write specific setup. - // - if(ui32Transaction & ONEWIRE_CS_OP_WR) - { - // - // Load the data into the write register. - // - HWREG(ui32Base + ONEWIRE_O_DATW) = ui32Data; - } - } - - // - // Start the transaction. - // - HWREG(ui32Base + ONEWIRE_O_CS) = ui32Transaction; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/onewire.h b/bsp/tm4c129x-dk/libraries/driverlib/onewire.h deleted file mode 100644 index 731f3f99bbc21a51efe1418a7813a52b591410b7..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/onewire.h +++ /dev/null @@ -1,307 +0,0 @@ -//***************************************************************************** -// -// onewire.h - Prototypes for the OneWire Driver. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_ONEWIRE_H__ -#define __DRIVERLIB_ONEWIRE_H__ - -//***************************************************************************** -// -//! \addtogroup onewire_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines used in the OneWireInit() function call. -// -//***************************************************************************** - -// -// This define is used in initialization to request standard speed bus -// timings. This is the default. -// -#define ONEWIRE_INIT_SPD_STD 0x00000000 - -// -// This define is used in initialization to request overdrive speed bus -// timings. -// -#define ONEWIRE_INIT_SPD_OD 0x00000020 - -// -// This define is used in initialization to request standard read sampling -// timing (2us for ONEWIRE_INIT_SPD_OD and 16us for ONEWIRE_INIT_SPD_STD). -// This is the default. -// -#define ONEWIRE_INIT_READ_STD 0x00000000 - -// -// This define is used in initialization to request late read sampling -// timing (7us for ONEWIRE_INIT_SPD_OD and 50us for ONEWIRE_INIT_SPD_STD). -// -#define ONEWIRE_INIT_READ_LATE 0x00000040 - -// -// This define is used in initialization to request a standard -// Answer-to-Reset (presence detect) monitor. This is the default. -// -#define ONEWIRE_INIT_ATR 0x00000000 - -// -// This define is used in initialization to request no Answer-to-Reset -// (presence detect) monitor. The module will delay operations after a bus -// reset for the expected presence detect period in this case. -// -#define ONEWIRE_INIT_NO_ATR 0x00000080 - -// -// This define is used in initialization to request standard signal polarity -// on the 1-Wire bus (pin is driven low to drive bus low). This is the -// default. -// -#define ONEWIRE_INIT_STD_POL 0x00000000 - -// -// This define is used in initialization to request alternate signal polarity -// on the 1-Wire bus (pin is driven high to drive bus low). -// -#define ONEWIRE_INIT_ALT_POL 0x40000000 - -// -// This define is used in initialization to request normal 1-Wire operational -// mode. This is the default. -// -#define ONEWIRE_INIT_1_WIRE_CFG 0x00000000 - -// -// This define is used in initialization to request a 2 pin operational -// mode where one pin is used exclusively for TX operations and the other -// for RX. -// -#define ONEWIRE_INIT_2_WIRE_CFG 0x80000000 - -//***************************************************************************** -// -// Defines for bus status conditions. These values can be returned by -// OneWireBusStatus(). -// -//***************************************************************************** - -// -// This will be set if the bus is busy handling a Read, Write or -// Reset activity. -// -#define ONEWIRE_BUS_STATUS_BUSY 0x00000100 - -// -// This will be set if the module did not detect any slave presence pulses -// after a bus reset. -// -#define ONEWIRE_BUS_STATUS_NO_SLAVE \ - 0x00000200 - -// -// This will be set if the bus is being held low outside of a normal Read, -// Write or Reset activity. -// -#define ONEWIRE_BUS_STATUS_STUCK \ - 0x00000400 - -//***************************************************************************** -// -// OneWire operation modes used with OneWireTransaction(). -// -//***************************************************************************** - -// -// This mode flag indicates a single reset should be issued prior to a write -// and/or read operation. -// -#define ONEWIRE_OP_RESET 0x00000001 - -// -// This mode flag indicates a read operation. -// -#define ONEWIRE_OP_READ 0x00000002 - -// -// This mode flag indicates a write operation. -// -#define ONEWIRE_OP_WRITE 0x00000004 - -//***************************************************************************** -// -// OneWire DMA used with OneWireDMAEnable(). -// -//***************************************************************************** - -// -// This indicates the DMA should issue a 1-Wire bus reset before starting. -// -#define ONEWIRE_DMA_BUS_RESET 0x00000001 - -// -// The DMA operation will be a single Read after each module transaction. -// -#define ONEWIRE_DMA_OP_READ 0x00000002 - -// -// The DMA will write values to the 1-Wire interface as each previous DMA -// write operation completes. -// -#define ONEWIRE_DMA_OP_MULTI_WRITE \ - 0x00000004 - -// -// The DMA will read values from the 1-Wire interface as each previous DMA -// read operation completes. -// -#define ONEWIRE_DMA_OP_MULTI_READ \ - 0x00000006 - -// -// This Scatter Gather DMA mode is paired with ONEWIRE_DMA_OP_READ to instruct -// the 1-Wire DMA to initiate an operation at the start of and then on each -// transition completion thereafter. -// -#define ONEWIRE_DMA_MODE_SG 0x00000008 - -// -// DMA expects a Read/Write bus operation size of 8 bits. This should match -// the uDMA channel setup. -// -#define ONEWIRE_DMA_OP_SZ_8 0x00000000 - -// -// DMA expects a Read/Write bus operation size of 16 bits. This should match -// the uDMA channel setup. -// -#define ONEWIRE_DMA_OP_SZ_16 0x00000800 - -// -// DMA expects a Read/Write bus operation size of 32 bits. This should match -// the uDMA channel setup. -// -#define ONEWIRE_DMA_OP_SZ_32 0x00001800 - -//***************************************************************************** -// -// OneWire interrupt defines. Use in calls to OneWireIntEnable(), -// OneWireIntDisable(), OneWireIntClear() and returned by OneWireIntStatus(). -// -//***************************************************************************** - -// -// This interrupt indicates a bus reset has just completed. -// -#define ONEWIRE_INT_RESET_DONE 0x00000001 - -// -// The interrupt indicates a Read or Write master initiated operation -// has just completed. -// -#define ONEWIRE_INT_OP_DONE 0x00000002 - -// -// This interrupt indicates that no presence detect was signaled by a slave -// on the bus after a reset. -// -#define ONEWIRE_INT_NO_SLAVE 0x00000004 - -// -// This interrupt indicates the bus is being held low outside of normal -// operations. -// -#define ONEWIRE_INT_STUCK 0x00000008 - -// -// This interrupt indicates a OneWire DMA operation has completed. -// -#define ONEWIRE_INT_DMA_DONE 0x00000010 - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void OneWireBusReset(uint32_t ui32Base); -extern uint32_t OneWireBusStatus(uint32_t ui32Base); -extern void OneWireDataGet(uint32_t u3i2Base, uint32_t *pui32Data); -extern bool OneWireDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data); -extern void OneWireDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); -extern void OneWireDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); -extern void OneWireInit(uint32_t ui32Base, uint32_t ui32InitFlags); -extern void OneWireIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void OneWireIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void OneWireIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void OneWireIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void OneWireIntUnregister(uint32_t ui32Base); -extern uint32_t OneWireIntStatus(uint32_t ui32Base, bool bMasked); -extern void OneWireTransaction(uint32_t ui32Base, uint32_t ui32OpFlags, - uint32_t ui32Data, uint32_t ui32BitCnt); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_ONEWIRE_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/pin_map.h b/bsp/tm4c129x-dk/libraries/driverlib/pin_map.h deleted file mode 100644 index 9d686098616d980c55f9614161868bc3ef7e6a2b..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/pin_map.h +++ /dev/null @@ -1,20953 +0,0 @@ -//***************************************************************************** -// -// pin_map.h - Mapping of peripherals to pins for all parts. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_PIN_MAP_H__ -#define __DRIVERLIB_PIN_MAP_H__ - -//***************************************************************************** -// -// TM4C1230C3PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1230C3PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1230C3PM - -//***************************************************************************** -// -// TM4C1230D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1230D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1230D5PM - -//***************************************************************************** -// -// TM4C1230E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1230E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1230E6PM - -//***************************************************************************** -// -// TM4C1230H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1230H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1230H6PM - -//***************************************************************************** -// -// TM4C1231C3PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231C3PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1231C3PM - -//***************************************************************************** -// -// TM4C1231D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1231D5PM - -//***************************************************************************** -// -// TM4C1231D5PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231D5PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1231D5PZ - -//***************************************************************************** -// -// TM4C1231E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1231E6PM - -//***************************************************************************** -// -// TM4C1231E6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231E6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1231E6PZ - -//***************************************************************************** -// -// TM4C1231H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1231H6PM - -//***************************************************************************** -// -// TM4C1231H6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231H6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1231H6PZ - -//***************************************************************************** -// -// TM4C1232C3PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1232C3PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1232C3PM - -//***************************************************************************** -// -// TM4C1232D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1232D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1232D5PM - -//***************************************************************************** -// -// TM4C1232E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1232E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1232E6PM - -//***************************************************************************** -// -// TM4C1232H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1232H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1232H6PM - -//***************************************************************************** -// -// TM4C1233C3PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233C3PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1233C3PM - -//***************************************************************************** -// -// TM4C1233D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1233D5PM - -//***************************************************************************** -// -// TM4C1233D5PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233D5PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1233D5PZ - -//***************************************************************************** -// -// TM4C1233E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1233E6PM - -//***************************************************************************** -// -// TM4C1233E6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233E6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1233E6PZ - -//***************************************************************************** -// -// TM4C1233H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1233H6PM - -//***************************************************************************** -// -// TM4C1233H6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233H6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1233H6PZ - -//***************************************************************************** -// -// TM4C1236D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1236D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#endif // PART_TM4C1236D5PM - -//***************************************************************************** -// -// TM4C1236E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1236E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#endif // PART_TM4C1236E6PM - -//***************************************************************************** -// -// TM4C1236H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1236H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#endif // PART_TM4C1236H6PM - -//***************************************************************************** -// -// TM4C1237D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#endif // PART_TM4C1237D5PM - -//***************************************************************************** -// -// TM4C1237D5PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237D5PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1237D5PZ - -//***************************************************************************** -// -// TM4C1237E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#endif // PART_TM4C1237E6PM - -//***************************************************************************** -// -// TM4C1237E6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237E6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1237E6PZ - -//***************************************************************************** -// -// TM4C1237H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#endif // PART_TM4C1237H6PM - -//***************************************************************************** -// -// TM4C1237H6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237H6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1237H6PZ - -//***************************************************************************** -// -// TM4C123AE6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123AE6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C123AE6PM - -//***************************************************************************** -// -// TM4C123AH6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123AH6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C123AH6PM - -//***************************************************************************** -// -// TM4C123BE6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BE6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C123BE6PM - -//***************************************************************************** -// -// TM4C123BE6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BE6PZ - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#endif // PART_TM4C123BE6PZ - -//***************************************************************************** -// -// TM4C123BH6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BH6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C123BH6PM - -//***************************************************************************** -// -// TM4C123BH6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BH6PZ - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#endif // PART_TM4C123BH6PZ - -//***************************************************************************** -// -// TM4C123FE6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123FE6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#endif // PART_TM4C123FE6PM - -//***************************************************************************** -// -// TM4C123FH6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123FH6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#endif // PART_TM4C123FH6PM - -//***************************************************************************** -// -// TM4C123GE6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GE6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#endif // PART_TM4C123GE6PM - -//***************************************************************************** -// -// TM4C123GE6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GE6PZ - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#endif // PART_TM4C123GE6PZ - -//***************************************************************************** -// -// TM4C123GH6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GH6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#endif // PART_TM4C123GH6PM - -//***************************************************************************** -// -// TM4C123GH6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GH6PZ - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#endif // PART_TM4C123GH6PZ - -//***************************************************************************** -// -// TM4C1231H6PGE Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231H6PGE - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_T5CCP0 0x000D0807 - -#endif // PART_TM4C1231H6PGE - -//***************************************************************************** -// -// TM4C1233H6PGE Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233H6PGE - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_T5CCP0 0x000D0807 - -#endif // PART_TM4C1233H6PGE - -//***************************************************************************** -// -// TM4C1237H6PGE Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237H6PGE - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_T5CCP0 0x000D0807 - -#endif // PART_TM4C1237H6PGE - -//***************************************************************************** -// -// TM4C123BH6PGE Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BH6PGE - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_M0FAULT0 0x00091006 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_M0FAULT1 0x00091406 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_M0FAULT2 0x00091806 -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_M0FAULT3 0x00091C06 -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_M0PWM4 0x000B1802 -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_M0PWM5 0x000B1C02 -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_M0PWM6 0x000C0802 -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_M0PWM7 0x000C0C02 -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_M1PWM4 0x000C1002 -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_M1PWM5 0x000C1402 -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_M1PWM6 0x000C1802 -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_M1PWM7 0x000C1C02 -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_M0PWM0 0x000D0001 -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_M0PWM1 0x000D0401 -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_M0PWM2 0x000D0801 -#define GPIO_PP2_T5CCP0 0x000D0807 - -#endif // PART_TM4C123BH6PGE - -//***************************************************************************** -// -// TM4C123BH6ZRB Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BH6ZRB - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_M0FAULT0 0x00091006 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_M0FAULT1 0x00091406 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_M0FAULT2 0x00091806 -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_M0FAULT3 0x00091C06 -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_M0PWM4 0x000B1802 -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_M0PWM5 0x000B1C02 -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_M0PWM6 0x000C0802 -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_M0PWM7 0x000C0C02 -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_M1PWM4 0x000C1002 -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_M1PWM5 0x000C1402 -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_M1PWM6 0x000C1802 -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_M1PWM7 0x000C1C02 -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_M0PWM0 0x000D0001 -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_M0PWM1 0x000D0401 -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_M0PWM2 0x000D0801 -#define GPIO_PP2_T5CCP0 0x000D0807 - -#define GPIO_PP3_M0PWM3 0x000D0C01 -#define GPIO_PP3_T5CCP1 0x000D0C07 - -#define GPIO_PP4_M0PWM4 0x000D1001 -#define GPIO_PP4_WT0CCP0 0x000D1007 - -#define GPIO_PP5_M0PWM5 0x000D1401 -#define GPIO_PP5_WT0CCP1 0x000D1407 - -#define GPIO_PP6_M0PWM6 0x000D1801 -#define GPIO_PP6_WT1CCP0 0x000D1807 - -#define GPIO_PP7_M0PWM7 0x000D1C01 -#define GPIO_PP7_WT1CCP1 0x000D1C07 - -#define GPIO_PQ0_M1PWM0 0x000E0001 -#define GPIO_PQ0_WT2CCP0 0x000E0007 - -#define GPIO_PQ1_M1PWM1 0x000E0401 -#define GPIO_PQ1_WT2CCP1 0x000E0407 - -#define GPIO_PQ2_M1PWM2 0x000E0801 -#define GPIO_PQ2_WT3CCP0 0x000E0807 - -#define GPIO_PQ3_M1PWM3 0x000E0C01 -#define GPIO_PQ3_WT3CCP1 0x000E0C07 - -#define GPIO_PQ4_M1PWM4 0x000E1001 -#define GPIO_PQ4_WT4CCP0 0x000E1007 - -#define GPIO_PQ5_M1PWM5 0x000E1401 -#define GPIO_PQ5_WT4CCP1 0x000E1407 - -#define GPIO_PQ6_M1PWM6 0x000E1801 -#define GPIO_PQ6_WT5CCP0 0x000E1807 - -#define GPIO_PQ7_M1PWM7 0x000E1C01 -#define GPIO_PQ7_WT5CCP1 0x000E1C07 - -#endif // PART_TM4C123BH6ZRB - -//***************************************************************************** -// -// TM4C123GH6PGE Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GH6PGE - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_M0FAULT0 0x00091006 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_M0FAULT1 0x00091406 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_M0FAULT2 0x00091806 -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_M0FAULT3 0x00091C06 -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_M0PWM4 0x000B1802 -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_M0PWM5 0x000B1C02 -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_M0PWM6 0x000C0802 -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_M0PWM7 0x000C0C02 -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_M1PWM4 0x000C1002 -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_M1PWM5 0x000C1402 -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_M1PWM6 0x000C1802 -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_M1PWM7 0x000C1C02 -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_M0PWM0 0x000D0001 -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_M0PWM1 0x000D0401 -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_M0PWM2 0x000D0801 -#define GPIO_PP2_T5CCP0 0x000D0807 - -#endif // PART_TM4C123GH6PGE - -//***************************************************************************** -// -// TM4C123GH6ZRB Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GH6ZRB - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_M0FAULT0 0x00091006 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_M0FAULT1 0x00091406 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_M0FAULT2 0x00091806 -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_M0FAULT3 0x00091C06 -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_M0PWM4 0x000B1802 -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_M0PWM5 0x000B1C02 -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_M0PWM6 0x000C0802 -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_M0PWM7 0x000C0C02 -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_M1PWM4 0x000C1002 -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_M1PWM5 0x000C1402 -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_M1PWM6 0x000C1802 -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_M1PWM7 0x000C1C02 -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_M0PWM0 0x000D0001 -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_M0PWM1 0x000D0401 -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_M0PWM2 0x000D0801 -#define GPIO_PP2_T5CCP0 0x000D0807 - -#define GPIO_PP3_M0PWM3 0x000D0C01 -#define GPIO_PP3_T5CCP1 0x000D0C07 - -#define GPIO_PP4_M0PWM4 0x000D1001 -#define GPIO_PP4_WT0CCP0 0x000D1007 - -#define GPIO_PP5_M0PWM5 0x000D1401 -#define GPIO_PP5_WT0CCP1 0x000D1407 - -#define GPIO_PP6_M0PWM6 0x000D1801 -#define GPIO_PP6_WT1CCP0 0x000D1807 - -#define GPIO_PP7_M0PWM7 0x000D1C01 -#define GPIO_PP7_WT1CCP1 0x000D1C07 - -#define GPIO_PQ0_M1PWM0 0x000E0001 -#define GPIO_PQ0_WT2CCP0 0x000E0007 - -#define GPIO_PQ1_M1PWM1 0x000E0401 -#define GPIO_PQ1_WT2CCP1 0x000E0407 - -#define GPIO_PQ2_M1PWM2 0x000E0801 -#define GPIO_PQ2_WT3CCP0 0x000E0807 - -#define GPIO_PQ3_M1PWM3 0x000E0C01 -#define GPIO_PQ3_WT3CCP1 0x000E0C07 - -#define GPIO_PQ4_M1PWM4 0x000E1001 -#define GPIO_PQ4_WT4CCP0 0x000E1007 - -#define GPIO_PQ5_M1PWM5 0x000E1401 -#define GPIO_PQ5_WT4CCP1 0x000E1407 - -#define GPIO_PQ6_M1PWM6 0x000E1801 -#define GPIO_PQ6_WT5CCP0 0x000E1807 - -#define GPIO_PQ7_M1PWM7 0x000E1C01 -#define GPIO_PQ7_WT5CCP1 0x000E1C07 - -#endif // PART_TM4C123GH6ZRB - -//***************************************************************************** -// -// TM4C123GH6ZXR Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GH6ZXR - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_M0FAULT0 0x00091006 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_M0FAULT1 0x00091406 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_M0FAULT2 0x00091806 -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_M0FAULT3 0x00091C06 -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_M0PWM4 0x000B1802 -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_M0PWM5 0x000B1C02 -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_M0PWM6 0x000C0802 -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_M0PWM7 0x000C0C02 -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_M1PWM4 0x000C1002 -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_M1PWM5 0x000C1402 -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_M1PWM6 0x000C1802 -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_M1PWM7 0x000C1C02 -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_M0PWM0 0x000D0001 -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_M0PWM1 0x000D0401 -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_M0PWM2 0x000D0801 -#define GPIO_PP2_T5CCP0 0x000D0807 - -#define GPIO_PP3_M0PWM3 0x000D0C01 -#define GPIO_PP3_T5CCP1 0x000D0C07 - -#define GPIO_PP4_M0PWM4 0x000D1001 -#define GPIO_PP4_WT0CCP0 0x000D1007 - -#define GPIO_PP5_M0PWM5 0x000D1401 -#define GPIO_PP5_WT0CCP1 0x000D1407 - -#define GPIO_PP6_M0PWM6 0x000D1801 -#define GPIO_PP6_WT1CCP0 0x000D1807 - -#define GPIO_PP7_M0PWM7 0x000D1C01 -#define GPIO_PP7_WT1CCP1 0x000D1C07 - -#define GPIO_PQ0_M1PWM0 0x000E0001 -#define GPIO_PQ0_WT2CCP0 0x000E0007 - -#define GPIO_PQ1_M1PWM1 0x000E0401 -#define GPIO_PQ1_WT2CCP1 0x000E0407 - -#define GPIO_PQ2_M1PWM2 0x000E0801 -#define GPIO_PQ2_WT3CCP0 0x000E0807 - -#define GPIO_PQ3_M1PWM3 0x000E0C01 -#define GPIO_PQ3_WT3CCP1 0x000E0C07 - -#define GPIO_PQ4_M1PWM4 0x000E1001 -#define GPIO_PQ4_WT4CCP0 0x000E1007 - -#define GPIO_PQ5_M1PWM5 0x000E1401 -#define GPIO_PQ5_WT4CCP1 0x000E1407 - -#define GPIO_PQ6_M1PWM6 0x000E1801 -#define GPIO_PQ6_WT5CCP0 0x000E1807 - -#define GPIO_PQ7_M1PWM7 0x000E1C01 -#define GPIO_PQ7_WT5CCP1 0x000E1C07 - -#endif // PART_TM4C123GH6ZXR - -//***************************************************************************** -// -// TM4C1290NCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1290NCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#endif // PART_TM4C1290NCPDT - -//***************************************************************************** -// -// TM4C1290NCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1290NCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 - -#define GPIO_PS7_T5CCP1 0x00101C03 - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C1290NCZAD - -//***************************************************************************** -// -// TM4C1292NCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1292NCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#endif // PART_TM4C1292NCPDT - -//***************************************************************************** -// -// TM4C1292NCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1292NCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_EN0TXER 0x000C180E - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_EN0TXEN 0x000F1C0E - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_EN0TXD0 0x0010100E - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_EN0TXD1 0x0010140E - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_EN0RXER 0x0010180E - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_EN0RXDV 0x00101C0E - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_EN0RXD0 0x0011000E - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_EN0RXD1 0x0011040E - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C1292NCZAD - -//***************************************************************************** -// -// TM4C1294KCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1294KCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#endif // PART_TM4C1294KCPDT - -//***************************************************************************** -// -// TM4C1294NCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1294NCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#endif // PART_TM4C1294NCPDT - -//***************************************************************************** -// -// TM4C1294NCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1294NCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 - -#define GPIO_PS7_T5CCP1 0x00101C03 - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C1294NCZAD - -//***************************************************************************** -// -// TM4C1297NCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1297NCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C1297NCZAD - -//***************************************************************************** -// -// TM4C1299KCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1299KCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C1299KCZAD - -//***************************************************************************** -// -// TM4C1299NCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1299NCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C1299NCZAD - -//***************************************************************************** -// -// TM4C129CNCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129CNCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#endif // PART_TM4C129CNCPDT - -//***************************************************************************** -// -// TM4C129CNCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129CNCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 - -#define GPIO_PS7_T5CCP1 0x00101C03 - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C129CNCZAD - -//***************************************************************************** -// -// TM4C129DNCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129DNCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#endif // PART_TM4C129DNCPDT - -//***************************************************************************** -// -// TM4C129DNCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129DNCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_EN0TXER 0x000C180E - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_EN0TXEN 0x000F1C0E - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_EN0TXD0 0x0010100E - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_EN0TXD1 0x0010140E - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_EN0RXER 0x0010180E - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_EN0RXDV 0x00101C0E - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_EN0RXD0 0x0011000E - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_EN0RXD1 0x0011040E - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C129DNCZAD - -//***************************************************************************** -// -// TM4C129EKCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129EKCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#endif // PART_TM4C129EKCPDT - -//***************************************************************************** -// -// TM4C129ENCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129ENCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#endif // PART_TM4C129ENCPDT - -//***************************************************************************** -// -// TM4C129ENCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129ENCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 - -#define GPIO_PS7_T5CCP1 0x00101C03 - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C129ENCZAD - -//***************************************************************************** -// -// TM4C129LNCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129LNCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C129LNCZAD - -//***************************************************************************** -// -// TM4C129XKCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129XKCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 -#define GPIO_PE3_OWIRE 0x00040C05 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_OWIRE 0x00061005 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_OWALT 0x00061405 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_OWIRE 0x00061805 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_OWIRE 0x00061C05 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_EN0TXER 0x000C180E -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_OWIRE 0x000D1004 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_OWALT 0x000D1404 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PP7_OWIRE 0x000D1C05 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_EN0TXEN 0x000F1C0E -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_EN0TXD0 0x0010100E -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_EN0TXD1 0x0010140E -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_EN0RXER 0x0010180E -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_EN0RXDV 0x00101C0E -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_EN0RXD0 0x0011000E -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_EN0RXD1 0x0011040E -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C129XKCZAD - -//***************************************************************************** -// -// TM4C129XNCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129XNCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 -#define GPIO_PE3_OWIRE 0x00040C05 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_OWIRE 0x00061005 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_OWALT 0x00061405 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_OWIRE 0x00061805 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_OWIRE 0x00061C05 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_EN0TXER 0x000C180E -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_OWIRE 0x000D1004 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_OWALT 0x000D1404 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PP7_OWIRE 0x000D1C05 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_EN0TXEN 0x000F1C0E -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_EN0TXD0 0x0010100E -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_EN0TXD1 0x0010140E -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_EN0RXER 0x0010180E -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_EN0RXDV 0x00101C0E -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_EN0RXD0 0x0011000E -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_EN0RXD1 0x0011040E -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C129XNCZAD - -#endif // __DRIVERLIB_PIN_MAP_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/pwm.c b/bsp/tm4c129x-dk/libraries/driverlib/pwm.c deleted file mode 100644 index 54fbe52e5c02265edc5a47aec54ddc9f4a2ca2f4..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/pwm.c +++ /dev/null @@ -1,2162 +0,0 @@ -//***************************************************************************** -// -// pwm.c - API for the PWM modules -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup pwm_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_pwm.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/pwm.h" - -//***************************************************************************** -// -// Misc macros for manipulating the encoded generator and output defines used -// by the API. -// -//***************************************************************************** -#define PWM_GEN_BADDR(_mod_, _gen_) \ - ((_mod_) + (_gen_)) -#define PWM_GEN_EXT_BADDR(_mod_, _gen_) \ - ((_mod_) + PWM_GEN_EXT_0 + \ - ((_gen_) - PWM_GEN_0) * 2) -#define PWM_OUT_BADDR(_mod_, _out_) \ - ((_mod_) + ((_out_) & 0xFFFFFFC0)) -#define PWM_IS_OUTPUT_ODD(_out_) \ - ((_out_) & 0x00000001) - -//***************************************************************************** -// -//! \internal -//! Checks a PWM generator number. -//! -//! \param ui32Gen is the generator number. -//! -//! This function determines if a PWM generator number is valid. -//! -//! \return Returnes \b true if the generator number is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_PWMGenValid(uint32_t ui32Gen) -{ - return((ui32Gen == PWM_GEN_0) || (ui32Gen == PWM_GEN_1) || - (ui32Gen == PWM_GEN_2) || (ui32Gen == PWM_GEN_3)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Checks a PWM output number. -//! -//! \param ui32PWMOut is the output number. -//! -//! This function determines if a PWM output number is valid. -//! -//! \return Returns \b true if the output number is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_PWMOutValid(uint32_t ui32PWMOut) -{ - return((ui32PWMOut == PWM_OUT_0) || (ui32PWMOut == PWM_OUT_1) || - (ui32PWMOut == PWM_OUT_2) || (ui32PWMOut == PWM_OUT_3) || - (ui32PWMOut == PWM_OUT_4) || (ui32PWMOut == PWM_OUT_5) || - (ui32PWMOut == PWM_OUT_6) || (ui32PWMOut == PWM_OUT_7)); -} -#endif - -//***************************************************************************** -// -//! Configures a PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to configure. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Config is the configuration for the PWM generator. -//! -//! This function is used to set the mode of operation for a PWM generator. -//! The counting mode, synchronization mode, and debug behavior are all -//! configured. After configuration, the generator is left in the disabled -//! state. -//! -//! A PWM generator can count in two different modes: count down mode or count -//! up/down mode. In count down mode, it counts from a value down to zero, -//! and then resets to the preset value, producing left-aligned PWM -//! signals (that is, the rising edge of the two PWM signals produced by the -//! generator occur at the same time). In count up/down mode, it counts up -//! from zero to the preset value, counts back down to zero, and then repeats -//! the process, producing center-aligned PWM signals (that is, -//! the middle of the high/low period of the PWM signals produced by the -//! generator occurs at the same time). -//! -//! When the PWM generator parameters (period and pulse width) are modified, -//! their effect on the output PWM signals can be delayed. In synchronous -//! mode, the parameter updates are not applied until a synchronization event -//! occurs. This mode allows multiple parameters to be modified and take -//! effect simultaneously, instead of one at a time. Additionally, parameters -//! to multiple PWM generators in synchronous mode can be updated -//! simultaneously, allowing them to be treated as if they were a unified -//! generator. In non-synchronous mode, the parameter updates are not delayed -//! until a synchronization event. In either mode, the parameter updates only -//! occur when the counter is at zero to help prevent oddly formed PWM signals -//! during the update (that is, a PWM pulse that is too short or too long). -//! -//! The PWM generator can either pause or continue running when the processor -//! is stopped via the debugger. If configured to pause, it continues to -//! count until it reaches zero, at which point it pauses until the -//! processor is restarted. If configured to continue running, it keeps -//! counting as if nothing had happened. -//! -//! The \e ui32Config parameter contains the desired configuration. It is the -//! logical OR of the following: -//! -//! - \b PWM_GEN_MODE_DOWN or \b PWM_GEN_MODE_UP_DOWN to specify the counting -//! mode -//! - \b PWM_GEN_MODE_SYNC or \b PWM_GEN_MODE_NO_SYNC to specify the counter -//! load and comparator update synchronization mode -//! - \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug -//! behavior -//! - \b PWM_GEN_MODE_GEN_NO_SYNC, \b PWM_GEN_MODE_GEN_SYNC_LOCAL, or -//! \b PWM_GEN_MODE_GEN_SYNC_GLOBAL to specify the update synchronization -//! mode for generator counting mode changes -//! - \b PWM_GEN_MODE_DB_NO_SYNC, \b PWM_GEN_MODE_DB_SYNC_LOCAL, or -//! \b PWM_GEN_MODE_DB_SYNC_GLOBAL to specify the deadband parameter -//! synchronization mode -//! - \b PWM_GEN_MODE_FAULT_LATCHED or \b PWM_GEN_MODE_FAULT_UNLATCHED to -//! specify whether fault conditions are latched or not -//! - \b PWM_GEN_MODE_FAULT_MINPER or \b PWM_GEN_MODE_FAULT_NO_MINPER to -//! specify whether minimum fault period support is required -//! - \b PWM_GEN_MODE_FAULT_EXT or \b PWM_GEN_MODE_FAULT_LEGACY to specify -//! whether extended fault source selection support is enabled or not -//! -//! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the -//! minimum duration of a PWM fault signal. Faults are signaled for at -//! least this time even if the external fault pin deasserts earlier. Care -//! should be taken when using this mode because during the fault signal -//! period, the fault interrupt from the PWM generator remains asserted. The -//! fault interrupt handler may, therefore, reenter immediately if it exits -//! prior to expiration of the fault timer. -//! -//! \note Changes to the counter mode affect the period of the PWM signals -//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after -//! any changes to the counter mode of a generator. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Compute the generator's base address. - // - ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); - - // - // Change the global configuration of the generator. - // - HWREG(ui32Gen + PWM_O_X_CTL) = ((HWREG(ui32Gen + PWM_O_X_CTL) & - ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG | - PWM_X_CTL_LATCH | PWM_X_CTL_MINFLTPER | - PWM_X_CTL_FLTSRC | - PWM_X_CTL_DBFALLUPD_M | - PWM_X_CTL_DBRISEUPD_M | - PWM_X_CTL_DBCTLUPD_M | - PWM_X_CTL_GENBUPD_M | - PWM_X_CTL_GENAUPD_M | - PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD | - PWM_X_CTL_CMPBUPD)) | ui32Config); - - // - // Set the individual PWM generator controls. - // - if(ui32Config & PWM_X_CTL_MODE) - { - // - // In up/down count mode, set the signal high on up count comparison - // and low on down count comparison (that is, center align the - // signals). - // - HWREG(ui32Gen + PWM_O_X_GENA) = (PWM_X_GENA_ACTCMPAU_ONE | - PWM_X_GENA_ACTCMPAD_ZERO); - HWREG(ui32Gen + PWM_O_X_GENB) = (PWM_X_GENB_ACTCMPBU_ONE | - PWM_X_GENB_ACTCMPBD_ZERO); - } - else - { - // - // In down count mode, set the signal high on load and low on count - // comparison (that is, left align the signals). - // - HWREG(ui32Gen + PWM_O_X_GENA) = (PWM_X_GENA_ACTLOAD_ONE | - PWM_X_GENA_ACTCMPAD_ZERO); - HWREG(ui32Gen + PWM_O_X_GENB) = (PWM_X_GENB_ACTLOAD_ONE | - PWM_X_GENB_ACTCMPBD_ZERO); - } -} - -//***************************************************************************** -// -//! Sets the period of a PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to be modified. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Period specifies the period of PWM generator output, measured -//! in clock ticks. -//! -//! This function sets the period of the specified PWM generator block, where -//! the period of the generator block is defined as the number of PWM clock -//! ticks between pulses on the generator block zero signal. -//! -//! \note Any subsequent calls made to this function before an update occurs -//! cause the previous values to be overwritten. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Period) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Compute the generator's base address. - // - ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); - - // - // Set the reload register based on the mode. - // - if(HWREG(ui32Gen + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - // - // In up/down count mode, set the reload register to half the requested - // period. - // - ASSERT((ui32Period / 2) < 65536); - HWREG(ui32Gen + PWM_O_X_LOAD) = ui32Period / 2; - } - else - { - // - // In down count mode, set the reload register to the requested period - // minus one. - // - ASSERT((ui32Period <= 65536) && (ui32Period != 0)); - HWREG(ui32Gen + PWM_O_X_LOAD) = ui32Period - 1; - } -} - -//***************************************************************************** -// -//! Gets the period of a PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to query. This parameter must be one -//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function gets the period of the specified PWM generator block. The -//! period of the generator block is defined as the number of PWM clock ticks -//! between pulses on the generator block zero signal. -//! -//! If the update of the counter for the specified PWM generator has yet -//! to be completed, the value returned may not be the active period. The -//! value returned is the programmed period, measured in PWM clock ticks. -//! -//! \return Returns the programmed period of the specified generator block -//! in PWM clock ticks. -// -//***************************************************************************** -uint32_t -PWMGenPeriodGet(uint32_t ui32Base, uint32_t ui32Gen) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Compute the generator's base address. - // - ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); - - // - // Figure out the counter mode. - // - if(HWREG(ui32Gen + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - // - // The period is twice the reload register value. - // - return(HWREG(ui32Gen + PWM_O_X_LOAD) * 2); - } - else - { - // - // The period is the reload register value plus one. - // - return(HWREG(ui32Gen + PWM_O_X_LOAD) + 1); - } -} - -//***************************************************************************** -// -//! Enables the timer/counter for a PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to be enabled. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function allows the PWM clock to drive the timer/counter for the -//! specified generator block. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Enable the PWM generator. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE; -} - -//***************************************************************************** -// -//! Disables the timer/counter for a PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to be disabled. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function blocks the PWM clock from driving the timer/counter for the -//! specified generator block. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Disable the PWM generator. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_CTL) &= - ~(PWM_X_CTL_ENABLE); -} - -//***************************************************************************** -// -//! Sets the pulse width for the specified PWM output. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOut is the PWM output to modify. This parameter must be one -//! of \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, -//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. -//! \param ui32Width specifies the width of the positive portion of the pulse. -//! -//! This function sets the pulse width for the specified PWM output, where the -//! pulse width is defined as the number of PWM clock ticks. -//! -//! \note Any subsequent calls made to this function before an update occurs -//! cause the previous values to be overwritten. -//! -//! \return None. -// -//***************************************************************************** -void -PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut, - uint32_t ui32Width) -{ - uint32_t ui32GenBase, ui32Reg; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMOutValid(ui32PWMOut)); - - // - // Compute the generator's base address. - // - ui32GenBase = PWM_OUT_BADDR(ui32Base, ui32PWMOut); - - // - // If the counter is in up/down count mode, divide the width by two. - // - if(HWREG(ui32GenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - ui32Width /= 2; - } - - // - // Get the period. - // - ui32Reg = HWREG(ui32GenBase + PWM_O_X_LOAD); - - // - // Make sure the width is not too large. - // - ASSERT(ui32Width < ui32Reg); - - // - // Compute the compare value. - // - ui32Reg = ui32Reg - ui32Width; - - // - // Write to the appropriate registers. - // - if(PWM_IS_OUTPUT_ODD(ui32PWMOut)) - { - HWREG(ui32GenBase + PWM_O_X_CMPB) = ui32Reg; - } - else - { - HWREG(ui32GenBase + PWM_O_X_CMPA) = ui32Reg; - } -} - -//***************************************************************************** -// -//! Gets the pulse width of a PWM output. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOut is the PWM output to query. This parameter must be one -//! of \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, -//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. -//! -//! This function gets the currently programmed pulse width for the specified -//! PWM output. If the update of the comparator for the specified output has -//! yet to be completed, the value returned may not be the active pulse width. -//! The value returned is the programmed pulse width, measured in PWM clock -//! ticks. -//! -//! \return Returns the width of the pulse in PWM clock ticks. -// -//***************************************************************************** -uint32_t -PWMPulseWidthGet(uint32_t ui32Base, uint32_t ui32PWMOut) -{ - uint32_t ui32GenBase, ui32Reg, ui32Load; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMOutValid(ui32PWMOut)); - - // - // Compute the generator's base address. - // - ui32GenBase = PWM_OUT_BADDR(ui32Base, ui32PWMOut); - - // - // Then compute the pulse width. If mode is UpDown, set - // width = (load - compare) * 2. Otherwise, set width = load - compare. - // - ui32Load = HWREG(ui32GenBase + PWM_O_X_LOAD); - if(PWM_IS_OUTPUT_ODD(ui32PWMOut)) - { - ui32Reg = HWREG(ui32GenBase + PWM_O_X_CMPB); - } - else - { - ui32Reg = HWREG(ui32GenBase + PWM_O_X_CMPA); - } - ui32Reg = ui32Load - ui32Reg; - - // - // If in up/down count mode, double the pulse width. - // - if(HWREG(ui32GenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - ui32Reg = ui32Reg * 2; - } - - // - // Return the pulse width. - // - return(ui32Reg); -} - -//***************************************************************************** -// -//! Enables the PWM dead band output and sets the dead band delays. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to modify. This parameter must be one -//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui16Rise specifies the width of delay from the rising edge. -//! \param ui16Fall specifies the width of delay from the falling edge. -//! -//! This function sets the dead bands for the specified PWM generator, where -//! the dead bands are defined as the number of \b PWM clock ticks from the -//! rising or falling edge of the generator's \b OutA signal. Note that this -//! function causes the coupling of \b OutB to \b OutA. -//! -//! \return None. -// -//***************************************************************************** -void -PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen, - uint16_t ui16Rise, uint16_t ui16Fall) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT(ui16Rise < 4096); - ASSERT(ui16Fall < 4096); - - // - // Compute the generator's base address. - // - ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); - - // - // Write the dead band delay values. - // - HWREG(ui32Gen + PWM_O_X_DBRISE) = ui16Rise; - HWREG(ui32Gen + PWM_O_X_DBFALL) = ui16Fall; - - // - // Enable the deadband functionality. - // - HWREG(ui32Gen + PWM_O_X_DBCTL) |= PWM_X_DBCTL_ENABLE; -} - -//***************************************************************************** -// -//! Disables the PWM dead band output. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to modify. This parameter must be one -//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function disables the dead band mode for the specified PWM generator. -//! Doing so decouples the \b OutA and \b OutB signals. -//! -//! \return None. -// -//***************************************************************************** -void -PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Disable the deadband functionality. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_DBCTL) &= - ~(PWM_X_DBCTL_ENABLE); -} - -//***************************************************************************** -// -//! Synchronizes all pending updates. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32GenBits are the PWM generator blocks to be updated. This -//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, -//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. -//! -//! For the selected PWM generators, this function causes all queued updates to -//! the period or pulse width to be applied the next time the corresponding -//! counter becomes zero. -//! -//! \return None. -// -//***************************************************************************** -void -PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32GenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | - PWM_GEN_3_BIT))); - - // - // Synchronize pending PWM register changes. - // - HWREG(ui32Base + PWM_O_CTL) = ui32GenBits; -} - -//***************************************************************************** -// -//! Synchronizes the counters in one or multiple PWM generator blocks. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32GenBits are the PWM generator blocks to be synchronized. This -//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, -//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. -//! -//! For the selected PWM module, this function synchronizes the time base of -//! the generator blocks by causing the specified generator counters to be -//! reset to zero. -//! -//! \return None. -// -//***************************************************************************** -void -PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32GenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | - PWM_GEN_3_BIT))); - - // - // Synchronize the counters in the specified generators by writing to the - // module's synchronization register. - // - HWREG(ui32Base + PWM_O_SYNC) = ui32GenBits; -} - -//***************************************************************************** -// -//! Enables or disables PWM outputs. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter -//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, -//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, -//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. -//! \param bEnable determines if the signal is enabled or disabled. -//! -//! This function enables or disables the selected PWM outputs. The outputs -//! are selected using the parameter \e ui32PWMOutBits. The parameter \e -//! bEnable determines the state of the selected outputs. If \e bEnable is -//! \b true, then the selected PWM outputs are enabled, or placed in the active -//! state. If \e bEnable is \b false, then the selected outputs are disabled -//! or placed in the inactive state. -//! -//! \return None. -// -//***************************************************************************** -void -PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bEnable) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | - PWM_OUT_6_BIT | PWM_OUT_7_BIT))); - - // - // Read the module's ENABLE output control register and set or clear the - // requested bits. - // - if(bEnable == true) - { - HWREG(ui32Base + PWM_O_ENABLE) |= ui32PWMOutBits; - } - else - { - HWREG(ui32Base + PWM_O_ENABLE) &= ~(ui32PWMOutBits); - } -} - -//***************************************************************************** -// -//! Selects the inversion mode for PWM outputs. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter -//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, -//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, -//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. -//! \param bInvert determines if the signal is inverted or passed through. -//! -//! This function is used to select the inversion mode for the selected PWM -//! outputs. The outputs are selected using the parameter \e ui32PWMOutBits. -//! The parameter \e bInvert determines the inversion mode for the selected -//! outputs. If \e bInvert is \b true, this function causes the specified -//! PWM output signals to be inverted or made active low. If \e bInvert is -//! \b false, the specified outputs are passed through as is or made active -//! high. -//! -//! \return None. -// -//***************************************************************************** -void -PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bInvert) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | - PWM_OUT_6_BIT | PWM_OUT_7_BIT))); - - // - // Read the module's INVERT output control register and set or clear the - // requested bits. - // - if(bInvert == true) - { - HWREG(ui32Base + PWM_O_INVERT) |= ui32PWMOutBits; - } - else - { - HWREG(ui32Base + PWM_O_INVERT) &= ~(ui32PWMOutBits); - } -} - -//***************************************************************************** -// -//! Specifies the level of PWM outputs suppressed in response to a fault -//! condition. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter -//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, -//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, -//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. -//! \param bDriveHigh determines if the signal is driven high or low during an -//! active fault condition. -//! -//! This function determines whether a PWM output pin that is suppressed in -//! response to a fault condition is driven high or low. The affected outputs -//! are selected using the parameter \e ui32PWMOutBits. The parameter -//! \e bDriveHigh determines the output level for the pins identified by -//! \e ui32PWMOutBits. If \e bDriveHigh is \b true then the selected outputs -//! are driven high when a fault is detected. If it is \e false, the pins are -//! driven low. -//! -//! In a fault condition, pins which have not been configured to be suppressed -//! via a call to PWMOutputFault() are unaffected by this function. -//! -//! \note This function is available only on devices which support extended -//! PWM fault handling. -//! -//! \return None. -// -//***************************************************************************** -void -PWMOutputFaultLevel(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bDriveHigh) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | - PWM_OUT_6_BIT | PWM_OUT_7_BIT))); - - // - // Read the module's FAULT output control register and set or clear the - // requested bits. - // - if(bDriveHigh == true) - { - HWREG(ui32Base + PWM_O_FAULTVAL) |= ui32PWMOutBits; - } - else - { - HWREG(ui32Base + PWM_O_FAULTVAL) &= ~(ui32PWMOutBits); - } -} - -//***************************************************************************** -// -//! Specifies the state of PWM outputs in response to a fault condition. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter -//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, -//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, -//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. -//! \param bFaultSuppress determines if the signal is suppressed or passed -//! through during an active fault condition. -//! -//! This function sets the fault handling characteristics of the selected PWM -//! outputs. The outputs are selected using the parameter \e ui32PWMOutBits. -//! The parameter \e bFaultSuppress determines the fault handling -//! characteristics for the selected outputs. If \e bFaultSuppress is \b true, -//! then the selected outputs are made inactive. If \e bFaultSuppress is -//! \b false, then the selected outputs are unaffected by the detected fault. -//! -//! On devices supporting extended PWM fault handling, the state the affected -//! output pins are driven to can be configured with PWMOutputFaultLevel(). If -//! not configured, or if the device does not support extended PWM fault -//! handling, affected outputs are driven low on a fault condition. -//! -//! \return None. -// -//***************************************************************************** -void -PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bFaultSuppress) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | - PWM_OUT_6_BIT | PWM_OUT_7_BIT))); - - // - // Read the module's FAULT output control register and set or clear the - // requested bits. - // - if(bFaultSuppress == true) - { - HWREG(ui32Base + PWM_O_FAULT) |= ui32PWMOutBits; - } - else - { - HWREG(ui32Base + PWM_O_FAULT) &= ~(ui32PWMOutBits); - } -} - -//***************************************************************************** -// -//! Gets the PWM generator interrupt number. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator in question. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function returns the interrupt number of the corresponding PWM -//! generator. -//! -//! \return Returns the interrupt number. -// -//***************************************************************************** -static uint32_t -_PWMGenIntNumberGet(uint32_t ui32Base, uint32_t ui32Gen) -{ - // - // Determine the generator and PWM module in question. - // - switch(ui32Base + ui32Gen) - { - // - // The first PWM generator in the first PWM module. - // - case PWM0_BASE + PWM_GEN_0: - { - if(CLASS_IS_TM4C123) - { - return(INT_PWM0_0_TM4C123); - } - else if(CLASS_IS_TM4C129) - { - return(INT_PWM0_0_TM4C129); - } - else - { - return(0); - } - } - - // - // The second PWM generator in the first PWM module. - // - case PWM0_BASE + PWM_GEN_1: - { - if(CLASS_IS_TM4C129) - { - return(INT_PWM0_1_TM4C129); - } - else - { - return(0); - } - } - - // - // The third PWM generator in the first PWM module. - // - case PWM0_BASE + PWM_GEN_2: - { - if(CLASS_IS_TM4C129) - { - return(INT_PWM0_2_TM4C129); - } - else - { - return(0); - } - } - - // - // The fourth PWM generator in the first PWM module. - // - case PWM0_BASE + PWM_GEN_3: - { - if(CLASS_IS_TM4C129) - { - return(INT_PWM0_3_TM4C129); - } - else - { - return(0); - } - } - - // - // The first PWM generator in the second PWM module. - // - case PWM1_BASE + PWM_GEN_0: - { - if(CLASS_IS_TM4C123) - { - return(INT_PWM1_0_TM4C123); - } - else - { - return(0); - } - } - - // - // The first PWM generator in the second PWM module. - // - case PWM1_BASE + PWM_GEN_1: - { - if(CLASS_IS_TM4C123) - { - return(INT_PWM1_1_TM4C123); - } - else - { - return(0); - } - } - - // - // The first PWM generator in the second PWM module. - // - case PWM1_BASE + PWM_GEN_2: - { - if(CLASS_IS_TM4C123) - { - return(INT_PWM1_2_TM4C123); - } - else - { - return(0); - } - } - - // - // The first PWM generator in the second PWM module. - // - case PWM1_BASE + PWM_GEN_3: - { - if(CLASS_IS_TM4C123) - { - return(INT_PWM1_3_TM4C123); - } - else - { - return(0); - } - } - - // - // An unknown PWM module/generator was specified. - // - default: - { - return(0); - } - } -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator in question. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param pfnIntHandler is a pointer to the function to be called when the PWM -//! generator interrupt occurs. -//! -//! This function ensures that the interrupt handler specified by -//! \e pfnIntHandler is called when an interrupt is detected for the specified -//! PWM generator block. This function also enables the corresponding -//! PWM generator interrupt in the interrupt controller; individual generator -//! interrupts and interrupt sources must be enabled with PWMIntEnable() and -//! PWMGenIntTrigEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen, - void (*pfnIntHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Get the interrupt number associated with the specified generator. - // - ui32Int = _PWMGenIntNumberGet(ui32Base, ui32Gen); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnIntHandler); - - // - // Enable the PWMx interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Removes an interrupt handler for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator in question. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function unregisters the interrupt handler for the specified -//! PWM generator block. This function also disables the corresponding -//! PWM generator interrupt in the interrupt controller; individual generator -//! interrupts and interrupt sources must be disabled with PWMIntDisable() and -//! PWMGenIntTrigDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Get the interrupt number associated with the specified generator. - // - ui32Int = _PWMGenIntNumberGet(ui32Base, ui32Gen); - - ASSERT(ui32Int != 0); - - // - // Disable the PWMx interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Gets the PWM fault interrupt number. -//! -//! \param ui32Base is the base address of the PWM module. -//! -//! This function returns the fault interrupt number of the corresponding -//! PWM module. -//! -//! \return Returns the interrupt number. -// -//***************************************************************************** -static uint32_t -_PWMFaultIntNumberGet(uint32_t ui32Base) -{ - // - // Return the fault interrupt number. - // - if(CLASS_IS_TM4C123) - { - return((ui32Base == PWM0_BASE) ? INT_PWM0_FAULT_TM4C123 : - INT_PWM1_FAULT_TM4C123); - } - else if(CLASS_IS_TM4C129) - { - return((ui32Base == PWM0_BASE) ? INT_PWM0_FAULT_TM4C129 : 0); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a fault condition detected in a PWM -//! module. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param pfnIntHandler is a pointer to the function to be called when the PWM -//! fault interrupt occurs. -//! -//! This function ensures that the interrupt handler specified by -//! \e pfnIntHandler is called when a fault interrupt is detected for the -//! selected PWM module. This function also enables the PWM fault -//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the -//! module level using PWMIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -PWMFaultIntRegister(uint32_t ui32Base, void (*pfnIntHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - - // - // Get the interrupt number associated with the specified module. - // - ui32Int = _PWMFaultIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler, returning an error if one occurs. - // - IntRegister(ui32Int, pfnIntHandler); - - // - // Enable the PWM fault interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Removes the PWM fault condition interrupt handler. -//! -//! \param ui32Base is the base address of the PWM module. -//! -//! This function removes the interrupt handler for a PWM fault interrupt -//! from the selected PWM module. This function also disables the PWM -//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled -//! at the module level using PWMIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -PWMFaultIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - - // - // Get the interrupt number associated with the specified module. - // - ui32Int = _PWMFaultIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the PWM fault interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler, returning an error if one occurs. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables interrupts and triggers for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to have interrupts and triggers -//! enabled. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32IntTrig specifies the interrupts and triggers to be enabled. -//! -//! This function unmasks the specified interrupt(s) and trigger(s) by setting -//! the specified bits of the interrupt/trigger enable register for the -//! specified PWM generator. The \e ui32IntTrig parameter is the logical OR of -//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, -//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, -//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, -//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32IntTrig) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32IntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | - PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | - PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | - PWM_TR_CNT_LOAD | PWM_TR_CNT_AU | PWM_TR_CNT_AD | - PWM_TR_CNT_BU | PWM_TR_CNT_BD)) == 0); - - // - // Enable the specified interrupts/triggers. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_INTEN) |= ui32IntTrig; -} - -//***************************************************************************** -// -//! Disables interrupts for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to have interrupts and triggers -//! disabled. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32IntTrig specifies the interrupts and triggers to be disabled. -//! -//! This function masks the specified interrupt(s) and trigger(s) by clearing -//! the specified bits of the interrupt/trigger enable register for the -//! specified PWM generator. The \e ui32IntTrig parameter is the logical OR of -//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, -//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, -//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, -//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32IntTrig) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32IntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | - PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | - PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | - PWM_TR_CNT_LOAD | PWM_TR_CNT_AU | PWM_TR_CNT_AD | - PWM_TR_CNT_BU | PWM_TR_CNT_BD)) == 0); - - // - // Disable the specified interrupts/triggers. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_INTEN) &= ~(ui32IntTrig); -} - -//***************************************************************************** -// -//! Gets interrupt status for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to query. This parameter must be one -//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status is returned. -//! -//! \return Returns the contents of the interrupt status register or the -//! contents of the raw interrupt status register for the specified -//! PWM generator. -// -//***************************************************************************** -uint32_t -PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Compute the generator's base address. - // - ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); - - // - // Read and return the specified generator's raw or enabled interrupt - // status. - // - if(bMasked == true) - { - return(HWREG(ui32Gen + PWM_O_X_ISC)); - } - else - { - return(HWREG(ui32Gen + PWM_O_X_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the specified interrupt(s) for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to query. This parameter must be one -//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Ints specifies the interrupts to be cleared. -//! -//! This function clears the specified interrupt(s) by writing a 1 to the -//! specified bits of the interrupt status register for the specified PWM -//! generator. The \e ui32Ints parameter is the logical OR of -//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, -//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen, uint32_t ui32Ints) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32Ints & - ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU | - PWM_INT_CNT_AD | PWM_INT_CNT_BU | PWM_INT_CNT_BD)) == 0); - - // - // Clear the requested interrupts by writing ones to the specified bit - // of the module's interrupt enable register. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_ISC) = ui32Ints; -} - -//***************************************************************************** -// -//! Enables generator and fault interrupts for a PWM module. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32GenFault contains the interrupts to be enabled. This parameter -//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, -//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, -//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. -//! -//! This function unmasks the specified interrupt(s) by setting the specified -//! bits of the interrupt enable register for the selected PWM module. -//! -//! \return None. -// -//***************************************************************************** -void -PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT((ui32GenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | - PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | - PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); - - // - // Read the module's interrupt enable register and enable interrupts - // for the specified PWM generators. - // - HWREG(ui32Base + PWM_O_INTEN) |= ui32GenFault; -} - -//***************************************************************************** -// -//! Disables generator and fault interrupts for a PWM module. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32GenFault contains the interrupts to be disabled. This parameter -//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, -//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, -//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. -//! -//! This function masks the specified interrupt(s) by clearing the specified -//! bits of the interrupt enable register for the selected PWM module. -//! -//! \return None. -// -//***************************************************************************** -void -PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT((ui32GenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | - PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | - PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); - - // - // Read the module's interrupt enable register and disable interrupts - // for the specified PWM generators. - // - HWREG(ui32Base + PWM_O_INTEN) &= ~(ui32GenFault); -} - -//***************************************************************************** -// -//! Clears the fault interrupt for a PWM module. -//! -//! \param ui32Base is the base address of the PWM module. -//! -//! This function clears the fault interrupt by writing to the appropriate bit -//! of the interrupt status register for the selected PWM module. -//! -//! This function clears only the FAULT0 interrupt and is retained for -//! backwards compatibility. It is recommended that PWMFaultIntClearExt() be -//! used instead because it supports all fault interrupts supported on devices -//! with and without extended PWM fault handling support. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -PWMFaultIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - - // - // Write the only writeable bit in the module's interrupt register. - // - HWREG(ui32Base + PWM_O_ISC) = PWM_ISC_INTFAULT0; -} - -//***************************************************************************** -// -//! Gets the interrupt status for a PWM module. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status is returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, -//! \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, and -//! \b PWM_INT_FAULT3. -//! -//***************************************************************************** -uint32_t -PWMIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - - // - // Read and return either the module's raw or enabled interrupt status. - // - if(bMasked == true) - { - return(HWREG(ui32Base + PWM_O_ISC)); - } - else - { - return(HWREG(ui32Base + PWM_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the fault interrupt for a PWM module. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32FaultInts specifies the fault interrupts to clear. -//! -//! This function clears one or more fault interrupts by writing to the -//! appropriate bit of the PWM interrupt status register. The parameter -//! \e ui32FaultInts must be the logical OR of any of \b PWM_INT_FAULT0, -//! \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. -//! -//! The fault interrupts are derived by performing a logical OR of each of the -//! configured fault trigger signals for a given generator. Therefore, these -//! interrupts are not directly related to the four possible FAULTn inputs to -//! the device but indicate that a fault has been signaled to one of the four -//! possible PWM generators. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -PWMFaultIntClearExt(uint32_t ui32Base, uint32_t ui32FaultInts) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT((ui32FaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 | - PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); - - // - // Clear the supplied fault bits. - // - HWREG(ui32Base + PWM_O_ISC) = ui32FaultInts; -} - -//***************************************************************************** -// -//! Configures the minimum fault period and fault pin senses for a given -//! PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator for which fault configuration is being -//! set. This function must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32MinFaultPeriod is the minimum fault active period expressed in -//! PWM clock cycles. -//! \param ui32FaultSenses indicates which sense of each FAULT input should be -//! considered the ``asserted'' state. Valid values are logical OR -//! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW. -//! -//! This function configures the minimum fault period for a given generator -//! along with the sense of each of the 4 possible fault inputs. The minimum -//! fault period is expressed in PWM clock cycles and takes effect only if -//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the -//! \e ui32Config parameter. When a fault input is asserted, the minimum fault -//! period timer ensures that it remains asserted for at least the number of -//! clock cycles specified. -//! -//! \note This function is only available on devices supporting extended PWM -//! fault handling. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32MinFaultPeriod, - uint32_t ui32FaultSenses) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT(ui32MinFaultPeriod < PWM_X_MINFLTPER_M); - ASSERT((ui32FaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW | - PWM_FAULT1_SENSE_HIGH | PWM_FAULT1_SENSE_LOW | - PWM_FAULT2_SENSE_HIGH | PWM_FAULT2_SENSE_LOW | - PWM_FAULT3_SENSE_HIGH | - PWM_FAULT3_SENSE_LOW)) == 0); - - // - // Write the minimum fault period. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_MINFLTPER) = - ui32MinFaultPeriod; - - // - // Write the fault senses. - // - HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSEN) = - ui32FaultSenses; -} - -//***************************************************************************** -// -//! Configures the set of fault triggers for a given PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator for which fault triggers are being set. -//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or -//! \b PWM_GEN_3. -//! \param ui32Group indicates the subset of possible faults that are to be -//! configured. This parameter must be \b PWM_FAULT_GROUP_0 or -//! \b PWM_FAULT_GROUP_1. -//! \param ui32FaultTriggers defines the set of inputs that are to contribute -//! towards generation of the fault signal to the given PWM generator. For -//! \b PWM_FAULT_GROUP_0, this is the logical OR of \b PWM_FAULT_FAULT0, -//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3. For -//! \b PWM_FAULT_GROUP_1, this is the logical OR of \b PWM_FAULT_DCMP0, -//! \b PWM_FAULT_DCMP1, \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, -//! \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or -//! \b PWM_FAULT_DCMP7. -//! -//! This function allows selection of the set of fault inputs that is combined -//! to generate a fault condition to a given PWM generator. By default, all -//! generators use only FAULT0 (for backwards compatibility) but if -//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the -//! \e ui32Config parameter, extended fault handling is enabled and this -//! function must be called to configure the fault triggers. -//! -//! The fault signal to the PWM generator is generated by ORing together each -//! of the signals specified in the \e ui32FaultTriggers parameter after having -//! adjusted the sense of each FAULTn input based on the configuration -//! previously set using a call to PWMGenFaultConfigure(). -//! -//! \note This function is only available on devices supporting extended PWM -//! fault handling. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group, uint32_t ui32FaultTriggers) -{ - // - // Check for valid parameters. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) || - (ui32Group == PWM_FAULT_GROUP_1)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) && - ((ui32FaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 | - PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == - 0)); - ASSERT((ui32Group == PWM_FAULT_GROUP_1) && - ((ui32FaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 | - PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 | - PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 | - PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0)); - - // - // Write the fault triggers to the appropriate register. - // - if(ui32Group == PWM_FAULT_GROUP_0) - { - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC0) = - ui32FaultTriggers; - } - else - { - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC1) = - ui32FaultTriggers; - } -} - -//***************************************************************************** -// -//! Returns the set of fault triggers currently configured for a given PWM -//! generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator for which fault triggers are being -//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Group indicates the subset of faults that are being queried. -//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. -//! -//! This function allows an application to query the current set of inputs that -//! contribute to the generation of a fault condition to a given PWM generator. -//! -//! \note This function is only available on devices supporting extended PWM -//! fault handling. -//! -//! \return Returns the current fault triggers configured for the fault group -//! provided. For \b PWM_FAULT_GROUP_0, the returned value is a logical OR of -//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or -//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value is the -//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, -//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, -//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. -// -//***************************************************************************** -uint32_t -PWMGenFaultTriggerGet(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group) -{ - // - // Check for valid parameters. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) || - (ui32Group == PWM_FAULT_GROUP_1)); - - // - // Return the current fault triggers. - // - if(ui32Group == PWM_FAULT_GROUP_0) - { - return(HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC0)); - } - else - { - return(HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC1)); - } -} - -//***************************************************************************** -// -//! Returns the current state of the fault triggers for a given PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator for which fault trigger states are -//! being queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Group indicates the subset of faults that are being queried. -//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. -//! -//! This function allows an application to query the current state of each of -//! the fault trigger inputs to a given PWM generator. The current state of -//! each fault trigger input is returned unless PWMGenConfigure() has -//! previously been called with flag \b PWM_GEN_MODE_FAULT_LATCHED in the -//! \e ui32Config parameter, in which case the returned status is the latched -//! fault trigger status. -//! -//! If latched faults are configured, the application must call -//! PWMGenFaultClear() to clear each trigger. -//! -//! \note This function is only available on devices supporting extended PWM -//! fault handling. -//! -//! \return Returns the current state of the fault triggers for the given PWM -//! generator. A set bit indicates that the associated trigger is active. -//! For \b PWM_FAULT_GROUP_0, the returned value is a logical OR of -//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or -//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value is the -//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, -//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, -//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. -// -//***************************************************************************** -uint32_t -PWMGenFaultStatus(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group) -{ - // - // Check for valid parameters. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) || - (ui32Group == PWM_FAULT_GROUP_1)); - - // - // Return the current fault status. - // - if(ui32Group == PWM_FAULT_GROUP_0) - { - return(HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT0)); - } - else - { - return(HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT1)); - } -} - -//***************************************************************************** -// -//! Clears one or more latched fault triggers for a given PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator for which fault trigger states are -//! being queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Group indicates the subset of faults that are being queried. -//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. -//! \param ui32FaultTriggers is the set of fault triggers which are to be -//! cleared. -//! -//! This function allows an application to clear the fault triggers for a -//! given PWM generator. This function is only required if PWMGenConfigure() -//! has previously been called with flag \b PWM_GEN_MODE_FAULT_LATCHED in -//! parameter \e ui32Config. -//! -//! \note This function is only available on devices supporting extended PWM -//! fault handling. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group, uint32_t ui32FaultTriggers) -{ - // - // Check for valid parameters. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) || - (ui32Group == PWM_FAULT_GROUP_1)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) && - ((ui32FaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 | - PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == - 0)); - ASSERT((ui32Group == PWM_FAULT_GROUP_1) && - ((ui32FaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 | - PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 | - PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 | - PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0)); - - // - // Clear the given faults. - // - if(ui32Group == PWM_FAULT_GROUP_0) - { - HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT0) = - ui32FaultTriggers; - } - else - { - HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT1) = - ui32FaultTriggers; - } -} - -//***************************************************************************** -/// -//! Sets the PWM clock configuration. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Config is the configuration for the PWM clock; it must be one of -//! \b PWM_SYSCLK_DIV_1, \b PWM_SYSCLK_DIV_2, \b PWM_SYSCLK_DIV_4, -//! \b PWM_SYSCLK_DIV_8, \b PWM_SYSCLK_DIV_16, \b PWM_SYSCLK_DIV_32, or -//! \b PWM_SYSCLK_DIV_64. -//! -//! This function sets the PWM clock divider as the PWM clock source. It also -//! configures the clock frequency to the PWM module as a division of the -//! system clock. This clock is used by the PWM module to generate PWM -//! signals; its rate forms the basis for all PWM signals. -//! -//! \note This function should not be used with TM4C123 devices. For -//! TM4C123 devices, the SysCtlPWMClockGet() function should be used. -//! -//! \note The clocking of the PWM is dependent upon the system clock rate as -//! configured by SysCtlClockFreqSet(). -//! -//! \return None. -// -//***************************************************************************** -void -PWMClockSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT((ui32Config == PWM_SYSCLK_DIV_2) || - (ui32Config == PWM_SYSCLK_DIV_4) || - (ui32Config == PWM_SYSCLK_DIV_8) || - (ui32Config == PWM_SYSCLK_DIV_16) || - (ui32Config == PWM_SYSCLK_DIV_32) || - (ui32Config == PWM_SYSCLK_DIV_64)); - - // - // Set the PWM clock configuration into the PWM clock configuration - // register. - // - HWREG(ui32Base + PWM_O_CC) = ((HWREG(ui32Base + PWM_O_CC) & - ~(PWM_CC_USEPWM | PWM_CC_PWMDIV_M)) | - ui32Config); -} - -//***************************************************************************** -// -//! Gets the current PWM clock configuration. -//! -//! \param ui32Base is the base address of the PWM module. -//! -//! This function returns the current PWM clock configuration. -//! -//! \note This function should not be used with TM4C123 devices. For -//! TM4C123 devices, the SysCtlPWMClockGet() function should be used. -//! -//! \return Returns the current PWM clock configuration; is one of -//! \b PWM_SYSCLK_DIV_1, \b PWM_SYSCLK_DIV_2, \b PWM_SYSCLK_DIV_4, -//! \b PWM_SYSCLK_DIV_8, \b PWM_SYSCLK_DIV_16, \b PWM_SYSCLK_DIV_32, -//! or \b PWM_SYSCLK_DIV_64. -// -//***************************************************************************** -uint32_t -PWMClockGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - - // - // Return the current PWM clock configuration. Make sure that - // PWM_SYSCLK_DIV_1 is returned in all cases where the divider is disabled. - // - if(!(HWREG(ui32Base + PWM_O_CC) & PWM_CC_USEPWM)) - { - // - // The divider is not active so reflect this in the value we return. - // - return(PWM_SYSCLK_DIV_1); - } - else - { - // - // The divider is active so directly return the masked register value. - // - return(HWREG(ui32Base + PWM_O_CC) & (PWM_CC_USEPWM | PWM_CC_PWMDIV_M)); - } -} - -//***************************************************************************** -// -//! Sets the update mode or synchronization mode to the PWM outputs. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter -//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, -//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, -//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. -//! \param ui32Mode specifies the enable update mode to use when enabling or -//! disabling PWM outputs. -//! -//! This function sets one of three possible update modes to enable or disable -//! the requested PWM outputs. The \e ui32Mode parameter controls when changes -//! made via calls to PWMOutputState() take effect. Possible values are: -//! -//! - \b PWM_OUTPUT_MODE_NO_SYNC, which enables/disables changes to take effect -//! immediately. -//! - \b PWM_OUTPUT_MODE_SYNC_LOCAL, which causes changes to take effect when -//! the local PWM generator's count next reaches 0. -//! - \b PWM_OUTPUT_MODE_SYNC_GLOBAL, which causes changes to take effect when -//! the local PWM generator's count next reaches 0 following a call to -//! PWMSyncUpdate() which specifies the same generator in its \e ui32GenBits -//! parameter. -//! -//! \note This function is only available on Snowflake class devices. -//! -//! \return None. -// -//***************************************************************************** -void -PWMOutputUpdateMode(uint32_t ui32Base, uint32_t ui32PWMOutBits, - uint32_t ui32Mode) -{ - uint_fast8_t ui8Index; - uint32_t ui32PWMOutputMask; - uint32_t ui32UpdateValueMask; - uint32_t ui32UpdateValue; - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | - PWM_OUT_6_BIT | PWM_OUT_7_BIT))); - ASSERT((ui32Mode == PWM_OUTPUT_MODE_NO_SYNC) || - (ui32Mode == PWM_OUTPUT_MODE_SYNC_LOCAL) || - (ui32Mode == PWM_OUTPUT_MODE_SYNC_GLOBAL)); - - // - // Initialize the local variables - // - ui8Index = 0; - ui32PWMOutputMask = 1; - ui32UpdateValue = 0; - ui32UpdateValueMask = 0; - - // - // Loop to find out which PWM outputs are to be modified. - // - while(ui8Index < 8) - { - // - // Check if this PWM output is to be modified. - // - if(ui32PWMOutputMask & ui32PWMOutBits) - { - // - // Set the update mode value for the requested PWM output by - // writing to the appropriate field. - // - ui32UpdateValue |= ui32Mode << (ui8Index * 2); - - // - // Compute the mask for the bits to be updated. - // - ui32UpdateValueMask |= 3 << (ui8Index * 2); - } - - // - // Update the PWM output to be checked and the index. - // - ui32PWMOutputMask = ui32PWMOutputMask << 1; - ui8Index++; - } - - // - // Read the Enable Update register and mask the bits that are to be - // updated. - // - ui32Temp = ~ui32UpdateValueMask & HWREG(ui32Base + PWM_O_ENUPD); - - // - // Write the updated values to Enable Update register. - // - HWREG(ui32Base + PWM_O_ENUPD) = ui32Temp | ui32UpdateValue; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/pwm.h b/bsp/tm4c129x-dk/libraries/driverlib/pwm.h deleted file mode 100644 index c18d98acb229e2552585fcc5679e457e32da9c65..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/pwm.h +++ /dev/null @@ -1,326 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_PWM_H__ -#define __DRIVERLIB_PWM_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ui32Config -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode -#define PWM_GEN_MODE_FAULT_LATCHED \ - 0x00040000 // Fault is latched -#define PWM_GEN_MODE_FAULT_UNLATCHED \ - 0x00000000 // Fault is not latched -#define PWM_GEN_MODE_FAULT_MINPER \ - 0x00020000 // Enable min fault period -#define PWM_GEN_MODE_FAULT_NO_MINPER \ - 0x00000000 // Disable min fault period -#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support -#define PWM_GEN_MODE_FAULT_LEGACY \ - 0x00000000 // Disable extended fault support -#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur - // immediately -#define PWM_GEN_MODE_DB_SYNC_LOCAL \ - 0x0000A800 // Deadband updates locally - // synchronized -#define PWM_GEN_MODE_DB_SYNC_GLOBAL \ - 0x0000FC00 // Deadband updates globally - // synchronized -#define PWM_GEN_MODE_GEN_NO_SYNC \ - 0x00000000 // Generator mode updates occur - // immediately -#define PWM_GEN_MODE_GEN_SYNC_LOCAL \ - 0x00000280 // Generator mode updates locally - // synchronized -#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \ - 0x000003C0 // Generator mode updates globally - // synchronized - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt -#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt -#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt -#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt -#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt -#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 -#define PWM_GEN_3 0x00000100 // Offset address of Gen3 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 -#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3 - -#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range -#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range -#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range -#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 -#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6 -#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 -#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6 -#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7 - -//***************************************************************************** -// -// Defines to identify each of the possible fault trigger conditions in -// PWM_FAULT_GROUP_0. -// -//***************************************************************************** -#define PWM_FAULT_GROUP_0 0 - -#define PWM_FAULT_FAULT0 0x00000001 -#define PWM_FAULT_FAULT1 0x00000002 -#define PWM_FAULT_FAULT2 0x00000004 -#define PWM_FAULT_FAULT3 0x00000008 -#define PWM_FAULT_ACMP0 0x00010000 -#define PWM_FAULT_ACMP1 0x00020000 -#define PWM_FAULT_ACMP2 0x00040000 - -//***************************************************************************** -// -// Defines to identify each of the possible fault trigger conditions in -// PWM_FAULT_GROUP_1. -// -//***************************************************************************** -#define PWM_FAULT_GROUP_1 1 - -#define PWM_FAULT_DCMP0 0x00000001 -#define PWM_FAULT_DCMP1 0x00000002 -#define PWM_FAULT_DCMP2 0x00000004 -#define PWM_FAULT_DCMP3 0x00000008 -#define PWM_FAULT_DCMP4 0x00000010 -#define PWM_FAULT_DCMP5 0x00000020 -#define PWM_FAULT_DCMP6 0x00000040 -#define PWM_FAULT_DCMP7 0x00000080 - -//***************************************************************************** -// -// Defines to identify the sense of each of the external FAULTn signals -// -//***************************************************************************** -#define PWM_FAULT0_SENSE_HIGH 0x00000000 -#define PWM_FAULT0_SENSE_LOW 0x00000001 -#define PWM_FAULT1_SENSE_HIGH 0x00000000 -#define PWM_FAULT1_SENSE_LOW 0x00000002 -#define PWM_FAULT2_SENSE_HIGH 0x00000000 -#define PWM_FAULT2_SENSE_LOW 0x00000004 -#define PWM_FAULT3_SENSE_HIGH 0x00000000 -#define PWM_FAULT3_SENSE_LOW 0x00000008 - -//***************************************************************************** -// -// Defines that can be passed to the PWMClockSet() API as the ui32Config -// parameter, and can be returned by the PWMClockGet() API. -// -//***************************************************************************** -#define PWM_SYSCLK_DIV_1 0x00000000 // PWM clock is system clock -#define PWM_SYSCLK_DIV_2 0x00000100 // PWM clock is system clock /2 -#define PWM_SYSCLK_DIV_4 0x00000101 // PWM clock is system clock /4 -#define PWM_SYSCLK_DIV_8 0x00000102 // PWM clock is system clock /8 -#define PWM_SYSCLK_DIV_16 0x00000103 // PWM clock is system clock /16 -#define PWM_SYSCLK_DIV_32 0x00000104 // PWM clock is system clock /32 -#define PWM_SYSCLK_DIV_64 0x00000105 // PWM clock is system clock /64 - -//***************************************************************************** -// -// Defines passed to PWMOutputUpdateMode() to identify the synchronization mode -// to use when enabling or disabling outputs using PWMOutputState(). -// -//***************************************************************************** -#define PWM_OUTPUT_MODE_NO_SYNC 0x00000000 // Updates to occur immediately -#define PWM_OUTPUT_MODE_SYNC_LOCAL \ - 0x00000002 // Updates are locally synchronized -#define PWM_OUTPUT_MODE_SYNC_GLOBAL \ - 0x00000003 // Updates are globally synchronized - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Config); -extern void PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Period); -extern uint32_t PWMGenPeriodGet(uint32_t ui32Base, - uint32_t ui32Gen); -extern void PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen); -extern void PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen); -extern void PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut, - uint32_t ui32Width); -extern uint32_t PWMPulseWidthGet(uint32_t ui32Base, - uint32_t ui32PWMOut); -extern void PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen, - uint16_t ui16Rise, uint16_t ui16Fall); -extern void PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen); -extern void PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits); -extern void PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits); -extern void PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bEnable); -extern void PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bInvert); -extern void PWMOutputFaultLevel(uint32_t ui32Base, - uint32_t ui32PWMOutBits, - bool bDriveHigh); -extern void PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bFaultSuppress); -extern void PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen, - void (*pfnIntHandler)(void)); -extern void PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen); -extern void PWMFaultIntRegister(uint32_t ui32Base, - void (*pfnIntHandler)(void)); -extern void PWMFaultIntUnregister(uint32_t ui32Base); -extern void PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32IntTrig); -extern void PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32IntTrig); -extern uint32_t PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen, - bool bMasked); -extern void PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Ints); -extern void PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault); -extern void PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault); -extern void PWMFaultIntClear(uint32_t ui32Base); -extern uint32_t PWMIntStatus(uint32_t ui32Base, bool bMasked); -extern void PWMFaultIntClearExt(uint32_t ui32Base, - uint32_t ui32FaultInts); -extern void PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32MinFaultPeriod, - uint32_t ui32FaultSenses); -extern void PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group, - uint32_t ui32FaultTriggers); -extern uint32_t PWMGenFaultTriggerGet(uint32_t ui32Base, - uint32_t ui32Gen, - uint32_t ui32Group); -extern uint32_t PWMGenFaultStatus(uint32_t ui32Base, - uint32_t ui32Gen, - uint32_t ui32Group); -extern void PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group, - uint32_t ui32FaultTriggers); -extern void PWMClockSet(uint32_t ui32Base, uint32_t ui32Config); -extern uint32_t PWMClockGet(uint32_t ui32Base); -extern void PWMOutputUpdateMode(uint32_t ui32Base, - uint32_t ui32PWMOutBits, - uint32_t ui32Mode); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_PWM_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/qei.c b/bsp/tm4c129x-dk/libraries/driverlib/qei.c deleted file mode 100644 index b4def78493344c4eb41e4a5ce89488f329e7de75..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/qei.c +++ /dev/null @@ -1,783 +0,0 @@ -//***************************************************************************** -// -// qei.c - Driver for the Quadrature Encoder with Index. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup qei_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_qei.h" -#include "inc/hw_types.h" -#include "inc/hw_sysctl.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/qei.h" - -//***************************************************************************** -// -//! Enables the quadrature encoder. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function enables operation of the quadrature encoder module. The -//! module must be configured before it is enabled. -//! -//! \sa QEIConfigure() -//! -//! \return None. -// -//***************************************************************************** -void -QEIEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Enable the QEI module. - // - HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_ENABLE; -} - -//***************************************************************************** -// -//! Disables the quadrature encoder. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function disables operation of the quadrature encoder module. -//! -//! \return None. -// -//***************************************************************************** -void -QEIDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Disable the QEI module. - // - HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_ENABLE); -} - -//***************************************************************************** -// -//! Configures the quadrature encoder. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32Config is the configuration for the quadrature encoder. See -//! below for a description of this parameter. -//! \param ui32MaxPosition specifies the maximum position value. -//! -//! This function configures the operation of the quadrature encoder. The -//! \e ui32Config parameter provides the configuration of the encoder and is -//! the logical OR of several values: -//! -//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B specify if edges -//! on channel A or on both channels A and B should be counted by the -//! position integrator and velocity accumulator. -//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX specify if the -//! position integrator should be reset when the index pulse is detected. -//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR specify if -//! quadrature signals are being provided on ChA and ChB, or if a direction -//! signal and a clock are being provided instead. -//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals -//! provided on ChA and ChB should be swapped before being processed. -//! -//! \e ui32MaxPosition is the maximum value of the position integrator and is -//! the value used to reset the position capture when in index reset mode and -//! moving in the reverse (negative) direction. -//! -//! \return None. -// -//***************************************************************************** -void -QEIConfigure(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32MaxPosition) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Write the new configuration to the hardware. - // - HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & - ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE | - QEI_CTL_SIGMODE | QEI_CTL_SWAP)) | - ui32Config); - - // - // Set the maximum position. - // - HWREG(ui32Base + QEI_O_MAXPOS) = ui32MaxPosition; -} - -//***************************************************************************** -// -//! Gets the current encoder position. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function returns the current position of the encoder. Depending upon -//! the configuration of the encoder, and the incident of an index pulse, this -//! value may or may not contain the expected data (that is, if in reset on -//! index mode, if an index pulse has not been encountered, the position -//! counter is not yet aligned with the index pulse). -//! -//! \return The current position of the encoder. -// -//***************************************************************************** -uint32_t -QEIPositionGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Return the current position counter. - // - return(HWREG(ui32Base + QEI_O_POS)); -} - -//***************************************************************************** -// -//! Sets the current encoder position. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32Position is the new position for the encoder. -//! -//! This function sets the current position of the encoder; the encoder -//! position is then measured relative to this value. -//! -//! \return None. -// -//***************************************************************************** -void -QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Set the position counter. - // - HWREG(ui32Base + QEI_O_POS) = ui32Position; -} - -//***************************************************************************** -// -//! Gets the current direction of rotation. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function returns the current direction of rotation. In this case, -//! current means the most recently detected direction of the encoder; it may -//! not be presently moving but this is the direction it last moved before it -//! stopped. -//! -//! \return Returns 1 if moving in the forward direction or -1 if moving in the -//! reverse direction. -// -//***************************************************************************** -int32_t -QEIDirectionGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Return the direction of rotation. - // - return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1); -} - -//***************************************************************************** -// -//! Gets the encoder error indicator. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function returns the error indicator for the quadrature encoder. It -//! is an error for both of the signals of the quadrature input to change at -//! the same time. -//! -//! \return Returns \b true if an error has occurred and \b false otherwise. -// -//***************************************************************************** -bool -QEIErrorGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Return the error indicator. - // - return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); -} - -//***************************************************************************** -// -//! Enables the input filter. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function enables operation of the input filter in the quadrature -//! encoder module. The module must be configured before input filter is -//! enabled. -//! -//! \sa QEIFilterConfigure() and QEIEnable() -//! -//! \return None. -// -//***************************************************************************** -void -QEIFilterEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Enable the input filter. - // - HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_FILTEN; -} - -//***************************************************************************** -// -//! Disables the input filter. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function disables operation of the input filter in the quadrature -//! encoder module. -//! -//! \return None. -// -//***************************************************************************** -void -QEIFilterDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Disable the input filter. - // - HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_FILTEN); -} - -//***************************************************************************** -// -//! Configures the input filter. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32FiltCnt specifies the filter count applied to the input quadrature -//! signal before it is counted; can be one of \b QEI_FILTCNT_2, -//! \b QEI_FILTCNT_3, \b QEI_FILTCNT_4, \b QEI_FILTCNT_5, \b QEI_FILTCNT_6, -//! \b QEI_FILTCNT_7, \b QEI_FILTCNT_8, \b QEI_FILTCNT_9, \b QEI_FILTCNT_10, -//! \b QEI_FILTCNT_11, \b QEI_FILTCNT_12, \b QEI_FILTCNT_13, \b QEI_FILTCNT_14, -//! \b QEI_FILTCNT_15, \b QEI_FILTCNT_16 or \b QEI_FILTCNT_17 -//! -//! This function configures the operation of the input filter prescale count. -//! as specified by \e ui32FiltCnt before the input signals are sent to the -//! quadrature encoder module. -//! -//! \return None. -// -//***************************************************************************** -void -QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - ASSERT(!(ui32FiltCnt & ~(QEI_CTL_FILTCNT_M))); - - // - // Set the input filter prescale count. - // - HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & - ~(QEI_CTL_FILTCNT_M)) | ui32FiltCnt); -} - -//***************************************************************************** -// -//! Enables the velocity capture. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function enables operation of the velocity capture in the quadrature -//! encoder module. The module must be configured before velocity capture is -//! enabled. -//! -//! \sa QEIVelocityConfigure() and QEIEnable() -//! -//! \return None. -// -//***************************************************************************** -void -QEIVelocityEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Enable the velocity capture. - // - HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_VELEN; -} - -//***************************************************************************** -// -//! Disables the velocity capture. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function disables operation of the velocity capture in the quadrature -//! encoder module. -//! -//! \return None. -// -//***************************************************************************** -void -QEIVelocityDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Disable the velocity capture. - // - HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_VELEN); -} - -//***************************************************************************** -// -//! Configures the velocity capture. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32PreDiv specifies the predivider applied to the input quadrature -//! signal before it is counted; can be one of \b QEI_VELDIV_1, -//! \b QEI_VELDIV_2, \b QEI_VELDIV_4, \b QEI_VELDIV_8, \b QEI_VELDIV_16, -//! \b QEI_VELDIV_32, \b QEI_VELDIV_64, or \b QEI_VELDIV_128. -//! \param ui32Period specifies the number of clock ticks over which to measure -//! the velocity; must be non-zero. -//! -//! This function configures the operation of the velocity capture portion of -//! the quadrature encoder. The position increment signal is predivided as -//! specified by \e ui32PreDiv before being accumulated by the velocity -//! capture. The divided signal is accumulated over \e ui32Period system clock -//! before being saved and resetting the accumulator. -//! -//! \return None. -// -//***************************************************************************** -void -QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv, - uint32_t ui32Period) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - ASSERT(!(ui32PreDiv & ~(QEI_CTL_VELDIV_M))); - ASSERT(ui32Period != 0); - - // - // Set the velocity predivider. - // - HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & - ~(QEI_CTL_VELDIV_M)) | ui32PreDiv); - - // - // Set the timer period. - // - HWREG(ui32Base + QEI_O_LOAD) = ui32Period - 1; -} - -//***************************************************************************** -// -//! Gets the current encoder speed. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function returns the current speed of the encoder. The value returned -//! is the number of pulses detected in the specified time period; this number -//! can be multiplied by the number of time periods per second and divided by -//! the number of pulses per revolution to obtain the number of revolutions per -//! second. -//! -//! \return Returns the number of pulses captured in the given time period. -// -//***************************************************************************** -uint32_t -QEIVelocityGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Return the speed capture value. - // - return(HWREG(ui32Base + QEI_O_SPEED)); -} - -//***************************************************************************** -// -//! Returns the quadrature encoder interrupt number. -//! -//! \param ui32Base is the base address of the selected quadrature encoder -//! -//! This function returns the interrupt number for the quadrature encoder with -//! the base address passed in the \e ui32Base parameter. -//! -//! \return Returns a quadrature encoder interrupt number or 0 if the interrupt -//! does not exist. -// -//***************************************************************************** -static uint32_t -_QEIIntNumberGet(uint32_t ui32Base) -{ - uint32_t ui32Int; - - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Find the valid interrupt number for this quadrature encoder. - // - if(CLASS_IS_TM4C123) - { - if(ui32Base == QEI0_BASE) - { - ui32Int = INT_QEI0_TM4C123; - } - else - { - ui32Int = INT_QEI1_TM4C123; - } - } - else if(CLASS_IS_TM4C129) - { - if(ui32Base == QEI0_BASE) - { - ui32Int = INT_QEI0_TM4C129; - } - else - { - ui32Int = 0; - } - } - else - { - ui32Int = 0; - } - - return(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the quadrature encoder interrupt. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param pfnHandler is a pointer to the function to be called when the -//! quadrature encoder interrupt occurs. -//! -//! This function registers the handler to be called when a quadrature encoder -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific quadrature encoder interrupts must be -//! enabled via QEIIntEnable(). It is the interrupt handler's responsibility -//! to clear the interrupt source via QEIIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Determine the interrupt number based on the QEI module. - // - ui32Int = _QEIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the quadrature encoder interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the quadrature encoder interrupt. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function unregisters the handler to be called when a quadrature -//! encoder interrupt occurs. This function also masks off the interrupt in -//! the interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -QEIIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Determine the interrupt number based on the QEI module. - // - ui32Int = _QEIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables individual quadrature encoder interrupt sources. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or -//! \b QEI_INTINDEX values. -//! -//! This function enables the indicated quadrature encoder interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Enable the specified interrupts. - // - HWREG(ui32Base + QEI_O_INTEN) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual quadrature encoder interrupt sources. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, -//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. -//! -//! This function disables the indicated quadrature encoder interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Disable the specified interrupts. - // - HWREG(ui32Base + QEI_O_INTEN) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the quadrature encoder -//! module. Either the raw interrupt status or the status of interrupts that -//! are allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX. -// -//***************************************************************************** -uint32_t -QEIIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + QEI_O_ISC)); - } - else - { - return(HWREG(ui32Base + QEI_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears quadrature encoder interrupt sources. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, -//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. -//! -//! The specified quadrature encoder interrupt sources are cleared, so that -//! they no longer assert. This function must be called in the interrupt -//! handler to keep the interrupt from being triggered again immediately upon -//! exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Clear the requested interrupt sources. - // - HWREG(ui32Base + QEI_O_ISC) = ui32IntFlags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/qei.h b/bsp/tm4c129x-dk/libraries/driverlib/qei.h deleted file mode 100644 index 031897ae31db0a0bbc208f0ef1cebf97a862c886..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/qei.h +++ /dev/null @@ -1,154 +0,0 @@ -//***************************************************************************** -// -// qei.h - Prototypes for the Quadrature Encoder Driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_QEI_H__ -#define __DRIVERLIB_QEI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to QEIConfigure as the ui32Config paramater. -// -//***************************************************************************** -#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only -#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges -#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse -#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse -#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature -#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir -#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB -#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB - -//***************************************************************************** -// -// Values that can be passed to QEIFilterConfigure as the ui32PreDiv -// parameter. -// -//***************************************************************************** -#define QEI_FILTCNT_2 0x00000000 // Filter Count of 2 System Clocks -#define QEI_FILTCNT_3 0x00010000 // Filter Count of 3 System Clocks -#define QEI_FILTCNT_4 0x00020000 // Filter Count of 4 System Clocks -#define QEI_FILTCNT_5 0x00030000 // Filter Count of 5 System Clocks -#define QEI_FILTCNT_6 0x00040000 // Filter Count of 6 System Clocks -#define QEI_FILTCNT_7 0x00050000 // Filter Count of 7 System Clocks -#define QEI_FILTCNT_8 0x00060000 // Filter Count of 8 System Clocks -#define QEI_FILTCNT_9 0x00070000 // Filter Count of 9 System Clocks -#define QEI_FILTCNT_10 0x00080000 // Filter Count of 10 System Clocks -#define QEI_FILTCNT_11 0x00090000 // Filter Count of 11 System Clocks -#define QEI_FILTCNT_12 0x000A0000 // Filter Count of 12 System Clocks -#define QEI_FILTCNT_13 0x000B0000 // Filter Count of 13 System Clocks -#define QEI_FILTCNT_14 0x000C0000 // Filter Count of 14 System Clocks -#define QEI_FILTCNT_15 0x000D0000 // Filter Count of 15 System Clocks -#define QEI_FILTCNT_16 0x000E0000 // Filter Count of 16 System Clocks -#define QEI_FILTCNT_17 0x000F0000 // Filter Count of 17 System Clocks - -//***************************************************************************** -// -// Values that can be passed to QEIVelocityConfigure as the ui32PreDiv -// parameter. -// -//***************************************************************************** -#define QEI_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 - -//***************************************************************************** -// -// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts -// as the ui32IntFlags parameter, and returned by QEIGetIntStatus. -// -//***************************************************************************** -#define QEI_INTERROR 0x00000008 // Phase error detected -#define QEI_INTDIR 0x00000004 // Direction change -#define QEI_INTTIMER 0x00000002 // Velocity timer expired -#define QEI_INTINDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void QEIEnable(uint32_t ui32Base); -extern void QEIDisable(uint32_t ui32Base); -extern void QEIConfigure(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32MaxPosition); -extern uint32_t QEIPositionGet(uint32_t ui32Base); -extern void QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position); -extern int32_t QEIDirectionGet(uint32_t ui32Base); -extern bool QEIErrorGet(uint32_t ui32Base); -extern void QEIFilterEnable(uint32_t ui32Base); -extern void QEIFilterDisable(uint32_t ui32Base); -extern void QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt); -extern void QEIVelocityEnable(uint32_t ui32Base); -extern void QEIVelocityDisable(uint32_t ui32Base); -extern void QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv, - uint32_t ui32Period); -extern uint32_t QEIVelocityGet(uint32_t ui32Base); -extern void QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void QEIIntUnregister(uint32_t ui32Base); -extern void QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t QEIIntStatus(uint32_t ui32Base, bool bMasked); -extern void QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_QEI_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/readme.txt b/bsp/tm4c129x-dk/libraries/driverlib/readme.txt deleted file mode 100644 index 1f90c23656c7c3ff9d849a627afff401c4523f90..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/readme.txt +++ /dev/null @@ -1,36 +0,0 @@ -This project will build the TivaWare Peripheral Driver Library. - -------------------------------------------------------------------------------- - -Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -Software License Agreement - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions - are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the - distribution. - - Neither the name of Texas Instruments Incorporated nor the names of - its contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. diff --git a/bsp/tm4c129x-dk/libraries/driverlib/rom.h b/bsp/tm4c129x-dk/libraries/driverlib/rom.h deleted file mode 100644 index 2ffdab87e5f7daf5d0ea4a46e9a31f36680605cd..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/rom.h +++ /dev/null @@ -1,8346 +0,0 @@ -//***************************************************************************** -// -// rom.h - Macros to facilitate calling functions in the ROM. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_ROM_H__ -#define __DRIVERLIB_ROM_H__ - -#ifndef DEPRECATED -//***************************************************************************** -// -// ROM selection labels changed between TivaWare 2.0.1 and 2.1. The following -// labels are intended to ensure backwards compatibility for applications -// which have not yet been updated to use the replacement labels. -// -//***************************************************************************** -#ifdef TARGET_IS_SNOWFLAKE_RA0 -#define TARGET_IS_TM4C129_RA0 -#endif -#ifdef TARGET_IS_SNOWFLAKE_RA1 -#define TARGET_IS_TM4C129_RA1 -#endif -#ifdef TARGET_IS_SNOWFLAKE_RA2 -#define TARGET_IS_TM4C129_RA2 -#endif -#ifdef TARGET_IS_BLIZZARD_RA1 -#define TARGET_IS_TM4C123_RA1 -#endif -#ifdef TARGET_IS_BLIZZARD_RA2 -#define TARGET_IS_TM4C123_RA2 -#endif -#ifdef TARGET_IS_BLIZZARD_RA3 -#define TARGET_IS_TM4C123_RA3 -#endif -#ifdef TARGET_IS_BLIZZARD_RB0 -#define TARGET_IS_TM4C123_RB0 -#endif -#ifdef TARGET_IS_BLIZZARD_RB1 -#define TARGET_IS_TM4C123_RB1 -#endif -#endif - -//***************************************************************************** -// -// Pointers to the main API tables. -// -//***************************************************************************** -#define ROM_APITABLE ((uint32_t *)0x01000010) -#define ROM_VERSION (ROM_APITABLE[0]) -#define ROM_UARTTABLE ((uint32_t *)(ROM_APITABLE[1])) -#define ROM_SSITABLE ((uint32_t *)(ROM_APITABLE[2])) -#define ROM_I2CTABLE ((uint32_t *)(ROM_APITABLE[3])) -#define ROM_GPIOTABLE ((uint32_t *)(ROM_APITABLE[4])) -#define ROM_ADCTABLE ((uint32_t *)(ROM_APITABLE[5])) -#define ROM_COMPARATORTABLE ((uint32_t *)(ROM_APITABLE[6])) -#define ROM_FLASHTABLE ((uint32_t *)(ROM_APITABLE[7])) -#define ROM_PWMTABLE ((uint32_t *)(ROM_APITABLE[8])) -#define ROM_QEITABLE ((uint32_t *)(ROM_APITABLE[9])) -#define ROM_SYSTICKTABLE ((uint32_t *)(ROM_APITABLE[10])) -#define ROM_TIMERTABLE ((uint32_t *)(ROM_APITABLE[11])) -#define ROM_WATCHDOGTABLE ((uint32_t *)(ROM_APITABLE[12])) -#define ROM_SYSCTLTABLE ((uint32_t *)(ROM_APITABLE[13])) -#define ROM_INTERRUPTTABLE ((uint32_t *)(ROM_APITABLE[14])) -#define ROM_USBTABLE ((uint32_t *)(ROM_APITABLE[16])) -#define ROM_UDMATABLE ((uint32_t *)(ROM_APITABLE[17])) -#define ROM_CANTABLE ((uint32_t *)(ROM_APITABLE[18])) -#define ROM_HIBERNATETABLE ((uint32_t *)(ROM_APITABLE[19])) -#define ROM_MPUTABLE ((uint32_t *)(ROM_APITABLE[20])) -#define ROM_SOFTWARETABLE ((uint32_t *)(ROM_APITABLE[21])) -#define ROM_EPITABLE ((uint32_t *)(ROM_APITABLE[23])) -#define ROM_EEPROMTABLE ((uint32_t *)(ROM_APITABLE[24])) -#define ROM_FPUTABLE ((uint32_t *)(ROM_APITABLE[26])) -#define ROM_SMBUSTABLE ((uint32_t *)(ROM_APITABLE[29])) -#define ROM_SYSEXCTABLE ((uint32_t *)(ROM_APITABLE[30])) -#define ROM_ONEWIRETABLE ((uint32_t *)(ROM_APITABLE[34])) -#define ROM_SPIFLASHTABLE ((uint32_t *)(ROM_APITABLE[38])) -#define ROM_LCDTABLE ((uint32_t *)(ROM_APITABLE[41])) -#define ROM_EMACTABLE ((uint32_t *)(ROM_APITABLE[42])) -#define ROM_AESTABLE ((uint32_t *)(ROM_APITABLE[43])) -#define ROM_CRCTABLE ((uint32_t *)(ROM_APITABLE[44])) -#define ROM_DESTABLE ((uint32_t *)(ROM_APITABLE[45])) -#define ROM_SHAMD5TABLE ((uint32_t *)(ROM_APITABLE[46])) - -//***************************************************************************** -// -// Macros for calling ROM functions in the ADC API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceDataGet \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum, \ - uint32_t *pui32Buffer))ROM_ADCTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum, \ - bool bMasked))ROM_ADCTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum, \ - uint32_t ui32Trigger, \ - uint32_t ui32Priority))ROM_ADCTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceStepConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum, \ - uint32_t ui32Step, \ - uint32_t ui32Config))ROM_ADCTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceOverflow \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceOverflowClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceUnderflow \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceUnderflowClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCProcessorTrigger \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCHardwareOversampleConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Factor))ROM_ADCTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp, \ - uint32_t ui32Config))ROM_ADCTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorRegionSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp, \ - uint32_t ui32LowRef, \ - uint32_t ui32HighRef))ROM_ADCTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorReset \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp, \ - bool bTrigger, \ - bool bInterrupt))ROM_ADCTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorIntStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Status))ROM_ADCTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCReferenceSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Ref))ROM_ADCTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCReferenceGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCPhaseDelaySet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Phase))ROM_ADCTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCPhaseDelayGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntDisableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_ADCTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntEnableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_ADCTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntStatusEx \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_ADCTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCBusy \ - ((bool (*)(uint32_t ui32Base))ROM_ADCTABLE[34]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the AES API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_AESTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESAuthLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_AESTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_AESTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataAuth \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src, \ - uint32_t ui32Length, \ - uint32_t *pui32Tag))ROM_AESTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src, \ - uint32_t *pui32Dest, \ - uint32_t ui32Length))ROM_AESTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataProcessAuth \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src, \ - uint32_t *pui32Dest, \ - uint32_t ui32Length, \ - uint32_t *pui32AuthSrc, \ - uint32_t ui32AuthLength, \ - uint32_t *pui32Tag))ROM_AESTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Dest))ROM_AESTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataReadNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Dest))ROM_AESTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_AESTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_AESTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_AESTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_AESTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIVSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32IVdata))ROM_AESTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESKey1Set \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Key, \ - uint32_t ui32Keysize))ROM_AESTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESKey2Set \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Key, \ - uint32_t ui32Keysize))ROM_AESTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESKey3Set \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Key))ROM_AESTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint64_t ui64Length))ROM_AESTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESReset \ - ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESTagRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32TagData))ROM_AESTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIVRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32IVdata))ROM_AESTABLE[22]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CAN API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntClr))ROM_CANTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANInit \ - ((void (*)(uint32_t ui32Base))ROM_CANTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANEnable \ - ((void (*)(uint32_t ui32Base))ROM_CANTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANDisable \ - ((void (*)(uint32_t ui32Base))ROM_CANTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANBitTimingSet \ - ((void (*)(uint32_t ui32Base, \ - tCANBitClkParms *psClkParms))ROM_CANTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANBitTimingGet \ - ((void (*)(uint32_t ui32Base, \ - tCANBitClkParms *psClkParms))ROM_CANTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANMessageSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ObjID, \ - tCANMsgObject *psMsgObject, \ - tMsgObjType eMsgType))ROM_CANTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANMessageGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ObjID, \ - tCANMsgObject *psMsgObject, \ - bool bClrPendingInt))ROM_CANTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANStatusGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - tCANStsReg eStatusReg))ROM_CANTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANMessageClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ObjID))ROM_CANTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_CANTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_CANTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - tCANIntStsReg eIntStsReg))ROM_CANTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANRetryGet \ - ((bool (*)(uint32_t ui32Base))ROM_CANTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANRetrySet \ - ((void (*)(uint32_t ui32Base, \ - bool bAutoRetry))ROM_CANTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANErrCntrGet \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32RxCount, \ - uint32_t *pui32TxCount))ROM_CANTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANBitRateSet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32SourceClock, \ - uint32_t ui32BitRate))ROM_CANTABLE[16]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Comparator API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp))ROM_COMPARATORTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp, \ - uint32_t ui32Config))ROM_COMPARATORTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorRefSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Ref))ROM_COMPARATORTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorValueGet \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t ui32Comp))ROM_COMPARATORTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp))ROM_COMPARATORTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp))ROM_COMPARATORTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorIntStatus \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t ui32Comp, \ - bool bMasked))ROM_COMPARATORTABLE[6]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CRC API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CRCConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CRCConfig))ROM_CRCTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CRCDataProcess \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t *pui32DataIn, \ - uint32_t ui32DataLength, \ - bool bPPResult))ROM_CRCTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CRCDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_CRCTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CRCResultRead \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bPPResult))ROM_CRCTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CRCSeedSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seed))ROM_CRCTABLE[4]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the DES API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_DESTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_DESTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDataRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Dest))ROM_DESTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDataReadNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Dest))ROM_DESTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDataProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src, \ - uint32_t *pui32Dest, \ - uint32_t ui32Length))ROM_DESTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_DESTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_DESTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_DESTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_DESTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESIVSet \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32IVdata))ROM_DESTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Key))ROM_DESTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_DESTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESReset \ - ((void (*)(uint32_t ui32Base))ROM_DESTABLE[15]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the EEPROM API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMRead \ - ((void (*)(uint32_t *pui32Data, \ - uint32_t ui32Address, \ - uint32_t ui32Count))ROM_EEPROMTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockCountGet \ - ((uint32_t (*)(void))ROM_EEPROMTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockHide \ - ((void (*)(uint32_t ui32Block))ROM_EEPROMTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockLock \ - ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockPasswordSet \ - ((uint32_t (*)(uint32_t ui32Block, \ - uint32_t *pui32Password, \ - uint32_t ui32Count))ROM_EEPROMTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockProtectGet \ - ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockProtectSet \ - ((uint32_t (*)(uint32_t ui32Block, \ - uint32_t ui32Protect))ROM_EEPROMTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockUnlock \ - ((uint32_t (*)(uint32_t ui32Block, \ - uint32_t *pui32Password, \ - uint32_t ui32Count))ROM_EEPROMTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMIntClear \ - ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMIntDisable \ - ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMIntEnable \ - ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMIntStatus \ - ((uint32_t (*)(bool bMasked))ROM_EEPROMTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) -#define ROM_EEPROMMassErase \ - ((uint32_t (*)(void))ROM_EEPROMTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMProgram \ - ((uint32_t (*)(uint32_t *pui32Data, \ - uint32_t ui32Address, \ - uint32_t ui32Count))ROM_EEPROMTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMProgramNonBlocking \ - ((uint32_t (*)(uint32_t ui32Data, \ - uint32_t ui32Address))ROM_EEPROMTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMSizeGet \ - ((uint32_t (*)(void))ROM_EEPROMTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMStatusGet \ - ((uint32_t (*)(void))ROM_EEPROMTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMInit \ - ((uint32_t (*)(void))ROM_EEPROMTABLE[17]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the EPI API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_EPITABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_EPITABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIDividerSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Divider))ROM_EPITABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigSDRAMSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32Refresh))ROM_EPITABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigGPModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32FrameCount, \ - uint32_t ui32MaxWait))ROM_EPITABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB8Set \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32MaxWait))ROM_EPITABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB16Set \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32MaxWait))ROM_EPITABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIAddressMapSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Map))ROM_EPITABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel, \ - uint32_t ui32DataSize, \ - uint32_t ui32Address))ROM_EPITABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadStart \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel, \ - uint32_t ui32Count))ROM_EPITABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadStop \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_EPITABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadCount \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_EPITABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadAvail \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadGet32 \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Count, \ - uint32_t *pui32Buf))ROM_EPITABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadGet16 \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Count, \ - uint16_t *pui16Buf))ROM_EPITABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadGet8 \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Count, \ - uint8_t *pui8Buf))ROM_EPITABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIFIFOConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_EPITABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIWriteFIFOCountGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_EPITABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_EPITABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIIntErrorStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIIntErrorClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ErrFlags))ROM_EPITABLE[21]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIDividerCSSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32Divider))ROM_EPITABLE[22]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIDMATxCount \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Count))ROM_EPITABLE[23]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB8CSSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32Config))ROM_EPITABLE[24]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB16CSSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32Config))ROM_EPITABLE[25]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB8TimingSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32Config))ROM_EPITABLE[26]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB16TimingSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32Config))ROM_EPITABLE[27]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIPSRAMConfigRegSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32CR))ROM_EPITABLE[28]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIPSRAMConfigRegRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS))ROM_EPITABLE[29]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIPSRAMConfigRegGetNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t *pui32CR))ROM_EPITABLE[30]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIPSRAMConfigRegGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32CS))ROM_EPITABLE[31]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the EMAC API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_EMACTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACAddrGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Index, \ - uint8_t *pui8MACAddr))ROM_EMACTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Index, \ - const uint8_t *pui8MACAddr))ROM_EMACTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACConfigGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Config, \ - uint32_t *pui32Mode, \ - uint32_t *pui32RxMaxFrameSize))ROM_EMACTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32ModeFlags, \ - uint32_t ui32RxMaxFrameSize))ROM_EMACTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACDMAStateGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACFrameFilterGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACFrameFilterSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32FilterOpts))ROM_EMACTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACInit \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SysClk, \ - uint32_t ui32BusConfig, \ - uint32_t ui32RxBurst, \ - uint32_t ui32TxBurst, \ - uint32_t ui32DescSkipSize))ROM_EMACTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_EMACTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_EMACTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_EMACTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_EMACTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYPowerOff \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr))ROM_EMACTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYPowerOn \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr))ROM_EMACTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYRead \ - ((uint16_t (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr, \ - uint8_t ui8RegAddr))ROM_EMACTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr, \ - uint8_t ui8RegAddr, \ - uint16_t ui16Data))ROM_EMACTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACReset \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDisable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDMACurrentBufferGet \ - ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDMACurrentDescriptorGet \ - ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDMADescriptorListGet \ - ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDMADescriptorListSet \ - ((void (*)(uint32_t ui32Base, \ - tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDMAPollDemand \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxEnable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxWatchdogTimerSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Timeout))ROM_EMACTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACStatusGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDisable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDMACurrentBufferGet \ - ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDMACurrentDescriptorGet \ - ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDMADescriptorListGet \ - ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDMADescriptorListSet \ - ((void (*)(uint32_t ui32Base, \ - tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDMAPollDemand \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxEnable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxFlush \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACAddrFilterGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Index))ROM_EMACTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACAddrFilterSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Index, \ - uint32_t ui32Config))ROM_EMACTABLE[36]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACHashFilterBitCalculate \ - ((uint32_t (*)(uint8_t *pui8MACAddr))ROM_EMACTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACHashFilterGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32HashHi, \ - uint32_t *pui32HashLo))ROM_EMACTABLE[38]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACHashFilterSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32HashHi, \ - uint32_t ui32HashLo))ROM_EMACTABLE[39]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACNumAddrGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[40]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYExtendedRead \ - ((uint16_t (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr, \ - uint16_t ui16RegAddr))ROM_EMACTABLE[41]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYExtendedWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr, \ - uint16_t ui16RegAddr, \ - uint16_t ui16Data))ROM_EMACTABLE[42]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPowerManagementControlGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[43]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPowerManagementControlSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_EMACTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPowerManagementStatusGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[45]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRemoteWakeUpFrameFilterGet \ - ((void (*)(uint32_t ui32Base, \ - tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[46]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRemoteWakeUpFrameFilterSet \ - ((void (*)(uint32_t ui32Base, \ - const tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[47]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampAddendSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seconds))ROM_EMACTABLE[48]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampConfigGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t *pui32SubSecondInc))ROM_EMACTABLE[49]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32SubSecondInc))ROM_EMACTABLE[50]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampDisable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampEnable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[52]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampIntStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[53]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampPPSCommand \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Cmd))ROM_EMACTABLE[54]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampPPSCommandModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_EMACTABLE[55]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampPPSPeriodSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Period, \ - uint32_t ui32Width))ROM_EMACTABLE[56]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampPPSSimpleModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32FreqConfig))ROM_EMACTABLE[57]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampSysTimeGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Seconds, \ - uint32_t *pui32SubSeconds))ROM_EMACTABLE[58]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampSysTimeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seconds, \ - uint32_t ui32SubSeconds))ROM_EMACTABLE[59]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampSysTimeUpdate \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seconds, \ - uint32_t ui32SubSeconds, \ - bool bInc))ROM_EMACTABLE[60]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampTargetIntDisable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[61]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampTargetIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[62]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampTargetSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seconds, \ - uint32_t ui32Nanoseconds))ROM_EMACTABLE[63]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANHashFilterBitCalculate \ - ((uint32_t (*)(uint16_t ui16Tag))ROM_EMACTABLE[64]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANHashFilterGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[65]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANHashFilterSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Hash))ROM_EMACTABLE[66]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANRxConfigGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint16_t *pui16Tag))ROM_EMACTABLE[67]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANRxConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint16_t ui16Tag, \ - uint32_t ui32Config))ROM_EMACTABLE[68]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANTxConfigGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint16_t *pui16Tag))ROM_EMACTABLE[69]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANTxConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint16_t ui16Tag, \ - uint32_t ui32Config))ROM_EMACTABLE[70]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UpdateEMAC \ - ((void (*)(uint32_t ui32Clock))ROM_EMACTABLE[71]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Flash API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashProgram \ - ((int32_t (*)(uint32_t *pui32Data, \ - uint32_t ui32Address, \ - uint32_t ui32Count))ROM_FLASHTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashErase \ - ((int32_t (*)(uint32_t ui32Address))ROM_FLASHTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashProtectGet \ - ((tFlashProtection (*)(uint32_t ui32Address))ROM_FLASHTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashProtectSet \ - ((int32_t (*)(uint32_t ui32Address, \ - tFlashProtection eProtect))ROM_FLASHTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashProtectSave \ - ((int32_t (*)(void))ROM_FLASHTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashUserGet \ - ((int32_t (*)(uint32_t *pui32User0, \ - uint32_t *pui32User1))ROM_FLASHTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashUserSet \ - ((int32_t (*)(uint32_t ui32User0, \ - uint32_t ui32User1))ROM_FLASHTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashUserSave \ - ((int32_t (*)(void))ROM_FLASHTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashIntEnable \ - ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashIntDisable \ - ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashIntStatus \ - ((uint32_t (*)(bool bMasked))ROM_FLASHTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashIntClear \ - ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[13]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the FPU API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUEnable \ - ((void (*)(void))ROM_FPUTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUDisable \ - ((void (*)(void))ROM_FPUTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUFlushToZeroModeSet \ - ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUHalfPrecisionModeSet \ - ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPULazyStackingEnable \ - ((void (*)(void))ROM_FPUTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUNaNModeSet \ - ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPURoundingModeSet \ - ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUStackingDisable \ - ((void (*)(void))ROM_FPUTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUStackingEnable \ - ((void (*)(void))ROM_FPUTABLE[8]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the GPIO API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinWrite \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins, \ - uint8_t ui8Val))ROM_GPIOTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIODirModeSet \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins, \ - uint32_t ui32PinIO))ROM_GPIOTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIODirModeGet \ - ((uint32_t (*)(uint32_t ui32Port, \ - uint8_t ui8Pin))ROM_GPIOTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntTypeSet \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins, \ - uint32_t ui32IntType))ROM_GPIOTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntTypeGet \ - ((uint32_t (*)(uint32_t ui32Port, \ - uint8_t ui8Pin))ROM_GPIOTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_GPIOPadConfigSet \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins, \ - uint32_t ui32Strength, \ - uint32_t ui32PadType))ROM_GPIOTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPadConfigGet \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pin, \ - uint32_t *pui32Strength, \ - uint32_t *pui32PadType))ROM_GPIOTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinRead \ - ((int32_t (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_GPIOPinTypeCAN \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeComparator \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeGPIOInput \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeGPIOOutput \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeI2C \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypePWM \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeQEI \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeSSI \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeTimer \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeUART \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeGPIOOutputOD \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeADC \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeUSBDigital \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinConfigure \ - ((void (*)(uint32_t ui32PinConfig))ROM_GPIOTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeUSBAnalog \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIODMATriggerEnable \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIODMATriggerDisable \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOADCTriggerEnable \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOADCTriggerDisable \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeI2CSCL \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[39]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeOneWire \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeWakeHigh \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[48]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeWakeLow \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[49]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntClear \ - ((void (*)(uint32_t ui32Port, \ - uint32_t ui32IntFlags))ROM_GPIOTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntDisable \ - ((void (*)(uint32_t ui32Port, \ - uint32_t ui32IntFlags))ROM_GPIOTABLE[52]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntEnable \ - ((void (*)(uint32_t ui32Port, \ - uint32_t ui32IntFlags))ROM_GPIOTABLE[53]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntStatus \ - ((uint32_t (*)(uint32_t ui32Port, \ - bool bMasked))ROM_GPIOTABLE[54]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Hibernate API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateIntClear \ - ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateEnableExpClk \ - ((void (*)(uint32_t ui32HibClk))ROM_HIBERNATETABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateDisable \ - ((void (*)(void))ROM_HIBERNATETABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCEnable \ - ((void (*)(void))ROM_HIBERNATETABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCDisable \ - ((void (*)(void))ROM_HIBERNATETABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateWakeSet \ - ((void (*)(uint32_t ui32WakeFlags))ROM_HIBERNATETABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateWakeGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateLowBatSet \ - ((void (*)(uint32_t ui32LowBatFlags))ROM_HIBERNATETABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateLowBatGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCSet \ - ((void (*)(uint32_t ui32RTCValue))ROM_HIBERNATETABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCTrimSet \ - ((void (*)(uint32_t ui32Trim))ROM_HIBERNATETABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCTrimGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateDataSet \ - ((void (*)(uint32_t *pui32Data, \ - uint32_t ui32Count))ROM_HIBERNATETABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateDataGet \ - ((void (*)(uint32_t *pui32Data, \ - uint32_t ui32Count))ROM_HIBERNATETABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRequest \ - ((void (*)(void))ROM_HIBERNATETABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateIntEnable \ - ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateIntDisable \ - ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateIntStatus \ - ((uint32_t (*)(bool bMasked))ROM_HIBERNATETABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateIsActive \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCSSGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[27]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateClockConfig \ - ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateBatCheckStart \ - ((void (*)(void))ROM_HIBERNATETABLE[29]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateBatCheckDone \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[30]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateGPIORetentionEnable \ - ((void (*)(void))ROM_HIBERNATETABLE[31]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateGPIORetentionDisable \ - ((void (*)(void))ROM_HIBERNATETABLE[32]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateGPIORetentionGet \ - ((bool (*)(void))ROM_HIBERNATETABLE[33]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateCounterMode \ - ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateCalendarSet \ - ((void (*)(struct tm *psTime))ROM_HIBERNATETABLE[35]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateCalendarGet \ - ((int (*)(struct tm *psTime))ROM_HIBERNATETABLE[36]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateCalendarMatchSet \ - ((void (*)(uint32_t ui32Index, \ - struct tm *psTime))ROM_HIBERNATETABLE[37]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateCalendarMatchGet \ - ((void (*)(uint32_t ui32Index, \ - struct tm *psTime))ROM_HIBERNATETABLE[38]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperDisable \ - ((void (*)(void))ROM_HIBERNATETABLE[39]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperEnable \ - ((void (*)(void))ROM_HIBERNATETABLE[40]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperEventsClear \ - ((void (*)(void))ROM_HIBERNATETABLE[41]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperEventsConfig \ - ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[42]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperEventsGet \ - ((bool (*)(uint32_t ui32Index, \ - uint32_t *pui32RTC, \ - uint32_t *pui32Event))ROM_HIBERNATETABLE[43]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperExtOscValid \ - ((bool (*)(void))ROM_HIBERNATETABLE[44]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperExtOscRecover \ - ((void (*)(void))ROM_HIBERNATETABLE[45]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperIODisable \ - ((void (*)(uint32_t ui32Input))ROM_HIBERNATETABLE[46]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperIOEnable \ - ((void (*)(uint32_t ui32Input, \ - uint32_t ui32Config))ROM_HIBERNATETABLE[47]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperStatusGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[48]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCMatchGet \ - ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[49]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCMatchSet \ - ((void (*)(uint32_t ui32Match, \ - uint32_t ui32Value))ROM_HIBERNATETABLE[50]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCSSMatchGet \ - ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[51]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCSSMatchSet \ - ((void (*)(uint32_t ui32Match, \ - uint32_t ui32Value))ROM_HIBERNATETABLE[52]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the I2C API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterDataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterInitExpClk \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32I2CClk, \ - bool bFast))ROM_I2CTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveInit \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8SlaveAddr))ROM_I2CTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntStatus \ - ((bool (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntStatus \ - ((bool (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntClear \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntClear \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterSlaveAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8SlaveAddr, \ - bool bReceive))ROM_I2CTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterBusy \ - ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterBusBusy \ - ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterControl \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Cmd))ROM_I2CTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterErr \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterDataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveDataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveDataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UpdateI2C \ - ((void (*)(void))ROM_I2CTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntEnableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntDisableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntStatusEx \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntClearEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntEnableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntDisableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntStatusEx \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntClearEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterTimeoutSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Value))ROM_I2CTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveACKOverride \ - ((void (*)(uint32_t ui32Base, \ - bool bEnable))ROM_I2CTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveACKValueSet \ - ((void (*)(uint32_t ui32Base, \ - bool bACK))ROM_I2CTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveAddressSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8AddrNum, \ - uint8_t ui8SlaveAddr))ROM_I2CTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterLineStateGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[38]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CTxFIFOConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[39]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CTxFIFOFlush \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CRxFIFOConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[41]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CRxFIFOFlush \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[42]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CFIFOStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[43]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CFIFODataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CFIFODataPutNonBlocking \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[45]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CFIFODataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[46]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CFIFODataGetNonBlocking \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint8_t *pui8Data))ROM_I2CTABLE[47]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterBurstLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Length))ROM_I2CTABLE[48]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterBurstCountGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[49]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveFIFODisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[50]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveFIFOEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterGlitchFilterConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[54]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Interrupt API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntEnable \ - ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntMasterEnable \ - ((bool (*)(void))ROM_INTERRUPTTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntMasterDisable \ - ((bool (*)(void))ROM_INTERRUPTTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntDisable \ - ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPriorityGroupingSet \ - ((void (*)(uint32_t ui32Bits))ROM_INTERRUPTTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPriorityGroupingGet \ - ((uint32_t (*)(void))ROM_INTERRUPTTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPrioritySet \ - ((void (*)(uint32_t ui32Interrupt, \ - uint8_t ui8Priority))ROM_INTERRUPTTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPriorityGet \ - ((int32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPendSet \ - ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPendClear \ - ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPriorityMaskSet \ - ((void (*)(uint32_t ui32PriorityMask))ROM_INTERRUPTTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPriorityMaskGet \ - ((uint32_t (*)(void))ROM_INTERRUPTTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntIsEnabled \ - ((uint32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntTrigger \ - ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[13]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the LCD API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_LCDTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDClockReset \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Clocks))ROM_LCDTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDDMAConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_LCDTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDCommandWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint16_t ui16Cmd))ROM_LCDTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_LCDTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDDataRead \ - ((uint16_t (*)(uint32_t ui32Base, \ - uint32_t ui32CS))ROM_LCDTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint16_t ui16Data))ROM_LCDTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDDMADisable \ - ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDDMAWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - const uint32_t *pui32Data, \ - uint32_t ui32Count))ROM_LCDTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDIndexedRead \ - ((uint16_t (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint16_t ui16Addr))ROM_LCDTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDIndexedWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint16_t ui16Addr, \ - uint16_t ui16Data))ROM_LCDTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDStatusRead \ - ((uint16_t (*)(uint32_t ui32Base, \ - uint32_t ui32CS))ROM_LCDTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDTimingSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - const tLCDIDDTiming *pTiming))ROM_LCDTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_LCDTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_LCDTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_LCDTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDModeSet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint8_t ui8Mode, \ - uint32_t ui32PixClk, \ - uint32_t ui32SysClk))ROM_LCDTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterACBiasIntCountSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Count))ROM_LCDTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint8_t ui8PalLoadDelay))ROM_LCDTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterDisable \ - ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterEnable \ - ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterFrameBufferSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Buffer, \ - uint32_t *pui32Addr, \ - uint32_t ui32NumBytes))ROM_LCDTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterPaletteSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Type, \ - uint32_t *pui32PalAddr, \ - const uint32_t *pui32SrcColors, \ - uint32_t ui32Start, \ - uint32_t ui32Count))ROM_LCDTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterSubPanelConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags, \ - uint32_t ui32BottomLines, \ - uint32_t ui32DefaultPixel))ROM_LCDTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterSubPanelDisable \ - ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterSubPanelEnable \ - ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterTimingSet \ - ((void (*)(uint32_t ui32Base, \ - const tLCDRasterTiming *pTiming))ROM_LCDTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterEnabled \ - ((bool (*)(uint32_t ui32Base))ROM_LCDTABLE[27]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the MPU API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPUEnable \ - ((void (*)(uint32_t ui32MPUConfig))ROM_MPUTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPUDisable \ - ((void (*)(void))ROM_MPUTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPURegionCountGet \ - ((uint32_t (*)(void))ROM_MPUTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPURegionEnable \ - ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPURegionDisable \ - ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPURegionSet \ - ((void (*)(uint32_t ui32Region, \ - uint32_t ui32Addr, \ - uint32_t ui32Flags))ROM_MPUTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPURegionGet \ - ((void (*)(uint32_t ui32Region, \ - uint32_t *pui32Addr, \ - uint32_t *pui32Flags))ROM_MPUTABLE[6]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the OneWire API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_ONEWIRETABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireBusReset \ - ((void (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireBusStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireDataGet \ - ((void (*)(uint32_t u3i2Base, \ - uint32_t *pui32Data))ROM_ONEWIRETABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireDataGetNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Data))ROM_ONEWIRETABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireInit \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32InitFlags))ROM_ONEWIRETABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_ONEWIRETABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_ONEWIRETABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_ONEWIRETABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireTransaction \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32OpFlags, \ - uint32_t ui32Data, \ - uint32_t ui32BitCnt))ROM_ONEWIRETABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[11]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the PWM API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMPulseWidthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOut, \ - uint32_t ui32Width))ROM_PWMTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Config))ROM_PWMTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenPeriodSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Period))ROM_PWMTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenPeriodGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Gen))ROM_PWMTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen))ROM_PWMTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen))ROM_PWMTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMPulseWidthGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOut))ROM_PWMTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMDeadBandEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint16_t ui16Rise, \ - uint16_t ui16Fall))ROM_PWMTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMDeadBandDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen))ROM_PWMTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMSyncUpdate \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32GenBits))ROM_PWMTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMSyncTimeBase \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32GenBits))ROM_PWMTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMOutputState \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOutBits, \ - bool bEnable))ROM_PWMTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMOutputInvert \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOutBits, \ - bool bInvert))ROM_PWMTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMOutputFault \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOutBits, \ - bool bFaultSuppress))ROM_PWMTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenIntTrigEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32IntTrig))ROM_PWMTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenIntTrigDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32IntTrig))ROM_PWMTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - bool bMasked))ROM_PWMTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Ints))ROM_PWMTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32GenFault))ROM_PWMTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32GenFault))ROM_PWMTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMFaultIntClear \ - ((void (*)(uint32_t ui32Base))ROM_PWMTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_PWMTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMOutputFaultLevel \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOutBits, \ - bool bDriveHigh))ROM_PWMTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMFaultIntClearExt \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32FaultInts))ROM_PWMTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenFaultConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32MinFaultPeriod, \ - uint32_t ui32FaultSenses))ROM_PWMTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenFaultTriggerSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Group, \ - uint32_t ui32FaultTriggers))ROM_PWMTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenFaultTriggerGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Group))ROM_PWMTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenFaultStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Group))ROM_PWMTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenFaultClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Group, \ - uint32_t ui32FaultTriggers))ROM_PWMTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMClockSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_PWMTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMClockGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_PWMTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMOutputUpdateMode \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOutBits, \ - uint32_t ui32Mode))ROM_PWMTABLE[31]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the QEI API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIPositionGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIEnable \ - ((void (*)(uint32_t ui32Base))ROM_QEITABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIDisable \ - ((void (*)(uint32_t ui32Base))ROM_QEITABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32MaxPosition))ROM_QEITABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIPositionSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Position))ROM_QEITABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIDirectionGet \ - ((int32_t (*)(uint32_t ui32Base))ROM_QEITABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIErrorGet \ - ((bool (*)(uint32_t ui32Base))ROM_QEITABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIVelocityEnable \ - ((void (*)(uint32_t ui32Base))ROM_QEITABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIVelocityDisable \ - ((void (*)(uint32_t ui32Base))ROM_QEITABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIVelocityConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PreDiv, \ - uint32_t ui32Period))ROM_QEITABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIVelocityGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_QEITABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_QEITABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_QEITABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_QEITABLE[14]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SHAMD5 API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5IntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_SHAMD5TABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5ConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_SHAMD5TABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5DataProcess \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32DataSrc, \ - uint32_t ui32DataLength, \ - uint32_t *pui32HashResult))ROM_SHAMD5TABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5DataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_SHAMD5TABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5DataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_SHAMD5TABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5DMADisable \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5DMAEnable \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5HashLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_SHAMD5TABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5HMACKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_SHAMD5TABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5HMACPPKeyGenerate \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Key, \ - uint32_t *pui32PPKey))ROM_SHAMD5TABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5HMACPPKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_SHAMD5TABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5HMACProcess \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32DataSrc, \ - uint32_t ui32DataLength, \ - uint32_t *pui32HashResult))ROM_SHAMD5TABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5IntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5IntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5IntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5Reset \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5ResultRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Dest))ROM_SHAMD5TABLE[16]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SMBus API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterIntProcess \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusARPDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusARPEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusARPUDIDPacketDecode \ - ((void (*)(tSMBusUDID *pUDID, \ - uint8_t *pui8Address, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusARPUDIDPacketEncode \ - ((void (*)(tSMBusUDID *pUDID, \ - uint8_t ui8Address, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPAssignAddress \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPGetUDIDDir \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPGetUDIDGen \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPNotifyMaster \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPPrepareToARP \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPResetDeviceDir \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress))ROM_SMBUSTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPResetDeviceGen \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterBlockProcessCall \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8TxData, \ - uint8_t ui8TxSize, \ - uint8_t *pui8RxData))ROM_SMBUSTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterBlockRead \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterBlockWrite \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterByteReceive \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterByteSend \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Data))ROM_SMBUSTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterByteWordRead \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterByteWordWrite \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterHostNotify \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8OwnSlaveAddress, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterI2CRead \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterI2CWrite \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterI2CWriteRead \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t *pui8TxData, \ - uint8_t ui8TxSize, \ - uint8_t *pui8RxData, \ - uint8_t ui8RxSize))ROM_SMBUSTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterInit \ - ((void (*)(tSMBus *psSMBus, \ - uint32_t ui32I2CBase, \ - uint32_t ui32SMBusClock))ROM_SMBUSTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterIntEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterProcessCall \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8TxData, \ - uint8_t *pui8RxData))ROM_SMBUSTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterQuickCommand \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - bool bData))ROM_SMBUSTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusPECDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusPECEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusRxPacketSizeGet \ - ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveACKSend \ - ((void (*)(tSMBus *psSMBus, \ - bool bACK))ROM_SMBUSTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveAddressSet \ - ((void (*)(tSMBus *psSMBus, \ - uint8_t ui8AddressNum, \ - uint8_t ui8SlaveAddress))ROM_SMBUSTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveARPFlagARGet \ - ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveARPFlagARSet \ - ((void (*)(tSMBus *psSMBus, \ - bool bValue))ROM_SMBUSTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveARPFlagAVGet \ - ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveARPFlagAVSet \ - ((void (*)(tSMBus *psSMBus, \ - bool bValue))ROM_SMBUSTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveBlockTransferDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[36]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveBlockTransferEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveCommandGet \ - ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[38]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveI2CDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[39]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveI2CEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[40]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveInit \ - ((void (*)(tSMBus *psSMBus, \ - uint32_t ui32I2CBase))ROM_SMBUSTABLE[41]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveIntAddressGet \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[42]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveIntEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[43]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveIntProcess \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveManualACKDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[45]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveManualACKEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[46]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveManualACKStatusGet \ - ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[47]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveProcessCallDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[48]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveProcessCallEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[49]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveRxBufferSet \ - ((void (*)(tSMBus *psSMBus, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[50]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveTransferInit \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveTxBufferSet \ - ((void (*)(tSMBus *psSMBus, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[52]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveUDIDSet \ - ((void (*)(tSMBus *psSMBus, \ - tSMBusUDID *pUDID))ROM_SMBUSTABLE[53]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusStatusGet \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[54]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveDataSend \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[55]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusFIFOEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[56]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusFIFODisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[57]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusDMAEnable \ - ((void (*)(tSMBus *psSMBus, \ - uint8_t ui8TxChannel, \ - uint8_t ui8RxChannel))ROM_SMBUSTABLE[58]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusDMADisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[59]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SPIFlash API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashIntHandler \ - ((uint32_t (*)(tSPIFlashState *pState))ROM_SPIFLASHTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashInit \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Clock, \ - uint32_t ui32BitRate))ROM_SPIFLASHTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashWriteStatus \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Status))ROM_SPIFLASHTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashPageProgram \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr, \ - const uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SPIFLASHTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashPageProgramNonBlocking \ - ((void (*)(tSPIFlashState *pState, \ - uint32_t ui32Base, \ - uint32_t ui32Addr, \ - const uint8_t *pui8Data, \ - uint32_t ui32Count, \ - bool bUseDMA, \ - uint32_t ui32TxChannel))ROM_SPIFLASHTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SPIFLASHTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashReadNonBlocking \ - ((void (*)(tSPIFlashState *pState, \ - uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count, \ - bool bUseDMA, \ - uint32_t ui32TxChannel, \ - uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashWriteDisable \ - ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashReadStatus \ - ((uint8_t (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashWriteEnable \ - ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashFastRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SPIFLASHTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashFastReadNonBlocking \ - ((void (*)(tSPIFlashState *pState, \ - uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count, \ - bool bUseDMA, \ - uint32_t ui32TxChannel, \ - uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashSectorErase \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr))ROM_SPIFLASHTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashDualRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SPIFLASHTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashDualReadNonBlocking \ - ((void (*)(tSPIFlashState *pState, \ - uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count, \ - bool bUseDMA, \ - uint32_t ui32TxChannel, \ - uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashBlockErase32 \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr))ROM_SPIFLASHTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashQuadRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SPIFLASHTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashQuadReadNonBlocking \ - ((void (*)(tSPIFlashState *pState, \ - uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count, \ - bool bUseDMA, \ - uint32_t ui32TxChannel, \ - uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashReadID \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8ManufacturerID, \ - uint16_t *pui16DeviceID))ROM_SPIFLASHTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashChipErase \ - ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashBlockErase64 \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr))ROM_SPIFLASHTABLE[20]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SSI API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDataPut \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_SSITABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SSIClk, \ - uint32_t ui32Protocol, \ - uint32_t ui32Mode, \ - uint32_t ui32BitRate, \ - uint32_t ui32DataWidth))ROM_SSITABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIEnable \ - ((void (*)(uint32_t ui32Base))ROM_SSITABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDisable \ - ((void (*)(uint32_t ui32Base))ROM_SSITABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SSITABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SSITABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_SSITABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SSITABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDataPutNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_SSITABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDataGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Data))ROM_SSITABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDataGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t *pui32Data))ROM_SSITABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UpdateSSI \ - ((void (*)(void))ROM_SSITABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_SSITABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_SSITABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIBusy \ - ((bool (*)(uint32_t ui32Base))ROM_SSITABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIClockSourceGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_SSITABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIClockSourceSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Source))ROM_SSITABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIAdvModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_SSITABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIAdvDataPutFrameEnd \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_SSITABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIAdvDataPutFrameEndNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_SSITABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIAdvFrameHoldEnable \ - ((void (*)(uint32_t ui32Base))ROM_SSITABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIAdvFrameHoldDisable \ - ((void (*)(uint32_t ui32Base))ROM_SSITABLE[21]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SysCtl API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlSleep \ - ((void (*)(void))ROM_SYSCTLTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlSRAMSizeGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlFlashSizeGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralPresent \ - ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralReset \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralEnable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralDisable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralSleepEnable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralSleepDisable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralDeepSleepEnable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralDeepSleepDisable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralClockGating \ - ((void (*)(bool bEnable))ROM_SYSCTLTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlIntEnable \ - ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlIntDisable \ - ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlIntClear \ - ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlIntStatus \ - ((uint32_t (*)(bool bMasked))ROM_SYSCTLTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlReset \ - ((void (*)(void))ROM_SYSCTLTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlDeepSleep \ - ((void (*)(void))ROM_SYSCTLTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlResetCauseGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlResetCauseClear \ - ((void (*)(uint32_t ui32Causes))ROM_SYSCTLTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlClockSet \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlClockGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlPWMClockSet \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlPWMClockGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlUSBPLLEnable \ - ((void (*)(void))ROM_SYSCTLTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlUSBPLLDisable \ - ((void (*)(void))ROM_SYSCTLTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlDelay \ - ((void (*)(uint32_t ui32Count))ROM_SYSCTLTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralReady \ - ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralPowerOn \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[36]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralPowerOff \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlMOSCConfigSet \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPIOSCCalibrate \ - ((uint32_t (*)(uint32_t ui32Type))ROM_SYSCTLTABLE[45]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlDeepSleepClockSet \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[46]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlDeepSleepClockConfigSet \ - ((void (*)(uint32_t ui32Div, \ - uint32_t ui32Config))ROM_SYSCTLTABLE[47]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlResetBehaviorSet \ - ((void (*)(uint32_t ui32Behavior))ROM_SYSCTLTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlResetBehaviorGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[52]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlFlashSectorSizeGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[54]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlVoltageEventConfig \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[55]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlVoltageEventStatus \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[56]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlVoltageEventClear \ - ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[57]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlNMIStatus \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[58]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlNMIClear \ - ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[59]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlClockOutConfig \ - ((void (*)(uint32_t ui32Config, \ - uint32_t ui32Div))ROM_SYSCTLTABLE[60]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlAltClkConfig \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[61]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SysExc API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysExcIntStatus \ - ((uint32_t (*)(bool bMasked))ROM_SYSEXCTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysExcIntClear \ - ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysExcIntDisable \ - ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysExcIntEnable \ - ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[3]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SysTick API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickValueGet \ - ((uint32_t (*)(void))ROM_SYSTICKTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickEnable \ - ((void (*)(void))ROM_SYSTICKTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickDisable \ - ((void (*)(void))ROM_SYSTICKTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickIntEnable \ - ((void (*)(void))ROM_SYSTICKTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickIntDisable \ - ((void (*)(void))ROM_SYSTICKTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickPeriodSet \ - ((void (*)(uint32_t ui32Period))ROM_SYSTICKTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickPeriodGet \ - ((uint32_t (*)(void))ROM_SYSTICKTABLE[6]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Timer API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_TIMERTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_TIMERTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerControlLevel \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - bool bInvert))ROM_TIMERTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA1) -#define ROM_TimerControlTrigger \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - bool bEnable))ROM_TIMERTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerControlEvent \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - uint32_t ui32Event))ROM_TIMERTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerControlStall \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - bool bStall))ROM_TIMERTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerRTCEnable \ - ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerRTCDisable \ - ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerPrescaleSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - uint32_t ui32Value))ROM_TIMERTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerPrescaleGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerPrescaleMatchSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - uint32_t ui32Value))ROM_TIMERTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerPrescaleMatchGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerLoadSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - uint32_t ui32Value))ROM_TIMERTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerLoadGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerValueGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerMatchSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - uint32_t ui32Value))ROM_TIMERTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerMatchGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_TIMERTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_TIMERTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_TIMERTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerControlWaitOnTrigger \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - bool bWait))ROM_TIMERTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_TimerLoadSet64 \ - ((void (*)(uint32_t ui32Base, \ - uint64_t ui64Value))ROM_TIMERTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_TimerLoadGet64 \ - ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_TimerValueGet64 \ - ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_TimerMatchSet64 \ - ((void (*)(uint32_t ui32Base, \ - uint64_t ui64Value))ROM_TIMERTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_TimerMatchGet64 \ - ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerClockSourceGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerClockSourceSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Source))ROM_TIMERTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerADCEventGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerADCEventSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ADCEvent))ROM_TIMERTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerDMAEventGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerDMAEventSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAEvent))ROM_TIMERTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerSynchronize \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timers))ROM_TIMERTABLE[34]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the UART API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTCharPut \ - ((void (*)(uint32_t ui32Base, \ - unsigned char ucData))ROM_UARTTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTParityModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Parity))ROM_UARTTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTParityModeGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFIFOLevelSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32TxLevel, \ - uint32_t ui32RxLevel))ROM_UARTTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFIFOLevelGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32TxLevel, \ - uint32_t *pui32RxLevel))ROM_UARTTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32UARTClk, \ - uint32_t ui32Baud, \ - uint32_t ui32Config))ROM_UARTTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTConfigGetExpClk \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32UARTClk, \ - uint32_t *pui32Baud, \ - uint32_t *pui32Config))ROM_UARTTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTEnable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTDisable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTEnableSIR \ - ((void (*)(uint32_t ui32Base, \ - bool bLowPower))ROM_UARTTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTDisableSIR \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTCharsAvail \ - ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTSpaceAvail \ - ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTCharGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTCharGet \ - ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTCharPutNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - unsigned char ucData))ROM_UARTTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTBreakCtl \ - ((void (*)(uint32_t ui32Base, \ - bool bBreakState))ROM_UARTTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_UARTTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_UARTTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_UARTTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_UARTTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UpdateUART \ - ((void (*)(void))ROM_UARTTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_UARTTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_UARTTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFIFOEnable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFIFODisable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTBusy \ - ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTTxIntModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_UARTTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTTxIntModeGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTRxErrorGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTRxErrorClear \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTClockSourceSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Source))ROM_UARTTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTClockSourceGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UART9BitEnable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UART9BitDisable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UART9BitAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Addr, \ - uint8_t ui8Mask))ROM_UARTTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UART9BitAddrSend \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Addr))ROM_UARTTABLE[36]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTSmartCardDisable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTSmartCardEnable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[38]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTModemControlClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Control))ROM_UARTTABLE[39]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTModemControlGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[40]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTModemControlSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Control))ROM_UARTTABLE[41]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTModemStatusGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[42]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFlowControlGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[43]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFlowControlSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_UARTTABLE[44]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the uDMA API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelTransferSet \ - ((void (*)(uint32_t ui32ChannelStructIndex, \ - uint32_t ui32Mode, \ - void *pvSrcAddr, \ - void *pvDstAddr, \ - uint32_t ui32TransferSize))ROM_UDMATABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAEnable \ - ((void (*)(void))ROM_UDMATABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMADisable \ - ((void (*)(void))ROM_UDMATABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAErrorStatusGet \ - ((uint32_t (*)(void))ROM_UDMATABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAErrorStatusClear \ - ((void (*)(void))ROM_UDMATABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelEnable \ - ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelDisable \ - ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelIsEnabled \ - ((bool (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAControlBaseSet \ - ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAControlBaseGet \ - ((void * (*)(void))ROM_UDMATABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelRequest \ - ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelAttributeEnable \ - ((void (*)(uint32_t ui32ChannelNum, \ - uint32_t ui32Attr))ROM_UDMATABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelAttributeDisable \ - ((void (*)(uint32_t ui32ChannelNum, \ - uint32_t ui32Attr))ROM_UDMATABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelAttributeGet \ - ((uint32_t (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelControlSet \ - ((void (*)(uint32_t ui32ChannelStructIndex, \ - uint32_t ui32Control))ROM_UDMATABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelSizeGet \ - ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelModeGet \ - ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelSelectSecondary \ - ((void (*)(uint32_t ui32SecPeriphs))ROM_UDMATABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelSelectDefault \ - ((void (*)(uint32_t ui32DefPeriphs))ROM_UDMATABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAIntStatus \ - ((uint32_t (*)(void))ROM_UDMATABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAIntClear \ - ((void (*)(uint32_t ui32ChanMask))ROM_UDMATABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAControlAlternateBaseGet \ - ((void * (*)(void))ROM_UDMATABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelScatterGatherSet \ - ((void (*)(uint32_t ui32ChannelNum, \ - uint32_t ui32TaskCount, \ - void *pvTaskList, \ - uint32_t ui32IsPeriphSG))ROM_UDMATABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelAssign \ - ((void (*)(uint32_t ui32Mapping))ROM_UDMATABLE[23]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the USB API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevAddrGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Address))ROM_USBTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevConnect \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevDisconnect \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32MaxPacketSize, \ - uint32_t ui32Flags))ROM_USBTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointDataAck \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - bool bIsLastPacket))ROM_USBTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointStall \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointStallClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointStatusClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDataGet \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint8_t *pui8Data, \ - uint32_t *pui32Size))ROM_USBTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDataPut \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint8_t *pui8Data, \ - uint32_t ui32Size))ROM_USBTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDataSend \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32TransType))ROM_USBTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDataToggleClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBFIFOAddrGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBFIFOConfigGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t *pui32FIFOAddress, \ - uint32_t *pui32FIFOSize, \ - uint32_t ui32Flags))ROM_USBTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBFIFOConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32FIFOAddress, \ - uint32_t ui32FIFOSize, \ - uint32_t ui32Flags))ROM_USBTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBFIFOFlush \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBFrameNumberGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostAddrGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Addr, \ - uint32_t ui32Flags))ROM_USBTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32MaxPacketSize, \ - uint32_t ui32NAKPollInterval, \ - uint32_t ui32TargetEndpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointDataAck \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointDataToggle \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - bool bDataToggle, \ - uint32_t ui32Flags))ROM_USBTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointStatusClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostHubAddrGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostHubAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Addr, \ - uint32_t ui32Flags))ROM_USBTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostPwrDisable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostPwrEnable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostPwrConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_USBTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostPwrFaultDisable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostPwrFaultEnable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostRequestIN \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostRequestStatus \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostReset \ - ((void (*)(uint32_t ui32Base, \ - bool bStart))ROM_USBTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostResume \ - ((void (*)(uint32_t ui32Base, \ - bool bStart))ROM_USBTABLE[36]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostSpeedGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostSuspend \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[38]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointConfigGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t *pui32MaxPacketSize, \ - uint32_t *pui32Flags))ROM_USBTABLE[41]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[42]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[43]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDataAvail \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBModeGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[46]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDMAChannel \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Channel))ROM_USBTABLE[47]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntDisableControl \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_USBTABLE[48]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntEnableControl \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_USBTABLE[49]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntStatusControl \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[50]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntDisableEndpoint \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_USBTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntEnableEndpoint \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_USBTABLE[52]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntStatusEndpoint \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[53]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostMode \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[54]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevMode \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[55]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBPHYPowerOff \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[56]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBPHYPowerOn \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[57]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UpdateUSB \ - ((void (*)(uint8_t *pui8DescriptorInfo))ROM_USBTABLE[58]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBOTGMode \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[59]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostRequestINClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[60]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBNumEndpointsGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[61]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBClockDisable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[62]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBClockEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Div, \ - uint32_t ui32Flags))ROM_USBTABLE[63]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBControllerVersion \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[64]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevLPMConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_USBTABLE[65]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevLPMDisable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[66]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevLPMEnable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[67]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevLPMRemoteWake \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[68]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevSpeedGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[69]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelAddressGet \ - ((void * (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[70]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelAddressSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel, \ - void *pvAddress))ROM_USBTABLE[71]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Config))ROM_USBTABLE[72]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[73]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[74]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[75]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[76]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelCountGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[77]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelCountSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Count, \ - uint32_t ui32Channel))ROM_USBTABLE[78]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelIntStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[79]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[80]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelStatusClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel, \ - uint32_t ui32Status))ROM_USBTABLE[81]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHighSpeed \ - ((void (*)(uint32_t ui32Base, \ - bool bEnable))ROM_USBTABLE[82]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointPing \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - bool bEnable))ROM_USBTABLE[83]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointSpeed \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[84]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostLPMConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ResumeTime, \ - uint32_t ui32Config))ROM_USBTABLE[85]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostLPMResume \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[86]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostLPMSend \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Address, \ - uint32_t uiEndpoint))ROM_USBTABLE[87]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBLPMIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Ints))ROM_USBTABLE[88]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBLPMIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Ints))ROM_USBTABLE[89]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBLPMIntStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[90]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBLPMLinkStateGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[91]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointPacketCountSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Count))ROM_USBTABLE[92]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBULPIConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_USBTABLE[93]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBULPIDisable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[94]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBULPIEnable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[95]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBULPIRegRead \ - ((uint8_t (*)(uint32_t ui32Base, \ - uint8_t ui8Reg))ROM_USBTABLE[96]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBULPIRegWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Reg, \ - uint8_t ui8Data))ROM_USBTABLE[97]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBOTGSessionRequest \ - ((void (*)(uint32_t ui32Base, \ - bool bStart))ROM_USBTABLE[98]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMANumChannels \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[99]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDMAConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Config))ROM_USBTABLE[100]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBLPMRemoteWakeEnabled \ - ((bool (*)(uint32_t ui32Base))ROM_USBTABLE[102]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBModeConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_USBTABLE[103]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Watchdog API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogIntClear \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogRunning \ - ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogEnable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogResetEnable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogResetDisable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogLock \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogUnlock \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogLockState \ - ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogReloadSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32LoadVal))ROM_WATCHDOGTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogReloadGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogValueGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_WATCHDOGTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogStallEnable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogStallDisable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogIntTypeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Type))ROM_WATCHDOGTABLE[15]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Software API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_Crc16Array \ - ((uint16_t (*)(uint32_t ui32WordLen, \ - const uint32_t *pui32Data))ROM_SOFTWARETABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_Crc16Array3 \ - ((void (*)(uint32_t ui32WordLen, \ - const uint32_t *pui32Data, \ - uint16_t *pui16Crc3))ROM_SOFTWARETABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_Crc16 \ - ((uint16_t (*)(uint16_t ui16Crc, \ - const uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SOFTWARETABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_Crc8CCITT \ - ((uint8_t (*)(uint8_t ui8Crc, \ - const uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SOFTWARETABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_Crc32 \ - ((uint32_t (*)(uint32_t ui32Crc, \ - const uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SOFTWARETABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_pvAESTable \ - ((void *)&(ROM_SOFTWARETABLE[7])) -#endif - -#endif // __DRIVERLIB_ROM_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/rom_map.h b/bsp/tm4c129x-dk/libraries/driverlib/rom_map.h deleted file mode 100644 index e45ede445fb4ba4d04d63f5ca40886dd24d39c6f..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/rom_map.h +++ /dev/null @@ -1,6409 +0,0 @@ -//***************************************************************************** -// -// rom_map.h - Macros to facilitate calling functions in the ROM when they are -// available and in flash otherwise. -// -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_ROM_MAP_H__ -#define __DRIVERLIB_ROM_MAP_H__ - -//***************************************************************************** -// -// Macros for the ADC API. -// -//***************************************************************************** -#ifdef ROM_ADCSequenceDataGet -#define MAP_ADCSequenceDataGet \ - ROM_ADCSequenceDataGet -#else -#define MAP_ADCSequenceDataGet \ - ADCSequenceDataGet -#endif -#ifdef ROM_ADCIntDisable -#define MAP_ADCIntDisable \ - ROM_ADCIntDisable -#else -#define MAP_ADCIntDisable \ - ADCIntDisable -#endif -#ifdef ROM_ADCIntEnable -#define MAP_ADCIntEnable \ - ROM_ADCIntEnable -#else -#define MAP_ADCIntEnable \ - ADCIntEnable -#endif -#ifdef ROM_ADCIntStatus -#define MAP_ADCIntStatus \ - ROM_ADCIntStatus -#else -#define MAP_ADCIntStatus \ - ADCIntStatus -#endif -#ifdef ROM_ADCIntClear -#define MAP_ADCIntClear \ - ROM_ADCIntClear -#else -#define MAP_ADCIntClear \ - ADCIntClear -#endif -#ifdef ROM_ADCSequenceEnable -#define MAP_ADCSequenceEnable \ - ROM_ADCSequenceEnable -#else -#define MAP_ADCSequenceEnable \ - ADCSequenceEnable -#endif -#ifdef ROM_ADCSequenceDisable -#define MAP_ADCSequenceDisable \ - ROM_ADCSequenceDisable -#else -#define MAP_ADCSequenceDisable \ - ADCSequenceDisable -#endif -#ifdef ROM_ADCSequenceConfigure -#define MAP_ADCSequenceConfigure \ - ROM_ADCSequenceConfigure -#else -#define MAP_ADCSequenceConfigure \ - ADCSequenceConfigure -#endif -#ifdef ROM_ADCSequenceStepConfigure -#define MAP_ADCSequenceStepConfigure \ - ROM_ADCSequenceStepConfigure -#else -#define MAP_ADCSequenceStepConfigure \ - ADCSequenceStepConfigure -#endif -#ifdef ROM_ADCSequenceOverflow -#define MAP_ADCSequenceOverflow \ - ROM_ADCSequenceOverflow -#else -#define MAP_ADCSequenceOverflow \ - ADCSequenceOverflow -#endif -#ifdef ROM_ADCSequenceOverflowClear -#define MAP_ADCSequenceOverflowClear \ - ROM_ADCSequenceOverflowClear -#else -#define MAP_ADCSequenceOverflowClear \ - ADCSequenceOverflowClear -#endif -#ifdef ROM_ADCSequenceUnderflow -#define MAP_ADCSequenceUnderflow \ - ROM_ADCSequenceUnderflow -#else -#define MAP_ADCSequenceUnderflow \ - ADCSequenceUnderflow -#endif -#ifdef ROM_ADCSequenceUnderflowClear -#define MAP_ADCSequenceUnderflowClear \ - ROM_ADCSequenceUnderflowClear -#else -#define MAP_ADCSequenceUnderflowClear \ - ADCSequenceUnderflowClear -#endif -#ifdef ROM_ADCProcessorTrigger -#define MAP_ADCProcessorTrigger \ - ROM_ADCProcessorTrigger -#else -#define MAP_ADCProcessorTrigger \ - ADCProcessorTrigger -#endif -#ifdef ROM_ADCHardwareOversampleConfigure -#define MAP_ADCHardwareOversampleConfigure \ - ROM_ADCHardwareOversampleConfigure -#else -#define MAP_ADCHardwareOversampleConfigure \ - ADCHardwareOversampleConfigure -#endif -#ifdef ROM_ADCComparatorConfigure -#define MAP_ADCComparatorConfigure \ - ROM_ADCComparatorConfigure -#else -#define MAP_ADCComparatorConfigure \ - ADCComparatorConfigure -#endif -#ifdef ROM_ADCComparatorRegionSet -#define MAP_ADCComparatorRegionSet \ - ROM_ADCComparatorRegionSet -#else -#define MAP_ADCComparatorRegionSet \ - ADCComparatorRegionSet -#endif -#ifdef ROM_ADCComparatorReset -#define MAP_ADCComparatorReset \ - ROM_ADCComparatorReset -#else -#define MAP_ADCComparatorReset \ - ADCComparatorReset -#endif -#ifdef ROM_ADCComparatorIntDisable -#define MAP_ADCComparatorIntDisable \ - ROM_ADCComparatorIntDisable -#else -#define MAP_ADCComparatorIntDisable \ - ADCComparatorIntDisable -#endif -#ifdef ROM_ADCComparatorIntEnable -#define MAP_ADCComparatorIntEnable \ - ROM_ADCComparatorIntEnable -#else -#define MAP_ADCComparatorIntEnable \ - ADCComparatorIntEnable -#endif -#ifdef ROM_ADCComparatorIntStatus -#define MAP_ADCComparatorIntStatus \ - ROM_ADCComparatorIntStatus -#else -#define MAP_ADCComparatorIntStatus \ - ADCComparatorIntStatus -#endif -#ifdef ROM_ADCComparatorIntClear -#define MAP_ADCComparatorIntClear \ - ROM_ADCComparatorIntClear -#else -#define MAP_ADCComparatorIntClear \ - ADCComparatorIntClear -#endif -#ifdef ROM_ADCReferenceSet -#define MAP_ADCReferenceSet \ - ROM_ADCReferenceSet -#else -#define MAP_ADCReferenceSet \ - ADCReferenceSet -#endif -#ifdef ROM_ADCReferenceGet -#define MAP_ADCReferenceGet \ - ROM_ADCReferenceGet -#else -#define MAP_ADCReferenceGet \ - ADCReferenceGet -#endif -#ifdef ROM_ADCPhaseDelaySet -#define MAP_ADCPhaseDelaySet \ - ROM_ADCPhaseDelaySet -#else -#define MAP_ADCPhaseDelaySet \ - ADCPhaseDelaySet -#endif -#ifdef ROM_ADCPhaseDelayGet -#define MAP_ADCPhaseDelayGet \ - ROM_ADCPhaseDelayGet -#else -#define MAP_ADCPhaseDelayGet \ - ADCPhaseDelayGet -#endif -#ifdef ROM_ADCIntClearEx -#define MAP_ADCIntClearEx \ - ROM_ADCIntClearEx -#else -#define MAP_ADCIntClearEx \ - ADCIntClearEx -#endif -#ifdef ROM_ADCIntDisableEx -#define MAP_ADCIntDisableEx \ - ROM_ADCIntDisableEx -#else -#define MAP_ADCIntDisableEx \ - ADCIntDisableEx -#endif -#ifdef ROM_ADCIntEnableEx -#define MAP_ADCIntEnableEx \ - ROM_ADCIntEnableEx -#else -#define MAP_ADCIntEnableEx \ - ADCIntEnableEx -#endif -#ifdef ROM_ADCIntStatusEx -#define MAP_ADCIntStatusEx \ - ROM_ADCIntStatusEx -#else -#define MAP_ADCIntStatusEx \ - ADCIntStatusEx -#endif -#ifdef ROM_ADCSequenceDMAEnable -#define MAP_ADCSequenceDMAEnable \ - ROM_ADCSequenceDMAEnable -#else -#define MAP_ADCSequenceDMAEnable \ - ADCSequenceDMAEnable -#endif -#ifdef ROM_ADCSequenceDMADisable -#define MAP_ADCSequenceDMADisable \ - ROM_ADCSequenceDMADisable -#else -#define MAP_ADCSequenceDMADisable \ - ADCSequenceDMADisable -#endif -#ifdef ROM_ADCBusy -#define MAP_ADCBusy \ - ROM_ADCBusy -#else -#define MAP_ADCBusy \ - ADCBusy -#endif - -//***************************************************************************** -// -// Macros for the AES API. -// -//***************************************************************************** -#ifdef ROM_AESIntStatus -#define MAP_AESIntStatus \ - ROM_AESIntStatus -#else -#define MAP_AESIntStatus \ - AESIntStatus -#endif -#ifdef ROM_AESAuthLengthSet -#define MAP_AESAuthLengthSet \ - ROM_AESAuthLengthSet -#else -#define MAP_AESAuthLengthSet \ - AESAuthLengthSet -#endif -#ifdef ROM_AESConfigSet -#define MAP_AESConfigSet \ - ROM_AESConfigSet -#else -#define MAP_AESConfigSet \ - AESConfigSet -#endif -#ifdef ROM_AESDataAuth -#define MAP_AESDataAuth \ - ROM_AESDataAuth -#else -#define MAP_AESDataAuth \ - AESDataAuth -#endif -#ifdef ROM_AESDataProcess -#define MAP_AESDataProcess \ - ROM_AESDataProcess -#else -#define MAP_AESDataProcess \ - AESDataProcess -#endif -#ifdef ROM_AESDataProcessAuth -#define MAP_AESDataProcessAuth \ - ROM_AESDataProcessAuth -#else -#define MAP_AESDataProcessAuth \ - AESDataProcessAuth -#endif -#ifdef ROM_AESDataRead -#define MAP_AESDataRead \ - ROM_AESDataRead -#else -#define MAP_AESDataRead \ - AESDataRead -#endif -#ifdef ROM_AESDataReadNonBlocking -#define MAP_AESDataReadNonBlocking \ - ROM_AESDataReadNonBlocking -#else -#define MAP_AESDataReadNonBlocking \ - AESDataReadNonBlocking -#endif -#ifdef ROM_AESDataWrite -#define MAP_AESDataWrite \ - ROM_AESDataWrite -#else -#define MAP_AESDataWrite \ - AESDataWrite -#endif -#ifdef ROM_AESDataWriteNonBlocking -#define MAP_AESDataWriteNonBlocking \ - ROM_AESDataWriteNonBlocking -#else -#define MAP_AESDataWriteNonBlocking \ - AESDataWriteNonBlocking -#endif -#ifdef ROM_AESDMADisable -#define MAP_AESDMADisable \ - ROM_AESDMADisable -#else -#define MAP_AESDMADisable \ - AESDMADisable -#endif -#ifdef ROM_AESDMAEnable -#define MAP_AESDMAEnable \ - ROM_AESDMAEnable -#else -#define MAP_AESDMAEnable \ - AESDMAEnable -#endif -#ifdef ROM_AESIntClear -#define MAP_AESIntClear \ - ROM_AESIntClear -#else -#define MAP_AESIntClear \ - AESIntClear -#endif -#ifdef ROM_AESIntDisable -#define MAP_AESIntDisable \ - ROM_AESIntDisable -#else -#define MAP_AESIntDisable \ - AESIntDisable -#endif -#ifdef ROM_AESIntEnable -#define MAP_AESIntEnable \ - ROM_AESIntEnable -#else -#define MAP_AESIntEnable \ - AESIntEnable -#endif -#ifdef ROM_AESIVSet -#define MAP_AESIVSet \ - ROM_AESIVSet -#else -#define MAP_AESIVSet \ - AESIVSet -#endif -#ifdef ROM_AESKey1Set -#define MAP_AESKey1Set \ - ROM_AESKey1Set -#else -#define MAP_AESKey1Set \ - AESKey1Set -#endif -#ifdef ROM_AESKey2Set -#define MAP_AESKey2Set \ - ROM_AESKey2Set -#else -#define MAP_AESKey2Set \ - AESKey2Set -#endif -#ifdef ROM_AESKey3Set -#define MAP_AESKey3Set \ - ROM_AESKey3Set -#else -#define MAP_AESKey3Set \ - AESKey3Set -#endif -#ifdef ROM_AESLengthSet -#define MAP_AESLengthSet \ - ROM_AESLengthSet -#else -#define MAP_AESLengthSet \ - AESLengthSet -#endif -#ifdef ROM_AESReset -#define MAP_AESReset \ - ROM_AESReset -#else -#define MAP_AESReset \ - AESReset -#endif -#ifdef ROM_AESTagRead -#define MAP_AESTagRead \ - ROM_AESTagRead -#else -#define MAP_AESTagRead \ - AESTagRead -#endif -#ifdef ROM_AESIVRead -#define MAP_AESIVRead \ - ROM_AESIVRead -#else -#define MAP_AESIVRead \ - AESIVRead -#endif - -//***************************************************************************** -// -// Macros for the CAN API. -// -//***************************************************************************** -#ifdef ROM_CANIntClear -#define MAP_CANIntClear \ - ROM_CANIntClear -#else -#define MAP_CANIntClear \ - CANIntClear -#endif -#ifdef ROM_CANInit -#define MAP_CANInit \ - ROM_CANInit -#else -#define MAP_CANInit \ - CANInit -#endif -#ifdef ROM_CANEnable -#define MAP_CANEnable \ - ROM_CANEnable -#else -#define MAP_CANEnable \ - CANEnable -#endif -#ifdef ROM_CANDisable -#define MAP_CANDisable \ - ROM_CANDisable -#else -#define MAP_CANDisable \ - CANDisable -#endif -#ifdef ROM_CANBitTimingSet -#define MAP_CANBitTimingSet \ - ROM_CANBitTimingSet -#else -#define MAP_CANBitTimingSet \ - CANBitTimingSet -#endif -#ifdef ROM_CANBitTimingGet -#define MAP_CANBitTimingGet \ - ROM_CANBitTimingGet -#else -#define MAP_CANBitTimingGet \ - CANBitTimingGet -#endif -#ifdef ROM_CANMessageSet -#define MAP_CANMessageSet \ - ROM_CANMessageSet -#else -#define MAP_CANMessageSet \ - CANMessageSet -#endif -#ifdef ROM_CANMessageGet -#define MAP_CANMessageGet \ - ROM_CANMessageGet -#else -#define MAP_CANMessageGet \ - CANMessageGet -#endif -#ifdef ROM_CANStatusGet -#define MAP_CANStatusGet \ - ROM_CANStatusGet -#else -#define MAP_CANStatusGet \ - CANStatusGet -#endif -#ifdef ROM_CANMessageClear -#define MAP_CANMessageClear \ - ROM_CANMessageClear -#else -#define MAP_CANMessageClear \ - CANMessageClear -#endif -#ifdef ROM_CANIntEnable -#define MAP_CANIntEnable \ - ROM_CANIntEnable -#else -#define MAP_CANIntEnable \ - CANIntEnable -#endif -#ifdef ROM_CANIntDisable -#define MAP_CANIntDisable \ - ROM_CANIntDisable -#else -#define MAP_CANIntDisable \ - CANIntDisable -#endif -#ifdef ROM_CANIntStatus -#define MAP_CANIntStatus \ - ROM_CANIntStatus -#else -#define MAP_CANIntStatus \ - CANIntStatus -#endif -#ifdef ROM_CANRetryGet -#define MAP_CANRetryGet \ - ROM_CANRetryGet -#else -#define MAP_CANRetryGet \ - CANRetryGet -#endif -#ifdef ROM_CANRetrySet -#define MAP_CANRetrySet \ - ROM_CANRetrySet -#else -#define MAP_CANRetrySet \ - CANRetrySet -#endif -#ifdef ROM_CANErrCntrGet -#define MAP_CANErrCntrGet \ - ROM_CANErrCntrGet -#else -#define MAP_CANErrCntrGet \ - CANErrCntrGet -#endif -#ifdef ROM_CANBitRateSet -#define MAP_CANBitRateSet \ - ROM_CANBitRateSet -#else -#define MAP_CANBitRateSet \ - CANBitRateSet -#endif - -//***************************************************************************** -// -// Macros for the Comparator API. -// -//***************************************************************************** -#ifdef ROM_ComparatorIntClear -#define MAP_ComparatorIntClear \ - ROM_ComparatorIntClear -#else -#define MAP_ComparatorIntClear \ - ComparatorIntClear -#endif -#ifdef ROM_ComparatorConfigure -#define MAP_ComparatorConfigure \ - ROM_ComparatorConfigure -#else -#define MAP_ComparatorConfigure \ - ComparatorConfigure -#endif -#ifdef ROM_ComparatorRefSet -#define MAP_ComparatorRefSet \ - ROM_ComparatorRefSet -#else -#define MAP_ComparatorRefSet \ - ComparatorRefSet -#endif -#ifdef ROM_ComparatorValueGet -#define MAP_ComparatorValueGet \ - ROM_ComparatorValueGet -#else -#define MAP_ComparatorValueGet \ - ComparatorValueGet -#endif -#ifdef ROM_ComparatorIntEnable -#define MAP_ComparatorIntEnable \ - ROM_ComparatorIntEnable -#else -#define MAP_ComparatorIntEnable \ - ComparatorIntEnable -#endif -#ifdef ROM_ComparatorIntDisable -#define MAP_ComparatorIntDisable \ - ROM_ComparatorIntDisable -#else -#define MAP_ComparatorIntDisable \ - ComparatorIntDisable -#endif -#ifdef ROM_ComparatorIntStatus -#define MAP_ComparatorIntStatus \ - ROM_ComparatorIntStatus -#else -#define MAP_ComparatorIntStatus \ - ComparatorIntStatus -#endif - -//***************************************************************************** -// -// Macros for the CRC API. -// -//***************************************************************************** -#ifdef ROM_CRCConfigSet -#define MAP_CRCConfigSet \ - ROM_CRCConfigSet -#else -#define MAP_CRCConfigSet \ - CRCConfigSet -#endif -#ifdef ROM_CRCDataProcess -#define MAP_CRCDataProcess \ - ROM_CRCDataProcess -#else -#define MAP_CRCDataProcess \ - CRCDataProcess -#endif -#ifdef ROM_CRCDataWrite -#define MAP_CRCDataWrite \ - ROM_CRCDataWrite -#else -#define MAP_CRCDataWrite \ - CRCDataWrite -#endif -#ifdef ROM_CRCResultRead -#define MAP_CRCResultRead \ - ROM_CRCResultRead -#else -#define MAP_CRCResultRead \ - CRCResultRead -#endif -#ifdef ROM_CRCSeedSet -#define MAP_CRCSeedSet \ - ROM_CRCSeedSet -#else -#define MAP_CRCSeedSet \ - CRCSeedSet -#endif - -//***************************************************************************** -// -// Macros for the DES API. -// -//***************************************************************************** -#ifdef ROM_DESIntStatus -#define MAP_DESIntStatus \ - ROM_DESIntStatus -#else -#define MAP_DESIntStatus \ - DESIntStatus -#endif -#ifdef ROM_DESConfigSet -#define MAP_DESConfigSet \ - ROM_DESConfigSet -#else -#define MAP_DESConfigSet \ - DESConfigSet -#endif -#ifdef ROM_DESDataRead -#define MAP_DESDataRead \ - ROM_DESDataRead -#else -#define MAP_DESDataRead \ - DESDataRead -#endif -#ifdef ROM_DESDataReadNonBlocking -#define MAP_DESDataReadNonBlocking \ - ROM_DESDataReadNonBlocking -#else -#define MAP_DESDataReadNonBlocking \ - DESDataReadNonBlocking -#endif -#ifdef ROM_DESDataProcess -#define MAP_DESDataProcess \ - ROM_DESDataProcess -#else -#define MAP_DESDataProcess \ - DESDataProcess -#endif -#ifdef ROM_DESDataWrite -#define MAP_DESDataWrite \ - ROM_DESDataWrite -#else -#define MAP_DESDataWrite \ - DESDataWrite -#endif -#ifdef ROM_DESDataWriteNonBlocking -#define MAP_DESDataWriteNonBlocking \ - ROM_DESDataWriteNonBlocking -#else -#define MAP_DESDataWriteNonBlocking \ - DESDataWriteNonBlocking -#endif -#ifdef ROM_DESDMADisable -#define MAP_DESDMADisable \ - ROM_DESDMADisable -#else -#define MAP_DESDMADisable \ - DESDMADisable -#endif -#ifdef ROM_DESDMAEnable -#define MAP_DESDMAEnable \ - ROM_DESDMAEnable -#else -#define MAP_DESDMAEnable \ - DESDMAEnable -#endif -#ifdef ROM_DESIntClear -#define MAP_DESIntClear \ - ROM_DESIntClear -#else -#define MAP_DESIntClear \ - DESIntClear -#endif -#ifdef ROM_DESIntDisable -#define MAP_DESIntDisable \ - ROM_DESIntDisable -#else -#define MAP_DESIntDisable \ - DESIntDisable -#endif -#ifdef ROM_DESIntEnable -#define MAP_DESIntEnable \ - ROM_DESIntEnable -#else -#define MAP_DESIntEnable \ - DESIntEnable -#endif -#ifdef ROM_DESIVSet -#define MAP_DESIVSet \ - ROM_DESIVSet -#else -#define MAP_DESIVSet \ - DESIVSet -#endif -#ifdef ROM_DESKeySet -#define MAP_DESKeySet \ - ROM_DESKeySet -#else -#define MAP_DESKeySet \ - DESKeySet -#endif -#ifdef ROM_DESLengthSet -#define MAP_DESLengthSet \ - ROM_DESLengthSet -#else -#define MAP_DESLengthSet \ - DESLengthSet -#endif -#ifdef ROM_DESReset -#define MAP_DESReset \ - ROM_DESReset -#else -#define MAP_DESReset \ - DESReset -#endif - -//***************************************************************************** -// -// Macros for the EEPROM API. -// -//***************************************************************************** -#ifdef ROM_EEPROMRead -#define MAP_EEPROMRead \ - ROM_EEPROMRead -#else -#define MAP_EEPROMRead \ - EEPROMRead -#endif -#ifdef ROM_EEPROMBlockCountGet -#define MAP_EEPROMBlockCountGet \ - ROM_EEPROMBlockCountGet -#else -#define MAP_EEPROMBlockCountGet \ - EEPROMBlockCountGet -#endif -#ifdef ROM_EEPROMBlockHide -#define MAP_EEPROMBlockHide \ - ROM_EEPROMBlockHide -#else -#define MAP_EEPROMBlockHide \ - EEPROMBlockHide -#endif -#ifdef ROM_EEPROMBlockLock -#define MAP_EEPROMBlockLock \ - ROM_EEPROMBlockLock -#else -#define MAP_EEPROMBlockLock \ - EEPROMBlockLock -#endif -#ifdef ROM_EEPROMBlockPasswordSet -#define MAP_EEPROMBlockPasswordSet \ - ROM_EEPROMBlockPasswordSet -#else -#define MAP_EEPROMBlockPasswordSet \ - EEPROMBlockPasswordSet -#endif -#ifdef ROM_EEPROMBlockProtectGet -#define MAP_EEPROMBlockProtectGet \ - ROM_EEPROMBlockProtectGet -#else -#define MAP_EEPROMBlockProtectGet \ - EEPROMBlockProtectGet -#endif -#ifdef ROM_EEPROMBlockProtectSet -#define MAP_EEPROMBlockProtectSet \ - ROM_EEPROMBlockProtectSet -#else -#define MAP_EEPROMBlockProtectSet \ - EEPROMBlockProtectSet -#endif -#ifdef ROM_EEPROMBlockUnlock -#define MAP_EEPROMBlockUnlock \ - ROM_EEPROMBlockUnlock -#else -#define MAP_EEPROMBlockUnlock \ - EEPROMBlockUnlock -#endif -#ifdef ROM_EEPROMIntClear -#define MAP_EEPROMIntClear \ - ROM_EEPROMIntClear -#else -#define MAP_EEPROMIntClear \ - EEPROMIntClear -#endif -#ifdef ROM_EEPROMIntDisable -#define MAP_EEPROMIntDisable \ - ROM_EEPROMIntDisable -#else -#define MAP_EEPROMIntDisable \ - EEPROMIntDisable -#endif -#ifdef ROM_EEPROMIntEnable -#define MAP_EEPROMIntEnable \ - ROM_EEPROMIntEnable -#else -#define MAP_EEPROMIntEnable \ - EEPROMIntEnable -#endif -#ifdef ROM_EEPROMIntStatus -#define MAP_EEPROMIntStatus \ - ROM_EEPROMIntStatus -#else -#define MAP_EEPROMIntStatus \ - EEPROMIntStatus -#endif -#ifdef ROM_EEPROMMassErase -#define MAP_EEPROMMassErase \ - ROM_EEPROMMassErase -#else -#define MAP_EEPROMMassErase \ - EEPROMMassErase -#endif -#ifdef ROM_EEPROMProgram -#define MAP_EEPROMProgram \ - ROM_EEPROMProgram -#else -#define MAP_EEPROMProgram \ - EEPROMProgram -#endif -#ifdef ROM_EEPROMProgramNonBlocking -#define MAP_EEPROMProgramNonBlocking \ - ROM_EEPROMProgramNonBlocking -#else -#define MAP_EEPROMProgramNonBlocking \ - EEPROMProgramNonBlocking -#endif -#ifdef ROM_EEPROMSizeGet -#define MAP_EEPROMSizeGet \ - ROM_EEPROMSizeGet -#else -#define MAP_EEPROMSizeGet \ - EEPROMSizeGet -#endif -#ifdef ROM_EEPROMStatusGet -#define MAP_EEPROMStatusGet \ - ROM_EEPROMStatusGet -#else -#define MAP_EEPROMStatusGet \ - EEPROMStatusGet -#endif -#ifdef ROM_EEPROMInit -#define MAP_EEPROMInit \ - ROM_EEPROMInit -#else -#define MAP_EEPROMInit \ - EEPROMInit -#endif - -//***************************************************************************** -// -// Macros for the EPI API. -// -//***************************************************************************** -#ifdef ROM_EPIIntStatus -#define MAP_EPIIntStatus \ - ROM_EPIIntStatus -#else -#define MAP_EPIIntStatus \ - EPIIntStatus -#endif -#ifdef ROM_EPIModeSet -#define MAP_EPIModeSet \ - ROM_EPIModeSet -#else -#define MAP_EPIModeSet \ - EPIModeSet -#endif -#ifdef ROM_EPIDividerSet -#define MAP_EPIDividerSet \ - ROM_EPIDividerSet -#else -#define MAP_EPIDividerSet \ - EPIDividerSet -#endif -#ifdef ROM_EPIConfigSDRAMSet -#define MAP_EPIConfigSDRAMSet \ - ROM_EPIConfigSDRAMSet -#else -#define MAP_EPIConfigSDRAMSet \ - EPIConfigSDRAMSet -#endif -#ifdef ROM_EPIConfigGPModeSet -#define MAP_EPIConfigGPModeSet \ - ROM_EPIConfigGPModeSet -#else -#define MAP_EPIConfigGPModeSet \ - EPIConfigGPModeSet -#endif -#ifdef ROM_EPIConfigHB8Set -#define MAP_EPIConfigHB8Set \ - ROM_EPIConfigHB8Set -#else -#define MAP_EPIConfigHB8Set \ - EPIConfigHB8Set -#endif -#ifdef ROM_EPIConfigHB16Set -#define MAP_EPIConfigHB16Set \ - ROM_EPIConfigHB16Set -#else -#define MAP_EPIConfigHB16Set \ - EPIConfigHB16Set -#endif -#ifdef ROM_EPIAddressMapSet -#define MAP_EPIAddressMapSet \ - ROM_EPIAddressMapSet -#else -#define MAP_EPIAddressMapSet \ - EPIAddressMapSet -#endif -#ifdef ROM_EPINonBlockingReadConfigure -#define MAP_EPINonBlockingReadConfigure \ - ROM_EPINonBlockingReadConfigure -#else -#define MAP_EPINonBlockingReadConfigure \ - EPINonBlockingReadConfigure -#endif -#ifdef ROM_EPINonBlockingReadStart -#define MAP_EPINonBlockingReadStart \ - ROM_EPINonBlockingReadStart -#else -#define MAP_EPINonBlockingReadStart \ - EPINonBlockingReadStart -#endif -#ifdef ROM_EPINonBlockingReadStop -#define MAP_EPINonBlockingReadStop \ - ROM_EPINonBlockingReadStop -#else -#define MAP_EPINonBlockingReadStop \ - EPINonBlockingReadStop -#endif -#ifdef ROM_EPINonBlockingReadCount -#define MAP_EPINonBlockingReadCount \ - ROM_EPINonBlockingReadCount -#else -#define MAP_EPINonBlockingReadCount \ - EPINonBlockingReadCount -#endif -#ifdef ROM_EPINonBlockingReadAvail -#define MAP_EPINonBlockingReadAvail \ - ROM_EPINonBlockingReadAvail -#else -#define MAP_EPINonBlockingReadAvail \ - EPINonBlockingReadAvail -#endif -#ifdef ROM_EPINonBlockingReadGet32 -#define MAP_EPINonBlockingReadGet32 \ - ROM_EPINonBlockingReadGet32 -#else -#define MAP_EPINonBlockingReadGet32 \ - EPINonBlockingReadGet32 -#endif -#ifdef ROM_EPINonBlockingReadGet16 -#define MAP_EPINonBlockingReadGet16 \ - ROM_EPINonBlockingReadGet16 -#else -#define MAP_EPINonBlockingReadGet16 \ - EPINonBlockingReadGet16 -#endif -#ifdef ROM_EPINonBlockingReadGet8 -#define MAP_EPINonBlockingReadGet8 \ - ROM_EPINonBlockingReadGet8 -#else -#define MAP_EPINonBlockingReadGet8 \ - EPINonBlockingReadGet8 -#endif -#ifdef ROM_EPIFIFOConfig -#define MAP_EPIFIFOConfig \ - ROM_EPIFIFOConfig -#else -#define MAP_EPIFIFOConfig \ - EPIFIFOConfig -#endif -#ifdef ROM_EPIWriteFIFOCountGet -#define MAP_EPIWriteFIFOCountGet \ - ROM_EPIWriteFIFOCountGet -#else -#define MAP_EPIWriteFIFOCountGet \ - EPIWriteFIFOCountGet -#endif -#ifdef ROM_EPIIntEnable -#define MAP_EPIIntEnable \ - ROM_EPIIntEnable -#else -#define MAP_EPIIntEnable \ - EPIIntEnable -#endif -#ifdef ROM_EPIIntDisable -#define MAP_EPIIntDisable \ - ROM_EPIIntDisable -#else -#define MAP_EPIIntDisable \ - EPIIntDisable -#endif -#ifdef ROM_EPIIntErrorStatus -#define MAP_EPIIntErrorStatus \ - ROM_EPIIntErrorStatus -#else -#define MAP_EPIIntErrorStatus \ - EPIIntErrorStatus -#endif -#ifdef ROM_EPIIntErrorClear -#define MAP_EPIIntErrorClear \ - ROM_EPIIntErrorClear -#else -#define MAP_EPIIntErrorClear \ - EPIIntErrorClear -#endif -#ifdef ROM_EPIDividerCSSet -#define MAP_EPIDividerCSSet \ - ROM_EPIDividerCSSet -#else -#define MAP_EPIDividerCSSet \ - EPIDividerCSSet -#endif -#ifdef ROM_EPIDMATxCount -#define MAP_EPIDMATxCount \ - ROM_EPIDMATxCount -#else -#define MAP_EPIDMATxCount \ - EPIDMATxCount -#endif -#ifdef ROM_EPIConfigHB8CSSet -#define MAP_EPIConfigHB8CSSet \ - ROM_EPIConfigHB8CSSet -#else -#define MAP_EPIConfigHB8CSSet \ - EPIConfigHB8CSSet -#endif -#ifdef ROM_EPIConfigHB16CSSet -#define MAP_EPIConfigHB16CSSet \ - ROM_EPIConfigHB16CSSet -#else -#define MAP_EPIConfigHB16CSSet \ - EPIConfigHB16CSSet -#endif -#ifdef ROM_EPIConfigHB8TimingSet -#define MAP_EPIConfigHB8TimingSet \ - ROM_EPIConfigHB8TimingSet -#else -#define MAP_EPIConfigHB8TimingSet \ - EPIConfigHB8TimingSet -#endif -#ifdef ROM_EPIConfigHB16TimingSet -#define MAP_EPIConfigHB16TimingSet \ - ROM_EPIConfigHB16TimingSet -#else -#define MAP_EPIConfigHB16TimingSet \ - EPIConfigHB16TimingSet -#endif -#ifdef ROM_EPIPSRAMConfigRegSet -#define MAP_EPIPSRAMConfigRegSet \ - ROM_EPIPSRAMConfigRegSet -#else -#define MAP_EPIPSRAMConfigRegSet \ - EPIPSRAMConfigRegSet -#endif -#ifdef ROM_EPIPSRAMConfigRegRead -#define MAP_EPIPSRAMConfigRegRead \ - ROM_EPIPSRAMConfigRegRead -#else -#define MAP_EPIPSRAMConfigRegRead \ - EPIPSRAMConfigRegRead -#endif -#ifdef ROM_EPIPSRAMConfigRegGetNonBlocking -#define MAP_EPIPSRAMConfigRegGetNonBlocking \ - ROM_EPIPSRAMConfigRegGetNonBlocking -#else -#define MAP_EPIPSRAMConfigRegGetNonBlocking \ - EPIPSRAMConfigRegGetNonBlocking -#endif -#ifdef ROM_EPIPSRAMConfigRegGet -#define MAP_EPIPSRAMConfigRegGet \ - ROM_EPIPSRAMConfigRegGet -#else -#define MAP_EPIPSRAMConfigRegGet \ - EPIPSRAMConfigRegGet -#endif - -//***************************************************************************** -// -// Macros for the EMAC API. -// -//***************************************************************************** -#ifdef ROM_EMACIntStatus -#define MAP_EMACIntStatus \ - ROM_EMACIntStatus -#else -#define MAP_EMACIntStatus \ - EMACIntStatus -#endif -#ifdef ROM_EMACAddrGet -#define MAP_EMACAddrGet \ - ROM_EMACAddrGet -#else -#define MAP_EMACAddrGet \ - EMACAddrGet -#endif -#ifdef ROM_EMACAddrSet -#define MAP_EMACAddrSet \ - ROM_EMACAddrSet -#else -#define MAP_EMACAddrSet \ - EMACAddrSet -#endif -#ifdef ROM_EMACConfigGet -#define MAP_EMACConfigGet \ - ROM_EMACConfigGet -#else -#define MAP_EMACConfigGet \ - EMACConfigGet -#endif -#ifdef ROM_EMACConfigSet -#define MAP_EMACConfigSet \ - ROM_EMACConfigSet -#else -#define MAP_EMACConfigSet \ - EMACConfigSet -#endif -#ifdef ROM_EMACDMAStateGet -#define MAP_EMACDMAStateGet \ - ROM_EMACDMAStateGet -#else -#define MAP_EMACDMAStateGet \ - EMACDMAStateGet -#endif -#ifdef ROM_EMACFrameFilterGet -#define MAP_EMACFrameFilterGet \ - ROM_EMACFrameFilterGet -#else -#define MAP_EMACFrameFilterGet \ - EMACFrameFilterGet -#endif -#ifdef ROM_EMACFrameFilterSet -#define MAP_EMACFrameFilterSet \ - ROM_EMACFrameFilterSet -#else -#define MAP_EMACFrameFilterSet \ - EMACFrameFilterSet -#endif -#ifdef ROM_EMACInit -#define MAP_EMACInit \ - ROM_EMACInit -#else -#define MAP_EMACInit \ - EMACInit -#endif -#ifdef ROM_EMACIntClear -#define MAP_EMACIntClear \ - ROM_EMACIntClear -#else -#define MAP_EMACIntClear \ - EMACIntClear -#endif -#ifdef ROM_EMACIntDisable -#define MAP_EMACIntDisable \ - ROM_EMACIntDisable -#else -#define MAP_EMACIntDisable \ - EMACIntDisable -#endif -#ifdef ROM_EMACIntEnable -#define MAP_EMACIntEnable \ - ROM_EMACIntEnable -#else -#define MAP_EMACIntEnable \ - EMACIntEnable -#endif -#ifdef ROM_EMACPHYConfigSet -#define MAP_EMACPHYConfigSet \ - ROM_EMACPHYConfigSet -#else -#define MAP_EMACPHYConfigSet \ - EMACPHYConfigSet -#endif -#ifdef ROM_EMACPHYPowerOff -#define MAP_EMACPHYPowerOff \ - ROM_EMACPHYPowerOff -#else -#define MAP_EMACPHYPowerOff \ - EMACPHYPowerOff -#endif -#ifdef ROM_EMACPHYPowerOn -#define MAP_EMACPHYPowerOn \ - ROM_EMACPHYPowerOn -#else -#define MAP_EMACPHYPowerOn \ - EMACPHYPowerOn -#endif -#ifdef ROM_EMACPHYRead -#define MAP_EMACPHYRead \ - ROM_EMACPHYRead -#else -#define MAP_EMACPHYRead \ - EMACPHYRead -#endif -#ifdef ROM_EMACPHYWrite -#define MAP_EMACPHYWrite \ - ROM_EMACPHYWrite -#else -#define MAP_EMACPHYWrite \ - EMACPHYWrite -#endif -#ifdef ROM_EMACReset -#define MAP_EMACReset \ - ROM_EMACReset -#else -#define MAP_EMACReset \ - EMACReset -#endif -#ifdef ROM_EMACRxDisable -#define MAP_EMACRxDisable \ - ROM_EMACRxDisable -#else -#define MAP_EMACRxDisable \ - EMACRxDisable -#endif -#ifdef ROM_EMACRxDMACurrentBufferGet -#define MAP_EMACRxDMACurrentBufferGet \ - ROM_EMACRxDMACurrentBufferGet -#else -#define MAP_EMACRxDMACurrentBufferGet \ - EMACRxDMACurrentBufferGet -#endif -#ifdef ROM_EMACRxDMACurrentDescriptorGet -#define MAP_EMACRxDMACurrentDescriptorGet \ - ROM_EMACRxDMACurrentDescriptorGet -#else -#define MAP_EMACRxDMACurrentDescriptorGet \ - EMACRxDMACurrentDescriptorGet -#endif -#ifdef ROM_EMACRxDMADescriptorListGet -#define MAP_EMACRxDMADescriptorListGet \ - ROM_EMACRxDMADescriptorListGet -#else -#define MAP_EMACRxDMADescriptorListGet \ - EMACRxDMADescriptorListGet -#endif -#ifdef ROM_EMACRxDMADescriptorListSet -#define MAP_EMACRxDMADescriptorListSet \ - ROM_EMACRxDMADescriptorListSet -#else -#define MAP_EMACRxDMADescriptorListSet \ - EMACRxDMADescriptorListSet -#endif -#ifdef ROM_EMACRxDMAPollDemand -#define MAP_EMACRxDMAPollDemand \ - ROM_EMACRxDMAPollDemand -#else -#define MAP_EMACRxDMAPollDemand \ - EMACRxDMAPollDemand -#endif -#ifdef ROM_EMACRxEnable -#define MAP_EMACRxEnable \ - ROM_EMACRxEnable -#else -#define MAP_EMACRxEnable \ - EMACRxEnable -#endif -#ifdef ROM_EMACRxWatchdogTimerSet -#define MAP_EMACRxWatchdogTimerSet \ - ROM_EMACRxWatchdogTimerSet -#else -#define MAP_EMACRxWatchdogTimerSet \ - EMACRxWatchdogTimerSet -#endif -#ifdef ROM_EMACStatusGet -#define MAP_EMACStatusGet \ - ROM_EMACStatusGet -#else -#define MAP_EMACStatusGet \ - EMACStatusGet -#endif -#ifdef ROM_EMACTxDisable -#define MAP_EMACTxDisable \ - ROM_EMACTxDisable -#else -#define MAP_EMACTxDisable \ - EMACTxDisable -#endif -#ifdef ROM_EMACTxDMACurrentBufferGet -#define MAP_EMACTxDMACurrentBufferGet \ - ROM_EMACTxDMACurrentBufferGet -#else -#define MAP_EMACTxDMACurrentBufferGet \ - EMACTxDMACurrentBufferGet -#endif -#ifdef ROM_EMACTxDMACurrentDescriptorGet -#define MAP_EMACTxDMACurrentDescriptorGet \ - ROM_EMACTxDMACurrentDescriptorGet -#else -#define MAP_EMACTxDMACurrentDescriptorGet \ - EMACTxDMACurrentDescriptorGet -#endif -#ifdef ROM_EMACTxDMADescriptorListGet -#define MAP_EMACTxDMADescriptorListGet \ - ROM_EMACTxDMADescriptorListGet -#else -#define MAP_EMACTxDMADescriptorListGet \ - EMACTxDMADescriptorListGet -#endif -#ifdef ROM_EMACTxDMADescriptorListSet -#define MAP_EMACTxDMADescriptorListSet \ - ROM_EMACTxDMADescriptorListSet -#else -#define MAP_EMACTxDMADescriptorListSet \ - EMACTxDMADescriptorListSet -#endif -#ifdef ROM_EMACTxDMAPollDemand -#define MAP_EMACTxDMAPollDemand \ - ROM_EMACTxDMAPollDemand -#else -#define MAP_EMACTxDMAPollDemand \ - EMACTxDMAPollDemand -#endif -#ifdef ROM_EMACTxEnable -#define MAP_EMACTxEnable \ - ROM_EMACTxEnable -#else -#define MAP_EMACTxEnable \ - EMACTxEnable -#endif -#ifdef ROM_EMACTxFlush -#define MAP_EMACTxFlush \ - ROM_EMACTxFlush -#else -#define MAP_EMACTxFlush \ - EMACTxFlush -#endif -#ifdef ROM_EMACAddrFilterGet -#define MAP_EMACAddrFilterGet \ - ROM_EMACAddrFilterGet -#else -#define MAP_EMACAddrFilterGet \ - EMACAddrFilterGet -#endif -#ifdef ROM_EMACAddrFilterSet -#define MAP_EMACAddrFilterSet \ - ROM_EMACAddrFilterSet -#else -#define MAP_EMACAddrFilterSet \ - EMACAddrFilterSet -#endif -#ifdef ROM_EMACHashFilterBitCalculate -#define MAP_EMACHashFilterBitCalculate \ - ROM_EMACHashFilterBitCalculate -#else -#define MAP_EMACHashFilterBitCalculate \ - EMACHashFilterBitCalculate -#endif -#ifdef ROM_EMACHashFilterGet -#define MAP_EMACHashFilterGet \ - ROM_EMACHashFilterGet -#else -#define MAP_EMACHashFilterGet \ - EMACHashFilterGet -#endif -#ifdef ROM_EMACHashFilterSet -#define MAP_EMACHashFilterSet \ - ROM_EMACHashFilterSet -#else -#define MAP_EMACHashFilterSet \ - EMACHashFilterSet -#endif -#ifdef ROM_EMACNumAddrGet -#define MAP_EMACNumAddrGet \ - ROM_EMACNumAddrGet -#else -#define MAP_EMACNumAddrGet \ - EMACNumAddrGet -#endif -#ifdef ROM_EMACPHYExtendedRead -#define MAP_EMACPHYExtendedRead \ - ROM_EMACPHYExtendedRead -#else -#define MAP_EMACPHYExtendedRead \ - EMACPHYExtendedRead -#endif -#ifdef ROM_EMACPHYExtendedWrite -#define MAP_EMACPHYExtendedWrite \ - ROM_EMACPHYExtendedWrite -#else -#define MAP_EMACPHYExtendedWrite \ - EMACPHYExtendedWrite -#endif -#ifdef ROM_EMACPowerManagementControlGet -#define MAP_EMACPowerManagementControlGet \ - ROM_EMACPowerManagementControlGet -#else -#define MAP_EMACPowerManagementControlGet \ - EMACPowerManagementControlGet -#endif -#ifdef ROM_EMACPowerManagementControlSet -#define MAP_EMACPowerManagementControlSet \ - ROM_EMACPowerManagementControlSet -#else -#define MAP_EMACPowerManagementControlSet \ - EMACPowerManagementControlSet -#endif -#ifdef ROM_EMACPowerManagementStatusGet -#define MAP_EMACPowerManagementStatusGet \ - ROM_EMACPowerManagementStatusGet -#else -#define MAP_EMACPowerManagementStatusGet \ - EMACPowerManagementStatusGet -#endif -#ifdef ROM_EMACRemoteWakeUpFrameFilterGet -#define MAP_EMACRemoteWakeUpFrameFilterGet \ - ROM_EMACRemoteWakeUpFrameFilterGet -#else -#define MAP_EMACRemoteWakeUpFrameFilterGet \ - EMACRemoteWakeUpFrameFilterGet -#endif -#ifdef ROM_EMACRemoteWakeUpFrameFilterSet -#define MAP_EMACRemoteWakeUpFrameFilterSet \ - ROM_EMACRemoteWakeUpFrameFilterSet -#else -#define MAP_EMACRemoteWakeUpFrameFilterSet \ - EMACRemoteWakeUpFrameFilterSet -#endif -#ifdef ROM_EMACTimestampAddendSet -#define MAP_EMACTimestampAddendSet \ - ROM_EMACTimestampAddendSet -#else -#define MAP_EMACTimestampAddendSet \ - EMACTimestampAddendSet -#endif -#ifdef ROM_EMACTimestampConfigGet -#define MAP_EMACTimestampConfigGet \ - ROM_EMACTimestampConfigGet -#else -#define MAP_EMACTimestampConfigGet \ - EMACTimestampConfigGet -#endif -#ifdef ROM_EMACTimestampConfigSet -#define MAP_EMACTimestampConfigSet \ - ROM_EMACTimestampConfigSet -#else -#define MAP_EMACTimestampConfigSet \ - EMACTimestampConfigSet -#endif -#ifdef ROM_EMACTimestampDisable -#define MAP_EMACTimestampDisable \ - ROM_EMACTimestampDisable -#else -#define MAP_EMACTimestampDisable \ - EMACTimestampDisable -#endif -#ifdef ROM_EMACTimestampEnable -#define MAP_EMACTimestampEnable \ - ROM_EMACTimestampEnable -#else -#define MAP_EMACTimestampEnable \ - EMACTimestampEnable -#endif -#ifdef ROM_EMACTimestampIntStatus -#define MAP_EMACTimestampIntStatus \ - ROM_EMACTimestampIntStatus -#else -#define MAP_EMACTimestampIntStatus \ - EMACTimestampIntStatus -#endif -#ifdef ROM_EMACTimestampPPSCommand -#define MAP_EMACTimestampPPSCommand \ - ROM_EMACTimestampPPSCommand -#else -#define MAP_EMACTimestampPPSCommand \ - EMACTimestampPPSCommand -#endif -#ifdef ROM_EMACTimestampPPSCommandModeSet -#define MAP_EMACTimestampPPSCommandModeSet \ - ROM_EMACTimestampPPSCommandModeSet -#else -#define MAP_EMACTimestampPPSCommandModeSet \ - EMACTimestampPPSCommandModeSet -#endif -#ifdef ROM_EMACTimestampPPSPeriodSet -#define MAP_EMACTimestampPPSPeriodSet \ - ROM_EMACTimestampPPSPeriodSet -#else -#define MAP_EMACTimestampPPSPeriodSet \ - EMACTimestampPPSPeriodSet -#endif -#ifdef ROM_EMACTimestampPPSSimpleModeSet -#define MAP_EMACTimestampPPSSimpleModeSet \ - ROM_EMACTimestampPPSSimpleModeSet -#else -#define MAP_EMACTimestampPPSSimpleModeSet \ - EMACTimestampPPSSimpleModeSet -#endif -#ifdef ROM_EMACTimestampSysTimeGet -#define MAP_EMACTimestampSysTimeGet \ - ROM_EMACTimestampSysTimeGet -#else -#define MAP_EMACTimestampSysTimeGet \ - EMACTimestampSysTimeGet -#endif -#ifdef ROM_EMACTimestampSysTimeSet -#define MAP_EMACTimestampSysTimeSet \ - ROM_EMACTimestampSysTimeSet -#else -#define MAP_EMACTimestampSysTimeSet \ - EMACTimestampSysTimeSet -#endif -#ifdef ROM_EMACTimestampSysTimeUpdate -#define MAP_EMACTimestampSysTimeUpdate \ - ROM_EMACTimestampSysTimeUpdate -#else -#define MAP_EMACTimestampSysTimeUpdate \ - EMACTimestampSysTimeUpdate -#endif -#ifdef ROM_EMACTimestampTargetIntDisable -#define MAP_EMACTimestampTargetIntDisable \ - ROM_EMACTimestampTargetIntDisable -#else -#define MAP_EMACTimestampTargetIntDisable \ - EMACTimestampTargetIntDisable -#endif -#ifdef ROM_EMACTimestampTargetIntEnable -#define MAP_EMACTimestampTargetIntEnable \ - ROM_EMACTimestampTargetIntEnable -#else -#define MAP_EMACTimestampTargetIntEnable \ - EMACTimestampTargetIntEnable -#endif -#ifdef ROM_EMACTimestampTargetSet -#define MAP_EMACTimestampTargetSet \ - ROM_EMACTimestampTargetSet -#else -#define MAP_EMACTimestampTargetSet \ - EMACTimestampTargetSet -#endif -#ifdef ROM_EMACVLANHashFilterBitCalculate -#define MAP_EMACVLANHashFilterBitCalculate \ - ROM_EMACVLANHashFilterBitCalculate -#else -#define MAP_EMACVLANHashFilterBitCalculate \ - EMACVLANHashFilterBitCalculate -#endif -#ifdef ROM_EMACVLANHashFilterGet -#define MAP_EMACVLANHashFilterGet \ - ROM_EMACVLANHashFilterGet -#else -#define MAP_EMACVLANHashFilterGet \ - EMACVLANHashFilterGet -#endif -#ifdef ROM_EMACVLANHashFilterSet -#define MAP_EMACVLANHashFilterSet \ - ROM_EMACVLANHashFilterSet -#else -#define MAP_EMACVLANHashFilterSet \ - EMACVLANHashFilterSet -#endif -#ifdef ROM_EMACVLANRxConfigGet -#define MAP_EMACVLANRxConfigGet \ - ROM_EMACVLANRxConfigGet -#else -#define MAP_EMACVLANRxConfigGet \ - EMACVLANRxConfigGet -#endif -#ifdef ROM_EMACVLANRxConfigSet -#define MAP_EMACVLANRxConfigSet \ - ROM_EMACVLANRxConfigSet -#else -#define MAP_EMACVLANRxConfigSet \ - EMACVLANRxConfigSet -#endif -#ifdef ROM_EMACVLANTxConfigGet -#define MAP_EMACVLANTxConfigGet \ - ROM_EMACVLANTxConfigGet -#else -#define MAP_EMACVLANTxConfigGet \ - EMACVLANTxConfigGet -#endif -#ifdef ROM_EMACVLANTxConfigSet -#define MAP_EMACVLANTxConfigSet \ - ROM_EMACVLANTxConfigSet -#else -#define MAP_EMACVLANTxConfigSet \ - EMACVLANTxConfigSet -#endif - -//***************************************************************************** -// -// Macros for the Flash API. -// -//***************************************************************************** -#ifdef ROM_FlashProgram -#define MAP_FlashProgram \ - ROM_FlashProgram -#else -#define MAP_FlashProgram \ - FlashProgram -#endif -#ifdef ROM_FlashErase -#define MAP_FlashErase \ - ROM_FlashErase -#else -#define MAP_FlashErase \ - FlashErase -#endif -#ifdef ROM_FlashProtectGet -#define MAP_FlashProtectGet \ - ROM_FlashProtectGet -#else -#define MAP_FlashProtectGet \ - FlashProtectGet -#endif -#ifdef ROM_FlashProtectSet -#define MAP_FlashProtectSet \ - ROM_FlashProtectSet -#else -#define MAP_FlashProtectSet \ - FlashProtectSet -#endif -#ifdef ROM_FlashProtectSave -#define MAP_FlashProtectSave \ - ROM_FlashProtectSave -#else -#define MAP_FlashProtectSave \ - FlashProtectSave -#endif -#ifdef ROM_FlashUserGet -#define MAP_FlashUserGet \ - ROM_FlashUserGet -#else -#define MAP_FlashUserGet \ - FlashUserGet -#endif -#ifdef ROM_FlashUserSet -#define MAP_FlashUserSet \ - ROM_FlashUserSet -#else -#define MAP_FlashUserSet \ - FlashUserSet -#endif -#ifdef ROM_FlashUserSave -#define MAP_FlashUserSave \ - ROM_FlashUserSave -#else -#define MAP_FlashUserSave \ - FlashUserSave -#endif -#ifdef ROM_FlashIntEnable -#define MAP_FlashIntEnable \ - ROM_FlashIntEnable -#else -#define MAP_FlashIntEnable \ - FlashIntEnable -#endif -#ifdef ROM_FlashIntDisable -#define MAP_FlashIntDisable \ - ROM_FlashIntDisable -#else -#define MAP_FlashIntDisable \ - FlashIntDisable -#endif -#ifdef ROM_FlashIntStatus -#define MAP_FlashIntStatus \ - ROM_FlashIntStatus -#else -#define MAP_FlashIntStatus \ - FlashIntStatus -#endif -#ifdef ROM_FlashIntClear -#define MAP_FlashIntClear \ - ROM_FlashIntClear -#else -#define MAP_FlashIntClear \ - FlashIntClear -#endif - -//***************************************************************************** -// -// Macros for the FPU API. -// -//***************************************************************************** -#ifdef ROM_FPUEnable -#define MAP_FPUEnable \ - ROM_FPUEnable -#else -#define MAP_FPUEnable \ - FPUEnable -#endif -#ifdef ROM_FPUDisable -#define MAP_FPUDisable \ - ROM_FPUDisable -#else -#define MAP_FPUDisable \ - FPUDisable -#endif -#ifdef ROM_FPUFlushToZeroModeSet -#define MAP_FPUFlushToZeroModeSet \ - ROM_FPUFlushToZeroModeSet -#else -#define MAP_FPUFlushToZeroModeSet \ - FPUFlushToZeroModeSet -#endif -#ifdef ROM_FPUHalfPrecisionModeSet -#define MAP_FPUHalfPrecisionModeSet \ - ROM_FPUHalfPrecisionModeSet -#else -#define MAP_FPUHalfPrecisionModeSet \ - FPUHalfPrecisionModeSet -#endif -#ifdef ROM_FPULazyStackingEnable -#define MAP_FPULazyStackingEnable \ - ROM_FPULazyStackingEnable -#else -#define MAP_FPULazyStackingEnable \ - FPULazyStackingEnable -#endif -#ifdef ROM_FPUNaNModeSet -#define MAP_FPUNaNModeSet \ - ROM_FPUNaNModeSet -#else -#define MAP_FPUNaNModeSet \ - FPUNaNModeSet -#endif -#ifdef ROM_FPURoundingModeSet -#define MAP_FPURoundingModeSet \ - ROM_FPURoundingModeSet -#else -#define MAP_FPURoundingModeSet \ - FPURoundingModeSet -#endif -#ifdef ROM_FPUStackingDisable -#define MAP_FPUStackingDisable \ - ROM_FPUStackingDisable -#else -#define MAP_FPUStackingDisable \ - FPUStackingDisable -#endif -#ifdef ROM_FPUStackingEnable -#define MAP_FPUStackingEnable \ - ROM_FPUStackingEnable -#else -#define MAP_FPUStackingEnable \ - FPUStackingEnable -#endif - -//***************************************************************************** -// -// Macros for the GPIO API. -// -//***************************************************************************** -#ifdef ROM_GPIOPinWrite -#define MAP_GPIOPinWrite \ - ROM_GPIOPinWrite -#else -#define MAP_GPIOPinWrite \ - GPIOPinWrite -#endif -#ifdef ROM_GPIODirModeSet -#define MAP_GPIODirModeSet \ - ROM_GPIODirModeSet -#else -#define MAP_GPIODirModeSet \ - GPIODirModeSet -#endif -#ifdef ROM_GPIODirModeGet -#define MAP_GPIODirModeGet \ - ROM_GPIODirModeGet -#else -#define MAP_GPIODirModeGet \ - GPIODirModeGet -#endif -#ifdef ROM_GPIOIntTypeSet -#define MAP_GPIOIntTypeSet \ - ROM_GPIOIntTypeSet -#else -#define MAP_GPIOIntTypeSet \ - GPIOIntTypeSet -#endif -#ifdef ROM_GPIOIntTypeGet -#define MAP_GPIOIntTypeGet \ - ROM_GPIOIntTypeGet -#else -#define MAP_GPIOIntTypeGet \ - GPIOIntTypeGet -#endif -#ifdef ROM_GPIOPadConfigSet -#define MAP_GPIOPadConfigSet \ - ROM_GPIOPadConfigSet -#else -#define MAP_GPIOPadConfigSet \ - GPIOPadConfigSet -#endif -#ifdef ROM_GPIOPadConfigGet -#define MAP_GPIOPadConfigGet \ - ROM_GPIOPadConfigGet -#else -#define MAP_GPIOPadConfigGet \ - GPIOPadConfigGet -#endif -#ifdef ROM_GPIOPinRead -#define MAP_GPIOPinRead \ - ROM_GPIOPinRead -#else -#define MAP_GPIOPinRead \ - GPIOPinRead -#endif -#ifdef ROM_GPIOPinTypeCAN -#define MAP_GPIOPinTypeCAN \ - ROM_GPIOPinTypeCAN -#else -#define MAP_GPIOPinTypeCAN \ - GPIOPinTypeCAN -#endif -#ifdef ROM_GPIOPinTypeComparator -#define MAP_GPIOPinTypeComparator \ - ROM_GPIOPinTypeComparator -#else -#define MAP_GPIOPinTypeComparator \ - GPIOPinTypeComparator -#endif -#ifdef ROM_GPIOPinTypeGPIOInput -#define MAP_GPIOPinTypeGPIOInput \ - ROM_GPIOPinTypeGPIOInput -#else -#define MAP_GPIOPinTypeGPIOInput \ - GPIOPinTypeGPIOInput -#endif -#ifdef ROM_GPIOPinTypeGPIOOutput -#define MAP_GPIOPinTypeGPIOOutput \ - ROM_GPIOPinTypeGPIOOutput -#else -#define MAP_GPIOPinTypeGPIOOutput \ - GPIOPinTypeGPIOOutput -#endif -#ifdef ROM_GPIOPinTypeI2C -#define MAP_GPIOPinTypeI2C \ - ROM_GPIOPinTypeI2C -#else -#define MAP_GPIOPinTypeI2C \ - GPIOPinTypeI2C -#endif -#ifdef ROM_GPIOPinTypePWM -#define MAP_GPIOPinTypePWM \ - ROM_GPIOPinTypePWM -#else -#define MAP_GPIOPinTypePWM \ - GPIOPinTypePWM -#endif -#ifdef ROM_GPIOPinTypeQEI -#define MAP_GPIOPinTypeQEI \ - ROM_GPIOPinTypeQEI -#else -#define MAP_GPIOPinTypeQEI \ - GPIOPinTypeQEI -#endif -#ifdef ROM_GPIOPinTypeSSI -#define MAP_GPIOPinTypeSSI \ - ROM_GPIOPinTypeSSI -#else -#define MAP_GPIOPinTypeSSI \ - GPIOPinTypeSSI -#endif -#ifdef ROM_GPIOPinTypeTimer -#define MAP_GPIOPinTypeTimer \ - ROM_GPIOPinTypeTimer -#else -#define MAP_GPIOPinTypeTimer \ - GPIOPinTypeTimer -#endif -#ifdef ROM_GPIOPinTypeUART -#define MAP_GPIOPinTypeUART \ - ROM_GPIOPinTypeUART -#else -#define MAP_GPIOPinTypeUART \ - GPIOPinTypeUART -#endif -#ifdef ROM_GPIOPinTypeGPIOOutputOD -#define MAP_GPIOPinTypeGPIOOutputOD \ - ROM_GPIOPinTypeGPIOOutputOD -#else -#define MAP_GPIOPinTypeGPIOOutputOD \ - GPIOPinTypeGPIOOutputOD -#endif -#ifdef ROM_GPIOPinTypeADC -#define MAP_GPIOPinTypeADC \ - ROM_GPIOPinTypeADC -#else -#define MAP_GPIOPinTypeADC \ - GPIOPinTypeADC -#endif -#ifdef ROM_GPIOPinTypeUSBDigital -#define MAP_GPIOPinTypeUSBDigital \ - ROM_GPIOPinTypeUSBDigital -#else -#define MAP_GPIOPinTypeUSBDigital \ - GPIOPinTypeUSBDigital -#endif -#ifdef ROM_GPIOPinConfigure -#define MAP_GPIOPinConfigure \ - ROM_GPIOPinConfigure -#else -#define MAP_GPIOPinConfigure \ - GPIOPinConfigure -#endif -#ifdef ROM_GPIOPinTypeUSBAnalog -#define MAP_GPIOPinTypeUSBAnalog \ - ROM_GPIOPinTypeUSBAnalog -#else -#define MAP_GPIOPinTypeUSBAnalog \ - GPIOPinTypeUSBAnalog -#endif -#ifdef ROM_GPIODMATriggerEnable -#define MAP_GPIODMATriggerEnable \ - ROM_GPIODMATriggerEnable -#else -#define MAP_GPIODMATriggerEnable \ - GPIODMATriggerEnable -#endif -#ifdef ROM_GPIODMATriggerDisable -#define MAP_GPIODMATriggerDisable \ - ROM_GPIODMATriggerDisable -#else -#define MAP_GPIODMATriggerDisable \ - GPIODMATriggerDisable -#endif -#ifdef ROM_GPIOADCTriggerEnable -#define MAP_GPIOADCTriggerEnable \ - ROM_GPIOADCTriggerEnable -#else -#define MAP_GPIOADCTriggerEnable \ - GPIOADCTriggerEnable -#endif -#ifdef ROM_GPIOADCTriggerDisable -#define MAP_GPIOADCTriggerDisable \ - ROM_GPIOADCTriggerDisable -#else -#define MAP_GPIOADCTriggerDisable \ - GPIOADCTriggerDisable -#endif -#ifdef ROM_GPIOPinTypeI2CSCL -#define MAP_GPIOPinTypeI2CSCL \ - ROM_GPIOPinTypeI2CSCL -#else -#define MAP_GPIOPinTypeI2CSCL \ - GPIOPinTypeI2CSCL -#endif -#ifdef ROM_GPIOPinTypeOneWire -#define MAP_GPIOPinTypeOneWire \ - ROM_GPIOPinTypeOneWire -#else -#define MAP_GPIOPinTypeOneWire \ - GPIOPinTypeOneWire -#endif -#ifdef ROM_GPIOPinTypeWakeHigh -#define MAP_GPIOPinTypeWakeHigh \ - ROM_GPIOPinTypeWakeHigh -#else -#define MAP_GPIOPinTypeWakeHigh \ - GPIOPinTypeWakeHigh -#endif -#ifdef ROM_GPIOPinTypeWakeLow -#define MAP_GPIOPinTypeWakeLow \ - ROM_GPIOPinTypeWakeLow -#else -#define MAP_GPIOPinTypeWakeLow \ - GPIOPinTypeWakeLow -#endif -#ifdef ROM_GPIOIntClear -#define MAP_GPIOIntClear \ - ROM_GPIOIntClear -#else -#define MAP_GPIOIntClear \ - GPIOIntClear -#endif -#ifdef ROM_GPIOIntDisable -#define MAP_GPIOIntDisable \ - ROM_GPIOIntDisable -#else -#define MAP_GPIOIntDisable \ - GPIOIntDisable -#endif -#ifdef ROM_GPIOIntEnable -#define MAP_GPIOIntEnable \ - ROM_GPIOIntEnable -#else -#define MAP_GPIOIntEnable \ - GPIOIntEnable -#endif -#ifdef ROM_GPIOIntStatus -#define MAP_GPIOIntStatus \ - ROM_GPIOIntStatus -#else -#define MAP_GPIOIntStatus \ - GPIOIntStatus -#endif -#ifdef ROM_GPIOPinWakeStatus -#define MAP_GPIOPinWakeStatus \ - ROM_GPIOPinWakeStatus -#else -#define MAP_GPIOPinWakeStatus \ - GPIOPinWakeStatus -#endif - -//***************************************************************************** -// -// Macros for the Hibernate API. -// -//***************************************************************************** -#ifdef ROM_HibernateIntClear -#define MAP_HibernateIntClear \ - ROM_HibernateIntClear -#else -#define MAP_HibernateIntClear \ - HibernateIntClear -#endif -#ifdef ROM_HibernateEnableExpClk -#define MAP_HibernateEnableExpClk \ - ROM_HibernateEnableExpClk -#else -#define MAP_HibernateEnableExpClk \ - HibernateEnableExpClk -#endif -#ifdef ROM_HibernateDisable -#define MAP_HibernateDisable \ - ROM_HibernateDisable -#else -#define MAP_HibernateDisable \ - HibernateDisable -#endif -#ifdef ROM_HibernateRTCEnable -#define MAP_HibernateRTCEnable \ - ROM_HibernateRTCEnable -#else -#define MAP_HibernateRTCEnable \ - HibernateRTCEnable -#endif -#ifdef ROM_HibernateRTCDisable -#define MAP_HibernateRTCDisable \ - ROM_HibernateRTCDisable -#else -#define MAP_HibernateRTCDisable \ - HibernateRTCDisable -#endif -#ifdef ROM_HibernateWakeSet -#define MAP_HibernateWakeSet \ - ROM_HibernateWakeSet -#else -#define MAP_HibernateWakeSet \ - HibernateWakeSet -#endif -#ifdef ROM_HibernateWakeGet -#define MAP_HibernateWakeGet \ - ROM_HibernateWakeGet -#else -#define MAP_HibernateWakeGet \ - HibernateWakeGet -#endif -#ifdef ROM_HibernateLowBatSet -#define MAP_HibernateLowBatSet \ - ROM_HibernateLowBatSet -#else -#define MAP_HibernateLowBatSet \ - HibernateLowBatSet -#endif -#ifdef ROM_HibernateLowBatGet -#define MAP_HibernateLowBatGet \ - ROM_HibernateLowBatGet -#else -#define MAP_HibernateLowBatGet \ - HibernateLowBatGet -#endif -#ifdef ROM_HibernateRTCSet -#define MAP_HibernateRTCSet \ - ROM_HibernateRTCSet -#else -#define MAP_HibernateRTCSet \ - HibernateRTCSet -#endif -#ifdef ROM_HibernateRTCGet -#define MAP_HibernateRTCGet \ - ROM_HibernateRTCGet -#else -#define MAP_HibernateRTCGet \ - HibernateRTCGet -#endif -#ifdef ROM_HibernateRTCTrimSet -#define MAP_HibernateRTCTrimSet \ - ROM_HibernateRTCTrimSet -#else -#define MAP_HibernateRTCTrimSet \ - HibernateRTCTrimSet -#endif -#ifdef ROM_HibernateRTCTrimGet -#define MAP_HibernateRTCTrimGet \ - ROM_HibernateRTCTrimGet -#else -#define MAP_HibernateRTCTrimGet \ - HibernateRTCTrimGet -#endif -#ifdef ROM_HibernateDataSet -#define MAP_HibernateDataSet \ - ROM_HibernateDataSet -#else -#define MAP_HibernateDataSet \ - HibernateDataSet -#endif -#ifdef ROM_HibernateDataGet -#define MAP_HibernateDataGet \ - ROM_HibernateDataGet -#else -#define MAP_HibernateDataGet \ - HibernateDataGet -#endif -#ifdef ROM_HibernateRequest -#define MAP_HibernateRequest \ - ROM_HibernateRequest -#else -#define MAP_HibernateRequest \ - HibernateRequest -#endif -#ifdef ROM_HibernateIntEnable -#define MAP_HibernateIntEnable \ - ROM_HibernateIntEnable -#else -#define MAP_HibernateIntEnable \ - HibernateIntEnable -#endif -#ifdef ROM_HibernateIntDisable -#define MAP_HibernateIntDisable \ - ROM_HibernateIntDisable -#else -#define MAP_HibernateIntDisable \ - HibernateIntDisable -#endif -#ifdef ROM_HibernateIntStatus -#define MAP_HibernateIntStatus \ - ROM_HibernateIntStatus -#else -#define MAP_HibernateIntStatus \ - HibernateIntStatus -#endif -#ifdef ROM_HibernateIsActive -#define MAP_HibernateIsActive \ - ROM_HibernateIsActive -#else -#define MAP_HibernateIsActive \ - HibernateIsActive -#endif -#ifdef ROM_HibernateRTCSSGet -#define MAP_HibernateRTCSSGet \ - ROM_HibernateRTCSSGet -#else -#define MAP_HibernateRTCSSGet \ - HibernateRTCSSGet -#endif -#ifdef ROM_HibernateClockConfig -#define MAP_HibernateClockConfig \ - ROM_HibernateClockConfig -#else -#define MAP_HibernateClockConfig \ - HibernateClockConfig -#endif -#ifdef ROM_HibernateBatCheckStart -#define MAP_HibernateBatCheckStart \ - ROM_HibernateBatCheckStart -#else -#define MAP_HibernateBatCheckStart \ - HibernateBatCheckStart -#endif -#ifdef ROM_HibernateBatCheckDone -#define MAP_HibernateBatCheckDone \ - ROM_HibernateBatCheckDone -#else -#define MAP_HibernateBatCheckDone \ - HibernateBatCheckDone -#endif -#ifdef ROM_HibernateGPIORetentionEnable -#define MAP_HibernateGPIORetentionEnable \ - ROM_HibernateGPIORetentionEnable -#else -#define MAP_HibernateGPIORetentionEnable \ - HibernateGPIORetentionEnable -#endif -#ifdef ROM_HibernateGPIORetentionDisable -#define MAP_HibernateGPIORetentionDisable \ - ROM_HibernateGPIORetentionDisable -#else -#define MAP_HibernateGPIORetentionDisable \ - HibernateGPIORetentionDisable -#endif -#ifdef ROM_HibernateGPIORetentionGet -#define MAP_HibernateGPIORetentionGet \ - ROM_HibernateGPIORetentionGet -#else -#define MAP_HibernateGPIORetentionGet \ - HibernateGPIORetentionGet -#endif -#ifdef ROM_HibernateCounterMode -#define MAP_HibernateCounterMode \ - ROM_HibernateCounterMode -#else -#define MAP_HibernateCounterMode \ - HibernateCounterMode -#endif -#ifdef ROM_HibernateCalendarSet -#define MAP_HibernateCalendarSet \ - ROM_HibernateCalendarSet -#else -#define MAP_HibernateCalendarSet \ - HibernateCalendarSet -#endif -#ifdef ROM_HibernateCalendarGet -#define MAP_HibernateCalendarGet \ - ROM_HibernateCalendarGet -#else -#define MAP_HibernateCalendarGet \ - HibernateCalendarGet -#endif -#ifdef ROM_HibernateCalendarMatchSet -#define MAP_HibernateCalendarMatchSet \ - ROM_HibernateCalendarMatchSet -#else -#define MAP_HibernateCalendarMatchSet \ - HibernateCalendarMatchSet -#endif -#ifdef ROM_HibernateCalendarMatchGet -#define MAP_HibernateCalendarMatchGet \ - ROM_HibernateCalendarMatchGet -#else -#define MAP_HibernateCalendarMatchGet \ - HibernateCalendarMatchGet -#endif -#ifdef ROM_HibernateTamperDisable -#define MAP_HibernateTamperDisable \ - ROM_HibernateTamperDisable -#else -#define MAP_HibernateTamperDisable \ - HibernateTamperDisable -#endif -#ifdef ROM_HibernateTamperEnable -#define MAP_HibernateTamperEnable \ - ROM_HibernateTamperEnable -#else -#define MAP_HibernateTamperEnable \ - HibernateTamperEnable -#endif -#ifdef ROM_HibernateTamperEventsClear -#define MAP_HibernateTamperEventsClear \ - ROM_HibernateTamperEventsClear -#else -#define MAP_HibernateTamperEventsClear \ - HibernateTamperEventsClear -#endif -#ifdef ROM_HibernateTamperEventsConfig -#define MAP_HibernateTamperEventsConfig \ - ROM_HibernateTamperEventsConfig -#else -#define MAP_HibernateTamperEventsConfig \ - HibernateTamperEventsConfig -#endif -#ifdef ROM_HibernateTamperEventsGet -#define MAP_HibernateTamperEventsGet \ - ROM_HibernateTamperEventsGet -#else -#define MAP_HibernateTamperEventsGet \ - HibernateTamperEventsGet -#endif -#ifdef ROM_HibernateTamperExtOscValid -#define MAP_HibernateTamperExtOscValid \ - ROM_HibernateTamperExtOscValid -#else -#define MAP_HibernateTamperExtOscValid \ - HibernateTamperExtOscValid -#endif -#ifdef ROM_HibernateTamperExtOscRecover -#define MAP_HibernateTamperExtOscRecover \ - ROM_HibernateTamperExtOscRecover -#else -#define MAP_HibernateTamperExtOscRecover \ - HibernateTamperExtOscRecover -#endif -#ifdef ROM_HibernateTamperIODisable -#define MAP_HibernateTamperIODisable \ - ROM_HibernateTamperIODisable -#else -#define MAP_HibernateTamperIODisable \ - HibernateTamperIODisable -#endif -#ifdef ROM_HibernateTamperIOEnable -#define MAP_HibernateTamperIOEnable \ - ROM_HibernateTamperIOEnable -#else -#define MAP_HibernateTamperIOEnable \ - HibernateTamperIOEnable -#endif -#ifdef ROM_HibernateTamperStatusGet -#define MAP_HibernateTamperStatusGet \ - ROM_HibernateTamperStatusGet -#else -#define MAP_HibernateTamperStatusGet \ - HibernateTamperStatusGet -#endif -#ifdef ROM_HibernateRTCMatchGet -#define MAP_HibernateRTCMatchGet \ - ROM_HibernateRTCMatchGet -#else -#define MAP_HibernateRTCMatchGet \ - HibernateRTCMatchGet -#endif -#ifdef ROM_HibernateRTCMatchSet -#define MAP_HibernateRTCMatchSet \ - ROM_HibernateRTCMatchSet -#else -#define MAP_HibernateRTCMatchSet \ - HibernateRTCMatchSet -#endif -#ifdef ROM_HibernateRTCSSMatchGet -#define MAP_HibernateRTCSSMatchGet \ - ROM_HibernateRTCSSMatchGet -#else -#define MAP_HibernateRTCSSMatchGet \ - HibernateRTCSSMatchGet -#endif -#ifdef ROM_HibernateRTCSSMatchSet -#define MAP_HibernateRTCSSMatchSet \ - ROM_HibernateRTCSSMatchSet -#else -#define MAP_HibernateRTCSSMatchSet \ - HibernateRTCSSMatchSet -#endif - -//***************************************************************************** -// -// Macros for the I2C API. -// -//***************************************************************************** -#ifdef ROM_I2CMasterDataPut -#define MAP_I2CMasterDataPut \ - ROM_I2CMasterDataPut -#else -#define MAP_I2CMasterDataPut \ - I2CMasterDataPut -#endif -#ifdef ROM_I2CMasterInitExpClk -#define MAP_I2CMasterInitExpClk \ - ROM_I2CMasterInitExpClk -#else -#define MAP_I2CMasterInitExpClk \ - I2CMasterInitExpClk -#endif -#ifdef ROM_I2CSlaveInit -#define MAP_I2CSlaveInit \ - ROM_I2CSlaveInit -#else -#define MAP_I2CSlaveInit \ - I2CSlaveInit -#endif -#ifdef ROM_I2CMasterEnable -#define MAP_I2CMasterEnable \ - ROM_I2CMasterEnable -#else -#define MAP_I2CMasterEnable \ - I2CMasterEnable -#endif -#ifdef ROM_I2CSlaveEnable -#define MAP_I2CSlaveEnable \ - ROM_I2CSlaveEnable -#else -#define MAP_I2CSlaveEnable \ - I2CSlaveEnable -#endif -#ifdef ROM_I2CMasterDisable -#define MAP_I2CMasterDisable \ - ROM_I2CMasterDisable -#else -#define MAP_I2CMasterDisable \ - I2CMasterDisable -#endif -#ifdef ROM_I2CSlaveDisable -#define MAP_I2CSlaveDisable \ - ROM_I2CSlaveDisable -#else -#define MAP_I2CSlaveDisable \ - I2CSlaveDisable -#endif -#ifdef ROM_I2CMasterIntEnable -#define MAP_I2CMasterIntEnable \ - ROM_I2CMasterIntEnable -#else -#define MAP_I2CMasterIntEnable \ - I2CMasterIntEnable -#endif -#ifdef ROM_I2CSlaveIntEnable -#define MAP_I2CSlaveIntEnable \ - ROM_I2CSlaveIntEnable -#else -#define MAP_I2CSlaveIntEnable \ - I2CSlaveIntEnable -#endif -#ifdef ROM_I2CMasterIntDisable -#define MAP_I2CMasterIntDisable \ - ROM_I2CMasterIntDisable -#else -#define MAP_I2CMasterIntDisable \ - I2CMasterIntDisable -#endif -#ifdef ROM_I2CSlaveIntDisable -#define MAP_I2CSlaveIntDisable \ - ROM_I2CSlaveIntDisable -#else -#define MAP_I2CSlaveIntDisable \ - I2CSlaveIntDisable -#endif -#ifdef ROM_I2CMasterIntStatus -#define MAP_I2CMasterIntStatus \ - ROM_I2CMasterIntStatus -#else -#define MAP_I2CMasterIntStatus \ - I2CMasterIntStatus -#endif -#ifdef ROM_I2CSlaveIntStatus -#define MAP_I2CSlaveIntStatus \ - ROM_I2CSlaveIntStatus -#else -#define MAP_I2CSlaveIntStatus \ - I2CSlaveIntStatus -#endif -#ifdef ROM_I2CMasterIntClear -#define MAP_I2CMasterIntClear \ - ROM_I2CMasterIntClear -#else -#define MAP_I2CMasterIntClear \ - I2CMasterIntClear -#endif -#ifdef ROM_I2CSlaveIntClear -#define MAP_I2CSlaveIntClear \ - ROM_I2CSlaveIntClear -#else -#define MAP_I2CSlaveIntClear \ - I2CSlaveIntClear -#endif -#ifdef ROM_I2CMasterSlaveAddrSet -#define MAP_I2CMasterSlaveAddrSet \ - ROM_I2CMasterSlaveAddrSet -#else -#define MAP_I2CMasterSlaveAddrSet \ - I2CMasterSlaveAddrSet -#endif -#ifdef ROM_I2CMasterBusy -#define MAP_I2CMasterBusy \ - ROM_I2CMasterBusy -#else -#define MAP_I2CMasterBusy \ - I2CMasterBusy -#endif -#ifdef ROM_I2CMasterBusBusy -#define MAP_I2CMasterBusBusy \ - ROM_I2CMasterBusBusy -#else -#define MAP_I2CMasterBusBusy \ - I2CMasterBusBusy -#endif -#ifdef ROM_I2CMasterControl -#define MAP_I2CMasterControl \ - ROM_I2CMasterControl -#else -#define MAP_I2CMasterControl \ - I2CMasterControl -#endif -#ifdef ROM_I2CMasterErr -#define MAP_I2CMasterErr \ - ROM_I2CMasterErr -#else -#define MAP_I2CMasterErr \ - I2CMasterErr -#endif -#ifdef ROM_I2CMasterDataGet -#define MAP_I2CMasterDataGet \ - ROM_I2CMasterDataGet -#else -#define MAP_I2CMasterDataGet \ - I2CMasterDataGet -#endif -#ifdef ROM_I2CSlaveStatus -#define MAP_I2CSlaveStatus \ - ROM_I2CSlaveStatus -#else -#define MAP_I2CSlaveStatus \ - I2CSlaveStatus -#endif -#ifdef ROM_I2CSlaveDataPut -#define MAP_I2CSlaveDataPut \ - ROM_I2CSlaveDataPut -#else -#define MAP_I2CSlaveDataPut \ - I2CSlaveDataPut -#endif -#ifdef ROM_I2CSlaveDataGet -#define MAP_I2CSlaveDataGet \ - ROM_I2CSlaveDataGet -#else -#define MAP_I2CSlaveDataGet \ - I2CSlaveDataGet -#endif -#ifdef ROM_I2CSlaveIntEnableEx -#define MAP_I2CSlaveIntEnableEx \ - ROM_I2CSlaveIntEnableEx -#else -#define MAP_I2CSlaveIntEnableEx \ - I2CSlaveIntEnableEx -#endif -#ifdef ROM_I2CSlaveIntDisableEx -#define MAP_I2CSlaveIntDisableEx \ - ROM_I2CSlaveIntDisableEx -#else -#define MAP_I2CSlaveIntDisableEx \ - I2CSlaveIntDisableEx -#endif -#ifdef ROM_I2CSlaveIntStatusEx -#define MAP_I2CSlaveIntStatusEx \ - ROM_I2CSlaveIntStatusEx -#else -#define MAP_I2CSlaveIntStatusEx \ - I2CSlaveIntStatusEx -#endif -#ifdef ROM_I2CSlaveIntClearEx -#define MAP_I2CSlaveIntClearEx \ - ROM_I2CSlaveIntClearEx -#else -#define MAP_I2CSlaveIntClearEx \ - I2CSlaveIntClearEx -#endif -#ifdef ROM_I2CMasterIntEnableEx -#define MAP_I2CMasterIntEnableEx \ - ROM_I2CMasterIntEnableEx -#else -#define MAP_I2CMasterIntEnableEx \ - I2CMasterIntEnableEx -#endif -#ifdef ROM_I2CMasterIntDisableEx -#define MAP_I2CMasterIntDisableEx \ - ROM_I2CMasterIntDisableEx -#else -#define MAP_I2CMasterIntDisableEx \ - I2CMasterIntDisableEx -#endif -#ifdef ROM_I2CMasterIntStatusEx -#define MAP_I2CMasterIntStatusEx \ - ROM_I2CMasterIntStatusEx -#else -#define MAP_I2CMasterIntStatusEx \ - I2CMasterIntStatusEx -#endif -#ifdef ROM_I2CMasterIntClearEx -#define MAP_I2CMasterIntClearEx \ - ROM_I2CMasterIntClearEx -#else -#define MAP_I2CMasterIntClearEx \ - I2CMasterIntClearEx -#endif -#ifdef ROM_I2CMasterTimeoutSet -#define MAP_I2CMasterTimeoutSet \ - ROM_I2CMasterTimeoutSet -#else -#define MAP_I2CMasterTimeoutSet \ - I2CMasterTimeoutSet -#endif -#ifdef ROM_I2CSlaveACKOverride -#define MAP_I2CSlaveACKOverride \ - ROM_I2CSlaveACKOverride -#else -#define MAP_I2CSlaveACKOverride \ - I2CSlaveACKOverride -#endif -#ifdef ROM_I2CSlaveACKValueSet -#define MAP_I2CSlaveACKValueSet \ - ROM_I2CSlaveACKValueSet -#else -#define MAP_I2CSlaveACKValueSet \ - I2CSlaveACKValueSet -#endif -#ifdef ROM_I2CSlaveAddressSet -#define MAP_I2CSlaveAddressSet \ - ROM_I2CSlaveAddressSet -#else -#define MAP_I2CSlaveAddressSet \ - I2CSlaveAddressSet -#endif -#ifdef ROM_I2CMasterLineStateGet -#define MAP_I2CMasterLineStateGet \ - ROM_I2CMasterLineStateGet -#else -#define MAP_I2CMasterLineStateGet \ - I2CMasterLineStateGet -#endif -#ifdef ROM_I2CTxFIFOConfigSet -#define MAP_I2CTxFIFOConfigSet \ - ROM_I2CTxFIFOConfigSet -#else -#define MAP_I2CTxFIFOConfigSet \ - I2CTxFIFOConfigSet -#endif -#ifdef ROM_I2CTxFIFOFlush -#define MAP_I2CTxFIFOFlush \ - ROM_I2CTxFIFOFlush -#else -#define MAP_I2CTxFIFOFlush \ - I2CTxFIFOFlush -#endif -#ifdef ROM_I2CRxFIFOConfigSet -#define MAP_I2CRxFIFOConfigSet \ - ROM_I2CRxFIFOConfigSet -#else -#define MAP_I2CRxFIFOConfigSet \ - I2CRxFIFOConfigSet -#endif -#ifdef ROM_I2CRxFIFOFlush -#define MAP_I2CRxFIFOFlush \ - ROM_I2CRxFIFOFlush -#else -#define MAP_I2CRxFIFOFlush \ - I2CRxFIFOFlush -#endif -#ifdef ROM_I2CFIFOStatus -#define MAP_I2CFIFOStatus \ - ROM_I2CFIFOStatus -#else -#define MAP_I2CFIFOStatus \ - I2CFIFOStatus -#endif -#ifdef ROM_I2CFIFODataPut -#define MAP_I2CFIFODataPut \ - ROM_I2CFIFODataPut -#else -#define MAP_I2CFIFODataPut \ - I2CFIFODataPut -#endif -#ifdef ROM_I2CFIFODataPutNonBlocking -#define MAP_I2CFIFODataPutNonBlocking \ - ROM_I2CFIFODataPutNonBlocking -#else -#define MAP_I2CFIFODataPutNonBlocking \ - I2CFIFODataPutNonBlocking -#endif -#ifdef ROM_I2CFIFODataGet -#define MAP_I2CFIFODataGet \ - ROM_I2CFIFODataGet -#else -#define MAP_I2CFIFODataGet \ - I2CFIFODataGet -#endif -#ifdef ROM_I2CFIFODataGetNonBlocking -#define MAP_I2CFIFODataGetNonBlocking \ - ROM_I2CFIFODataGetNonBlocking -#else -#define MAP_I2CFIFODataGetNonBlocking \ - I2CFIFODataGetNonBlocking -#endif -#ifdef ROM_I2CMasterBurstLengthSet -#define MAP_I2CMasterBurstLengthSet \ - ROM_I2CMasterBurstLengthSet -#else -#define MAP_I2CMasterBurstLengthSet \ - I2CMasterBurstLengthSet -#endif -#ifdef ROM_I2CMasterBurstCountGet -#define MAP_I2CMasterBurstCountGet \ - ROM_I2CMasterBurstCountGet -#else -#define MAP_I2CMasterBurstCountGet \ - I2CMasterBurstCountGet -#endif -#ifdef ROM_I2CSlaveFIFODisable -#define MAP_I2CSlaveFIFODisable \ - ROM_I2CSlaveFIFODisable -#else -#define MAP_I2CSlaveFIFODisable \ - I2CSlaveFIFODisable -#endif -#ifdef ROM_I2CSlaveFIFOEnable -#define MAP_I2CSlaveFIFOEnable \ - ROM_I2CSlaveFIFOEnable -#else -#define MAP_I2CSlaveFIFOEnable \ - I2CSlaveFIFOEnable -#endif -#ifdef ROM_I2CMasterGlitchFilterConfigSet -#define MAP_I2CMasterGlitchFilterConfigSet \ - ROM_I2CMasterGlitchFilterConfigSet -#else -#define MAP_I2CMasterGlitchFilterConfigSet \ - I2CMasterGlitchFilterConfigSet -#endif - -//***************************************************************************** -// -// Macros for the Interrupt API. -// -//***************************************************************************** -#ifdef ROM_IntEnable -#define MAP_IntEnable \ - ROM_IntEnable -#else -#define MAP_IntEnable \ - IntEnable -#endif -#ifdef ROM_IntMasterEnable -#define MAP_IntMasterEnable \ - ROM_IntMasterEnable -#else -#define MAP_IntMasterEnable \ - IntMasterEnable -#endif -#ifdef ROM_IntMasterDisable -#define MAP_IntMasterDisable \ - ROM_IntMasterDisable -#else -#define MAP_IntMasterDisable \ - IntMasterDisable -#endif -#ifdef ROM_IntDisable -#define MAP_IntDisable \ - ROM_IntDisable -#else -#define MAP_IntDisable \ - IntDisable -#endif -#ifdef ROM_IntPriorityGroupingSet -#define MAP_IntPriorityGroupingSet \ - ROM_IntPriorityGroupingSet -#else -#define MAP_IntPriorityGroupingSet \ - IntPriorityGroupingSet -#endif -#ifdef ROM_IntPriorityGroupingGet -#define MAP_IntPriorityGroupingGet \ - ROM_IntPriorityGroupingGet -#else -#define MAP_IntPriorityGroupingGet \ - IntPriorityGroupingGet -#endif -#ifdef ROM_IntPrioritySet -#define MAP_IntPrioritySet \ - ROM_IntPrioritySet -#else -#define MAP_IntPrioritySet \ - IntPrioritySet -#endif -#ifdef ROM_IntPriorityGet -#define MAP_IntPriorityGet \ - ROM_IntPriorityGet -#else -#define MAP_IntPriorityGet \ - IntPriorityGet -#endif -#ifdef ROM_IntPendSet -#define MAP_IntPendSet \ - ROM_IntPendSet -#else -#define MAP_IntPendSet \ - IntPendSet -#endif -#ifdef ROM_IntPendClear -#define MAP_IntPendClear \ - ROM_IntPendClear -#else -#define MAP_IntPendClear \ - IntPendClear -#endif -#ifdef ROM_IntPriorityMaskSet -#define MAP_IntPriorityMaskSet \ - ROM_IntPriorityMaskSet -#else -#define MAP_IntPriorityMaskSet \ - IntPriorityMaskSet -#endif -#ifdef ROM_IntPriorityMaskGet -#define MAP_IntPriorityMaskGet \ - ROM_IntPriorityMaskGet -#else -#define MAP_IntPriorityMaskGet \ - IntPriorityMaskGet -#endif -#ifdef ROM_IntIsEnabled -#define MAP_IntIsEnabled \ - ROM_IntIsEnabled -#else -#define MAP_IntIsEnabled \ - IntIsEnabled -#endif -#ifdef ROM_IntTrigger -#define MAP_IntTrigger \ - ROM_IntTrigger -#else -#define MAP_IntTrigger \ - IntTrigger -#endif - -//***************************************************************************** -// -// Macros for the LCD API. -// -//***************************************************************************** -#ifdef ROM_LCDIntStatus -#define MAP_LCDIntStatus \ - ROM_LCDIntStatus -#else -#define MAP_LCDIntStatus \ - LCDIntStatus -#endif -#ifdef ROM_LCDClockReset -#define MAP_LCDClockReset \ - ROM_LCDClockReset -#else -#define MAP_LCDClockReset \ - LCDClockReset -#endif -#ifdef ROM_LCDDMAConfigSet -#define MAP_LCDDMAConfigSet \ - ROM_LCDDMAConfigSet -#else -#define MAP_LCDDMAConfigSet \ - LCDDMAConfigSet -#endif -#ifdef ROM_LCDIDDCommandWrite -#define MAP_LCDIDDCommandWrite \ - ROM_LCDIDDCommandWrite -#else -#define MAP_LCDIDDCommandWrite \ - LCDIDDCommandWrite -#endif -#ifdef ROM_LCDIDDConfigSet -#define MAP_LCDIDDConfigSet \ - ROM_LCDIDDConfigSet -#else -#define MAP_LCDIDDConfigSet \ - LCDIDDConfigSet -#endif -#ifdef ROM_LCDIDDDataRead -#define MAP_LCDIDDDataRead \ - ROM_LCDIDDDataRead -#else -#define MAP_LCDIDDDataRead \ - LCDIDDDataRead -#endif -#ifdef ROM_LCDIDDDataWrite -#define MAP_LCDIDDDataWrite \ - ROM_LCDIDDDataWrite -#else -#define MAP_LCDIDDDataWrite \ - LCDIDDDataWrite -#endif -#ifdef ROM_LCDIDDDMADisable -#define MAP_LCDIDDDMADisable \ - ROM_LCDIDDDMADisable -#else -#define MAP_LCDIDDDMADisable \ - LCDIDDDMADisable -#endif -#ifdef ROM_LCDIDDDMAWrite -#define MAP_LCDIDDDMAWrite \ - ROM_LCDIDDDMAWrite -#else -#define MAP_LCDIDDDMAWrite \ - LCDIDDDMAWrite -#endif -#ifdef ROM_LCDIDDIndexedRead -#define MAP_LCDIDDIndexedRead \ - ROM_LCDIDDIndexedRead -#else -#define MAP_LCDIDDIndexedRead \ - LCDIDDIndexedRead -#endif -#ifdef ROM_LCDIDDIndexedWrite -#define MAP_LCDIDDIndexedWrite \ - ROM_LCDIDDIndexedWrite -#else -#define MAP_LCDIDDIndexedWrite \ - LCDIDDIndexedWrite -#endif -#ifdef ROM_LCDIDDStatusRead -#define MAP_LCDIDDStatusRead \ - ROM_LCDIDDStatusRead -#else -#define MAP_LCDIDDStatusRead \ - LCDIDDStatusRead -#endif -#ifdef ROM_LCDIDDTimingSet -#define MAP_LCDIDDTimingSet \ - ROM_LCDIDDTimingSet -#else -#define MAP_LCDIDDTimingSet \ - LCDIDDTimingSet -#endif -#ifdef ROM_LCDIntClear -#define MAP_LCDIntClear \ - ROM_LCDIntClear -#else -#define MAP_LCDIntClear \ - LCDIntClear -#endif -#ifdef ROM_LCDIntDisable -#define MAP_LCDIntDisable \ - ROM_LCDIntDisable -#else -#define MAP_LCDIntDisable \ - LCDIntDisable -#endif -#ifdef ROM_LCDIntEnable -#define MAP_LCDIntEnable \ - ROM_LCDIntEnable -#else -#define MAP_LCDIntEnable \ - LCDIntEnable -#endif -#ifdef ROM_LCDModeSet -#define MAP_LCDModeSet \ - ROM_LCDModeSet -#else -#define MAP_LCDModeSet \ - LCDModeSet -#endif -#ifdef ROM_LCDRasterACBiasIntCountSet -#define MAP_LCDRasterACBiasIntCountSet \ - ROM_LCDRasterACBiasIntCountSet -#else -#define MAP_LCDRasterACBiasIntCountSet \ - LCDRasterACBiasIntCountSet -#endif -#ifdef ROM_LCDRasterConfigSet -#define MAP_LCDRasterConfigSet \ - ROM_LCDRasterConfigSet -#else -#define MAP_LCDRasterConfigSet \ - LCDRasterConfigSet -#endif -#ifdef ROM_LCDRasterDisable -#define MAP_LCDRasterDisable \ - ROM_LCDRasterDisable -#else -#define MAP_LCDRasterDisable \ - LCDRasterDisable -#endif -#ifdef ROM_LCDRasterEnable -#define MAP_LCDRasterEnable \ - ROM_LCDRasterEnable -#else -#define MAP_LCDRasterEnable \ - LCDRasterEnable -#endif -#ifdef ROM_LCDRasterFrameBufferSet -#define MAP_LCDRasterFrameBufferSet \ - ROM_LCDRasterFrameBufferSet -#else -#define MAP_LCDRasterFrameBufferSet \ - LCDRasterFrameBufferSet -#endif -#ifdef ROM_LCDRasterPaletteSet -#define MAP_LCDRasterPaletteSet \ - ROM_LCDRasterPaletteSet -#else -#define MAP_LCDRasterPaletteSet \ - LCDRasterPaletteSet -#endif -#ifdef ROM_LCDRasterSubPanelConfigSet -#define MAP_LCDRasterSubPanelConfigSet \ - ROM_LCDRasterSubPanelConfigSet -#else -#define MAP_LCDRasterSubPanelConfigSet \ - LCDRasterSubPanelConfigSet -#endif -#ifdef ROM_LCDRasterSubPanelDisable -#define MAP_LCDRasterSubPanelDisable \ - ROM_LCDRasterSubPanelDisable -#else -#define MAP_LCDRasterSubPanelDisable \ - LCDRasterSubPanelDisable -#endif -#ifdef ROM_LCDRasterSubPanelEnable -#define MAP_LCDRasterSubPanelEnable \ - ROM_LCDRasterSubPanelEnable -#else -#define MAP_LCDRasterSubPanelEnable \ - LCDRasterSubPanelEnable -#endif -#ifdef ROM_LCDRasterTimingSet -#define MAP_LCDRasterTimingSet \ - ROM_LCDRasterTimingSet -#else -#define MAP_LCDRasterTimingSet \ - LCDRasterTimingSet -#endif -#ifdef ROM_LCDRasterEnabled -#define MAP_LCDRasterEnabled \ - ROM_LCDRasterEnabled -#else -#define MAP_LCDRasterEnabled \ - LCDRasterEnabled -#endif - -//***************************************************************************** -// -// Macros for the MPU API. -// -//***************************************************************************** -#ifdef ROM_MPUEnable -#define MAP_MPUEnable \ - ROM_MPUEnable -#else -#define MAP_MPUEnable \ - MPUEnable -#endif -#ifdef ROM_MPUDisable -#define MAP_MPUDisable \ - ROM_MPUDisable -#else -#define MAP_MPUDisable \ - MPUDisable -#endif -#ifdef ROM_MPURegionCountGet -#define MAP_MPURegionCountGet \ - ROM_MPURegionCountGet -#else -#define MAP_MPURegionCountGet \ - MPURegionCountGet -#endif -#ifdef ROM_MPURegionEnable -#define MAP_MPURegionEnable \ - ROM_MPURegionEnable -#else -#define MAP_MPURegionEnable \ - MPURegionEnable -#endif -#ifdef ROM_MPURegionDisable -#define MAP_MPURegionDisable \ - ROM_MPURegionDisable -#else -#define MAP_MPURegionDisable \ - MPURegionDisable -#endif -#ifdef ROM_MPURegionSet -#define MAP_MPURegionSet \ - ROM_MPURegionSet -#else -#define MAP_MPURegionSet \ - MPURegionSet -#endif -#ifdef ROM_MPURegionGet -#define MAP_MPURegionGet \ - ROM_MPURegionGet -#else -#define MAP_MPURegionGet \ - MPURegionGet -#endif - -//***************************************************************************** -// -// Macros for the OneWire API. -// -//***************************************************************************** -#ifdef ROM_OneWireIntStatus -#define MAP_OneWireIntStatus \ - ROM_OneWireIntStatus -#else -#define MAP_OneWireIntStatus \ - OneWireIntStatus -#endif -#ifdef ROM_OneWireBusReset -#define MAP_OneWireBusReset \ - ROM_OneWireBusReset -#else -#define MAP_OneWireBusReset \ - OneWireBusReset -#endif -#ifdef ROM_OneWireBusStatus -#define MAP_OneWireBusStatus \ - ROM_OneWireBusStatus -#else -#define MAP_OneWireBusStatus \ - OneWireBusStatus -#endif -#ifdef ROM_OneWireDataGet -#define MAP_OneWireDataGet \ - ROM_OneWireDataGet -#else -#define MAP_OneWireDataGet \ - OneWireDataGet -#endif -#ifdef ROM_OneWireDataGetNonBlocking -#define MAP_OneWireDataGetNonBlocking \ - ROM_OneWireDataGetNonBlocking -#else -#define MAP_OneWireDataGetNonBlocking \ - OneWireDataGetNonBlocking -#endif -#ifdef ROM_OneWireInit -#define MAP_OneWireInit \ - ROM_OneWireInit -#else -#define MAP_OneWireInit \ - OneWireInit -#endif -#ifdef ROM_OneWireIntClear -#define MAP_OneWireIntClear \ - ROM_OneWireIntClear -#else -#define MAP_OneWireIntClear \ - OneWireIntClear -#endif -#ifdef ROM_OneWireIntDisable -#define MAP_OneWireIntDisable \ - ROM_OneWireIntDisable -#else -#define MAP_OneWireIntDisable \ - OneWireIntDisable -#endif -#ifdef ROM_OneWireIntEnable -#define MAP_OneWireIntEnable \ - ROM_OneWireIntEnable -#else -#define MAP_OneWireIntEnable \ - OneWireIntEnable -#endif -#ifdef ROM_OneWireTransaction -#define MAP_OneWireTransaction \ - ROM_OneWireTransaction -#else -#define MAP_OneWireTransaction \ - OneWireTransaction -#endif -#ifdef ROM_OneWireDMADisable -#define MAP_OneWireDMADisable \ - ROM_OneWireDMADisable -#else -#define MAP_OneWireDMADisable \ - OneWireDMADisable -#endif -#ifdef ROM_OneWireDMAEnable -#define MAP_OneWireDMAEnable \ - ROM_OneWireDMAEnable -#else -#define MAP_OneWireDMAEnable \ - OneWireDMAEnable -#endif - -//***************************************************************************** -// -// Macros for the PWM API. -// -//***************************************************************************** -#ifdef ROM_PWMPulseWidthSet -#define MAP_PWMPulseWidthSet \ - ROM_PWMPulseWidthSet -#else -#define MAP_PWMPulseWidthSet \ - PWMPulseWidthSet -#endif -#ifdef ROM_PWMGenConfigure -#define MAP_PWMGenConfigure \ - ROM_PWMGenConfigure -#else -#define MAP_PWMGenConfigure \ - PWMGenConfigure -#endif -#ifdef ROM_PWMGenPeriodSet -#define MAP_PWMGenPeriodSet \ - ROM_PWMGenPeriodSet -#else -#define MAP_PWMGenPeriodSet \ - PWMGenPeriodSet -#endif -#ifdef ROM_PWMGenPeriodGet -#define MAP_PWMGenPeriodGet \ - ROM_PWMGenPeriodGet -#else -#define MAP_PWMGenPeriodGet \ - PWMGenPeriodGet -#endif -#ifdef ROM_PWMGenEnable -#define MAP_PWMGenEnable \ - ROM_PWMGenEnable -#else -#define MAP_PWMGenEnable \ - PWMGenEnable -#endif -#ifdef ROM_PWMGenDisable -#define MAP_PWMGenDisable \ - ROM_PWMGenDisable -#else -#define MAP_PWMGenDisable \ - PWMGenDisable -#endif -#ifdef ROM_PWMPulseWidthGet -#define MAP_PWMPulseWidthGet \ - ROM_PWMPulseWidthGet -#else -#define MAP_PWMPulseWidthGet \ - PWMPulseWidthGet -#endif -#ifdef ROM_PWMDeadBandEnable -#define MAP_PWMDeadBandEnable \ - ROM_PWMDeadBandEnable -#else -#define MAP_PWMDeadBandEnable \ - PWMDeadBandEnable -#endif -#ifdef ROM_PWMDeadBandDisable -#define MAP_PWMDeadBandDisable \ - ROM_PWMDeadBandDisable -#else -#define MAP_PWMDeadBandDisable \ - PWMDeadBandDisable -#endif -#ifdef ROM_PWMSyncUpdate -#define MAP_PWMSyncUpdate \ - ROM_PWMSyncUpdate -#else -#define MAP_PWMSyncUpdate \ - PWMSyncUpdate -#endif -#ifdef ROM_PWMSyncTimeBase -#define MAP_PWMSyncTimeBase \ - ROM_PWMSyncTimeBase -#else -#define MAP_PWMSyncTimeBase \ - PWMSyncTimeBase -#endif -#ifdef ROM_PWMOutputState -#define MAP_PWMOutputState \ - ROM_PWMOutputState -#else -#define MAP_PWMOutputState \ - PWMOutputState -#endif -#ifdef ROM_PWMOutputInvert -#define MAP_PWMOutputInvert \ - ROM_PWMOutputInvert -#else -#define MAP_PWMOutputInvert \ - PWMOutputInvert -#endif -#ifdef ROM_PWMOutputFault -#define MAP_PWMOutputFault \ - ROM_PWMOutputFault -#else -#define MAP_PWMOutputFault \ - PWMOutputFault -#endif -#ifdef ROM_PWMGenIntTrigEnable -#define MAP_PWMGenIntTrigEnable \ - ROM_PWMGenIntTrigEnable -#else -#define MAP_PWMGenIntTrigEnable \ - PWMGenIntTrigEnable -#endif -#ifdef ROM_PWMGenIntTrigDisable -#define MAP_PWMGenIntTrigDisable \ - ROM_PWMGenIntTrigDisable -#else -#define MAP_PWMGenIntTrigDisable \ - PWMGenIntTrigDisable -#endif -#ifdef ROM_PWMGenIntStatus -#define MAP_PWMGenIntStatus \ - ROM_PWMGenIntStatus -#else -#define MAP_PWMGenIntStatus \ - PWMGenIntStatus -#endif -#ifdef ROM_PWMGenIntClear -#define MAP_PWMGenIntClear \ - ROM_PWMGenIntClear -#else -#define MAP_PWMGenIntClear \ - PWMGenIntClear -#endif -#ifdef ROM_PWMIntEnable -#define MAP_PWMIntEnable \ - ROM_PWMIntEnable -#else -#define MAP_PWMIntEnable \ - PWMIntEnable -#endif -#ifdef ROM_PWMIntDisable -#define MAP_PWMIntDisable \ - ROM_PWMIntDisable -#else -#define MAP_PWMIntDisable \ - PWMIntDisable -#endif -#ifdef ROM_PWMFaultIntClear -#define MAP_PWMFaultIntClear \ - ROM_PWMFaultIntClear -#else -#define MAP_PWMFaultIntClear \ - PWMFaultIntClear -#endif -#ifdef ROM_PWMIntStatus -#define MAP_PWMIntStatus \ - ROM_PWMIntStatus -#else -#define MAP_PWMIntStatus \ - PWMIntStatus -#endif -#ifdef ROM_PWMOutputFaultLevel -#define MAP_PWMOutputFaultLevel \ - ROM_PWMOutputFaultLevel -#else -#define MAP_PWMOutputFaultLevel \ - PWMOutputFaultLevel -#endif -#ifdef ROM_PWMFaultIntClearExt -#define MAP_PWMFaultIntClearExt \ - ROM_PWMFaultIntClearExt -#else -#define MAP_PWMFaultIntClearExt \ - PWMFaultIntClearExt -#endif -#ifdef ROM_PWMGenFaultConfigure -#define MAP_PWMGenFaultConfigure \ - ROM_PWMGenFaultConfigure -#else -#define MAP_PWMGenFaultConfigure \ - PWMGenFaultConfigure -#endif -#ifdef ROM_PWMGenFaultTriggerSet -#define MAP_PWMGenFaultTriggerSet \ - ROM_PWMGenFaultTriggerSet -#else -#define MAP_PWMGenFaultTriggerSet \ - PWMGenFaultTriggerSet -#endif -#ifdef ROM_PWMGenFaultTriggerGet -#define MAP_PWMGenFaultTriggerGet \ - ROM_PWMGenFaultTriggerGet -#else -#define MAP_PWMGenFaultTriggerGet \ - PWMGenFaultTriggerGet -#endif -#ifdef ROM_PWMGenFaultStatus -#define MAP_PWMGenFaultStatus \ - ROM_PWMGenFaultStatus -#else -#define MAP_PWMGenFaultStatus \ - PWMGenFaultStatus -#endif -#ifdef ROM_PWMGenFaultClear -#define MAP_PWMGenFaultClear \ - ROM_PWMGenFaultClear -#else -#define MAP_PWMGenFaultClear \ - PWMGenFaultClear -#endif -#ifdef ROM_PWMClockSet -#define MAP_PWMClockSet \ - ROM_PWMClockSet -#else -#define MAP_PWMClockSet \ - PWMClockSet -#endif -#ifdef ROM_PWMClockGet -#define MAP_PWMClockGet \ - ROM_PWMClockGet -#else -#define MAP_PWMClockGet \ - PWMClockGet -#endif -#ifdef ROM_PWMOutputUpdateMode -#define MAP_PWMOutputUpdateMode \ - ROM_PWMOutputUpdateMode -#else -#define MAP_PWMOutputUpdateMode \ - PWMOutputUpdateMode -#endif - -//***************************************************************************** -// -// Macros for the QEI API. -// -//***************************************************************************** -#ifdef ROM_QEIPositionGet -#define MAP_QEIPositionGet \ - ROM_QEIPositionGet -#else -#define MAP_QEIPositionGet \ - QEIPositionGet -#endif -#ifdef ROM_QEIEnable -#define MAP_QEIEnable \ - ROM_QEIEnable -#else -#define MAP_QEIEnable \ - QEIEnable -#endif -#ifdef ROM_QEIDisable -#define MAP_QEIDisable \ - ROM_QEIDisable -#else -#define MAP_QEIDisable \ - QEIDisable -#endif -#ifdef ROM_QEIConfigure -#define MAP_QEIConfigure \ - ROM_QEIConfigure -#else -#define MAP_QEIConfigure \ - QEIConfigure -#endif -#ifdef ROM_QEIPositionSet -#define MAP_QEIPositionSet \ - ROM_QEIPositionSet -#else -#define MAP_QEIPositionSet \ - QEIPositionSet -#endif -#ifdef ROM_QEIDirectionGet -#define MAP_QEIDirectionGet \ - ROM_QEIDirectionGet -#else -#define MAP_QEIDirectionGet \ - QEIDirectionGet -#endif -#ifdef ROM_QEIErrorGet -#define MAP_QEIErrorGet \ - ROM_QEIErrorGet -#else -#define MAP_QEIErrorGet \ - QEIErrorGet -#endif -#ifdef ROM_QEIVelocityEnable -#define MAP_QEIVelocityEnable \ - ROM_QEIVelocityEnable -#else -#define MAP_QEIVelocityEnable \ - QEIVelocityEnable -#endif -#ifdef ROM_QEIVelocityDisable -#define MAP_QEIVelocityDisable \ - ROM_QEIVelocityDisable -#else -#define MAP_QEIVelocityDisable \ - QEIVelocityDisable -#endif -#ifdef ROM_QEIVelocityConfigure -#define MAP_QEIVelocityConfigure \ - ROM_QEIVelocityConfigure -#else -#define MAP_QEIVelocityConfigure \ - QEIVelocityConfigure -#endif -#ifdef ROM_QEIVelocityGet -#define MAP_QEIVelocityGet \ - ROM_QEIVelocityGet -#else -#define MAP_QEIVelocityGet \ - QEIVelocityGet -#endif -#ifdef ROM_QEIIntEnable -#define MAP_QEIIntEnable \ - ROM_QEIIntEnable -#else -#define MAP_QEIIntEnable \ - QEIIntEnable -#endif -#ifdef ROM_QEIIntDisable -#define MAP_QEIIntDisable \ - ROM_QEIIntDisable -#else -#define MAP_QEIIntDisable \ - QEIIntDisable -#endif -#ifdef ROM_QEIIntStatus -#define MAP_QEIIntStatus \ - ROM_QEIIntStatus -#else -#define MAP_QEIIntStatus \ - QEIIntStatus -#endif -#ifdef ROM_QEIIntClear -#define MAP_QEIIntClear \ - ROM_QEIIntClear -#else -#define MAP_QEIIntClear \ - QEIIntClear -#endif - -//***************************************************************************** -// -// Macros for the SHAMD5 API. -// -//***************************************************************************** -#ifdef ROM_SHAMD5IntStatus -#define MAP_SHAMD5IntStatus \ - ROM_SHAMD5IntStatus -#else -#define MAP_SHAMD5IntStatus \ - SHAMD5IntStatus -#endif -#ifdef ROM_SHAMD5ConfigSet -#define MAP_SHAMD5ConfigSet \ - ROM_SHAMD5ConfigSet -#else -#define MAP_SHAMD5ConfigSet \ - SHAMD5ConfigSet -#endif -#ifdef ROM_SHAMD5DataProcess -#define MAP_SHAMD5DataProcess \ - ROM_SHAMD5DataProcess -#else -#define MAP_SHAMD5DataProcess \ - SHAMD5DataProcess -#endif -#ifdef ROM_SHAMD5DataWrite -#define MAP_SHAMD5DataWrite \ - ROM_SHAMD5DataWrite -#else -#define MAP_SHAMD5DataWrite \ - SHAMD5DataWrite -#endif -#ifdef ROM_SHAMD5DataWriteNonBlocking -#define MAP_SHAMD5DataWriteNonBlocking \ - ROM_SHAMD5DataWriteNonBlocking -#else -#define MAP_SHAMD5DataWriteNonBlocking \ - SHAMD5DataWriteNonBlocking -#endif -#ifdef ROM_SHAMD5DMADisable -#define MAP_SHAMD5DMADisable \ - ROM_SHAMD5DMADisable -#else -#define MAP_SHAMD5DMADisable \ - SHAMD5DMADisable -#endif -#ifdef ROM_SHAMD5DMAEnable -#define MAP_SHAMD5DMAEnable \ - ROM_SHAMD5DMAEnable -#else -#define MAP_SHAMD5DMAEnable \ - SHAMD5DMAEnable -#endif -#ifdef ROM_SHAMD5HashLengthSet -#define MAP_SHAMD5HashLengthSet \ - ROM_SHAMD5HashLengthSet -#else -#define MAP_SHAMD5HashLengthSet \ - SHAMD5HashLengthSet -#endif -#ifdef ROM_SHAMD5HMACKeySet -#define MAP_SHAMD5HMACKeySet \ - ROM_SHAMD5HMACKeySet -#else -#define MAP_SHAMD5HMACKeySet \ - SHAMD5HMACKeySet -#endif -#ifdef ROM_SHAMD5HMACPPKeyGenerate -#define MAP_SHAMD5HMACPPKeyGenerate \ - ROM_SHAMD5HMACPPKeyGenerate -#else -#define MAP_SHAMD5HMACPPKeyGenerate \ - SHAMD5HMACPPKeyGenerate -#endif -#ifdef ROM_SHAMD5HMACPPKeySet -#define MAP_SHAMD5HMACPPKeySet \ - ROM_SHAMD5HMACPPKeySet -#else -#define MAP_SHAMD5HMACPPKeySet \ - SHAMD5HMACPPKeySet -#endif -#ifdef ROM_SHAMD5HMACProcess -#define MAP_SHAMD5HMACProcess \ - ROM_SHAMD5HMACProcess -#else -#define MAP_SHAMD5HMACProcess \ - SHAMD5HMACProcess -#endif -#ifdef ROM_SHAMD5IntClear -#define MAP_SHAMD5IntClear \ - ROM_SHAMD5IntClear -#else -#define MAP_SHAMD5IntClear \ - SHAMD5IntClear -#endif -#ifdef ROM_SHAMD5IntDisable -#define MAP_SHAMD5IntDisable \ - ROM_SHAMD5IntDisable -#else -#define MAP_SHAMD5IntDisable \ - SHAMD5IntDisable -#endif -#ifdef ROM_SHAMD5IntEnable -#define MAP_SHAMD5IntEnable \ - ROM_SHAMD5IntEnable -#else -#define MAP_SHAMD5IntEnable \ - SHAMD5IntEnable -#endif -#ifdef ROM_SHAMD5Reset -#define MAP_SHAMD5Reset \ - ROM_SHAMD5Reset -#else -#define MAP_SHAMD5Reset \ - SHAMD5Reset -#endif -#ifdef ROM_SHAMD5ResultRead -#define MAP_SHAMD5ResultRead \ - ROM_SHAMD5ResultRead -#else -#define MAP_SHAMD5ResultRead \ - SHAMD5ResultRead -#endif - -//***************************************************************************** -// -// Macros for the SMBus API. -// -//***************************************************************************** -#ifdef ROM_SMBusMasterIntProcess -#define MAP_SMBusMasterIntProcess \ - ROM_SMBusMasterIntProcess -#else -#define MAP_SMBusMasterIntProcess \ - SMBusMasterIntProcess -#endif -#ifdef ROM_SMBusARPDisable -#define MAP_SMBusARPDisable \ - ROM_SMBusARPDisable -#else -#define MAP_SMBusARPDisable \ - SMBusARPDisable -#endif -#ifdef ROM_SMBusARPEnable -#define MAP_SMBusARPEnable \ - ROM_SMBusARPEnable -#else -#define MAP_SMBusARPEnable \ - SMBusARPEnable -#endif -#ifdef ROM_SMBusARPUDIDPacketDecode -#define MAP_SMBusARPUDIDPacketDecode \ - ROM_SMBusARPUDIDPacketDecode -#else -#define MAP_SMBusARPUDIDPacketDecode \ - SMBusARPUDIDPacketDecode -#endif -#ifdef ROM_SMBusARPUDIDPacketEncode -#define MAP_SMBusARPUDIDPacketEncode \ - ROM_SMBusARPUDIDPacketEncode -#else -#define MAP_SMBusARPUDIDPacketEncode \ - SMBusARPUDIDPacketEncode -#endif -#ifdef ROM_SMBusMasterARPAssignAddress -#define MAP_SMBusMasterARPAssignAddress \ - ROM_SMBusMasterARPAssignAddress -#else -#define MAP_SMBusMasterARPAssignAddress \ - SMBusMasterARPAssignAddress -#endif -#ifdef ROM_SMBusMasterARPGetUDIDDir -#define MAP_SMBusMasterARPGetUDIDDir \ - ROM_SMBusMasterARPGetUDIDDir -#else -#define MAP_SMBusMasterARPGetUDIDDir \ - SMBusMasterARPGetUDIDDir -#endif -#ifdef ROM_SMBusMasterARPGetUDIDGen -#define MAP_SMBusMasterARPGetUDIDGen \ - ROM_SMBusMasterARPGetUDIDGen -#else -#define MAP_SMBusMasterARPGetUDIDGen \ - SMBusMasterARPGetUDIDGen -#endif -#ifdef ROM_SMBusMasterARPNotifyMaster -#define MAP_SMBusMasterARPNotifyMaster \ - ROM_SMBusMasterARPNotifyMaster -#else -#define MAP_SMBusMasterARPNotifyMaster \ - SMBusMasterARPNotifyMaster -#endif -#ifdef ROM_SMBusMasterARPPrepareToARP -#define MAP_SMBusMasterARPPrepareToARP \ - ROM_SMBusMasterARPPrepareToARP -#else -#define MAP_SMBusMasterARPPrepareToARP \ - SMBusMasterARPPrepareToARP -#endif -#ifdef ROM_SMBusMasterARPResetDeviceDir -#define MAP_SMBusMasterARPResetDeviceDir \ - ROM_SMBusMasterARPResetDeviceDir -#else -#define MAP_SMBusMasterARPResetDeviceDir \ - SMBusMasterARPResetDeviceDir -#endif -#ifdef ROM_SMBusMasterARPResetDeviceGen -#define MAP_SMBusMasterARPResetDeviceGen \ - ROM_SMBusMasterARPResetDeviceGen -#else -#define MAP_SMBusMasterARPResetDeviceGen \ - SMBusMasterARPResetDeviceGen -#endif -#ifdef ROM_SMBusMasterBlockProcessCall -#define MAP_SMBusMasterBlockProcessCall \ - ROM_SMBusMasterBlockProcessCall -#else -#define MAP_SMBusMasterBlockProcessCall \ - SMBusMasterBlockProcessCall -#endif -#ifdef ROM_SMBusMasterBlockRead -#define MAP_SMBusMasterBlockRead \ - ROM_SMBusMasterBlockRead -#else -#define MAP_SMBusMasterBlockRead \ - SMBusMasterBlockRead -#endif -#ifdef ROM_SMBusMasterBlockWrite -#define MAP_SMBusMasterBlockWrite \ - ROM_SMBusMasterBlockWrite -#else -#define MAP_SMBusMasterBlockWrite \ - SMBusMasterBlockWrite -#endif -#ifdef ROM_SMBusMasterByteReceive -#define MAP_SMBusMasterByteReceive \ - ROM_SMBusMasterByteReceive -#else -#define MAP_SMBusMasterByteReceive \ - SMBusMasterByteReceive -#endif -#ifdef ROM_SMBusMasterByteSend -#define MAP_SMBusMasterByteSend \ - ROM_SMBusMasterByteSend -#else -#define MAP_SMBusMasterByteSend \ - SMBusMasterByteSend -#endif -#ifdef ROM_SMBusMasterByteWordRead -#define MAP_SMBusMasterByteWordRead \ - ROM_SMBusMasterByteWordRead -#else -#define MAP_SMBusMasterByteWordRead \ - SMBusMasterByteWordRead -#endif -#ifdef ROM_SMBusMasterByteWordWrite -#define MAP_SMBusMasterByteWordWrite \ - ROM_SMBusMasterByteWordWrite -#else -#define MAP_SMBusMasterByteWordWrite \ - SMBusMasterByteWordWrite -#endif -#ifdef ROM_SMBusMasterHostNotify -#define MAP_SMBusMasterHostNotify \ - ROM_SMBusMasterHostNotify -#else -#define MAP_SMBusMasterHostNotify \ - SMBusMasterHostNotify -#endif -#ifdef ROM_SMBusMasterI2CRead -#define MAP_SMBusMasterI2CRead \ - ROM_SMBusMasterI2CRead -#else -#define MAP_SMBusMasterI2CRead \ - SMBusMasterI2CRead -#endif -#ifdef ROM_SMBusMasterI2CWrite -#define MAP_SMBusMasterI2CWrite \ - ROM_SMBusMasterI2CWrite -#else -#define MAP_SMBusMasterI2CWrite \ - SMBusMasterI2CWrite -#endif -#ifdef ROM_SMBusMasterI2CWriteRead -#define MAP_SMBusMasterI2CWriteRead \ - ROM_SMBusMasterI2CWriteRead -#else -#define MAP_SMBusMasterI2CWriteRead \ - SMBusMasterI2CWriteRead -#endif -#ifdef ROM_SMBusMasterInit -#define MAP_SMBusMasterInit \ - ROM_SMBusMasterInit -#else -#define MAP_SMBusMasterInit \ - SMBusMasterInit -#endif -#ifdef ROM_SMBusMasterIntEnable -#define MAP_SMBusMasterIntEnable \ - ROM_SMBusMasterIntEnable -#else -#define MAP_SMBusMasterIntEnable \ - SMBusMasterIntEnable -#endif -#ifdef ROM_SMBusMasterProcessCall -#define MAP_SMBusMasterProcessCall \ - ROM_SMBusMasterProcessCall -#else -#define MAP_SMBusMasterProcessCall \ - SMBusMasterProcessCall -#endif -#ifdef ROM_SMBusMasterQuickCommand -#define MAP_SMBusMasterQuickCommand \ - ROM_SMBusMasterQuickCommand -#else -#define MAP_SMBusMasterQuickCommand \ - SMBusMasterQuickCommand -#endif -#ifdef ROM_SMBusPECDisable -#define MAP_SMBusPECDisable \ - ROM_SMBusPECDisable -#else -#define MAP_SMBusPECDisable \ - SMBusPECDisable -#endif -#ifdef ROM_SMBusPECEnable -#define MAP_SMBusPECEnable \ - ROM_SMBusPECEnable -#else -#define MAP_SMBusPECEnable \ - SMBusPECEnable -#endif -#ifdef ROM_SMBusRxPacketSizeGet -#define MAP_SMBusRxPacketSizeGet \ - ROM_SMBusRxPacketSizeGet -#else -#define MAP_SMBusRxPacketSizeGet \ - SMBusRxPacketSizeGet -#endif -#ifdef ROM_SMBusSlaveACKSend -#define MAP_SMBusSlaveACKSend \ - ROM_SMBusSlaveACKSend -#else -#define MAP_SMBusSlaveACKSend \ - SMBusSlaveACKSend -#endif -#ifdef ROM_SMBusSlaveAddressSet -#define MAP_SMBusSlaveAddressSet \ - ROM_SMBusSlaveAddressSet -#else -#define MAP_SMBusSlaveAddressSet \ - SMBusSlaveAddressSet -#endif -#ifdef ROM_SMBusSlaveARPFlagARGet -#define MAP_SMBusSlaveARPFlagARGet \ - ROM_SMBusSlaveARPFlagARGet -#else -#define MAP_SMBusSlaveARPFlagARGet \ - SMBusSlaveARPFlagARGet -#endif -#ifdef ROM_SMBusSlaveARPFlagARSet -#define MAP_SMBusSlaveARPFlagARSet \ - ROM_SMBusSlaveARPFlagARSet -#else -#define MAP_SMBusSlaveARPFlagARSet \ - SMBusSlaveARPFlagARSet -#endif -#ifdef ROM_SMBusSlaveARPFlagAVGet -#define MAP_SMBusSlaveARPFlagAVGet \ - ROM_SMBusSlaveARPFlagAVGet -#else -#define MAP_SMBusSlaveARPFlagAVGet \ - SMBusSlaveARPFlagAVGet -#endif -#ifdef ROM_SMBusSlaveARPFlagAVSet -#define MAP_SMBusSlaveARPFlagAVSet \ - ROM_SMBusSlaveARPFlagAVSet -#else -#define MAP_SMBusSlaveARPFlagAVSet \ - SMBusSlaveARPFlagAVSet -#endif -#ifdef ROM_SMBusSlaveBlockTransferDisable -#define MAP_SMBusSlaveBlockTransferDisable \ - ROM_SMBusSlaveBlockTransferDisable -#else -#define MAP_SMBusSlaveBlockTransferDisable \ - SMBusSlaveBlockTransferDisable -#endif -#ifdef ROM_SMBusSlaveBlockTransferEnable -#define MAP_SMBusSlaveBlockTransferEnable \ - ROM_SMBusSlaveBlockTransferEnable -#else -#define MAP_SMBusSlaveBlockTransferEnable \ - SMBusSlaveBlockTransferEnable -#endif -#ifdef ROM_SMBusSlaveCommandGet -#define MAP_SMBusSlaveCommandGet \ - ROM_SMBusSlaveCommandGet -#else -#define MAP_SMBusSlaveCommandGet \ - SMBusSlaveCommandGet -#endif -#ifdef ROM_SMBusSlaveI2CDisable -#define MAP_SMBusSlaveI2CDisable \ - ROM_SMBusSlaveI2CDisable -#else -#define MAP_SMBusSlaveI2CDisable \ - SMBusSlaveI2CDisable -#endif -#ifdef ROM_SMBusSlaveI2CEnable -#define MAP_SMBusSlaveI2CEnable \ - ROM_SMBusSlaveI2CEnable -#else -#define MAP_SMBusSlaveI2CEnable \ - SMBusSlaveI2CEnable -#endif -#ifdef ROM_SMBusSlaveInit -#define MAP_SMBusSlaveInit \ - ROM_SMBusSlaveInit -#else -#define MAP_SMBusSlaveInit \ - SMBusSlaveInit -#endif -#ifdef ROM_SMBusSlaveIntAddressGet -#define MAP_SMBusSlaveIntAddressGet \ - ROM_SMBusSlaveIntAddressGet -#else -#define MAP_SMBusSlaveIntAddressGet \ - SMBusSlaveIntAddressGet -#endif -#ifdef ROM_SMBusSlaveIntEnable -#define MAP_SMBusSlaveIntEnable \ - ROM_SMBusSlaveIntEnable -#else -#define MAP_SMBusSlaveIntEnable \ - SMBusSlaveIntEnable -#endif -#ifdef ROM_SMBusSlaveIntProcess -#define MAP_SMBusSlaveIntProcess \ - ROM_SMBusSlaveIntProcess -#else -#define MAP_SMBusSlaveIntProcess \ - SMBusSlaveIntProcess -#endif -#ifdef ROM_SMBusSlaveManualACKDisable -#define MAP_SMBusSlaveManualACKDisable \ - ROM_SMBusSlaveManualACKDisable -#else -#define MAP_SMBusSlaveManualACKDisable \ - SMBusSlaveManualACKDisable -#endif -#ifdef ROM_SMBusSlaveManualACKEnable -#define MAP_SMBusSlaveManualACKEnable \ - ROM_SMBusSlaveManualACKEnable -#else -#define MAP_SMBusSlaveManualACKEnable \ - SMBusSlaveManualACKEnable -#endif -#ifdef ROM_SMBusSlaveManualACKStatusGet -#define MAP_SMBusSlaveManualACKStatusGet \ - ROM_SMBusSlaveManualACKStatusGet -#else -#define MAP_SMBusSlaveManualACKStatusGet \ - SMBusSlaveManualACKStatusGet -#endif -#ifdef ROM_SMBusSlaveProcessCallDisable -#define MAP_SMBusSlaveProcessCallDisable \ - ROM_SMBusSlaveProcessCallDisable -#else -#define MAP_SMBusSlaveProcessCallDisable \ - SMBusSlaveProcessCallDisable -#endif -#ifdef ROM_SMBusSlaveProcessCallEnable -#define MAP_SMBusSlaveProcessCallEnable \ - ROM_SMBusSlaveProcessCallEnable -#else -#define MAP_SMBusSlaveProcessCallEnable \ - SMBusSlaveProcessCallEnable -#endif -#ifdef ROM_SMBusSlaveRxBufferSet -#define MAP_SMBusSlaveRxBufferSet \ - ROM_SMBusSlaveRxBufferSet -#else -#define MAP_SMBusSlaveRxBufferSet \ - SMBusSlaveRxBufferSet -#endif -#ifdef ROM_SMBusSlaveTransferInit -#define MAP_SMBusSlaveTransferInit \ - ROM_SMBusSlaveTransferInit -#else -#define MAP_SMBusSlaveTransferInit \ - SMBusSlaveTransferInit -#endif -#ifdef ROM_SMBusSlaveTxBufferSet -#define MAP_SMBusSlaveTxBufferSet \ - ROM_SMBusSlaveTxBufferSet -#else -#define MAP_SMBusSlaveTxBufferSet \ - SMBusSlaveTxBufferSet -#endif -#ifdef ROM_SMBusSlaveUDIDSet -#define MAP_SMBusSlaveUDIDSet \ - ROM_SMBusSlaveUDIDSet -#else -#define MAP_SMBusSlaveUDIDSet \ - SMBusSlaveUDIDSet -#endif -#ifdef ROM_SMBusStatusGet -#define MAP_SMBusStatusGet \ - ROM_SMBusStatusGet -#else -#define MAP_SMBusStatusGet \ - SMBusStatusGet -#endif -#ifdef ROM_SMBusSlaveDataSend -#define MAP_SMBusSlaveDataSend \ - ROM_SMBusSlaveDataSend -#else -#define MAP_SMBusSlaveDataSend \ - SMBusSlaveDataSend -#endif -#ifdef ROM_SMBusFIFOEnable -#define MAP_SMBusFIFOEnable \ - ROM_SMBusFIFOEnable -#else -#define MAP_SMBusFIFOEnable \ - SMBusFIFOEnable -#endif -#ifdef ROM_SMBusFIFODisable -#define MAP_SMBusFIFODisable \ - ROM_SMBusFIFODisable -#else -#define MAP_SMBusFIFODisable \ - SMBusFIFODisable -#endif -#ifdef ROM_SMBusDMAEnable -#define MAP_SMBusDMAEnable \ - ROM_SMBusDMAEnable -#else -#define MAP_SMBusDMAEnable \ - SMBusDMAEnable -#endif -#ifdef ROM_SMBusDMADisable -#define MAP_SMBusDMADisable \ - ROM_SMBusDMADisable -#else -#define MAP_SMBusDMADisable \ - SMBusDMADisable -#endif - -//***************************************************************************** -// -// Macros for the SPIFlash API. -// -//***************************************************************************** -#ifdef ROM_SPIFlashIntHandler -#define MAP_SPIFlashIntHandler \ - ROM_SPIFlashIntHandler -#else -#define MAP_SPIFlashIntHandler \ - SPIFlashIntHandler -#endif -#ifdef ROM_SPIFlashInit -#define MAP_SPIFlashInit \ - ROM_SPIFlashInit -#else -#define MAP_SPIFlashInit \ - SPIFlashInit -#endif -#ifdef ROM_SPIFlashWriteStatus -#define MAP_SPIFlashWriteStatus \ - ROM_SPIFlashWriteStatus -#else -#define MAP_SPIFlashWriteStatus \ - SPIFlashWriteStatus -#endif -#ifdef ROM_SPIFlashPageProgram -#define MAP_SPIFlashPageProgram \ - ROM_SPIFlashPageProgram -#else -#define MAP_SPIFlashPageProgram \ - SPIFlashPageProgram -#endif -#ifdef ROM_SPIFlashPageProgramNonBlocking -#define MAP_SPIFlashPageProgramNonBlocking \ - ROM_SPIFlashPageProgramNonBlocking -#else -#define MAP_SPIFlashPageProgramNonBlocking \ - SPIFlashPageProgramNonBlocking -#endif -#ifdef ROM_SPIFlashRead -#define MAP_SPIFlashRead \ - ROM_SPIFlashRead -#else -#define MAP_SPIFlashRead \ - SPIFlashRead -#endif -#ifdef ROM_SPIFlashReadNonBlocking -#define MAP_SPIFlashReadNonBlocking \ - ROM_SPIFlashReadNonBlocking -#else -#define MAP_SPIFlashReadNonBlocking \ - SPIFlashReadNonBlocking -#endif -#ifdef ROM_SPIFlashWriteDisable -#define MAP_SPIFlashWriteDisable \ - ROM_SPIFlashWriteDisable -#else -#define MAP_SPIFlashWriteDisable \ - SPIFlashWriteDisable -#endif -#ifdef ROM_SPIFlashReadStatus -#define MAP_SPIFlashReadStatus \ - ROM_SPIFlashReadStatus -#else -#define MAP_SPIFlashReadStatus \ - SPIFlashReadStatus -#endif -#ifdef ROM_SPIFlashWriteEnable -#define MAP_SPIFlashWriteEnable \ - ROM_SPIFlashWriteEnable -#else -#define MAP_SPIFlashWriteEnable \ - SPIFlashWriteEnable -#endif -#ifdef ROM_SPIFlashFastRead -#define MAP_SPIFlashFastRead \ - ROM_SPIFlashFastRead -#else -#define MAP_SPIFlashFastRead \ - SPIFlashFastRead -#endif -#ifdef ROM_SPIFlashFastReadNonBlocking -#define MAP_SPIFlashFastReadNonBlocking \ - ROM_SPIFlashFastReadNonBlocking -#else -#define MAP_SPIFlashFastReadNonBlocking \ - SPIFlashFastReadNonBlocking -#endif -#ifdef ROM_SPIFlashSectorErase -#define MAP_SPIFlashSectorErase \ - ROM_SPIFlashSectorErase -#else -#define MAP_SPIFlashSectorErase \ - SPIFlashSectorErase -#endif -#ifdef ROM_SPIFlashDualRead -#define MAP_SPIFlashDualRead \ - ROM_SPIFlashDualRead -#else -#define MAP_SPIFlashDualRead \ - SPIFlashDualRead -#endif -#ifdef ROM_SPIFlashDualReadNonBlocking -#define MAP_SPIFlashDualReadNonBlocking \ - ROM_SPIFlashDualReadNonBlocking -#else -#define MAP_SPIFlashDualReadNonBlocking \ - SPIFlashDualReadNonBlocking -#endif -#ifdef ROM_SPIFlashBlockErase32 -#define MAP_SPIFlashBlockErase32 \ - ROM_SPIFlashBlockErase32 -#else -#define MAP_SPIFlashBlockErase32 \ - SPIFlashBlockErase32 -#endif -#ifdef ROM_SPIFlashQuadRead -#define MAP_SPIFlashQuadRead \ - ROM_SPIFlashQuadRead -#else -#define MAP_SPIFlashQuadRead \ - SPIFlashQuadRead -#endif -#ifdef ROM_SPIFlashQuadReadNonBlocking -#define MAP_SPIFlashQuadReadNonBlocking \ - ROM_SPIFlashQuadReadNonBlocking -#else -#define MAP_SPIFlashQuadReadNonBlocking \ - SPIFlashQuadReadNonBlocking -#endif -#ifdef ROM_SPIFlashReadID -#define MAP_SPIFlashReadID \ - ROM_SPIFlashReadID -#else -#define MAP_SPIFlashReadID \ - SPIFlashReadID -#endif -#ifdef ROM_SPIFlashChipErase -#define MAP_SPIFlashChipErase \ - ROM_SPIFlashChipErase -#else -#define MAP_SPIFlashChipErase \ - SPIFlashChipErase -#endif -#ifdef ROM_SPIFlashBlockErase64 -#define MAP_SPIFlashBlockErase64 \ - ROM_SPIFlashBlockErase64 -#else -#define MAP_SPIFlashBlockErase64 \ - SPIFlashBlockErase64 -#endif - -//***************************************************************************** -// -// Macros for the SSI API. -// -//***************************************************************************** -#ifdef ROM_SSIDataPut -#define MAP_SSIDataPut \ - ROM_SSIDataPut -#else -#define MAP_SSIDataPut \ - SSIDataPut -#endif -#ifdef ROM_SSIConfigSetExpClk -#define MAP_SSIConfigSetExpClk \ - ROM_SSIConfigSetExpClk -#else -#define MAP_SSIConfigSetExpClk \ - SSIConfigSetExpClk -#endif -#ifdef ROM_SSIEnable -#define MAP_SSIEnable \ - ROM_SSIEnable -#else -#define MAP_SSIEnable \ - SSIEnable -#endif -#ifdef ROM_SSIDisable -#define MAP_SSIDisable \ - ROM_SSIDisable -#else -#define MAP_SSIDisable \ - SSIDisable -#endif -#ifdef ROM_SSIIntEnable -#define MAP_SSIIntEnable \ - ROM_SSIIntEnable -#else -#define MAP_SSIIntEnable \ - SSIIntEnable -#endif -#ifdef ROM_SSIIntDisable -#define MAP_SSIIntDisable \ - ROM_SSIIntDisable -#else -#define MAP_SSIIntDisable \ - SSIIntDisable -#endif -#ifdef ROM_SSIIntStatus -#define MAP_SSIIntStatus \ - ROM_SSIIntStatus -#else -#define MAP_SSIIntStatus \ - SSIIntStatus -#endif -#ifdef ROM_SSIIntClear -#define MAP_SSIIntClear \ - ROM_SSIIntClear -#else -#define MAP_SSIIntClear \ - SSIIntClear -#endif -#ifdef ROM_SSIDataPutNonBlocking -#define MAP_SSIDataPutNonBlocking \ - ROM_SSIDataPutNonBlocking -#else -#define MAP_SSIDataPutNonBlocking \ - SSIDataPutNonBlocking -#endif -#ifdef ROM_SSIDataGet -#define MAP_SSIDataGet \ - ROM_SSIDataGet -#else -#define MAP_SSIDataGet \ - SSIDataGet -#endif -#ifdef ROM_SSIDataGetNonBlocking -#define MAP_SSIDataGetNonBlocking \ - ROM_SSIDataGetNonBlocking -#else -#define MAP_SSIDataGetNonBlocking \ - SSIDataGetNonBlocking -#endif -#ifdef ROM_SSIDMAEnable -#define MAP_SSIDMAEnable \ - ROM_SSIDMAEnable -#else -#define MAP_SSIDMAEnable \ - SSIDMAEnable -#endif -#ifdef ROM_SSIDMADisable -#define MAP_SSIDMADisable \ - ROM_SSIDMADisable -#else -#define MAP_SSIDMADisable \ - SSIDMADisable -#endif -#ifdef ROM_SSIBusy -#define MAP_SSIBusy \ - ROM_SSIBusy -#else -#define MAP_SSIBusy \ - SSIBusy -#endif -#ifdef ROM_SSIClockSourceGet -#define MAP_SSIClockSourceGet \ - ROM_SSIClockSourceGet -#else -#define MAP_SSIClockSourceGet \ - SSIClockSourceGet -#endif -#ifdef ROM_SSIClockSourceSet -#define MAP_SSIClockSourceSet \ - ROM_SSIClockSourceSet -#else -#define MAP_SSIClockSourceSet \ - SSIClockSourceSet -#endif -#ifdef ROM_SSIAdvModeSet -#define MAP_SSIAdvModeSet \ - ROM_SSIAdvModeSet -#else -#define MAP_SSIAdvModeSet \ - SSIAdvModeSet -#endif -#ifdef ROM_SSIAdvDataPutFrameEnd -#define MAP_SSIAdvDataPutFrameEnd \ - ROM_SSIAdvDataPutFrameEnd -#else -#define MAP_SSIAdvDataPutFrameEnd \ - SSIAdvDataPutFrameEnd -#endif -#ifdef ROM_SSIAdvDataPutFrameEndNonBlocking -#define MAP_SSIAdvDataPutFrameEndNonBlocking \ - ROM_SSIAdvDataPutFrameEndNonBlocking -#else -#define MAP_SSIAdvDataPutFrameEndNonBlocking \ - SSIAdvDataPutFrameEndNonBlocking -#endif -#ifdef ROM_SSIAdvFrameHoldEnable -#define MAP_SSIAdvFrameHoldEnable \ - ROM_SSIAdvFrameHoldEnable -#else -#define MAP_SSIAdvFrameHoldEnable \ - SSIAdvFrameHoldEnable -#endif -#ifdef ROM_SSIAdvFrameHoldDisable -#define MAP_SSIAdvFrameHoldDisable \ - ROM_SSIAdvFrameHoldDisable -#else -#define MAP_SSIAdvFrameHoldDisable \ - SSIAdvFrameHoldDisable -#endif - -//***************************************************************************** -// -// Macros for the SysCtl API. -// -//***************************************************************************** -#ifdef ROM_SysCtlSleep -#define MAP_SysCtlSleep \ - ROM_SysCtlSleep -#else -#define MAP_SysCtlSleep \ - SysCtlSleep -#endif -#ifdef ROM_SysCtlSRAMSizeGet -#define MAP_SysCtlSRAMSizeGet \ - ROM_SysCtlSRAMSizeGet -#else -#define MAP_SysCtlSRAMSizeGet \ - SysCtlSRAMSizeGet -#endif -#ifdef ROM_SysCtlFlashSizeGet -#define MAP_SysCtlFlashSizeGet \ - ROM_SysCtlFlashSizeGet -#else -#define MAP_SysCtlFlashSizeGet \ - SysCtlFlashSizeGet -#endif -#ifdef ROM_SysCtlPeripheralPresent -#define MAP_SysCtlPeripheralPresent \ - ROM_SysCtlPeripheralPresent -#else -#define MAP_SysCtlPeripheralPresent \ - SysCtlPeripheralPresent -#endif -#ifdef ROM_SysCtlPeripheralReset -#define MAP_SysCtlPeripheralReset \ - ROM_SysCtlPeripheralReset -#else -#define MAP_SysCtlPeripheralReset \ - SysCtlPeripheralReset -#endif -#ifdef ROM_SysCtlPeripheralEnable -#define MAP_SysCtlPeripheralEnable \ - ROM_SysCtlPeripheralEnable -#else -#define MAP_SysCtlPeripheralEnable \ - SysCtlPeripheralEnable -#endif -#ifdef ROM_SysCtlPeripheralDisable -#define MAP_SysCtlPeripheralDisable \ - ROM_SysCtlPeripheralDisable -#else -#define MAP_SysCtlPeripheralDisable \ - SysCtlPeripheralDisable -#endif -#ifdef ROM_SysCtlPeripheralSleepEnable -#define MAP_SysCtlPeripheralSleepEnable \ - ROM_SysCtlPeripheralSleepEnable -#else -#define MAP_SysCtlPeripheralSleepEnable \ - SysCtlPeripheralSleepEnable -#endif -#ifdef ROM_SysCtlPeripheralSleepDisable -#define MAP_SysCtlPeripheralSleepDisable \ - ROM_SysCtlPeripheralSleepDisable -#else -#define MAP_SysCtlPeripheralSleepDisable \ - SysCtlPeripheralSleepDisable -#endif -#ifdef ROM_SysCtlPeripheralDeepSleepEnable -#define MAP_SysCtlPeripheralDeepSleepEnable \ - ROM_SysCtlPeripheralDeepSleepEnable -#else -#define MAP_SysCtlPeripheralDeepSleepEnable \ - SysCtlPeripheralDeepSleepEnable -#endif -#ifdef ROM_SysCtlPeripheralDeepSleepDisable -#define MAP_SysCtlPeripheralDeepSleepDisable \ - ROM_SysCtlPeripheralDeepSleepDisable -#else -#define MAP_SysCtlPeripheralDeepSleepDisable \ - SysCtlPeripheralDeepSleepDisable -#endif -#ifdef ROM_SysCtlPeripheralClockGating -#define MAP_SysCtlPeripheralClockGating \ - ROM_SysCtlPeripheralClockGating -#else -#define MAP_SysCtlPeripheralClockGating \ - SysCtlPeripheralClockGating -#endif -#ifdef ROM_SysCtlIntEnable -#define MAP_SysCtlIntEnable \ - ROM_SysCtlIntEnable -#else -#define MAP_SysCtlIntEnable \ - SysCtlIntEnable -#endif -#ifdef ROM_SysCtlIntDisable -#define MAP_SysCtlIntDisable \ - ROM_SysCtlIntDisable -#else -#define MAP_SysCtlIntDisable \ - SysCtlIntDisable -#endif -#ifdef ROM_SysCtlIntClear -#define MAP_SysCtlIntClear \ - ROM_SysCtlIntClear -#else -#define MAP_SysCtlIntClear \ - SysCtlIntClear -#endif -#ifdef ROM_SysCtlIntStatus -#define MAP_SysCtlIntStatus \ - ROM_SysCtlIntStatus -#else -#define MAP_SysCtlIntStatus \ - SysCtlIntStatus -#endif -#ifdef ROM_SysCtlReset -#define MAP_SysCtlReset \ - ROM_SysCtlReset -#else -#define MAP_SysCtlReset \ - SysCtlReset -#endif -#ifdef ROM_SysCtlDeepSleep -#define MAP_SysCtlDeepSleep \ - ROM_SysCtlDeepSleep -#else -#define MAP_SysCtlDeepSleep \ - SysCtlDeepSleep -#endif -#ifdef ROM_SysCtlResetCauseGet -#define MAP_SysCtlResetCauseGet \ - ROM_SysCtlResetCauseGet -#else -#define MAP_SysCtlResetCauseGet \ - SysCtlResetCauseGet -#endif -#ifdef ROM_SysCtlResetCauseClear -#define MAP_SysCtlResetCauseClear \ - ROM_SysCtlResetCauseClear -#else -#define MAP_SysCtlResetCauseClear \ - SysCtlResetCauseClear -#endif -#ifdef ROM_SysCtlClockSet -#define MAP_SysCtlClockSet \ - ROM_SysCtlClockSet -#else -#define MAP_SysCtlClockSet \ - SysCtlClockSet -#endif -#ifdef ROM_SysCtlClockGet -#define MAP_SysCtlClockGet \ - ROM_SysCtlClockGet -#else -#define MAP_SysCtlClockGet \ - SysCtlClockGet -#endif -#ifdef ROM_SysCtlPWMClockSet -#define MAP_SysCtlPWMClockSet \ - ROM_SysCtlPWMClockSet -#else -#define MAP_SysCtlPWMClockSet \ - SysCtlPWMClockSet -#endif -#ifdef ROM_SysCtlPWMClockGet -#define MAP_SysCtlPWMClockGet \ - ROM_SysCtlPWMClockGet -#else -#define MAP_SysCtlPWMClockGet \ - SysCtlPWMClockGet -#endif -#ifdef ROM_SysCtlUSBPLLEnable -#define MAP_SysCtlUSBPLLEnable \ - ROM_SysCtlUSBPLLEnable -#else -#define MAP_SysCtlUSBPLLEnable \ - SysCtlUSBPLLEnable -#endif -#ifdef ROM_SysCtlUSBPLLDisable -#define MAP_SysCtlUSBPLLDisable \ - ROM_SysCtlUSBPLLDisable -#else -#define MAP_SysCtlUSBPLLDisable \ - SysCtlUSBPLLDisable -#endif -#ifdef ROM_SysCtlDelay -#define MAP_SysCtlDelay \ - ROM_SysCtlDelay -#else -#define MAP_SysCtlDelay \ - SysCtlDelay -#endif -#ifdef ROM_SysCtlPeripheralReady -#define MAP_SysCtlPeripheralReady \ - ROM_SysCtlPeripheralReady -#else -#define MAP_SysCtlPeripheralReady \ - SysCtlPeripheralReady -#endif -#ifdef ROM_SysCtlPeripheralPowerOn -#define MAP_SysCtlPeripheralPowerOn \ - ROM_SysCtlPeripheralPowerOn -#else -#define MAP_SysCtlPeripheralPowerOn \ - SysCtlPeripheralPowerOn -#endif -#ifdef ROM_SysCtlPeripheralPowerOff -#define MAP_SysCtlPeripheralPowerOff \ - ROM_SysCtlPeripheralPowerOff -#else -#define MAP_SysCtlPeripheralPowerOff \ - SysCtlPeripheralPowerOff -#endif -#ifdef ROM_SysCtlMOSCConfigSet -#define MAP_SysCtlMOSCConfigSet \ - ROM_SysCtlMOSCConfigSet -#else -#define MAP_SysCtlMOSCConfigSet \ - SysCtlMOSCConfigSet -#endif -#ifdef ROM_SysCtlPIOSCCalibrate -#define MAP_SysCtlPIOSCCalibrate \ - ROM_SysCtlPIOSCCalibrate -#else -#define MAP_SysCtlPIOSCCalibrate \ - SysCtlPIOSCCalibrate -#endif -#ifdef ROM_SysCtlDeepSleepClockSet -#define MAP_SysCtlDeepSleepClockSet \ - ROM_SysCtlDeepSleepClockSet -#else -#define MAP_SysCtlDeepSleepClockSet \ - SysCtlDeepSleepClockSet -#endif -#ifdef ROM_SysCtlDeepSleepClockConfigSet -#define MAP_SysCtlDeepSleepClockConfigSet \ - ROM_SysCtlDeepSleepClockConfigSet -#else -#define MAP_SysCtlDeepSleepClockConfigSet \ - SysCtlDeepSleepClockConfigSet -#endif -#ifdef ROM_SysCtlClockFreqSet -#define MAP_SysCtlClockFreqSet \ - ROM_SysCtlClockFreqSet -#else -#define MAP_SysCtlClockFreqSet \ - SysCtlClockFreqSet -#endif -#ifdef ROM_SysCtlResetBehaviorSet -#define MAP_SysCtlResetBehaviorSet \ - ROM_SysCtlResetBehaviorSet -#else -#define MAP_SysCtlResetBehaviorSet \ - SysCtlResetBehaviorSet -#endif -#ifdef ROM_SysCtlResetBehaviorGet -#define MAP_SysCtlResetBehaviorGet \ - ROM_SysCtlResetBehaviorGet -#else -#define MAP_SysCtlResetBehaviorGet \ - SysCtlResetBehaviorGet -#endif -#ifdef ROM_SysCtlFlashSectorSizeGet -#define MAP_SysCtlFlashSectorSizeGet \ - ROM_SysCtlFlashSectorSizeGet -#else -#define MAP_SysCtlFlashSectorSizeGet \ - SysCtlFlashSectorSizeGet -#endif -#ifdef ROM_SysCtlVoltageEventConfig -#define MAP_SysCtlVoltageEventConfig \ - ROM_SysCtlVoltageEventConfig -#else -#define MAP_SysCtlVoltageEventConfig \ - SysCtlVoltageEventConfig -#endif -#ifdef ROM_SysCtlVoltageEventStatus -#define MAP_SysCtlVoltageEventStatus \ - ROM_SysCtlVoltageEventStatus -#else -#define MAP_SysCtlVoltageEventStatus \ - SysCtlVoltageEventStatus -#endif -#ifdef ROM_SysCtlVoltageEventClear -#define MAP_SysCtlVoltageEventClear \ - ROM_SysCtlVoltageEventClear -#else -#define MAP_SysCtlVoltageEventClear \ - SysCtlVoltageEventClear -#endif -#ifdef ROM_SysCtlNMIStatus -#define MAP_SysCtlNMIStatus \ - ROM_SysCtlNMIStatus -#else -#define MAP_SysCtlNMIStatus \ - SysCtlNMIStatus -#endif -#ifdef ROM_SysCtlNMIClear -#define MAP_SysCtlNMIClear \ - ROM_SysCtlNMIClear -#else -#define MAP_SysCtlNMIClear \ - SysCtlNMIClear -#endif -#ifdef ROM_SysCtlClockOutConfig -#define MAP_SysCtlClockOutConfig \ - ROM_SysCtlClockOutConfig -#else -#define MAP_SysCtlClockOutConfig \ - SysCtlClockOutConfig -#endif -#ifdef ROM_SysCtlAltClkConfig -#define MAP_SysCtlAltClkConfig \ - ROM_SysCtlAltClkConfig -#else -#define MAP_SysCtlAltClkConfig \ - SysCtlAltClkConfig -#endif - -//***************************************************************************** -// -// Macros for the SysExc API. -// -//***************************************************************************** -#ifdef ROM_SysExcIntStatus -#define MAP_SysExcIntStatus \ - ROM_SysExcIntStatus -#else -#define MAP_SysExcIntStatus \ - SysExcIntStatus -#endif -#ifdef ROM_SysExcIntClear -#define MAP_SysExcIntClear \ - ROM_SysExcIntClear -#else -#define MAP_SysExcIntClear \ - SysExcIntClear -#endif -#ifdef ROM_SysExcIntDisable -#define MAP_SysExcIntDisable \ - ROM_SysExcIntDisable -#else -#define MAP_SysExcIntDisable \ - SysExcIntDisable -#endif -#ifdef ROM_SysExcIntEnable -#define MAP_SysExcIntEnable \ - ROM_SysExcIntEnable -#else -#define MAP_SysExcIntEnable \ - SysExcIntEnable -#endif - -//***************************************************************************** -// -// Macros for the SysTick API. -// -//***************************************************************************** -#ifdef ROM_SysTickValueGet -#define MAP_SysTickValueGet \ - ROM_SysTickValueGet -#else -#define MAP_SysTickValueGet \ - SysTickValueGet -#endif -#ifdef ROM_SysTickEnable -#define MAP_SysTickEnable \ - ROM_SysTickEnable -#else -#define MAP_SysTickEnable \ - SysTickEnable -#endif -#ifdef ROM_SysTickDisable -#define MAP_SysTickDisable \ - ROM_SysTickDisable -#else -#define MAP_SysTickDisable \ - SysTickDisable -#endif -#ifdef ROM_SysTickIntEnable -#define MAP_SysTickIntEnable \ - ROM_SysTickIntEnable -#else -#define MAP_SysTickIntEnable \ - SysTickIntEnable -#endif -#ifdef ROM_SysTickIntDisable -#define MAP_SysTickIntDisable \ - ROM_SysTickIntDisable -#else -#define MAP_SysTickIntDisable \ - SysTickIntDisable -#endif -#ifdef ROM_SysTickPeriodSet -#define MAP_SysTickPeriodSet \ - ROM_SysTickPeriodSet -#else -#define MAP_SysTickPeriodSet \ - SysTickPeriodSet -#endif -#ifdef ROM_SysTickPeriodGet -#define MAP_SysTickPeriodGet \ - ROM_SysTickPeriodGet -#else -#define MAP_SysTickPeriodGet \ - SysTickPeriodGet -#endif - -//***************************************************************************** -// -// Macros for the Timer API. -// -//***************************************************************************** -#ifdef ROM_TimerIntClear -#define MAP_TimerIntClear \ - ROM_TimerIntClear -#else -#define MAP_TimerIntClear \ - TimerIntClear -#endif -#ifdef ROM_TimerEnable -#define MAP_TimerEnable \ - ROM_TimerEnable -#else -#define MAP_TimerEnable \ - TimerEnable -#endif -#ifdef ROM_TimerDisable -#define MAP_TimerDisable \ - ROM_TimerDisable -#else -#define MAP_TimerDisable \ - TimerDisable -#endif -#ifdef ROM_TimerConfigure -#define MAP_TimerConfigure \ - ROM_TimerConfigure -#else -#define MAP_TimerConfigure \ - TimerConfigure -#endif -#ifdef ROM_TimerControlLevel -#define MAP_TimerControlLevel \ - ROM_TimerControlLevel -#else -#define MAP_TimerControlLevel \ - TimerControlLevel -#endif -#ifdef ROM_TimerControlTrigger -#define MAP_TimerControlTrigger \ - ROM_TimerControlTrigger -#else -#define MAP_TimerControlTrigger \ - TimerControlTrigger -#endif -#ifdef ROM_TimerControlEvent -#define MAP_TimerControlEvent \ - ROM_TimerControlEvent -#else -#define MAP_TimerControlEvent \ - TimerControlEvent -#endif -#ifdef ROM_TimerControlStall -#define MAP_TimerControlStall \ - ROM_TimerControlStall -#else -#define MAP_TimerControlStall \ - TimerControlStall -#endif -#ifdef ROM_TimerRTCEnable -#define MAP_TimerRTCEnable \ - ROM_TimerRTCEnable -#else -#define MAP_TimerRTCEnable \ - TimerRTCEnable -#endif -#ifdef ROM_TimerRTCDisable -#define MAP_TimerRTCDisable \ - ROM_TimerRTCDisable -#else -#define MAP_TimerRTCDisable \ - TimerRTCDisable -#endif -#ifdef ROM_TimerPrescaleSet -#define MAP_TimerPrescaleSet \ - ROM_TimerPrescaleSet -#else -#define MAP_TimerPrescaleSet \ - TimerPrescaleSet -#endif -#ifdef ROM_TimerPrescaleGet -#define MAP_TimerPrescaleGet \ - ROM_TimerPrescaleGet -#else -#define MAP_TimerPrescaleGet \ - TimerPrescaleGet -#endif -#ifdef ROM_TimerPrescaleMatchSet -#define MAP_TimerPrescaleMatchSet \ - ROM_TimerPrescaleMatchSet -#else -#define MAP_TimerPrescaleMatchSet \ - TimerPrescaleMatchSet -#endif -#ifdef ROM_TimerPrescaleMatchGet -#define MAP_TimerPrescaleMatchGet \ - ROM_TimerPrescaleMatchGet -#else -#define MAP_TimerPrescaleMatchGet \ - TimerPrescaleMatchGet -#endif -#ifdef ROM_TimerLoadSet -#define MAP_TimerLoadSet \ - ROM_TimerLoadSet -#else -#define MAP_TimerLoadSet \ - TimerLoadSet -#endif -#ifdef ROM_TimerLoadGet -#define MAP_TimerLoadGet \ - ROM_TimerLoadGet -#else -#define MAP_TimerLoadGet \ - TimerLoadGet -#endif -#ifdef ROM_TimerValueGet -#define MAP_TimerValueGet \ - ROM_TimerValueGet -#else -#define MAP_TimerValueGet \ - TimerValueGet -#endif -#ifdef ROM_TimerMatchSet -#define MAP_TimerMatchSet \ - ROM_TimerMatchSet -#else -#define MAP_TimerMatchSet \ - TimerMatchSet -#endif -#ifdef ROM_TimerMatchGet -#define MAP_TimerMatchGet \ - ROM_TimerMatchGet -#else -#define MAP_TimerMatchGet \ - TimerMatchGet -#endif -#ifdef ROM_TimerIntEnable -#define MAP_TimerIntEnable \ - ROM_TimerIntEnable -#else -#define MAP_TimerIntEnable \ - TimerIntEnable -#endif -#ifdef ROM_TimerIntDisable -#define MAP_TimerIntDisable \ - ROM_TimerIntDisable -#else -#define MAP_TimerIntDisable \ - TimerIntDisable -#endif -#ifdef ROM_TimerIntStatus -#define MAP_TimerIntStatus \ - ROM_TimerIntStatus -#else -#define MAP_TimerIntStatus \ - TimerIntStatus -#endif -#ifdef ROM_TimerControlWaitOnTrigger -#define MAP_TimerControlWaitOnTrigger \ - ROM_TimerControlWaitOnTrigger -#else -#define MAP_TimerControlWaitOnTrigger \ - TimerControlWaitOnTrigger -#endif -#ifdef ROM_TimerLoadSet64 -#define MAP_TimerLoadSet64 \ - ROM_TimerLoadSet64 -#else -#define MAP_TimerLoadSet64 \ - TimerLoadSet64 -#endif -#ifdef ROM_TimerLoadGet64 -#define MAP_TimerLoadGet64 \ - ROM_TimerLoadGet64 -#else -#define MAP_TimerLoadGet64 \ - TimerLoadGet64 -#endif -#ifdef ROM_TimerValueGet64 -#define MAP_TimerValueGet64 \ - ROM_TimerValueGet64 -#else -#define MAP_TimerValueGet64 \ - TimerValueGet64 -#endif -#ifdef ROM_TimerMatchSet64 -#define MAP_TimerMatchSet64 \ - ROM_TimerMatchSet64 -#else -#define MAP_TimerMatchSet64 \ - TimerMatchSet64 -#endif -#ifdef ROM_TimerMatchGet64 -#define MAP_TimerMatchGet64 \ - ROM_TimerMatchGet64 -#else -#define MAP_TimerMatchGet64 \ - TimerMatchGet64 -#endif -#ifdef ROM_TimerClockSourceGet -#define MAP_TimerClockSourceGet \ - ROM_TimerClockSourceGet -#else -#define MAP_TimerClockSourceGet \ - TimerClockSourceGet -#endif -#ifdef ROM_TimerClockSourceSet -#define MAP_TimerClockSourceSet \ - ROM_TimerClockSourceSet -#else -#define MAP_TimerClockSourceSet \ - TimerClockSourceSet -#endif -#ifdef ROM_TimerADCEventGet -#define MAP_TimerADCEventGet \ - ROM_TimerADCEventGet -#else -#define MAP_TimerADCEventGet \ - TimerADCEventGet -#endif -#ifdef ROM_TimerADCEventSet -#define MAP_TimerADCEventSet \ - ROM_TimerADCEventSet -#else -#define MAP_TimerADCEventSet \ - TimerADCEventSet -#endif -#ifdef ROM_TimerDMAEventGet -#define MAP_TimerDMAEventGet \ - ROM_TimerDMAEventGet -#else -#define MAP_TimerDMAEventGet \ - TimerDMAEventGet -#endif -#ifdef ROM_TimerDMAEventSet -#define MAP_TimerDMAEventSet \ - ROM_TimerDMAEventSet -#else -#define MAP_TimerDMAEventSet \ - TimerDMAEventSet -#endif -#ifdef ROM_TimerSynchronize -#define MAP_TimerSynchronize \ - ROM_TimerSynchronize -#else -#define MAP_TimerSynchronize \ - TimerSynchronize -#endif - -//***************************************************************************** -// -// Macros for the UART API. -// -//***************************************************************************** -#ifdef ROM_UARTCharPut -#define MAP_UARTCharPut \ - ROM_UARTCharPut -#else -#define MAP_UARTCharPut \ - UARTCharPut -#endif -#ifdef ROM_UARTParityModeSet -#define MAP_UARTParityModeSet \ - ROM_UARTParityModeSet -#else -#define MAP_UARTParityModeSet \ - UARTParityModeSet -#endif -#ifdef ROM_UARTParityModeGet -#define MAP_UARTParityModeGet \ - ROM_UARTParityModeGet -#else -#define MAP_UARTParityModeGet \ - UARTParityModeGet -#endif -#ifdef ROM_UARTFIFOLevelSet -#define MAP_UARTFIFOLevelSet \ - ROM_UARTFIFOLevelSet -#else -#define MAP_UARTFIFOLevelSet \ - UARTFIFOLevelSet -#endif -#ifdef ROM_UARTFIFOLevelGet -#define MAP_UARTFIFOLevelGet \ - ROM_UARTFIFOLevelGet -#else -#define MAP_UARTFIFOLevelGet \ - UARTFIFOLevelGet -#endif -#ifdef ROM_UARTConfigSetExpClk -#define MAP_UARTConfigSetExpClk \ - ROM_UARTConfigSetExpClk -#else -#define MAP_UARTConfigSetExpClk \ - UARTConfigSetExpClk -#endif -#ifdef ROM_UARTConfigGetExpClk -#define MAP_UARTConfigGetExpClk \ - ROM_UARTConfigGetExpClk -#else -#define MAP_UARTConfigGetExpClk \ - UARTConfigGetExpClk -#endif -#ifdef ROM_UARTEnable -#define MAP_UARTEnable \ - ROM_UARTEnable -#else -#define MAP_UARTEnable \ - UARTEnable -#endif -#ifdef ROM_UARTDisable -#define MAP_UARTDisable \ - ROM_UARTDisable -#else -#define MAP_UARTDisable \ - UARTDisable -#endif -#ifdef ROM_UARTEnableSIR -#define MAP_UARTEnableSIR \ - ROM_UARTEnableSIR -#else -#define MAP_UARTEnableSIR \ - UARTEnableSIR -#endif -#ifdef ROM_UARTDisableSIR -#define MAP_UARTDisableSIR \ - ROM_UARTDisableSIR -#else -#define MAP_UARTDisableSIR \ - UARTDisableSIR -#endif -#ifdef ROM_UARTCharsAvail -#define MAP_UARTCharsAvail \ - ROM_UARTCharsAvail -#else -#define MAP_UARTCharsAvail \ - UARTCharsAvail -#endif -#ifdef ROM_UARTSpaceAvail -#define MAP_UARTSpaceAvail \ - ROM_UARTSpaceAvail -#else -#define MAP_UARTSpaceAvail \ - UARTSpaceAvail -#endif -#ifdef ROM_UARTCharGetNonBlocking -#define MAP_UARTCharGetNonBlocking \ - ROM_UARTCharGetNonBlocking -#else -#define MAP_UARTCharGetNonBlocking \ - UARTCharGetNonBlocking -#endif -#ifdef ROM_UARTCharGet -#define MAP_UARTCharGet \ - ROM_UARTCharGet -#else -#define MAP_UARTCharGet \ - UARTCharGet -#endif -#ifdef ROM_UARTCharPutNonBlocking -#define MAP_UARTCharPutNonBlocking \ - ROM_UARTCharPutNonBlocking -#else -#define MAP_UARTCharPutNonBlocking \ - UARTCharPutNonBlocking -#endif -#ifdef ROM_UARTBreakCtl -#define MAP_UARTBreakCtl \ - ROM_UARTBreakCtl -#else -#define MAP_UARTBreakCtl \ - UARTBreakCtl -#endif -#ifdef ROM_UARTIntEnable -#define MAP_UARTIntEnable \ - ROM_UARTIntEnable -#else -#define MAP_UARTIntEnable \ - UARTIntEnable -#endif -#ifdef ROM_UARTIntDisable -#define MAP_UARTIntDisable \ - ROM_UARTIntDisable -#else -#define MAP_UARTIntDisable \ - UARTIntDisable -#endif -#ifdef ROM_UARTIntStatus -#define MAP_UARTIntStatus \ - ROM_UARTIntStatus -#else -#define MAP_UARTIntStatus \ - UARTIntStatus -#endif -#ifdef ROM_UARTIntClear -#define MAP_UARTIntClear \ - ROM_UARTIntClear -#else -#define MAP_UARTIntClear \ - UARTIntClear -#endif -#ifdef ROM_UARTDMAEnable -#define MAP_UARTDMAEnable \ - ROM_UARTDMAEnable -#else -#define MAP_UARTDMAEnable \ - UARTDMAEnable -#endif -#ifdef ROM_UARTDMADisable -#define MAP_UARTDMADisable \ - ROM_UARTDMADisable -#else -#define MAP_UARTDMADisable \ - UARTDMADisable -#endif -#ifdef ROM_UARTFIFOEnable -#define MAP_UARTFIFOEnable \ - ROM_UARTFIFOEnable -#else -#define MAP_UARTFIFOEnable \ - UARTFIFOEnable -#endif -#ifdef ROM_UARTFIFODisable -#define MAP_UARTFIFODisable \ - ROM_UARTFIFODisable -#else -#define MAP_UARTFIFODisable \ - UARTFIFODisable -#endif -#ifdef ROM_UARTBusy -#define MAP_UARTBusy \ - ROM_UARTBusy -#else -#define MAP_UARTBusy \ - UARTBusy -#endif -#ifdef ROM_UARTTxIntModeSet -#define MAP_UARTTxIntModeSet \ - ROM_UARTTxIntModeSet -#else -#define MAP_UARTTxIntModeSet \ - UARTTxIntModeSet -#endif -#ifdef ROM_UARTTxIntModeGet -#define MAP_UARTTxIntModeGet \ - ROM_UARTTxIntModeGet -#else -#define MAP_UARTTxIntModeGet \ - UARTTxIntModeGet -#endif -#ifdef ROM_UARTRxErrorGet -#define MAP_UARTRxErrorGet \ - ROM_UARTRxErrorGet -#else -#define MAP_UARTRxErrorGet \ - UARTRxErrorGet -#endif -#ifdef ROM_UARTRxErrorClear -#define MAP_UARTRxErrorClear \ - ROM_UARTRxErrorClear -#else -#define MAP_UARTRxErrorClear \ - UARTRxErrorClear -#endif -#ifdef ROM_UARTClockSourceSet -#define MAP_UARTClockSourceSet \ - ROM_UARTClockSourceSet -#else -#define MAP_UARTClockSourceSet \ - UARTClockSourceSet -#endif -#ifdef ROM_UARTClockSourceGet -#define MAP_UARTClockSourceGet \ - ROM_UARTClockSourceGet -#else -#define MAP_UARTClockSourceGet \ - UARTClockSourceGet -#endif -#ifdef ROM_UART9BitEnable -#define MAP_UART9BitEnable \ - ROM_UART9BitEnable -#else -#define MAP_UART9BitEnable \ - UART9BitEnable -#endif -#ifdef ROM_UART9BitDisable -#define MAP_UART9BitDisable \ - ROM_UART9BitDisable -#else -#define MAP_UART9BitDisable \ - UART9BitDisable -#endif -#ifdef ROM_UART9BitAddrSet -#define MAP_UART9BitAddrSet \ - ROM_UART9BitAddrSet -#else -#define MAP_UART9BitAddrSet \ - UART9BitAddrSet -#endif -#ifdef ROM_UART9BitAddrSend -#define MAP_UART9BitAddrSend \ - ROM_UART9BitAddrSend -#else -#define MAP_UART9BitAddrSend \ - UART9BitAddrSend -#endif -#ifdef ROM_UARTSmartCardDisable -#define MAP_UARTSmartCardDisable \ - ROM_UARTSmartCardDisable -#else -#define MAP_UARTSmartCardDisable \ - UARTSmartCardDisable -#endif -#ifdef ROM_UARTSmartCardEnable -#define MAP_UARTSmartCardEnable \ - ROM_UARTSmartCardEnable -#else -#define MAP_UARTSmartCardEnable \ - UARTSmartCardEnable -#endif -#ifdef ROM_UARTModemControlClear -#define MAP_UARTModemControlClear \ - ROM_UARTModemControlClear -#else -#define MAP_UARTModemControlClear \ - UARTModemControlClear -#endif -#ifdef ROM_UARTModemControlGet -#define MAP_UARTModemControlGet \ - ROM_UARTModemControlGet -#else -#define MAP_UARTModemControlGet \ - UARTModemControlGet -#endif -#ifdef ROM_UARTModemControlSet -#define MAP_UARTModemControlSet \ - ROM_UARTModemControlSet -#else -#define MAP_UARTModemControlSet \ - UARTModemControlSet -#endif -#ifdef ROM_UARTModemStatusGet -#define MAP_UARTModemStatusGet \ - ROM_UARTModemStatusGet -#else -#define MAP_UARTModemStatusGet \ - UARTModemStatusGet -#endif -#ifdef ROM_UARTFlowControlGet -#define MAP_UARTFlowControlGet \ - ROM_UARTFlowControlGet -#else -#define MAP_UARTFlowControlGet \ - UARTFlowControlGet -#endif -#ifdef ROM_UARTFlowControlSet -#define MAP_UARTFlowControlSet \ - ROM_UARTFlowControlSet -#else -#define MAP_UARTFlowControlSet \ - UARTFlowControlSet -#endif - -//***************************************************************************** -// -// Macros for the uDMA API. -// -//***************************************************************************** -#ifdef ROM_uDMAChannelTransferSet -#define MAP_uDMAChannelTransferSet \ - ROM_uDMAChannelTransferSet -#else -#define MAP_uDMAChannelTransferSet \ - uDMAChannelTransferSet -#endif -#ifdef ROM_uDMAEnable -#define MAP_uDMAEnable \ - ROM_uDMAEnable -#else -#define MAP_uDMAEnable \ - uDMAEnable -#endif -#ifdef ROM_uDMADisable -#define MAP_uDMADisable \ - ROM_uDMADisable -#else -#define MAP_uDMADisable \ - uDMADisable -#endif -#ifdef ROM_uDMAErrorStatusGet -#define MAP_uDMAErrorStatusGet \ - ROM_uDMAErrorStatusGet -#else -#define MAP_uDMAErrorStatusGet \ - uDMAErrorStatusGet -#endif -#ifdef ROM_uDMAErrorStatusClear -#define MAP_uDMAErrorStatusClear \ - ROM_uDMAErrorStatusClear -#else -#define MAP_uDMAErrorStatusClear \ - uDMAErrorStatusClear -#endif -#ifdef ROM_uDMAChannelEnable -#define MAP_uDMAChannelEnable \ - ROM_uDMAChannelEnable -#else -#define MAP_uDMAChannelEnable \ - uDMAChannelEnable -#endif -#ifdef ROM_uDMAChannelDisable -#define MAP_uDMAChannelDisable \ - ROM_uDMAChannelDisable -#else -#define MAP_uDMAChannelDisable \ - uDMAChannelDisable -#endif -#ifdef ROM_uDMAChannelIsEnabled -#define MAP_uDMAChannelIsEnabled \ - ROM_uDMAChannelIsEnabled -#else -#define MAP_uDMAChannelIsEnabled \ - uDMAChannelIsEnabled -#endif -#ifdef ROM_uDMAControlBaseSet -#define MAP_uDMAControlBaseSet \ - ROM_uDMAControlBaseSet -#else -#define MAP_uDMAControlBaseSet \ - uDMAControlBaseSet -#endif -#ifdef ROM_uDMAControlBaseGet -#define MAP_uDMAControlBaseGet \ - ROM_uDMAControlBaseGet -#else -#define MAP_uDMAControlBaseGet \ - uDMAControlBaseGet -#endif -#ifdef ROM_uDMAChannelRequest -#define MAP_uDMAChannelRequest \ - ROM_uDMAChannelRequest -#else -#define MAP_uDMAChannelRequest \ - uDMAChannelRequest -#endif -#ifdef ROM_uDMAChannelAttributeEnable -#define MAP_uDMAChannelAttributeEnable \ - ROM_uDMAChannelAttributeEnable -#else -#define MAP_uDMAChannelAttributeEnable \ - uDMAChannelAttributeEnable -#endif -#ifdef ROM_uDMAChannelAttributeDisable -#define MAP_uDMAChannelAttributeDisable \ - ROM_uDMAChannelAttributeDisable -#else -#define MAP_uDMAChannelAttributeDisable \ - uDMAChannelAttributeDisable -#endif -#ifdef ROM_uDMAChannelAttributeGet -#define MAP_uDMAChannelAttributeGet \ - ROM_uDMAChannelAttributeGet -#else -#define MAP_uDMAChannelAttributeGet \ - uDMAChannelAttributeGet -#endif -#ifdef ROM_uDMAChannelControlSet -#define MAP_uDMAChannelControlSet \ - ROM_uDMAChannelControlSet -#else -#define MAP_uDMAChannelControlSet \ - uDMAChannelControlSet -#endif -#ifdef ROM_uDMAChannelSizeGet -#define MAP_uDMAChannelSizeGet \ - ROM_uDMAChannelSizeGet -#else -#define MAP_uDMAChannelSizeGet \ - uDMAChannelSizeGet -#endif -#ifdef ROM_uDMAChannelModeGet -#define MAP_uDMAChannelModeGet \ - ROM_uDMAChannelModeGet -#else -#define MAP_uDMAChannelModeGet \ - uDMAChannelModeGet -#endif -#ifdef ROM_uDMAChannelSelectSecondary -#define MAP_uDMAChannelSelectSecondary \ - ROM_uDMAChannelSelectSecondary -#else -#define MAP_uDMAChannelSelectSecondary \ - uDMAChannelSelectSecondary -#endif -#ifdef ROM_uDMAChannelSelectDefault -#define MAP_uDMAChannelSelectDefault \ - ROM_uDMAChannelSelectDefault -#else -#define MAP_uDMAChannelSelectDefault \ - uDMAChannelSelectDefault -#endif -#ifdef ROM_uDMAIntStatus -#define MAP_uDMAIntStatus \ - ROM_uDMAIntStatus -#else -#define MAP_uDMAIntStatus \ - uDMAIntStatus -#endif -#ifdef ROM_uDMAIntClear -#define MAP_uDMAIntClear \ - ROM_uDMAIntClear -#else -#define MAP_uDMAIntClear \ - uDMAIntClear -#endif -#ifdef ROM_uDMAControlAlternateBaseGet -#define MAP_uDMAControlAlternateBaseGet \ - ROM_uDMAControlAlternateBaseGet -#else -#define MAP_uDMAControlAlternateBaseGet \ - uDMAControlAlternateBaseGet -#endif -#ifdef ROM_uDMAChannelScatterGatherSet -#define MAP_uDMAChannelScatterGatherSet \ - ROM_uDMAChannelScatterGatherSet -#else -#define MAP_uDMAChannelScatterGatherSet \ - uDMAChannelScatterGatherSet -#endif -#ifdef ROM_uDMAChannelAssign -#define MAP_uDMAChannelAssign \ - ROM_uDMAChannelAssign -#else -#define MAP_uDMAChannelAssign \ - uDMAChannelAssign -#endif - -//***************************************************************************** -// -// Macros for the USB API. -// -//***************************************************************************** -#ifdef ROM_USBDevAddrGet -#define MAP_USBDevAddrGet \ - ROM_USBDevAddrGet -#else -#define MAP_USBDevAddrGet \ - USBDevAddrGet -#endif -#ifdef ROM_USBDevAddrSet -#define MAP_USBDevAddrSet \ - ROM_USBDevAddrSet -#else -#define MAP_USBDevAddrSet \ - USBDevAddrSet -#endif -#ifdef ROM_USBDevConnect -#define MAP_USBDevConnect \ - ROM_USBDevConnect -#else -#define MAP_USBDevConnect \ - USBDevConnect -#endif -#ifdef ROM_USBDevDisconnect -#define MAP_USBDevDisconnect \ - ROM_USBDevDisconnect -#else -#define MAP_USBDevDisconnect \ - USBDevDisconnect -#endif -#ifdef ROM_USBDevEndpointConfigSet -#define MAP_USBDevEndpointConfigSet \ - ROM_USBDevEndpointConfigSet -#else -#define MAP_USBDevEndpointConfigSet \ - USBDevEndpointConfigSet -#endif -#ifdef ROM_USBDevEndpointDataAck -#define MAP_USBDevEndpointDataAck \ - ROM_USBDevEndpointDataAck -#else -#define MAP_USBDevEndpointDataAck \ - USBDevEndpointDataAck -#endif -#ifdef ROM_USBDevEndpointStall -#define MAP_USBDevEndpointStall \ - ROM_USBDevEndpointStall -#else -#define MAP_USBDevEndpointStall \ - USBDevEndpointStall -#endif -#ifdef ROM_USBDevEndpointStallClear -#define MAP_USBDevEndpointStallClear \ - ROM_USBDevEndpointStallClear -#else -#define MAP_USBDevEndpointStallClear \ - USBDevEndpointStallClear -#endif -#ifdef ROM_USBDevEndpointStatusClear -#define MAP_USBDevEndpointStatusClear \ - ROM_USBDevEndpointStatusClear -#else -#define MAP_USBDevEndpointStatusClear \ - USBDevEndpointStatusClear -#endif -#ifdef ROM_USBEndpointDataGet -#define MAP_USBEndpointDataGet \ - ROM_USBEndpointDataGet -#else -#define MAP_USBEndpointDataGet \ - USBEndpointDataGet -#endif -#ifdef ROM_USBEndpointDataPut -#define MAP_USBEndpointDataPut \ - ROM_USBEndpointDataPut -#else -#define MAP_USBEndpointDataPut \ - USBEndpointDataPut -#endif -#ifdef ROM_USBEndpointDataSend -#define MAP_USBEndpointDataSend \ - ROM_USBEndpointDataSend -#else -#define MAP_USBEndpointDataSend \ - USBEndpointDataSend -#endif -#ifdef ROM_USBEndpointDataToggleClear -#define MAP_USBEndpointDataToggleClear \ - ROM_USBEndpointDataToggleClear -#else -#define MAP_USBEndpointDataToggleClear \ - USBEndpointDataToggleClear -#endif -#ifdef ROM_USBEndpointStatus -#define MAP_USBEndpointStatus \ - ROM_USBEndpointStatus -#else -#define MAP_USBEndpointStatus \ - USBEndpointStatus -#endif -#ifdef ROM_USBFIFOAddrGet -#define MAP_USBFIFOAddrGet \ - ROM_USBFIFOAddrGet -#else -#define MAP_USBFIFOAddrGet \ - USBFIFOAddrGet -#endif -#ifdef ROM_USBFIFOConfigGet -#define MAP_USBFIFOConfigGet \ - ROM_USBFIFOConfigGet -#else -#define MAP_USBFIFOConfigGet \ - USBFIFOConfigGet -#endif -#ifdef ROM_USBFIFOConfigSet -#define MAP_USBFIFOConfigSet \ - ROM_USBFIFOConfigSet -#else -#define MAP_USBFIFOConfigSet \ - USBFIFOConfigSet -#endif -#ifdef ROM_USBFIFOFlush -#define MAP_USBFIFOFlush \ - ROM_USBFIFOFlush -#else -#define MAP_USBFIFOFlush \ - USBFIFOFlush -#endif -#ifdef ROM_USBFrameNumberGet -#define MAP_USBFrameNumberGet \ - ROM_USBFrameNumberGet -#else -#define MAP_USBFrameNumberGet \ - USBFrameNumberGet -#endif -#ifdef ROM_USBHostAddrGet -#define MAP_USBHostAddrGet \ - ROM_USBHostAddrGet -#else -#define MAP_USBHostAddrGet \ - USBHostAddrGet -#endif -#ifdef ROM_USBHostAddrSet -#define MAP_USBHostAddrSet \ - ROM_USBHostAddrSet -#else -#define MAP_USBHostAddrSet \ - USBHostAddrSet -#endif -#ifdef ROM_USBHostEndpointConfig -#define MAP_USBHostEndpointConfig \ - ROM_USBHostEndpointConfig -#else -#define MAP_USBHostEndpointConfig \ - USBHostEndpointConfig -#endif -#ifdef ROM_USBHostEndpointDataAck -#define MAP_USBHostEndpointDataAck \ - ROM_USBHostEndpointDataAck -#else -#define MAP_USBHostEndpointDataAck \ - USBHostEndpointDataAck -#endif -#ifdef ROM_USBHostEndpointDataToggle -#define MAP_USBHostEndpointDataToggle \ - ROM_USBHostEndpointDataToggle -#else -#define MAP_USBHostEndpointDataToggle \ - USBHostEndpointDataToggle -#endif -#ifdef ROM_USBHostEndpointStatusClear -#define MAP_USBHostEndpointStatusClear \ - ROM_USBHostEndpointStatusClear -#else -#define MAP_USBHostEndpointStatusClear \ - USBHostEndpointStatusClear -#endif -#ifdef ROM_USBHostHubAddrGet -#define MAP_USBHostHubAddrGet \ - ROM_USBHostHubAddrGet -#else -#define MAP_USBHostHubAddrGet \ - USBHostHubAddrGet -#endif -#ifdef ROM_USBHostHubAddrSet -#define MAP_USBHostHubAddrSet \ - ROM_USBHostHubAddrSet -#else -#define MAP_USBHostHubAddrSet \ - USBHostHubAddrSet -#endif -#ifdef ROM_USBHostPwrDisable -#define MAP_USBHostPwrDisable \ - ROM_USBHostPwrDisable -#else -#define MAP_USBHostPwrDisable \ - USBHostPwrDisable -#endif -#ifdef ROM_USBHostPwrEnable -#define MAP_USBHostPwrEnable \ - ROM_USBHostPwrEnable -#else -#define MAP_USBHostPwrEnable \ - USBHostPwrEnable -#endif -#ifdef ROM_USBHostPwrConfig -#define MAP_USBHostPwrConfig \ - ROM_USBHostPwrConfig -#else -#define MAP_USBHostPwrConfig \ - USBHostPwrConfig -#endif -#ifdef ROM_USBHostPwrFaultDisable -#define MAP_USBHostPwrFaultDisable \ - ROM_USBHostPwrFaultDisable -#else -#define MAP_USBHostPwrFaultDisable \ - USBHostPwrFaultDisable -#endif -#ifdef ROM_USBHostPwrFaultEnable -#define MAP_USBHostPwrFaultEnable \ - ROM_USBHostPwrFaultEnable -#else -#define MAP_USBHostPwrFaultEnable \ - USBHostPwrFaultEnable -#endif -#ifdef ROM_USBHostRequestIN -#define MAP_USBHostRequestIN \ - ROM_USBHostRequestIN -#else -#define MAP_USBHostRequestIN \ - USBHostRequestIN -#endif -#ifdef ROM_USBHostRequestStatus -#define MAP_USBHostRequestStatus \ - ROM_USBHostRequestStatus -#else -#define MAP_USBHostRequestStatus \ - USBHostRequestStatus -#endif -#ifdef ROM_USBHostReset -#define MAP_USBHostReset \ - ROM_USBHostReset -#else -#define MAP_USBHostReset \ - USBHostReset -#endif -#ifdef ROM_USBHostResume -#define MAP_USBHostResume \ - ROM_USBHostResume -#else -#define MAP_USBHostResume \ - USBHostResume -#endif -#ifdef ROM_USBHostSpeedGet -#define MAP_USBHostSpeedGet \ - ROM_USBHostSpeedGet -#else -#define MAP_USBHostSpeedGet \ - USBHostSpeedGet -#endif -#ifdef ROM_USBHostSuspend -#define MAP_USBHostSuspend \ - ROM_USBHostSuspend -#else -#define MAP_USBHostSuspend \ - USBHostSuspend -#endif -#ifdef ROM_USBDevEndpointConfigGet -#define MAP_USBDevEndpointConfigGet \ - ROM_USBDevEndpointConfigGet -#else -#define MAP_USBDevEndpointConfigGet \ - USBDevEndpointConfigGet -#endif -#ifdef ROM_USBEndpointDMAEnable -#define MAP_USBEndpointDMAEnable \ - ROM_USBEndpointDMAEnable -#else -#define MAP_USBEndpointDMAEnable \ - USBEndpointDMAEnable -#endif -#ifdef ROM_USBEndpointDMADisable -#define MAP_USBEndpointDMADisable \ - ROM_USBEndpointDMADisable -#else -#define MAP_USBEndpointDMADisable \ - USBEndpointDMADisable -#endif -#ifdef ROM_USBEndpointDataAvail -#define MAP_USBEndpointDataAvail \ - ROM_USBEndpointDataAvail -#else -#define MAP_USBEndpointDataAvail \ - USBEndpointDataAvail -#endif -#ifdef ROM_USBModeGet -#define MAP_USBModeGet \ - ROM_USBModeGet -#else -#define MAP_USBModeGet \ - USBModeGet -#endif -#ifdef ROM_USBEndpointDMAChannel -#define MAP_USBEndpointDMAChannel \ - ROM_USBEndpointDMAChannel -#else -#define MAP_USBEndpointDMAChannel \ - USBEndpointDMAChannel -#endif -#ifdef ROM_USBIntDisableControl -#define MAP_USBIntDisableControl \ - ROM_USBIntDisableControl -#else -#define MAP_USBIntDisableControl \ - USBIntDisableControl -#endif -#ifdef ROM_USBIntEnableControl -#define MAP_USBIntEnableControl \ - ROM_USBIntEnableControl -#else -#define MAP_USBIntEnableControl \ - USBIntEnableControl -#endif -#ifdef ROM_USBIntStatusControl -#define MAP_USBIntStatusControl \ - ROM_USBIntStatusControl -#else -#define MAP_USBIntStatusControl \ - USBIntStatusControl -#endif -#ifdef ROM_USBIntDisableEndpoint -#define MAP_USBIntDisableEndpoint \ - ROM_USBIntDisableEndpoint -#else -#define MAP_USBIntDisableEndpoint \ - USBIntDisableEndpoint -#endif -#ifdef ROM_USBIntEnableEndpoint -#define MAP_USBIntEnableEndpoint \ - ROM_USBIntEnableEndpoint -#else -#define MAP_USBIntEnableEndpoint \ - USBIntEnableEndpoint -#endif -#ifdef ROM_USBIntStatusEndpoint -#define MAP_USBIntStatusEndpoint \ - ROM_USBIntStatusEndpoint -#else -#define MAP_USBIntStatusEndpoint \ - USBIntStatusEndpoint -#endif -#ifdef ROM_USBHostMode -#define MAP_USBHostMode \ - ROM_USBHostMode -#else -#define MAP_USBHostMode \ - USBHostMode -#endif -#ifdef ROM_USBDevMode -#define MAP_USBDevMode \ - ROM_USBDevMode -#else -#define MAP_USBDevMode \ - USBDevMode -#endif -#ifdef ROM_USBPHYPowerOff -#define MAP_USBPHYPowerOff \ - ROM_USBPHYPowerOff -#else -#define MAP_USBPHYPowerOff \ - USBPHYPowerOff -#endif -#ifdef ROM_USBPHYPowerOn -#define MAP_USBPHYPowerOn \ - ROM_USBPHYPowerOn -#else -#define MAP_USBPHYPowerOn \ - USBPHYPowerOn -#endif -#ifdef ROM_USBOTGMode -#define MAP_USBOTGMode \ - ROM_USBOTGMode -#else -#define MAP_USBOTGMode \ - USBOTGMode -#endif -#ifdef ROM_USBHostRequestINClear -#define MAP_USBHostRequestINClear \ - ROM_USBHostRequestINClear -#else -#define MAP_USBHostRequestINClear \ - USBHostRequestINClear -#endif -#ifdef ROM_USBNumEndpointsGet -#define MAP_USBNumEndpointsGet \ - ROM_USBNumEndpointsGet -#else -#define MAP_USBNumEndpointsGet \ - USBNumEndpointsGet -#endif -#ifdef ROM_USBClockDisable -#define MAP_USBClockDisable \ - ROM_USBClockDisable -#else -#define MAP_USBClockDisable \ - USBClockDisable -#endif -#ifdef ROM_USBClockEnable -#define MAP_USBClockEnable \ - ROM_USBClockEnable -#else -#define MAP_USBClockEnable \ - USBClockEnable -#endif -#ifdef ROM_USBControllerVersion -#define MAP_USBControllerVersion \ - ROM_USBControllerVersion -#else -#define MAP_USBControllerVersion \ - USBControllerVersion -#endif -#ifdef ROM_USBDevLPMConfig -#define MAP_USBDevLPMConfig \ - ROM_USBDevLPMConfig -#else -#define MAP_USBDevLPMConfig \ - USBDevLPMConfig -#endif -#ifdef ROM_USBDevLPMDisable -#define MAP_USBDevLPMDisable \ - ROM_USBDevLPMDisable -#else -#define MAP_USBDevLPMDisable \ - USBDevLPMDisable -#endif -#ifdef ROM_USBDevLPMEnable -#define MAP_USBDevLPMEnable \ - ROM_USBDevLPMEnable -#else -#define MAP_USBDevLPMEnable \ - USBDevLPMEnable -#endif -#ifdef ROM_USBDevLPMRemoteWake -#define MAP_USBDevLPMRemoteWake \ - ROM_USBDevLPMRemoteWake -#else -#define MAP_USBDevLPMRemoteWake \ - USBDevLPMRemoteWake -#endif -#ifdef ROM_USBDevSpeedGet -#define MAP_USBDevSpeedGet \ - ROM_USBDevSpeedGet -#else -#define MAP_USBDevSpeedGet \ - USBDevSpeedGet -#endif -#ifdef ROM_USBDMAChannelAddressGet -#define MAP_USBDMAChannelAddressGet \ - ROM_USBDMAChannelAddressGet -#else -#define MAP_USBDMAChannelAddressGet \ - USBDMAChannelAddressGet -#endif -#ifdef ROM_USBDMAChannelAddressSet -#define MAP_USBDMAChannelAddressSet \ - ROM_USBDMAChannelAddressSet -#else -#define MAP_USBDMAChannelAddressSet \ - USBDMAChannelAddressSet -#endif -#ifdef ROM_USBDMAChannelConfigSet -#define MAP_USBDMAChannelConfigSet \ - ROM_USBDMAChannelConfigSet -#else -#define MAP_USBDMAChannelConfigSet \ - USBDMAChannelConfigSet -#endif -#ifdef ROM_USBDMAChannelDisable -#define MAP_USBDMAChannelDisable \ - ROM_USBDMAChannelDisable -#else -#define MAP_USBDMAChannelDisable \ - USBDMAChannelDisable -#endif -#ifdef ROM_USBDMAChannelEnable -#define MAP_USBDMAChannelEnable \ - ROM_USBDMAChannelEnable -#else -#define MAP_USBDMAChannelEnable \ - USBDMAChannelEnable -#endif -#ifdef ROM_USBDMAChannelIntDisable -#define MAP_USBDMAChannelIntDisable \ - ROM_USBDMAChannelIntDisable -#else -#define MAP_USBDMAChannelIntDisable \ - USBDMAChannelIntDisable -#endif -#ifdef ROM_USBDMAChannelIntEnable -#define MAP_USBDMAChannelIntEnable \ - ROM_USBDMAChannelIntEnable -#else -#define MAP_USBDMAChannelIntEnable \ - USBDMAChannelIntEnable -#endif -#ifdef ROM_USBDMAChannelCountGet -#define MAP_USBDMAChannelCountGet \ - ROM_USBDMAChannelCountGet -#else -#define MAP_USBDMAChannelCountGet \ - USBDMAChannelCountGet -#endif -#ifdef ROM_USBDMAChannelCountSet -#define MAP_USBDMAChannelCountSet \ - ROM_USBDMAChannelCountSet -#else -#define MAP_USBDMAChannelCountSet \ - USBDMAChannelCountSet -#endif -#ifdef ROM_USBDMAChannelIntStatus -#define MAP_USBDMAChannelIntStatus \ - ROM_USBDMAChannelIntStatus -#else -#define MAP_USBDMAChannelIntStatus \ - USBDMAChannelIntStatus -#endif -#ifdef ROM_USBDMAChannelStatus -#define MAP_USBDMAChannelStatus \ - ROM_USBDMAChannelStatus -#else -#define MAP_USBDMAChannelStatus \ - USBDMAChannelStatus -#endif -#ifdef ROM_USBDMAChannelStatusClear -#define MAP_USBDMAChannelStatusClear \ - ROM_USBDMAChannelStatusClear -#else -#define MAP_USBDMAChannelStatusClear \ - USBDMAChannelStatusClear -#endif -#ifdef ROM_USBHighSpeed -#define MAP_USBHighSpeed \ - ROM_USBHighSpeed -#else -#define MAP_USBHighSpeed \ - USBHighSpeed -#endif -#ifdef ROM_USBHostEndpointPing -#define MAP_USBHostEndpointPing \ - ROM_USBHostEndpointPing -#else -#define MAP_USBHostEndpointPing \ - USBHostEndpointPing -#endif -#ifdef ROM_USBHostEndpointSpeed -#define MAP_USBHostEndpointSpeed \ - ROM_USBHostEndpointSpeed -#else -#define MAP_USBHostEndpointSpeed \ - USBHostEndpointSpeed -#endif -#ifdef ROM_USBHostLPMConfig -#define MAP_USBHostLPMConfig \ - ROM_USBHostLPMConfig -#else -#define MAP_USBHostLPMConfig \ - USBHostLPMConfig -#endif -#ifdef ROM_USBHostLPMResume -#define MAP_USBHostLPMResume \ - ROM_USBHostLPMResume -#else -#define MAP_USBHostLPMResume \ - USBHostLPMResume -#endif -#ifdef ROM_USBHostLPMSend -#define MAP_USBHostLPMSend \ - ROM_USBHostLPMSend -#else -#define MAP_USBHostLPMSend \ - USBHostLPMSend -#endif -#ifdef ROM_USBLPMIntDisable -#define MAP_USBLPMIntDisable \ - ROM_USBLPMIntDisable -#else -#define MAP_USBLPMIntDisable \ - USBLPMIntDisable -#endif -#ifdef ROM_USBLPMIntEnable -#define MAP_USBLPMIntEnable \ - ROM_USBLPMIntEnable -#else -#define MAP_USBLPMIntEnable \ - USBLPMIntEnable -#endif -#ifdef ROM_USBLPMIntStatus -#define MAP_USBLPMIntStatus \ - ROM_USBLPMIntStatus -#else -#define MAP_USBLPMIntStatus \ - USBLPMIntStatus -#endif -#ifdef ROM_USBLPMLinkStateGet -#define MAP_USBLPMLinkStateGet \ - ROM_USBLPMLinkStateGet -#else -#define MAP_USBLPMLinkStateGet \ - USBLPMLinkStateGet -#endif -#ifdef ROM_USBEndpointPacketCountSet -#define MAP_USBEndpointPacketCountSet \ - ROM_USBEndpointPacketCountSet -#else -#define MAP_USBEndpointPacketCountSet \ - USBEndpointPacketCountSet -#endif -#ifdef ROM_USBULPIConfig -#define MAP_USBULPIConfig \ - ROM_USBULPIConfig -#else -#define MAP_USBULPIConfig \ - USBULPIConfig -#endif -#ifdef ROM_USBULPIDisable -#define MAP_USBULPIDisable \ - ROM_USBULPIDisable -#else -#define MAP_USBULPIDisable \ - USBULPIDisable -#endif -#ifdef ROM_USBULPIEnable -#define MAP_USBULPIEnable \ - ROM_USBULPIEnable -#else -#define MAP_USBULPIEnable \ - USBULPIEnable -#endif -#ifdef ROM_USBULPIRegRead -#define MAP_USBULPIRegRead \ - ROM_USBULPIRegRead -#else -#define MAP_USBULPIRegRead \ - USBULPIRegRead -#endif -#ifdef ROM_USBULPIRegWrite -#define MAP_USBULPIRegWrite \ - ROM_USBULPIRegWrite -#else -#define MAP_USBULPIRegWrite \ - USBULPIRegWrite -#endif -#ifdef ROM_USBOTGSessionRequest -#define MAP_USBOTGSessionRequest \ - ROM_USBOTGSessionRequest -#else -#define MAP_USBOTGSessionRequest \ - USBOTGSessionRequest -#endif -#ifdef ROM_USBDMANumChannels -#define MAP_USBDMANumChannels \ - ROM_USBDMANumChannels -#else -#define MAP_USBDMANumChannels \ - USBDMANumChannels -#endif -#ifdef ROM_USBEndpointDMAConfigSet -#define MAP_USBEndpointDMAConfigSet \ - ROM_USBEndpointDMAConfigSet -#else -#define MAP_USBEndpointDMAConfigSet \ - USBEndpointDMAConfigSet -#endif -#ifdef ROM_USBLPMRemoteWakeEnabled -#define MAP_USBLPMRemoteWakeEnabled \ - ROM_USBLPMRemoteWakeEnabled -#else -#define MAP_USBLPMRemoteWakeEnabled \ - USBLPMRemoteWakeEnabled -#endif -#ifdef ROM_USBModeConfig -#define MAP_USBModeConfig \ - ROM_USBModeConfig -#else -#define MAP_USBModeConfig \ - USBModeConfig -#endif - -//***************************************************************************** -// -// Macros for the Watchdog API. -// -//***************************************************************************** -#ifdef ROM_WatchdogIntClear -#define MAP_WatchdogIntClear \ - ROM_WatchdogIntClear -#else -#define MAP_WatchdogIntClear \ - WatchdogIntClear -#endif -#ifdef ROM_WatchdogRunning -#define MAP_WatchdogRunning \ - ROM_WatchdogRunning -#else -#define MAP_WatchdogRunning \ - WatchdogRunning -#endif -#ifdef ROM_WatchdogEnable -#define MAP_WatchdogEnable \ - ROM_WatchdogEnable -#else -#define MAP_WatchdogEnable \ - WatchdogEnable -#endif -#ifdef ROM_WatchdogResetEnable -#define MAP_WatchdogResetEnable \ - ROM_WatchdogResetEnable -#else -#define MAP_WatchdogResetEnable \ - WatchdogResetEnable -#endif -#ifdef ROM_WatchdogResetDisable -#define MAP_WatchdogResetDisable \ - ROM_WatchdogResetDisable -#else -#define MAP_WatchdogResetDisable \ - WatchdogResetDisable -#endif -#ifdef ROM_WatchdogLock -#define MAP_WatchdogLock \ - ROM_WatchdogLock -#else -#define MAP_WatchdogLock \ - WatchdogLock -#endif -#ifdef ROM_WatchdogUnlock -#define MAP_WatchdogUnlock \ - ROM_WatchdogUnlock -#else -#define MAP_WatchdogUnlock \ - WatchdogUnlock -#endif -#ifdef ROM_WatchdogLockState -#define MAP_WatchdogLockState \ - ROM_WatchdogLockState -#else -#define MAP_WatchdogLockState \ - WatchdogLockState -#endif -#ifdef ROM_WatchdogReloadSet -#define MAP_WatchdogReloadSet \ - ROM_WatchdogReloadSet -#else -#define MAP_WatchdogReloadSet \ - WatchdogReloadSet -#endif -#ifdef ROM_WatchdogReloadGet -#define MAP_WatchdogReloadGet \ - ROM_WatchdogReloadGet -#else -#define MAP_WatchdogReloadGet \ - WatchdogReloadGet -#endif -#ifdef ROM_WatchdogValueGet -#define MAP_WatchdogValueGet \ - ROM_WatchdogValueGet -#else -#define MAP_WatchdogValueGet \ - WatchdogValueGet -#endif -#ifdef ROM_WatchdogIntEnable -#define MAP_WatchdogIntEnable \ - ROM_WatchdogIntEnable -#else -#define MAP_WatchdogIntEnable \ - WatchdogIntEnable -#endif -#ifdef ROM_WatchdogIntStatus -#define MAP_WatchdogIntStatus \ - ROM_WatchdogIntStatus -#else -#define MAP_WatchdogIntStatus \ - WatchdogIntStatus -#endif -#ifdef ROM_WatchdogStallEnable -#define MAP_WatchdogStallEnable \ - ROM_WatchdogStallEnable -#else -#define MAP_WatchdogStallEnable \ - WatchdogStallEnable -#endif -#ifdef ROM_WatchdogStallDisable -#define MAP_WatchdogStallDisable \ - ROM_WatchdogStallDisable -#else -#define MAP_WatchdogStallDisable \ - WatchdogStallDisable -#endif -#ifdef ROM_WatchdogIntTypeSet -#define MAP_WatchdogIntTypeSet \ - ROM_WatchdogIntTypeSet -#else -#define MAP_WatchdogIntTypeSet \ - WatchdogIntTypeSet -#endif - -//***************************************************************************** -// -// Macros for the Software API. -// -//***************************************************************************** -#ifdef ROM_Crc16Array -#define MAP_Crc16Array \ - ROM_Crc16Array -#else -#define MAP_Crc16Array \ - Crc16Array -#endif -#ifdef ROM_Crc16Array3 -#define MAP_Crc16Array3 \ - ROM_Crc16Array3 -#else -#define MAP_Crc16Array3 \ - Crc16Array3 -#endif -#ifdef ROM_Crc16 -#define MAP_Crc16 \ - ROM_Crc16 -#else -#define MAP_Crc16 \ - Crc16 -#endif -#ifdef ROM_Crc8CCITT -#define MAP_Crc8CCITT \ - ROM_Crc8CCITT -#else -#define MAP_Crc8CCITT \ - Crc8CCITT -#endif -#ifdef ROM_Crc32 -#define MAP_Crc32 \ - ROM_Crc32 -#else -#define MAP_Crc32 \ - Crc32 -#endif - -#endif // __DRIVERLIB_ROM_MAP_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/rtos_bindings.h b/bsp/tm4c129x-dk/libraries/driverlib/rtos_bindings.h deleted file mode 100644 index 90762502c02e9506d6a073977c96c323a7e94f27..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/rtos_bindings.h +++ /dev/null @@ -1,108 +0,0 @@ -//***************************************************************************** -// -// rtos_bindings.h - Macros intended to aid porting of TivaWare modules -// for use with an RTOS. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_RTOS_BINDINGS_H__ -#define __DRIVERLIB_RTOS_BINDINGS_H__ - -#ifdef USE_RTOS -//***************************************************************************** -// -// If an RTOS is in use, implement a header file called "tiva_rtos.h" -// which contains RTOS-specific versions of each of the macros defined below -// and make sure it appears on the include path set when you build your -// project. -// -// Note that there is no default implementation of this header file included -// in TivaWare - it is your responsibility to create it specifically for -// your RTOS. -// -//***************************************************************************** -#include "tiva_rtos.h" - -#else -//***************************************************************************** -// -// When no RTOS is in use, the follow macros compile to either nothing or a -// minimal implementation that works in a bare-metal environment. -// -// Each of these macros must be redefined in tiva_rtos.h if you are using -// TivaWare under an RTOS. -// -//***************************************************************************** - -//***************************************************************************** -// -// A simple macro used to yield within polling loops. In the default, non-RTOS -// implementation, this compiles to nothing. -// -//***************************************************************************** -#define OS_YIELD() - -//***************************************************************************** -// -// A simple macro around the SysCtlDelay function. The parameter is the number -// of 3 cycle loops to wait before returning (as for SysCtlDelay). In an RTOS -// implementation, this could be replaced with an OS delay call with -// appropriate parameter scaling. -// -//***************************************************************************** -#define OS_DELAY(ul3Cycles) MAP_SysCtlDelay(ul3Cycles) - -//***************************************************************************** -// -// Wrappers around low level interrupt control functions. For information -// on each of these functions, please see the appropriate API documentation -// for the DriverLib Interrupt driver. -// -// The macros defined here represent interrupt-control functions that may be -// called from within TivaWare code. It is expected that application -// code will use RTOS-specific functions to control interrupt priority, to -// pend interrupts and to perform runtime vector manipulation. As a result, -// no macros are defined to wrap any of these functions from interrupt.c. -// -//***************************************************************************** -#define OS_INT_MASTER_ENABLE() MAP_IntMasterEnable() -#define OS_INT_MASTER_DISABLE() MAP_IntMasterDisable() -#define OS_INT_DISABLE(ui32IntID) MAP_IntDisable(ui32IntID) -#define OS_INT_ENABLE(ui32IntID) MAP_IntEnable(ui32IntID) - -#endif // USE_RTOS - -#endif // __DRIVERLIB_RTOS_BINDINGS_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/shamd5.c b/bsp/tm4c129x-dk/libraries/driverlib/shamd5.c deleted file mode 100644 index d748ac4bb5310b48399d428d9f0a1d2dbc4506d6..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/shamd5.c +++ /dev/null @@ -1,1092 +0,0 @@ -//***************************************************************************** -// -// shamd5.c - Driver for the SHA/MD5 module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_nvic.h" -#include "inc/hw_shamd5.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/shamd5.h" - -//***************************************************************************** -// -//! \addtogroup shamd5_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -//! Resets the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function performs a soft-reset of the SHA/MD5 module using the -//! SYSCONFIG register. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5Reset(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Set the soft-reset bit. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_SOFTRESET; - - // - // Wait for the reset to complete. - // - while((HWREG(ui32Base + SHAMD5_O_SYSSTATUS) & - SHAMD5_SYSSTATUS_RESETDONE) == 0) - { - } - - // - // Force idle mode. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) = - ((HWREG(ui32Base + SHAMD5_O_SYSCONFIG) & ~SHAMD5_SYSCONFIG_SIDLE_M) | - SHAMD5_SYSCONFIG_SIDLE_FORCE); -} - -//***************************************************************************** -// -//! Enables the uDMA requests in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function configures the DMA options of the SHA/MD5 module. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5DMAEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the new configuration into the register. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= - SHAMD5_SYSCONFIG_SADVANCED | SHAMD5_SYSCONFIG_DMA_EN; -} - -//***************************************************************************** -// -//! Disables the uDMA requests in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function configures the DMA options of the SHA/MD5 module. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5DMADisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the new configuration into the register. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= - ~(SHAMD5_SYSCONFIG_SADVANCED | SHAMD5_SYSCONFIG_DMA_EN); -} - -//***************************************************************************** -// -//! Get the interrupt status of the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the current value of the IRQSTATUS register. The -//! value will be a logical OR of the following: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return Interrupt status -// -//***************************************************************************** -uint32_t -SHAMD5IntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Status, ui32Enable, ui32Temp; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Return the value of the IRQSTATUS register. - // - ui32Status = HWREG(ui32Base + SHAMD5_O_IRQSTATUS); - if(bMasked) - { - ui32Enable = HWREG(ui32Base + SHAMD5_O_IRQENABLE); - ui32Temp = HWREG(ui32Base + SHAMD5_O_DMAMIS); - return((ui32Status & ui32Enable) | - ((ui32Temp & 0x00000001) << 19) | - ((ui32Temp & 0x00000002) << 16) | - ((ui32Temp & 0x00000004) << 14)); - } - else - { - ui32Temp = HWREG(ui32Base + SHAMD5_O_DMARIS); - return(ui32Status | - ((ui32Temp & 0x00000001) << 19) | - ((ui32Temp & 0x00000002) << 16) | - ((ui32Temp & 0x00000004) << 14)); - } -} - -//***************************************************************************** -// -//! Enable interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to enable. -//! -//! This function enables interrupt sources in the SHA/MD5 module. -//! ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Enable the interrupt sources. - // - HWREG(ui32Base + SHAMD5_O_DMAIM) |= (((ui32IntFlags & 0x00010000) >> 14) | - ((ui32IntFlags & 0x00020000) >> 16) | - ((ui32IntFlags & 0x00040000) >> 19)); - HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; - - // - // Enable all interrupts. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_IT_EN; -} - -//***************************************************************************** -// -//! Disable interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to disable. -//! -//! \e ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Clear the corresponding flags disabling the interrupt sources. - // - HWREG(ui32Base + SHAMD5_O_DMAIM) &= ~(((ui32IntFlags & 0x00010000) >> 14) | - ((ui32IntFlags & 0x00020000) >> 16) | - ((ui32IntFlags & 0x00040000) >> 19)); - HWREG(ui32Base + SHAMD5_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); - - // - // If there are no interrupts enabled, then disable all interrupts. - // - if(HWREG(ui32Base + SHAMD5_O_IRQENABLE) == 0x0) - { - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= ~SHAMD5_SYSCONFIG_IT_EN; - } -} - -//***************************************************************************** -// -//! Clears interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to disable. -//! -//! \e ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Clear the corresponding flags disabling the interrupt sources. - // - HWREG(ui32Base + SHAMD5_O_DMAIC) = (((ui32IntFlags & 0x00010000) >> 14) | - ((ui32IntFlags & 0x00020000) >> 16) | - ((ui32IntFlags & 0x00040000) >> 19)); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled SHA/MD5 interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables SHA/MD5 interrupts on the interrupt controller; -//! specific SHA/MD5 interrupt sources must be enabled using -//! SHAMD5IntEnable(). The interrupt handler being registered must clear -//! the source of the interrupt using SHAMD5IntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() should be used to enable SHA/MD5 interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_SHA0_TM4C129, pfnHandler); - - // - // Enable the interrupt - // - IntEnable(INT_SHA0_TM4C129); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_SHA0_TM4C129); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_SHA0_TM4C129); -} - -//***************************************************************************** -// -//! Write the hash length to the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32Length is the hash length in bytes. -//! -//! This function writes the length of the hash data of the current operation -//! to the SHA/MD5 module. The value must be a multiple of 64 if the close -//! hash is not set in the mode register. -//! -//! \note When this register is written, hash processing is triggered. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Set the LENGTH register and start processing. - // - HWREG(ui32Base + SHAMD5_O_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Writes the mode in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32Mode is the mode of the SHA/MD5 module. -//! -//! This function writes the mode register configuring the SHA/MD5 module. -//! -//! The ui32Mode parameter is a bit-wise OR of values: -//! -//! - \b SHAMD5_ALGO_MD5 - Regular hash with MD5 -//! - \b SHAMD5_ALGO_SHA1 - Regular hash with SHA-1 -//! - \b SHAMD5_ALGO_SHA224 - Regular hash with SHA-224 -//! - \b SHAMD5_ALGO_SHA256 - Regular hash with SHA-256 -//! - \b SHAMD5_ALGO_HMAC_MD5 - HMAC with MD5 -//! - \b SHAMD5_ALGO_HMAC_SHA1 - HMAC with SHA-1 -//! - \b SHAMD5_ALGO_HMAC_SHA224 - HMAC with SHA-224 -//! - \b SHAMD5_ALGO_HMAC_SHA256 - HMAC with SHA-256 -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32Mode == SHAMD5_ALGO_MD5) || - (ui32Mode == SHAMD5_ALGO_SHA1) || - (ui32Mode == SHAMD5_ALGO_SHA224) || - (ui32Mode == SHAMD5_ALGO_SHA256) || - (ui32Mode == SHAMD5_ALGO_HMAC_MD5) || - (ui32Mode == SHAMD5_ALGO_HMAC_SHA1) || - (ui32Mode == SHAMD5_ALGO_HMAC_SHA224) || - (ui32Mode == SHAMD5_ALGO_HMAC_SHA256)); - - // - // Write the value in the MODE register. - // - HWREG(ui32Base + SHAMD5_O_MODE) = ui32Mode; -} - -//***************************************************************************** -// -//! Perform a non-blocking write of 16 words of data to the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Src is the pointer to the 16-word array of data that will be -//! written. -//! -//! This function writes 16 words of data into the data register regardless -//! of whether or not the module is ready to accept the data. -//! -//! \return This function returns true if the write completed successfully. -//! It returns false if the module was not ready. -// -//***************************************************************************** -bool -SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src) -{ - uint32_t ui32Counter; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Check that the SHA/MD5 module is ready for data. If not, return false. - // - if((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0) - { - return(false); - } - - // - // Write the 16 words of data. - // - for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4) - { - HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++; - } - - // - // Return true as a sign of successfully completing the function. - // - return(true); -} - -//***************************************************************************** -// -//! Perform a blocking write of 16 words of data to the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Src is the pointer to the 16-word array of data that will be -//! written. -//! -//! This function does not return until the module is ready to accept data and -//! the data has been written. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src) -{ - uint32_t ui32Counter; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Wait for the module to be ready to accept data. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0) - { - } - - // - // Write the 16 words of data. - // - for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4) - { - HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++; - } -} - -//***************************************************************************** -// -//! Reads the result of a hashing operation. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Dest is the pointer to the 16-word array of data that will be -//! written. -//! -//! This function does not return until the module is ready to accept data and -//! the data has been written. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest) -{ - uint32_t ui32Idx, ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Determine the number of bytes in the result, based on the hash type. - // - switch(HWREG(ui32Base + SHAMD5_O_MODE) & SHAMD5_MODE_ALGO_M) - { - // - // The MD5 hash is being used. - // - case SHAMD5_MODE_ALGO_MD5: - { - // - // There are 16 bytes in the MD5 hash. - // - ui32Count = 16; - - // - // Done. - // - break; - } - - // - // The SHA-1 hash is being used. - // - case SHAMD5_MODE_ALGO_SHA1: - { - // - // There are 20 bytes in the SHA-1 hash. - // - ui32Count = 20; - - // - // Done. - // - break; - } - - // - // The SHA-224 hash is being used. - // - case SHAMD5_MODE_ALGO_SHA224: - { - // - // There are 28 bytes in the SHA-224 hash. - // - ui32Count = 28; - - // - // Done. - // - break; - } - - // - // The SHA-256 hash is being used. - // - case SHAMD5_MODE_ALGO_SHA256: - { - // - // There are 32 bytes in the SHA-256 hash. - // - ui32Count = 32; - - // - // Done. - // - break; - } - - // - // The hash type is not recognized. - // - default: - { - // - // Return without reading a result since the hardware appears to be - // misconfigured. - // - return; - } - } - - // - // Read the hash result. - // - for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4) - { - *pui32Dest++ = HWREG(ui32Base + SHAMD5_O_IDIGEST_A + ui32Idx); - } -} - -//***************************************************************************** -// -//! Writes multiple words of data into the SHA/MD5 data registers. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32DataSrc is a pointer to an array of data to be written. -//! \param ui32DataLength is the length of the data to be written in bytes. -//! -//! This function writes a variable number of words into the SHA/MD5 data -//! registers. The function waits for each block of data to be processed -//! before another is written. The \e ui32DataLength parameter must be a -//! multiple of 4 to fall on a word boundry. -//! -//! \note This function is used by SHAMD5DataProcess() and SHAMD5HMACProcess() -//! to process data. -//! -//! \return None. -// -//***************************************************************************** -static void -_SHAMD5DataWriteMultiple(uint32_t ui32Base, uint32_t *pui32DataSrc, - uint32_t ui32DataLength) -{ - uint32_t ui32Idx, ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Calculate the number of blocks of data. - // - ui32Count = ui32DataLength / 64; - - // - // Loop through all the blocks and write them into the data registers - // making sure to block additional operations until we can write the - // next 16 words. - // - for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++) - { - // - // Write the block of data. - // - SHAMD5DataWrite(ui32Base, pui32DataSrc); - - // - // Increment the pointer to next block of data. - // - pui32DataSrc += 16; - } - - // - // Calculate the remaining bytes of data that don't make up a full block. - // - ui32Count = ui32DataLength % 64; - - // - // If there are bytes that do not make up a whole block, then - // write them separately. - // - if(ui32Count) - { - // - // Wait until the engine has finished processing the previous block. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & - SHAMD5_INT_INPUT_READY) == 0) - { - } - - // - // Loop through the remaining words. - // - for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4) - { - // - // Write the word into the data register. - // - HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Idx) = *pui32DataSrc++; - } - } -} - -//***************************************************************************** -// -//! Compute a hash using the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32DataSrc is a pointer to an array of data that contains the -//! data that will be hashed. -//! \param ui32DataLength specifies the length of the data to be hashed in -//! bytes. -//! \param pui32HashResult is a pointer to an array that holds the result -//! of the hashing operation. -//! -//! This function computes the hash of an array of data using the SHA/MD5 -//! module. -//! -//! The length of the hash result is dependent on the algorithm that is in use. -//! The following table shows the correct array size for each algorithm: -//! -//! ----------------------------------------- -//! | Algorithm | Number of Words in Result | -//! ----------------------------------------- -//! | MD5 | 4 Words (128 bits) | -//! | SHA-1 | 5 Words (160 bits) | -//! | SHA-224 | 7 Words (224 bits) | -//! | SHA-256 | 8 Words (256 bits) | -//! ----------------------------------------- -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5DataProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, - uint32_t ui32DataLength, uint32_t *pui32HashResult) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32DataLength % 64) == 0); - - // - // Wait for the context to be ready before writing the mode. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) == - 0) - { - } - - // - // Write the length. - // - SHAMD5HashLengthSet(ui32Base, ui32DataLength); - - // - // Write the data. - // - _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength); - - // - // Wait for the output to be ready. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) == - 0) - { - } - - // - // Read the result. - // - SHAMD5ResultRead(ui32Base, pui32HashResult); -} - -//***************************************************************************** -// -//! Compute a HMAC with key pre-processing using the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32DataSrc is a pointer to an array of data that contains the -//! data that is to be hashed. -//! \param ui32DataLength specifies the length of the data to be hashed in -//! bytes. -//! \param pui32HashResult is a pointer to an array that holds the result -//! of the hashing operation. -//! -//! This function computes a HMAC with the given data using the SHA/MD5 -//! module with a preprocessed key. -//! -//! The length of the hash result is dependent on the algorithm that is -//! selected with the \e ui32Algo argument. The following table shows the -//! correct array size for each algorithm: -//! -//! ----------------------------------------- -//! | Algorithm | Number of Words in Result | -//! ----------------------------------------- -//! | MD5 | 4 Words (128 bits) | -//! | SHA-1 | 5 Words (160 bits) | -//! | SHA-224 | 7 Words (224 bits) | -//! | SHA-256 | 8 Words (256 bits) | -//! ----------------------------------------- -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5HMACProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, - uint32_t ui32DataLength, uint32_t *pui32HashResult) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Wait for the context to be ready before writing the mode. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) == - 0) - { - } - - // - // Write the length. - // - SHAMD5HashLengthSet(ui32Base, ui32DataLength); - - // - // Write the data in the registers. - // - _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength); - - // - // Wait for the output to be ready. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) == - 0) - { - } - - // - // Read the result. - // - SHAMD5ResultRead(ui32Base, pui32HashResult); -} - -//***************************************************************************** -// -//! Process an HMAC key using the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Key is a pointer to an array that contains the key to be -//! processed. -//! \param pui32PPKey is the pointer to the array that contains the -//! pre-processed key. -//! -//! This function processes an HMAC key using the SHA/MD5. The resultant -//! pre-processed key can then be used with later HMAC operations to speed -//! processing time. -//! -//! The \e pui32Key array must be 16 words (512 bits) long. If the key is less -//! than 512 bits, it must be padded with zeros. The \e pui32PPKey array must -//! each be 16 words (512 bits) long. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint32_t *pui32Key, - uint32_t *pui32PPKey) -{ - uint32_t ui32Index; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Wait for the context to be ready before writing the mode. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) == - 0) - { - } - - // - // Write the HMAC key. - // - for(ui32Index = 0; ui32Index < 64; ui32Index += 4) - { - HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index) = *pui32Key++; - } - - // - // Set the flag to cause the HMAC key to be pre-processed. - // - HWREG(ui32Base + SHAMD5_O_MODE) |= SHAMD5_MODE_HMAC_KEY_PROC; - - // - // Set the length to zero to start the HMAC key pre-processing. - // - HWREG(ui32Base + SHAMD5_O_LENGTH) = 0; - - // - // Wait for key to be processed. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) == - 0) - { - } - - // - // Read the pre-processed key from the SHA/MD5 module. - // - for(ui32Index = 0; ui32Index < 64; ui32Index += 4) - { - *pui32PPKey++ = HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index); - } -} - -//***************************************************************************** -// -//! Writes an HMAC key to the digest registers in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Src is the pointer to the 16-word array of the HMAC key. -//! -//! This function is used to write HMAC key to the digest registers for -//! key preprocessing. The size of pui32Src must be 512 bytes. If the key is -//! less than 512 bytes, then it must be padded with zeros. -//! -//! \note It is recommended to use the SHAMD5IntStatus() function to check -//! whether the context is ready before writing the key. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5HMACKeySet(uint32_t ui32Base, uint32_t *pui32Src) -{ - uint32_t ui32Idx; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the key to the digest registers. - // - for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4) - { - HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++; - } - - // - // Configure the SHA engine for HMAC operation. - // - HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH | - SHAMD5_MODE_HMAC_KEY_PROC | - SHAMD5_MODE_CLOSE_HASH); -} - -//***************************************************************************** -// -//! Writes a pre-processed HMAC key to the digest registers in the SHA/MD5 -//! module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Src is the pointer to the 16-word array of the HMAC key. -//! -//! This function is used to write HMAC key to the digest registers for -//! key preprocessing. The size of pui32Src must be 512 bytes. If the key is -//! less than 512 bytes, then it must be padded with zeros. -//! -//! \note It is recommended to use the SHAMD5IntStatus() function to check -//! whether the context is ready before writing the key. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5HMACPPKeySet(uint32_t ui32Base, uint32_t *pui32Src) -{ - uint32_t ui32Idx; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the key to the digest registers. - // - for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4) - { - HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++; - } - - // - // Configure the SHA engine to continue the HMAC. - // - HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH | - SHAMD5_MODE_CLOSE_HASH); - - // - // Write the digest count to 64 to account for the preprocessed key. - // - HWREG(ui32Base + SHAMD5_O_DIGEST_COUNT) = 64; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/shamd5.h b/bsp/tm4c129x-dk/libraries/driverlib/shamd5.h deleted file mode 100644 index 3b0e793b4f53bcd5667d94ea78828f1a2cfe77cf..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/shamd5.h +++ /dev/null @@ -1,127 +0,0 @@ -//***************************************************************************** -// -// shamd5.h - Defines and Macros for the SHA/MD5. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_SHAMD5_H__ -#define __DRIVERLIB_SHAMD5_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used to specify the algorithm in use in the -// SHA/MD5 module. -// -//***************************************************************************** -#define SHAMD5_ALGO_MD5 0x00000018 -#define SHAMD5_ALGO_SHA1 0x0000001a -#define SHAMD5_ALGO_SHA224 0x0000001c -#define SHAMD5_ALGO_SHA256 0x0000001e -#define SHAMD5_ALGO_HMAC_MD5 0x00000000 -#define SHAMD5_ALGO_HMAC_SHA1 0x00000002 -#define SHAMD5_ALGO_HMAC_SHA224 0x00000004 -#define SHAMD5_ALGO_HMAC_SHA256 0x00000006 - -//***************************************************************************** -// -// The following defines are used to represent the different interrupt sources -// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and -// SHAMD5BlockOnIntStatus() functions. -// -//***************************************************************************** -#define SHAMD5_INT_CONTEXT_READY \ - 0x00000008 -#define SHAMD5_INT_PARTHASH_READY \ - 0x00000004 -#define SHAMD5_INT_INPUT_READY 0x00000002 -#define SHAMD5_INT_OUTPUT_READY 0x00000001 -#define SHAMD5_INT_DMA_CONTEXT_IN \ - 0x00080000 -#define SHAMD5_INT_DMA_DATA_IN 0x00020000 -#define SHAMD5_INT_DMA_CONTEXT_OUT \ - 0x00010000 - -//***************************************************************************** -// -// Function prototypes -// -//***************************************************************************** -extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode); -extern void SHAMD5DataProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, - uint32_t ui32DataLength, - uint32_t *pui32HashResult); -extern void SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src); -extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src); -extern void SHAMD5DMADisable(uint32_t ui32Base); -extern void SHAMD5DMAEnable(uint32_t ui32Base); -extern void SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length); -extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint32_t *pui32Src); -extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint32_t *pui32Key, - uint32_t *pui32PPKey); -extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint32_t *pui32Src); -extern void SHAMD5HMACProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, - uint32_t ui32DataLength, - uint32_t *pui32HashResult); -extern void SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SHAMD5IntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked); -extern void SHAMD5IntUnregister(uint32_t ui32Base); -extern void SHAMD5Reset(uint32_t ui32Base); -extern void SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_SHAMD5_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/ssi.c b/bsp/tm4c129x-dk/libraries/driverlib/ssi.c deleted file mode 100644 index cf7a2d3bc2aa087a837b840ebc0c849f4e9aa8c6..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/ssi.c +++ /dev/null @@ -1,1150 +0,0 @@ -//***************************************************************************** -// -// ssi.c - Driver for Synchronous Serial Interface. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ssi_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_ssi.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/ssi.h" - -//***************************************************************************** -// -// A mapping of timer base address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32SSIIntMap[][2] = -{ - { SSI0_BASE, INT_SSI0_TM4C123 }, - { SSI1_BASE, INT_SSI1_TM4C123 }, - { SSI2_BASE, INT_SSI2_TM4C123 }, - { SSI3_BASE, INT_SSI3_TM4C123 }, -}; -static const uint_fast8_t g_ui8SSIIntMapRows = - sizeof(g_ppui32SSIIntMap) / sizeof(g_ppui32SSIIntMap[0]); - -static const uint32_t g_ppui32SSIIntMapSnowflake[][2] = -{ - { SSI0_BASE, INT_SSI0_TM4C129 }, - { SSI1_BASE, INT_SSI1_TM4C129 }, - { SSI2_BASE, INT_SSI2_TM4C129 }, - { SSI3_BASE, INT_SSI3_TM4C129 }, -}; -static const uint_fast8_t g_ui8SSIIntMapSnowflakeRows = - sizeof(g_ppui32SSIIntMapSnowflake) / sizeof(g_ppui32SSIIntMapSnowflake[0]); - -//***************************************************************************** -// -//! \internal -//! Checks an SSI base address. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! This function determines if a SSI module base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_SSIBaseValid(uint32_t ui32Base) -{ - return((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE) || - (ui32Base == SSI2_BASE) || (ui32Base == SSI3_BASE)); -} -#endif - -//***************************************************************************** -// -//! Returns the interrupt number of SSI module . -//! -//! \param ui32Base is the base address of the SSI module. -//! -//! This function returns the interrupt number for the SSI module with the base -//! address passed in the \e ui32Base parameter. -//! -//! \return Returns an SSI interrupt number, or 0 if the interrupt does not -//! exist. -// -//***************************************************************************** -static uint32_t -_SSIIntNumberGet(uint32_t ui32Base) -{ - uint_fast8_t ui8Idx, ui8Rows; - const uint32_t (*ppui32SSIIntMap)[2]; - - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - ppui32SSIIntMap = g_ppui32SSIIntMap; - ui8Rows = g_ui8SSIIntMapRows; - - if(CLASS_IS_TM4C129) - { - ppui32SSIIntMap = g_ppui32SSIIntMapSnowflake; - ui8Rows = g_ui8SSIIntMapSnowflakeRows; - } - - // - // Loop through the table that maps SSI base addresses to interrupt - // numbers. - // - for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++) - { - // - // See if this base address matches. - // - if(ppui32SSIIntMap[ui8Idx][0] == ui32Base) - { - // - // Return the corresponding interrupt number. - // - return(ppui32SSIIntMap[ui8Idx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Configures the synchronous serial interface. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32SSIClk is the rate of the clock supplied to the SSI module. -//! \param ui32Protocol specifies the data transfer protocol. -//! \param ui32Mode specifies the mode of operation. -//! \param ui32BitRate specifies the clock rate. -//! \param ui32DataWidth specifies number of bits transferred per frame. -//! -//! This function configures the synchronous serial interface. It sets -//! the SSI protocol, mode of operation, bit rate, and data width. -//! -//! The \e ui32Protocol parameter defines the data frame format. The -//! \e ui32Protocol parameter can be one of the following values: -//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2, -//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. Note that -//! the \b SSI_FRF_NMW option is only available on some devices. Refer to the -//! device data sheet to determine if the Microwire format is supported on -//! a particular device. The Motorola frame formats encode the following -//! polarity and phase configurations: -//! -//! 
-//! Polarity Phase       Mode
-//!   0       0   SSI_FRF_MOTO_MODE_0
-//!   0       1   SSI_FRF_MOTO_MODE_1
-//!   1       0   SSI_FRF_MOTO_MODE_2
-//!   1       1   SSI_FRF_MOTO_MODE_3
-//!
-//! -//! The \e ui32Mode parameter defines the operating mode of the SSI module. -//! The SSI module can operate as a master or slave; if it is a slave, the SSI -//! can be configured to disable output on its serial output line. The -//! \e ui32Mode parameter can be one of the following values: -//! \b SSI_MODE_MASTER, \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD. -//! -//! The \e ui32BitRate parameter defines the bit rate for the SSI. This bit -//! rate must satisfy the following clock ratio criteria: -//! -//! - FSSI >= 2 * bit rate (master mode) -//! - FSSI >= 12 * bit rate (slave modes) -//! -//! where FSSI is the frequency of the clock supplied to the SSI module. Note -//! that there are frequency limits for FSSI that are described in the Bit Rate -//! Generation section of the SSI chapter in the data sheet. -//! -//! The \e ui32DataWidth parameter defines the width of the data transfers and -//! can be a value between 4 and 16, inclusive. -//! -//! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet() for TM4C123x -//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, -//! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the -//! variable call holding the return value of SysCtlClockFreqSet()). -//! -//! \return None. -// -//***************************************************************************** -void -SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, - uint32_t ui32Protocol, uint32_t ui32Mode, - uint32_t ui32BitRate, uint32_t ui32DataWidth) -{ - uint32_t ui32MaxBitRate; - uint32_t ui32RegVal; - uint32_t ui32PreDiv; - uint32_t ui32SCR; - uint32_t ui32SPH_SPO; - - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || - (ui32Protocol == SSI_FRF_MOTO_MODE_1) || - (ui32Protocol == SSI_FRF_MOTO_MODE_2) || - (ui32Protocol == SSI_FRF_MOTO_MODE_3) || - (ui32Protocol == SSI_FRF_TI) || - (ui32Protocol == SSI_FRF_NMW)); - ASSERT((ui32Mode == SSI_MODE_MASTER) || - (ui32Mode == SSI_MODE_SLAVE)); - ASSERT(((ui32Mode == SSI_MODE_MASTER) && - (ui32BitRate <= (ui32SSIClk / 2))) || - ((ui32Mode != SSI_MODE_MASTER) && - (ui32BitRate <= (ui32SSIClk / 12)))); - ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); - ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); - - // - // Set the mode. - // - ui32RegVal = (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; - HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; - - // - // Set the clock predivider. - // - ui32MaxBitRate = ui32SSIClk / ui32BitRate; - ui32PreDiv = 0; - do - { - ui32PreDiv += 2; - ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; - } - while(ui32SCR > 255); - HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; - - // - // Set protocol and clock rate. - // - ui32SPH_SPO = (ui32Protocol & 3) << 6; - ui32Protocol &= SSI_CR0_FRF_M; - ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | - (ui32DataWidth - 1); - HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; -} - -//***************************************************************************** -// -//! Enables the synchronous serial interface. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! This function enables operation of the synchronous serial interface. The -//! synchronous serial interface must be configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -SSIEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Read-modify-write the enable bit. - // - HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE; -} - -//***************************************************************************** -// -//! Disables the synchronous serial interface. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! This function disables operation of the synchronous serial interface. -//! -//! \return None. -// -//***************************************************************************** -void -SSIDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Read-modify-write the enable bit. - // - HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the synchronous serial interface. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pfnHandler is a pointer to the function to be called when the -//! synchronous serial interface interrupt occurs. -//! -//! This function registers the handler to be called when an SSI interrupt -//! occurs. This function enables the global interrupt in the interrupt -//! controller; specific SSI interrupts must be enabled via SSIIntEnable(). If -//! necessary, it is the interrupt handler's responsibility to clear the -//! interrupt source via SSIIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the SSI module. - // - ui32Int = _SSIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the synchronous serial interface interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the synchronous serial interface. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! This function clears the handler to be called when an SSI interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SSIIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the SSI module. - // - ui32Int = _SSIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables individual SSI interrupt sources. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated SSI interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. The \e ui32IntFlags -//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or -//! \b SSI_RXOR values. -//! -//! \return None. -// -//***************************************************************************** -void -SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Enable the specified interrupts. - // - HWREG(ui32Base + SSI_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual SSI interrupt sources. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated SSI interrupt sources. The -//! \e ui32IntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, -//! \b SSI_RXTO, or \b SSI_RXOR values. -//! -//! \return None. -// -//***************************************************************************** -void -SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Disable the specified interrupts. - // - HWREG(ui32Base + SSI_O_IM) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param bMasked is \b false if the raw interrupt status is required or -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the SSI module. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR. -// -//***************************************************************************** -uint32_t -SSIIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + SSI_O_MIS)); - } - else - { - return(HWREG(ui32Base + SSI_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears SSI interrupt sources. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! This function clears the specified SSI interrupt sources so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupts from being triggered again immediately upon exit. The -//! \e ui32IntFlags parameter can consist of either or both the \b SSI_RXTO and -//! \b SSI_RXOR values. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Clear the requested interrupt sources. - // - HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module. If there is no space available in the transmit FIFO, -//! this function waits until there is space available before returning. -//! -//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware, -//! where N is the data width as configured by SSIConfigSetExpClk(). For -//! example, if the interface is configured for 8-bit data width, the upper 24 -//! bits of \e ui32Data are discarded. -//! -//! \return None. -// -//***************************************************************************** -void -SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & - SSI_CR0_DSS_M))) == 0); - - // - // Wait until there is space. - // - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) - { - } - - // - // Write the data to the SSI. - // - HWREG(ui32Base + SSI_O_DR) = ui32Data; -} - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module. If there is no space in the FIFO, then this function -//! returns a zero. -//! -//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware, -//! where N is the data width as configured by SSIConfigSetExpClk(). For -//! example, if the interface is configured for 8-bit data width, the upper 24 -//! bits of \e ui32Data are discarded. -//! -//! \return Returns the number of elements written to the SSI transmit FIFO. -// -//***************************************************************************** -int32_t -SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & - SSI_CR0_DSS_M))) == 0); - - // - // Check for space to write. - // - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) - { - HWREG(ui32Base + SSI_O_DR) = ui32Data; - return(1); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -//! Gets a data element from the SSI receive FIFO. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pui32Data is a pointer to a storage location for data that was -//! received over the SSI interface. -//! -//! This function gets received data from the receive FIFO of the specified -//! SSI module and places that data into the location specified by the -//! \e pui32Data parameter. If there is no data available, this function waits -//! until data is received before returning. -//! -//! \note Only the lower N bits of the value written to \e pui32Data contain -//! valid data, where N is the data width as configured by -//! SSIConfigSetExpClk(). For example, if the interface is configured for -//! 8-bit data width, only the lower 8 bits of the value written to -//! \e pui32Data contain valid data. -//! -//! \return None. -// -//***************************************************************************** -void -SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Wait until there is data to be read. - // - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) - { - } - - // - // Read data from SSI. - // - *pui32Data = HWREG(ui32Base + SSI_O_DR); -} - -//***************************************************************************** -// -//! Gets a data element from the SSI receive FIFO. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pui32Data is a pointer to a storage location for data that was -//! received over the SSI interface. -//! -//! This function gets received data from the receive FIFO of the specified SSI -//! module and places that data into the location specified by the \e ui32Data -//! parameter. If there is no data in the FIFO, then this function returns a -//! zero. -//! -//! \note Only the lower N bits of the value written to \e pui32Data contain -//! valid data, where N is the data width as configured by -//! SSIConfigSetExpClk(). For example, if the interface is configured for -//! 8-bit data width, only the lower 8 bits of the value written to -//! \e pui32Data contain valid data. -//! -//! \return Returns the number of elements read from the SSI receive FIFO. -// -//***************************************************************************** -int32_t -SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Check for data to read. - // - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) - { - *pui32Data = HWREG(ui32Base + SSI_O_DR); - return(1); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -//! Enables SSI DMA operation. -//! -//! \param ui32Base is the base address of the SSI module. -//! \param ui32DMAFlags is a bit mask of the DMA features to enable. -//! -//! This function enables the specified SSI DMA features. The SSI can be -//! configured to use DMA for transmit and/or receive data transfers. -//! The \e ui32DMAFlags parameter is the logical OR of any of the following -//! values: -//! -//! - SSI_DMA_RX - enable DMA for receive -//! - SSI_DMA_TX - enable DMA for transmit -//! -//! \note The uDMA controller must also be set up before DMA can be used -//! with the SSI. -//! -//! \return None. -// -//***************************************************************************** -void -SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Set the requested bits in the SSI DMA control register. - // - HWREG(ui32Base + SSI_O_DMACTL) |= ui32DMAFlags; -} - -//***************************************************************************** -// -//! Disables SSI DMA operation. -//! -//! \param ui32Base is the base address of the SSI module. -//! \param ui32DMAFlags is a bit mask of the DMA features to disable. -//! -//! This function is used to disable SSI DMA features that were enabled -//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The -//! \e ui32DMAFlags parameter is the logical OR of any of the following values: -//! -//! - SSI_DMA_RX - disable DMA for receive -//! - SSI_DMA_TX - disable DMA for transmit -//! -//! \return None. -// -//***************************************************************************** -void -SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Clear the requested bits in the SSI DMA control register. - // - HWREG(ui32Base + SSI_O_DMACTL) &= ~ui32DMAFlags; -} - -//***************************************************************************** -// -//! Determines whether the SSI transmitter is busy or not. -//! -//! \param ui32Base is the base address of the SSI module. -//! -//! This function allows the caller to determine whether all transmitted bytes -//! have cleared the transmitter hardware. If \b false is returned, then the -//! transmit FIFO is empty and all bits of the last transmitted word have left -//! the hardware shift register. -//! -//! \return Returns \b true if the SSI is transmitting or \b false if all -//! transmissions are complete. -// -//***************************************************************************** -bool -SSIBusy(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Determine if the SSI is busy. - // - return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false); -} - -//***************************************************************************** -// -//! Sets the data clock source for the specified SSI peripheral. -//! -//! \param ui32Base is the base address of the SSI module. -//! \param ui32Source is the baud clock source for the SSI. -//! -//! This function allows the baud clock source for the SSI to be selected. -//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or -//! the precision internal oscillator (\b SSI_CLOCK_PIOSC). -//! -//! Changing the baud clock source changes the data rate generated by the -//! SSI. Therefore, the data rate should be reconfigured after any change to -//! the SSI clock source. -//! -//! \note The ability to specify the SSI baud clock source varies with the -//! Tiva part and SSI in use. Please consult the data sheet for the part -//! in use to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Source == SSI_CLOCK_SYSTEM) || - (ui32Source == SSI_CLOCK_PIOSC)); - - // - // Set the SSI clock source. - // - HWREG(ui32Base + SSI_O_CC) = ui32Source; -} - -//***************************************************************************** -// -//! Gets the data clock source for the specified SSI peripheral. -//! -//! \param ui32Base is the base address of the SSI module. -//! -//! This function returns the data clock source for the specified SSI. -//! -//! \note The ability to specify the SSI data clock source varies with the -//! Tiva part and SSI in use. Please consult the data sheet for the part -//! in use to determine whether this support is available. -//! -//! \return Returns the current clock source, which is either -//! \b SSI_CLOCK_SYSTEM or \b SSI_CLOCK_PIOSC. -// -//***************************************************************************** -uint32_t -SSIClockSourceGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Return the SSI clock source. - // - return(HWREG(ui32Base + SSI_O_CC)); -} - -//***************************************************************************** -// -//! Selects the advanced mode of operation for the SSI module. -//! -//! \param ui32Base is the base address of the SSI module. -//! \param ui32Mode is the mode of operation to use. -//! -//! This function selects the mode of operation for the SSI module, which is -//! needed when using the advanced operation modes (Bi- or Quad-SPI). One of -//! the following modes can be selected: -//! -//! - \b SSI_ADV_MODE_LEGACY - Disables the advanced modes of operation, -//! resulting in legacy, or backwards-compatible, operation. When this mode -//! is selected, it is not valid to switch to Bi- or Quad-SPI operation. -//! This mode is the default. -//! - \b SSI_ADV_MODE_WRITE - The advanced mode of operation where data is only -//! written to the slave; any data clocked in via the \b SSIRx pin is thrown -//! away (instead of being placed into the SSI Rx FIFO). -//! - \b SSI_ADV_MODE_READ_WRITE - The advanced mode of operation where data is -//! written to and read from the slave; this mode is the same as -//! \b SSI_ADV_MODE_LEGACY but allows transitions to Bi- or Quad-SPI -//! operation. -//! - \b SSI_ADV_MODE_BI_READ - The advanced mode of operation where data is -//! read from the slave in Bi-SPI mode, with two bits of data read on every -//! SSI clock. -//! - \b SSI_ADV_MODE_BI_WRITE - The advanced mode of operation where data is -//! written to the slave in Bi-SPI mode, with two bits of data written on -//! every SSI clock. -//! - \b SSI_ADV_MODE_QUAD_READ - The advanced mode of operation where data is -//! read from the slave in Quad-SPI mode, with four bits of data read on -//! every SSI clock. -//! - \b SSI_ADV_MODE_QUAD_WRITE - The advanced mode of operation where data is -//! written to the slave in Quad-SPI mode, with four bits of data written on -//! every SSI clock. -//! -//! The following mode transitions are valid (other transitions produce -//! undefined results): -//! -//! \verbatim -//! +----------+-------------------------------------------------------------+ -//! |FROM | TO | -//! | |Legacy|Write|Read Write|Bi Read|Bi Write|Quad Read|Quad Write| -//! +----------+------+-----+----------+-------+--------+---------+----------+ -//! |Legacy | yes | yes | yes | | | | | -//! |Write | yes | yes | yes | yes | yes | yes | yes | -//! |Read/Write| yes | yes | yes | yes | yes | yes | yes | -//! |Bi Read | | yes | yes | yes | yes | | | -//! |Bi write | | yes | yes | yes | yes | | | -//! |Quad read | | yes | yes | | | yes | yes | -//! |Quad write| | yes | yes | | | yes | yes | -//! +----------+------+-----+----------+-------+--------+---------+----------+ -//! \endverbatim -//! -//! When using an advanced mode of operation, the SSI module must have been -//! configured for eight data bits and the \b SSI_FRF_MOTO_MODE_0 protocol. -//! The advanced mode operation that is selected applies only to data newly -//! written into the FIFO; the data that is already present in the FIFO is -//! handled using the advanced mode of operation in effect when that data was -//! written. -//! -//! Switching into and out of legacy mode should only occur when the FIFO is -//! empty. -//! -//! \note The availability of the advanced mode of SSI operation varies with -//! the Tiva part and SSI in use. Please consult the data sheet for the -//! part in use to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Mode == SSI_ADV_MODE_LEGACY) || - (ui32Mode == SSI_ADV_MODE_WRITE) || - (ui32Mode == SSI_ADV_MODE_READ_WRITE) || - (ui32Mode == SSI_ADV_MODE_BI_READ) || - (ui32Mode == SSI_ADV_MODE_BI_WRITE) || - (ui32Mode == SSI_ADV_MODE_QUAD_READ) || - (ui32Mode == SSI_ADV_MODE_QUAD_WRITE)); - - // - // Set the SSI mode of operation. - // - HWREG(ui32Base + SSI_O_CR1) = - ((HWREG(ui32Base + SSI_O_CR1) & ~(SSI_CR1_DIR | SSI_CR1_MODE_M)) | - ui32Mode); -} - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO as the end of a frame. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module, marking it as the end of a frame. If there is no -//! space available in the transmit FIFO, this function waits until there is -//! space available before returning. After this byte is transmitted by the -//! SSI module, the FSS signal de-asserts for at least one SSI clock. -//! -//! \note The upper 24 bits of \e ui32Data are discarded by the hardware. -//! -//! \note The availability of the advanced mode of SSI operation varies with -//! the Tiva part and SSI in use. Please consult the data sheet for the -//! part in use to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Data & 0xff) == 0); - - // - // Wait until there is space. - // - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) - { - } - - // - // Write the data to the SSI. - // - HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_EOM; - HWREG(ui32Base + SSI_O_DR) = ui32Data; -} - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO as the end of a frame. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module, marking it as the end of a frame. After this byte is -//! transmitted by the SSI module, the FSS signal de-asserts for at least one -//! SSI clock. If there is no space in the FIFO, then this function returns a -//! zero. -//! -//! \note The upper 24 bits of \e ui32Data are discarded by the hardware. -//! -//! \note The availability of the advanced mode of SSI operation varies with -//! the Tiva part and SSI in use. Please consult the data sheet for the -//! part in use to determine whether this support is available. -//! -//! \return Returns the number of elements written to the SSI transmit FIFO. -// -//***************************************************************************** -int32_t -SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Data & 0xff) == 0); - - // - // Check for space to write. - // - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) - { - HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_EOM; - HWREG(ui32Base + SSI_O_DR) = ui32Data; - return(1); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -//! Configures the SSI advanced mode to hold the SSIFss signal during the full -//! transfer. -//! -//! \param ui32Base is the base address of the SSI module. -//! -//! This function configures the SSI module to de-assert the SSIFss signal -//! during the entire data transfer when using one of the advanced modes -//! (instead of briefly de-asserting it after every byte). When using this -//! mode, SSIFss can be directly controlled via SSIAdvDataPutFrameEnd() and -//! SSIAdvDataPutFrameEndNonBlocking(). -//! -//! \note The availability of the advanced mode of SSI operation varies with -//! the Tiva part and SSI in use. Please consult the data sheet for the -//! part in use to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SSIAdvFrameHoldEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Set the hold frame bit. - // - HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_FSSHLDFRM; -} - -//***************************************************************************** -// -//! Configures the SSI advanced mode to de-assert the SSIFss signal after every -//! byte transfer. -//! -//! \param ui32Base is the base address of the SSI module. -//! -//! This function configures the SSI module to de-assert the SSIFss signal -//! for one SSI clock cycle after every byte is transferred using one of the -//! advanced modes (instead of leaving it asserted for the entire transfer). -//! This mode is the default operation. -//! -//! \note The availability of the advanced mode of SSI operation varies with -//! the Tiva part and SSI in use. Please consult the data sheet for the -//! part in use to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SSIAdvFrameHoldDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Clear the hold frame bit. - // - HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_FSSHLDFRM); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/ssi.h b/bsp/tm4c129x-dk/libraries/driverlib/ssi.h deleted file mode 100644 index 37d928dd1b905c587dba824847abf2f3304aa0cb..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/ssi.h +++ /dev/null @@ -1,157 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_SSI_H__ -#define __DRIVERLIB_SSI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ui32IntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXEOT 0x00000040 // Transmit FIFO is empty -#define SSI_DMATX 0x00000020 // DMA Transmit complete -#define SSI_DMARX 0x00000010 // DMA Receive complete -#define SSI_TXFF 0x00000008 // TX FIFO half full or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or more -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfigSetExpClk. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). -// -//***************************************************************************** -#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit -#define SSI_DMA_RX 0x00000001 // Enable DMA for receive - -//***************************************************************************** -// -// Values that can be passed to SSIClockSourceSet() or returned from -// SSIClockSourceGet(). -// -//***************************************************************************** -#define SSI_CLOCK_SYSTEM 0x00000000 -#define SSI_CLOCK_PIOSC 0x00000005 - -//***************************************************************************** -// -// Values that can be passed to SSIAdvModeSet(). -// -//***************************************************************************** -#define SSI_ADV_MODE_LEGACY 0x00000000 -#define SSI_ADV_MODE_READ_WRITE 0x000001c0 -#define SSI_ADV_MODE_WRITE 0x000000c0 -#define SSI_ADV_MODE_BI_READ 0x00000140 -#define SSI_ADV_MODE_BI_WRITE 0x00000040 -#define SSI_ADV_MODE_QUAD_READ 0x00000180 -#define SSI_ADV_MODE_QUAD_WRITE 0x00000080 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, - uint32_t ui32Protocol, uint32_t ui32Mode, - uint32_t ui32BitRate, - uint32_t ui32DataWidth); -extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data); -extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, - uint32_t *pui32Data); -extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data); -extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data); -extern void SSIDisable(uint32_t ui32Base); -extern void SSIEnable(uint32_t ui32Base); -extern void SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern uint32_t SSIIntStatus(uint32_t ui32Base, bool bMasked); -extern void SSIIntUnregister(uint32_t ui32Base); -extern void SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); -extern void SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); -extern bool SSIBusy(uint32_t ui32Base); -extern void SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); -extern uint32_t SSIClockSourceGet(uint32_t ui32Base); -extern void SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode); -extern void SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data); -extern int32_t SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base, - uint32_t ui32Data); -extern void SSIAdvFrameHoldEnable(uint32_t ui32Base); -extern void SSIAdvFrameHoldDisable(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_SSI_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sw_crc.c b/bsp/tm4c129x-dk/libraries/driverlib/sw_crc.c deleted file mode 100644 index 0706c34d50da692516666a86324d856bff8571f1..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/sw_crc.c +++ /dev/null @@ -1,770 +0,0 @@ -//***************************************************************************** -// -// sw_crc.c - Software CRC functions. -// -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup sw_crc_api -//! @{ -// -//***************************************************************************** - -#include -#include "driverlib/sw_crc.h" - -//***************************************************************************** -// -// The CRC table for the polynomial C(x) = x^8 + x^2 + x + 1 (CRC-8-CCITT). -// -//***************************************************************************** -static const uint8_t g_pui8Crc8CCITT[256] = -{ - 0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15, - 0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D, - 0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65, - 0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D, - 0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5, - 0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD, - 0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85, - 0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD, - 0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2, - 0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA, - 0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2, - 0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A, - 0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32, - 0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A, - 0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42, - 0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A, - 0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C, - 0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4, - 0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC, - 0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4, - 0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C, - 0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44, - 0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C, - 0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34, - 0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B, - 0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63, - 0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B, - 0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13, - 0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB, - 0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83, - 0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB, - 0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3 -}; - -//***************************************************************************** -// -// The CRC-16 table for the polynomial C(x) = x^16 + x^15 + x^2 + 1 (standard -// CRC-16, also known as CRC-16-IBM and CRC-16-ANSI). -// -//***************************************************************************** -static const uint16_t g_pui16Crc16[256] = -{ - 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, - 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, - 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, - 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, - 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, - 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, - 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, - 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, - 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, - 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, - 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, - 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, - 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, - 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, - 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, - 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, - 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, - 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, - 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, - 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, - 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, - 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, - 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, - 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, - 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, - 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, - 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, - 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, - 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, - 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, - 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, - 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 -}; - -//***************************************************************************** -// -// The CRC-32 table for the polynomial C(x) = x^32 + x^26 + x^23 + x^22 + -// x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1 (standard -// CRC32 as used in Ethernet, MPEG-2, PNG, etc.). -// -//***************************************************************************** -static const uint32_t g_pui32Crc32[] = -{ - 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, - 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, - 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, - 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, - 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, - 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, - 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, - 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, - 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, - 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, - 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, - 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, - 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, - 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, - 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, - 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, - 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, - 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, - 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, - 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, - 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, - 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, - 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, - 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, - 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, - 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, - 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, - 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, - 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, - 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, - 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, - 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, - 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, - 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, - 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, - 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, - 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, - 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, - 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, - 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, - 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, - 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, - 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, - 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, - 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, - 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, - 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, - 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, - 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, - 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, - 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, - 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, - 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, - 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, - 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, - 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, - 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, - 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, - 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, - 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, - 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, - 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, - 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, - 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d, -}; - -//***************************************************************************** -// -// This macro executes one iteration of the CRC-8-CCITT. -// -//***************************************************************************** -#define CRC8_ITER(crc, data) g_pui8Crc8CCITT[(uint8_t)((crc) ^ (data))] - -//***************************************************************************** -// -// This macro executes one iteration of the CRC-16. -// -//***************************************************************************** -#define CRC16_ITER(crc, data) (((crc) >> 8) ^ \ - g_pui16Crc16[(uint8_t)((crc) ^ (data))]) - -//***************************************************************************** -// -// This macro executes one iteration of the CRC-32. -// -//***************************************************************************** -#define CRC32_ITER(crc, data) (((crc) >> 8) ^ \ - g_pui32Crc32[(uint8_t)((crc & 0xFF) ^ \ - (data))]) - -//***************************************************************************** -// -//! Calculates the CRC-8-CCITT of an array of bytes. -//! -//! \param ui8Crc is the starting CRC-8-CCITT value. -//! \param pui8Data is a pointer to the data buffer. -//! \param ui32Count is the number of bytes in the data buffer. -//! -//! This function is used to calculate the CRC-8-CCITT of the input buffer. -//! The CRC-8-CCITT is computed in a running fashion, meaning that the entire -//! data block that is to have its CRC-8-CCITT computed does not need to be -//! supplied all at once. If the input buffer contains the entire block of -//! data, then \b ui8Crc should be set to 0. If, however, the entire block of -//! data is not available, then \b ui8Crc should be set to 0 for the first -//! portion of the data, and then the returned value should be passed back in -//! as \b ui8Crc for the next portion of the data. -//! -//! For example, to compute the CRC-8-CCITT of a block that has been split into -//! three pieces, use the following: -//! -//! \verbatim -//! ui8Crc = Crc8CCITT(0, pui8Data1, ui32Len1); -//! ui8Crc = Crc8CCITT(ui8Crc, pui8Data2, ui32Len2); -//! ui8Crc = Crc8CCITT(ui8Crc, pui8Data3, ui32Len3); -//! \endverbatim -//! -//! Computing a CRC-8-CCITT in a running fashion is useful in cases where the -//! data is arriving via a serial link (for example) and is therefore not all -//! available at one time. -//! -//! \return The CRC-8-CCITT of the input data. -// -//***************************************************************************** -uint8_t -Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data, uint32_t ui32Count) -{ - uint32_t ui32Temp; - - // - // If the data buffer is not 16 bit-aligned, then perform a single step of - // the CRC to make it 16 bit-aligned. - // - if((uint32_t)pui8Data & 1) - { - // - // Perform the CRC on this input byte. - // - ui8Crc = CRC8_ITER(ui8Crc, *pui8Data); - - // - // Skip this input byte. - // - pui8Data++; - ui32Count--; - } - - // - // If the data buffer is not word-aligned and there are at least two bytes - // of data left, then perform two steps of the CRC to make it word-aligned. - // - if(((uint32_t)pui8Data & 2) && (ui32Count > 1)) - { - // - // Read the next 16 bits. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp); - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // While there is at least a word remaining in the data buffer, perform - // four steps of the CRC to consume a word. - // - while(ui32Count > 3) - { - // - // Read the next word. - // - ui32Temp = *(uint32_t *)pui8Data; - - // - // Perform the CRC on these four bytes. - // - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp); - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8); - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 16); - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 24); - - // - // Skip these input bytes. - // - pui8Data += 4; - ui32Count -= 4; - } - - // - // If there are 16 bits left in the input buffer, then perform two steps of - // the CRC. - // - if(ui32Count > 1) - { - // - // Read the 16 bits. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp); - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // If there is a final byte remaining in the input buffer, then perform a - // single step of the CRC. - // - if(ui32Count != 0) - { - ui8Crc = CRC8_ITER(ui8Crc, *pui8Data); - } - - // - // Return the resulting CRC-8-CCITT value. - // - return(ui8Crc); -} - -//***************************************************************************** -// -//! Calculates the CRC-16 of an array of bytes. -//! -//! \param ui16Crc is the starting CRC-16 value. -//! \param pui8Data is a pointer to the data buffer. -//! \param ui32Count is the number of bytes in the data buffer. -//! -//! This function is used to calculate the CRC-16 of the input buffer. The -//! CRC-16 is computed in a running fashion, meaning that the entire data block -//! that is to have its CRC-16 computed does not need to be supplied all at -//! once. If the input buffer contains the entire block of data, then -//! \b ui16Crc should be set to 0. If, however, the entire block of data is -//! not available, then \b ui16Crc should be set to 0 for the first portion of -//! the data, and then the returned value should be passed back in as -//! \b ui16Crc for the next portion of the data. -//! -//! For example, to compute the CRC-16 of a block that has been split into -//! three pieces, use the following: -//! -//! \verbatim -//! ui16Crc = Crc16(0, pui8Data1, ui32Len1); -//! ui16Crc = Crc16(ui16Crc, pui8Data2, ui32Len2); -//! ui16Crc = Crc16(ui16Crc, pui8Data3, ui32Len3); -//! \endverbatim -//! -//! Computing a CRC-16 in a running fashion is useful in cases where the data -//! is arriving via a serial link (for example) and is therefore not all -//! available at one time. -//! -//! \return The CRC-16 of the input data. -// -//***************************************************************************** -uint16_t -Crc16(uint16_t ui16Crc, const uint8_t *pui8Data, uint32_t ui32Count) -{ - uint32_t ui32Temp; - - // - // If the data buffer is not 16 bit-aligned, then perform a single step of - // the CRC to make it 16 bit-aligned. - // - if((uint32_t)pui8Data & 1) - { - // - // Perform the CRC on this input byte. - // - ui16Crc = CRC16_ITER(ui16Crc, *pui8Data); - - // - // Skip this input byte. - // - pui8Data++; - ui32Count--; - } - - // - // If the data buffer is not word-aligned and there are at least two bytes - // of data left, then perform two steps of the CRC to make it word-aligned. - // - if(((uint32_t)pui8Data & 2) && (ui32Count > 1)) - { - // - // Read the next 16 bits. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // While there is at least a word remaining in the data buffer, perform - // four steps of the CRC to consume a word. - // - while(ui32Count > 3) - { - // - // Read the next word. - // - ui32Temp = *(uint32_t *)pui8Data; - - // - // Perform the CRC on these four bytes. - // - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24); - - // - // Skip these input bytes. - // - pui8Data += 4; - ui32Count -= 4; - } - - // - // If there are two bytes left in the input buffer, then perform two steps - // of the CRC. - // - if(ui32Count > 1) - { - // - // Read the two bytes. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // If there is a final byte remaining in the input buffer, then perform a - // single step of the CRC. - // - if(ui32Count != 0) - { - ui16Crc = CRC16_ITER(ui16Crc, *pui8Data); - } - - // - // Return the resulting CRC-16 value. - // - return(ui16Crc); -} - -//***************************************************************************** -// -//! Calculates the CRC-16 of an array of words. -//! -//! \param ui32WordLen is the length of the array in words (the number of bytes -//! divided by 4). -//! \param pui32Data is a pointer to the data buffer. -//! -//! This function is a wrapper around the running CRC-16 function, providing -//! the CRC-16 for a single block of data. -//! -//! \return The CRC-16 of the input data. -// -//***************************************************************************** -uint16_t -Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data) -{ - // - // Calculate and return the CRC-16 of this array of words. - // - return(Crc16(0, (const uint8_t *)pui32Data, ui32WordLen * 4)); -} - -//***************************************************************************** -// -//! Calculates three CRC-16s of an array of words. -//! -//! \param ui32WordLen is the length of the array in words (the number of bytes -//! divided by 4). -//! \param pui32Data is a pointer to the data buffer. -//! \param pui16Crc3 is a pointer to an array in which to place the three -//! CRC-16 values. -//! -//! This function is used to calculate three CRC-16s of the input buffer; the -//! first uses every byte from the array, the second uses only the even-index -//! bytes from the array (in other words, bytes 0, 2, 4, etc.), and the third -//! uses only the odd-index bytes from the array (in other words, bytes 1, 3, -//! 5, etc.). -//! -//! \return None -// -//***************************************************************************** -void -Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data, - uint16_t *pui16Crc3) -{ - uint16_t ui16Crc, ui16Cri8Odd, ui16Cri8Even; - uint32_t ui32Temp; - - // - // Initialize the CRC values to zero. - // - ui16Crc = 0; - ui16Cri8Odd = 0; - ui16Cri8Even = 0; - - // - // Loop while there are more words in the data buffer. - // - while(ui32WordLen--) - { - // - // Read the next word. - // - ui32Temp = *pui32Data++; - - // - // Perform the first CRC on all four data bytes. - // - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24); - - // - // Perform the second CRC on only the even-index data bytes. - // - ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp); - ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp >> 16); - - // - // Perform the third CRC on only the odd-index data bytes. - // - ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 8); - ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 24); - } - - // - // Return the resulting CRC-16 values. - // - pui16Crc3[0] = ui16Crc; - pui16Crc3[1] = ui16Cri8Even; - pui16Crc3[2] = ui16Cri8Odd; -} - -//***************************************************************************** -// -//! Calculates the CRC-32 of an array of bytes. -//! -//! \param ui32Crc is the starting CRC-32 value. -//! \param pui8Data is a pointer to the data buffer. -//! \param ui32Count is the number of bytes in the data buffer. -//! -//! This function is used to calculate the CRC-32 of the input buffer. The -//! CRC-32 is computed in a running fashion, meaning that the entire data block -//! that is to have its CRC-32 computed does not need to be supplied all at -//! once. If the input buffer contains the entire block of data, then -//! \b ui32Crc should be set to 0xFFFFFFFF. If, however, the entire block of -//! data is not available, then \b ui32Crc should be set to 0xFFFFFFFF for the -//! first portion of the data, and then the returned value should be passed -//! back in as \b ui32Crc for the next portion of the data. Once all data has -//! been passed to the function, the final CRC-32 can be obtained by inverting -//! the last returned value. -//! -//! For example, to compute the CRC-32 of a block that has been split into -//! three pieces, use the following: -//! -//! \verbatim -//! ui32Crc = Crc32(0xFFFFFFFF, pui8Data1, ui32Len1); -//! ui32Crc = Crc32(ui32Crc, pui8Data2, ui32Len2); -//! ui32Crc = Crc32(ui32Crc, pui8Data3, ui32Len3); -//! ui32Crc ^= 0xFFFFFFFF; -//! \endverbatim -//! -//! Computing a CRC-32 in a running fashion is useful in cases where the data -//! is arriving via a serial link (for example) and is therefore not all -//! available at one time. -//! -//! \return The accumulated CRC-32 of the input data. -// -//***************************************************************************** -uint32_t -Crc32(uint32_t ui32Crc, const uint8_t *pui8Data, uint32_t ui32Count) -{ - uint32_t ui32Temp; - - // - // If the data buffer is not 16 bit-aligned, then perform a single step - // of the CRC to make it 16 bit-aligned. - // - if((uint32_t)pui8Data & 1) - { - // - // Perform the CRC on this input byte. - // - ui32Crc = CRC32_ITER(ui32Crc, *pui8Data); - - // - // Skip this input byte. - // - pui8Data++; - ui32Count--; - } - - // - // If the data buffer is not word-aligned and there are at least two bytes - // of data left, then perform two steps of the CRC to make it word-aligned. - // - if(((uint32_t)pui8Data & 2) && (ui32Count > 1)) - { - // - // Read the next int16_t. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp); - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // While there is at least a word remaining in the data buffer, perform - // four steps of the CRC to consume a word. - // - while(ui32Count > 3) - { - // - // Read the next word. - // - ui32Temp = *(uint32_t *)pui8Data; - - // - // Perform the CRC on these four bytes. - // - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp); - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8); - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 16); - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 24); - - // - // Skip these input bytes. - // - pui8Data += 4; - ui32Count -= 4; - } - - // - // If there are 16 bits left in the input buffer, then perform two steps of - // the CRC. - // - if(ui32Count > 1) - { - // - // Read the two bytes. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp); - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // If there is a final byte remaining in the input buffer, then perform a - // single step of the CRC. - // - if(ui32Count != 0) - { - ui32Crc = CRC32_ITER(ui32Crc, *pui8Data); - } - - // - // Return the resulting CRC-32 value. - // - return(ui32Crc); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sw_crc.h b/bsp/tm4c129x-dk/libraries/driverlib/sw_crc.h deleted file mode 100644 index 0e60775ffc293d1a16f78c01d76c19a152fe735d..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/sw_crc.h +++ /dev/null @@ -1,78 +0,0 @@ -//***************************************************************************** -// -// sw_crc.h - Prototypes for the software CRC functions. -// -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_SW_CRC_H__ -#define __DRIVERLIB_SW_CRC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the functions. -// -//***************************************************************************** -extern uint8_t Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data, - uint32_t ui32Count); -extern uint16_t Crc16(uint16_t ui16Crc, const uint8_t *pui8Data, - uint32_t ui32Count); -extern uint16_t Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data); -extern void Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data, - uint16_t *pui16Crc3); -extern uint32_t Crc32(uint32_t ui32Crc, const uint8_t *pui8Data, - uint32_t ui32Count); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_SW_CRC_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sysctl.c b/bsp/tm4c129x-dk/libraries/driverlib/sysctl.c deleted file mode 100644 index 161b5fa6d713f1144dd88de0b57aca50ae43d1d2..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/sysctl.c +++ /dev/null @@ -1,3797 +0,0 @@ -//***************************************************************************** -// -// sysctl.c - Driver for the system controller. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup sysctl_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_nvic.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "inc/hw_flash.h" -#include "driverlib/cpu.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" - -//***************************************************************************** -// -// The flash shift used in the math to calculate the flash sector size. -// -//***************************************************************************** -#ifndef FLASH_PP_MAINSS_S -#define FLASH_PP_MAINSS_S 16 -#endif - -//***************************************************************************** -// -// This macro converts the XTAL value provided in the ui32Config parameter to -// an index to the g_pui32Xtals array. -// -//***************************************************************************** -#define SysCtlXtalCfgToIndex(a) ((a & 0x7c0) >> 6) - -//***************************************************************************** -// -// An array that maps the crystal number in RCC to a frequency. -// -//***************************************************************************** -static const uint32_t g_pui32Xtals[] = -{ - 1000000, - 1843200, - 2000000, - 2457600, - 3579545, - 3686400, - 4000000, - 4096000, - 4915200, - 5000000, - 5120000, - 6000000, - 6144000, - 7372800, - 8000000, - 8192000, - 10000000, - 12000000, - 12288000, - 13560000, - 14318180, - 16000000, - 16384000, - 18000000, - 20000000, - 24000000, - 25000000 -}; - -//***************************************************************************** -// -// Maximum number of VCO entries in the g_pui32XTALtoVCO and -// g_pui32VCOFrequencies structures for a device. -// -//***************************************************************************** -#define MAX_VCO_ENTRIES 2 -#define MAX_XTAL_ENTRIES 18 - -//***************************************************************************** -// -// These macros are used in the g_pui32XTALtoVCO table to make it more -// readable. -// -//***************************************************************************** -#define PLL_M_TO_REG(mi, mf) \ - ((uint32_t)mi | (uint32_t)(mf << SYSCTL_PLLFREQ0_MFRAC_S)) -#define PLL_N_TO_REG(n) \ - ((uint32_t)(n - 1) << SYSCTL_PLLFREQ1_N_S) -#define PLL_Q_TO_REG(q) \ - ((uint32_t)(q - 1) << SYSCTL_PLLFREQ1_Q_S) - -//***************************************************************************** -// -// Look up of the values that go into the PLLFREQ0 and PLLFREQ1 registers. -// -//***************************************************************************** -static const uint32_t g_pppui32XTALtoVCO[MAX_VCO_ENTRIES][MAX_XTAL_ENTRIES][3] = -{ - { - // - // VCO 320 MHz - // - { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5 MHz - { PLL_M_TO_REG(62, 512), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5.12 MHz - { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 6 MHz - { PLL_M_TO_REG(52, 85), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6.144 MHz - { PLL_M_TO_REG(43, 412), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 7.3728 MHz - { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8 MHz - { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8.192 MHz - { PLL_M_TO_REG(32, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 10 MHz - { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 12 MHz - { PLL_M_TO_REG(26, 43), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12.288 MHz - { PLL_M_TO_REG(23, 613), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 13.56 MHz - { PLL_M_TO_REG(22, 358), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 14.318180 MHz - { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16 MHz - { PLL_M_TO_REG(19, 544), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16.384 MHz - { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(9), PLL_Q_TO_REG(2) }, // 18 MHz - { PLL_M_TO_REG(16, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 20 MHz - { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 24 MHz - { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(5), PLL_Q_TO_REG(2) }, // 25 MHz - }, - { - // - // VCO 480 MHz - // - { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5 MHz - { PLL_M_TO_REG(93, 768), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5.12 MHz - { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6 MHz - { PLL_M_TO_REG(78, 128), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6.144 MHz - { PLL_M_TO_REG(65, 107), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 7.3728 MHz - { PLL_M_TO_REG(60, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8 MHz - { PLL_M_TO_REG(58, 608), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8.192 MHz - { PLL_M_TO_REG(48, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 10 MHz - { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12 MHz - { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12.288 MHz - { PLL_M_TO_REG(35, 408), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 13.56 MHz - { PLL_M_TO_REG(33, 536), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 14.318180 MHz - { PLL_M_TO_REG(30, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16 MHz - { PLL_M_TO_REG(29, 304), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16.384 MHz - { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 18 MHz - { PLL_M_TO_REG(24, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 20 MHz - { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 24 MHz - { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(5), PLL_Q_TO_REG(2) }, // 25 MHz - }, -}; - -//***************************************************************************** -// -// The mapping of system clock frequency to flash memory timing parameters. -// -//***************************************************************************** -static const struct -{ - uint32_t ui32Frequency; - uint32_t ui32MemTiming; -} -g_sXTALtoMEMTIM[] = -{ - { 16000000, (SYSCTL_MEMTIM0_FBCHT_0_5 | SYSCTL_MEMTIM0_FBCE | - (0 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_0_5 | SYSCTL_MEMTIM0_EBCE | - (0 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, - { 40000000, (SYSCTL_MEMTIM0_FBCHT_1_5 | (1 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_1_5 | (1 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, - { 60000000, (SYSCTL_MEMTIM0_FBCHT_2 | (2 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_2 | (2 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, - { 80000000, (SYSCTL_MEMTIM0_FBCHT_2_5 | (3 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_2_5 | (3 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, - { 100000000, (SYSCTL_MEMTIM0_FBCHT_3 | (4 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_3 | (4 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, - { 120000000, (SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, -}; - -//***************************************************************************** -// -// Get the correct memory timings for a given system clock value. -// -//***************************************************************************** -static uint32_t -_SysCtlMemTimingGet(uint32_t ui32SysClock) -{ - uint_fast8_t ui8Idx; - - // - // Loop through the flash memory timings. - // - for(ui8Idx = 0; - ui8Idx < (sizeof(g_sXTALtoMEMTIM) / sizeof(g_sXTALtoMEMTIM[0])); - ui8Idx++) - { - // - // See if the system clock frequency is less than the maximum frequency - // for this flash memory timing. - // - if(ui32SysClock <= g_sXTALtoMEMTIM[ui8Idx].ui32Frequency) - { - // - // This flash memory timing is the best choice for the system clock - // frequency, so return it now. - // - return(g_sXTALtoMEMTIM[ui8Idx].ui32MemTiming); - } - } - - // - // An appropriate flash memory timing could not be found, so the device is - // being clocked too fast. Return the default flash memory timing. - // - return(0); -} - -//***************************************************************************** -// -// Calculate the system frequency from the register settings base on the -// oscillator input. -// -//***************************************************************************** -static uint32_t -_SysCtlFrequencyGet(uint32_t ui32Xtal) -{ - uint32_t ui32Result; - uint_fast16_t ui16F1, ui16F2; - uint_fast16_t ui16PInt, ui16PFract; - uint_fast8_t ui8Q, ui8N; - - // - // Extract all of the values from the hardware registers. - // - ui16PFract = ((HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MFRAC_M) >> - SYSCTL_PLLFREQ0_MFRAC_S); - ui16PInt = HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MINT_M; - ui8Q = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_Q_M) >> - SYSCTL_PLLFREQ1_Q_S) + 1); - ui8N = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_N_M) >> - SYSCTL_PLLFREQ1_N_S) + 1); - - // - // Divide the crystal value by N. - // - ui32Xtal /= (uint32_t)ui8N; - - // - // Calculate the multiplier for bits 9:5. - // - ui16F1 = ui16PFract / 32; - - // - // Calculate the multiplier for bits 4:0. - // - ui16F2 = ui16PFract - (ui16F1 * 32); - - // - // Get the integer portion. - // - ui32Result = ui32Xtal * (uint32_t)ui16PInt; - - // - // Add first fractional bits portion(9:0). - // - ui32Result += (ui32Xtal * (uint32_t)ui16F1) / 32; - - // - // Add the second fractional bits portion(4:0). - // - ui32Result += (ui32Xtal * (uint32_t)ui16F2) / 1024; - - // - // Divide the result by Q. - // - ui32Result = ui32Result / (uint32_t)ui8Q; - - // - // Return the resulting PLL frequency. - // - return(ui32Result); -} - -//***************************************************************************** -// -// Look up of the possible VCO frequencies. -// -//***************************************************************************** -static const uint32_t g_pui32VCOFrequencies[MAX_VCO_ENTRIES] = -{ - 160000000, // VCO 320 - 240000000, // VCO 480 -}; - -//***************************************************************************** -// -// The base addresses of the various peripheral control registers. -// -//***************************************************************************** -#define SYSCTL_PPBASE 0x400fe300 -#define SYSCTL_SRBASE 0x400fe500 -#define SYSCTL_RCGCBASE 0x400fe600 -#define SYSCTL_SCGCBASE 0x400fe700 -#define SYSCTL_DCGCBASE 0x400fe800 -#define SYSCTL_PCBASE 0x400fe900 -#define SYSCTL_PRBASE 0x400fea00 - -//***************************************************************************** -// -//! \internal -//! Checks a peripheral identifier. -//! -//! \param ui32Peripheral is the peripheral identifier. -//! -//! This function determines if a peripheral identifier is valid. -//! -//! \return Returns \b true if the peripheral identifier is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_SysCtlPeripheralValid(uint32_t ui32Peripheral) -{ - return((ui32Peripheral == SYSCTL_PERIPH_ADC0) || - (ui32Peripheral == SYSCTL_PERIPH_ADC1) || - (ui32Peripheral == SYSCTL_PERIPH_CAN0) || - (ui32Peripheral == SYSCTL_PERIPH_CAN1) || - (ui32Peripheral == SYSCTL_PERIPH_COMP0) || - (ui32Peripheral == SYSCTL_PERIPH_CCM0) || - (ui32Peripheral == SYSCTL_PERIPH_EEPROM0) || - (ui32Peripheral == SYSCTL_PERIPH_EPHY0) || - (ui32Peripheral == SYSCTL_PERIPH_EMAC0) || - (ui32Peripheral == SYSCTL_PERIPH_EPI0) || - (ui32Peripheral == SYSCTL_PERIPH_FAN0) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOA) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOB) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOC) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOD) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOE) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOF) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOG) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOH) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOJ) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOK) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOL) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOM) || - (ui32Peripheral == SYSCTL_PERIPH_GPION) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOP) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOQ) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOR) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOS) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOT) || - (ui32Peripheral == SYSCTL_PERIPH_HIBERNATE) || - (ui32Peripheral == SYSCTL_PERIPH_I2C0) || - (ui32Peripheral == SYSCTL_PERIPH_I2C1) || - (ui32Peripheral == SYSCTL_PERIPH_I2C2) || - (ui32Peripheral == SYSCTL_PERIPH_I2C3) || - (ui32Peripheral == SYSCTL_PERIPH_I2C4) || - (ui32Peripheral == SYSCTL_PERIPH_I2C5) || - (ui32Peripheral == SYSCTL_PERIPH_I2C6) || - (ui32Peripheral == SYSCTL_PERIPH_I2C7) || - (ui32Peripheral == SYSCTL_PERIPH_I2C8) || - (ui32Peripheral == SYSCTL_PERIPH_I2C9) || - (ui32Peripheral == SYSCTL_PERIPH_LCD0) || - (ui32Peripheral == SYSCTL_PERIPH_PWM0) || - (ui32Peripheral == SYSCTL_PERIPH_PWM1) || - (ui32Peripheral == SYSCTL_PERIPH_QEI0) || - (ui32Peripheral == SYSCTL_PERIPH_QEI1) || - (ui32Peripheral == SYSCTL_PERIPH_SSI0) || - (ui32Peripheral == SYSCTL_PERIPH_SSI1) || - (ui32Peripheral == SYSCTL_PERIPH_SSI2) || - (ui32Peripheral == SYSCTL_PERIPH_SSI3) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER0) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER1) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER2) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER3) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER4) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER5) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER6) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER7) || - (ui32Peripheral == SYSCTL_PERIPH_UART0) || - (ui32Peripheral == SYSCTL_PERIPH_UART1) || - (ui32Peripheral == SYSCTL_PERIPH_UART2) || - (ui32Peripheral == SYSCTL_PERIPH_UART3) || - (ui32Peripheral == SYSCTL_PERIPH_UART4) || - (ui32Peripheral == SYSCTL_PERIPH_UART5) || - (ui32Peripheral == SYSCTL_PERIPH_UART6) || - (ui32Peripheral == SYSCTL_PERIPH_UART7) || - (ui32Peripheral == SYSCTL_PERIPH_UDMA) || - (ui32Peripheral == SYSCTL_PERIPH_USB0) || - (ui32Peripheral == SYSCTL_PERIPH_WDOG0) || - (ui32Peripheral == SYSCTL_PERIPH_WDOG1) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER0) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER1) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER2) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER3) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER4) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER5)); -} -#endif - -//***************************************************************************** -// -//! Gets the size of the SRAM. -//! -//! This function determines the size of the SRAM on the Tiva device. -//! -//! \return The total number of bytes of SRAM. -// -//***************************************************************************** -uint32_t -SysCtlSRAMSizeGet(void) -{ - return((HWREG(FLASH_SSIZE) + 1) * 256); -} - -//***************************************************************************** -// -//! Gets the size of the flash. -//! -//! This function determines the size of the flash on the Tiva device. -//! -//! \return The total number of bytes of flash. -// -//***************************************************************************** -uint32_t -SysCtlFlashSizeGet(void) -{ - - // - // TM4C123 devices report the flash size in DC0. - // - if(CLASS_IS_TM4C123) - { - // - // Compute the size of the flash. - // - return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800); - } - else - { - // - // Get the flash size from the FLASH_PP register. - // - return(2048 * ((HWREG(FLASH_PP) & FLASH_PP_SIZE_M) + 1)); - } -} - -//***************************************************************************** -// -//! Gets the size of a single eraseable sector of flash. -//! -//! This function determines the flash sector size on the Tiva device. -//! This size determines the erase granularity of the device flash. -//! -//! \return The number of bytes in a single flash sector. -// -//***************************************************************************** -uint32_t -SysCtlFlashSectorSizeGet(void) -{ - // - // TM4C129 devices store the value in a different register. - // - if(CLASS_IS_TM4C129) - { - // - // Get the flash sector size from the FLASH_PP register. - // - return(1 << (10 + - ((HWREG(FLASH_PP) & - FLASH_PP_MAINSS_M) >> FLASH_PP_MAINSS_S))); - } - else - { - // - // The sector size is fixed at 1KB. - // - return(1024); - } -} - -//***************************************************************************** -// -//! Determines if a peripheral is present. -//! -//! \param ui32Peripheral is the peripheral in question. -//! -//! This function determines if a particular peripheral is present in the -//! device. Each member of the Tiva family has a different peripheral -//! set; this function determines which peripherals are present on this device. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return Returns \b true if the specified peripheral is present and \b false -//! if it is not. -// -//***************************************************************************** -bool -SysCtlPeripheralPresent(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // See if this peripheral is present. - // - return(HWREGBITW(SYSCTL_PPBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff)); -} - -//***************************************************************************** -// -//! Determines if a peripheral is ready. -//! -//! \param ui32Peripheral is the peripheral in question. -//! -//! This function determines if a particular peripheral is ready to be -//! accessed. The peripheral may be in a non-ready state if it is not enabled, -//! is being held in reset, or is in the process of becoming ready after being -//! enabled or taken out of reset. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \note The ability to check for a peripheral being ready varies based on the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine if this feature is available. -//! -//! \return Returns \b true if the specified peripheral is ready and \b false -//! if it is not. -// -//***************************************************************************** -bool -SysCtlPeripheralReady(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // See if this peripheral is ready. - // - return(HWREGBITW(SYSCTL_PRBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff)); -} - -//***************************************************************************** -// -//! Powers on a peripheral. -//! -//! \param ui32Peripheral is the peripheral to be powered on. -//! -//! This function turns on the power to a peripheral. The peripheral continues -//! to receive power even when its clock is not enabled. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_CAN0,\b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_EMAC, -//! \b SYSCTL_PERIPH_EPHY, \b SYSCTL_PERIPH_LCD0, \b SYSCTL_PERIPH_USB0 -//! -//! \note The ability to power off a peripheral varies based on the Tiva -//! part in use. Please consult the data sheet for the part you are using to -//! determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralPowerOn(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Power on this peripheral. - // - HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 1; -} - -//***************************************************************************** -// -//! Powers off a peripheral. -//! -//! \param ui32Peripheral is the peripheral to be powered off. -//! -//! This function allows the power to a peripheral to be turned off. The -//! peripheral continues to receive power when its clock is enabled, but -//! the power is removed when its clock is disabled. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_CAN0,\b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_EMAC, -//! \b SYSCTL_PERIPH_EPHY, \b SYSCTL_PERIPH_LCD0, \b SYSCTL_PERIPH_USB0 -//! -//! \note The ability to power off a peripheral varies based on the Tiva -//! part in use. Please consult the data sheet for the part you are using to -//! determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralPowerOff(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Power off this peripheral. - // - HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 0; -} - -//***************************************************************************** -// -//! Performs a software reset of a peripheral. -//! -//! \param ui32Peripheral is the peripheral to reset. -//! -//! This function performs a software reset of the specified peripheral. An -//! individual peripheral reset signal is asserted for a brief period and then -//! de-asserted, returning the internal state of the peripheral to its reset -//! condition. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralReset(uint32_t ui32Peripheral) -{ - volatile uint_fast8_t ui8Delay; - - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Put the peripheral into the reset state. - // - HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 1; - - // - // Delay for a little bit. - // - for(ui8Delay = 0; ui8Delay < 16; ui8Delay++) - { - } - - // - // Take the peripheral out of the reset state. - // - HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 0; -} - -//***************************************************************************** -// -//! Enables a peripheral. -//! -//! \param ui32Peripheral is the peripheral to enable. -//! -//! This function enables a peripheral. At power-up, all peripherals are -//! disabled; they must be enabled in order to operate or respond to register -//! reads/writes. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \note It takes five clock cycles after the write to enable a peripheral -//! before the the peripheral is actually enabled. During this time, attempts -//! to access the peripheral result in a bus fault. Care should be taken -//! to ensure that the peripheral is not accessed during this brief time -//! period. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralEnable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Enable this peripheral. - // - HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 1; -} - -//***************************************************************************** -// -//! Disables a peripheral. -//! -//! \param ui32Peripheral is the peripheral to disable. -//! -//! This function disables a peripheral. Once disabled, they do not operate or -//! respond to register reads/writes. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralDisable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Disable this peripheral. - // - HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 0; -} - -//***************************************************************************** -// -//! Enables a peripheral in sleep mode. -//! -//! \param ui32Peripheral is the peripheral to enable in sleep mode. -//! -//! This function allows a peripheral to continue operating when the processor -//! goes into sleep mode. Because the clocking configuration of the device -//! does not change, any peripheral can safely continue operating while the -//! processor is in sleep mode and can therefore wake the processor from sleep -//! mode. -//! -//! Sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode -//! configuration is maintained but has no effect when sleep mode is entered. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Enable this peripheral in sleep mode. - // - HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 1; -} - -//***************************************************************************** -// -//! Disables a peripheral in sleep mode. -//! -//! \param ui32Peripheral is the peripheral to disable in sleep mode. -//! -//! This function causes a peripheral to stop operating when the processor goes -//! into sleep mode. Disabling peripherals while in sleep mode helps to lower -//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), -//! the peripheral automatically resumes operation when the processor -//! leaves sleep mode, maintaining its entire state from before sleep mode was -//! entered. -//! -//! Sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode -//! configuration is maintained but has no effect when sleep mode is entered. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Disable this peripheral in sleep mode. - // - HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 0; -} - -//***************************************************************************** -// -//! Enables a peripheral in deep-sleep mode. -//! -//! \param ui32Peripheral is the peripheral to enable in deep-sleep mode. -//! -//! This function allows a peripheral to continue operating when the processor -//! goes into deep-sleep mode. Because the clocking configuration of the -//! device may change, not all peripherals can safely continue operating while -//! the processor is in deep-sleep mode. Those that must run at a particular -//! frequency (such as a UART) do not work as expected if the clock changes. -//! It is the responsibility of the caller to make sensible choices. -//! -//! Deep-sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode -//! configuration is maintained but has no effect when deep-sleep mode is -//! entered. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Enable this peripheral in deep-sleep mode. - // - HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 1; -} - -//***************************************************************************** -// -//! Disables a peripheral in deep-sleep mode. -//! -//! \param ui32Peripheral is the peripheral to disable in deep-sleep mode. -//! -//! This function causes a peripheral to stop operating when the processor goes -//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps -//! to lower the current draw of the device, and can keep peripherals that -//! require a particular clock frequency from operating when the clock changes -//! as a result of entering deep-sleep mode. If enabled (via -//! SysCtlPeripheralEnable()), the peripheral automatically resumes -//! operation when the processor leaves deep-sleep mode, maintaining its entire -//! state from before deep-sleep mode was entered. -//! -//! Deep-sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode -//! configuration is maintained but has no effect when deep-sleep mode is -//! entered. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Disable this peripheral in deep-sleep mode. - // - HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 0; -} - -//***************************************************************************** -// -//! Controls peripheral clock gating in sleep and deep-sleep mode. -//! -//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep -//! peripheral configuration should be used and \b false if not. -//! -//! This function controls how peripherals are clocked when the processor goes -//! into sleep or deep-sleep mode. By default, the peripherals are clocked the -//! same as in run mode; if peripheral clock gating is enabled, they are -//! clocked according to the configuration set by -//! SysCtlPeripheralSleepEnable(), SysCtlPeripheralSleepDisable(), -//! SysCtlPeripheralDeepSleepEnable(), and SysCtlPeripheralDeepSleepDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralClockGating(bool bEnable) -{ - if(CLASS_IS_TM4C123) - { - // - // Enable peripheral clock gating as requested. - // - if(bEnable) - { - HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG; - } - else - { - HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG); - } - } - else - { - // - // Enable peripheral clock gating as requested. - // - if(bEnable) - { - HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_ACG; - } - else - { - HWREG(SYSCTL_RSCLKCFG) &= ~SYSCTL_RSCLKCFG_ACG; - } - } -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the system control interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the system -//! control interrupt occurs. -//! -//! This function registers the handler to be called when a system control -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific system control interrupts must be enabled -//! via SysCtlIntEnable(). It is the interrupt handler's responsibility to -//! clear the interrupt source via SysCtlIntClear(). -//! -//! System control can generate interrupts when the PLL achieves lock, if the -//! internal LDO current limit is exceeded, if the internal oscillator fails, -//! if the main oscillator fails, if the internal LDO output voltage droops too -//! much, if the external voltage droops too much, or if the PLL fails. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note The events that cause system control interrupts vary based on the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_SYSCTL_TM4C123, pfnHandler); - - // - // Enable the system control interrupt. - // - IntEnable(INT_SYSCTL_TM4C123); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the system control interrupt. -//! -//! This function unregisters the handler to be called when a system control -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(INT_SYSCTL_TM4C123); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_SYSCTL_TM4C123); -} - -//***************************************************************************** -// -//! Enables individual system control interrupt sources. -//! -//! \param ui32Ints is a bit mask of the interrupt sources to be enabled. Must -//! be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, -//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, -//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or -//! \b SYSCTL_INT_BOR1. -//! -//! This function enables the indicated system control interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \note The interrupt sources vary based on the Tiva part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlIntEnable(uint32_t ui32Ints) -{ - // - // Enable the specified interrupts. - // - HWREG(SYSCTL_IMC) |= ui32Ints; -} - -//***************************************************************************** -// -//! Disables individual system control interrupt sources. -//! -//! \param ui32Ints is a bit mask of the interrupt sources to be disabled. -//! Must be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, -//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, -//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or -//! \b SYSCTL_INT_BOR1. -//! -//! This function disables the indicated system control interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! \note The interrupt sources vary based on the Tiva part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlIntDisable(uint32_t ui32Ints) -{ - // - // Disable the specified interrupts. - // - HWREG(SYSCTL_IMC) &= ~(ui32Ints); -} - -//***************************************************************************** -// -//! Clears system control interrupt sources. -//! -//! \param ui32Ints is a bit mask of the interrupt sources to be cleared. Must -//! be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, -//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, -//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or -//! \b SYSCTL_INT_BOR1. -//! -//! The specified system control interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep it from being called again immediately on exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \note The interrupt sources vary based on the Tiva part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlIntClear(uint32_t ui32Ints) -{ - // - // Clear the requested interrupt sources. - // - HWREG(SYSCTL_MISC) = ui32Ints; -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the system controller. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \note The interrupt sources vary based on the Tiva part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, -//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, -//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or -//! \b SYSCTL_INT_BOR1. -// -//***************************************************************************** -uint32_t -SysCtlIntStatus(bool bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(SYSCTL_MISC)); - } - else - { - return(HWREG(SYSCTL_RIS)); - } -} - -//***************************************************************************** -// -//! Sets the output voltage of the LDO when the device enters sleep mode. -//! -//! \param ui32Voltage is the required output voltage from the LDO while in -//! sleep mode. -//! -//! This function sets the output voltage of the LDO while in sleep mode. -//! The \e ui32Voltage parameter must be one of the following values: -//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, -//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or -//! \b SYSCTL_LDO_1_20V. -//! -//! \note The availability of this feature, the default LDO voltage, and the -//! adjustment range varies with the Tiva part in use. Please consult the -//! data sheet for the part you are using to determine whether this support is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlLDOSleepSet(uint32_t ui32Voltage) -{ - // - // Check the arguments. - // - ASSERT((ui32Voltage == SYSCTL_LDO_0_90V) || - (ui32Voltage == SYSCTL_LDO_0_95V) || - (ui32Voltage == SYSCTL_LDO_1_00V) || - (ui32Voltage == SYSCTL_LDO_1_05V) || - (ui32Voltage == SYSCTL_LDO_1_10V) || - (ui32Voltage == SYSCTL_LDO_1_15V) || - (ui32Voltage == SYSCTL_LDO_1_20V)); - - // - // Set the sleep-mode LDO voltage to the requested value. - // - HWREG(SYSCTL_LDOSPCTL) = ui32Voltage; -} - -//***************************************************************************** -// -//! Returns the output voltage of the LDO when the device enters sleep mode. -//! -//! This function determines the output voltage of the LDO while in sleep mode, -//! as specified by the control register. -//! -//! \note The availability of this feature, the default LDO voltage, and the -//! adjustment range varies with the Tiva part in use. Please consult the -//! data sheet for the part you are using to determine whether this support is -//! available. -//! -//! \return Returns the sleep-mode voltage of the LDO and is one of -//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, -//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or -//! \b SYSCTL_LDO_1_20V. -// -//***************************************************************************** -uint32_t -SysCtlLDOSleepGet(void) -{ - // - // Return the sleep-mode LDO voltage setting. - // - return(HWREG(SYSCTL_LDOSPCTL)); -} - -//***************************************************************************** -// -//! Sets the output voltage of the LDO when the device enters deep-sleep -//! mode. -//! -//! \param ui32Voltage is the required output voltage from the LDO while in -//! deep-sleep mode. -//! -//! This function sets the output voltage of the LDO while in deep-sleep mode. -//! The \e ui32Voltage parameter specifies the output voltage of the LDO and -//! must be one of the following values: \b SYSCTL_LDO_0_90V, -//! \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, \b SYSCTL_LDO_1_05V, -//! \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or \b SYSCTL_LDO_1_20V. -//! -//! \note The availability of this feature, the default LDO voltage, and the -//! adjustment range varies with the Tiva part in use. Please consult the -//! data sheet for the part you are using to determine whether this support is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlLDODeepSleepSet(uint32_t ui32Voltage) -{ - // - // Check the arguments. - // - ASSERT((ui32Voltage == SYSCTL_LDO_0_90V) || - (ui32Voltage == SYSCTL_LDO_0_95V) || - (ui32Voltage == SYSCTL_LDO_1_00V) || - (ui32Voltage == SYSCTL_LDO_1_05V) || - (ui32Voltage == SYSCTL_LDO_1_10V) || - (ui32Voltage == SYSCTL_LDO_1_15V) || - (ui32Voltage == SYSCTL_LDO_1_20V)); - - // - // Set the deep-sleep LDO voltage to the requested value. - // - HWREG(SYSCTL_LDODPCTL) = ui32Voltage; -} - -//***************************************************************************** -// -//! Returns the output voltage of the LDO when the device enters deep-sleep -//! mode. -//! -//! This function returns the output voltage of the LDO when the device is -//! in deep-sleep mode, as specified by the control register. -//! -//! \note The availability of this feature, the default LDO voltage, and the -//! adjustment range varies with the Tiva part in use. Please consult the -//! data sheet for the part you are using to determine whether this support is -//! available. -//! -//! \return Returns the deep-sleep-mode voltage of the LDO; is one of -//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, -//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or -//! \b SYSCTL_LDO_1_20V. -// -//***************************************************************************** -uint32_t -SysCtlLDODeepSleepGet(void) -{ - // - // Return the deep-sleep-mode LDO voltage setting. - // - return(HWREG(SYSCTL_LDODPCTL)); -} - -//***************************************************************************** -// -//! Configures the power to the flash and SRAM while in sleep mode. -//! -//! \param ui32Config is the required flash and SRAM power configuration. -//! -//! This function allows the power configuration of the flash and SRAM while in -//! sleep mode to be set. The \e ui32Config parameter is the logical OR of the -//! flash power configuration and the SRAM power configuration. -//! -//! The flash power configuration is specified as either: -//! -//! - \b SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode, -//! providing fast wake-up time but higher power consumption. -//! - \b SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing -//! reduced power consumption but longer wake-up time. -//! -//! The SRAM power configuration is specified as one of: -//! -//! - \b SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing -//! fast wake-up time but higher power consumption. -//! - \b SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode, -//! providing reduced power consumption but longer wake-up time. -//! - \b SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode, -//! providing further reduced power consumption but longer wake-up time. -//! -//! \note The availability of this feature varies with the Tiva part in -//! use. Please consult the data sheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlSleepPowerSet(uint32_t ui32Config) -{ - // - // Set the sleep-mode flash and SRAM power configuration. - // - HWREG(SYSCTL_SLPPWRCFG) = ui32Config; -} - -//***************************************************************************** -// -//! Configures the power to the flash and SRAM while in deep-sleep mode. -//! -//! \param ui32Config is the required flash and SRAM power configuration. -//! -//! This function allows the power configuration of the flash and SRAM while in -//! deep-sleep mode to be set. The \e ui32Config parameter is the logical OR -//! of the flash power configuration and the SRAM power configuration. -//! -//! The flash power configuration is specified as either: -//! -//! - \b SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode, -//! providing fast wake-up time but higher power consumption. -//! - \b SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing -//! reduced power consumption but longer wake-up time. -//! -//! The SRAM power configuration is specified as one of: -//! -//! - \b SYSCTL_LDO_SLEEP - The LDO is in sleep mode. -//! - \b SYSCTL_TEMP_LOW_POWER - The temperature sensor in low power mode. -//! - \b SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing -//! fast wake-up time but higher power consumption. -//! - \b SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode, -//! providing reduced power consumption but longer wake-up time. -//! - \b SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode, -//! providing further reduced power consumption but longer wake-up time. -//! -//! \note The availability of this feature varies with the Tiva part in -//! use. Please consult the data sheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlDeepSleepPowerSet(uint32_t ui32Config) -{ - // - // Set the deep-sleep-mode flash and SRAM power configuration. - // - HWREG(SYSCTL_DSLPPWRCFG) = ui32Config; -} - -//***************************************************************************** -// -//! Resets the device. -//! -//! This function performs a software reset of the entire device. The -//! processor and all peripherals are reset and all device registers are -//! returned to their default values (with the exception of the reset cause -//! register, which maintains its current value but has the software reset -//! bit set as well). -//! -//! \return This function does not return. -// -//***************************************************************************** -void -SysCtlReset(void) -{ - // - // Perform a software reset request. This request causes the device to - // reset, no further code is executed. - // - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; - - // - // The device should have reset, so this should never be reached. Just in - // case, loop forever. - // - while(1) - { - } -} - -//***************************************************************************** -// -//! Puts the processor into sleep mode. -//! -//! This function places the processor into sleep mode; it does not return -//! until the processor returns to run mode. The peripherals that are enabled -//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the -//! processor (if automatic clock gating is enabled with -//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to -//! operate). -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlSleep(void) -{ - // - // Wait for an interrupt. - // - CPUwfi(); -} - -//***************************************************************************** -// -//! Puts the processor into deep-sleep mode. -//! -//! This function places the processor into deep-sleep mode; it does not return -//! until the processor returns to run mode. The peripherals that are enabled -//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up -//! the processor (if automatic clock gating is enabled with -//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to -//! operate). -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlDeepSleep(void) -{ - // - // Enable deep-sleep. - // - HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; - - // - // Wait for an interrupt. - // - CPUwfi(); - - // - // Disable deep-sleep so that a future sleep works correctly. - // - HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); -} - -//***************************************************************************** -// -//! Gets the reason for a reset. -//! -//! This function returns the reason(s) for a reset. Because the reset -//! reasons are sticky until either cleared by software or a power-on reset, -//! multiple reset reasons may be returned if multiple resets have occurred. -//! The reset reason is a logical OR of \b SYSCTL_CAUSE_HSRVREQ, -//! \b SYSCTL_CAUSE_HIB, \b SYSCTL_CAUSE_WDOG1, \b SYSCTL_CAUSE_SW, -//! \b SYSCTL_CAUSE_WDOG0, \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, -//! and/or \b SYSCTL_CAUSE_EXT. -//! -//! \return Returns the reason(s) for a reset. -// -//***************************************************************************** -uint32_t -SysCtlResetCauseGet(void) -{ - // - // Return the reset reasons. - // - return(HWREG(SYSCTL_RESC)); -} - -//***************************************************************************** -// -//! Clears reset reasons. -//! -//! \param ui32Causes are the reset causes to be cleared; must be a logical OR -//! of \b SYSCTL_CAUSE_HSRVREQ, \b SYSCTL_CAUSE_HIB, \b SYSCTL_CAUSE_WDOG1, -//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG0, \b SYSCTL_CAUSE_BOR, -//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. -//! -//! This function clears the specified sticky reset reasons. Once cleared, -//! another reset for the same reason can be detected, and a reset for a -//! different reason can be distinguished (instead of having two reset causes -//! set). If the reset reason is used by an application, all reset causes -//! should be cleared after they are retrieved with SysCtlResetCauseGet(). -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlResetCauseClear(uint32_t ui32Causes) -{ - // - // Clear the given reset reasons. - // - HWREG(SYSCTL_RESC) &= ~(ui32Causes); -} - -//***************************************************************************** -// -//! Provides a small delay. -//! -//! \param ui32Count is the number of delay loop iterations to perform. -//! -//! This function provides a means of generating a delay by executing a simple -//! 3 instruction cycle loop a given number of times. It is written in -//! assembly to keep the loop instruction count consistent across tool chains. -//! -//! It is important to note that this function does NOT provide an accurate -//! timing mechanism. Although the delay loop is 3 instruction cycles long, -//! the execution time of the loop will vary dramatically depending upon the -//! application's interrupt environment (the loop will be interrupted unless -//! run with interrupts disabled and this is generally an unwise thing to do) -//! and also the current system clock rate and flash timings (wait states and -//! the operation of the prefetch buffer affect the timing). -//! -//! For better accuracy, the ROM version of this function may be used. This -//! version will not suffer from flash- and prefect buffer-related timing -//! variability but will still be delayed by interrupt service routines. -//! -//! For best accuracy, a system timer should be used with code either polling -//! for a particular timer value being exceeded or processing the timer -//! interrupt to determine when a particular time period has elapsed. -//! -//! \return None. -// -//***************************************************************************** -#if defined(ewarm) || defined(DOXYGEN) -void -SysCtlDelay(uint32_t ui32Count) -{ - __asm(" subs r0, #1\n" - " bne.n SysCtlDelay\n" - " bx lr"); -} -#endif -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -void __attribute__((naked)) -SysCtlDelay(uint32_t ui32Count) -{ - __asm(" subs r0, #1\n" - " bne SysCtlDelay\n" - " bx lr"); -} -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm void -SysCtlDelay(uint32_t ui32Count) -{ - subs r0, #1; - bne SysCtlDelay; - bx lr; -} -#endif -// -// For CCS implement this function in pure assembly. This prevents the TI -// compiler from doing funny things with the optimizer. -// -#if defined(ccs) -__asm(" .sect \".text:SysCtlDelay\"\n" - " .clink\n" - " .thumbfunc SysCtlDelay\n" - " .thumb\n" - " .global SysCtlDelay\n" - "SysCtlDelay:\n" - " subs r0, #1\n" - " bne.n SysCtlDelay\n" - " bx lr\n"); -#endif - -//***************************************************************************** -// -//! Sets the configuration of the main oscillator (MOSC) control. -//! -//! \param ui32Config is the required configuration of the MOSC control. -//! -//! This function configures the control of the main oscillator. The -//! \e ui32Config is specified as the logical OR of the following values: -//! -//! - \b SYSCTL_MOSC_VALIDATE enables the MOSC verification circuit that -//! detects a failure of the main oscillator (such as a loss of the clock). -//! - \b SYSCTL_MOSC_INTERRUPT indicates that a MOSC failure should generate an -//! interrupt instead of resetting the processor. -//! - \b SYSCTL_MOSC_NO_XTAL indicates that there is no crystal or oscillator -//! connected to the OSC0/OSC1 pins, allowing power consumption to be -//! reduced. -//! - \b SYSCTL_MOSC_PWR_DIS disable power to the main oscillator. If this -//! parameter is not specified, the MOSC input remains powered. -//! - \b SYSCTL_MOSC_LOWFREQ MOSC is less than 10 MHz. -//! - \b SYSCTL_MOSC_HIGHFREQ MOSC is greater than 10 MHz. -//! - \b SYSCTL_MOSC_SESRC specifies that the MOSC is a single-ended -//! oscillator connected to OSC0. If this parameter is not specified, the -//! input is assumed to be a crystal. -//! -//! \note The availability of MOSC control varies based on the Tiva part -//! in use. Please consult the data sheet for the part you are using to -//! determine whether this support is available. In addition, the capability -//! of MOSC control varies based on the Tiva part in use. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlMOSCConfigSet(uint32_t ui32Config) -{ - // - // Configure the MOSC control. - // - HWREG(SYSCTL_MOSCCTL) = ui32Config; -} - -//***************************************************************************** -// -//! Calibrates the precision internal oscillator. -//! -//! \param ui32Type is the type of calibration to perform. -//! -//! This function performs a calibration of the PIOSC. There are three types -//! of calibration available; the desired calibration type as specified in -//! \e ui32Type is one of: -//! -//! - \b SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the -//! 32-kHz clock from the hibernate module as a reference. This type is -//! only possible on parts that have a hibernate module, and then only if -//! it is enabled, a 32.768-kHz clock source is attached to the XOSC0/1 -//! pins and the hibernate module's RTC is also enabled. -//! -//! - \b SYSCTL_PIOSC_CAL_FACT to reset the PIOSC calibration to the factory -//! provided calibration. -//! -//! - \b SYSCTL_PIOSC_CAL_USER to set the PIOSC calibration to a user-supplied -//! value. The value to be used is ORed into the lower 7-bits of this value, -//! with 0x40 being the ``nominal'' value (in other words, if everything were -//! perfect, 0x40 provides exactly 16 MHz). Values larger than 0x40 -//! slow down PIOSC, and values smaller than 0x40 speed up PIOSC. -//! -//! \return Returns 1 if the calibration was successful and 0 if it failed. -// -//***************************************************************************** -uint32_t -SysCtlPIOSCCalibrate(uint32_t ui32Type) -{ - // - // Perform the requested calibration. If performing user calibration, the - // UTEN bit must be set with one write, then the UT field in a second - // write, and the UPDATE bit in a final write. For other calibration - // types, a single write to set UPDATE or CAL is all that is required. - // - if(ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UPDATE)) - { - HWREG(SYSCTL_PIOSCCAL) = ui32Type & SYSCTL_PIOSCCAL_UTEN; - HWREG(SYSCTL_PIOSCCAL) = - ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UT_M); - } - HWREG(SYSCTL_PIOSCCAL) = ui32Type; - - // - // See if an automatic calibration was requested. - // - if(ui32Type & SYSCTL_PIOSCCAL_CAL) - { - // - // Wait for the automatic calibration to complete. - // - while((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) == 0) - { - } - - // - // If the automatic calibration failed, return an error. - // - if((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) != - SYSCTL_PIOSCSTAT_CRPASS) - { - return(0); - } - } - - // - // The calibration was successful. - // - return(1); -} - -//***************************************************************************** -// -//! Sets the type of reset issued due to certain reset events. -//! -//! \param ui32Behavior specifies the types of resets for each of the -//! configurable reset events. -//! -//! This function sets the types of reset issued when a configurable reset -//! event occurs. The reset events that are configurable are: Watchdog 0 or 1, -//! a brown out and the external RSTn pin. The valid actions are either a -//! system reset or a full POR sequence. See the data sheet for more -//! information on the differences between a full POR and a system reset. All -//! reset behaviors can be configured with a single call using the logical OR -//! of the values defined below. Any reset option that is not specifically set -//! remains configured for its default behavior. Either POR or system reset -//! can be selected for each reset cause. -//! -//! Valid values are logical combinations of the following: -//! -//! - \b SYSCTL_ONRST_WDOG0_POR configures a Watchdog 0 reset to perform a full -//! POR. -//! - \b SYSCTL_ONRST_WDOG0_SYS configures a Watchdog 0 reset to perform a -//! system reset. -//! - \b SYSCTL_ONRST_WDOG1_POR configures a Watchdog 1 reset to perform a full -//! POR. -//! - \b SYSCTL_ONRST_WDOG1_SYS configures a Watchdog 1 reset to perform a -//! system reset. -//! - \b SYSCTL_ONRST_BOR_POR configures a brown-out reset to perform a full -//! POR. -//! - \b SYSCTL_ONRST_BOR_SYS configures a brown-out reset to perform a system -//! reset. -//! - \b SYSCTL_ONRST_EXT_POR configures an external pin reset to perform a -//! full POR. -//! - \b SYSCTL_ONRST_EXT_SYS configures an external pin reset to perform a -//! system reset. -//! -//! \b Example: Set Watchdog 0 reset to trigger a POR and a brown-out reset -//! to trigger a system reset while leaving the remaining resets with their -//! default behaviors. -//! -//! \verbatim -//! SysCtlResetBehaviorSet(SYSCTL_ONRST_WDOG0_POR | SYSCTL_ONRST_BOR_SYS); -//! \endverbatim -//! -//! \note This function cannot be used with TM4C123 devices. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlResetBehaviorSet(uint32_t ui32Behavior) -{ - HWREG(SYSCTL_RESBEHAVCTL) = ui32Behavior; -} - -//***************************************************************************** -// -//! Returns the current types of reset issued due to reset events. -//! -//! This function returns the types of resets issued when a configurable reset -//! occurs. The value returned is a logical OR combination of the valid values -//! that are described in the documentation for the \e ui32Behavior parameter -//! of the SysCtlResetBehaviorSet() function. -//! -//! \note This function should only be used with Flurry-class devices. -//! -//! \return The reset behaviors for all configurable resets. -// -//***************************************************************************** -uint32_t -SysCtlResetBehaviorGet(void) -{ - return(HWREG(SYSCTL_RESBEHAVCTL)); -} - -//***************************************************************************** -// -//! Configures the system clock. -//! -//! \param ui32Config is the required configuration of the device clocking. -//! \param ui32SysClock is the requested processor frequency. -//! -//! This function configures the main system clocking for the device. The -//! input frequency, oscillator source, whether or not to enable the PLL, and -//! the system clock divider are all configured with this function. This -//! function configures the system frequency to the closest available divisor -//! of one of the fixed PLL VCO settings provided in the \e ui32Config -//! parameter. The caller sets the \e ui32SysClock parameter to request the -//! system clock frequency, and this function then attempts to match this using -//! the values provided in the \e ui32Config parameter. If this function -//! cannot exactly match the requested frequency, it picks the closest -//! frequency that is lower than the requested frequency. The \e ui32Config -//! parameter provides the remaining configuration options using a set of -//! defines that are a logical OR of several different values, many of which -//! are grouped into sets where only one of the set can be chosen. This -//! function returns the current system frequency which may not match the -//! requested frequency. -//! -//! If the application is using an external crystal then the frequency is -//! set by using one of the following values: -//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_8MHZ, -//! \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, \b SYSCTL_XTAL_16MHZ, -//! \b SYSCTL_XTAL_18MHZ, \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or -//! \b SYSCTL_XTAL_25MHz. -//! -//! The oscillator source is chosen with one of the following values: -//! -//! - \b SYSCTL_OSC_MAIN to use an external crystal or oscillator. -//! - \b SYSCTL_OSC_INT to use the 16-MHz precision internal oscillator. -//! - \b SYSCTL_OSC_INT30 to use the internal low frequency oscillator. -//! - \b SYSCTL_OSC_EXT32 to use the hibernate modules 32.786-kHz oscillator. -//! This option is only available on devices that include the hibernation -//! module. -//! -//! The system clock source is chosen with one of the following values: -//! -//! - \b SYSCTL_USE_PLL is used to select the PLL output as the system clock. -//! - \b SYSCTL_USE_OSC is used to choose one of the oscillators as the -//! system clock. -//! -//! The PLL VCO frequency is chosen with one of the the following values: -//! -//! - \b SYSCTL_CFG_VCO_480 to set the PLL VCO output to 480-MHz -//! - \b SYSCTL_CFG_VCO_320 to set the PLL VCO output to 320-MHz -//! -//! Example: Configure the system clocking to be 40 MHz with a 320-MHz PLL -//! setting using the 16-MHz internal oscillator. -//! -//! \verbatim -//! SysCtlClockFreqSet(SYSCTL_OSC_INT | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_320, -//! 40000000); -//! \endverbatim -//! -//! \note This function cannot be used with TM4C123 devices. For TM4C123 -//! devices use the SysCtlClockSet() function. -//! -//! \return The actual configured system clock frequency in Hz or zero if the -//! value could not be changed due to a parameter error or PLL lock failure. -// -//***************************************************************************** -uint32_t -SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) -{ - int32_t i32Timeout, i32VCOIdx, i32XtalIdx; - uint32_t ui32MOSCCTL; - uint32_t ui32Delay; - uint32_t ui32SysDiv, ui32Osc, ui32OscSelect, ui32RSClkConfig; - - // - // TM4C123 devices should not use this function. - // - if(CLASS_IS_TM4C123) - { - return(0); - } - - // - // Get the index of the crystal from the ui32Config parameter. - // - i32XtalIdx = SysCtlXtalCfgToIndex(ui32Config); - - // - // Determine which non-PLL source was selected. - // - if((ui32Config & 0x38) == SYSCTL_OSC_INT) - { - // - // Use the nominal frequency for the PIOSC oscillator and set the - // crystal select. - // - ui32Osc = 16000000; - ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC; - ui32OscSelect |= SYSCTL_RSCLKCFG_PLLSRC_PIOSC; - - // - // Force the crystal index to the value for 16-MHz. - // - i32XtalIdx = SysCtlXtalCfgToIndex(SYSCTL_XTAL_16MHZ); - } - else if((ui32Config & 0x38) == SYSCTL_OSC_INT30) - { - // - // Use the nominal frequency for the low frequency oscillator. - // - ui32Osc = 30000; - ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_LFIOSC; - } - else if((ui32Config & 0x38) == (SYSCTL_OSC_EXT32 & 0x38)) - { - // - // Use the RTC frequency. - // - ui32Osc = 32768; - ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_RTC; - } - else if((ui32Config & 0x38) == SYSCTL_OSC_MAIN) - { - // - // Bounds check the source frequency for the main oscillator. The is - // because the PLL tables in the g_pppui32XTALtoVCO structure range - // from 5MHz to 25MHz. - // - if((i32XtalIdx > (SysCtlXtalCfgToIndex(SYSCTL_XTAL_25MHZ))) || - (i32XtalIdx < (SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ)))) - { - return(0); - } - - ui32Osc = g_pui32Xtals[i32XtalIdx]; - - // - // Set the PLL source select to MOSC. - // - ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_MOSC; - ui32OscSelect |= SYSCTL_RSCLKCFG_PLLSRC_MOSC; - - // - // Clear MOSC power down, high oscillator range setting, and no crystal - // present setting. - // - ui32MOSCCTL = HWREG(SYSCTL_MOSCCTL) & - ~(SYSCTL_MOSCCTL_OSCRNG | SYSCTL_MOSCCTL_PWRDN | - SYSCTL_MOSCCTL_NOXTAL); - - // - // Increase the drive strength for MOSC of 10 MHz and above. - // - if(i32XtalIdx >= (SysCtlXtalCfgToIndex(SYSCTL_XTAL_10MHZ) - - (SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ)))) - { - ui32MOSCCTL |= SYSCTL_MOSCCTL_OSCRNG; - } - - HWREG(SYSCTL_MOSCCTL) = ui32MOSCCTL; - - // - // Timeout using the legacy delay value. - // - ui32Delay = 524288; - - while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0) - { - ui32Delay--; - - if(ui32Delay == 0) - { - break; - } - } - - // - // If the main oscillator failed to start up then do not switch to - // it and return. - // - if(ui32Delay == 0) - { - return(0); - } - - - } - else - { - // - // This was an invalid request because no oscillator source was - // indicated. - // - ui32Osc = 0; - ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC; - } - - // - // Check if the running with the PLL enabled was requested. - // - if((ui32Config & SYSCTL_USE_OSC) == SYSCTL_USE_PLL) - { - // - // ui32Config must be SYSCTL_OSC_MAIN or SYSCTL_OSC_INT. - // - if(((ui32Config & 0x38) != SYSCTL_OSC_MAIN) && - ((ui32Config & 0x38) != SYSCTL_OSC_INT)) - { - return(0); - } - - // - // Get the VCO index out of the ui32Config parameter. - // - i32VCOIdx = (ui32Config >> 24) & 7; - - // - // Check that the VCO index is not out of bounds. - // - ASSERT(i32VCOIdx < MAX_VCO_ENTRIES); - - // - // Set the memory timings for the maximum external frequency since - // this could be a switch to PIOSC or possibly to MOSC which can be - // up to 25MHz. - // - HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(25000000); - - // - // Clear the old PLL divider and source in case it was set. - // - ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG) & - ~(SYSCTL_RSCLKCFG_PSYSDIV_M | - SYSCTL_RSCLKCFG_OSCSRC_M | - SYSCTL_RSCLKCFG_PLLSRC_M | SYSCTL_RSCLKCFG_USEPLL); - - // - // Update the memory timings to match running from PIOSC. - // - ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; - - // - // Update clock configuration to switch back to PIOSC. - // - HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; - - // - // The table starts at 5 MHz so modify the index to match this. - // - i32XtalIdx -= SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ); - - // - // Calculate the System divider such that we get a frequency that is - // the closest to the requested frequency without going over. - // - ui32SysDiv = (g_pui32VCOFrequencies[i32VCOIdx] + ui32SysClock - 1) / - ui32SysClock; - - // - // Set the oscillator source. - // - HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect; - - // - // Set the M, N and Q values provided from the table and preserve - // the power state of the main PLL. - // - HWREG(SYSCTL_PLLFREQ1) = - g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1]; - HWREG(SYSCTL_PLLFREQ1) |= PLL_Q_TO_REG(ui32SysDiv); - HWREG(SYSCTL_PLLFREQ0) = - (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] | - (HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR)); - - // - // Calculate the actual system clock as PSYSDIV is always div-by 2. - // - ui32SysClock = _SysCtlFrequencyGet(ui32Osc) / 2; - - // - // Set the Flash and EEPROM timing values. - // - HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock); - - // - // Check if the PLL is already powered up. - // - if(HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR) - { - // - // Trigger the PLL to lock to the new frequency. - // - HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_NEWFREQ; - } - else - { - // - // Power up the PLL. - // - HWREG(SYSCTL_PLLFREQ0) |= SYSCTL_PLLFREQ0_PLLPWR; - } - - // - // Wait until the PLL has locked. - // - for(i32Timeout = 32768; i32Timeout > 0; i32Timeout--) - { - if((HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK)) - { - break; - } - } - - // - // If the loop above did not timeout then switch over to the PLL - // - if(i32Timeout) - { - ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); - ui32RSClkConfig |= (1 << SYSCTL_RSCLKCFG_PSYSDIV_S) | - ui32OscSelect | SYSCTL_RSCLKCFG_USEPLL; - ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; - - // - // Set the new clock configuration. - // - HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; - } - else - { - ui32SysClock = 0; - } - } - else - { - // - // Set the Flash and EEPROM timing values for PIOSC. - // - HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(16000000); - - // - // Make sure that the PLL is powered down since it is not being used. - // - HWREG(SYSCTL_PLLFREQ0) &= ~SYSCTL_PLLFREQ0_PLLPWR; - - // - // Clear the old PLL divider and source in case it was set. - // - ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); - ui32RSClkConfig &= ~(SYSCTL_RSCLKCFG_OSYSDIV_M | - SYSCTL_RSCLKCFG_OSCSRC_M | - SYSCTL_RSCLKCFG_USEPLL); - - // - // Update the memory timings. - // - ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; - - // - // Set the new clock configuration. - // - HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; - - // - // If zero given as the system clock then default to divide by 1. - // - if(ui32SysClock == 0) - { - ui32SysDiv = 0; - } - else - { - // - // Calculate the System divider based on the requested - // frequency. - // - ui32SysDiv = ui32Osc / ui32SysClock; - - // - // If the system divisor is not already zero, subtract one to - // set the value in the register which requires the value to - // be n-1. - // - if(ui32SysDiv != 0) - { - ui32SysDiv -= 1; - } - - // - // Calculate the system clock. - // - ui32SysClock = ui32Osc / (ui32SysDiv + 1); - } - - // - // Set the memory timing values for the new system clock. - // - HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock); - - // - // Set the new system clock values. - // - ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); - ui32RSClkConfig |= (ui32SysDiv << SYSCTL_RSCLKCFG_OSYSDIV_S) | - ui32OscSelect; - - // - // Update the memory timings. - // - ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; - - // - // Set the new clock configuration. - // - HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; - } - - // - // Finally change the OSCSRC back to PIOSC - // - HWREG(SYSCTL_RSCLKCFG) &= ~(SYSCTL_RSCLKCFG_OSCSRC_M); - - return(ui32SysClock); -} - -//***************************************************************************** -// -//! Sets the clocking of the device. -//! -//! \param ui32Config is the required configuration of the device clocking. -//! -//! This function configures the clocking of the device. The input crystal -//! frequency, oscillator to be used, use of the PLL, and the system clock -//! divider are all configured with this function. -//! -//! The \e ui32Config parameter is the logical OR of several different values, -//! many of which are grouped into sets where only one can be chosen. -//! -//! The system clock divider is chosen with one of the following values: -//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ... -//! \b SYSCTL_SYSDIV_64. -//! -//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or -//! \b SYSCTL_USE_OSC. -//! -//! The external crystal frequency is chosen with one of the following values: -//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, -//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, -//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, -//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, -//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ, -//! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ, -//! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz. -//! Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in -//! operation. -//! -//! The oscillator source is chosen with one of the following values: -//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4, -//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only -//! available on devices with the hibernate module, and then only when the -//! hibernate module has been enabled. -//! -//! The internal and main oscillators are disabled with the -//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. -//! The external oscillator must be enabled in order to use an external clock -//! source. Note that attempts to disable the oscillator used to clock the -//! device is prevented by the hardware. -//! -//! To clock the system from an external source (such as an external crystal -//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the -//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | -//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use -//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate -//! crystal with one of the \b SYSCTL_XTAL_xxx values. -//! -//! \note This function should only be called on TM4C123 devices. For -//! all other devices use the SysCtlClockFreqSet() function. -//! -//! \note If selecting the PLL as the system clock source (that is, via -//! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to -//! determine when the PLL has locked. If an interrupt handler for the -//! system control interrupt is in place, and it responds to and clears the -//! PLL lock interrupt, this function delays until its timeout has occurred -//! instead of completing as soon as PLL lock is achieved. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlClockSet(uint32_t ui32Config) -{ - uint32_t ui32Delay, ui32RCC, ui32RCC2; - - // - // Get the current value of the RCC and RCC2 registers. - // - ui32RCC = HWREG(SYSCTL_RCC); - ui32RCC2 = HWREG(SYSCTL_RCC2); - - // - // Bypass the PLL and system clock dividers for now. - // - ui32RCC |= SYSCTL_RCC_BYPASS; - ui32RCC &= ~(SYSCTL_RCC_USESYSDIV); - ui32RCC2 |= SYSCTL_RCC2_BYPASS2; - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ui32RCC; - HWREG(SYSCTL_RCC2) = ui32RCC2; - - // - // See if the oscillator needs to be enabled. - // - if((ui32RCC & SYSCTL_RCC_MOSCDIS) && !(ui32Config & SYSCTL_MAIN_OSC_DIS)) - { - // - // Make sure that the required oscillators are enabled. For now, the - // previously enabled oscillators must be enabled along with the newly - // requested oscillators. - // - ui32RCC &= (~SYSCTL_RCC_MOSCDIS | (ui32Config & SYSCTL_MAIN_OSC_DIS)); - - // - // Clear the MOSC power up raw interrupt status to be sure it is not - // set when waiting below. - // - HWREG(SYSCTL_MISC) = SYSCTL_MISC_MOSCPUPMIS; - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ui32RCC; - - // - // Timeout using the legacy delay value. - // - ui32Delay = 524288; - - while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0) - { - ui32Delay--; - - if(ui32Delay == 0) - { - break; - } - } - - // - // If the main oscillator failed to start up then do not switch to - // it and return. - // - if(ui32Delay == 0) - { - return; - } - - } - - // - // Set the new crystal value and oscillator source. Because the OSCSRC2 - // field in RCC2 overlaps the XTAL field in RCC, the OSCSRC field has a - // special encoding within ui32Config to avoid the overlap. - // - ui32RCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M); - ui32RCC |= ui32Config & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M); - ui32RCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M); - ui32RCC2 |= ui32Config & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M); - ui32RCC2 |= (ui32Config & 0x00000008) << 3; - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ui32RCC; - HWREG(SYSCTL_RCC2) = ui32RCC2; - - // - // Set the PLL configuration. - // - ui32RCC &= ~SYSCTL_RCC_PWRDN; - ui32RCC |= ui32Config & SYSCTL_RCC_PWRDN; - ui32RCC2 &= ~SYSCTL_RCC2_PWRDN2; - ui32RCC2 |= ui32Config & SYSCTL_RCC2_PWRDN2; - - // - // Clear the PLL lock interrupt. - // - HWREG(SYSCTL_MISC) = SYSCTL_MISC_PLLLMIS; - - // - // Write the new RCC value. - // - if(ui32RCC2 & SYSCTL_RCC2_USERCC2) - { - HWREG(SYSCTL_RCC2) = ui32RCC2; - HWREG(SYSCTL_RCC) = ui32RCC; - } - else - { - HWREG(SYSCTL_RCC) = ui32RCC; - HWREG(SYSCTL_RCC2) = ui32RCC2; - } - - // - // Set the requested system divider and disable the appropriate - // oscillators. This value is not written immediately. - // - ui32RCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | - SYSCTL_RCC_MOSCDIS); - ui32RCC |= ui32Config & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | - SYSCTL_RCC_MOSCDIS); - ui32RCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M); - ui32RCC2 |= ui32Config & SYSCTL_RCC2_SYSDIV2_M; - if(ui32Config & SYSCTL_RCC2_DIV400) - { - ui32RCC |= SYSCTL_RCC_USESYSDIV; - ui32RCC2 &= ~(SYSCTL_RCC_USESYSDIV); - ui32RCC2 |= ui32Config & (SYSCTL_RCC2_DIV400 | SYSCTL_RCC2_SYSDIV2LSB); - } - else - { - ui32RCC2 &= ~(SYSCTL_RCC2_DIV400); - } - - // - // See if the PLL output is being used to clock the system. - // - if(!(ui32Config & SYSCTL_RCC_BYPASS)) - { - // - // Wait until the PLL has locked. - // - for(ui32Delay = 32768; ui32Delay > 0; ui32Delay--) - { - if((HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK)) - { - break; - } - } - - // - // Enable use of the PLL. - // - ui32RCC &= ~(SYSCTL_RCC_BYPASS); - ui32RCC2 &= ~(SYSCTL_RCC2_BYPASS2); - } - - // - // Write the final RCC value. - // - HWREG(SYSCTL_RCC) = ui32RCC; - HWREG(SYSCTL_RCC2) = ui32RCC2; - - // - // Delay for a little bit so that the system divider takes effect. - // - SysCtlDelay(16); -} - -//***************************************************************************** -// -//! Gets the processor clock rate. -//! -//! This function determines the clock rate of the processor clock, which is -//! also the clock rate of the peripheral modules (with the exception of -//! PWM, which has its own clock divider; other peripherals may have different -//! clocking, see the device data sheet for details). -//! -//! \note This cannot return accurate results if SysCtlClockSet() has not -//! been called to configure the clocking of the device, or if the device is -//! directly clocked from a crystal (or a clock source) that is not one of the -//! supported crystal frequencies. In the latter case, this function should be -//! modified to directly return the correct system clock rate. -//! -//! \note This function can only be called on TM4C123 devices. For TM4C129 -//! devices, the return value from SysCtlClockFreqSet() indicates the system -//! clock frequency. -//! -//! \return The processor clock rate for TM4C123 devices only. -// -//***************************************************************************** -uint32_t -SysCtlClockGet(void) -{ - uint32_t ui32RCC, ui32RCC2, ui32PLL, ui32Clk, ui32Max; - uint32_t ui32PLL1; - - // - // This function is only valid on TM4C123 devices. - // - ASSERT(CLASS_IS_TM4C123); - - // - // Read RCC and RCC2. - // - ui32RCC = HWREG(SYSCTL_RCC); - ui32RCC2 = HWREG(SYSCTL_RCC2); - - // - // Get the base clock rate. - // - switch((ui32RCC2 & SYSCTL_RCC2_USERCC2) ? - (ui32RCC2 & SYSCTL_RCC2_OSCSRC2_M) : - (ui32RCC & SYSCTL_RCC_OSCSRC_M)) - { - // - // The main oscillator is the clock source. Determine its rate from - // the crystal setting field. - // - case SYSCTL_RCC_OSCSRC_MAIN: - { - ui32Clk = g_pui32Xtals[(ui32RCC & SYSCTL_RCC_XTAL_M) >> - SYSCTL_RCC_XTAL_S]; - break; - } - - // - // The internal oscillator is the source clock. - // - case SYSCTL_RCC_OSCSRC_INT: - { - // - // The internal oscillator on all devices is 16 MHz. - // - ui32Clk = 16000000; - break; - } - - // - // The internal oscillator divided by four is the source clock. - // - case SYSCTL_RCC_OSCSRC_INT4: - { - // - // The internal oscillator on all devices is 16 MHz. - // - ui32Clk = 16000000 / 4; - break; - } - - // - // The internal 30-KHz oscillator is the source clock. - // - case SYSCTL_RCC_OSCSRC_30: - { - // - // The internal 30-KHz oscillator has an accuracy of +/- 30%. - // - ui32Clk = 30000; - break; - } - - // - // The 32.768-KHz clock from the hibernate module is the source clock. - // - case SYSCTL_RCC2_OSCSRC2_32: - { - ui32Clk = 32768; - break; - } - - // - // An unknown setting, so return a zero clock (that is, an unknown - // clock rate). - // - default: - { - return(0); - } - } - - // - // Default the maximum frequency to the maximum 32-bit unsigned value. - // - ui32Max = 0xffffffff; - - // - // See if the PLL is being used. - // - if(((ui32RCC2 & SYSCTL_RCC2_USERCC2) && - !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) || - (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) && !(ui32RCC & SYSCTL_RCC_BYPASS))) - { - // - // Read the two PLL frequency registers. The formula for a - // TM4C123 device is "(xtal * m) / ((q + 1) * (n + 1))". - // - ui32PLL = HWREG(SYSCTL_PLLFREQ0); - ui32PLL1 = HWREG(SYSCTL_PLLFREQ1); - - // - // Divide the input clock by the dividers. - // - ui32Clk /= ((((ui32PLL1 & SYSCTL_PLLFREQ1_Q_M) >> - SYSCTL_PLLFREQ1_Q_S) + 1) * - (((ui32PLL1 & SYSCTL_PLLFREQ1_N_M) >> - SYSCTL_PLLFREQ1_N_S) + 1) * 2); - - // - // Multiply the clock by the multiplier, which is split into an - // integer part and a fractional part. - // - ui32Clk = ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MINT_M) >> - SYSCTL_PLLFREQ0_MINT_S)) + - ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MFRAC_M) >> - SYSCTL_PLLFREQ0_MFRAC_S)) >> 10)); - - // - // Force the system divider to be enabled. It is always used when - // using the PLL, but in some cases it does not read as being enabled. - // - ui32RCC |= SYSCTL_RCC_USESYSDIV; - - // - // Calculate the maximum system frequency. - // - switch(HWREG(SYSCTL_DC1) & SYSCTL_DC1_MINSYSDIV_M) - { - case SYSCTL_DC1_MINSYSDIV_80: - { - ui32Max = 80000000; - break; - } - case SYSCTL_DC1_MINSYSDIV_50: - { - ui32Max = 50000000; - break; - } - case SYSCTL_DC1_MINSYSDIV_40: - { - ui32Max = 40000000; - break; - } - case SYSCTL_DC1_MINSYSDIV_25: - { - ui32Max = 25000000; - break; - } - case SYSCTL_DC1_MINSYSDIV_20: - { - ui32Max = 20000000; - break; - } - default: - { - break; - } - } - } - - // - // See if the system divider is being used. - // - if(ui32RCC & SYSCTL_RCC_USESYSDIV) - { - // - // Adjust the clock rate by the system clock divider. - // - if(ui32RCC2 & SYSCTL_RCC2_USERCC2) - { - if((ui32RCC2 & SYSCTL_RCC2_DIV400) && - (((ui32RCC2 & SYSCTL_RCC2_USERCC2) && - !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) || - (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) && - !(ui32RCC & SYSCTL_RCC_BYPASS)))) - - { - ui32Clk = ((ui32Clk * 2) / (((ui32RCC2 & - (SYSCTL_RCC2_SYSDIV2_M | - SYSCTL_RCC2_SYSDIV2LSB)) >> - (SYSCTL_RCC2_SYSDIV2_S - 1)) + - 1)); - } - else - { - ui32Clk /= (((ui32RCC2 & SYSCTL_RCC2_SYSDIV2_M) >> - SYSCTL_RCC2_SYSDIV2_S) + 1); - } - } - else - { - ui32Clk /= (((ui32RCC & SYSCTL_RCC_SYSDIV_M) >> - SYSCTL_RCC_SYSDIV_S) + 1); - } - } - - // - // Limit the maximum clock to the maximum clock frequency. - // - if(ui32Max < ui32Clk) - { - ui32Clk = ui32Max; - } - - // - // Return the computed clock rate. - // - return(ui32Clk); -} - -//***************************************************************************** -// -//! Sets the clocking of the device while in deep-sleep mode. -//! -//! \param ui32Config is the required configuration of the device clocking -//! while in deep-sleep mode. -//! -//! This function configures the clocking of the device while in deep-sleep -//! mode. The oscillator to be used and the system clock divider are -//! configured with this function. -//! -//! The \e ui32Config parameter is the logical OR of the following values: -//! -//! The system clock divider is chosen from one of the following values: -//! \b SYSCTL_DSLP_DIV_1, \b SYSCTL_DSLP_DIV_2, \b SYSCTL_DSLP_DIV_3, ... -//! \b SYSCTL_DSLP_DIV_64. -//! -//! The oscillator source is chosen from one of the following values: -//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30, -//! or \b SYSCTL_DSLP_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only available on -//! devices with the hibernation module, and then only when the hibernation -//! module has been enabled. -//! -//! The precision internal oscillator can be powered down in deep-sleep mode by -//! specifying \b SYSCTL_DSLP_PIOSC_PD. The precision internal oscillator is -//! not powered down if it is required for operation while in deep-sleep -//! (based on other configuration settings.) -//! -//! \note This function should only be called on TM4C123 devices. For -//! other devices use the SysCtlDeepSleepClockConfigSet() function. -//! -//! \note The availability of deep-sleep clocking configuration varies with the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlDeepSleepClockSet(uint32_t ui32Config) -{ - // - // Set the deep-sleep clock configuration. - // - HWREG(SYSCTL_DSLPCLKCFG) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the clock configuration of the device while in deep-sleep mode. -//! -//! \param ui32Div is the clock divider when in deep-sleep mode. -//! \param ui32Config is the configuration of the device clocking while -//! in deep-sleep mode. -//! -//! This function configures the clocking of the device while in deep-sleep -//! mode. The \e ui32Config parameter selects the oscillator and the -//! \e ui32Div parameter sets the clock divider used in deep-sleep mode. The -//! valid values for the \e ui32Div parameter range from 1 to 1024, however not -//! all Tiva microcontrollers support this full range. This function -//! replaces the SysCtlDeepSleepClockSet() function and can be used on -//! Tiva devices that support deep-sleep mode. -//! -//! The oscillator source is chosen from one of the following values: -//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30, -//! or \b SYSCTL_DSLP_OSC_EXT32. The \b SYSCTL_DSLP_OSC_EXT32 option is only -//! available on devices with the hibernation module, and then only when the -//! hibernation module is enabled. -//! -//! The precision internal oscillator can be powered down in deep-sleep mode by -//! specifying \b SYSCTL_DSLP_PIOSC_PD. The precision internal oscillator is -//! not powered down if it is required for operation while in deep-sleep -//! (based on other configuration settings). -//! -//! The main oscillator can be powered down in deep-sleep mode by -//! specifying \b SYSCTL_DSLP_MOSC_PD. The main oscillator is -//! not powered down if it is required for operation while in deep-sleep -//! (based on other configuration settings). -//! -//! \note The availability of deep-sleep clocking configuration and the -//! configuration values vary with the Tiva device in use. Please consult -//! the data sheet for the device you are using to determine whether the -//! desired configuration options are available and to determine the valid -//! range for the clock divider. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlDeepSleepClockConfigSet(uint32_t ui32Div, uint32_t ui32Config) -{ - uint32_t ui32Value; - - ASSERT(ui32Div != 0); - - if(CLASS_IS_TM4C123) - { - // - // Set the deep-sleep clock configuration. - // - HWREG(SYSCTL_DSLPCLKCFG) = (ui32Config & ~SYSCTL_DSLPCLKCFG_D_M) | - ((ui32Div - 1) << SYSCTL_DSLPCLKCFG_D_S); - } - else - { - // - // Initialize the value with the divider. - // - ui32Value = ui32Div - 1; - - // - // Set the clock source selection based on the defines used for - // SysCtlDeepSleepClockSet() function so that there is some backwards - // compatibility. - // - switch(ui32Config & SYSCTL_DSLPCLKCFG_O_M) - { - // - // Choose the main external oscillator. - // - case SYSCTL_DSLP_OSC_MAIN: - { - ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_MOSC; - - break; - } - - // - // Choose the low frequency oscillator. - // - case SYSCTL_DSLP_OSC_INT30: - { - ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC; - - break; - } - - // - // Choose the low frequency oscillator. - // - case SYSCTL_DSLP_OSC_EXT32: - { - ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_RTC; - - break; - } - // - // The zero value uses the PIOSC as the clock source. - // - case SYSCTL_DSLP_OSC_INT: - default: - { - break; - } - } - - // - // Set the PIOSC power down bit. - // - if(ui32Config & SYSCTL_DSLP_PIOSC_PD) - { - ui32Value |= SYSCTL_DSCLKCFG_PIOSCPD; - } - - // - // Set the PIOSC power down bit. - // - if(ui32Config & SYSCTL_DSLP_MOSC_PD) - { - ui32Value |= SYSCTL_DSCLKCFG_MOSCDPD; - } - - // - // Update the deep-sleep clock configuration. - // - HWREG(SYSCTL_DSCLKCFG) = ui32Value; - } -} - -//***************************************************************************** -// -//! Sets the PWM clock configuration. -//! -//! \param ui32Config is the configuration for the PWM clock; it must be one of -//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, -//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or -//! \b SYSCTL_PWMDIV_64. -//! -//! This function configures the rate of the clock provided to the PWM module -//! as a ratio of the processor clock. This clock is used by the PWM module to -//! generate PWM signals; its rate forms the basis for all PWM signals. -//! -//! \note This function should only be used with TM4C123 devices. For -//! other TM4C devices, the PWMClockSet() function should be used. -//! -//! \note The clocking of the PWM is dependent on the system clock rate as -//! configured by SysCtlClockSet(). -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPWMClockSet(uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT((ui32Config == SYSCTL_PWMDIV_1) || - (ui32Config == SYSCTL_PWMDIV_2) || - (ui32Config == SYSCTL_PWMDIV_4) || - (ui32Config == SYSCTL_PWMDIV_8) || - (ui32Config == SYSCTL_PWMDIV_16) || - (ui32Config == SYSCTL_PWMDIV_32) || - (ui32Config == SYSCTL_PWMDIV_64)); - - // - // Check that there is a PWM block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1)); - - // - // Set the PWM clock configuration into the run-mode clock configuration - // register. - // - HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & - ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) | - ui32Config); -} - -//***************************************************************************** -// -//! Gets the current PWM clock configuration. -//! -//! This function returns the current PWM clock configuration. -//! -//! \return Returns the current PWM clock configuration; is one of -//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, -//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or -//! \b SYSCTL_PWMDIV_64. -//! -//! \note This function should only be used with TM4C123 devices. For -//! other TM4C devices, the PWMClockGet() function should be used. -// -//***************************************************************************** -uint32_t -SysCtlPWMClockGet(void) -{ - // - // Check that there is a PWM block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1)); - - // - // Return the current PWM clock configuration. Make sure that - // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled. - // - if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV)) - { - // - // The divider is not active so reflect this in the value we return. - // - return(SYSCTL_PWMDIV_1); - } - else - { - // - // The divider is active so directly return the masked register value. - // - return(HWREG(SYSCTL_RCC) & - (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)); - } -} - -//***************************************************************************** -// -//! Enables access to a GPIO peripheral via the AHB. -//! -//! \param ui32GPIOPeripheral is the GPIO peripheral to enable. -//! -//! This function is used to enable the specified GPIO peripheral to be -//! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced -//! Peripheral Bus (APB). When a GPIO peripheral is enabled for AHB access, -//! the \b _AHB_BASE form of the base address should be used for GPIO -//! functions. For example, instead of using \b GPIO_PORTA_BASE as the base -//! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead. -//! -//! The \e ui32GPIOPeripheral argument must be only one of the following -//! values: -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. -//! -//! \note On some devices, all GPIO ports are only available on AHB. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ)); - - // - // Enable this GPIO for AHB access. - // - HWREG(SYSCTL_GPIOHBCTL) |= (1 << (ui32GPIOPeripheral & 0xF)); -} - -//***************************************************************************** -// -//! Disables access to a GPIO peripheral via the AHB. -//! -//! \param ui32GPIOPeripheral is the GPIO peripheral to disable. -//! -//! This function disables the specified GPIO peripheral for access from the -//! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed -//! from the legacy Advanced Peripheral Bus (APB). -//! -//! The \b ui32GPIOPeripheral argument must be only one of the following -//! values: -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. -//! -//! \note Some devices allow disabling AHB access to GPIO ports that are only -//! present on the AHB. Disabling AHB access to these ports will disable -//! access to these GPIO ports. On some devices, all GPIO ports are only -//! available on AHB. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ)); - - // - // Disable this GPIO for AHB access. - // - HWREG(SYSCTL_GPIOHBCTL) &= ~(1 << (ui32GPIOPeripheral & 0xF)); -} - -//***************************************************************************** -// -//! Powers up the USB PLL. -//! -//! This function enables the USB controller's PLL, which is used by its -//! physical layer. This call is necessary before connecting to any external -//! devices. -//! -//! \note This function should only be called on TM4C123 devices. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlUSBPLLEnable(void) -{ - // - // Turn on the USB PLL. - // - HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN; -} - -//***************************************************************************** -// -//! Powers down the USB PLL. -//! -//! This function disables the USB controller's PLL, which is used by its -//! physical layer. The USB registers are still accessible, but the physical -//! layer no longer functions. -//! -//! \note This function should only be called on TM4C123 devices. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlUSBPLLDisable(void) -{ - // - // Turn off the USB PLL. - // - HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN; -} - -//***************************************************************************** -// -//! Configures the response to system voltage events. -//! -//! \param ui32Config holds the configuration options for the voltage events. -//! -//! This function configures the response to voltage-related events. -//! These events are triggered when the voltage rails drop below certain -//! levels. The \e ui32Config parameter provides the configuration for the -//! voltage events and is a combination of the \b SYSCTL_VEVENT_* values. -//! -//! The response to a brown out on the VDDA rail is set by using one of the -//! following values: -//! - \b SYSCTL_VEVENT_VDDABO_NONE - There is no action taken on a VDDA -//! brown out. -//! - \b SYSCTL_VEVENT_VDDABO_INT - A system interrupt is generated when a -//! VDDA brown out occurs. -//! - \b SYSCTL_VEVENT_VDDABO_NMI - An NMI is generated when a VDDA brown out -//! occurs. -//! - \b SYSCTL_VEVENT_VDDABO_RST - A reset is generated when a VDDA brown out -//! occurs. The type of reset that is generated is controller by the -//! \b SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet() -//! function. -//! -//! The response to a brown out on the VDD rail is set by using one of the -//! following values: -//! - \b SYSCTL_VEVENT_VDDBO_NONE - There is no action taken on a VDD -//! brown out. -//! - \b SYSCTL_VEVENT_VDDBO_INT - A system interrupt is generated when a -//! VDD brown out occurs. -//! - \b SYSCTL_VEVENT_VDDBO_NMI - An NMI is generated when a VDD brown out -//! occurs. -//! - \b SYSCTL_VEVENT_VDDBO_RST - A reset is generated when a VDD brown out -//! occurs. The type of reset that is generated is controller by the -//! \b SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet() -//! function. -//! -//! \b Example: Configure the voltage events to trigger an interrupt on a VDDA -//! brown out, an NMI on a VDDC brown out and a reset on a VDD brown out. -//! -//! \verbatim -//! -//! // -//! // Configure the BOR rest to trigger a full POR. This is needed because -//! // the SysCtlVoltageEventConfig() call is triggering a reset so the type -//! // of reset is specified by this call. -//! // -//! SysCtlResetBehaviorSet(SYSCTL_ONRST_BOR_POR); -//! -//! // -//! // Trigger an interrupt on a VDDA brown out and a reset on a VDD brown out. -//! // -//! SysCtlVoltageEventConfig(SYSCTL_VEVENT_VDDABO_INT | -//! SYSCTL_VEVENT_VDDBO_RST); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlVoltageEventConfig(uint32_t ui32Config) -{ - // - // Set the requested events. - // - HWREG(SYSCTL_PTBOCTL) = ui32Config; -} - -//***************************************************************************** -// -//! Returns the voltage event status. -//! -//! This function returns the voltage event status for the system controller. -//! The value returned is a logical OR of the following values: -//! - \b SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail. -//! - \b SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail. -//! -//! The values returned from this function can be passed to the -//! SysCtlVoltageEventClear() to clear the current voltage event status. -//! Because voltage events are not cleared due to a reset, the voltage event -//! status must be cleared by calling SysCtlVoltageEventClear(). -//! -//! \b Example: Clear the current voltage event status. -//! -//! \verbatim -//! uint32_t ui32VoltageEvents; -//! -//! // -//! // Read the current voltage event status. -//! // -//! ui32VoltageEvents = SysCtlVoltageEventStatus(); -//! -//! // -//! // Clear all the current voltage events. -//! // -//! SysCtlVoltageEventClear(ui32VoltageEvents); -//! \endverbatim -//! -//! \return The current voltage event status. -//! -//! \note The availability of voltage events varies with the Tiva part -//! in use. Please consult the data sheet for the part you are using to -//! determine which interrupt sources are available. -// -//***************************************************************************** -uint32_t -SysCtlVoltageEventStatus(void) -{ - // - // Return the current voltage event status. - // - return(HWREG(SYSCTL_PWRTC)); -} - -//***************************************************************************** -// -//! Clears the voltage event status. -//! -//! \param ui32Status is a bit mask of the voltage events to clear. -//! -//! This function clears the current voltage events status for the values -//! specified in the \e ui32Status parameter. The \e ui32Status value must be -//! a logical OR of the following values: -//! - \b SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail. -//! - \b SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail. -//! -//! \b Example: Clear the current voltage event status. -//! -//! \verbatim -//! // -//! // Clear all the current voltage events. -//! // -//! SysCtlVoltageEventClear(SysCtlVoltageEventStatus()); -//! \endverbatim -//! -//! \note The availability of voltage event status varies with the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlVoltageEventClear(uint32_t ui32Status) -{ - // - // Clear the requested voltage events. - // - HWREG(SYSCTL_PWRTC) |= ui32Status; -} - -//***************************************************************************** -// -//! Gets the effective VCO frequency. -//! -//! \param ui32Crystal holds the crystal value used for the PLL. -//! \param pui32VCOFrequency is a pointer to the storage location which holds -//! value of the VCO computed. -//! -//! This function calculates the VCO of the PLL before the system divider is -//! applied -//! -//! \return \b true if the PLL is configured correctly and a VCO is valid or -//! \b false if the device is not TM4C129x or the PLL is not used -// -//***************************************************************************** -bool -SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency) -{ - int32_t i32XtalIdx; - uint32_t ui32RSClkConfig, ui32PLLFreq0, ui32PLLFreq1, ui32Osc; - uint32_t ui32MInt, ui32MFrac, ui32NDiv, ui32QDiv, ui32TempVCO; - - // - // Check if TM4C123 device is being used. should not use this function. - // - if(CLASS_IS_TM4C123) - { - // - // Return error if TM4C123. - // - *pui32VCOFrequency = 0; - return(false); - } - - // - // Read the RSCLKCFG register to determine if PLL is being used. - // - ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); - - // - // Check if PLL is used. - // - if((ui32RSClkConfig & SYSCTL_RSCLKCFG_USEPLL) != SYSCTL_RSCLKCFG_USEPLL) - { - // - // Return error if PLL is not used. - // - *pui32VCOFrequency = 0; - return(false); - } - - // - // Get the index of the crystal from the ui32Config parameter. - // - i32XtalIdx = SysCtlXtalCfgToIndex(ui32Crystal); - - // - // Get the value of the crystal frequency based on the index - // - ui32Osc = g_pui32Xtals[i32XtalIdx]; - - // - // Read the PLLFREQ0 and PLLFREQ1 registers to get information on the - // MINT, MFRAC, N and Q values of the PLL - // - ui32PLLFreq0 = HWREG(SYSCTL_PLLFREQ0); - ui32PLLFreq1 = HWREG(SYSCTL_PLLFREQ1); - - ui32MInt = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MINT_M) >> - SYSCTL_PLLFREQ0_MINT_S; - ui32MFrac = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MFRAC_M) >> - SYSCTL_PLLFREQ0_MFRAC_S; - ui32NDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_N_M) >> - SYSCTL_PLLFREQ1_N_S; - ui32QDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_Q_M) >> - SYSCTL_PLLFREQ1_Q_S; - - // - // Calculate the VCO at the output of the PLL - // - ui32TempVCO = (ui32Osc * ui32MInt) + ((ui32Osc * ui32MFrac) / 1024); - ui32TempVCO /= ((ui32NDiv + 1) * (ui32QDiv + 1)); - - *pui32VCOFrequency = ui32TempVCO; - return(true); -} - -//***************************************************************************** -// -//! Returns the current NMI status. -//! -//! This function returns the NMI status for the system controller. The valid -//! values for the \e ui32Ints parameter are a logical OR of the following -//! values: -//! - \b SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not -//! start. -//! - \b SYSCTL_NMI_TAMPER a tamper event has been detected. -//! - \b SYSCTL_NMI_WDT0 watchdog 0 generated a timeout. -//! - \b SYSCTL_NMI_WDT1 watchdog 1 generated a timeout. -//! - \b SYSCTL_NMI_POWER a power event occurred. -//! - \b SYSCTL_NMI_EXTERNAL an external NMI pin asserted. -//! -//! \b Example: Clear all current NMI status flags. -//! -//! \verbatim -//! -//! // -//! // Clear all the current NMI sources. -//! // -//! SysCtlNMIClear(SysCtlNMIStatus()); -//! \endverbatim -//! -//! \note The availability of the NMI status varies with the Tiva part in -//! use. Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return The current NMI status. -// -//***************************************************************************** -uint32_t -SysCtlNMIStatus(void) -{ - return(HWREG(SYSCTL_NMIC)); -} - -//***************************************************************************** -// -//! Clears NMI sources. -//! -//! \param ui32Ints is a bit mask of the non-maskable interrupt sources. -//! -//! This function clears the current NMI status specified in the \e ui32Ints -//! parameter. The valid values for the \e ui32Ints parameter are a logical OR -//! of the following values: -//! - \b SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not -//! start. -//! - \b SYSCTL_NMI_TAMPER a tamper event has been detected. -//! - \b SYSCTL_NMI_WDT0 watchdog 0 generated a timeout. -//! - \b SYSCTL_NMI_WDT1 watchdog 1 generated a timeout. -//! - \b SYSCTL_NMI_POWER a power event occurred. -//! - \b SYSCTL_NMI_EXTERNAL an external NMI pin asserted. -//! -//! \b Example: Clear all current NMI status flags. -//! -//! \verbatim -//! -//! // -//! // Clear all the current NMI sources. -//! // -//! SysCtlNMIClear(SysCtlNMIStatus()); -//! \endverbatim -//! -//! \note The availability of the NMI status varies with the Tiva part in -//! use. Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlNMIClear(uint32_t ui32Ints) -{ - // - // Clear the requested interrupt sources. - // - HWREG(SYSCTL_NMIC) &= ~ui32Ints; -} - -//***************************************************************************** -// -//! Configures and enables or disables the clock output on the DIVSCLK pin. -//! -//! \param ui32Config holds the configuration options including enabling or -//! disabling the clock output on the DIVSCLK pin. -//! \param ui32Div is the divisor for the clock selected in the \e ui32Config -//! parameter. -//! -//! This function selects the source for the DIVSCLK, enables or disables -//! the clock output and provides an output divider value. The \e ui32Div -//! parameter specifies the divider for the selected clock source and has a -//! valid range of 1-256. The \e ui32Config parameter configures -//! the DIVSCLK output based on the following settings: -//! -//! The first setting allows the output to be enabled or disabled. -//! - \b SYSCTL_CLKOUT_EN - enable the DIVSCLK output. -//! - \b SYSCTL_CLKOUT_DIS - disable the DIVSCLK output (default). -//! -//! The next group of settings selects the source for the DIVSCLK. -//! - \b SYSCTL_CLKOUT_SYSCLK - use the current system clock as the -//! source (default). -//! - \b SYSCTL_CLKOUT_PIOSC - use the PIOSC as the source. -//! - \b SYSCTL_CLKOUT_MOSC - use the MOSC as the source. -//! -//! \b Example: Enable the PIOSC divided by 4 as the DIVSCLK output. -//! -//! \verbatim -//! -//! // -//! // Enable the PIOSC divided by 4 as the DIVSCLK output. -//! // -//! SysCtlClockOutConfig(SYSCTL_DIVSCLK_EN | SYSCTL_DIVSCLK_SRC_PIOSC, 4); -//! \endverbatim -//! -//! \note The availability of the DIVSCLK output varies with the Tiva part -//! in use. Please consult the data sheet for the part you are using to -//! determine which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div) -{ - ASSERT(ui32Div != 0); - ASSERT((ui32Config & ~(SYSCTL_CLKOUT_EN | SYSCTL_CLKOUT_DIS | - SYSCTL_CLKOUT_SYSCLK | SYSCTL_CLKOUT_PIOSC | - SYSCTL_CLKOUT_MOSC)) == 0); - - // - // Set the requested configuration and divisor. - // - HWREG(SYSCTL_DIVSCLK) = ui32Config | ((ui32Div - 1) & - SYSCTL_DIVSCLK_DIV_M); -} - -//***************************************************************************** -// -//! Configures the alternate peripheral clock source. -//! -//! \param ui32Config holds the configuration options for the alternate -//! peripheral clock. -//! -//! This function configures the alternate peripheral clock. The alternate -//! peripheral clock is used to provide a known clock in all operating modes -//! to peripherals that support using the alternate peripheral clock as an -//! input clock. The \e ui32Config parameter value provides the clock input -//! source using one of the following values: -//! - \b SYSCTL_ALTCLK_PIOSC - use the PIOSC as the alternate clock -//! source (default). -//! - \b SYSCTL_ALTCLK_RTCOSC - use the Hibernate module RTC clock as the -//! alternate clock source. -//! - \b SYSCTL_ALTCLK_LFIOSC - use the low-frequency internal oscillator as -//! the alternate clock source. -//! -//! \b Example: Select the Hibernate module RTC clock as the alternate clock -//! source. -//! -//! \verbatim -//! -//! // -//! // Select the Hibernate module RTC clock as the alternate clock source. -//! // -//! SysCtlAltClkConfig(SYSCTL_ALTCLK_RTCOSC); -//! \endverbatim -//! -//! \note The availability of the alternate peripheral clock varies with the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlAltClkConfig(uint32_t ui32Config) -{ - // - // Set the requested configuration and divisor. - // - HWREG(SYSCTL_ALTCLKCFG) = ui32Config; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sysctl.h b/bsp/tm4c129x-dk/libraries/driverlib/sysctl.h deleted file mode 100644 index 0bce4852d7c19d0652233972f7f509c98c5bb5e9..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/sysctl.h +++ /dev/null @@ -1,656 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_SYSCTL_H__ -#define __DRIVERLIB_SYSCTL_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ui32Peripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_ADC0 0xf0003800 // ADC 0 -#define SYSCTL_PERIPH_ADC1 0xf0003801 // ADC 1 -#define SYSCTL_PERIPH_CAN0 0xf0003400 // CAN 0 -#define SYSCTL_PERIPH_CAN1 0xf0003401 // CAN 1 -#define SYSCTL_PERIPH_COMP0 0xf0003c00 // Analog Comparator Module 0 -#define SYSCTL_PERIPH_EMAC0 0xf0009c00 // Ethernet MAC0 -#define SYSCTL_PERIPH_EPHY0 0xf0003000 // Ethernet PHY0 -#define SYSCTL_PERIPH_EPI0 0xf0001000 // EPI0 -#define SYSCTL_PERIPH_GPIOA 0xf0000800 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0xf0000801 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0xf0000802 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0xf0000803 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0xf0000804 // GPIO E -#define SYSCTL_PERIPH_GPIOF 0xf0000805 // GPIO F -#define SYSCTL_PERIPH_GPIOG 0xf0000806 // GPIO G -#define SYSCTL_PERIPH_GPIOH 0xf0000807 // GPIO H -#define SYSCTL_PERIPH_GPIOJ 0xf0000808 // GPIO J -#define SYSCTL_PERIPH_HIBERNATE 0xf0001400 // Hibernation module -#define SYSCTL_PERIPH_CCM0 0xf0007400 // CCM 0 -#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0 -#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0 -#define SYSCTL_PERIPH_FAN1 0xf0005401 // FAN 1 -#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K -#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L -#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M -#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N -#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P -#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q -#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R -#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S -#define SYSCTL_PERIPH_GPIOT 0xf0000811 // GPIO T -#define SYSCTL_PERIPH_I2C0 0xf0002000 // I2C 0 -#define SYSCTL_PERIPH_I2C1 0xf0002001 // I2C 1 -#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2 -#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3 -#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4 -#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5 -#define SYSCTL_PERIPH_I2C6 0xf0002006 // I2C 6 -#define SYSCTL_PERIPH_I2C7 0xf0002007 // I2C 7 -#define SYSCTL_PERIPH_I2C8 0xf0002008 // I2C 8 -#define SYSCTL_PERIPH_I2C9 0xf0002009 // I2C 9 -#define SYSCTL_PERIPH_LCD0 0xf0009000 // LCD 0 -#define SYSCTL_PERIPH_ONEWIRE0 0xf0009800 // One Wire 0 -#define SYSCTL_PERIPH_PWM0 0xf0004000 // PWM 0 -#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1 -#define SYSCTL_PERIPH_QEI0 0xf0004400 // QEI 0 -#define SYSCTL_PERIPH_QEI1 0xf0004401 // QEI 1 -#define SYSCTL_PERIPH_SSI0 0xf0001c00 // SSI 0 -#define SYSCTL_PERIPH_SSI1 0xf0001c01 // SSI 1 -#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2 -#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3 -#define SYSCTL_PERIPH_TIMER0 0xf0000400 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0xf0000401 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0xf0000402 // Timer 2 -#define SYSCTL_PERIPH_TIMER3 0xf0000403 // Timer 3 -#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4 -#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5 -#define SYSCTL_PERIPH_TIMER6 0xf0000406 // Timer 6 -#define SYSCTL_PERIPH_TIMER7 0xf0000407 // Timer 7 -#define SYSCTL_PERIPH_UART0 0xf0001800 // UART 0 -#define SYSCTL_PERIPH_UART1 0xf0001801 // UART 1 -#define SYSCTL_PERIPH_UART2 0xf0001802 // UART 2 -#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3 -#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4 -#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5 -#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6 -#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7 -#define SYSCTL_PERIPH_UDMA 0xf0000c00 // uDMA -#define SYSCTL_PERIPH_USB0 0xf0002800 // USB 0 -#define SYSCTL_PERIPH_WDOG0 0xf0000000 // Watchdog 0 -#define SYSCTL_PERIPH_WDOG1 0xf0000001 // Watchdog 1 -#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0 -#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1 -#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2 -#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3 -#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4 -#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSleepSet() and -// SysCtlLDODeepSleepSet() APIs as the ui32Voltage value, or returned by the -// SysCtlLDOSleepGet() and SysCtlLDODeepSleepGet() APIs. -// -//***************************************************************************** -#define SYSCTL_LDO_0_90V 0x80000012 // LDO output of 0.90V -#define SYSCTL_LDO_0_95V 0x80000013 // LDO output of 0.95V -#define SYSCTL_LDO_1_00V 0x80000014 // LDO output of 1.00V -#define SYSCTL_LDO_1_05V 0x80000015 // LDO output of 1.05V -#define SYSCTL_LDO_1_10V 0x80000016 // LDO output of 1.10V -#define SYSCTL_LDO_1_15V 0x80000017 // LDO output of 1.15V -#define SYSCTL_LDO_1_20V 0x80000018 // LDO output of 1.20V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_BOR0 0x00000800 // VDD under BOR0 -#define SYSCTL_INT_VDDA_OK 0x00000400 // VDDA Power OK -#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt -#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_BOR1 0x00000002 // VDD under BOR1 -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_HSRVREQ 0x00001000 // Hardware System Service Request -#define SYSCTL_CAUSE_HIB 0x00000040 // Hibernate reset -#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset -#ifndef DEPRECATED -#define SYSCTL_CAUSE_WDOG SYSCTL_CAUSE_WDOG0 - // Watchdog reset(Deprecated) -#endif -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ui32Config parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ui32Config parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ui32Config parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 -#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 -#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 -#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 -#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 -#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 -#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 -#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 -#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 -#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 -#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 -#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 -#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 -#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 -#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 -#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 -#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 -#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 -#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 -#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 -#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 -#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 -#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 -#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 -#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 -#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 -#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 -#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 -#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 -#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 -#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 -#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 -#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 -#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 -#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 -#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 -#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 -#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 -#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 -#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 -#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 -#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 -#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 -#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 -#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 -#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 -#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 -#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 -#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5 -#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5 -#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5 -#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5 -#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5 -#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5 -#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5 -#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5 -#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5 -#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5 -#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5 -#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5 -#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5 -#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5 -#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5 -#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5 -#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5 -#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5 -#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5 -#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5 -#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5 -#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5 -#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5 -#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5 -#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5 -#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5 -#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5 -#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5 -#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5 -#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5 -#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5 -#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5 -#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5 -#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5 -#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5 -#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5 -#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5 -#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5 -#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5 -#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5 -#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5 -#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5 -#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5 -#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5 -#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5 -#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5 -#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5 -#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5 -#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5 -#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5 -#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5 -#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5 -#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5 -#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5 -#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5 -#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5 -#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5 -#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5 -#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5 -#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 -#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 -#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 -#define SYSCTL_CFG_VCO_480 0xF1000000 // VCO is 480 MHz -#define SYSCTL_CFG_VCO_320 0xF0000000 // VCO is 320 MHz -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz -#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz -#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz -#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz -#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz -#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz -#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz -#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz -#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz -#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz -#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz -#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz -#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz -#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 -#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz -#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlDeepSleepClockSet() -// API as the ui32Config parameter. -// -//***************************************************************************** -#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1 -#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2 -#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3 -#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4 -#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5 -#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6 -#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7 -#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8 -#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9 -#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10 -#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11 -#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12 -#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13 -#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14 -#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15 -#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16 -#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17 -#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18 -#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19 -#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20 -#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21 -#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22 -#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23 -#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24 -#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25 -#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26 -#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27 -#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28 -#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29 -#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30 -#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31 -#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32 -#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33 -#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34 -#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35 -#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36 -#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37 -#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38 -#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39 -#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40 -#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41 -#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42 -#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43 -#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44 -#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45 -#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46 -#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47 -#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48 -#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49 -#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50 -#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51 -#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52 -#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53 -#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54 -#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55 -#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56 -#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57 -#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58 -#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59 -#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60 -#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61 -#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62 -#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63 -#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64 -#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc -#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc -#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz -#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz -#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep -#define SYSCTL_DSLP_MOSC_PD 0x40000000 // Power down MOSC in deep-sleep - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPIOSCCalibrate() -// API as the ui32Type parameter. -// -//***************************************************************************** -#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration -#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration -#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlMOSCConfigSet() API -// as the ui32Config parameter. -// -//***************************************************************************** -#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation -#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail -#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC -#define SYSCTL_MOSC_PWR_DIS 0x00000008 // Power down the MOSC. -#define SYSCTL_MOSC_LOWFREQ 0x00000000 // MOSC is less than 10MHz -#define SYSCTL_MOSC_HIGHFREQ 0x00000010 // MOSC is greater than 10MHz -#define SYSCTL_MOSC_SESRC 0x00000020 // Singled ended oscillator source. - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlSleepPowerSet() and -// SysCtlDeepSleepPowerSet() APIs as the ui32Config parameter. -// -//***************************************************************************** -#define SYSCTL_LDO_SLEEP 0x00000200 // LDO in sleep mode - // (Deep Sleep Only) -#define SYSCTL_TEMP_LOW_POWER 0x00000100 // Temp sensor in low power mode - // (Deep Sleep Only) -#define SYSCTL_FLASH_NORMAL 0x00000000 // Flash in normal mode -#define SYSCTL_FLASH_LOW_POWER 0x00000020 // Flash in low power mode -#define SYSCTL_SRAM_NORMAL 0x00000000 // SRAM in normal mode -#define SYSCTL_SRAM_STANDBY 0x00000001 // SRAM in standby mode -#define SYSCTL_SRAM_LOW_POWER 0x00000003 // SRAM in low power mode - -//***************************************************************************** -// -// Defines for the SysCtlResetBehaviorSet() and SysCtlResetBehaviorGet() APIs. -// -//***************************************************************************** -#define SYSCTL_ONRST_WDOG0_POR 0x00000030 -#define SYSCTL_ONRST_WDOG0_SYS 0x00000020 -#define SYSCTL_ONRST_WDOG1_POR 0x000000C0 -#define SYSCTL_ONRST_WDOG1_SYS 0x00000080 -#define SYSCTL_ONRST_BOR_POR 0x0000000C -#define SYSCTL_ONRST_BOR_SYS 0x00000008 -#define SYSCTL_ONRST_EXT_POR 0x00000003 -#define SYSCTL_ONRST_EXT_SYS 0x00000002 - -//***************************************************************************** -// -// Values used with the SysCtlVoltageEventConfig() API. -// -//***************************************************************************** -#define SYSCTL_VEVENT_VDDABO_NONE \ - 0x00000000 -#define SYSCTL_VEVENT_VDDABO_INT \ - 0x00000100 -#define SYSCTL_VEVENT_VDDABO_NMI \ - 0x00000200 -#define SYSCTL_VEVENT_VDDABO_RST \ - 0x00000300 -#define SYSCTL_VEVENT_VDDBO_NONE \ - 0x00000000 -#define SYSCTL_VEVENT_VDDBO_INT 0x00000001 -#define SYSCTL_VEVENT_VDDBO_NMI 0x00000002 -#define SYSCTL_VEVENT_VDDBO_RST 0x00000003 - -//***************************************************************************** -// -// Values used with the SysCtlVoltageEventStatus() and -// SysCtlVoltageEventClear() APIs. -// -//***************************************************************************** -#define SYSCTL_VESTAT_VDDBOR 0x00000040 -#define SYSCTL_VESTAT_VDDABOR 0x00000010 - -//***************************************************************************** -// -// Values used with the SysCtlNMIStatus() API. -// -//***************************************************************************** -#define SYSCTL_NMI_MOSCFAIL 0x00010000 -#define SYSCTL_NMI_TAMPER 0x00000200 -#define SYSCTL_NMI_WDT1 0x00000020 -#define SYSCTL_NMI_WDT0 0x00000008 -#define SYSCTL_NMI_POWER 0x00000004 -#define SYSCTL_NMI_EXTERNAL 0x00000001 - -//***************************************************************************** -// -// The defines for the SysCtlClockOutConfig() API. -// -//***************************************************************************** -#define SYSCTL_CLKOUT_EN 0x80000000 -#define SYSCTL_CLKOUT_DIS 0x00000000 -#define SYSCTL_CLKOUT_SYSCLK 0x00000000 -#define SYSCTL_CLKOUT_PIOSC 0x00010000 -#define SYSCTL_CLKOUT_MOSC 0x00020000 - -//***************************************************************************** -// -// The following defines are used with the SysCtlAltClkConfig() function. -// -//***************************************************************************** -#define SYSCTL_ALTCLK_PIOSC 0x00000000 -#define SYSCTL_ALTCLK_RTCOSC 0x00000003 -#define SYSCTL_ALTCLK_LFIOSC 0x00000004 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern uint32_t SysCtlSRAMSizeGet(void); -extern uint32_t SysCtlFlashSizeGet(void); -extern uint32_t SysCtlFlashSectorSizeGet(void); -extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral); -extern bool SysCtlPeripheralReady(uint32_t ui32Peripheral); -extern void SysCtlPeripheralPowerOn(uint32_t ui32Peripheral); -extern void SysCtlPeripheralPowerOff(uint32_t ui32Peripheral); -extern void SysCtlPeripheralReset(uint32_t ui32Peripheral); -extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralClockGating(bool bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(uint32_t ui32Ints); -extern void SysCtlIntDisable(uint32_t ui32Ints); -extern void SysCtlIntClear(uint32_t ui32Ints); -extern uint32_t SysCtlIntStatus(bool bMasked); -extern void SysCtlLDOSleepSet(uint32_t ui32Voltage); -extern uint32_t SysCtlLDOSleepGet(void); -extern void SysCtlLDODeepSleepSet(uint32_t ui32Voltage); -extern uint32_t SysCtlLDODeepSleepGet(void); -extern void SysCtlSleepPowerSet(uint32_t ui32Config); -extern void SysCtlDeepSleepPowerSet(uint32_t ui32Config); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern uint32_t SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(uint32_t ui32Causes); -extern void SysCtlBrownOutConfigSet(uint32_t ui32Config, - uint32_t ui32Delay); -extern void SysCtlDelay(uint32_t ui32Count); -extern void SysCtlMOSCConfigSet(uint32_t ui32Config); -extern uint32_t SysCtlPIOSCCalibrate(uint32_t ui32Type); -extern void SysCtlClockSet(uint32_t ui32Config); -extern uint32_t SysCtlClockGet(void); -extern void SysCtlDeepSleepClockSet(uint32_t ui32Config); -extern void SysCtlDeepSleepClockConfigSet(uint32_t ui32Div, - uint32_t ui32Config); -extern void SysCtlPWMClockSet(uint32_t ui32Config); -extern uint32_t SysCtlPWMClockGet(void); -extern void SysCtlIOSCVerificationSet(bool bEnable); -extern void SysCtlMOSCVerificationSet(bool bEnable); -extern void SysCtlPLLVerificationSet(bool bEnable); -extern void SysCtlClkVerificationClear(void); -extern void SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral); -extern void SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral); -extern void SysCtlUSBPLLEnable(void); -extern void SysCtlUSBPLLDisable(void); -extern uint32_t SysCtlClockFreqSet(uint32_t ui32Config, - uint32_t ui32SysClock); -extern void SysCtlResetBehaviorSet(uint32_t ui32Behavior); -extern uint32_t SysCtlResetBehaviorGet(void); -extern void SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div); -extern void SysCtlAltClkConfig(uint32_t ui32Config); -extern uint32_t SysCtlNMIStatus(void); -extern void SysCtlNMIClear(uint32_t ui32Status); -extern void SysCtlVoltageEventConfig(uint32_t ui32Config); -extern uint32_t SysCtlVoltageEventStatus(void); -extern void SysCtlVoltageEventClear(uint32_t ui32Status); -extern bool SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_SYSCTL_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sysexc.c b/bsp/tm4c129x-dk/libraries/driverlib/sysexc.c deleted file mode 100644 index d269b74bcd3008fc7526e3a03559741516b54c9a..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/sysexc.c +++ /dev/null @@ -1,311 +0,0 @@ -//***************************************************************************** -// -// sysexc.c - Routines for the System Exception Module. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup sysexc_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_sysexc.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -//! Returns the interrupt number for a system exception. -//! -//! This function returns the interrupt number for a system exception. -//! -//! \return Returns the system exception interrupt number. -// -//***************************************************************************** -static uint32_t -_SysExcIntNumberGet(void) -{ - uint32_t ui32Int; - - // - // Get the interrupt number based on the class. - // - if(CLASS_IS_TM4C123) - { - ui32Int = INT_SYSEXC_TM4C123; - } - else if(CLASS_IS_TM4C129) - { - ui32Int = INT_SYSEXC_TM4C129; - } - else - { - ui32Int = 0; - } - return(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the system exception interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the system -//! exception interrupt occurs. -//! -//! This function places the address of the system exception interrupt handler -//! into the interrupt vector table in SRAM. This function also enables the -//! global interrupt in the interrupt controller; specific system exception -//! interrupts must be enabled via SysExcIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SysExcIntRegister(void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Get the system exception interrupt number. - // - ui32Int = _SysExcIntNumberGet(); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the system exception interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters the system exception interrupt handler. -//! -//! This function removes the system exception interrupt handler from the -//! vector table in SRAM. This function also masks off the system exception -//! interrupt in the interrupt controller so that the interrupt handler is no -//! longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SysExcIntUnregister(void) -{ - uint32_t ui32Int; - - // - // Get the system exception interrupt number. - // - ui32Int = _SysExcIntNumberGet(); - - ASSERT(ui32Int != 0); - - // - // Disable the system exception interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the system exception interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables individual system exception interrupt sources. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated system exception interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt -//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt -//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt -//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt -//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt -//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt -//! -//! \return None. -// -//***************************************************************************** -void -SysExcIntEnable(uint32_t ui32IntFlags) -{ - // - // Enable the specified interrupts. - // - HWREG(SYSEXC_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual system exception interrupt sources. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated system exception interrupt sources. -//! Only sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt -//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt -//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt -//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt -//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt -//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt -//! -//! \return None. -// -//***************************************************************************** -void -SysExcIntDisable(uint32_t ui32IntFlags) -{ - // - // Disable the specified interrupts. - // - HWREG(SYSEXC_IM) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current system exception interrupt status. -//! -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the system exception interrupt status. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return Returns the current system exception interrupt status, enumerated -//! as the logical OR of \b SYSEXC_INT_FP_IXC, \b SYSEXC_INT_FP_OFC, -//! \b SYSEXC_INT_FP_UFC, \b SYSEXC_INT_FP_IOC, \b SYSEXC_INT_FP_DZC, and -//! \b SYSEXC_INT_FP_IDC. -// -//***************************************************************************** -uint32_t -SysExcIntStatus(bool bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(SYSEXC_MIS)); - } - else - { - return(HWREG(SYSEXC_RIS)); - } -} - -//***************************************************************************** -// -//! Clears system exception interrupt sources. -//! -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! This function clears the specified system exception interrupt sources, so -//! that they no longer assert. This function must be called in the interrupt -//! handler to keep the interrupt from being recognized again immediately upon -//! exit. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt -//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt -//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt -//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt -//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt -//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -SysExcIntClear(uint32_t ui32IntFlags) -{ - // - // Clear the requested interrupt sources. - // - HWREG(SYSEXC_IC) = ui32IntFlags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sysexc.h b/bsp/tm4c129x-dk/libraries/driverlib/sysexc.h deleted file mode 100644 index aece4409d18708e4c9dbb2804a180760af093ad3..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/sysexc.h +++ /dev/null @@ -1,89 +0,0 @@ -//***************************************************************************** -// -// sysexc.h - Prototypes for the System Exception Module routines. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_SYSEXC_H__ -#define __DRIVERLIB_SYSEXC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and -// SysExcIntClear as the ui32IntFlags parameter, and returned from -// SysExcIntStatus. -// -//***************************************************************************** -#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt -#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt -#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt -#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt -#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int -#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void SysExcIntRegister(void (*pfnHandler)(void)); -extern void SysExcIntUnregister(void); -extern void SysExcIntEnable(uint32_t ui32IntFlags); -extern void SysExcIntDisable(uint32_t ui32IntFlags); -extern uint32_t SysExcIntStatus(bool bMasked); -extern void SysExcIntClear(uint32_t ui32IntFlags); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_SYSEXC_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/systick.c b/bsp/tm4c129x-dk/libraries/driverlib/systick.c deleted file mode 100644 index 662da1729e79b79ebd14e183691e1fc3d424ae20..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/systick.c +++ /dev/null @@ -1,277 +0,0 @@ -//***************************************************************************** -// -// systick.c - Driver for the SysTick timer in NVIC. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup systick_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/systick.h" - -//***************************************************************************** -// -//! Enables the SysTick counter. -//! -//! This function starts the SysTick counter. If an interrupt handler has been -//! registered, it is called when the SysTick counter rolls over. -//! -//! \note Calling this function causes the SysTick counter to (re)commence -//! counting from its current value. The counter is not automatically reloaded -//! with the period as specified in a previous call to SysTickPeriodSet(). If -//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be -//! written to force the reload. Any write to this register clears the SysTick -//! counter to 0 and causes a reload with the supplied period on the next -//! clock. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickEnable(void) -{ - // - // Enable SysTick. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; -} - -//***************************************************************************** -// -//! Disables the SysTick counter. -//! -//! This function stops the SysTick counter. If an interrupt handler has been -//! registered, it is not called until SysTick is restarted. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickDisable(void) -{ - // - // Disable SysTick. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the SysTick interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! SysTick interrupt occurs. -//! -//! This function registers the handler to be called when a SysTick interrupt -//! occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(FAULT_SYSTICK, pfnHandler); - - // - // Enable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the SysTick interrupt. -//! -//! This function unregisters the handler to be called when a SysTick interrupt -//! occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickIntUnregister(void) -{ - // - // Disable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - - // - // Unregister the interrupt handler. - // - IntUnregister(FAULT_SYSTICK); -} - -//***************************************************************************** -// -//! Enables the SysTick interrupt. -//! -//! This function enables the SysTick interrupt, allowing it to be -//! reflected to the processor. -//! -//! \note The SysTick interrupt handler is not required to clear the SysTick -//! interrupt source because it is cleared automatically by the NVIC when the -//! interrupt handler is called. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickIntEnable(void) -{ - // - // Enable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} - -//***************************************************************************** -// -//! Disables the SysTick interrupt. -//! -//! This function disables the SysTick interrupt, preventing it from being -//! reflected to the processor. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickIntDisable(void) -{ - // - // Disable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); -} - -//***************************************************************************** -// -//! Sets the period of the SysTick counter. -//! -//! \param ui32Period is the number of clock ticks in each period of the -//! SysTick counter and must be between 1 and 16,777,216, inclusive. -//! -//! This function sets the rate at which the SysTick counter wraps, which -//! equates to the number of processor clocks between interrupts. -//! -//! \note Calling this function does not cause the SysTick counter to reload -//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT -//! register must be written. Any write to this register clears the SysTick -//! counter to 0 and causes a reload with the \e ui32Period supplied here on -//! the next clock after SysTick is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickPeriodSet(uint32_t ui32Period) -{ - // - // Check the arguments. - // - ASSERT((ui32Period > 0) && (ui32Period <= 16777216)); - - // - // Set the period of the SysTick counter. - // - HWREG(NVIC_ST_RELOAD) = ui32Period - 1; -} - -//***************************************************************************** -// -//! Gets the period of the SysTick counter. -//! -//! This function returns the rate at which the SysTick counter wraps, which -//! equates to the number of processor clocks between interrupts. -//! -//! \return Returns the period of the SysTick counter. -// -//***************************************************************************** -uint32_t -SysTickPeriodGet(void) -{ - // - // Return the period of the SysTick counter. - // - return(HWREG(NVIC_ST_RELOAD) + 1); -} - -//***************************************************************************** -// -//! Gets the current value of the SysTick counter. -//! -//! This function returns the current value of the SysTick counter, which is -//! a value between the period - 1 and zero, inclusive. -//! -//! \return Returns the current value of the SysTick counter. -// -//***************************************************************************** -uint32_t -SysTickValueGet(void) -{ - // - // Return the current value of the SysTick counter. - // - return(HWREG(NVIC_ST_CURRENT)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/systick.h b/bsp/tm4c129x-dk/libraries/driverlib/systick.h deleted file mode 100644 index 35909ee3fb8a975463952e9cdd9eb916ff47d4dc..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/systick.h +++ /dev/null @@ -1,78 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_SYSTICK_H__ -#define __DRIVERLIB_SYSTICK_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(uint32_t ui32Period); -extern uint32_t SysTickPeriodGet(void); -extern uint32_t SysTickValueGet(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_SYSTICK_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.c b/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.c deleted file mode 100644 index d348849570752c7dd9445cafc19a45e5cc4729eb..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.c +++ /dev/null @@ -1,1898 +0,0 @@ -//***************************************************************************** -// -// timer.c - Driver for the timer module. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup timer_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_timer.h" -#include "inc/hw_types.h" -#include "inc/hw_sysctl.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/tiva_timer.h" - -//***************************************************************************** -// -// A macro used to determine whether the target part supports new -// configuration and control options. -// -//***************************************************************************** -#define NEW_TIMER_CONFIGURATION CLASS_IS_TM4C129 - -//***************************************************************************** -// -// A mapping of timer base address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32TimerIntMap[][2] = -{ - { TIMER0_BASE, INT_TIMER0A_TM4C123 }, - { TIMER1_BASE, INT_TIMER1A_TM4C123 }, - { TIMER2_BASE, INT_TIMER2A_TM4C123 }, - { TIMER3_BASE, INT_TIMER3A_TM4C123 }, - { TIMER4_BASE, INT_TIMER4A_TM4C123 }, - { TIMER5_BASE, INT_TIMER5A_TM4C123 }, - { WTIMER0_BASE, INT_WTIMER0A_TM4C123 }, - { WTIMER1_BASE, INT_WTIMER1A_TM4C123 }, - { WTIMER2_BASE, INT_WTIMER2A_TM4C123 }, - { WTIMER3_BASE, INT_WTIMER3A_TM4C123 }, - { WTIMER4_BASE, INT_WTIMER4A_TM4C123 }, - { WTIMER5_BASE, INT_WTIMER5A_TM4C123 }, -}; -static const uint_fast8_t g_ui8TimerIntMapRows = - sizeof(g_ppui32TimerIntMap) / sizeof(g_ppui32TimerIntMap[0]); - -static const uint32_t g_ppui32TimerIntMapSnowflake[][2] = -{ - { TIMER0_BASE, INT_TIMER0A_TM4C129 }, - { TIMER1_BASE, INT_TIMER1A_TM4C129 }, - { TIMER2_BASE, INT_TIMER2A_TM4C129 }, - { TIMER3_BASE, INT_TIMER3A_TM4C129 }, - { TIMER4_BASE, INT_TIMER4A_TM4C129 }, - { TIMER5_BASE, INT_TIMER5A_TM4C129 }, - { TIMER6_BASE, INT_TIMER6A_TM4C129 }, - { TIMER7_BASE, INT_TIMER7A_TM4C129 }, -}; -static const uint_fast8_t g_ui8TimerIntMapRowsSnowflake = - sizeof(g_ppui32TimerIntMapSnowflake) / - sizeof(g_ppui32TimerIntMapSnowflake[0]); - -//***************************************************************************** -// -//! \internal -//! Checks a timer base address. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function determines if a timer module base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_TimerBaseValid(uint32_t ui32Base) -{ - return((ui32Base == TIMER0_BASE) || (ui32Base == TIMER1_BASE) || - (ui32Base == TIMER2_BASE) || (ui32Base == TIMER3_BASE) || - (ui32Base == TIMER4_BASE) || (ui32Base == TIMER5_BASE) || - (ui32Base == TIMER6_BASE) || (ui32Base == TIMER7_BASE) || - (ui32Base == WTIMER0_BASE) || (ui32Base == WTIMER1_BASE) || - (ui32Base == WTIMER2_BASE) || (ui32Base == WTIMER3_BASE) || - (ui32Base == WTIMER4_BASE) || (ui32Base == WTIMER5_BASE)); -} -#endif - -//***************************************************************************** -// -//! Returns a timer modules interrupt number. -//! -//! \param ui32Base is the base address of the selected timer. -//! \param ui32Timer specifies the timer(s) to enable; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function returns the interrupt number for a given timer module -//! specified by the \e ui32Base and \e ui32Timer parameter. -//! -//! \return Returns a timer module's interrupt number or 0 if the interrupt -//! does not exist. -// -//***************************************************************************** -static uint32_t -_TimerIntNumberGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - uint32_t ui32Int; - uint_fast8_t ui8Idx, ui8Rows; - const uint32_t (*ppui32SSIIntMap)[2]; - - // - // Default interrupt map. - // - ppui32SSIIntMap = g_ppui32TimerIntMap; - ui8Rows = g_ui8TimerIntMapRows; - - if(CLASS_IS_TM4C129) - { - ppui32SSIIntMap = g_ppui32TimerIntMapSnowflake; - ui8Rows = g_ui8TimerIntMapRowsSnowflake; - } - - // - // Loop through the table that maps timer base addresses to interrupt - // numbers. - // - for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++) - { - // - // See if this base address matches. - // - if(ppui32SSIIntMap[ui8Idx][0] == ui32Base) - { - ui32Int = ppui32SSIIntMap[ui8Idx][1]; - - if(ui32Timer == TIMER_B) - { - ui32Int += 1; - } - - // - // Return the corresponding interrupt number. - // - return(ui32Int); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Enables the timer(s). -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to enable; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function enables operation of the timer module. The timer must be -//! configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Enable the timer(s) module. - // - HWREG(ui32Base + TIMER_O_CTL) |= ui32Timer & (TIMER_CTL_TAEN | - TIMER_CTL_TBEN); -} - -//***************************************************************************** -// -//! Disables the timer(s). -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to disable; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function disables operation of the timer module. -//! -//! \return None. -// -//***************************************************************************** -void -TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Disable the timer module. - // - HWREG(ui32Base + TIMER_O_CTL) &= ~(ui32Timer & - (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); -} - -//***************************************************************************** -// -//! Configures the timer(s). -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Config is the configuration for the timer. -//! -//! This function configures the operating mode of the timer(s). The timer -//! module is disabled before being configured and is left in the disabled -//! state. The timer can be configured to be a single full-width timer -//! by using the \b TIMER_CFG_* values or a pair of half-width timers using the -//! \b TIMER_CFG_A_* and \b TIMER_CFG_B_* values passed in the \e ui32Config -//! parameter. -//! -//! The configuration is specified in \e ui32Config as one of the following -//! values: -//! -//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer -//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer -//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_RTC - Full-width real time clock timer -//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers -//! -//! When configured for a pair of half-width timers, each timer is separately -//! configured. The first timer is configured by setting \e ui32Config to -//! the result of a logical OR operation between one of the following values -//! and \e ui32Config: -//! -//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer -//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer -//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture -//! - \b TIMER_CFG_A_CAP_COUNT_UP - Half-width edge count capture that counts -//! up instead of down (not available on all parts) -//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture -//! - \b TIMER_CFG_A_CAP_TIME_UP - Half-width edge time capture that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_A_PWM - Half-width PWM output -//! -//! Some Tiva devices also allow configuring an action when the timers -//! reach their timeout. Please consult the data sheet for the part you are -//! using to determine whether configuring actions on timers is available. -//! -//! One of the following can be combined with the \b TIMER_CFG_* values to -//! enable an action on timer A: -//! -//! - \b TIMER_CFG_A_ACT_TOINTD - masks the timeout interrupt of timer A. -//! - \b TIMER_CFG_A_ACT_NONE - no additional action on timeout of timer A. -//! - \b TIMER_CFG_A_ACT_TOGGLE - toggle CCP on timeout of timer A. -//! - \b TIMER_CFG_A_ACT_SETTO - set CCP on timeout of timer A. -//! - \b TIMER_CFG_A_ACT_CLRTO - clear CCP on timeout of timer A. -//! - \b TIMER_CFG_A_ACT_SETTOGTO - set CCP immediately and then toggle it on -//! timeout of timer A. -//! - \b TIMER_CFG_A_ACT_CLRTOGTO - clear CCP immediately and then toggle it on -//! timeout of timer A. -//! - \b TIMER_CFG_A_ACT_SETCLRTO - set CCP immediately and then clear it on -//! timeout of timer A. -//! - \b TIMER_CFG_A_ACT_CLRSETTO - clear CCP immediately and then set it on -//! timeout of timer A. -//! -//! One of the following can be combined with the \b TIMER_CFG_* values to -//! enable an action on timer B: -//! -//! - \b TIMER_CFG_B_ACT_TOINTD - masks the timeout interrupt of timer B. -//! - \b TIMER_CFG_B_ACT_NONE - no additional action on timeout of timer B. -//! - \b TIMER_CFG_B_ACT_TOGGLE - toggle CCP on timeout of timer B. -//! - \b TIMER_CFG_B_ACT_SETTO - set CCP on timeout of timer B. -//! - \b TIMER_CFG_B_ACT_CLRTO - clear CCP on timeout of timer B. -//! - \b TIMER_CFG_B_ACT_SETTOGTO - set CCP immediately and then toggle it on -//! timeout of timer B. -//! - \b TIMER_CFG_B_ACT_CLRTOGTO - clear CCP immediately and then toggle it on -//! timeout of timer B. -//! - \b TIMER_CFG_B_ACT_SETCLRTO - set CCP immediately and then clear it on -//! timeout of timer B. -//! - \b TIMER_CFG_B_ACT_CLRSETTO - clear CCP immediately and then set it on -//! timeout of timer B. -//! -//! Similarly, the second timer is configured by setting \e ui32Config to -//! the result of a logical OR operation between one of the corresponding -//! \b TIMER_CFG_B_* values and \e ui32Config. -//! -//! \return None. -// -//***************************************************************************** -void -TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || - (ui32Config == TIMER_CFG_ONE_SHOT_UP) || - (ui32Config == TIMER_CFG_PERIODIC) || - (ui32Config == TIMER_CFG_PERIODIC_UP) || - (ui32Config == TIMER_CFG_RTC) || - ((ui32Config & 0xff000000) == TIMER_CFG_SPLIT_PAIR)); - ASSERT(((ui32Config & 0xff000000) != TIMER_CFG_SPLIT_PAIR) || - ((((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT_UP) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME_UP) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_PWM)) && - (((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PWM)))); - - // - // Disable the timers. - // - HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); - - // - // Set the global timer configuration. - // - HWREG(ui32Base + TIMER_O_CFG) = ui32Config >> 24; - - // - // Set the configuration of the A and B timers and set the TxPWMIE bit. - // Note that the B timer configuration is ignored by the hardware in 32-bit - // modes. - // - if(NEW_TIMER_CONFIGURATION) - { - HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) | - (ui32Config & 0xff) | - TIMER_TAMR_TAPWMIE); - HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) | - ((ui32Config >> 8) & 0xff) | - TIMER_TBMR_TBPWMIE); - } - else - { - HWREG(ui32Base + TIMER_O_TAMR) = ((ui32Config & 0xff) | - TIMER_TAMR_TAPWMIE); - HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config >> 8) & 0xff) | - TIMER_TBMR_TBPWMIE); - } -} - -//***************************************************************************** -// -//! Controls the output level. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param bInvert specifies the output level. -//! -//! This function configures the PWM output level for the specified timer. If -//! the \e bInvert parameter is \b true, then the timer's output is made active -//! low; otherwise, it is made active high. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the output levels as requested. - // - ui32Timer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; - HWREG(ui32Base + TIMER_O_CTL) = (bInvert ? - (HWREG(ui32Base + TIMER_O_CTL) | - ui32Timer) : - (HWREG(ui32Base + TIMER_O_CTL) & - ~(ui32Timer))); -} - -//***************************************************************************** -// -//! Enables or disables the ADC trigger output. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param bEnable specifies the desired ADC trigger state. -//! -//! This function controls the ADC trigger output for the specified timer. If -//! the \e bEnable parameter is \b true, then the timer's ADC output trigger is -//! enabled; otherwise it is disabled. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer, - bool bEnable) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // On newer devices the Timer time out ADC trigger enable must also - // be set. - // - if(NEW_TIMER_CONFIGURATION) - { - uint32_t ui32Val; - - // - // Determine which bits to set or clear in GPTMADCEV. - // - ui32Val = (TIMER_ADCEV_TATOADCEN | TIMER_ADCEV_TBTOADCEN); - ui32Val &= ui32Timer; - - // - // Write the GPTM ADC Event register to enable or disable the trigger - // to the ADC. - // - HWREG(ui32Base + TIMER_O_ADCEV) = (bEnable ? - (HWREG(ui32Base + TIMER_O_ADCEV) | - ui32Val) : - (HWREG(ui32Base + TIMER_O_ADCEV) & - ~(ui32Val))); - } - - // - // Set the trigger output as requested. - // Set the ADC trigger output as requested. - // - ui32Timer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; - HWREG(ui32Base + TIMER_O_CTL) = (bEnable ? - (HWREG(ui32Base + TIMER_O_CTL) | - ui32Timer) : - (HWREG(ui32Base + TIMER_O_CTL) & - ~(ui32Timer))); -} - -//***************************************************************************** -// -//! Controls the event type. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param ui32Event specifies the type of event; must be one of -//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or -//! \b TIMER_EVENT_BOTH_EDGES. -//! -//! This function configures the signal edge(s) that triggers the timer when -//! in capture mode. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Event) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the event type. - // - ui32Timer &= TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M; - HWREG(ui32Base + TIMER_O_CTL) = ((HWREG(ui32Base + TIMER_O_CTL) & - ~ui32Timer) | (ui32Event & ui32Timer)); -} - -//***************************************************************************** -// -//! Controls the stall handling. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param bStall specifies the response to a stall signal. -//! -//! This function controls the stall response for the specified timer. If the -//! \e bStall parameter is \b true, then the timer stops counting if the -//! processor enters debug mode; otherwise the timer keeps running while in -//! debug mode. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer, - bool bStall) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the stall mode. - // - ui32Timer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; - HWREG(ui32Base + TIMER_O_CTL) = (bStall ? - (HWREG(ui32Base + TIMER_O_CTL) | - ui32Timer) : - (HWREG(ui32Base + TIMER_O_CTL) & - ~(ui32Timer))); -} - -//***************************************************************************** -// -//! Controls the wait on trigger handling. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param bWait specifies if the timer should wait for a trigger input. -//! -//! This function controls whether or not a timer waits for a trigger input to -//! start counting. When enabled, the previous timer in the trigger chain must -//! count to its timeout in order for this timer to start counting. Refer to -//! the part's data sheet for a description of the trigger chain. -//! -//! \note This functionality is not available on all parts. This function -//! should not be used for Timer 0A or Wide Timer 0A. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer, - bool bWait) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the wait on trigger mode for timer A. - // - if((ui32Timer & TIMER_A) != 0) - { - if(bWait) - { - HWREG(ui32Base + TIMER_O_TAMR) |= TIMER_TAMR_TAWOT; - } - else - { - HWREG(ui32Base + TIMER_O_TAMR) &= ~(TIMER_TAMR_TAWOT); - } - } - - // - // Set the wait on trigger mode for timer B. - // - if((ui32Timer & TIMER_B) != 0) - { - if(bWait) - { - HWREG(ui32Base + TIMER_O_TBMR) |= TIMER_TBMR_TBWOT; - } - else - { - HWREG(ui32Base + TIMER_O_TBMR) &= ~(TIMER_TBMR_TBWOT); - } - } -} - -//***************************************************************************** -// -//! Enables RTC counting. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function causes the timer to start counting when in RTC mode. If not -//! configured for RTC mode, this function does nothing. -//! -//! \return None. -// -//***************************************************************************** -void -TimerRTCEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Enable RTC counting. - // - HWREG(ui32Base + TIMER_O_CTL) |= TIMER_CTL_RTCEN; -} - -//***************************************************************************** -// -//! Disables RTC counting. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function causes the timer to stop counting when in RTC mode. -//! -//! \return None. -// -//***************************************************************************** -void -TimerRTCDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Disable RTC counting. - // - HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN); -} - -//***************************************************************************** -// -//! Sets the clock source for the specified timer module. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Source is the clock source for the timer module. -//! -//! This function sets the clock source for both timer A and timer B for the -//! given timer module. The possible clock sources are the system clock -//! (\b TIMER_CLOCK_SYSTEM) or the precision internal oscillator -//! (\b TIMER_CLOCK_PIOSC). -//! -//! \note The ability to specify the timer clock source varies with the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerClockSourceSet(uint32_t ui32Base, uint32_t ui32Source) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Source == TIMER_CLOCK_SYSTEM) || - (ui32Source == TIMER_CLOCK_PIOSC)); - - // - // Set the timer clock source. - // - HWREG(ui32Base + TIMER_O_CC) = ui32Source; -} - -//***************************************************************************** -// -//! Returns the clock source for the specified timer module. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function returns the clock source for the specified timer module. The -//! possible clock sources are the system clock (\b TIMER_CLOCK_SYSTEM) or -//! the precision internal oscillator (\b TIMER_CLOCK_PIOSC). -//! -//! \note The ability to specify the timer clock source varies with the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return Returns either \b TIMER_CLOCK_SYSTEM or \b TIMER_CLOCK_PIOSC. -// -//***************************************************************************** -uint32_t -TimerClockSourceGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Return the timer clock source. - // - return(HWREG(ui32Base + TIMER_O_CC)); -} - -//***************************************************************************** -// -//! Sets the timer prescale value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param ui32Value is the timer prescale value which must be between 0 and -//! 255 (inclusive) for 16/32-bit timers and between 0 and 65535 (inclusive) -//! for 32/64-bit timers. -//! -//! This function configures the value of the input clock prescaler. The -//! prescaler is only operational when in half-width mode and is used to extend -//! the range of the half-width timer modes. The prescaler provides the least -//! significant bits when counting down in periodic and one-shot modes; in all -//! other modes, the prescaler provides the most significant bits. -//! -//! \note The availability of the prescaler varies with the Tiva part and -//! timer mode in use. Please consult the datasheet for the part you are using -//! to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - ASSERT(ui32Value < 256); - - // - // Set the timer A prescaler if requested. - // - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + TIMER_O_TAPR) = ui32Value; - } - - // - // Set the timer B prescaler if requested. - // - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + TIMER_O_TBPR) = ui32Value; - } -} - -//***************************************************************************** -// -//! Gets the timer prescale value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler. The prescaler -//! is only operational when in half-width mode and is used to extend the range -//! of the half-width timer modes. The prescaler provides the least -//! significant bits when counting down in periodic and one-shot modes; in all -//! other modes, the prescaler provides the most significant bits. -//! -//! \note The availability of the prescaler varies with the Tiva part and -//! timer mode in use. Please consult the datasheet for the part you are using -//! to determine whether this support is available. -//! -//! \return The value of the timer prescaler. -// -//***************************************************************************** -uint32_t -TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Return the appropriate prescale value. - // - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPR) : - HWREG(ui32Base + TIMER_O_TBPR)); -} - -//***************************************************************************** -// -//! Sets the timer prescale match value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param ui32Value is the timer prescale match value which must be between 0 -//! and 255 (inclusive) for 16/32-bit timers and between 0 and 65535 -//! (inclusive) for 32/64-bit timers. -//! -//! This function configures the value of the input clock prescaler match -//! value. When in a half-width mode that uses the counter match and the -//! prescaler, the prescale match effectively extends the range of the match. -//! The prescaler provides the least significant bits when counting down in -//! periodic and one-shot modes; in all other modes, the prescaler provides the -//! most significant bits. -//! -//! \note The availability of the prescaler match varies with the Tiva -//! part and timer mode in use. Please consult the datasheet for the part you -//! are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - ASSERT(ui32Value < 256); - - // - // Set the timer A prescale match if requested. - // - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + TIMER_O_TAPMR) = ui32Value; - } - - // - // Set the timer B prescale match if requested. - // - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + TIMER_O_TBPMR) = ui32Value; - } -} - -//***************************************************************************** -// -//! Gets the timer prescale match value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler match value. -//! When in a half-width mode that uses the counter match and prescaler, the -//! prescale match effectively extends the range of the match. The prescaler -//! provides the least significant bits when counting down in periodic and -//! one-shot modes; in all other modes, the prescaler provides the most -//! significant bits. -//! -//! \note The availability of the prescaler match varies with the Tiva -//! part and timer mode in use. Please consult the datasheet for the part you -//! are using to determine whether this support is available. -//! -//! \return The value of the timer prescale match. -// -//***************************************************************************** -uint32_t -TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Return the appropriate prescale match value. - // - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPMR) : - HWREG(ui32Base + TIMER_O_TBPMR)); -} - -//***************************************************************************** -// -//! Sets the timer load value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used -//! when the timer is configured for full-width operation. -//! \param ui32Value is the load value. -//! -//! This function configures the timer load value; if the timer is running then -//! the value is immediately loaded into the timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use -//! TimerLoadSet64() for full-width modes of 32/64-bit timers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the timer A load value if requested. - // - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + TIMER_O_TAILR) = ui32Value; - } - - // - // Set the timer B load value if requested. - // - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + TIMER_O_TBILR) = ui32Value; - } -} - -//***************************************************************************** -// -//! Gets the timer load value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for full-width operation. -//! -//! This function gets the currently programmed interval load value for the -//! specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use -//! TimerLoadGet64() for full-width modes of 32/64-bit timers. -//! -//! \return Returns the load value for the timer. -// -//***************************************************************************** -uint32_t -TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // - // Return the appropriate load value. - // - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAILR) : - HWREG(ui32Base + TIMER_O_TBILR)); -} - -//***************************************************************************** -// -//! Sets the timer load value for a 64-bit timer. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui64Value is the load value. -//! -//! This function configures the timer load value for a 64-bit timer; if the -//! timer is running, then the value is immediately loaded into the timer. -//! -//! \return None. -// -//***************************************************************************** -void -TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Set the timer load value. The upper 32-bits must be written before the - // lower 32-bits in order to adhere to the hardware interlocks on the - // 64-bit value. - // - HWREG(ui32Base + TIMER_O_TBILR) = ui64Value >> 32; - HWREG(ui32Base + TIMER_O_TAILR) = ui64Value & 0xffffffff; -} - -//***************************************************************************** -// -//! Gets the timer load value for a 64-bit timer. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function gets the currently programmed interval load value for the -//! specified 64-bit timer. -//! -//! \return Returns the load value for the timer. -// -//***************************************************************************** -uint64_t -TimerLoadGet64(uint32_t ui32Base) -{ - uint32_t ui32High1, ui32High2, ui32Low; - - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Read the 64-bit load value. A read of the low 32-bits is performed - // between two reads of the upper 32-bits; if the upper 32-bit values match - // then the 64-bit value is consistent. If they do not match, then the - // read is performed again until they do match (it should never execute the - // loop body more than twice). - // - do - { - ui32High1 = HWREG(ui32Base + TIMER_O_TBILR); - ui32Low = HWREG(ui32Base + TIMER_O_TAILR); - ui32High2 = HWREG(ui32Base + TIMER_O_TBILR); - } - while(ui32High1 != ui32High2); - - // - // Return the load value. - // - return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low); -} - -//***************************************************************************** -// -//! Gets the current timer value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for full-width operation. -//! -//! This function reads the current value of the specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use -//! TimerValueGet64() for full-width modes of 32/64-bit timers. -//! -//! \return Returns the current value of the timer. -// -//***************************************************************************** -uint32_t -TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // - // Return the appropriate timer value. - // - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAR) : - HWREG(ui32Base + TIMER_O_TBR)); -} - -//***************************************************************************** -// -//! Gets the current 64-bit timer value. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function reads the current value of the specified timer. -//! -//! \return Returns the current value of the timer. -// -//***************************************************************************** -uint64_t -TimerValueGet64(uint32_t ui32Base) -{ - uint32_t ui32High1, ui32High2, ui32Low; - - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Read the 64-bit timer value. A read of the low 32-bits is performed - // between two reads of the upper 32-bits; if the upper 32-bit values match - // then the 64-bit value is consistent. If they do not match, then the - // read is performed again until they do match (it should never execute the - // loop body more than twice). - // - do - { - ui32High1 = HWREG(ui32Base + TIMER_O_TBR); - ui32Low = HWREG(ui32Base + TIMER_O_TAR); - ui32High2 = HWREG(ui32Base + TIMER_O_TBR); - } - while(ui32High1 != ui32High2); - - // - // Return the timer value. - // - return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low); -} - -//***************************************************************************** -// -//! Sets the timer match value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used -//! when the timer is configured for full-width operation. -//! \param ui32Value is the match value. -//! -//! This function configures the match value for a timer. This value is used -//! in capture count mode to determine when to interrupt the processor and in -//! PWM mode to determine the duty cycle of the output signal. On some -//! Tiva devices, match interrupts can also be generated in periodic and -//! one-shot modes. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use -//! TimerMatchSet64() for full-width modes of 32/64-bit timers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the timer A match value if requested. - // - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + TIMER_O_TAMATCHR) = ui32Value; - } - - // - // Set the timer B match value if requested. - // - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + TIMER_O_TBMATCHR) = ui32Value; - } -} - -//***************************************************************************** -// -//! Gets the timer match value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for full-width operation. -//! -//! This function gets the match value for the specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use -//! TimerMatchGet64() for full-width modes of 32/64-bit timers. -//! -//! \return Returns the match value for the timer. -// -//***************************************************************************** -uint32_t -TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // - // Return the appropriate match value. - // - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAMATCHR) : - HWREG(ui32Base + TIMER_O_TBMATCHR)); -} - -//***************************************************************************** -// -//! Sets the timer match value for a 64-bit timer. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui64Value is the match value. -//! -//! This function configures the match value for a timer. This value is used -//! in capture count mode to determine when to interrupt the processor and in -//! PWM mode to determine the duty cycle of the output signal. -//! -//! \return None. -// -//***************************************************************************** -void -TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Set the timer match value. The upper 32-bits must be written before the - // lower 32-bits in order to adhere to the hardware interlocks on the - // 64-bit value. - // - HWREG(ui32Base + TIMER_O_TBMATCHR) = ui64Value >> 32; - HWREG(ui32Base + TIMER_O_TAMATCHR) = ui64Value & 0xffffffff; -} - -//***************************************************************************** -// -//! Gets the timer match value for a 64-bit timer. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function gets the match value for the specified timer. -//! -//! \return Returns the match value for the timer. -// -//***************************************************************************** -uint64_t -TimerMatchGet64(uint32_t ui32Base) -{ - uint32_t ui32High1, ui32High2, ui32Low; - - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Read the 64-bit match value. A read of the low 32-bits is performed - // between two reads of the upper 32-bits; if the upper 32-bit values match - // then the 64-bit value is consistent. If they do not match, then the - // read is performed again until they do match (it should never execute the - // loop body more than twice). - // - do - { - ui32High1 = HWREG(ui32Base + TIMER_O_TBMATCHR); - ui32Low = HWREG(ui32Base + TIMER_O_TAMATCHR); - ui32High2 = HWREG(ui32Base + TIMER_O_TBMATCHR); - } - while(ui32High1 != ui32High2); - - // - // Return the match value. - // - return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the timer interrupt. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param pfnHandler is a pointer to the function to be called when the timer -//! interrupt occurs. -//! -//! This function registers the handler to be called when a timer interrupt -//! occurs. In addition, this function enables the global interrupt in the -//! interrupt controller; specific timer interrupts must be enabled via -//! TimerIntEnable(). It is the interrupt handler's responsibility to clear -//! the interrupt source via TimerIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, - void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Get the interrupt number for this timer module. - // - ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the timer interrupt. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function unregisters the handler to be called when a timer interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Get the interrupt number for this timer module. - // - ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables individual timer interrupt sources. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated timer interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter must be the logical OR of any combination of -//! the following: -//! -//! - \b TIMER_TIMB_DMA - Timer B uDMA complete -//! - \b TIMER_TIMA_DMA - Timer A uDMA complete -//! - \b TIMER_CAPB_EVENT - Capture B event interrupt -//! - \b TIMER_CAPB_MATCH - Capture B match interrupt -//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt -//! - \b TIMER_RTC_MATCH - RTC interrupt mask -//! - \b TIMER_CAPA_EVENT - Capture A event interrupt -//! - \b TIMER_CAPA_MATCH - Capture A match interrupt -//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Enable the specified interrupts. - // - HWREG(ui32Base + TIMER_O_IMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual timer interrupt sources. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated timer interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to TimerIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Disable the specified interrupts. - // - HWREG(ui32Base + TIMER_O_IMR) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base is the base address of the timer module. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the timer module. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! values described in TimerIntEnable(). -// -//***************************************************************************** -uint32_t -TimerIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - return(bMasked ? HWREG(ui32Base + TIMER_O_MIS) : - HWREG(ui32Base + TIMER_O_RIS)); -} - -//***************************************************************************** -// -//! Clears timer interrupt sources. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified timer interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to TimerIntEnable(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Clear the requested interrupt sources. - // - HWREG(ui32Base + TIMER_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Synchronizes the counters in a set of timers. -//! -//! \param ui32Base is the base address of the timer module. This parameter -//! must be the base address of Timer0 (in other words, \b TIMER0_BASE). -//! \param ui32Timers is the set of timers to synchronize. -//! -//! This function synchronizes the counters in a specified set of timers. -//! When a timer is running in half-width mode, each half can be included or -//! excluded in the synchronization event. When a timer is running in -//! full-width mode, only the A timer can be synchronized (specifying the B -//! timer has no effect). -//! -//! The \e ui32Timers parameter is the logical OR of any of the following -//! defines: -//! -//! - \b TIMER_0A_SYNC -//! - \b TIMER_0B_SYNC -//! - \b TIMER_1A_SYNC -//! - \b TIMER_1B_SYNC -//! - \b TIMER_2A_SYNC -//! - \b TIMER_2B_SYNC -//! - \b TIMER_3A_SYNC -//! - \b TIMER_3B_SYNC -//! - \b TIMER_4A_SYNC -//! - \b TIMER_4B_SYNC -//! - \b TIMER_5A_SYNC -//! - \b TIMER_5B_SYNC -//! - \b WTIMER_0A_SYNC -//! - \b WTIMER_0B_SYNC -//! - \b WTIMER_1A_SYNC -//! - \b WTIMER_1B_SYNC -//! - \b WTIMER_2A_SYNC -//! - \b WTIMER_2B_SYNC -//! - \b WTIMER_3A_SYNC -//! - \b WTIMER_3B_SYNC -//! - \b WTIMER_4A_SYNC -//! - \b WTIMER_4B_SYNC -//! - \b WTIMER_5A_SYNC -//! - \b WTIMER_5B_SYNC -//! -//! \note This functionality is not available on all parts. -//! -//! \return None. -// -//***************************************************************************** -void -TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == TIMER0_BASE); - - // - // Synchronize the specified timers. - // - HWREG(ui32Base + TIMER_O_SYNC) = ui32Timers; -} - -//***************************************************************************** -// -//! Enables the events that can cause an ADC trigger event. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32ADCEvent is a bit mask of the events that can cause an ADC -//! trigger event. -//! -//! This function enables the timer events that can cause an ADC trigger event. -//! The ADC trigger events are specified in the \e ui32ADCEvent parameter by -//! passing in the logical OR of any of the following values: -//! -//! - \b TIMER_ADC_MODEMATCH_B - Enables the mode match ADC trigger for timer -//! B. -//! - \b TIMER_ADC_CAPEVENT_B - Enables the capture event ADC trigger for -//! timer B. -//! - \b TIMER_ADC_CAPMATCH_B - Enables the capture match ADC trigger for -//! timer B. -//! - \b TIMER_ADC_TIMEOUT_B - Enables the timeout ADC trigger for timer B. -//! - \b TIMER_ADC_MODEMATCH_A - Enables the mode match ADC trigger for timer -//! A. -//! - \b TIMER_ADC_RTC_A - Enables the RTC ADC trigger for timer A. -//! - \b TIMER_ADC_CAPEVENT_A - Enables the capture event ADC trigger for -//! timer A. -//! - \b TIMER_ADC_CAPMATCH_A - Enables the capture match ADC trigger for -//! timer A. -//! - \b TIMER_ADC_TIMEOUT_A - Enables the timeout ADC trigger for timer A. -//! -//! \note The ability to specify ADC event triggers varies with the Tiva -//! part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerADCEventSet(uint32_t ui32Base, uint32_t ui32ADCEvent) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Set the ADC triggers. - // - HWREG(ui32Base + TIMER_O_ADCEV) = ui32ADCEvent; -} - -//***************************************************************************** -// -//! Returns the events that can cause an ADC trigger event. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function returns the timer events that can cause an ADC trigger event. -//! The ADC trigger events are the logical OR of any of the following values: -//! -//! - \b TIMER_ADC_MODEMATCH_B - The mode match ADC trigger for timer B is -//! enabled. -//! - \b TIMER_ADC_CAPEVENT_B - The capture event ADC trigger for timer B is -//! enabled. -//! - \b TIMER_ADC_CAPMATCH_B - The capture match ADC trigger for timer B is -//! enabled. -//! - \b TIMER_ADC_TIMEOUT_B - The timeout ADC trigger for timer B is enabled. -//! - \b TIMER_ADC_MODEMATCH_A - The mode match ADC trigger for timer A is -//! enabled. -//! - \b TIMER_ADC_RTC_A - The RTC ADC trigger for timer A is enabled. -//! - \b TIMER_ADC_CAPEVENT_A - The capture event ADC trigger for timer A is -//! enabled. -//! - \b TIMER_ADC_CAPMATCH_A - The capture match ADC trigger for timer A is -//! enabled. -//! - \b TIMER_ADC_TIMEOUT_A - The timeout ADC trigger for timer A is enabled. -//! -//! \note The ability to specify ADC event triggers varies with the Tiva -//! part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return The timer events that trigger the ADC. -// -//***************************************************************************** -uint32_t -TimerADCEventGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Return the current ADC triggers. - // - return(HWREG(ui32Base + TIMER_O_ADCEV)); -} - -//***************************************************************************** -// -//! Enables the events that can trigger a uDMA request. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32DMAEvent is a bit mask of the events that can trigger uDMA. -//! -//! This function enables the timer events that can trigger the start of a uDMA -//! sequence. The uDMA trigger events are specified in the \e ui32DMAEvent -//! parameter by passing in the logical OR of the following values: -//! -//! - \b TIMER_DMA_MODEMATCH_B - The mode match uDMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_CAPEVENT_B - The capture event uDMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_CAPMATCH_B - The capture match uDMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_TIMEOUT_B - The timeout uDMA trigger for timer B is enabled. -//! - \b TIMER_DMA_MODEMATCH_A - The mode match uDMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_RTC_A - The RTC uDMA trigger for timer A is enabled. -//! - \b TIMER_DMA_CAPEVENT_A - The capture event uDMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_CAPMATCH_A - The capture match uDMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_TIMEOUT_A - The timeout uDMA trigger for timer A is enabled. -//! -//! \note The ability to specify uDMA event triggers varies with the Tiva -//! part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerDMAEventSet(uint32_t ui32Base, uint32_t ui32DMAEvent) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Set the uDMA triggers. - // - HWREG(ui32Base + TIMER_O_DMAEV) = ui32DMAEvent; -} - -//***************************************************************************** -// -//! Returns the events that can trigger a uDMA request. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function returns the timer events that can trigger the start of a uDMA -//! sequence. The uDMA trigger events are the logical OR of the following -//! values: -//! -//! - \b TIMER_DMA_MODEMATCH_B - Enables the mode match uDMA trigger for timer -//! B. -//! - \b TIMER_DMA_CAPEVENT_B - Enables the capture event uDMA trigger for -//! timer B. -//! - \b TIMER_DMA_CAPMATCH_B - Enables the capture match uDMA trigger for -//! timer B. -//! - \b TIMER_DMA_TIMEOUT_B - Enables the timeout uDMA trigger for timer B. -//! - \b TIMER_DMA_MODEMATCH_A - Enables the mode match uDMA trigger for timer -//! A. -//! - \b TIMER_DMA_RTC_A - Enables the RTC uDMA trigger for timer A. -//! - \b TIMER_DMA_CAPEVENT_A - Enables the capture event uDMA trigger for -//! timer A. -//! - \b TIMER_DMA_CAPMATCH_A - Enables the capture match uDMA trigger for -//! timer A. -//! - \b TIMER_DMA_TIMEOUT_A - Enables the timeout uDMA trigger for timer A. -//! -//! \note The ability to specify uDMA event triggers varies with the Tiva -//! part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return The timer events that trigger the uDMA. -// -//***************************************************************************** -uint32_t -TimerDMAEventGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Return the current uDMA triggers. - // - return(HWREG(ui32Base + TIMER_O_DMAEV)); -} - -//***************************************************************************** -// -//! This function configures the update of timer load and match settings. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param ui32Config is a combination of the updates methods for the timers -//! specified in the \e ui32Timer parameter. -//! -//! This function configures how the timer updates the timer load and match -//! values for the timers. The \e ui32Timer values can be \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH to apply the settings in \e ui32Config to -//! either timer or both timers. If the timer is not split then the \b TIMER_A -//! should be used. The \e ui32Config values affects when the TimerLoadSet() -//! and TimerLoadSet64() values take effect. -//! -//! - \b TIMER_UP_LOAD_IMMEDIATE is the default mode that causes the -//! TimerLoadSet() or TimerLoadSet64() to update the timer counter immediately. -//! - \b TIMER_UP_LOAD_TIMEOUT causes the TimerLoadSet() or TimerLoadSet64() to -//! update the timer when it counts down to zero. -//! -//! Similarly the \e ui32Config value affects when the TimerMatchSet() and -//! TimerMatchSet64() values take effect. -//! -//! - \b TIMER_UP_MATCH_IMMEDIATE is the default mode that causes the -//! TimerMatchSet() or TimerMatchSet64() to update the timer match value -//! immediately. -//! - \b TIMER_UP_MATCH_TIMEOUT causes the TimerMatchSet() or TimerMatchSet64() -//! to update the timer match value when it counts down to zero. -//! -//! \note These settings have no effect if the timer is not in count down mode -//! and are mostly useful when operating in PWM mode to allow for synchronous -//! update of timer match and load values. -//! -//! \return None. -// -//***************************************************************************** -void -TimerUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Config) -{ - uint32_t ui32Value; - - if((ui32Timer & TIMER_A) == TIMER_A) - { - ui32Value = HWREG(ui32Base + TIMER_O_TAMR) & ~(0x00000500); - ui32Value |= ui32Config; - HWREG(ui32Base + TIMER_O_TAMR) = ui32Value; - } - - if((ui32Timer & TIMER_B) == TIMER_B) - { - ui32Value = HWREG(ui32Base + TIMER_O_TBMR) & ~(0x00000500); - ui32Value |= ui32Config; - HWREG(ui32Base + TIMER_O_TBMR) = ui32Value; - } -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.h b/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.h deleted file mode 100644 index 7eb619a7e09d05ca03f13b1271dce7192445f37d..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.h +++ /dev/null @@ -1,301 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_TIMER_H__ -#define __DRIVERLIB_TIMER_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ui32Config parameter. -// -//***************************************************************************** -#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer -#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count - // timer -#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer -#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count - // timer -#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer -#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers -#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer -#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer -#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer -#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer -#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer -#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer -#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output -#define TIMER_CFG_A_ACT_TOINTD 0x00010000 // Timer A compare action disable - // time-out interrupt. -#define TIMER_CFG_A_ACT_NONE 0x00000000 // Timer A compare action none. -#define TIMER_CFG_A_ACT_TOGGLE 0x00020000 // Timer A compare action toggle. -#define TIMER_CFG_A_ACT_CLRTO 0x00040000 // Timer A compare action CCP - // clear on time-out. -#define TIMER_CFG_A_ACT_SETTO 0x00060000 // Timer A compare action CCP set - // on time-out. -#define TIMER_CFG_A_ACT_SETTOGTO 0x00080000 // Timer A compare action set CCP - // toggle on time-out. -#define TIMER_CFG_A_ACT_CLRTOGTO 0x000A0000 // Timer A compare action clear - // CCP toggle on time-out. -#define TIMER_CFG_A_ACT_SETCLRTO 0x000C0000 // Timer A compare action set CCP - // clear on time-out. -#define TIMER_CFG_A_ACT_CLRSETTO 0x000E0000 // Timer A compare action clear - // CCP set on time-out. -#define TIMER_CFG_B_ACT_TOINTD 0x00100000 // Timer B compare action disable - // time-out interrupt. -#define TIMER_CFG_B_ACT_NONE 0x00000000 // Timer A compare action none. -#define TIMER_CFG_B_ACT_TOGGLE 0x00200000 // Timer A compare action toggle. -#define TIMER_CFG_B_ACT_CLRTO 0x00400000 // Timer A compare action CCP - // clear on time-out. -#define TIMER_CFG_B_ACT_SETTO 0x00600000 // Timer A compare action CCP set - // on time-out. -#define TIMER_CFG_B_ACT_SETTOGTO 0x00800000 // Timer A compare action set CCP - // toggle on time-out. -#define TIMER_CFG_B_ACT_CLRTOGTO 0x00A00000 // Timer A compare action clear - // CCP toggle on time-out. -#define TIMER_CFG_B_ACT_SETCLRTO 0x00C00000 // Timer A compare action set CCP - // clear on time-out. -#define TIMER_CFG_B_ACT_CLRSETTO 0x0000E000 // Timer A compare action clear - // CCP set on time-out. - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ui32IntFlags parameter, and returned from -// TimerIntStatus. -// -//***************************************************************************** -#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Complete Interrupt. -#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Complete Interrupt. -#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ui32Event parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ui32Timer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Values that can be passed to TimerSynchronize as the ui32Timers parameter. -// -//***************************************************************************** -#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A -#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B -#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A -#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B -#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A -#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B -#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A -#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B -#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A -#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B -#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A -#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B -#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A -#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B -#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A -#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B -#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A -#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B -#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A -#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B -#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A -#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B -#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A -#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B - -//***************************************************************************** -// -// Values that can be passed to TimerClockSourceSet() or returned from -// TimerClockSourceGet(). -// -//***************************************************************************** -#define TIMER_CLOCK_SYSTEM 0x00000000 -#define TIMER_CLOCK_PIOSC 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to TimerDMAEventSet() or returned from -// TimerDMAEventGet(). -// -//***************************************************************************** -#define TIMER_DMA_MODEMATCH_B 0x00000800 -#define TIMER_DMA_CAPEVENT_B 0x00000400 -#define TIMER_DMA_CAPMATCH_B 0x00000200 -#define TIMER_DMA_TIMEOUT_B 0x00000100 -#define TIMER_DMA_MODEMATCH_A 0x00000010 -#define TIMER_DMA_RTC_A 0x00000008 -#define TIMER_DMA_CAPEVENT_A 0x00000004 -#define TIMER_DMA_CAPMATCH_A 0x00000002 -#define TIMER_DMA_TIMEOUT_A 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to TimerADCEventSet() or returned from -// TimerADCEventGet(). -// -//***************************************************************************** -#define TIMER_ADC_MODEMATCH_B 0x00000800 -#define TIMER_ADC_CAPEVENT_B 0x00000400 -#define TIMER_ADC_CAPMATCH_B 0x00000200 -#define TIMER_ADC_TIMEOUT_B 0x00000100 -#define TIMER_ADC_MODEMATCH_A 0x00000010 -#define TIMER_ADC_RTC_A 0x00000008 -#define TIMER_ADC_CAPEVENT_A 0x00000004 -#define TIMER_ADC_CAPMATCH_A 0x00000002 -#define TIMER_ADC_TIMEOUT_A 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to TimerUpdateMode(). -// -//***************************************************************************** -#define TIMER_UP_LOAD_IMMEDIATE 0x00000000 -#define TIMER_UP_LOAD_TIMEOUT 0x00000100 -#define TIMER_UP_MATCH_IMMEDIATE \ - 0x00000000 -#define TIMER_UP_MATCH_TIMEOUT 0x00000400 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerDisable(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config); -extern void TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer, - bool bInvert); -extern void TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer, - bool bEnable); -extern void TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Event); -extern void TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer, - bool bStall); -extern void TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer, - bool bWait); -extern void TimerRTCEnable(uint32_t ui32Base); -extern void TimerRTCDisable(uint32_t ui32Base); -extern void TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value); -extern uint32_t TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value); -extern uint32_t TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value); -extern uint32_t TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value); -extern uint64_t TimerLoadGet64(uint32_t ui32Base); -extern uint32_t TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer); -extern uint64_t TimerValueGet64(uint32_t ui32Base); -extern void TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value); -extern uint32_t TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value); -extern uint64_t TimerMatchGet64(uint32_t ui32Base); -extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t TimerIntStatus(uint32_t ui32Base, bool bMasked); -extern void TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers); -extern uint32_t TimerClockSourceGet(uint32_t ui32Base); -extern void TimerClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); -extern uint32_t TimerADCEventGet(uint32_t ui32Base); -extern void TimerADCEventSet(uint32_t ui32Base, uint32_t ui32ADCEvent); -extern uint32_t TimerDMAEventGet(uint32_t ui32Base); -extern void TimerDMAEventSet(uint32_t ui32Base, uint32_t ui32DMAEvent); -extern void TimerUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Config); -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_TIMER_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/uart.c b/bsp/tm4c129x-dk/libraries/driverlib/uart.c deleted file mode 100644 index 847f464ceac304850286339867851172b0a0e241..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/uart.c +++ /dev/null @@ -1,1994 +0,0 @@ -//***************************************************************************** -// -// uart.c - Driver for the UART. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup uart_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "inc/hw_uart.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/uart.h" - -//***************************************************************************** -// -// The system clock divider defining the maximum baud rate supported by the -// UART. -// -//***************************************************************************** -#define UART_CLK_DIVIDER 8 - -//***************************************************************************** -// -// A mapping of UART base address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32UARTIntMap[][2] = -{ - { UART0_BASE, INT_UART0_TM4C123 }, - { UART1_BASE, INT_UART1_TM4C123 }, - { UART2_BASE, INT_UART2_TM4C123 }, - { UART3_BASE, INT_UART3_TM4C123 }, - { UART4_BASE, INT_UART4_TM4C123 }, - { UART5_BASE, INT_UART5_TM4C123 }, - { UART6_BASE, INT_UART6_TM4C123 }, - { UART7_BASE, INT_UART7_TM4C123 }, -}; -static const uint_fast8_t g_ui8UARTIntMapRows = - sizeof(g_ppui32UARTIntMap) / sizeof(g_ppui32UARTIntMap[0]); -static const uint32_t g_ppui32UARTIntMapSnowflake[][2] = -{ - { UART0_BASE, INT_UART0_TM4C129 }, - { UART1_BASE, INT_UART1_TM4C129 }, - { UART2_BASE, INT_UART2_TM4C129 }, - { UART3_BASE, INT_UART3_TM4C129 }, - { UART4_BASE, INT_UART4_TM4C129 }, - { UART5_BASE, INT_UART5_TM4C129 }, - { UART6_BASE, INT_UART6_TM4C129 }, - { UART7_BASE, INT_UART7_TM4C129 }, -}; -static const uint_fast8_t g_ui8UARTIntMapRowsSnowflake = - sizeof(g_ppui32UARTIntMapSnowflake) / - sizeof(g_ppui32UARTIntMapSnowflake[0]); - -//***************************************************************************** -// -//! \internal -//! Checks a UART base address. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function determines if a UART port base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_UARTBaseValid(uint32_t ui32Base) -{ - return((ui32Base == UART0_BASE) || (ui32Base == UART1_BASE) || - (ui32Base == UART2_BASE) || (ui32Base == UART3_BASE) || - (ui32Base == UART4_BASE) || (ui32Base == UART5_BASE) || - (ui32Base == UART6_BASE) || (ui32Base == UART7_BASE)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Gets the UART interrupt number. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! Given a UART base address, this function returns the corresponding -//! interrupt number. -//! -//! \return Returns a UART interrupt number, or 0 if \e ui32Base is invalid. -// -//***************************************************************************** -static uint32_t -_UARTIntNumberGet(uint32_t ui32Base) -{ - uint_fast8_t ui8Idx, ui8Rows; - const uint32_t (*ppui32UARTIntMap)[2]; - - // - // Default interrupt map. - // - ppui32UARTIntMap = g_ppui32UARTIntMap; - ui8Rows = g_ui8UARTIntMapRows; - - if(CLASS_IS_TM4C129) - { - ppui32UARTIntMap = g_ppui32UARTIntMapSnowflake; - ui8Rows = g_ui8UARTIntMapRowsSnowflake; - } - - // - // Loop through the table that maps UART base addresses to interrupt - // numbers. - // - for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++) - { - // - // See if this base address matches. - // - if(ppui32UARTIntMap[ui8Idx][0] == ui32Base) - { - // - // Return the corresponding interrupt number. - // - return(ppui32UARTIntMap[ui8Idx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Sets the type of parity. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Parity specifies the type of parity to use. -//! -//! This function configures the type of parity to use for transmitting and -//! expect when receiving. The \e ui32Parity parameter must be one of -//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, -//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two -//! parameters allow direct control of the parity bit; it is always either one -//! or zero based on the mode. -//! -//! \return None. -// -//***************************************************************************** -void -UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) || - (ui32Parity == UART_CONFIG_PAR_EVEN) || - (ui32Parity == UART_CONFIG_PAR_ODD) || - (ui32Parity == UART_CONFIG_PAR_ONE) || - (ui32Parity == UART_CONFIG_PAR_ZERO)); - - // - // Set the parity mode. - // - HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & - ~(UART_LCRH_SPS | UART_LCRH_EPS | - UART_LCRH_PEN)) | ui32Parity); -} - -//***************************************************************************** -// -//! Gets the type of parity currently being used. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function gets the type of parity used for transmitting data and -//! expected when receiving data. -//! -//! \return Returns the current parity settings, specified as one of -//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, -//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. -// -//***************************************************************************** -uint32_t -UARTParityModeGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the current parity setting. - // - return(HWREG(ui32Base + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -//! Sets the FIFO level at which interrupts are generated. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one -//! of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8, -//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. -//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of -//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, -//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. -//! -//! This function configures the FIFO level at which transmit and receive -//! interrupts are generated. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, - uint32_t ui32RxLevel) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT((ui32TxLevel == UART_FIFO_TX1_8) || - (ui32TxLevel == UART_FIFO_TX2_8) || - (ui32TxLevel == UART_FIFO_TX4_8) || - (ui32TxLevel == UART_FIFO_TX6_8) || - (ui32TxLevel == UART_FIFO_TX7_8)); - ASSERT((ui32RxLevel == UART_FIFO_RX1_8) || - (ui32RxLevel == UART_FIFO_RX2_8) || - (ui32RxLevel == UART_FIFO_RX4_8) || - (ui32RxLevel == UART_FIFO_RX6_8) || - (ui32RxLevel == UART_FIFO_RX7_8)); - - // - // Set the FIFO interrupt levels. - // - HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel; -} - -//***************************************************************************** -// -//! Gets the FIFO level at which interrupts are generated. -//! -//! \param ui32Base is the base address of the UART port. -//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, -//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, -//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. -//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, -//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, -//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. -//! -//! This function gets the FIFO level at which transmit and receive interrupts -//! are generated. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, - uint32_t *pui32RxLevel) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Read the FIFO level register. - // - ui32Temp = HWREG(ui32Base + UART_O_IFLS); - - // - // Extract the transmit and receive FIFO levels. - // - *pui32TxLevel = ui32Temp & UART_IFLS_TX_M; - *pui32RxLevel = ui32Temp & UART_IFLS_RX_M; -} - -//***************************************************************************** -// -//! Sets the configuration of a UART. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32UARTClk is the rate of the clock supplied to the UART module. -//! \param ui32Baud is the desired baud rate. -//! \param ui32Config is the data format for the port (number of data bits, -//! number of stop bits, and parity). -//! -//! This function configures the UART for operation in the specified data -//! format. The baud rate is provided in the \e ui32Baud parameter and the -//! data format in the \e ui32Config parameter. -//! -//! The \e ui32Config parameter is the logical OR of three values: the number -//! of data bits, the number of stop bits, and the parity. -//! \b UART_CONFIG_WLEN_8, \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and -//! \b UART_CONFIG_WLEN_5 select from eight to five data bits per byte -//! (respectively). \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select -//! one or two stop bits (respectively). \b UART_CONFIG_PAR_NONE, -//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, -//! and \b UART_CONFIG_PAR_ZERO select the parity mode (no parity bit, even -//! parity bit, odd parity bit, parity bit always one, and parity bit always -//! zero, respectively). -//! -//! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet() for TM4C123x -//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, -//! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the -//! variable call holding the return value of SysCtlClockFreqSet()). -//! -//! The function disables the UART by calling UARTDisable() before changing the -//! the parameters and enables the UART by calling UARTEnable(). -//! -//! For Tiva parts that have the ability to specify the UART baud clock -//! source (via UARTClockSourceSet()), the peripheral clock can be changed to -//! PIOSC. In this case, the peripheral clock should be specified as -//! 16,000,000 (the nominal rate of PIOSC). -//! -//! \return None. -// -//***************************************************************************** -void -UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t ui32Baud, uint32_t ui32Config) -{ - uint32_t ui32Div; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT(ui32Baud != 0); - ASSERT(ui32UARTClk >= (ui32Baud * UART_CLK_DIVIDER)); - - // - // Stop the UART. - // - UARTDisable(ui32Base); - - // - // Is the required baud rate greater than the maximum rate supported - // without the use of high speed mode? - // - if((ui32Baud * 16) > ui32UARTClk) - { - // - // Enable high speed mode. - // - HWREG(ui32Base + UART_O_CTL) |= UART_CTL_HSE; - - // - // Half the supplied baud rate to compensate for enabling high speed - // mode. This allows the following code to be common to both cases. - // - ui32Baud /= 2; - } - else - { - // - // Disable high speed mode. - // - HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_HSE); - } - - // - // Compute the fractional baud rate divider. - // - ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; - - // - // Set the baud rate. - // - HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; - HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; - - // - // Set parity, data length, and number of stop bits. - // - HWREG(ui32Base + UART_O_LCRH) = ui32Config; - - // - // Clear the flags register. - // - HWREG(ui32Base + UART_O_FR) = 0; - - // - // Start the UART. - // - UARTEnable(ui32Base); -} - -//***************************************************************************** -// -//! Gets the current configuration of a UART. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32UARTClk is the rate of the clock supplied to the UART module. -//! \param pui32Baud is a pointer to storage for the baud rate. -//! \param pui32Config is a pointer to storage for the data format. -//! -//! This function determines the baud rate and data format for the UART, given -//! an explicitly provided peripheral clock (hence the ExpClk suffix). The -//! returned baud rate is the actual baud rate; it may not be the exact baud -//! rate requested or an ``official'' baud rate. The data format returned in -//! \e pui32Config is enumerated the same as the \e ui32Config parameter of -//! UARTConfigSetExpClk(). -//! -//! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet() for TM4C123x -//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, -//! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the -//! variable call holding the return value of SysCtlClockFreqSet()). -//! -//! For Tiva parts that have the ability to specify the UART baud clock -//! source (via UARTClockSourceSet()), the peripheral clock can be changed to -//! PIOSC. In this case, the peripheral clock should be specified as -//! 16,000,000 (the nominal rate of PIOSC). -//! -//! \return None. -// -//***************************************************************************** -void -UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t *pui32Baud, uint32_t *pui32Config) -{ - uint32_t ui32Int, ui32Frac; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Compute the baud rate. - // - ui32Int = HWREG(ui32Base + UART_O_IBRD); - ui32Frac = HWREG(ui32Base + UART_O_FBRD); - *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); - - // - // See if high speed mode enabled. - // - if(HWREG(ui32Base + UART_O_CTL) & UART_CTL_HSE) - { - // - // High speed mode is enabled so the actual baud rate is actually - // double what was just calculated. - // - *pui32Baud *= 2; - } - - // - // Get the parity, data length, and number of stop bits. - // - *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | - UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -//! Enables transmitting and receiving. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function enables the UART and its transmit and receive FIFOs. -//! -//! \return None. -// -//***************************************************************************** -void -UARTEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Enable the FIFO. - // - HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; - - // - // Enable RX, TX, and the UART. - // - HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -//! Disables transmitting and receiving. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function disables the UART, waits for the end of transmission of the -//! current character, and flushes the transmit FIFO. -//! -//! \return None. -// -//***************************************************************************** -void -UARTDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Wait for end of TX. - // - while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) - { - } - - // - // Disable the FIFO. - // - HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); - - // - // Disable the UART. - // - HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -//! Enables the transmit and receive FIFOs. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This functions enables the transmit and receive FIFOs in the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Enable the FIFO. - // - HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; -} - -//***************************************************************************** -// -//! Disables the transmit and receive FIFOs. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function disables the transmit and receive FIFOs in the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFODisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Disable the FIFO. - // - HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); -} - -//***************************************************************************** -// -//! Enables SIR (IrDA) mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! \param bLowPower indicates if SIR Low Power Mode is to be used. -//! -//! This function enables SIR (IrDA) mode on the UART. If the \e bLowPower -//! flag is set, then SIR low power mode will be selected as well. This -//! function only has an effect if the UART has not been enabled by a call to -//! UARTEnable(). The call UARTEnableSIR() must be made before a call to -//! UARTConfigSetExpClk() because the UARTConfigSetExpClk() function calls the -//! UARTEnable() function. Another option is to call UARTDisable() followed by -//! UARTEnableSIR() and then enable the UART by calling UARTEnable(). -//! -//! \note The availability of SIR (IrDA) operation varies with the Tiva -//! part in use. Please consult the datasheet for the part you are using to -//! determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTEnableSIR(uint32_t ui32Base, bool bLowPower) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Enable SIR and SIRLP (if appropriate). - // - if(bLowPower) - { - HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP); - } - else - { - HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_SIREN); - } -} - -//***************************************************************************** -// -//! Disables SIR (IrDA) mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function disables SIR(IrDA) mode on the UART. This function only has -//! an effect if the UART has not been enabled by a call to UARTEnable(). The -//! call UARTEnableSIR() must be made before a call to UARTConfigSetExpClk() -//! because the UARTConfigSetExpClk() function calls the UARTEnable() function. -//! Another option is to call UARTDisable() followed by UARTEnableSIR() and -//! then enable the UART by calling UARTEnable(). -//! -//! \note The availability of SIR (IrDA) operation varies with the Tiva -//! part in use. Please consult the datasheet for the part you are using to -//! determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTDisableSIR(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Disable SIR and SIRLP (if appropriate). - // - HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP); -} - -//***************************************************************************** -// -//! Enables ISO7816 smart card mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function enables the SMART control bit for the ISO7816 smart card mode -//! on the UART. This call also sets 8-bit word length and even parity as -//! required by ISO7816. -//! -//! \note The availability of ISO7816 smart card mode varies with the Tiva -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTSmartCardEnable(uint32_t ui32Base) -{ - uint32_t ui32Val; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Set 8-bit word length, even parity, 2 stop bits (note that although the - // STP2 bit is ignored when in smartcard mode, this code lets the caller - // read back the actual setting in use). - // - ui32Val = HWREG(ui32Base + UART_O_LCRH); - ui32Val &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN | - UART_LCRH_WLEN_M); - ui32Val |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS | - UART_LCRH_STP2; - HWREG(ui32Base + UART_O_LCRH) = ui32Val; - - // - // Enable SMART mode. - // - HWREG(ui32Base + UART_O_CTL) |= UART_CTL_SMART; -} - -//***************************************************************************** -// -//! Disables ISO7816 smart card mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function clears the SMART (ISO7816 smart card) bit in the UART -//! control register. -//! -//! \note The availability of ISO7816 smart card mode varies with the Tiva -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTSmartCardDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Disable the SMART bit. - // - HWREG(ui32Base + UART_O_CTL) &= ~UART_CTL_SMART; -} - -//***************************************************************************** -// -//! Sets the states of the DTR and/or RTS modem control signals. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Control is a bit-mapped flag indicating which modem control bits -//! should be set. -//! -//! This function configures the states of the DTR or RTS modem handshake -//! outputs from the UART. -//! -//! The \e ui32Control parameter is the logical OR of any of the following: -//! -//! - \b UART_OUTPUT_DTR - The modem control DTR signal -//! - \b UART_OUTPUT_RTS - The modem control RTS signal -//! -//! \note The availability of hardware modem handshake signals varies with the -//! Tiva part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT(ui32Base == UART1_BASE); - ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); - - // - // Set the appropriate modem control output bits. - // - ui32Temp = HWREG(ui32Base + UART_O_CTL); - ui32Temp |= (ui32Control & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); - HWREG(ui32Base + UART_O_CTL) = ui32Temp; -} - -//***************************************************************************** -// -//! Clears the states of the DTR and/or RTS modem control signals. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Control is a bit-mapped flag indicating which modem control bits -//! should be set. -//! -//! This function clears the states of the DTR or RTS modem handshake outputs -//! from the UART. -//! -//! The \e ui32Control parameter is the logical OR of any of the following: -//! -//! - \b UART_OUTPUT_DTR - The modem control DTR signal -//! - \b UART_OUTPUT_RTS - The modem control RTS signal -//! -//! \note The availability of hardware modem handshake signals varies with the -//! Tiva part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT(ui32Base == UART1_BASE); - ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); - - // - // Set the appropriate modem control output bits. - // - ui32Temp = HWREG(ui32Base + UART_O_CTL); - ui32Temp &= ~(ui32Control & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); - HWREG(ui32Base + UART_O_CTL) = ui32Temp; -} - -//***************************************************************************** -// -//! Gets the states of the DTR and RTS modem control signals. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the current states of each of the two UART modem -//! control signals, DTR and RTS. -//! -//! \note The availability of hardware modem handshake signals varies with the -//! Tiva part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return Returns the states of the handshake output signals. This value is -//! a logical OR combination of values \b UART_OUTPUT_RTS and -//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the -//! associated signal is asserted. -// -//***************************************************************************** -uint32_t -UARTModemControlGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == UART1_BASE); - - return(HWREG(ui32Base + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); -} - -//***************************************************************************** -// -//! Gets the states of the RI, DCD, DSR and CTS modem status signals. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the current states of each of the four UART modem -//! status signals, RI, DCD, DSR and CTS. -//! -//! \note The availability of hardware modem handshake signals varies with the -//! Tiva part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return Returns the states of the handshake output signals. This value -//! is a logical OR combination of values \b UART_INPUT_RI, -//! \b UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the -//! presence of each flag indicates that the associated signal is asserted. -// -//***************************************************************************** -uint32_t -UARTModemStatusGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == UART1_BASE); - - return(HWREG(ui32Base + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD | - UART_INPUT_CTS | UART_INPUT_DSR)); -} - -//***************************************************************************** -// -//! Sets the UART hardware flow control mode to be used. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Mode indicates the flow control modes to be used. This -//! parameter is a logical OR combination of values \b UART_FLOWCONTROL_TX and -//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) -//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control. -//! -//! This function configures the required hardware flow control modes. If -//! \e ui32Mode contains flag \b UART_FLOWCONTROL_TX, data is only transmitted -//! if the incoming CTS signal is asserted. If \e ui32Mode contains flag -//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is -//! asserted only when there is space available in the receive FIFO. If no -//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be -//! passed. -//! -//! \note The availability of hardware flow control varies with the Tiva -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT((ui32Mode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0); - - // - // Set the flow control mode as requested. - // - HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & - ~(UART_FLOWCONTROL_TX | - UART_FLOWCONTROL_RX)) | ui32Mode); -} - -//***************************************************************************** -// -//! Returns the UART hardware flow control mode currently in use. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the current hardware flow control mode. -//! -//! \note The availability of hardware flow control varies with the Tiva -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return Returns the current flow control mode in use. This value is a -//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit -//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS) -//! flow control is in use. If hardware flow control is disabled, -//! \b UART_FLOWCONTROL_NONE is returned. -// -//***************************************************************************** -uint32_t -UARTFlowControlGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - return(HWREG(ui32Base + UART_O_CTL) & (UART_FLOWCONTROL_TX | - UART_FLOWCONTROL_RX)); -} - -//***************************************************************************** -// -//! Sets the operating mode for the UART transmit interrupt. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Mode is the operating mode for the transmit interrupt. It may -//! be \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is -//! idle or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit -//! FIFO level. -//! -//! This function allows the mode of the UART transmit interrupt to be set. By -//! default, the transmit interrupt is asserted when the FIFO level falls past -//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this -//! function is called with \e ui32Mode set to \b UART_TXINT_MODE_EOT, the -//! transmit interrupt is asserted once the transmitter is completely idle - -//! the transmit FIFO is empty and all bits, including any stop bits, have -//! cleared the transmitter. -//! -//! \note The availability of end-of-transmission mode varies with the -//! Tiva part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT((ui32Mode == UART_TXINT_MODE_EOT) || - (ui32Mode == UART_TXINT_MODE_FIFO)); - - // - // Set or clear the EOT bit of the UART control register as appropriate. - // - HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & - ~(UART_TXINT_MODE_EOT | - UART_TXINT_MODE_FIFO)) | ui32Mode); -} - -//***************************************************************************** -// -//! Returns the current operating mode for the UART transmit interrupt. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the current operating mode for the UART transmit -//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit -//! interrupt is currently configured to be asserted once the transmitter is -//! completely idle - the transmit FIFO is empty and all bits, including any -//! stop bits, have cleared the transmitter. The return value is -//! \b UART_TXINT_MODE_FIFO if the interrupt is configured to be asserted based -//! on the level of the transmit FIFO. -//! -//! \note The availability of end-of-transmission mode varies with the -//! Tiva part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT. -// -//***************************************************************************** -uint32_t -UARTTxIntModeGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the current transmit interrupt mode. - // - return(HWREG(ui32Base + UART_O_CTL) & (UART_TXINT_MODE_EOT | - UART_TXINT_MODE_FIFO)); -} - -//***************************************************************************** -// -//! Determines if there are any characters in the receive FIFO. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is data -//! available in the receive FIFO. -//! -//! \return Returns \b true if there is data in the receive FIFO or \b false -//! if there is no data in the receive FIFO. -// -//***************************************************************************** -bool -UARTCharsAvail(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the availability of characters. - // - return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true); -} - -//***************************************************************************** -// -//! Determines if there is any space in the transmit FIFO. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is space -//! available in the transmit FIFO. -//! -//! \return Returns \b true if there is space available in the transmit FIFO -//! or \b false if there is no space available in the transmit FIFO. -// -//***************************************************************************** -bool -UARTSpaceAvail(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the availability of space. - // - return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true); -} - -//***************************************************************************** -// -//! Receives a character from the specified port. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. -//! -//! \return Returns the character read from the specified port, cast as a -//! \e int32_t. A \b -1 is returned if there are no characters present in the -//! receive FIFO. The UARTCharsAvail() function should be called before -//! attempting to call this function. -// -//***************************************************************************** -int32_t -UARTCharGetNonBlocking(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // See if there are any characters in the receive FIFO. - // - if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) - { - // - // Read and return the next character. - // - return(HWREG(ui32Base + UART_O_DR)); - } - else - { - // - // There are no characters, so return a failure. - // - return(-1); - } -} - -//***************************************************************************** -// -//! Waits for a character from the specified port. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. If there are no characters available, this function waits until a -//! character is received before returning. -//! -//! \return Returns the character read from the specified port, cast as a -//! \e int32_t. -// -//***************************************************************************** -int32_t -UARTCharGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Wait until a char is available. - // - while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) - { - } - - // - // Now get the char. - // - return(HWREG(ui32Base + UART_O_DR)); -} - -//***************************************************************************** -// -//! Sends a character to the specified port. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! This function writes the character \e ucData to the transmit FIFO for the -//! specified port. This function does not block, so if there is no space -//! available, then a \b false is returned and the application must retry the -//! function later. -//! -//! \return Returns \b true if the character was successfully placed in the -//! transmit FIFO or \b false if there was no space available in the transmit -//! FIFO. -// -//***************************************************************************** -bool -UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // See if there is space in the transmit FIFO. - // - if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) - { - // - // Write this character to the transmit FIFO. - // - HWREG(ui32Base + UART_O_DR) = ucData; - - // - // Success. - // - return(true); - } - else - { - // - // There is no space in the transmit FIFO, so return a failure. - // - return(false); - } -} - -//***************************************************************************** -// -//! Waits to send a character from the specified port. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! This function sends the character \e ucData to the transmit FIFO for the -//! specified port. If there is no space available in the transmit FIFO, this -//! function waits until there is space available before returning. -//! -//! \return None. -// -//***************************************************************************** -void -UARTCharPut(uint32_t ui32Base, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Wait until space is available. - // - while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) - { - } - - // - // Send the char. - // - HWREG(ui32Base + UART_O_DR) = ucData; -} - -//***************************************************************************** -// -//! Causes a BREAK to be sent. -//! -//! \param ui32Base is the base address of the UART port. -//! \param bBreakState controls the output level. -//! -//! Calling this function with \e bBreakState set to \b true asserts a break -//! condition on the UART. Calling this function with \e bBreakState set to -//! \b false removes the break condition. For proper transmission of a break -//! command, the break must be asserted for at least two complete frames. -//! -//! \return None. -// -//***************************************************************************** -void -UARTBreakCtl(uint32_t ui32Base, bool bBreakState) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Set the break condition as requested. - // - HWREG(ui32Base + UART_O_LCRH) = - (bBreakState ? - (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : - (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); -} - -//***************************************************************************** -// -//! Determines whether the UART transmitter is busy or not. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function allows the caller to determine whether all transmitted bytes -//! have cleared the transmitter hardware. If \b false is returned, the -//! transmit FIFO is empty and all bits of the last transmitted character, -//! including all stop bits, have left the hardware shift register. -//! -//! \return Returns \b true if the UART is transmitting or \b false if all -//! transmissions are complete. -// -//***************************************************************************** -bool -UARTBusy(uint32_t ui32Base) -{ - // - // Check the argument. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Determine if the UART is busy. - // - return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? true : false); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a UART interrupt. -//! -//! \param ui32Base is the base address of the UART port. -//! \param pfnHandler is a pointer to the function to be called when the -//! UART interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; specific -//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the UART port. - // - ui32Int = _UARTIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the UART interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a UART interrupt. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a UART interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the UART port. - // - ui32Int = _UARTIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables individual UART interrupt sources. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b UART_INT_9BIT - 9-bit Address Match interrupt -//! - \b UART_INT_OE - Overrun Error interrupt -//! - \b UART_INT_BE - Break Error interrupt -//! - \b UART_INT_PE - Parity Error interrupt -//! - \b UART_INT_FE - Framing Error interrupt -//! - \b UART_INT_RT - Receive Timeout interrupt -//! - \b UART_INT_TX - Transmit interrupt -//! - \b UART_INT_RX - Receive interrupt -//! - \b UART_INT_DSR - DSR interrupt -//! - \b UART_INT_DCD - DCD interrupt -//! - \b UART_INT_CTS - CTS interrupt -//! - \b UART_INT_RI - RI interrupt -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Enable the specified interrupts. - // - HWREG(ui32Base + UART_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual UART interrupt sources. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to UARTIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Disable the specified interrupts. - // - HWREG(ui32Base + UART_O_IM) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base is the base address of the UART port. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the specified UART. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in UARTIntEnable(). -// -//***************************************************************************** -uint32_t -UARTIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + UART_O_MIS)); - } - else - { - return(HWREG(ui32Base + UART_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears UART interrupt sources. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified UART interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to UARTIntEnable(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Clear the requested interrupt sources. - // - HWREG(ui32Base + UART_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Enable UART uDMA operation. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32DMAFlags is a bit mask of the uDMA features to enable. -//! -//! The specified UART uDMA features are enabled. The UART can be -//! configured to use uDMA for transmit or receive and to disable -//! receive if an error occurs. The \e ui32DMAFlags parameter is the -//! logical OR of any of the following values: -//! -//! - \b UART_DMA_RX - enable uDMA for receive -//! - \b UART_DMA_TX - enable uDMA for transmit -//! - \b UART_DMA_ERR_RXSTOP - disable uDMA receive on UART error -//! -//! \note The uDMA controller must also be set up before DMA can be used -//! with the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Set the requested bits in the UART uDMA control register. - // - HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags; -} - -//***************************************************************************** -// -//! Disable UART uDMA operation. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32DMAFlags is a bit mask of the uDMA features to disable. -//! -//! This function is used to disable UART uDMA features that were enabled -//! by UARTDMAEnable(). The specified UART uDMA features are disabled. The -//! \e ui32DMAFlags parameter is the logical OR of any of the following values: -//! -//! - \b UART_DMA_RX - disable uDMA for receive -//! - \b UART_DMA_TX - disable uDMA for transmit -//! - \b UART_DMA_ERR_RXSTOP - do not disable uDMA receive on UART error -//! -//! \return None. -// -//***************************************************************************** -void -UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Clear the requested bits in the UART uDMA control register. - // - HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags; -} - -//***************************************************************************** -// -//! Gets current receiver errors. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the current state of each of the 4 receiver error -//! sources. The returned errors are equivalent to the four error bits -//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() -//! with the exception that the overrun error is set immediately when the -//! overrun occurs rather than when a character is next read. -//! -//! \return Returns a logical OR combination of the receiver error flags, -//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK -//! and \b UART_RXERROR_OVERRUN. -// -//***************************************************************************** -uint32_t -UARTRxErrorGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the current value of the receive status register. - // - return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F); -} - -//***************************************************************************** -// -//! Clears all reported receiver errors. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function is used to clear all receiver error conditions reported via -//! UARTRxErrorGet(). If using the overrun, framing error, parity error or -//! break interrupts, this function must be called after clearing the interrupt -//! to ensure that later errors of the same type trigger another interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -UARTRxErrorClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Any write to the Error Clear Register clears all bits which are - // currently set. - // - HWREG(ui32Base + UART_O_ECR) = 0; -} - -//***************************************************************************** -// -//! Sets the baud clock source for the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Source is the baud clock source for the UART. -//! -//! This function allows the baud clock source for the UART to be selected. -//! The possible clock source are the system clock (\b UART_CLOCK_SYSTEM) or -//! the precision internal oscillator (\b UART_CLOCK_PIOSC). -//! -//! Changing the baud clock source changes the baud rate generated by the -//! UART. Therefore, the baud rate should be reconfigured after any change to -//! the baud clock source. -//! -//! \note The ability to specify the UART baud clock source varies with the -//! Tiva part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT((ui32Source == UART_CLOCK_SYSTEM) || - (ui32Source == UART_CLOCK_PIOSC)); - - // - // Set the UART clock source. - // - HWREG(ui32Base + UART_O_CC) = ui32Source; -} - -//***************************************************************************** -// -//! Gets the baud clock source for the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the baud clock source for the specified UART. The -//! possible baud clock source are the system clock (\b UART_CLOCK_SYSTEM) or -//! the precision internal oscillator (\b UART_CLOCK_PIOSC). -//! -//! \note The ability to specify the UART baud clock source varies with the -//! Tiva part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -UARTClockSourceGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the UART clock source. - // - return(HWREG(ui32Base + UART_O_CC)); -} - -//***************************************************************************** -// -//! Enables 9-bit mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function enables the 9-bit operational mode of the UART. -//! -//! \note The availability of 9-bit mode varies with the Tiva part in use. -//! Please consult the datasheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UART9BitEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Enable 9-bit mode. - // - HWREG(ui32Base + UART_O_9BITADDR) |= UART_9BITADDR_9BITEN; -} - -//***************************************************************************** -// -//! Disables 9-bit mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function disables the 9-bit operational mode of the UART. -//! -//! \note The availability of 9-bit mode varies with the Tiva part in use. -//! Please consult the datasheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UART9BitDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Disable 9-bit mode. - // - HWREG(ui32Base + UART_O_9BITADDR) &= ~UART_9BITADDR_9BITEN; -} - -//***************************************************************************** -// -//! Sets the device address(es) for 9-bit mode. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui8Addr is the device address. -//! \param ui8Mask is the device address mask. -//! -//! This function configures the device address or range of device addresses -//! that respond to requests on the 9-bit UART port. The received address is -//! masked with the mask and then compared against the given address, allowing -//! either a single address (if \b ui8Mask is 0xff) or a set of addresses to be -//! matched. -//! -//! \note The availability of 9-bit mode varies with the Tiva part in use. -//! Please consult the datasheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr, - uint8_t ui8Mask) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Set the address and mask. - // - HWREG(ui32Base + UART_O_9BITADDR) = ui8Addr << UART_9BITADDR_ADDR_S; - HWREG(ui32Base + UART_O_9BITAMASK) = ui8Mask << UART_9BITAMASK_MASK_S; -} - -//***************************************************************************** -// -//! Sends an address character from the specified port when operating in 9-bit -//! mode. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui8Addr is the address to be transmitted. -//! -//! This function waits until all data has been sent from the specified port -//! and then sends the given address as an address byte. It then waits until -//! the address byte has been transmitted before returning. -//! -//! The normal data functions (UARTCharPut(), UARTCharPutNonBlocking(), -//! UARTCharGet(), and UARTCharGetNonBlocking()) are used to send and receive -//! data characters in 9-bit mode. -//! -//! \note The availability of 9-bit mode varies with the Tiva part in use. -//! Please consult the datasheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr) -{ - uint32_t ui32LCRH; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Wait until the FIFO is empty and the UART is not busy. - // - while((HWREG(ui32Base + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) != - UART_FR_TXFE) - { - } - - // - // Force the address/data bit to 1 to indicate this is an address byte. - // - ui32LCRH = HWREG(ui32Base + UART_O_LCRH); - HWREG(ui32Base + UART_O_LCRH) = ((ui32LCRH & ~UART_LCRH_EPS) | - UART_LCRH_SPS | UART_LCRH_PEN); - - // - // Send the address. - // - HWREG(ui32Base + UART_O_DR) = ui8Addr; - - // - // Wait until the address has been sent. - // - while((HWREG(ui32Base + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) != - UART_FR_TXFE) - { - } - - // - // Restore the address/data setting. - // - HWREG(ui32Base + UART_O_LCRH) = ui32LCRH; -} - -//***************************************************************************** -// -//! Enables internal loopback mode for a UART port -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function configures a UART port in internal loopback mode to help with -//! diagnostics and debug. In this mode, the transmit and receive terminals of -//! the same UART port are internally connected. Hence, the data transmitted -//! on the UnTx output is received on the UxRx input, without having to go -//! through I/O's. UARTCharPut(), UARTCharGet() functions can be used along -//! with this function. -//! -//! \return None. -// -//***************************************************************************** -void UARTLoopbackEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Write the Loopback Enable bit to register. - // - HWREG(ui32Base + UART_O_CTL) |= UART_CTL_LBE; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/uart.h b/bsp/tm4c129x-dk/libraries/driverlib/uart.h deleted file mode 100644 index 3a9397550da02a495963a35bb6159f7cca944549..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/uart.h +++ /dev/null @@ -1,256 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_UART_H__ -#define __DRIVERLIB_UART_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ui32IntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_DMATX 0x20000 // DMA TX interrupt -#define UART_INT_DMARX 0x10000 // DMA RX interrupt -#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask -#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask -#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask -#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask -#define UART_INT_RI 0x001 // RI Modem Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter -// and returned by UARTConfigGetExpClk in the pui32Config parameter. -// Additionally, the UART_CONFIG_PAR_* subset can be passed to -// UARTParityModeSet as the ui32Parity parameter, and are returned by -// UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero - -//***************************************************************************** -// -// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter -// and returned by UARTFIFOLevelGet in the pui32TxLevel. -// -//***************************************************************************** -#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full -#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full -#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full -#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full -#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full - -//***************************************************************************** -// -// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter -// and returned by UARTFIFOLevelGet in the pui32RxLevel. -// -//***************************************************************************** -#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full -#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full -#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full -#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full -#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full - -//***************************************************************************** -// -// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). -// -//***************************************************************************** -#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error -#define UART_DMA_TX 0x00000002 // Enable DMA for transmit -#define UART_DMA_RX 0x00000001 // Enable DMA for receive - -//***************************************************************************** -// -// Values returned from UARTRxErrorGet(). -// -//***************************************************************************** -#define UART_RXERROR_OVERRUN 0x00000008 -#define UART_RXERROR_BREAK 0x00000004 -#define UART_RXERROR_PARITY 0x00000002 -#define UART_RXERROR_FRAMING 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to UARTHandshakeOutputsSet() or returned from -// UARTHandshakeOutputGet(). -// -//***************************************************************************** -#define UART_OUTPUT_RTS 0x00000800 -#define UART_OUTPUT_DTR 0x00000400 - -//***************************************************************************** -// -// Values that can be returned from UARTHandshakeInputsGet(). -// -//***************************************************************************** -#define UART_INPUT_RI 0x00000100 -#define UART_INPUT_DCD 0x00000004 -#define UART_INPUT_DSR 0x00000002 -#define UART_INPUT_CTS 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to UARTFlowControl() or returned from -// UARTFlowControlGet(). -// -//***************************************************************************** -#define UART_FLOWCONTROL_TX 0x00008000 -#define UART_FLOWCONTROL_RX 0x00004000 -#define UART_FLOWCONTROL_NONE 0x00000000 - -//***************************************************************************** -// -// Values that can be passed to UARTTxIntModeSet() or returned from -// UARTTxIntModeGet(). -// -//***************************************************************************** -#define UART_TXINT_MODE_FIFO 0x00000000 -#define UART_TXINT_MODE_EOT 0x00000010 - -//***************************************************************************** -// -// Values that can be passed to UARTClockSourceSet() or returned from -// UARTClockSourceGet(). -// -//***************************************************************************** -#define UART_CLOCK_SYSTEM 0x00000000 -#define UART_CLOCK_PIOSC 0x00000005 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity); -extern uint32_t UARTParityModeGet(uint32_t ui32Base); -extern void UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, - uint32_t ui32RxLevel); -extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, - uint32_t *pui32RxLevel); -extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t ui32Baud, uint32_t ui32Config); -extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t *pui32Baud, uint32_t *pui32Config); -extern void UARTEnable(uint32_t ui32Base); -extern void UARTDisable(uint32_t ui32Base); -extern void UARTFIFOEnable(uint32_t ui32Base); -extern void UARTFIFODisable(uint32_t ui32Base); -extern void UARTEnableSIR(uint32_t ui32Base, bool bLowPower); -extern void UARTDisableSIR(uint32_t ui32Base); -extern bool UARTCharsAvail(uint32_t ui32Base); -extern bool UARTSpaceAvail(uint32_t ui32Base); -extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); -extern int32_t UARTCharGet(uint32_t ui32Base); -extern bool UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData); -extern void UARTCharPut(uint32_t ui32Base, unsigned char ucData); -extern void UARTBreakCtl(uint32_t ui32Base, bool bBreakState); -extern bool UARTBusy(uint32_t ui32Base); -extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void UARTIntUnregister(uint32_t ui32Base); -extern void UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t UARTIntStatus(uint32_t ui32Base, bool bMasked); -extern void UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); -extern void UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); -extern uint32_t UARTRxErrorGet(uint32_t ui32Base); -extern void UARTRxErrorClear(uint32_t ui32Base); -extern void UARTSmartCardEnable(uint32_t ui32Base); -extern void UARTSmartCardDisable(uint32_t ui32Base); -extern void UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control); -extern void UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control); -extern uint32_t UARTModemControlGet(uint32_t ui32Base); -extern uint32_t UARTModemStatusGet(uint32_t ui32Base); -extern void UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode); -extern uint32_t UARTFlowControlGet(uint32_t ui32Base); -extern void UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode); -extern uint32_t UARTTxIntModeGet(uint32_t ui32Base); -extern void UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); -extern uint32_t UARTClockSourceGet(uint32_t ui32Base); -extern void UART9BitEnable(uint32_t ui32Base); -extern void UART9BitDisable(uint32_t ui32Base); -extern void UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr, - uint8_t ui8Mask); -extern void UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr); -extern void UARTLoopbackEnable(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_UART_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/udma.c b/bsp/tm4c129x-dk/libraries/driverlib/udma.c deleted file mode 100644 index bb2941af92eaa46facbf0c4e28aa68f2adedfeb0..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/udma.c +++ /dev/null @@ -1,1382 +0,0 @@ -//***************************************************************************** -// -// udma.c - Driver for the micro-DMA controller. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup udma_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "inc/hw_udma.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/udma.h" - -//***************************************************************************** -// -//! Enables the uDMA controller for use. -//! -//! This function enables the uDMA controller. The uDMA controller must be -//! enabled before it can be configured and used. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAEnable(void) -{ - // - // Set the master enable bit in the config register. - // - HWREG(UDMA_CFG) = UDMA_CFG_MASTEN; -} - -//***************************************************************************** -// -//! Disables the uDMA controller for use. -//! -//! This function disables the uDMA controller. Once disabled, the uDMA -//! controller cannot operate until re-enabled with uDMAEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -uDMADisable(void) -{ - // - // Clear the master enable bit in the config register. - // - HWREG(UDMA_CFG) = 0; -} - -//***************************************************************************** -// -//! Gets the uDMA error status. -//! -//! This function returns the uDMA error status. It should be called from -//! within the uDMA error interrupt handler to determine if a uDMA error -//! occurred. -//! -//! \return Returns non-zero if a uDMA error is pending. -// -//***************************************************************************** -uint32_t -uDMAErrorStatusGet(void) -{ - // - // Return the uDMA error status. - // - return(HWREG(UDMA_ERRCLR)); -} - -//***************************************************************************** -// -//! Clears the uDMA error interrupt. -//! -//! This function clears a pending uDMA error interrupt. This function should -//! be called from within the uDMA error interrupt handler to clear the -//! interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAErrorStatusClear(void) -{ - // - // Clear the uDMA error interrupt. - // - HWREG(UDMA_ERRCLR) = 1; -} - -//***************************************************************************** -// -//! Enables a uDMA channel for operation. -//! -//! \param ui32ChannelNum is the channel number to enable. -//! -//! This function enables a specific uDMA channel for use. This function must -//! be used to enable a channel before it can be used to perform a uDMA -//! transfer. -//! -//! When a uDMA transfer is completed, the channel is automatically disabled by -//! the uDMA controller. Therefore, this function should be called prior to -//! starting up any new transfer. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelEnable(uint32_t ui32ChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the enable set register. - // - HWREG(UDMA_ENASET) = 1 << (ui32ChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Disables a uDMA channel for operation. -//! -//! \param ui32ChannelNum is the channel number to disable. -//! -//! This function disables a specific uDMA channel. Once disabled, a channel -//! cannot respond to uDMA transfer requests until re-enabled via -//! uDMAChannelEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelDisable(uint32_t ui32ChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the enable clear register. - // - HWREG(UDMA_ENACLR) = 1 << (ui32ChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Checks if a uDMA channel is enabled for operation. -//! -//! \param ui32ChannelNum is the channel number to check. -//! -//! This function checks to see if a specific uDMA channel is enabled. This -//! function can be used to check the status of a transfer, as the channel is -//! automatically disabled at the end of a transfer. -//! -//! \return Returns \b true if the channel is enabled, \b false if disabled. -// -//***************************************************************************** -bool -uDMAChannelIsEnabled(uint32_t ui32ChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - - // - // AND the specified channel bit with the enable register and return the - // result. - // - return((HWREG(UDMA_ENASET) & (1 << (ui32ChannelNum & 0x1f))) ? true : - false); -} - -//***************************************************************************** -// -//! Sets the base address for the channel control table. -//! -//! \param psControlTable is a pointer to the 1024-byte-aligned base address -//! of the uDMA channel control table. -//! -//! This function configures the base address of the channel control table. -//! This table resides in system memory and holds control information for each -//! uDMA channel. The table must be aligned on a 1024-byte boundary. The base -//! address must be configured before any of the channel functions can be used. -//! -//! The size of the channel control table depends on the number of uDMA -//! channels and the transfer modes that are used. Refer to the introductory -//! text and the microcontroller datasheet for more information about the -//! channel control table. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAControlBaseSet(void *psControlTable) -{ - // - // Check the arguments. - // - ASSERT(((uint32_t)psControlTable & ~0x3FF) == - (uint32_t)psControlTable); - ASSERT((uint32_t)psControlTable >= 0x20000000); - - // - // Program the base address into the register. - // - HWREG(UDMA_CTLBASE) = (uint32_t)psControlTable; -} - -//***************************************************************************** -// -//! Gets the base address for the channel control table. -//! -//! This function gets the base address of the channel control table. This -//! table resides in system memory and holds control information for each uDMA -//! channel. -//! -//! \return Returns a pointer to the base address of the channel control table. -// -//***************************************************************************** -void * -uDMAControlBaseGet(void) -{ - // - // Read the current value of the control base register and return it to - // the caller. - // - return((void *)HWREG(UDMA_CTLBASE)); -} - -//***************************************************************************** -// -//! Gets the base address for the channel control table alternate structures. -//! -//! This function gets the base address of the second half of the channel -//! control table that holds the alternate control structures for each channel. -//! -//! \return Returns a pointer to the base address of the second half of the -//! channel control table. -// -//***************************************************************************** -void * -uDMAControlAlternateBaseGet(void) -{ - // - // Read the current value of the control base register and return it to - // the caller. - // - return((void *)HWREG(UDMA_ALTBASE)); -} - -//***************************************************************************** -// -//! Requests a uDMA channel to start a transfer. -//! -//! \param ui32ChannelNum is the channel number on which to request a uDMA -//! transfer. -//! -//! This function allows software to request a uDMA channel to begin a -//! transfer. This function could be used for performing a memory-to-memory -//! transfer, or if for some reason a transfer needs to be initiated by -//! software instead of the peripheral associated with that channel. -//! -//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then -//! the completion is signaled on the uDMA dedicated interrupt. If a -//! peripheral channel is used, then the completion is signaled on the -//! peripheral's interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelRequest(uint32_t ui32ChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the software uDMA request register. - // - HWREG(UDMA_SWREQ) = 1 << (ui32ChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Enables attributes of a uDMA channel. -//! -//! \param ui32ChannelNum is the channel to configure. -//! \param ui32Attr is a combination of attributes for the channel. -//! -//! This function is used to enable attributes of a uDMA channel. -//! -//! The \e ui32Attr parameter is the logical OR of any of the following: -//! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel (it is very unlikely that this flag should be used). -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, uint32_t ui32Attr) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelNum parameter, extract just the channel number - // from this parameter. - // - ui32ChannelNum &= 0x1f; - - // - // Set the useburst bit for this channel if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_USEBURST) - { - HWREG(UDMA_USEBURSTSET) = 1 << ui32ChannelNum; - } - - // - // Set the alternate control select bit for this channel, - // if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_ALTSELECT) - { - HWREG(UDMA_ALTSET) = 1 << ui32ChannelNum; - } - - // - // Set the high priority bit for this channel, if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(UDMA_PRIOSET) = 1 << ui32ChannelNum; - } - - // - // Set the request mask bit for this channel, if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_REQMASK) - { - HWREG(UDMA_REQMASKSET) = 1 << ui32ChannelNum; - } -} - -//***************************************************************************** -// -//! Disables attributes of a uDMA channel. -//! -//! \param ui32ChannelNum is the channel to configure. -//! \param ui32Attr is a combination of attributes for the channel. -//! -//! This function is used to disable attributes of a uDMA channel. -//! -//! The \e ui32Attr parameter is the logical OR of any of the following: -//! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel. -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, uint32_t ui32Attr) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelNum parameter, extract just the channel number - // from this parameter. - // - ui32ChannelNum &= 0x1f; - - // - // Clear the useburst bit for this channel if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_USEBURST) - { - HWREG(UDMA_USEBURSTCLR) = 1 << ui32ChannelNum; - } - - // - // Clear the alternate control select bit for this channel, if set in - // ui32Config. - // - if(ui32Attr & UDMA_ATTR_ALTSELECT) - { - HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum; - } - - // - // Clear the high priority bit for this channel, if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(UDMA_PRIOCLR) = 1 << ui32ChannelNum; - } - - // - // Clear the request mask bit for this channel, if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_REQMASK) - { - HWREG(UDMA_REQMASKCLR) = 1 << ui32ChannelNum; - } -} - -//***************************************************************************** -// -//! Gets the enabled attributes of a uDMA channel. -//! -//! \param ui32ChannelNum is the channel to configure. -//! -//! This function returns a combination of flags representing the attributes of -//! the uDMA channel. -//! -//! \return Returns the logical OR of the attributes of the uDMA channel, which -//! can be any of the following: -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel. -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -// -//***************************************************************************** -uint32_t -uDMAChannelAttributeGet(uint32_t ui32ChannelNum) -{ - uint32_t ui32Attr = 0; - - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelNum parameter, extract just the channel number - // from this parameter. - // - ui32ChannelNum &= 0x1f; - - // - // Check to see if useburst bit is set for this channel. - // - if(HWREG(UDMA_USEBURSTSET) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_USEBURST; - } - - // - // Check to see if the alternate control bit is set for this channel. - // - if(HWREG(UDMA_ALTSET) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_ALTSELECT; - } - - // - // Check to see if the high priority bit is set for this channel. - // - if(HWREG(UDMA_PRIOSET) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; - } - - // - // Check to see if the request mask bit is set for this channel. - // - if(HWREG(UDMA_REQMASKSET) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_REQMASK; - } - - // - // Return the configuration flags. - // - return(ui32Attr); -} - -//***************************************************************************** -// -//! Sets the control parameters for a uDMA channel control structure. -//! -//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number -//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! \param ui32Control is logical OR of several control values to set the -//! control parameters for the channel. -//! -//! This function is used to set control parameters for a uDMA transfer. These -//! parameters are typically not changed often. -//! -//! The \e ui32ChannelStructIndex parameter should be the logical OR of the -//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to -//! choose whether the primary or alternate data structure is used. -//! -//! The \e ui32Control parameter is the logical OR of five values: the data -//! size, the source address increment, the destination address increment, the -//! arbitration size, and the use burst flag. The choices available for each -//! of these values is described below. -//! -//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or -//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits. -//! -//! Choose the source address increment from one of \b UDMA_SRC_INC_8, -//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select -//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or -//! to select non-incrementing. -//! -//! Choose the destination address increment from one of \b UDMA_DST_INC_8, -//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select -//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or -//! to select non-incrementing. -//! -//! The arbitration size determines how many items are transferred before -//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size -//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8, -//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024 -//! items, in powers of 2. -//! -//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only -//! respond to burst requests at the tail end of a scatter-gather transfer. -//! -//! \note The address increment cannot be smaller than the data size. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Control) -{ - tDMAControlTable *psCtl; - - // - // Check the arguments. - // - ASSERT((ui32ChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ui32ChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - psCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE); - - // - // Get the current control word value and mask off the fields to be - // changed, then OR in the new settings. - // - psCtl[ui32ChannelStructIndex].ui32Control = - ((psCtl[ui32ChannelStructIndex].ui32Control & - ~(UDMA_CHCTL_DSTINC_M | - UDMA_CHCTL_DSTSIZE_M | - UDMA_CHCTL_SRCINC_M | - UDMA_CHCTL_SRCSIZE_M | - UDMA_CHCTL_ARBSIZE_M | - UDMA_CHCTL_NXTUSEBURST)) | - ui32Control); -} - -//***************************************************************************** -// -//! Sets the transfer parameters for a uDMA channel control structure. -//! -//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! \param ui32Mode is the type of uDMA transfer. -//! \param pvSrcAddr is the source address for the transfer. -//! \param pvDstAddr is the destination address for the transfer. -//! \param ui32TransferSize is the number of data items to transfer. -//! -//! This function is used to configure the parameters for a uDMA transfer. -//! These parameters are not typically changed often. The function -//! uDMAChannelControlSet() MUST be called at least once for this channel prior -//! to calling this function. -//! -//! The \e ui32ChannelStructIndex parameter should be the logical OR of the -//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to -//! choose whether the primary or alternate data structure is used. -//! -//! The \e ui32Mode parameter should be one of the following values: -//! -//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode -//! to this value at the end of a transfer. -//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. -//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once -//! started even if the request is removed. -//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the -//! primary and alternate control structures for the channel. This mode -//! allows use of ping-pong buffering for uDMA transfers. -//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather -//! transfer. -//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather -//! transfer. -//! -//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first -//! location of the data to be transferred. These addresses should be aligned -//! according to the item size. The compiler takes care of this alignment if -//! the pointers are pointing to storage of the appropriate data type. -//! -//! The \e ui32TransferSize parameter is the number of data items, not the -//! number of bytes. -//! -//! The two scatter-gather modes, memory and peripheral, are actually different -//! depending on whether the primary or alternate control structure is -//! selected. This function looks for the \b UDMA_PRI_SELECT and -//! \b UDMA_ALT_SELECT flag along with the channel number and sets the -//! scatter-gather mode as appropriate for the primary or alternate control -//! structure. -//! -//! The channel must also be enabled using uDMAChannelEnable() after calling -//! this function. The transfer does not begin until the channel has been -//! configured and enabled. Note that the channel is automatically disabled -//! after the transfer is completed, meaning that uDMAChannelEnable() must be -//! called again after setting up the next transfer. -//! -//! \note Great care must be taken to not modify a channel control structure -//! that is in use or else the results are unpredictable, including the -//! possibility of undesired data transfers to or from memory or peripherals. -//! For BASIC and AUTO modes, it is safe to make changes when the channel is -//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For -//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the -//! primary or alternate control structure only when the other is being used. -//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a -//! channel control structure is inactive and safe to modify. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, - void *pvSrcAddr, void *pvDstAddr, - uint32_t ui32TransferSize) -{ - tDMAControlTable *psControlTable; - uint32_t ui32Control; - uint32_t ui32Inc; - uint32_t ui32BufferBytes; - - // - // Check the arguments. - // - ASSERT((ui32ChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_CTLBASE) != 0); - ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); - ASSERT((uint32_t)pvSrcAddr >= 0x20000000); - ASSERT((uint32_t)pvDstAddr >= 0x20000000); - ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= 1024)); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ui32ChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); - - // - // Get the current control word value and mask off the mode and size - // fields. - // - ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control & - ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); - - // - // Adjust the mode if the alt control structure is selected. - // - if(ui32ChannelStructIndex & UDMA_ALT_SELECT) - { - if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - ui32Mode |= UDMA_MODE_ALT_SELECT; - } - } - - // - // Set the transfer size and mode in the control word (but don't write the - // control word yet as it could kick off a transfer). - // - ui32Control |= ui32Mode | ((ui32TransferSize - 1) << 4); - - // - // Get the address increment value for the source, from the control word. - // - ui32Inc = (ui32Control & UDMA_CHCTL_SRCINC_M); - - // - // Compute the ending source address of the transfer. If the source - // increment is set to none, then the ending address is the same as the - // beginning. - // - if(ui32Inc != UDMA_SRC_INC_NONE) - { - ui32Inc = ui32Inc >> 26; - ui32BufferBytes = ui32TransferSize << ui32Inc; - pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - 1); - } - - // - // Load the source ending address into the control block. - // - psControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; - - // - // Get the address increment value for the destination, from the control - // word. - // - ui32Inc = ui32Control & UDMA_CHCTL_DSTINC_M; - - // - // Compute the ending destination address of the transfer. If the - // destination increment is set to none, then the ending address is the - // same as the beginning. - // - if(ui32Inc != UDMA_DST_INC_NONE) - { - // - // There is a special case if this is setting up a scatter-gather - // transfer. The destination pointer must point to the end of - // the alternate structure for this channel instead of calculating - // the end of the buffer in the normal way. - // - if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - pvDstAddr = - (void *)&psControlTable[ui32ChannelStructIndex | - UDMA_ALT_SELECT].ui32Spare; - } - // - // Not a scatter-gather transfer, calculate end pointer normally. - // - else - { - ui32Inc = ui32Inc >> 30; - ui32BufferBytes = ui32TransferSize << ui32Inc; - pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); - } - } - - // - // Load the destination ending address into the control block. - // - psControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; - - // - // Write the new control word value. - // - psControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; -} - -//***************************************************************************** -// -//! Configures a uDMA channel for scatter-gather mode. -//! -//! \param ui32ChannelNum is the uDMA channel number. -//! \param ui32TaskCount is the number of scatter-gather tasks to execute. -//! \param pvTaskList is a pointer to the beginning of the scatter-gather -//! task list. -//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral -//! scatter-gather transfer (else it is memory scatter-gather transfer) -//! -//! This function is used to configure a channel for scatter-gather mode. -//! The caller must have already set up a task list and must pass a pointer to -//! the start of the task list as the \e pvTaskList parameter. The -//! \e ui32TaskCount parameter is the count of tasks in the task list, not the -//! size of the task list. The flag \e bIsPeriphSG should be used to indicate -//! if scatter-gather should be configured for peripheral or memory -//! operation. -//! -//! \sa uDMATaskStructEntry -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, uint32_t ui32TaskCount, - void *pvTaskList, uint32_t ui32IsPeriphSG) -{ - tDMAControlTable *psControlTable; - tDMAControlTable *psTaskTable; - - // - // Check the parameters - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - ASSERT(HWREG(UDMA_CTLBASE) != 0); - ASSERT(pvTaskList != 0); - ASSERT(ui32TaskCount <= 1024); - ASSERT(ui32TaskCount != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelNum parameter, extract just the channel number - // from this parameter. - // - ui32ChannelNum &= 0x1f; - - // - // Get the base address of the control table. - // - psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); - - // - // Get a handy pointer to the task list - // - psTaskTable = (tDMAControlTable *)pvTaskList; - - // - // Compute the ending address for the source pointer. This address is the - // last element of the last task in the task table - // - psControlTable[ui32ChannelNum].pvSrcEndAddr = - &psTaskTable[ui32TaskCount - 1].ui32Spare; - - // - // Compute the ending address for the destination pointer. This address - // is the end of the alternate structure for this channel. - // - psControlTable[ui32ChannelNum].pvDstEndAddr = - &psControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; - - // - // Compute the control word. Most configurable items are fixed for - // scatter-gather. Item and increment sizes are all 32-bit and arb - // size must be 4. The count is the number of items in the task list - // times 4 (4 words per task). - // - psControlTable[ui32ChannelNum].ui32Control = - (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 | - UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 | - UDMA_CHCTL_ARBSIZE_4 | - (((ui32TaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) | - (ui32IsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG : - UDMA_CHCTL_XFERMODE_MEM_SG)); - - // - // Scatter-gather operations can leave the alt bit set. So if doing - // back to back scatter-gather transfers, the second attempt may not - // work correctly because the alt bit is set. Therefore, clear the - // alt bit here to ensure that it is always cleared before a new SG - // transfer is started. - // - HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -//! Gets the current transfer size for a uDMA channel control structure. -//! -//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! -//! This function is used to get the uDMA transfer size for a channel. The -//! transfer size is the number of items to transfer, where the size of an item -//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, -//! then the number of remaining items is returned. If the transfer is -//! complete, then 0 is returned. -//! -//! \return Returns the number of items remaining to transfer. -// -//***************************************************************************** -uint32_t -uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex) -{ - tDMAControlTable *psControlTable; - uint32_t ui32Control; - - // - // Check the arguments. - // - ASSERT((ui32ChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ui32ChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); - - // - // Get the current control word value and mask off all but the size field - // and the mode field. - // - ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control & - (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); - - // - // If the size field and mode field are 0 then the transfer is finished - // and there are no more items to transfer - // - if(ui32Control == 0) - { - return(0); - } - - // - // Otherwise, if either the size field or more field is non-zero, then - // not all the items have been transferred. - // - else - { - // - // Shift the size field and add one, then return to user. - // - return((ui32Control >> 4) + 1); - } -} - -//***************************************************************************** -// -//! Gets the transfer mode for a uDMA channel control structure. -//! -//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! -//! This function is used to get the transfer mode for the uDMA channel and -//! to query the status of a transfer on a channel. When the transfer is -//! complete the mode is \b UDMA_MODE_STOP. -//! -//! \return Returns the transfer mode of the specified channel and control -//! structure, which is one of the following values: \b UDMA_MODE_STOP, -//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG, -//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. -// -//***************************************************************************** -uint32_t -uDMAChannelModeGet(uint32_t ui32ChannelStructIndex) -{ - tDMAControlTable *psControlTable; - uint32_t ui32Control; - - // - // Check the arguments. - // - ASSERT((ui32ChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ui32ChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); - - // - // Get the current control word value and mask off all but the mode field. - // - ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control & - UDMA_CHCTL_XFERMODE_M); - - // - // Check if scatter/gather mode, and if so, mask off the alt bit. - // - if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == - UDMA_MODE_MEM_SCATTER_GATHER) || - ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) - { - ui32Control &= ~UDMA_MODE_ALT_SELECT; - } - - // - // Return the mode to the caller. - // - return(ui32Control); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the uDMA controller. -//! -//! \param ui32IntChannel identifies which uDMA interrupt is to be registered. -//! \param pfnHandler is a pointer to the function to be called when the -//! interrupt is activated. -//! -//! This function registers and enables the handler to be called when the uDMA -//! controller generates an interrupt. The \e ui32IntChannel parameter should -//! be one of the following: -//! -//! - \b INT_UDMA to register an interrupt handler to process interrupts -//! from the uDMA software channel (UDMA_CHANNEL_SW) -//! - \b INT_UDMAERR to register an interrupt handler to process uDMA error -//! interrupts -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note The interrupt handler for the uDMA is for transfer completion when -//! the channel UDMA_CHANNEL_SW is used and for error interrupts. The -//! interrupts for each peripheral channel are handled through the individual -//! peripheral interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(pfnHandler); - - // - // Register the interrupt handler. - // - IntRegister(ui32IntChannel, pfnHandler); - - // - // Enable the memory management fault. - // - IntEnable(ui32IntChannel); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the uDMA controller. -//! -//! \param ui32IntChannel identifies which uDMA interrupt to unregister. -//! -//! This function disables and unregisters the handler to be called for the -//! specified uDMA interrupt. The \e ui32IntChannel parameter should be one of -//! \b INT_UDMA or \b INT_UDMAERR as documented for the function -//! uDMAIntRegister(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntUnregister(uint32_t ui32IntChannel) -{ - // - // Disable the interrupt. - // - IntDisable(ui32IntChannel); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32IntChannel); -} - -//***************************************************************************** -// -//! Gets the uDMA controller channel interrupt status. -//! -//! This function is used to get the interrupt status of the uDMA controller. -//! The returned value is a 32-bit bit mask that indicates which channels are -//! requesting an interrupt. This function can be used from within an -//! interrupt handler to determine or confirm which uDMA channel has requested -//! an interrupt. -//! -//! \note This function is only available on devices that have the DMA Channel -//! Interrupt Status Register (DMACHIS). Please consult the data sheet for -//! your part. -//! -//! \return Returns a 32-bit mask which indicates requesting uDMA channels. -//! There is a bit for each channel and a 1 indicates that the channel -//! is requesting an interrupt. Multiple bits can be set. -// -//***************************************************************************** -uint32_t -uDMAIntStatus(void) -{ - // - // Return the value of the uDMA interrupt status register - // - return(HWREG(UDMA_CHIS)); -} - -//***************************************************************************** -// -//! Clears uDMA interrupt status. -//! -//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel. -//! -//! This function clears bits in the uDMA interrupt status register according -//! to which bits are set in \e ui32ChanMask. There is one bit for each -//! channel. If a a bit is set in \e ui32ChanMask, then that corresponding -//! channel's interrupt status is cleared (if it was set). -//! -//! \note This function is only available on devices that have the DMA Channel -//! Interrupt Status Register (DMACHIS). Please consult the data sheet for -//! your part. Devices without the DMACHIS register have uDMA done status in -//! the interrupt registers in the peripheral memory maps. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntClear(uint32_t ui32ChanMask) -{ - // - // Clear the requested bits in the uDMA interrupt status register - // - HWREG(UDMA_CHIS) = ui32ChanMask; -} - -//***************************************************************************** -// -//! Assigns a peripheral mapping for a uDMA channel. -//! -//! \param ui32Mapping is a macro specifying the peripheral assignment for -//! a channel. -//! -//! This function assigns a peripheral mapping to a uDMA channel. It is -//! used to select which peripheral is used for a uDMA channel. The parameter -//! \e ui32Mapping should be one of the macros named \b UDMA_CHn_tttt from the -//! header file \e udma.h. For example, to assign uDMA channel 0 to the -//! UART2 RX channel, the parameter should be the macro \b UDMA_CH0_UART2RX. -//! -//! Please consult the Tiva data sheet for a table showing all the -//! possible peripheral assignments for the uDMA channels for a particular -//! device. -//! -//! \note This function is only available on devices that have the DMA Channel -//! Map Select registers (DMACHMAP0-3). Please consult the data sheet for -//! your part. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAssign(uint32_t ui32Mapping) -{ - uint32_t ui32MapReg; - uint_fast8_t ui8MapShift; - uint_fast8_t ui8ChannelNum; - - // - // Check the parameters - // - ASSERT((ui32Mapping & 0xffffff00) < 0x00090000); - - // - // Extract the channel number and map encoding value from the parameter. - // - ui8ChannelNum = ui32Mapping & 0xff; - ui32Mapping = ui32Mapping >> 16; - - // - // Find the uDMA channel mapping register and shift value to use for this - // channel - // - ui32MapReg = UDMA_CHMAP0 + (uint32_t)((ui8ChannelNum / 8) * 4); - ui8MapShift = (ui8ChannelNum % 8) * 4; - - // - // Set the channel map encoding for this channel - // - HWREG(ui32MapReg) = (HWREG(ui32MapReg) & ~(0xf << ui8MapShift)) | - ui32Mapping << ui8MapShift; -} - -//***************************************************************************** -// -// The following functions are deprecated. Use uDMAChannelAssign() instead -// to accomplish the same end. -// -//***************************************************************************** -#ifndef DEPRECATED -//***************************************************************************** -// -//! Selects the secondary peripheral for a set of uDMA channels. -//! -//! \param ui32SecPeriphs is the logical OR of the uDMA channels for which to -//! use the secondary peripheral, instead of the default peripheral. -//! -//! This function is used to select the secondary peripheral assignment for a -//! set of uDMA channels. By selecting the secondary peripheral assignment for -//! a channel, the default peripheral assignment is no longer available for -//! that channel. -//! -//! The parameter \e ui32SecPeriphs can be the logical OR of any of the -//! following macros. If one of the macros below is in the list passed to this -//! function, then the secondary peripheral (marked as \b _SEC_) is selected. -//! -//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX -//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX -//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A -//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B -//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A -//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B -//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A -//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B -//! - \b UDMA_DEF_UART0RX_SEC_UART1RX -//! - \b UDMA_DEF_UART0TX_SEC_UART1TX -//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX -//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX -//! - \b UDMA_DEF_RESERVED_SEC_UART2RX -//! - \b UDMA_DEF_RESERVED_SEC_UART2TX -//! - \b UDMA_DEF_ADC00_SEC_TMR2A -//! - \b UDMA_DEF_ADC01_SEC_TMR2B -//! - \b UDMA_DEF_ADC02_SEC_RESERVED -//! - \b UDMA_DEF_ADC03_SEC_RESERVED -//! - \b UDMA_DEF_TMR0A_SEC_TMR1A -//! - \b UDMA_DEF_TMR0B_SEC_TMR1B -//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX -//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX -//! - \b UDMA_DEF_UART1RX_SEC_RESERVED -//! - \b UDMA_DEF_UART1TX_SEC_RESERVED -//! - \b UDMA_DEF_SSI1RX_SEC_ADC10 -//! - \b UDMA_DEF_SSI1TX_SEC_ADC11 -//! - \b UDMA_DEF_RESERVED_SEC_ADC12 -//! - \b UDMA_DEF_RESERVED_SEC_ADC13 -//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED -//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs) -{ - // - // Select the secondary peripheral for the specified channels. - // - HWREG(UDMA_CHASGN) |= ui32SecPeriphs; -} - -//***************************************************************************** -// -//! Selects the default peripheral for a set of uDMA channels. -//! -//! \param ui32DefPeriphs is the logical OR of the uDMA channels for which to -//! use the default peripheral, instead of the secondary peripheral. -//! -//! This function is used to select the default peripheral assignment for a set -//! of uDMA channels. -//! -//! The parameter \e ui32DefPeriphs can be the logical OR of any of the -//! following macros. If one of the macros below is in the list passed to this -//! function, then the default peripheral (marked as \b _DEF_) is selected. -//! -//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX -//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX -//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A -//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B -//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A -//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B -//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A -//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B -//! - \b UDMA_DEF_UART0RX_SEC_UART1RX -//! - \b UDMA_DEF_UART0TX_SEC_UART1TX -//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX -//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX -//! - \b UDMA_DEF_RESERVED_SEC_UART2RX -//! - \b UDMA_DEF_RESERVED_SEC_UART2TX -//! - \b UDMA_DEF_ADC00_SEC_TMR2A -//! - \b UDMA_DEF_ADC01_SEC_TMR2B -//! - \b UDMA_DEF_ADC02_SEC_RESERVED -//! - \b UDMA_DEF_ADC03_SEC_RESERVED -//! - \b UDMA_DEF_TMR0A_SEC_TMR1A -//! - \b UDMA_DEF_TMR0B_SEC_TMR1B -//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX -//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX -//! - \b UDMA_DEF_UART1RX_SEC_RESERVED -//! - \b UDMA_DEF_UART1TX_SEC_RESERVED -//! - \b UDMA_DEF_SSI1RX_SEC_ADC10 -//! - \b UDMA_DEF_SSI1TX_SEC_ADC11 -//! - \b UDMA_DEF_RESERVED_SEC_ADC12 -//! - \b UDMA_DEF_RESERVED_SEC_ADC13 -//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED -//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelSelectDefault(uint32_t ui32DefPeriphs) -{ - // - // Select the default peripheral for the specified channels. - // - HWREG(UDMA_CHASGN) &= ~ui32DefPeriphs; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/udma.h b/bsp/tm4c129x-dk/libraries/driverlib/udma.h deleted file mode 100644 index a8d3684489587cee20a50470ad34506f9fb7e1df..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/udma.h +++ /dev/null @@ -1,890 +0,0 @@ -//***************************************************************************** -// -// udma.h - Prototypes and macros for the uDMA controller. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_UDMA_H__ -#define __DRIVERLIB_UDMA_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup udma_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// A structure that defines an entry in the channel control table. These -// fields are used by the uDMA controller and normally it is not necessary for -// software to directly read or write fields in the table. -// -//***************************************************************************** -typedef struct -{ - // - // The ending source address of the data transfer. - // - volatile void *pvSrcEndAddr; - - // - // The ending destination address of the data transfer. - // - volatile void *pvDstEndAddr; - - // - // The channel control mode. - // - volatile uint32_t ui32Control; - - // - // An unused location. - // - volatile uint32_t ui32Spare; -} -tDMAControlTable; - -//***************************************************************************** -// -//! A helper macro for building scatter-gather task table entries. -//! -//! \param ui32TransferCount is the count of items to transfer for this task. -//! \param ui32ItemSize is the bit size of the items to transfer for this task. -//! \param ui32SrcIncrement is the bit size increment for source data. -//! \param pvSrcAddr is the starting address of the data to transfer. -//! \param ui32DstIncrement is the bit size increment for destination data. -//! \param pvDstAddr is the starting address of the destination data. -//! \param ui32ArbSize is the arbitration size to use for the transfer task. -//! \param ui32Mode is the transfer mode for this task. -//! -//! This macro is intended to be used to help populate a table of uDMA tasks -//! for a scatter-gather transfer. This macro will calculate the values for -//! the fields of a task structure entry based on the input parameters. -//! -//! There are specific requirements for the values of each parameter. No -//! checking is done so it is up to the caller to ensure that correct values -//! are used for the parameters. -//! -//! The \e ui32TransferCount parameter is the number of items that will be -//! transferred by this task. It must be in the range 1-1024. -//! -//! The \e ui32ItemSize parameter is the bit size of the transfer data. It -//! must be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. -//! -//! The \e ui32SrcIncrement parameter is the increment size for the source -//! data. It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, -//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. -//! -//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source -//! data. -//! -//! The \e ui32DstIncrement parameter is the increment size for the destination -//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, -//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. -//! -//! The \e pvDstAddr parameter is a void pointer to the beginning of the -//! location where the data will be transferred. -//! -//! The \e ui32ArbSize parameter is the arbitration size for the transfer, and -//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on -//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in -//! powers of 2, from 1 to 1024. -//! -//! The \e ui32Mode parameter is the mode to use for this transfer task. It -//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, -//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note -//! that normally all tasks will be one of the scatter-gather modes while the -//! last task is a task list will be AUTO or BASIC. -//! -//! This macro is intended to be used to initialize individual entries of -//! a structure of tDMAControlTable type, like this: -//! -//! \verbatim -//! tDMAControlTable MyTaskList[] = -//! { -//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, -//! UDMA_SRC_INC_8, MySourceBuf, -//! UDMA_DST_INC_8, MyDestBuf, -//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), -//! uDMATaskStructEntry(Task2Count, ...), -//! } -//! \endverbatim -//! -//! \return Nothing; this is not a function. -// -//***************************************************************************** -#define uDMATaskStructEntry(ui32TransferCount, \ - ui32ItemSize, \ - ui32SrcIncrement, \ - pvSrcAddr, \ - ui32DstIncrement, \ - pvDstAddr, \ - ui32ArbSize, \ - ui32Mode) \ - { \ - (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ - ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ - ((ui32SrcIncrement) >> 26)) - 1]))), \ - (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) :\ - ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ - ((ui32DstIncrement) >> 30)) - 1]))), \ - (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ - (ui32ArbSize) | \ - (((ui32TransferCount) - 1) << 4) | \ - ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ - ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ - (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ - } - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Flags that can be passed to uDMAChannelAttributeEnable(), -// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). -// -//***************************************************************************** -#define UDMA_ATTR_USEBURST 0x00000001 -#define UDMA_ATTR_ALTSELECT 0x00000002 -#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 -#define UDMA_ATTR_REQMASK 0x00000008 -#define UDMA_ATTR_ALL 0x0000000F - -//***************************************************************************** -// -// DMA control modes that can be passed to uDMAModeSet() and returned -// uDMAModeGet(). -// -//***************************************************************************** -#define UDMA_MODE_STOP 0x00000000 -#define UDMA_MODE_BASIC 0x00000001 -#define UDMA_MODE_AUTO 0x00000002 -#define UDMA_MODE_PINGPONG 0x00000003 -#define UDMA_MODE_MEM_SCATTER_GATHER \ - 0x00000004 -#define UDMA_MODE_PER_SCATTER_GATHER \ - 0x00000006 -#define UDMA_MODE_ALT_SELECT 0x00000001 - -//***************************************************************************** -// -// Channel configuration values that can be passed to uDMAControlSet(). -// -//***************************************************************************** -#define UDMA_DST_INC_8 0x00000000 -#define UDMA_DST_INC_16 0x40000000 -#define UDMA_DST_INC_32 0x80000000 -#define UDMA_DST_INC_NONE 0xc0000000 -#define UDMA_SRC_INC_8 0x00000000 -#define UDMA_SRC_INC_16 0x04000000 -#define UDMA_SRC_INC_32 0x08000000 -#define UDMA_SRC_INC_NONE 0x0c000000 -#define UDMA_SIZE_8 0x00000000 -#define UDMA_SIZE_16 0x11000000 -#define UDMA_SIZE_32 0x22000000 -#define UDMA_DST_PROT_PRIV 0x00200000 -#define UDMA_SRC_PROT_PRIV 0x00040000 -#define UDMA_ARB_1 0x00000000 -#define UDMA_ARB_2 0x00004000 -#define UDMA_ARB_4 0x00008000 -#define UDMA_ARB_8 0x0000c000 -#define UDMA_ARB_16 0x00010000 -#define UDMA_ARB_32 0x00014000 -#define UDMA_ARB_64 0x00018000 -#define UDMA_ARB_128 0x0001c000 -#define UDMA_ARB_256 0x00020000 -#define UDMA_ARB_512 0x00024000 -#define UDMA_ARB_1024 0x00028000 -#define UDMA_NEXT_USEBURST 0x00000008 - -//***************************************************************************** -// -// Channel numbers to be passed to API functions that require a channel number -// ID. -// -//***************************************************************************** -#define UDMA_CHANNEL_USBEP1RX 0 -#define UDMA_CHANNEL_USBEP1TX 1 -#define UDMA_CHANNEL_USBEP2RX 2 -#define UDMA_CHANNEL_USBEP2TX 3 -#define UDMA_CHANNEL_USBEP3RX 4 -#define UDMA_CHANNEL_USBEP3TX 5 -#define UDMA_CHANNEL_ETH0RX 6 -#define UDMA_CHANNEL_ETH0TX 7 -#define UDMA_CHANNEL_UART0RX 8 -#define UDMA_CHANNEL_UART0TX 9 -#define UDMA_CHANNEL_SSI0RX 10 -#define UDMA_CHANNEL_SSI0TX 11 -#define UDMA_CHANNEL_ADC0 14 -#define UDMA_CHANNEL_ADC1 15 -#define UDMA_CHANNEL_ADC2 16 -#define UDMA_CHANNEL_ADC3 17 -#define UDMA_CHANNEL_TMR0A 18 -#define UDMA_CHANNEL_TMR0B 19 -#define UDMA_CHANNEL_TMR1A 20 -#define UDMA_CHANNEL_TMR1B 21 -#define UDMA_CHANNEL_UART1RX 22 -#define UDMA_CHANNEL_UART1TX 23 -#define UDMA_CHANNEL_SSI1RX 24 -#define UDMA_CHANNEL_SSI1TX 25 -#define UDMA_CHANNEL_I2S0RX 28 -#define UDMA_CHANNEL_I2S0TX 29 -#define UDMA_CHANNEL_SW 30 - -//***************************************************************************** -// -// Flags to be OR'd with the channel ID to indicate if the primary or alternate -// control structure should be used. -// -//***************************************************************************** -#define UDMA_PRI_SELECT 0x00000000 -#define UDMA_ALT_SELECT 0x00000020 - -//***************************************************************************** -// -// Channel numbers to be passed to API functions that require a channel number -// ID. These are for secondary peripheral assignments. -// -//***************************************************************************** -#define UDMA_SEC_CHANNEL_UART2RX_0 \ - 0 -#define UDMA_SEC_CHANNEL_UART2TX_1 \ - 1 -#define UDMA_SEC_CHANNEL_TMR3A 2 -#define UDMA_SEC_CHANNEL_TMR3B 3 -#define UDMA_SEC_CHANNEL_TMR2A_4 \ - 4 -#define UDMA_SEC_CHANNEL_TMR2B_5 \ - 5 -#define UDMA_SEC_CHANNEL_TMR2A_6 \ - 6 -#define UDMA_SEC_CHANNEL_TMR2B_7 \ - 7 -#define UDMA_SEC_CHANNEL_UART1RX \ - 8 -#define UDMA_SEC_CHANNEL_UART1TX \ - 9 -#define UDMA_SEC_CHANNEL_SSI1RX 10 -#define UDMA_SEC_CHANNEL_SSI1TX 11 -#define UDMA_SEC_CHANNEL_UART2RX_12 \ - 12 -#define UDMA_SEC_CHANNEL_UART2TX_13 \ - 13 -#define UDMA_SEC_CHANNEL_TMR2A_14 \ - 14 -#define UDMA_SEC_CHANNEL_TMR2B_15 \ - 15 -#define UDMA_SEC_CHANNEL_TMR1A 18 -#define UDMA_SEC_CHANNEL_TMR1B 19 -#define UDMA_SEC_CHANNEL_EPI0RX 20 -#define UDMA_SEC_CHANNEL_EPI0TX 21 -#define UDMA_SEC_CHANNEL_ADC10 24 -#define UDMA_SEC_CHANNEL_ADC11 25 -#define UDMA_SEC_CHANNEL_ADC12 26 -#define UDMA_SEC_CHANNEL_ADC13 27 -#define UDMA_SEC_CHANNEL_SW 30 - -//***************************************************************************** -// -// Values that can be passed to uDMAChannelAssign() to select peripheral -// mapping for each channel. The channels named RESERVED may be assigned -// to a peripheral in future parts. -// -//***************************************************************************** -// -// Channel 0 -// -#define UDMA_CH0_USB0EP1RX 0x00000000 -#define UDMA_CH0_UART2RX 0x00010000 -#define UDMA_CH0_RESERVED2 0x00020000 -#define UDMA_CH0_TIMER4A 0x00030000 -#define UDMA_CH0_RESERVED4 0x00040000 -#define UDMA_CH0_RESERVED5 0x00050000 -#define UDMA_CH0_I2C0RX 0x00060000 -#define UDMA_CH0_RESERVED7 0x00070000 -#define UDMA_CH0_RESERVED8 0x00080000 - -// -// Channel 1 -// -#define UDMA_CH1_USB0EP1TX 0x00000001 -#define UDMA_CH1_UART2TX 0x00010001 -#define UDMA_CH1_RESERVED2 0x00020001 -#define UDMA_CH1_TIMER4B 0x00030001 -#define UDMA_CH1_RESERVED4 0x00040001 -#define UDMA_CH1_RESERVED5 0x00050001 -#define UDMA_CH1_I2C0TX 0x00060001 -#define UDMA_CH1_RESERVED7 0x00070001 -#define UDMA_CH1_RESERVED8 0x00080001 - -// -// Channel 2 -// -#define UDMA_CH2_USB0EP2RX 0x00000002 -#define UDMA_CH2_TIMER3A 0x00010002 -#define UDMA_CH2_RESERVED2 0x00020002 -#define UDMA_CH2_RESERVED3 0x00030002 -#define UDMA_CH2_RESERVED4 0x00040002 -#define UDMA_CH2_RESERVED5 0x00050002 -#define UDMA_CH2_I2C1RX 0x00060002 -#define UDMA_CH2_RESERVED7 0x00070002 -#define UDMA_CH2_RESERVED8 0x00080002 - -// -// Channel 3 -// -#define UDMA_CH3_USB0EP2TX 0x00000003 -#define UDMA_CH3_TIMER3B 0x00010003 -#define UDMA_CH3_RESERVED2 0x00020003 -#define UDMA_CH3_LPC0_3 0x00030003 -#define UDMA_CH3_RESERVED4 0x00040003 -#define UDMA_CH3_RESERVED5 0x00050003 -#define UDMA_CH3_I2C1TX 0x00060003 -#define UDMA_CH3_RESERVED7 0x00070003 -#define UDMA_CH3_RESERVED8 0x00080003 - -// -// Channel 4 -// -#define UDMA_CH4_USB0EP3RX 0x00000004 -#define UDMA_CH4_TIMER2A 0x00010004 -#define UDMA_CH4_RESERVED2 0x00020004 -#define UDMA_CH4_GPIOA 0x00030004 -#define UDMA_CH4_RESERVED4 0x00040004 -#define UDMA_CH4_SHAMD50CIN 0x00050004 -#define UDMA_CH4_I2C2RX 0x00060004 -#define UDMA_CH4_RESERVED7 0x00070004 -#define UDMA_CH4_RESERVED8 0x00080004 - -// -// Channel 5 -// -#define UDMA_CH5_USB0EP3TX 0x00000005 -#define UDMA_CH5_TIMER2B 0x00010005 -#define UDMA_CH5_RESERVED2 0x00020005 -#define UDMA_CH5_GPIOB 0x00030005 -#define UDMA_CH5_RESERVED4 0x00040005 -#define UDMA_CH5_SHAMD50DIN 0x00050005 -#define UDMA_CH5_I2C2TX 0x00060005 -#define UDMA_CH5_RESERVED7 0x00070005 -#define UDMA_CH5_RESERVED8 0x00080005 - -// -// Channel 6 -// -#define UDMA_CH6_RESERVED0 0x00000006 -#define UDMA_CH6_ETH0RX 0x00000006 -#define UDMA_CH6_TIMER2A 0x00010006 -#define UDMA_CH6_UART5RX 0x00020006 -#define UDMA_CH6_GPIOC 0x00030006 -#define UDMA_CH6_I2C0RX 0x00040006 -#define UDMA_CH6_SHAMD50COUT 0x00050006 -#define UDMA_CH6_RESERVED6 0x00060006 -#define UDMA_CH6_RESERVED7 0x00070006 -#define UDMA_CH6_RESERVED8 0x00080006 - -// -// Channel 7 -// -#define UDMA_CH7_RESERVED0 0x00000007 -#define UDMA_CH7_ETH0TX 0x00000007 -#define UDMA_CH7_TIMER2B 0x00010007 -#define UDMA_CH7_UART5TX 0x00020007 -#define UDMA_CH7_GPIOD 0x00030007 -#define UDMA_CH7_I2C0TX 0x00040007 -#define UDMA_CH7_RESERVED5 0x00050007 -#define UDMA_CH7_RESERVED6 0x00060007 -#define UDMA_CH7_RESERVED7 0x00070007 -#define UDMA_CH7_RESERVED8 0x00080007 - -// -// Channel 8 -// -#define UDMA_CH8_UART0RX 0x00000008 -#define UDMA_CH8_UART1RX 0x00010008 -#define UDMA_CH8_RESERVED2 0x00020008 -#define UDMA_CH8_TIMER5A 0x00030008 -#define UDMA_CH8_I2C1RX 0x00040008 -#define UDMA_CH8_RESERVED5 0x00050008 -#define UDMA_CH8_RESERVED6 0x00060008 -#define UDMA_CH8_RESERVED7 0x00070008 -#define UDMA_CH8_RESERVED8 0x00080008 - -// -// Channel 9 -// -#define UDMA_CH9_UART0TX 0x00000009 -#define UDMA_CH9_UART1TX 0x00010009 -#define UDMA_CH9_RESERVED2 0x00020009 -#define UDMA_CH9_TIMER5B 0x00030009 -#define UDMA_CH9_I2C1TX 0x00040009 -#define UDMA_CH9_RESERVED5 0x00050009 -#define UDMA_CH9_RESERVED6 0x00060009 -#define UDMA_CH9_RESERVED7 0x00070009 -#define UDMA_CH9_RESERVED8 0x00080009 - -// -// Channel 10 -// -#define UDMA_CH10_SSI0RX 0x0000000A -#define UDMA_CH10_SSI1RX 0x0001000A -#define UDMA_CH10_UART6RX 0x0002000A -#define UDMA_CH10_WTIMER0A 0x0003000A -#define UDMA_CH10_I2C2RX 0x0004000A -#define UDMA_CH10_RESERVED5 0x0005000A -#define UDMA_CH10_RESERVED6 0x0006000A -#define UDMA_CH10_TIMER6A 0x0007000A -#define UDMA_CH10_RESERVED8 0x0008000A - -// -// Channel 11 -// -#define UDMA_CH11_SSI0TX 0x0000000B -#define UDMA_CH11_SSI1TX 0x0001000B -#define UDMA_CH11_UART6TX 0x0002000B -#define UDMA_CH11_WTIMER0B 0x0003000B -#define UDMA_CH11_I2C2TX 0x0004000B -#define UDMA_CH11_RESERVED5 0x0005000B -#define UDMA_CH11_RESERVED6 0x0006000B -#define UDMA_CH11_TIMER6B 0x0007000B -#define UDMA_CH11_RESERVED8 0x0008000B - -// -// Channel 12 -// -#define UDMA_CH12_RESERVED0 0x0000000C -#define UDMA_CH12_UART2RX 0x0001000C -#define UDMA_CH12_SSI2RX 0x0002000C -#define UDMA_CH12_WTIMER1A 0x0003000C -#define UDMA_CH12_GPIOK 0x0004000C -#define UDMA_CH12_AES0CIN 0x0005000C -#define UDMA_CH12_RESERVED6 0x0006000C -#define UDMA_CH12_TIMER7A 0x0007000C -#define UDMA_CH12_RESERVED8 0x0008000C - -// -// Channel 13 -// -#define UDMA_CH13_RESERVED0 0x0000000D -#define UDMA_CH13_UART2TX 0x0001000D -#define UDMA_CH13_SSI2TX 0x0002000D -#define UDMA_CH13_WTIMER1B 0x0003000D -#define UDMA_CH13_GPIOL 0x0004000D -#define UDMA_CH13_AES0COUT 0x0005000D -#define UDMA_CH13_RESERVED6 0x0006000D -#define UDMA_CH13_TIMER7B 0x0007000D -#define UDMA_CH13_RESERVED8 0x0008000D - -// -// Channel 14 -// -#define UDMA_CH14_ADC0_0 0x0000000E -#define UDMA_CH14_TIMER2A 0x0001000E -#define UDMA_CH14_SSI3RX 0x0002000E -#define UDMA_CH14_GPIOE 0x0003000E -#define UDMA_CH14_GPIOM 0x0004000E -#define UDMA_CH14_AES0DIN 0x0005000E -#define UDMA_CH14_RESERVED6 0x0006000E -#define UDMA_CH14_RESERVED7 0x0007000E -#define UDMA_CH14_RESERVED8 0x0008000E - -// -// Channel 15 -// -#define UDMA_CH15_ADC0_1 0x0000000F -#define UDMA_CH15_TIMER2B 0x0001000F -#define UDMA_CH15_SSI3TX 0x0002000F -#define UDMA_CH15_GPIOF 0x0003000F -#define UDMA_CH15_GPION 0x0004000F -#define UDMA_CH15_AES0DOUT 0x0005000F -#define UDMA_CH15_RESERVED6 0x0006000F -#define UDMA_CH15_RESERVED7 0x0007000F -#define UDMA_CH15_RESERVED8 0x0008000F - -// -// Channel 16 -// -#define UDMA_CH16_ADC0_2 0x00000010 -#define UDMA_CH16_RESERVED1 0x00010010 -#define UDMA_CH16_UART3RX 0x00020010 -#define UDMA_CH16_WTIMER2A 0x00030010 -#define UDMA_CH16_GPIOP 0x00040010 -#define UDMA_CH16_RESERVED5 0x00050010 -#define UDMA_CH16_RESERVED6 0x00060010 -#define UDMA_CH16_RESERVED7 0x00070010 -#define UDMA_CH16_RESERVED8 0x00080010 - -// -// Channel 17 -// -#define UDMA_CH17_ADC0_3 0x00000011 -#define UDMA_CH17_RESERVED1 0x00010011 -#define UDMA_CH17_UART3TX 0x00020011 -#define UDMA_CH17_WTIMER2B 0x00030011 -#define UDMA_CH17_RESERVED4 0x00040011 -#define UDMA_CH17_RESERVED5 0x00050011 -#define UDMA_CH17_RESERVED6 0x00060011 -#define UDMA_CH17_RESERVED7 0x00070011 -#define UDMA_CH17_RESERVED8 0x00080011 - -// -// Channel 18 -// -#define UDMA_CH18_TIMER0A 0x00000012 -#define UDMA_CH18_TIMER1A 0x00010012 -#define UDMA_CH18_UART4RX 0x00020012 -#define UDMA_CH18_GPIOB 0x00030012 -#define UDMA_CH18_I2C3RX 0x00040012 -#define UDMA_CH18_RESERVED5 0x00050012 -#define UDMA_CH18_RESERVED6 0x00060012 -#define UDMA_CH18_RESERVED7 0x00070012 -#define UDMA_CH18_RESERVED8 0x00080012 - -// -// Channel 19 -// -#define UDMA_CH19_TIMER0B 0x00000013 -#define UDMA_CH19_TIMER1B 0x00010013 -#define UDMA_CH19_UART4TX 0x00020013 -#define UDMA_CH19_GPIOG 0x00030013 -#define UDMA_CH19_I2C3TX 0x00040013 -#define UDMA_CH19_RESERVED5 0x00050013 -#define UDMA_CH19_RESERVED6 0x00060013 -#define UDMA_CH19_RESERVED7 0x00070013 -#define UDMA_CH19_RESERVED8 0x00080013 - -// -// Channel 20 -// -#define UDMA_CH20_TIMER1A 0x00000014 -#define UDMA_CH20_RESERVED1 0x00010014 -#define UDMA_CH20_EPI0RX 0x00010014 -#define UDMA_CH20_UART7RX 0x00020014 -#define UDMA_CH20_GPIOH 0x00030014 -#define UDMA_CH20_I2C4RX 0x00040014 -#define UDMA_CH20_DES0CIN 0x00050014 -#define UDMA_CH20_RESERVED6 0x00060014 -#define UDMA_CH20_RESERVED7 0x00070014 -#define UDMA_CH20_RESERVED8 0x00080014 - -// -// Channel 21 -// -#define UDMA_CH21_TIMER1B 0x00000015 -#define UDMA_CH21_RESERVED1 0x00010015 -#define UDMA_CH21_EPI0TX 0x00010015 -#define UDMA_CH21_UART7TX 0x00020015 -#define UDMA_CH21_GPIOJ 0x00030015 -#define UDMA_CH21_I2C4TX 0x00040015 -#define UDMA_CH21_DES0DIN 0x00050015 -#define UDMA_CH21_RESERVED6 0x00060015 -#define UDMA_CH21_RESERVED7 0x00070015 -#define UDMA_CH21_RESERVED8 0x00080015 - -// -// Channel 22 -// -#define UDMA_CH22_UART1RX 0x00000016 -#define UDMA_CH22_RESERVED1 0x00010016 -#define UDMA_CH22_RESERVED2 0x00020016 -#define UDMA_CH22_LPC0_2 0x00030016 -#define UDMA_CH22_I2C5RX 0x00040016 -#define UDMA_CH22_DES0DOUT 0x00050016 -#define UDMA_CH22_RESERVED6 0x00060016 -#define UDMA_CH22_RESERVED7 0x00070016 -#define UDMA_CH22_I2C8RX 0x00080016 - -// -// Channel 23 -// -#define UDMA_CH23_UART1TX 0x00000017 -#define UDMA_CH23_RESERVED1 0x00010017 -#define UDMA_CH23_RESERVED2 0x00020017 -#define UDMA_CH23_LPC0_1 0x00030017 -#define UDMA_CH23_I2C5TX 0x00040017 -#define UDMA_CH23_RESERVED5 0x00050017 -#define UDMA_CH23_RESERVED6 0x00060017 -#define UDMA_CH23_RESERVED7 0x00070017 -#define UDMA_CH23_I2C8TX 0x00080017 - -// -// Channel 24 -// -#define UDMA_CH24_SSI1RX 0x00000018 -#define UDMA_CH24_ADC1_0 0x00010018 -#define UDMA_CH24_RESERVED2 0x00020018 -#define UDMA_CH24_WTIMER3A 0x00030018 -#define UDMA_CH24_GPIOQ 0x00040018 -#define UDMA_CH24_RESERVED5 0x00050018 -#define UDMA_CH24_RESERVED6 0x00060018 -#define UDMA_CH24_RESERVED7 0x00070018 -#define UDMA_CH24_I2C9RX 0x00080018 - -// -// Channel 25 -// -#define UDMA_CH25_SSI1TX 0x00000019 -#define UDMA_CH25_ADC1_1 0x00010019 -#define UDMA_CH25_RESERVED2 0x00020019 -#define UDMA_CH25_WTIMER3B 0x00030019 -#define UDMA_CH25_RESERVED4 0x00040019 -#define UDMA_CH25_RESERVED5 0x00050019 -#define UDMA_CH25_RESERVED6 0x00060019 -#define UDMA_CH25_RESERVED7 0x00070019 -#define UDMA_CH25_I2C9TX 0x00080019 - -// -// Channel 26 -// -#define UDMA_CH26_RESERVED0 0x0000001A -#define UDMA_CH26_ADC1_2 0x0001001A -#define UDMA_CH26_RESERVED2 0x0002001A -#define UDMA_CH26_WTIMER4A 0x0003001A -#define UDMA_CH26_RESERVED4 0x0004001A -#define UDMA_CH26_RESERVED5 0x0005001A -#define UDMA_CH26_RESERVED6 0x0006001A -#define UDMA_CH26_RESERVED7 0x0007001A -#define UDMA_CH26_I2C6RX 0x0008001A - -// -// Channel 27 -// -#define UDMA_CH27_RESERVED0 0x0000001B -#define UDMA_CH27_ADC1_3 0x0001001B -#define UDMA_CH27_RESERVED2 0x0002001B -#define UDMA_CH27_WTIMER4B 0x0003001B -#define UDMA_CH27_RESERVED4 0x0004001B -#define UDMA_CH27_RESERVED5 0x0005001B -#define UDMA_CH27_RESERVED6 0x0006001B -#define UDMA_CH27_RESERVED7 0x0007001B -#define UDMA_CH27_I2C6TX 0x0008001B - -// -// Channel 28 -// -#define UDMA_CH28_RESERVED0 0x0000001C -#define UDMA_CH28_RESERVED1 0x0001001C -#define UDMA_CH28_RESERVED2 0x0002001C -#define UDMA_CH28_WTIMER5A 0x0003001C -#define UDMA_CH28_RESERVED4 0x0004001C -#define UDMA_CH28_RESERVED5 0x0005001C -#define UDMA_CH28_RESERVED6 0x0006001C -#define UDMA_CH28_RESERVED7 0x0007001C -#define UDMA_CH28_I2C7RX 0x0008001C - -// -// Channel 29 -// -#define UDMA_CH29_RESERVED0 0x0000001D -#define UDMA_CH29_RESERVED1 0x0001001D -#define UDMA_CH29_RESERVED2 0x0002001D -#define UDMA_CH29_WTIMER5B 0x0003001D -#define UDMA_CH29_RESERVED4 0x0004001D -#define UDMA_CH29_RESERVED5 0x0005001D -#define UDMA_CH29_RESERVED6 0x0006001D -#define UDMA_CH29_RESERVED7 0x0007001D -#define UDMA_CH29_I2C7TX 0x0008001D - -// -// Channel 30 -// -#define UDMA_CH30_SW 0x0000001E -#define UDMA_CH30_RESERVED1 0x0001001E -#define UDMA_CH30_RESERVED2 0x0002001E -#define UDMA_CH30_RESERVED3 0x0003001E -#define UDMA_CH30_RESERVED4 0x0004001E -#define UDMA_CH30_RESERVED5 0x0005001E -#define UDMA_CH30_RESERVED6 0x0006001E -#define UDMA_CH30_EPI0RX 0x0007001E -#define UDMA_CH30_1WIRE0 0x0008001E - -// -// Channel 31 -// -#define UDMA_CH31_RESERVED0 0x0000001F -#define UDMA_CH31_RESERVED1 0x0001001F -#define UDMA_CH31_RESERVED2 0x0002001F -#define UDMA_CH31_LPC0_0 0x0003001F -#define UDMA_CH31_RESERVED4 0x0004001F -#define UDMA_CH31_RESERVED5 0x0005001F -#define UDMA_CH31_RESERVED6 0x0006001F -#define UDMA_CH31_EPI0RX 0x0007001F -#define UDMA_CH31_RESERVED8 0x0008001F - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void uDMAEnable(void); -extern void uDMADisable(void); -extern uint32_t uDMAErrorStatusGet(void); -extern void uDMAErrorStatusClear(void); -extern void uDMAChannelEnable(uint32_t ui32ChannelNum); -extern void uDMAChannelDisable(uint32_t ui32ChannelNum); -extern bool uDMAChannelIsEnabled(uint32_t ui32ChannelNum); -extern void uDMAControlBaseSet(void *pControlTable); -extern void *uDMAControlBaseGet(void); -extern void *uDMAControlAlternateBaseGet(void); -extern void uDMAChannelRequest(uint32_t ui32ChannelNum); -extern void uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, - uint32_t ui32Attr); -extern void uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, - uint32_t ui32Attr); -extern uint32_t uDMAChannelAttributeGet(uint32_t ui32ChannelNum); -extern void uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, - uint32_t ui32Control); -extern void uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, - uint32_t ui32Mode, void *pvSrcAddr, - void *pvDstAddr, uint32_t ui32TransferSize); -extern void uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, - uint32_t ui32TaskCount, - void *pvTaskList, - uint32_t ui32IsPeriphSG); -extern uint32_t uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex); -extern uint32_t uDMAChannelModeGet(uint32_t ui32ChannelStructIndex); -extern void uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void)); -extern void uDMAIntUnregister(uint32_t ui32IntChannel); -extern uint32_t uDMAIntStatus(void); -extern void uDMAIntClear(uint32_t ui32ChanMask); -extern void uDMAChannelAssign(uint32_t ui32Mapping); - -//***************************************************************************** -// -// The following functions and definitions are deprecated and will be removed -// from the API in the future. Use uDMAChannelAssign() instead to accomplish -// the same end. -// -//***************************************************************************** -#ifndef DEPRECATED -//***************************************************************************** -// -// uDMA default/secondary peripheral selections, to be passed to -// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault(). -// -//***************************************************************************** -#define UDMA_DEF_USBEP1RX_SEC_UART2RX \ - 0x00000001 -#define UDMA_DEF_USBEP1TX_SEC_UART2TX \ - 0x00000002 -#define UDMA_DEF_USBEP2RX_SEC_TMR3A \ - 0x00000004 -#define UDMA_DEF_USBEP2TX_SEC_TMR3B \ - 0x00000008 -#define UDMA_DEF_USBEP3RX_SEC_TMR2A \ - 0x00000010 -#define UDMA_DEF_USBEP3TX_SEC_TMR2B \ - 0x00000020 -#define UDMA_DEF_ETH0RX_SEC_TMR2A \ - 0x00000040 -#define UDMA_DEF_ETH0TX_SEC_TMR2B \ - 0x00000080 -#define UDMA_DEF_UART0RX_SEC_UART1RX \ - 0x00000100 -#define UDMA_DEF_UART0TX_SEC_UART1TX \ - 0x00000200 -#define UDMA_DEF_SSI0RX_SEC_SSI1RX \ - 0x00000400 -#define UDMA_DEF_SSI0TX_SEC_SSI1TX \ - 0x00000800 -#define UDMA_DEF_RESERVED_SEC_UART2RX \ - 0x00001000 -#define UDMA_DEF_RESERVED_SEC_UART2TX \ - 0x00002000 -#define UDMA_DEF_ADC00_SEC_TMR2A \ - 0x00004000 -#define UDMA_DEF_ADC01_SEC_TMR2B \ - 0x00008000 -#define UDMA_DEF_ADC02_SEC_RESERVED \ - 0x00010000 -#define UDMA_DEF_ADC03_SEC_RESERVED \ - 0x00020000 -#define UDMA_DEF_TMR0A_SEC_TMR1A \ - 0x00040000 -#define UDMA_DEF_TMR0B_SEC_TMR1B \ - 0x00080000 -#define UDMA_DEF_TMR1A_SEC_EPI0RX \ - 0x00100000 -#define UDMA_DEF_TMR1B_SEC_EPI0TX \ - 0x00200000 -#define UDMA_DEF_UART1RX_SEC_RESERVED \ - 0x00400000 -#define UDMA_DEF_UART1TX_SEC_RESERVED \ - 0x00800000 -#define UDMA_DEF_SSI1RX_SEC_ADC10 \ - 0x01000000 -#define UDMA_DEF_SSI1TX_SEC_ADC11 \ - 0x02000000 -#define UDMA_DEF_RESERVED_SEC_ADC12 \ - 0x04000000 -#define UDMA_DEF_RESERVED_SEC_ADC13 \ - 0x08000000 -#define UDMA_DEF_I2S0RX_SEC_RESERVED \ - 0x10000000 -#define UDMA_DEF_I2S0TX_SEC_RESERVED \ - 0x20000000 - -extern void uDMAChannelSelectDefault(uint32_t ui32DefPeriphs); -extern void uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs); - -#endif -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_UDMA_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/usb.c b/bsp/tm4c129x-dk/libraries/driverlib/usb.c deleted file mode 100644 index 839a5575edd24523e8e3f10f9f9dc6451a614b55..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/usb.c +++ /dev/null @@ -1,5910 +0,0 @@ -//***************************************************************************** -// -// usb.c - Driver for the USB Interface. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup usb_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_usb.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" -#include "driverlib/udma.h" -#include "driverlib/usb.h" - -//***************************************************************************** -// -// Amount to shift the RX interrupt sources by in the flags used in the -// interrupt calls. -// -//***************************************************************************** -#define USB_INTEP_RX_SHIFT 16 - -//***************************************************************************** -// -// Amount to shift the RX endpoint status sources by in the flags used in the -// calls. -// -//***************************************************************************** -#define USB_RX_EPSTATUS_SHIFT 16 - -//***************************************************************************** -// -// Converts from an endpoint specifier to the offset of the endpoint's -// control/status registers. -// -//***************************************************************************** -#define EP_OFFSET(Endpoint) (Endpoint - 0x10) - -//***************************************************************************** -// -// Sets one of the indexed registers. -// -// \param ui32Base specifies the USB module base address. -// \param ui32Endpoint is the endpoint index to target for this write. -// \param ui32IndexedReg is the indexed register to write to. -// \param ui8Value is the value to write to the register. -// -// This function is used to access the indexed registers for each endpoint. -// The only registers that are indexed are the FIFO configuration registers, -// which are not used after configuration. -// -// \return None. -// -//***************************************************************************** -static void -_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size) -{ - uint32_t ui32Index; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || - (ui32Endpoint == 3)); - ASSERT((ui32Size == 1) || (ui32Size == 2)); - - // - // Save the old index in case it was in use. - // - ui32Index = HWREGB(ui32Base + USB_O_EPIDX); - - // - // Set the index. - // - HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; - - // - // Determine the size of the register value. - // - if(ui32Size == 1) - { - // - // Set the value. - // - HWREGB(ui32Base + ui32IndexedReg) = ui32Value; - } - else - { - // - // Set the value. - // - HWREGH(ui32Base + ui32IndexedReg) = ui32Value; - } - - // - // Restore the old index in case it was in use. - // - HWREGB(ui32Base + USB_O_EPIDX) = ui32Index; -} - -//***************************************************************************** -// -// Reads one of the indexed registers. -// -// \param ui32Base specifies the USB module base address. -// \param ui32Endpoint is the endpoint index to target for this write. -// \param ui32IndexedReg is the indexed register to write to. -// \param ui32Size is a value of 1 or 2 indicating the byte size of the read. -// -// This function is used internally to access the indexed registers for each -// endpoint. The only registers that are indexed are the FIFO configuration -// registers, which are not used after configuration. -// -// \return The value in the register requested. -// -//***************************************************************************** -static uint32_t -_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32IndexedReg, uint32_t ui32Size) -{ - uint8_t ui8Index; - uint32_t ui32Value; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || - (ui32Endpoint == 3)); - ASSERT((ui32Size == 1) || (ui32Size == 2)); - - // - // Save the old index in case it was in use. - // - ui8Index = HWREGB(ui32Base + USB_O_EPIDX); - - // - // Set the index. - // - HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; - - // - // Determine the size of the register value. - // - if(ui32Size == 1) - { - // - // Get the value. - // - ui32Value = HWREGB(ui32Base + ui32IndexedReg); - } - else - { - // - // Get the value. - // - ui32Value = HWREGH(ui32Base + ui32IndexedReg); - } - - // - // Restore the old index in case it was in use. - // - HWREGB(ui32Base + USB_O_EPIDX) = ui8Index; - - // - // Return the register's value. - // - return(ui32Value); -} - -//***************************************************************************** -// -//! Puts the USB bus in a suspended state. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! When used in host mode, this function puts the USB bus in the suspended -//! state. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostSuspend(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Send the suspend signaling to the USB bus. - // - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND; -} - -//***************************************************************************** -// -//! Handles the USB bus reset condition. -//! -//! \param ui32Base specifies the USB module base address. -//! \param bStart specifies whether to start or stop signaling reset on the USB -//! bus. -//! -//! When this function is called with the \e bStart parameter set to \b true, -//! this function causes the start of a reset condition on the USB bus. -//! The caller must then delay at least 20ms before calling this function -//! again with the \e bStart parameter set to \b false. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostReset(uint32_t ui32Base, bool bStart) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Send a reset signal to the bus. - // - if(bStart) - { - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET; - } - else - { - HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET; - } -} - -//***************************************************************************** -// -//! Enables or disables USB high-speed negotiation. -//! -//! \param ui32Base specifies the USB module base address. -//! \param bEnable specifies whether to enable or disable high-speed -//! negotiation. -//! -//! High-speed negotiations for both host and device mode are enabled when this -//! function is called with the \e bEnable parameter set to \b true. In device -//! mode this causes the device to negotiate for high speed when the -//! USB controller receives a reset from the host. In host mode, the USB host -//! enables high-speed negotiations when resetting the connected device. If -//! \e bEnable is set to \b false the controller only operates only in -//! full-speed or low-speed. -//! -//! \b Example: Enable USB high-speed mode. -//! -//! \verbatim -//! // -//! // Enable USB high-speed mode. -//! // -//! USBHighSpeed(USB0_BASE, true); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices and should only be -//! called when the USB is connected to an external ULPI PHY. Please -//! check the data sheet to determine if the USB controller can interface with -//! a ULPI PHY. -//! -//! \return None. -// -//***************************************************************************** -void -USBHighSpeed(uint32_t ui32Base, bool bEnable) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - if(bEnable) - { - // - // Enable high speed mode negotiations in hosts or device mode. - // - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_HSENAB; - } - else - { - // - // Enable high speed mode negotiations in hosts or device mode. - // - HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_HSENAB; - } -} - -//***************************************************************************** -// -//! Handles the USB bus resume condition. -//! -//! \param ui32Base specifies the USB module base address. -//! \param bStart specifies if the USB controller is entering or leaving the -//! resume signaling state. -//! -//! When in device mode, this function brings the USB controller out of the -//! suspend state. This call must first be made with the \e bStart parameter -//! set to \b true to start resume signaling. The device application must -//! then delay at least 10ms but not more than 15ms before calling this -//! function with the \e bStart parameter set to \b false. -//! -//! When in host mode, this function signals devices to leave the suspend -//! state. This call must first be made with the \e bStart parameter set to -//! \b true to start resume signaling. The host application must then delay -//! at least 20ms before calling this function with the \e bStart parameter set -//! to \b false. This action causes the controller to complete the resume -//! signaling on the USB bus. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostResume(uint32_t ui32Base, bool bStart) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Send a resume signal to the bus. - // - if(bStart) - { - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME; - } - else - { - HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME; - } -} - -//***************************************************************************** -// -//! Returns the current speed of the USB device connected. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current speed of the USB bus in host mode. -//! -//! \b Example: Get the USB connection speed. -//! -//! \verbatim -//! // -//! // Get the connection speed of the device connected to the USB controller. -//! // -//! USBHostSpeedGet(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in host mode. -//! -//! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, -//! \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. -// -//***************************************************************************** -uint32_t -USBHostSpeedGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // If the Full Speed device bit is set, then this is a full speed device. - // - if(HWREGB(ui32Base + USB_O_POWER) & USB_POWER_HSMODE) - { - return(USB_HIGH_SPEED); - } - - // - // If the Full Speed device bit is set, then this is a full speed device. - // - if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV) - { - return(USB_FULL_SPEED); - } - - // - // If the Low Speed device bit is set, then this is a low speed device. - // - if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV) - { - return(USB_LOW_SPEED); - } - - // - // The device speed is not known. - // - return(USB_UNDEF_SPEED); -} - -//***************************************************************************** -// -//! Returns the current speed of the USB controller in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the operating speed of the connection to the USB host -//! controller. This function returns either \b USB_HIGH_SPEED or -//! \b USB_FULL_SPEED to indicate the connection speed in device mode. -//! -//! \b Example: Get the USB connection speed. -//! -//! \verbatim -//! // -//! // Get the connection speed of the USB controller. -//! // -//! USBDevSpeedGet(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in device mode. -//! -//! \return Returns either \b USB_HIGH_SPEED or \b USB_FULL_SPEED. -// -//***************************************************************************** -uint32_t -USBDevSpeedGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // If the Full Speed device bit is set, then this is a full speed device. - // - if(HWREGB(ui32Base + USB_O_POWER) & USB_POWER_HSMODE) - { - return(USB_HIGH_SPEED); - } - - return(USB_FULL_SPEED); -} - -//***************************************************************************** -// -//! Disables control interrupts on a specified USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Flags specifies which control interrupts to disable. -//! -//! This function disables the control interrupts for the USB controller -//! specified by the \e ui32Base parameter. The \e ui32Flags parameter -//! specifies which control interrupts to disable. The flags passed in the -//! \e ui32Flags parameters must be the definitions that start with -//! \b USB_INTCTRL_* and not any other \b USB_INT flags. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0); - - // - // If any general interrupts were disabled then write the general interrupt - // settings out to the hardware. - // - if(ui32Flags & USB_INTCTRL_STATUS) - { - HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS); - } - - // - // Disable the power fault interrupt. - // - if(ui32Flags & USB_INTCTRL_POWER_FAULT) - { - HWREG(ui32Base + USB_O_EPCIM) = 0; - } - - // - // Disable the ID pin detect interrupt. - // - if(ui32Flags & USB_INTCTRL_MODE_DETECT) - { - HWREG(USB0_BASE + USB_O_IDVIM) = 0; - } -} - -//***************************************************************************** -// -//! Enables control interrupts on a specified USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Flags specifies which control interrupts to enable. -//! -//! This function enables the control interrupts for the USB controller -//! specified by the \e ui32Base parameter. The \e ui32Flags parameter -//! specifies which control interrupts to enable. The flags passed in the -//! \e ui32Flags parameters must be the definitions that start with -//! \b USB_INTCTRL_* and not any other \b USB_INT flags. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0); - - // - // If any general interrupts were enabled, then write the general - // interrupt settings out to the hardware. - // - if(ui32Flags & USB_INTCTRL_STATUS) - { - HWREGB(ui32Base + USB_O_IE) |= ui32Flags; - } - - // - // Enable the power fault interrupt. - // - if(ui32Flags & USB_INTCTRL_POWER_FAULT) - { - HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF; - } - - // - // Enable the ID pin detect interrupt. - // - if(ui32Flags & USB_INTCTRL_MODE_DETECT) - { - HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID; - } -} - -//***************************************************************************** -// -//! Returns the control interrupt status on a specified USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function reads control interrupt status for a USB controller. This -//! call returns the current status for control interrupts only, the endpoint -//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit -//! values returned are compared against the \b USB_INTCTRL_* values. -//! -//! The following are the meanings of all \b USB_INCTRL_ flags and the modes -//! for which they are valid. These values apply to any calls to -//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). -//! Some of these flags are only valid in the following modes as indicated in -//! the parentheses: Host, Device, and OTG. -//! -//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. -//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). -//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable -//! (OTG Only). -//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) -//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) -//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) -//! - \b USB_INTCTRL_SOF - Start of Frame Detected. -//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past -//! the end of a frame (Host Only) -//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) -//! - \b USB_INTCTRL_RESUME - Resume signaling detected. -//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device -//! Only) -//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed -//! (OTG Only) -//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) -//! -//! \note This call clears the source of all of the control status interrupts. -//! -//! \return Returns the status of the control interrupts for a USB controller. -// -//***************************************************************************** -uint32_t -USBIntStatusControl(uint32_t ui32Base) -{ - uint32_t ui32Status; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Get the general interrupt status, these bits go into the upper 8 bits - // of the returned value. - // - ui32Status = HWREGB(ui32Base + USB_O_IS); - - // - // Add the power fault status. - // - if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) - { - // - // Indicate a power fault was detected. - // - ui32Status |= USB_INTCTRL_POWER_FAULT; - - // - // Clear the power fault interrupt. - // - HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; - } - - if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) - { - // - // Indicate an id detection. - // - ui32Status |= USB_INTCTRL_MODE_DETECT; - - // - // Clear the id detection interrupt. - // - HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; - } - - // - // Return the combined interrupt status. - // - return(ui32Status); -} - -//***************************************************************************** -// -//! Disables endpoint interrupts on a specified USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Flags specifies which endpoint interrupts to disable. -//! -//! This function disables endpoint interrupts for the USB controller specified -//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which -//! endpoint interrupts to disable. The flags passed in the \e ui32Flags -//! parameters must be the definitions that start with \b USB_INTEP_* and not -//! any other \b USB_INT flags. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // If any transmit interrupts were disabled, then write the transmit - // interrupt settings out to the hardware. - // - HWREGH(ui32Base + USB_O_TXIE) &= - ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); - - // - // If any receive interrupts were disabled, then write the receive - // interrupt settings out to the hardware. - // - HWREGH(ui32Base + USB_O_RXIE) &= - ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> - USB_INTEP_RX_SHIFT); -} - -//***************************************************************************** -// -//! Enables endpoint interrupts on a specified USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Flags specifies which endpoint interrupts to enable. -//! -//! This function enables endpoint interrupts for the USB controller specified -//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which -//! endpoint interrupts to enable. The flags passed in the \e ui32Flags -//! parameters must be the definitions that start with \b USB_INTEP_* and not -//! any other \b USB_INT flags. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Enable any transmit endpoint interrupts. - // - HWREGH(ui32Base + USB_O_TXIE) |= - ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); - - // - // Enable any receive endpoint interrupts. - // - HWREGH(ui32Base + USB_O_RXIE) |= - ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> - USB_INTEP_RX_SHIFT); -} - -//***************************************************************************** -// -//! Returns the endpoint interrupt status on a specified USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function reads endpoint interrupt status for a USB controller. This -//! call returns the current status for endpoint interrupts only, the control -//! interrupt status is retrieved by calling USBIntStatusControl(). The bit -//! values returned are compared against the \b USB_INTEP_* values. -//! These values are grouped into classes for \b USB_INTEP_HOST_* and -//! \b USB_INTEP_DEV_* values to handle both host and device modes with all -//! endpoints. -//! -//! \note This call clears the source of all of the endpoint interrupts. -//! -//! \return Returns the status of the endpoint interrupts for a USB controller. -// -//***************************************************************************** -uint32_t -USBIntStatusEndpoint(uint32_t ui32Base) -{ - uint32_t ui32Status; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Get the transmit interrupt status. - // - ui32Status = HWREGH(ui32Base + USB_O_TXIS); - ui32Status |= (HWREGH(ui32Base + USB_O_RXIS) << USB_INTEP_RX_SHIFT); - - // - // Return the combined interrupt status. - // - return(ui32Status); -} - -//***************************************************************************** -// -//! Returns the interrupt number for a specified USB module. -//! -//! \param ui32Base is the base address of the USB module. -//! -//! This function returns the interrupt number for the USB module with the base -//! address passed in the \e ui32Base parameter. -//! -//! \return Returns the USB interrupt number or 0 if the interrupt does not -//! exist. -// -//***************************************************************************** -static uint32_t -_USBIntNumberGet(uint32_t ui32Base) -{ - uint32_t ui32Int; - - if(CLASS_IS_TM4C123) - { - ui32Int = INT_USB0_TM4C123; - } - else if(CLASS_IS_TM4C129) - { - ui32Int = INT_USB0_TM4C129; - } - else - { - ui32Int = 0; - } - return(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param pfnHandler is a pointer to the function to be called when a USB -//! interrupt occurs. -//! -//! This function registers the handler to be called when a USB interrupt -//! occurs and enables the global USB interrupt in the interrupt controller. -//! The specific desired USB interrupts must be enabled via a separate call to -//! USBIntEnable(). It is the interrupt handler's responsibility to clear the -//! interrupt sources via calls to USBIntStatusControl() and -//! USBIntStatusEndpoint(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - ui32Int = _USBIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the USB interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function unregisters the interrupt handler. This function also -//! disables the USB interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering or -//! unregistering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - ui32Int = _USBIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the USB interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Returns the current status of an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! -//! This function returns the status of a specified endpoint. If any of these -//! status bits must be cleared, then the USBDevEndpointStatusClear() or the -//! USBHostEndpointStatusClear() functions must be called. -//! -//! The following are the status flags for host mode: -//! -//! - \b USB_HOST_IN_PID_ERROR - PID error on the specified endpoint. -//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. -//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. -//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN -//! endpoint in Isochronous mode. -//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than -//! the specified timeout period. -//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN -//! endpoint. -//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. -//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. -//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than -//! the specified timeout period. -//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT -//! request. -//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. -//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this -//! OUT endpoint. -//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. -//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not -//! completed. -//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the -//! specified timeout period. -//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on -//! endpoint zero. -//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an -//! IN transaction. -//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN -//! transaction. -//! -//! The following are the status flags for device mode: -//! -//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. -//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT -//! endpoint. -//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. -//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. -//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT -//! endpoint's FIFO. -//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. -//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. -//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no -//! data was ready. -//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. -//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not -//! completed. -//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End -//! condition was sent. -//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. -//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not -//! completed. -//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint -//! zero's OUT FIFO. -//! -//! \return The current status flags for the endpoint depending on mode. -// -//***************************************************************************** -uint32_t -USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - uint32_t ui32Status; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Get the TX portion of the endpoint status. - // - ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1); - - // - // Get the RX portion of the endpoint status. - // - ui32Status |= - ((HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) << - USB_RX_EPSTATUS_SHIFT); - - // - // Return the endpoint status. - // - return(ui32Status); -} - -//***************************************************************************** -// -//! Clears the status bits in this endpoint in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags are the status bits that are cleared. -//! -//! This function clears the status of any bits that are passed in the -//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value -//! returned from the USBEndpointStatus() call. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Clear the specified flags for the endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags; - } - else - { - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~ui32Flags; - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT); - } -} - -//***************************************************************************** -// -//! Clears the status bits in this endpoint in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags are the status bits that are cleared. -//! -//! This function clears the status of any bits that are passed in the -//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value -//! returned from the USBEndpointStatus() call. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // If this is endpoint 0, then the bits have different meaning and map - // into the TX memory location. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Set the Serviced RxPktRdy bit to clear the RxPktRdy. - // - if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY) - { - HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC; - } - - // - // Set the serviced Setup End bit to clear the SetupEnd status. - // - if(ui32Flags & USB_DEV_EP0_SETUP_END) - { - HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC; - } - - // - // Clear the Sent Stall status flag. - // - if(ui32Flags & USB_DEV_EP0_SENT_STALL) - { - HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL); - } - } - else - { - // - // Clear out any TX flags that were passed in. Only - // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. - // - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); - - // - // Clear out valid RX flags that were passed in. Only - // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN - // must be cleared. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | - USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); - } -} - -//***************************************************************************** -// -//! Sets the value data toggle on an endpoint in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies the endpoint to reset the data toggle. -//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1. -//! \param ui32Flags specifies whether to set the IN or OUT endpoint. -//! -//! This function is used to force the state of the data toggle in host mode. -//! If the value passed in the \e bDataToggle parameter is \b false, then the -//! data toggle is set to the DATA0 state, and if it is \b true it is set to -//! the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or -//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The -//! \e ui32Flags parameter is ignored for endpoint zero. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, - bool bDataToggle, uint32_t ui32Flags) -{ - uint32_t ui32DataToggle; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // The data toggle defaults to DATA0. - // - ui32DataToggle = 0; - - // - // See if the data toggle must be set to DATA1. - // - if(bDataToggle) - { - // - // Select the data toggle bit based on the endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - ui32DataToggle = USB_CSRH0_DT; - } - else if(ui32Flags == USB_EP_HOST_IN) - { - ui32DataToggle = USB_RXCSRH1_DT; - } - else - { - ui32DataToggle = USB_TXCSRH1_DT; - } - } - - // - // Set the data toggle based on the endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Set the write enable and the bit value for endpoint zero. - // - HWREGB(ui32Base + USB_O_CSRH0) = - ((HWREGB(ui32Base + USB_O_CSRH0) & - ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | - (ui32DataToggle | USB_CSRH0_DTWE)); - } - else if(ui32Flags == USB_EP_HOST_IN) - { - // - // Set the Write enable and the bit value for an IN endpoint. - // - HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) = - ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) & - ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | - (ui32DataToggle | USB_RXCSRH1_DTWE)); - } - else - { - // - // Set the Write enable and the bit value for an OUT endpoint. - // - HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) = - ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) & - ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | - (ui32DataToggle | USB_TXCSRH1_DTWE)); - } -} - -//***************************************************************************** -// -//! Sets the data toggle on an endpoint to zero. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies the endpoint to reset the data toggle. -//! \param ui32Flags specifies whether to access the IN or OUT endpoint. -//! -//! This function causes the USB controller to clear the data toggle for an -//! endpoint. This call is not valid for endpoint zero and can be made with -//! host or device controllers. -//! -//! The \e ui32Flags parameter must be one of \b USB_EP_HOST_OUT, -//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. -//! -//! \return None. -// -//***************************************************************************** -void -USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); - - // - // See if the transmit or receive data toggle must be cleared. - // - if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_TXCSRL1_CLRDT; - } - else - { - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_RXCSRL1_CLRDT; - } -} - -//***************************************************************************** -// -//! Enables or disables ping tokens for an endpoint using high-speed control -//! transfers in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies the endpoint to enable/disable ping tokens. -//! \param bEnable specifies whether enable or disable ping tokens. -//! -//! This function configures the USB controller to either send or not send ping -//! tokens during the data and status phase of high speed control transfers. -//! The only supported value for \e ui32Endpoint is \b USB_EP_0 because all -//! control transfers are handled using this endpoint. If the \e bEnable is -//! \b true then ping tokens are enabled, if \b false then ping tokens are -//! disabled. This must be used if the controller must support -//! communications with devices that do not support ping tokens in high speed -//! mode. -//! -//! \b Example: Disable ping transactions in host mode on endpoint 0. -//! -//! \verbatim -//! // -//! // Disable ping transaction on endpoint 0. -//! // -//! USBHostEndpointPing(USB0_BASE, USB_EP_0, false); -//! \endverbatim -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointPing(uint32_t ui32Base, uint32_t ui32Endpoint, bool bEnable) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0)); - - // - // Handle the endpoint 0 case separately. - // - if(bEnable) - { - HWREGB(USB0_BASE + USB_O_CSRH0) &= ~USB_CSRH0_DISPING; - } - else - { - HWREGB(USB0_BASE + USB_O_CSRH0) |= USB_CSRH0_DISPING; - } -} - -//***************************************************************************** -// -//! Stalls the specified endpoint in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies the endpoint to stall. -//! \param ui32Flags specifies whether to stall the IN or OUT endpoint. -//! -//! This function causes the endpoint number passed in to go into a stall -//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the -//! stall is issued on the IN portion of this endpoint. If the \e ui32Flags -//! parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion -//! of this endpoint. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Determine how to stall this endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Perform a stall on endpoint zero. - // - HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC; - } - else if(ui32Flags == USB_EP_DEV_IN) - { - // - // Perform a stall on an IN endpoint. - // - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_TXCSRL1_STALL; - } - else - { - // - // Perform a stall on an OUT endpoint. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_RXCSRL1_STALL; - } -} - -//***************************************************************************** -// -//! Clears the stall condition on the specified endpoint in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies which endpoint to remove the stall condition. -//! \param ui32Flags specifies whether to remove the stall condition from the -//! IN or the OUT portion of this endpoint. -//! -//! This function causes the endpoint number passed in to exit the stall -//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the -//! stall is cleared on the IN portion of this endpoint. If the \e ui32Flags -//! parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT -//! portion of this endpoint. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); - - // - // Determine how to clear the stall on this endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Clear the stall on endpoint zero. - // - HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED; - } - else if(ui32Flags == USB_EP_DEV_IN) - { - // - // Clear the stall on an IN endpoint. - // - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); - - // - // Reset the data toggle. - // - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_TXCSRL1_CLRDT; - } - else - { - // - // Clear the stall on an OUT endpoint. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); - - // - // Reset the data toggle. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_RXCSRL1_CLRDT; - } -} - -//***************************************************************************** -// -//! Connects the USB controller to the bus in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function causes the soft connect feature of the USB controller to -//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevConnect(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Enable connection to the USB bus. - // - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN; -} - -//***************************************************************************** -// -//! Removes the USB controller from the bus in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function causes the soft connect feature of the USB controller to -//! remove the device from the USB bus. A call to USBDevConnect() is needed to -//! reconnect to the bus. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevDisconnect(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Disable connection to the USB bus. - // - HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN); -} - -//***************************************************************************** -// -//! Sets the address in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Address is the address to use for a device. -//! -//! This function configures the device address on the USB bus. This address -//! was likely received via a SET ADDRESS command from the host controller. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Set the function address in the correct location. - // - HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address; -} - -//***************************************************************************** -// -//! Returns the current device address in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current device address. This address was set -//! by a call to USBDevAddrSet(). -//! -//! \note This function must only be called in device mode. -//! -//! \return The current device address. -// -//***************************************************************************** -uint32_t -USBDevAddrGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Return the function address. - // - return(HWREGB(ui32Base + USB_O_FADDR)); -} - -//***************************************************************************** -// -//! Sets the base configuration for a host endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32MaxPayload is the maximum payload for this endpoint. -//! \param ui32NAKPollInterval is the either the NAK timeout limit or the -//! polling interval, depending on the type of endpoint. -//! \param ui32TargetEndpoint is the endpoint that the host endpoint is -//! targeting. -//! \param ui32Flags are used to configure other endpoint settings. -//! -//! This function sets the basic configuration for the transmit or receive -//! portion of an endpoint in host mode. The \e ui32Flags parameter determines -//! some of the configuration while the other parameters provide the rest. The -//! \e ui32Flags parameter determines whether this is an IN endpoint -//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint -//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed -//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint -//! (\b USB_EP_SPEED_LOW). -//! -//! The \b USB_EP_MODE_ flags control the type of the endpoint. -//! - \b USB_EP_MODE_CTRL is a control endpoint. -//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. -//! - \b USB_EP_MODE_BULK is a bulk endpoint. -//! - \b USB_EP_MODE_INT is an interrupt endpoint. -//! -//! The \e ui32NAKPollInterval parameter has different meanings based on the -//! \b USB_EP_MODE value and whether or not this call is being made for -//! endpoint zero or another endpoint. For endpoint zero or any Bulk -//! endpoints, this value always indicates the number of frames to allow a -//! device to NAK before considering it a timeout. If this endpoint is an -//! isochronous or interrupt endpoint, this value is the polling interval for -//! this endpoint. -//! -//! For interrupt endpoints, the polling interval is the number of frames -//! between interrupt IN requests to an endpoint and has a range of 1 to 255. -//! For isochronous endpoints this value represents a polling interval of -//! 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the -//! \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) -//! frames before issuing a time out. -//! -//! There are two special time out values that can be specified when setting -//! the \e ui32NAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is -//! the maximum value that can be passed in this variable. The other is -//! \b DISABLE_NAK_LIMIT, which indicates that there is no limit on the -//! number of NAKs. -//! -//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the -//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA -//! controller is configured and how it is being used. See the ``Using USB -//! with the uDMA Controller'' or the ''Using the integrated USB DMA -//! Controller'' section for more information on DMA configuration depending -//! on the type of DMA that is supported by the USB controller. -//! -//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit -//! is specified to cause the transmission of data on the USB bus to start -//! as soon as the number of bytes specified by \e ui32MaxPayload has been -//! written into the OUT FIFO for this endpoint. -//! -//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST -//! bit can be specified to trigger the request for more data once the FIFO has -//! been drained enough to fit \e ui32MaxPayload bytes. The -//! \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag -//! automatically once the data has been read from the FIFO. If this option is -//! not used, this flag must be manually cleared via a call to -//! USBDevEndpointStatusClear() or USBHostEndpointStatusClear(). -//! -//! For interrupt endpoints in low or full speed mode, the polling interval -//! (\e ui32NAKPollInterval) is the number of frames between interrupt IN -//! requests to an endpoint and has a range of 1 to 255. For interrupt -//! endpoints in high speed mode the polling interval is -//! 2 ^ (\e ui32NAKPollInterval - 1) microframes between interrupt IN requests -//! to an endpoint and has a range of 1 to 16. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval, - uint32_t ui32TargetEndpoint, uint32_t ui32Flags) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - ASSERT(ui32NAKPollInterval <= MAX_NAK_LIMIT); - - // - // Endpoint zero is configured differently than the other endpoints, so see - // if this is endpoint zero. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Set the NAK timeout. - // - HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval; - - // - // Set the transfer type information. - // - // - // Set the speed of this endpoint. - // - if(ui32Flags & USB_EP_SPEED_HIGH) - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_HIGH; - } - else if(ui32Flags & USB_EP_SPEED_FULL) - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; - } - else - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; - } - } - else - { - // - // Start with the target endpoint. - // - ui32Register = ui32TargetEndpoint; - - // - // Set the speed for the device using this endpoint. - // - if(ui32Flags & USB_EP_SPEED_HIGH) - { - ui32Register |= USB_TXTYPE1_SPEED_HIGH; - } - else if(ui32Flags & USB_EP_SPEED_FULL) - { - ui32Register |= USB_TXTYPE1_SPEED_FULL; - } - else - { - ui32Register |= USB_TXTYPE1_SPEED_LOW; - } - - // - // Set the protocol for the device using this endpoint. - // - switch(ui32Flags & USB_EP_MODE_MASK) - { - // - // The bulk protocol is being used. - // - case USB_EP_MODE_BULK: - { - ui32Register |= USB_TXTYPE1_PROTO_BULK; - break; - } - - // - // The isochronous protocol is being used. - // - case USB_EP_MODE_ISOC: - { - ui32Register |= USB_TXTYPE1_PROTO_ISOC; - break; - } - - // - // The interrupt protocol is being used. - // - case USB_EP_MODE_INT: - { - ui32Register |= USB_TXTYPE1_PROTO_INT; - break; - } - - // - // The control protocol is being used. - // - case USB_EP_MODE_CTRL: - { - ui32Register |= USB_TXTYPE1_PROTO_CTRL; - break; - } - } - - // - // See if the transmit or receive endpoint is being configured. - // - if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Set the transfer type information. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) = - ui32Register; - - // - // Set the NAK timeout or polling interval. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) = - ui32NAKPollInterval; - - // - // Set the Maximum Payload per transaction. - // - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = - ui32MaxPayload; - - // - // Set the transmit control value to zero. - // - ui32Register = 0; - - // - // Allow auto setting of TxPktRdy when max packet size has been - // loaded into the FIFO. - // - if(ui32Flags & USB_EP_AUTO_SET) - { - ui32Register |= USB_TXCSRH1_AUTOSET; - } - - // - // Configure the DMA Mode. - // - if(ui32Flags & USB_EP_DMA_MODE_1) - { - ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; - } - else if(ui32Flags & USB_EP_DMA_MODE_0) - { - ui32Register |= USB_TXCSRH1_DMAEN; - } - - // - // Write out the transmit control value. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = - (uint8_t)ui32Register; - } - else - { - // - // Set the transfer type information. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) = - ui32Register; - - // - // Set the NAK timeout or polling interval. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) = - ui32NAKPollInterval; - - // - // Set the Maximum Payload per transaction. - // - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = - ui32MaxPayload; - - // - // Set the receive control value to zero. - // - ui32Register = 0; - - // - // Allow auto clearing of RxPktRdy when packet of size max packet - // has been unloaded from the FIFO. - // - if(ui32Flags & USB_EP_AUTO_CLEAR) - { - ui32Register |= USB_RXCSRH1_AUTOCL; - } - - // - // Allow auto generation of DMA requests. - // - if(ui32Flags & USB_EP_AUTO_REQUEST) - { - ui32Register |= USB_RXCSRH1_AUTORQ; - } - - // - // Configure the DMA Mode. - // - if(ui32Flags & USB_EP_DMA_MODE_1) - { - ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; - } - else if(ui32Flags & USB_EP_DMA_MODE_0) - { - ui32Register |= USB_RXCSRH1_DMAEN; - } - - // - // Write out the receive control value. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = - (uint8_t)ui32Register; - } - } -} - -//***************************************************************************** -// -//! Changes the speed of the connection for a host endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags are used to configure other endpoint settings. -//! -//! This function sets the USB speed for an IN or OUT endpoint in host mode. -//! The \e ui32Flags parameter specifies the speed using one of the following -//! values: \b USB_EP_SPEED_LOW, \b USB_EP_SPEED_FULL, or \b USB_EP_SPEED_HIGH. -//! The \e ui32Flags parameter also specifies which direction is set by -//! adding the logical OR in either \b USB_EP_HOST_IN or \b USB_EP_HOST_OUT. -//! All other flags are ignored. This function is typically only used for -//! endpoint 0, but could be used with other endpoints as well. -//! -//! \b Example: Set host transactions on endpoint 0 to full speed.. -//! -//! \verbatim -//! // -//! // Set host endpoint 0 transactions to full speed. -//! // -//! USBHostEndpointSpeed(USB0_BASE, USB_EP_0, USB_EP_SPEED_FULL); -//! \endverbatim -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - uint32_t ui32Reg; - uint32_t ui32Speed; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Create the register speed value. - // - if(ui32Flags & USB_EP_SPEED_HIGH) - { - ui32Speed = USB_TYPE0_SPEED_HIGH; - } - else if(ui32Flags & USB_EP_SPEED_FULL) - { - ui32Speed = USB_TYPE0_SPEED_FULL; - } - else - { - ui32Speed = USB_TYPE0_SPEED_LOW; - } - - // - // Endpoint 0 is handled differently as it is bi-directional. - // - if(ui32Endpoint == USB_EP_0) - { - HWREGB(ui32Base + USB_O_TYPE0) = ui32Speed; - } - else if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Clear the current speed and set the new speed. - // - ui32Reg = (HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) & - ~(USB_TXTYPE1_SPEED_M)); - ui32Reg |= ui32Speed; - - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) |= ui32Reg; - } - else - { - // - // Clear the current speed and set the new speed. - // - ui32Reg = (HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) & - ~(USB_RXTYPE1_SPEED_M)); - ui32Reg |= ui32Speed; - - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) |= ui32Reg; - } -} - -//***************************************************************************** -// -//! Sets the configuration for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32MaxPacketSize is the maximum packet size for this endpoint. -//! \param ui32Flags are used to configure other endpoint settings. -//! -//! This function sets the basic configuration for an endpoint in device mode. -//! Endpoint zero does not have a dynamic configuration, so this function -//! must not be called for endpoint zero. The \e ui32Flags parameter -//! determines some of the configuration while the other parameters provide the -//! rest. -//! -//! The \b USB_EP_MODE_ flags define what the type is for the specified endpoint. -//! -//! - \b USB_EP_MODE_CTRL is a control endpoint. -//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. -//! - \b USB_EP_MODE_BULK is a bulk endpoint. -//! - \b USB_EP_MODE_INT is an interrupt endpoint. -//! -//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the -//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA -//! controller is configured and how it is being used. See the ``Using USB -//! with the uDMA Controller'' or the ''Using the integrated USB DMA -//! Controller'' section for more information on DMA configuration depending -//! on the type of DMA that is supported by the USB controller. -//! -//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be -//! specified to cause the automatic transmission of data on the USB bus as -//! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for -//! this endpoint. This option is commonly used with DMA (both on devices -//! with integrated USB DMA as well as those that use uDMA) as no interaction -//! is required to start the transmission of data. -//! -//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is -//! specified to trigger the request for more data once the FIFO has been -//! drained enough to receive \e ui32MaxPacketSize more bytes of data. Also -//! for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the -//! data packet ready flag automatically once the data has been read from the -//! FIFO. If this option is not used, this flag must be manually cleared via a -//! call to USBDevEndpointStatusClear(). Both of these settings can be used to -//! remove the need for extra calls when using the controller with DMA. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, uint32_t ui32Flags) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); - - // - // Determine if a transmit or receive endpoint is being configured. - // - if(ui32Flags & USB_EP_DEV_IN) - { - // - // Set the maximum packet size. - // - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = - ui32MaxPacketSize; - - // - // The transmit control value is zero unless options are enabled. - // - ui32Register = 0; - - // - // Allow auto setting of TxPktRdy when max packet size has been loaded - // into the FIFO. - // - if(ui32Flags & USB_EP_AUTO_SET) - { - ui32Register |= USB_TXCSRH1_AUTOSET; - } - - // - // Configure the DMA mode. - // - if(ui32Flags & USB_EP_DMA_MODE_1) - { - ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; - } - else if(ui32Flags & USB_EP_DMA_MODE_0) - { - ui32Register |= USB_TXCSRH1_DMAEN; - } - - // - // Enable isochronous mode if requested. - // - if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) - { - ui32Register |= USB_TXCSRH1_ISO; - } - - // - // Write the transmit control value. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = - (uint8_t)ui32Register; - - // - // Reset the Data toggle to zero. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) = - USB_TXCSRL1_CLRDT; - } - else - { - // - // Set the MaxPacketSize. - // - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = - ui32MaxPacketSize; - - // - // The receive control value is zero unless options are enabled. - // - ui32Register = 0; - - // - // Allow auto clearing of RxPktRdy when packet of size max packet - // has been unloaded from the FIFO. - // - if(ui32Flags & USB_EP_AUTO_CLEAR) - { - ui32Register = USB_RXCSRH1_AUTOCL; - } - - // - // Configure the DMA mode. - // - if(ui32Flags & USB_EP_DMA_MODE_1) - { - ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; - } - else if(ui32Flags & USB_EP_DMA_MODE_0) - { - ui32Register |= USB_RXCSRH1_DMAEN; - } - - // - // If requested, disable NYET responses for high-speed bulk and - // interrupt endpoints. - // - if(ui32Flags & USB_EP_DIS_NYET) - { - ui32Register |= USB_RXCSRH1_DISNYET; - } - - // - // Enable isochronous mode if requested. - // - if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) - { - ui32Register |= USB_RXCSRH1_ISO; - } - - // - // Write the receive control value. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = - (uint8_t)ui32Register; - - // - // Reset the Data toggle to zero. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) = - USB_RXCSRL1_CLRDT; - } -} - -//***************************************************************************** -// -//! Gets the current configuration for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param pui32MaxPacketSize is a pointer which is written with the maximum -//! packet size for this endpoint. -//! \param pui32Flags is a pointer which is written with the current endpoint -//! settings. On entry to the function, this pointer must contain either -//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT -//! endpoint is to be queried. -//! -//! This function returns the basic configuration for an endpoint in device -//! mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are -//! equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed -//! to USBDevEndpointConfigSet() for this endpoint. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT(pui32MaxPacketSize && pui32Flags); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); - - // - // Determine if a transmit or receive endpoint is being queried. - // - if(*pui32Flags & USB_EP_DEV_IN) - { - // - // Clear the flags other than the direction bit. - // - *pui32Flags = USB_EP_DEV_IN; - - // - // Get the maximum packet size. - // - *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + - EP_OFFSET(ui32Endpoint) + - USB_O_TXMAXP1); - - // - // Get the current transmit control register value. - // - ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + - USB_O_TXCSRH1); - - // - // Are we allowing auto setting of TxPktRdy when max packet size has - // been loaded into the FIFO? - // - if(ui32Register & USB_TXCSRH1_AUTOSET) - { - *pui32Flags |= USB_EP_AUTO_SET; - } - - // - // Get the DMA mode. - // - if(ui32Register & USB_TXCSRH1_DMAEN) - { - if(ui32Register & USB_TXCSRH1_DMAMOD) - { - *pui32Flags |= USB_EP_DMA_MODE_1; - } - else - { - *pui32Flags |= USB_EP_DMA_MODE_0; - } - } - - // - // Are we in isochronous mode? - // - if(ui32Register & USB_TXCSRH1_ISO) - { - *pui32Flags |= USB_EP_MODE_ISOC; - } - else - { - // - // The hardware doesn't differentiate between bulk, interrupt - // and control mode for the endpoint so we just set something - // that isn't isochronous. This protocol ensures that anyone - // modifying the returned flags in preparation for a call to - // USBDevEndpointConfigSet do not see an unexpected mode change. - // If they decode the returned mode, however, they may be in for - // a surprise. - // - *pui32Flags |= USB_EP_MODE_BULK; - } - } - else - { - // - // Clear the flags other than the direction bit. - // - *pui32Flags = USB_EP_DEV_OUT; - - // - // Get the MaxPacketSize. - // - *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + - EP_OFFSET(ui32Endpoint) + - USB_O_RXMAXP1); - - // - // Get the current receive control register value. - // - ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + - USB_O_RXCSRH1); - - // - // Are we allowing auto clearing of RxPktRdy when packet of size max - // packet has been unloaded from the FIFO? - // - if(ui32Register & USB_RXCSRH1_AUTOCL) - { - *pui32Flags |= USB_EP_AUTO_CLEAR; - } - - // - // Get the DMA mode. - // - if(ui32Register & USB_RXCSRH1_DMAEN) - { - if(ui32Register & USB_RXCSRH1_DMAMOD) - { - *pui32Flags |= USB_EP_DMA_MODE_1; - } - else - { - *pui32Flags |= USB_EP_DMA_MODE_0; - } - } - - // - // Are we in isochronous mode? - // - if(ui32Register & USB_RXCSRH1_ISO) - { - *pui32Flags |= USB_EP_MODE_ISOC; - } - else - { - // - // The hardware doesn't differentiate between bulk, interrupt - // and control mode for the endpoint so we just set something - // that isn't isochronous. This protocol ensures that anyone - // modifying the returned flags in preparation for a call to - // USBDevEndpointConfigSet do not see an unexpected mode change. - // If they decode the returned mode, however, they may be in for - // a surprise. - // - *pui32Flags |= USB_EP_MODE_BULK; - } - } -} - -//***************************************************************************** -// -//! Sets the FIFO configuration for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32FIFOAddress is the starting address for the FIFO. -//! \param ui32FIFOSize is the size of the FIFO specified by one of the -//! \b USB_FIFO_SZ_ values. -//! \param ui32Flags specifies what information to set in the FIFO -//! configuration. -//! -//! This function configures the starting FIFO RAM address and size of the FIFO -//! for a specified endpoint. Endpoint zero does not have a dynamically -//! configurable FIFO, so this function must not be called for endpoint zero. -//! The \e ui32FIFOSize parameter must be one of the values in the -//! \b USB_FIFO_SZ_ values. -//! -//! The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly -//! indicates the starting address in the USB controller's FIFO RAM. For -//! example, a value of 64 indicates that the FIFO starts 64 bytes into -//! the USB controller's FIFO memory. The \e ui32Flags value specifies whether -//! the endpoint's OUT or IN FIFO must be configured. If in host mode, use -//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use -//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. -//! -//! \return None. -// -//***************************************************************************** -void -USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); - - // - // See if the transmit or receive FIFO is being configured. - // - if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - // - // Set the transmit FIFO location and size for this endpoint. - // - _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOSZ, - ui32FIFOSize, 1); - _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOADD, - ui32FIFOAddress >> 3, 2); - } - else - { - // - // Set the receive FIFO location and size for this endpoint. - // - _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOSZ, - ui32FIFOSize, 1); - _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOADD, - ui32FIFOAddress >> 3, 2); - } -} - -//***************************************************************************** -// -//! Returns the FIFO configuration for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param pui32FIFOAddress is the starting address for the FIFO. -//! \param pui32FIFOSize is the size of the FIFO as specified by one of the -//! \b USB_FIFO_SZ_ values. -//! \param ui32Flags specifies what information to retrieve from the FIFO -//! configuration. -//! -//! This function returns the starting address and size of the FIFO for a -//! specified endpoint. Endpoint zero does not have a dynamically configurable -//! FIFO, so this function must not be called for endpoint zero. The -//! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must -//! be read. If in host mode, the \e ui32Flags parameter must be -//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the -//! \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or -//! \b USB_EP_DEV_IN. -//! -//! \return None. -// -//***************************************************************************** -void -USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); - - // - // See if the transmit or receive FIFO is being configured. - // - if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - // - // Get the transmit FIFO location and size for this endpoint. - // - *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4, - (uint32_t)USB_O_TXFIFOADD, - 2)) << 3; - *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4, - (uint32_t)USB_O_TXFIFOSZ, 1); - } - else - { - // - // Get the receive FIFO location and size for this endpoint. - // - *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4, - (uint32_t)USB_O_RXFIFOADD, - 2)) << 3; - *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4, - (uint32_t)USB_O_RXFIFOSZ, 1); - } -} - -//***************************************************************************** -// -//! Configure the DMA settings for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Config specifies the configuration options for an endpoint. -//! -//! This function configures the DMA settings for a specified endpoint without -//! changing other options that may already be configured. In order for the -//! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be -//! called before starting the DMA transfer. The configuration -//! options are passed in the \e ui32Config parameter and can have the values -//! described below. -//! -//! One of the following values to specify direction: -//! - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with -//! DMA transfers from memory to the USB controller. -//! - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with -//! DMA transfers from the USB controller to memory. -//! -//! One of the following values: -//! - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for -//! transfers that do not span multiple packets or when interrupts are -//! required for each packet. -//! - \b USB_EP_DMA_MODE_1 - This setting is typically used for -//! transfers that span multiple packets and do not require interrupts -//! between packets. -//! -//! Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: -//! - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers -//! to automatically be sent when a full packet is loaded into a FIFO. -//! This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go -//! out when the FIFO becomes full and the DMA has more data to send. -//! -//! Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: -//! - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA -//! transfers to automatically be acknowledged as they are received. This is -//! needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to -//! be received and acknowledged when the FIFO is emptied by the DMA -//! transfer. -//! -//! Values only used with \b USB_EP_HOST_IN: -//! - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA -//! transfers to automatically request a new IN transaction when the -//! previous transfer has emptied the FIFO. This is typically used in -//! conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers -//! can continue without interrupting the main processor. -//! -//! \b Example: Set endpoint 1 receive endpoint to automatically acknowledge -//! request and automatically generate a new IN request in host mode. -//! -//! \verbatim -//! // -//! // Configure endpoint 1 for receiving multiple packets using DMA. -//! // -//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_1, USB_EP_HOST_IN | -//! USB_EP_DMA_MODE_1 | -//! USB_EP_AUTO_CLEAR | -//! USB_EP_AUTO_REQUEST); -//! \endverbatim -//! -//! \b Example: Set endpoint 2 transmit endpoint to automatically send each -//! packet in host mode when spanning multiple packets. -//! -//! \verbatim -//! // -//! // Configure endpoint 1 for transmitting multiple packets using DMA. -//! // -//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_2, USB_EP_HOST_OUT | -//! USB_EP_DMA_MODE_1 | -//! USB_EP_AUTO_SET); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Config) -{ - uint32_t ui32NewConfig; - - if(ui32Config & USB_EP_HOST_OUT) - { - // - // Clear mode and DMA enable. - // - ui32NewConfig = - (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) & - ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET)); - - if(ui32Config & USB_EP_DMA_MODE_1) - { - ui32NewConfig |= USB_TXCSRH1_DMAMOD; - } - - if(ui32Config & USB_EP_AUTO_SET) - { - ui32NewConfig |= USB_TXCSRH1_AUTOSET; - } - - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = - ui32NewConfig; - } - else - { - ui32NewConfig = - (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) & - ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD)); - - if(ui32Config & USB_EP_DMA_MODE_1) - { - ui32NewConfig |= USB_RXCSRH1_DMAMOD; - } - - if(ui32Config & USB_EP_AUTO_CLEAR) - { - ui32NewConfig |= USB_RXCSRH1_AUTOCL; - } - if(ui32Config & USB_EP_AUTO_REQUEST) - { - ui32NewConfig |= USB_RXCSRH1_AUTORQ; - } - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = - ui32NewConfig; - } -} - -//***************************************************************************** -// -//! Enable DMA on a specified endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags specifies which direction and what mode to use when -//! enabling DMA. -//! -//! This function enables DMA on a specified endpoint and configures the mode -//! according to the values in the \e ui32Flags parameter. The \e ui32Flags -//! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this -//! function is called the only DMA or error interrupts are generated by the -//! USB controller. -//! -//! \note If this function is called when an endpoint is configured in DMA -//! mode 0 the USB controller does not generate an interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // See if the transmit DMA is being enabled. - // - if(ui32Flags & USB_EP_DEV_IN) - { - // - // Enable DMA on the transmit endpoint. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |= - USB_TXCSRH1_DMAEN; - } - else - { - // - // Enable DMA on the receive endpoint. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |= - USB_RXCSRH1_DMAEN; - } -} - -//***************************************************************************** -// -//! Disable DMA on a specified endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags specifies which direction to disable. -//! -//! This function disables DMA on a specified endpoint to allow non-DMA USB -//! transactions to generate interrupts normally. The \e ui32Flags parameter -//! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. -//! -//! \return None. -// -//***************************************************************************** -void -USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // If this was a request to disable DMA on the IN portion of the endpoint - // then handle it. - // - if(ui32Flags & USB_EP_DEV_IN) - { - // - // Just disable DMA leave the mode setting. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &= - ~USB_TXCSRH1_DMAEN; - } - else - { - // - // Just disable DMA leave the mode setting. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &= - ~USB_RXCSRH1_DMAEN; - } -} - -//***************************************************************************** -// -//! Determines the number of bytes of data available in a specified endpoint's -//! FIFO. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! -//! This function returns the number of bytes of data currently available in -//! the FIFO for the specified receive (OUT) endpoint. It may be used prior to -//! calling USBEndpointDataGet() to determine the size of buffer required to -//! hold the newly-received packet. -//! -//! \return This call returns the number of bytes available in a specified endpoint -//! FIFO. -// -//***************************************************************************** -uint32_t -USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Get the address of the receive status register to use, based on the - // endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - ui32Register = USB_O_CSRL0; - } - else - { - ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); - } - - // - // Is there a packet ready in the FIFO? - // - if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) - { - return(0); - } - - // - // Return the byte count in the FIFO. - // - return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint)); -} - -//***************************************************************************** -// -//! Retrieves data from the specified endpoint's FIFO. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param pui8Data is a pointer to the data area used to return the data from -//! the FIFO. -//! \param pui32Size is initially the size of the buffer passed into this call -//! via the \e pui8Data parameter. It is set to the amount of data returned in -//! the buffer. -//! -//! This function returns the data from the FIFO for the specified endpoint. -//! The \e pui32Size parameter indicates the size of the buffer passed in -//! the \e pui32Data parameter. The data in the \e pui32Size parameter is -//! changed to match the amount of data returned in the \e pui8Data parameter. -//! If a zero-byte packet is received, this call does not return an error but -//! instead just returns a zero in the \e pui32Size parameter. The only error -//! case occurs when there is no data packet available. -//! -//! \return This call returns 0, or -1 if no packet was received. -// -//***************************************************************************** -int32_t -USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint8_t *pui8Data, uint32_t *pui32Size) -{ - uint32_t ui32Register, ui32ByteCount, ui32FIFO; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Get the address of the receive status register to use, based on the - // endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - ui32Register = USB_O_CSRL0; - } - else - { - ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); - } - - // - // Don't allow reading of data if the RxPktRdy bit is not set. - // - if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) - { - // - // Can't read the data because none is available. - // - *pui32Size = 0; - - // - // Return a failure since there is no data to read. - // - return(-1); - } - - // - // Get the byte count in the FIFO. - // - ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint); - - // - // Determine how many bytes are copied. - // - ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; - - // - // Return the number of bytes we are going to read. - // - *pui32Size = ui32ByteCount; - - // - // Calculate the FIFO address. - // - ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); - - // - // Read the data out of the FIFO. - // - for(; ui32ByteCount > 0; ui32ByteCount--) - { - // - // Read a byte at a time from the FIFO. - // - *pui8Data++ = HWREGB(ui32FIFO); - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Acknowledge that data was read from the specified endpoint's FIFO in device -//! mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param bIsLastPacket indicates if this packet is the last one. -//! -//! This function acknowledges that the data was read from the endpoint's FIFO. -//! The \e bIsLastPacket parameter is set to a \b true value if this is the -//! last in a series of data packets on endpoint zero. The \e bIsLastPacket -//! parameter is not used for endpoints other than endpoint zero. This call -//! can be used if processing is required between reading the data and -//! acknowledging that the data has been read. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, - bool bIsLastPacket) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Determine which endpoint is being acked. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. - // - HWREGB(ui32Base + USB_O_CSRL0) = - USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0); - } - else - { - // - // Clear RxPktRdy on all other endpoints. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(USB_RXCSRL1_RXRDY); - } -} - -//***************************************************************************** -// -//! Acknowledge that data was read from the specified endpoint's FIFO in host -//! mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! -//! This function acknowledges that the data was read from the endpoint's FIFO. -//! This call is used if processing is required between reading the data and -//! acknowledging that the data has been read. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Clear RxPktRdy. - // - if(ui32Endpoint == USB_EP_0) - { - HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY; - } - else - { - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(USB_RXCSRL1_RXRDY); - } -} - -//***************************************************************************** -// -//! Puts data into the specified endpoint's FIFO. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param pui8Data is a pointer to the data area used as the source for the -//! data to put into the FIFO. -//! \param ui32Size is the amount of data to put into the FIFO. -//! -//! This function puts the data from the \e pui8Data parameter into the FIFO -//! for this endpoint. If a packet is already pending for transmission, then -//! this call does not put any of the data into the FIFO and returns -1. Care -//! must be taken to not write more data than can fit into the FIFO -//! allocated by the call to USBFIFOConfigSet(). -//! -//! \return This call returns 0 on success, or -1 to indicate that the FIFO -//! is in use and cannot be written. -// -//***************************************************************************** -int32_t -USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, - uint8_t *pui8Data, uint32_t ui32Size) -{ - uint32_t ui32FIFO; - uint8_t ui8TxPktRdy; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Get the bit position of TxPktRdy based on the endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - ui8TxPktRdy = USB_CSRL0_TXRDY; - } - else - { - ui8TxPktRdy = USB_TXCSRL1_TXRDY; - } - - // - // Don't allow transmit of data if the TxPktRdy bit is already set. - // - if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy) - { - return(-1); - } - - // - // Calculate the FIFO address. - // - ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); - - // - // Write the data to the FIFO. - // - for(; ui32Size > 0; ui32Size--) - { - HWREGB(ui32FIFO) = *pui8Data++; - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Starts the transfer of data from an endpoint's FIFO. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32TransType is set to indicate what type of data is being sent. -//! -//! This function starts the transfer of data from the FIFO for a specified -//! endpoint. This function is called if the \b USB_EP_AUTO_SET bit was -//! not enabled for the endpoint. Setting the \e ui32TransType parameter -//! allows the appropriate signaling on the USB bus for the type of transaction -//! being requested. The \e ui32TransType parameter must be one of the -//! following: -//! -//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. -//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. -//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a -//! sequence of IN transactions. -//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. -//! - \b USB_TRANS_STATUS for status results on endpoint zero. -//! -//! \return This call returns 0 on success, or -1 if a transmission is already -//! in progress. -// -//***************************************************************************** -int32_t -USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32TransType) -{ - uint32_t ui32TxPktRdy; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Get the bit position of TxPktRdy based on the endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Don't allow transmit of data if the TxPktRdy bit is already set. - // - if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY) - { - return(-1); - } - - ui32TxPktRdy = ui32TransType & 0xff; - } - else - { - // - // Don't allow transmit of data if the TxPktRdy bit is already set. - // - if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY) - { - return(-1); - } - - ui32TxPktRdy = (ui32TransType >> 8) & 0xff; - } - - // - // Set TxPktRdy in order to send the data. - // - HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy; - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Forces a flush of an endpoint's FIFO. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags specifies if the IN or OUT endpoint is accessed. -//! -//! This function forces the USB controller to flush out the data in the FIFO. -//! The function can be called with either host or device controllers and -//! requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, -//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. -//! -//! \return None. -// -//***************************************************************************** -void -USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Endpoint zero has a different register set for FIFO flushing. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Nothing in the FIFO if neither of these bits are set. - // - if((HWREGB(ui32Base + USB_O_CSRL0) & - (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) - { - // - // Hit the Flush FIFO bit. - // - HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH; - } - } - else - { - // - // Only reset the IN or OUT FIFO. - // - if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - // - // Make sure the FIFO is not empty. - // - if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) & - USB_TXCSRL1_TXRDY) - { - // - // Hit the Flush FIFO bit. - // - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_TXCSRL1_FLUSH; - } - } - else - { - // - // Make sure that the FIFO is not empty. - // - if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) & - USB_RXCSRL1_RXRDY) - { - // - // Hit the Flush FIFO bit. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_RXCSRL1_FLUSH; - } - } - } -} - -//***************************************************************************** -// -//! Schedules a request for an IN transaction on an endpoint in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! -//! This function schedules a request for an IN transaction. When the USB -//! device being communicated with responds with the data, the data can be -//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. -//! -//! \note This function must only be called in host mode and only for IN -//! endpoints. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Endpoint zero uses a different offset than the other endpoints. - // - if(ui32Endpoint == USB_EP_0) - { - ui32Register = USB_O_CSRL0; - } - else - { - ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); - } - - // - // Set the request for an IN transaction. - // - HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT; -} - -//***************************************************************************** -// -//! Clears a scheduled IN transaction for an endpoint in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! -//! This function clears a previously scheduled IN transaction if it is still -//! pending. This function is used to safely disable any scheduled IN -//! transactions if the endpoint specified by \e ui32Endpoint is reconfigured -//! for communications with other devices. -//! -//! \note This function must only be called in host mode and only for IN -//! endpoints. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Endpoint zero uses a different offset than the other endpoints. - // - if(ui32Endpoint == USB_EP_0) - { - ui32Register = USB_O_CSRL0; - } - else - { - ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); - } - - // - // Clear the request for an IN transaction. - // - HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT; -} - -//***************************************************************************** -// -//! Issues a request for a status IN transaction on endpoint zero. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function is used to cause a request for a status IN transaction from -//! a device on endpoint zero. This function can only be used with endpoint -//! zero as that is the only control endpoint that supports this ability. This -//! function is used to complete the last phase of a control transaction to a -//! device and an interrupt is signaled when the status packet has been -//! received. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostRequestStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Set the request for a status IN transaction. - // - HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; -} - -//***************************************************************************** -// -//! Sets the functional address for the device that is connected to an -//! endpoint in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Addr is the functional address for the controller to use for -//! this endpoint. -//! \param ui32Flags determines if this is an IN or an OUT endpoint. -//! -//! This function configures the functional address for a device that is using -//! this endpoint for communication. This \e ui32Addr parameter is the address -//! of the target device that this endpoint is communicating with. The -//! \e ui32Flags parameter indicates if the IN or OUT endpoint is set. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // See if the transmit or receive address is set. - // - if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Set the transmit address. - // - HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1)) = ui32Addr; - } - else - { - // - // Set the receive address. - // - HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1)) = - ui32Addr; - } -} - -//***************************************************************************** -// -//! Gets the current functional device address for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags determines if this is an IN or an OUT endpoint. -//! -//! This function returns the current functional address that an endpoint is -//! using to communicate with a device. The \e ui32Flags parameter determines -//! if the IN or OUT endpoint's device address is returned. -//! -//! \note This function must only be called in host mode. -//! -//! \return Returns the current function address being used by an endpoint. -// -//***************************************************************************** -uint32_t -USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // See if the transmit or receive address is returned. - // - if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Return this endpoint's transmit address. - // - return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1))); - } - else - { - // - // Return this endpoint's receive address. - // - return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1))); - } -} - -//***************************************************************************** -// -//! Sets the hub address for the device that is connected to an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Addr is the hub address and port for the device using this -//! endpoint. The hub address must be defined in bits 0 through 6 with the -//! port number in bits 8 through 14. -//! \param ui32Flags determines if this is an IN or an OUT endpoint. -//! -//! This function configures the hub address for a device that is using this -//! endpoint for communication. The \e ui32Flags parameter determines if the -//! device address for the IN or the OUT endpoint is configured by this call -//! and sets the speed of the downstream device. Valid values are one of -//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with -//! \b USB_EP_SPEED_LOW. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // See if the hub transmit or receive address is being set. - // - if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Set the hub transmit address and port number for this endpoint. - // - HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1)) = ui32Addr; - } - else - { - // - // Set the hub receive address and port number for this endpoint. - // - HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1)) = - ui32Addr; - } - - // - // Set the speed of communication for endpoint 0. This configuration is - // done here because it changes on a transaction-by-transaction basis for - // EP0. For other endpoints, this is set in USBHostEndpointConfig(). - // - if(ui32Endpoint == USB_EP_0) - { - if(ui32Flags & USB_EP_SPEED_FULL) - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; - } - else if(ui32Flags & USB_EP_SPEED_HIGH) - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_HIGH; - } - else - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; - } - } -} - -//***************************************************************************** -// -//! Gets the current device hub address for this endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags determines if this is an IN or an OUT endpoint. -//! -//! This function returns the current hub address that an endpoint is using -//! to communicate with a device. The \e ui32Flags parameter determines if the -//! device address for the IN or OUT endpoint is returned. -//! -//! \note This function must only be called in host mode. -//! -//! \return This function returns the current hub address being used by an -//! endpoint. -// -//***************************************************************************** -uint32_t -USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // See if the hub transmit or receive address is returned. - // - if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Return the hub transmit address for this endpoint. - // - return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1))); - } - else - { - // - // Return the hub receive address for this endpoint. - // - return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1))); - } -} - -//***************************************************************************** -// -//! Sets the configuration for USB power fault. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Flags specifies the configuration of the power fault. -//! -//! This function controls how the USB controller uses its external power -//! control pins (USBnPFLT and USBnEPEN). The flags specify the power -//! fault level sensitivity, the power fault action, and the power enable level -//! and source. -//! -//! One of the following can be selected as the power fault level sensitivity: -//! -//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin -//! being driven low. -//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin -//! being driven high. -//! -//! One of the following can be selected as the power fault action: -//! -//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault -//! detected. -//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a -//! power fault. -//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a -//! power fault. -//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a -//! power fault. -//! -//! One of the following can be selected as the power enable level and source: -//! -//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller -//! when USBHostPwrEnable() is called. -//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB -//! controller when USBHostPwrEnable() is -//! called. -//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller -//! automatically if USBOTGSessionRequest() has -//! enabled a session. -//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB -//! controller automatically if -//! USBOTGSessionRequest() has enabled a -//! session. -//! -//! When using the VBUS glitch filter, the \b USB_HOST_PWREN_FILTER can be -//! addded to ignore small, short drops in VBUS level caused by high power -//! consumption. This feature is mainly used to avoid causing VBUS errors -//! caused by devices with high in-rush current. -//! -//! \note This function must only be called on microcontrollers that support -//! host mode or OTG operation. The \b USB_HOST_PWREN_AUTOLOW and -//! \b USB_HOST_PWREN_AUTOHIGH parameters can only be specified on devices that -//! support OTG operation. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M | - USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH | - USB_EPC_EPEN_M)) == 0); - - // - // If requested, enable VBUS droop detection on parts that support this - // feature. - // - HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16; - - // - // Set the power fault configuration as specified. This configuration - // does not change whether fault detection is enabled or not. - // - HWREGH(ui32Base + USB_O_EPC) = - (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) & - ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | - USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M))); -} - -//***************************************************************************** -// -//! Enables power fault detection. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function enables power fault detection in the USB controller. If the -//! USBnPFLT pin is not in use, this function must not be used. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostPwrFaultEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Enable power fault input. - // - HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN; -} - -//***************************************************************************** -// -//! Disables power fault detection. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function disables power fault detection in the USB controller. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostPwrFaultDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Enable power fault input. - // - HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN; -} - -//***************************************************************************** -// -//! Enables the external power pin. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function enables the USBnEPEN signal, which enables an external power -//! supply in host mode operation. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostPwrEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Enable the external power supply enable signal. - // - HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE; -} - -//***************************************************************************** -// -//! Disables the external power pin. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function disables the USBnEPEN signal, which disables an external -//! power supply in host mode operation. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostPwrDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Disable the external power supply enable signal. - // - HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE; -} - -//***************************************************************************** -// -//! Gets the current frame number. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the last frame number received. -//! -//! \return The last frame number received. -// -//***************************************************************************** -uint32_t -USBFrameNumberGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Return the most recent frame number. - // - return(HWREGH(ui32Base + USB_O_FRAME)); -} - -//***************************************************************************** -// -//! Starts or ends a session. -//! -//! \param ui32Base specifies the USB module base address. -//! \param bStart specifies if this call starts or ends a session. -//! -//! This function is used in OTG mode to start a session request or end a -//! session. If the \e bStart parameter is set to \b true, then this function -//! starts a session and if it is \b false it ends a session. -//! -//! \return None. -// -//***************************************************************************** -void -USBOTGSessionRequest(uint32_t ui32Base, bool bStart) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Start or end the session as directed. - // - if(bStart) - { - HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION; - } - else - { - HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION; - } -} - -//***************************************************************************** -// -//! Returns the absolute FIFO address for a specified endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies which endpoint's FIFO address to return. -//! -//! This function returns the actual physical address of the FIFO. This -//! address is needed when the USB is going to be used with the uDMA -//! controller and the source or destination address must be set to the -//! physical FIFO address for a specified endpoint. This function can also be -//! used to provide the physical address to manually read data from an -//! endpoints FIFO. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - // - // Return the FIFO address for this endpoint. - // - return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2)); -} - -//***************************************************************************** -// -//! Returns the current operating mode of the controller. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current operating mode on USB controllers with -//! OTG or Dual mode functionality. -//! -//! For OTG controllers: -//! -//! The function returns one of the following values on OTG controllers: -//! -//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode -//! on the A-side of the cable. -//! -//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode -//! on the A-side of the cable. -//! -//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode -//! on the B-side of the cable. -//! -//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode -//! on the B-side of the cable. If an OTG session request is started with no -//! cable in place, this mode is the default. -//! -//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to -//! determine its role in the system. -//! -//! For Dual Mode controllers: -//! -//! The function returns one of the following values: -//! -//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. -//! -//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. -//! -//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as -//! either a host or device. -//! -//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, -//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, -//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or -//! \b USB_DUAL_MODE_NONE. -// -//***************************************************************************** -uint32_t -USBModeGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Checks the current mode in the USB_O_DEVCTL and returns the current - // mode. - // - // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION - // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION - // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | - // USB_DEVCTL_HOST - // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION - // USB_OTG_MODE_NONE: USB_DEVCTL_DEV - // - return(HWREGB(ui32Base + USB_O_DEVCTL) & - (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION | - USB_DEVCTL_VBUS_M)); -} - -//***************************************************************************** -// -//! Sets the DMA channel to use for a specified endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies which endpoint's FIFO address to return. -//! \param ui32Channel specifies which DMA channel to use for which endpoint. -//! -//! This function is used to configure which DMA channel to use with a specified -//! endpoint. Receive DMA channels can only be used with receive endpoints -//! and transmit DMA channels can only be used with transmit endpoints. As a -//! result, the 3 receive and 3 transmit DMA channels can be mapped to any -//! endpoint other than 0. The values that are passed into the -//! \e ui32Channel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. -//! -//! \note This function only has an effect on microcontrollers that have the -//! ability to change the DMA channel for an endpoint. Calling this function -//! on other devices has no effect. -//! -//! \return None. -//! -//***************************************************************************** -void -USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Channel) -{ - uint32_t ui32Mask; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); - ASSERT(ui32Channel <= UDMA_CHANNEL_USBEP3TX); - - // - // The input select mask must be shifted into the correct position - // based on the channel. - // - ui32Mask = 0xf << (ui32Channel * 4); - - // - // Clear out the current selection for the channel. - // - ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask); - - // - // The input select is now shifted into the correct position based on the - // channel. - // - ui32Mask |= (USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4); - - // - // Write the value out to the register. - // - HWREG(ui32Base + USB_O_DMASEL) = ui32Mask; -} - -//***************************************************************************** -// -//! Change the mode of the USB controller to host. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function changes the mode of the USB controller to host mode. -//! -//! \note This function must only be called on microcontrollers that support -//! OTG operation. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostMode(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Force mode in OTG parts that support forcing USB controller mode. - // This bit is not writable in USB controllers that do not support - // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a - // force of host mode. - // - HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG; -} - -//***************************************************************************** -// -//! Change the mode of the USB controller to device. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function changes the mode of the USB controller to device mode. -//! -//! \note This function must only be called on microcontrollers that support -//! OTG operation. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevMode(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Set the USB controller mode to device. - // - HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD; -} - -//***************************************************************************** -// -//! Changes the mode of the USB controller to OTG. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function changes the mode of the USB controller to OTG mode. This -//! function is only valid on microcontrollers that have the OTG capabilities. -//! -//! \return None. -// -//***************************************************************************** -void -USBOTGMode(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Disable the override of the USB controller mode when running on an OTG - // device. - // - HWREGB(ui32Base + USB_O_GPCS) = 0; -} - -//***************************************************************************** -// -//! Change the operating mode of the USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Mode specifies the operating mode of the USB OTG pins. -//! -//! This function changes the operating modes of the USB controller. When -//! operating in full OTG mode, the USB controller uses the VBUS and ID pins to -//! detect mode and voltage changes. While these pins are primarily used in -//! OTG mode, they can also affect the operation of host and device modes. In -//! device mode, the USB controller can be configured to monitor or ignore -//! VBUS. Monitoring VBUS allows the controller to determine if it has been -//! disconnected from the host. In host mode, the USB controller uses the -//! VBUS pin to detect loss of VBUS caused by excessive power draw due to a -//! drop in the VBUS voltage. This call takes the place of USBHostMode(), -//! USBDevMode(), and USBOTGMode(). The \e ui32Mode value should be one of -//! the following values: -//! -//! - \b USB_MODE_OTG enables operating in full OTG mode, VBUS and ID are -//! used by the controller. -//! - \b USB_MODE_HOST enables operating only as a host with no monitoring of -//! VBUS or ID pins. -//! - \b USB_MODE_HOST_VBUS enables operating only as a host with monitoring of -//! VBUS pin. This configuration enables detection of VBUS droop while still -//! forcing host mode. -//! - \b USB_MODE_DEVICE enables operating only as a device with no monitoring -//! of VBUS or ID pins. -//! - \b USB_MODE_DEVICE_VBUS enables operating only as a device with -//! monitoring of VBUS pin. This configuration enables disconnect detection -//! while still forcing device mode. -//! -//! \note Some of the options above are not available on some Tiva devices. -//! Please check the data sheet to determine if the USB controller supports a -//! particular mode. -//! -//! \b Example: Force device mode but allow monitoring of the USB VBUS pin. -//! -//! \verbatim -//! // -//! // Force device mode but allow monitoring of VBUS for disconnect. -//! // -//! USBModeConfig(USB_MODE_DEVICE_VBUS); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -USBModeConfig(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - HWREG(ui32Base + USB_O_GPCS) = ui32Mode; -} - -//***************************************************************************** -// -//! Powers off the internal USB PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function powers off the internal USB PHY, reducing the current -//! consumption of the device. While in the powered-off state, the USB -//! controller is unable to operate. -//! -//! \return None. -// -//***************************************************************************** -void -USBPHYPowerOff(uint32_t ui32Base) -{ - // - // Set the PWRDNPHY bit in the PHY, putting it into its low power mode. - // - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY; -} - -//***************************************************************************** -// -//! Powers on the internal USB PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function powers on the internal USB PHY, enabling it return to normal -//! operation. By default, the PHY is powered on, so this function must -//! only be called if USBPHYPowerOff() has previously been called. -//! -//! \return None. -// -//***************************************************************************** -void -USBPHYPowerOn(uint32_t ui32Base) -{ - // - // Clear the PWRDNPHY bit in the PHY, putting it into normal operating - // mode. - // - HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; -} - -//***************************************************************************** -// -//! Sets the number of packets to request when transferring multiple bulk -//! packets. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint index to target for this write. -//! \param ui32Count is the number of packets to request. -//! -//! This function sets the number of consecutive bulk packets to request -//! when transferring multiple bulk packets with DMA. -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Count) -{ - HWREG(ui32Base + USB_O_RQPKTCOUNT1 + - (0x4 * (USBEPToIndex(ui32Endpoint) - 1))) = ui32Count; -} - -//***************************************************************************** -// -//! Returns the number of USB endpoint pairs on the device. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the number of endpoint pairs supported by the USB -//! controller corresponding to the passed base address. The value returned is -//! the number of IN or OUT endpoints available and does not include endpoint 0 -//! (the control endpoint). For example, if 15 is returned, there are 15 IN -//! and 15 OUT endpoints available in addition to endpoint 0. -//! -//! \return Returns the number of IN or OUT endpoints available. -// -//***************************************************************************** -uint32_t -USBNumEndpointsGet(uint32_t ui32Base) -{ - // - // Read the number of endpoints from the hardware. The number of TX and - // RX endpoints are always the same. - // - return(HWREGB(ui32Base + USB_O_EPINFO) & USB_EPINFO_TXEP_M); -} - -//***************************************************************************** -// -//! Returns the version of the USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the version number of the USB controller, which can -//! be be used to adjust for slight differences between the USB controllers in -//! the Tiva family. The values that are returned are -//! \b USB_CONTROLLER_VER_0 and \b USB_CONTROLLER_VER_1. -//! -//! \note The most significant difference between \b USB_CONTROLLER_VER_0 and -//! \b USB_CONTROLLER_VER_1 is that \b USB_CONTROLLER_VER_1 supports the USB -//! controller's own bus master DMA controller, while the -//! \b USB_CONTROLLER_VER_0 only supports using the uDMA controller with the -//! USB module. -//! -//! \b Example: Get the version of the Tiva USB controller. -//! -//! \verbatim -//! uint32_t ui32Version; -//! -//! // -//! // Retrieve the version of the Tiva USB controller. -//! // -//! ui32Version = USBControllerVersion(USB0_BASE); -//! \endverbatim -//! -//! \return This function returns one of the \b USB_CONTROLLER_VER_ values. -// -//***************************************************************************** -uint32_t -USBControllerVersion(uint32_t ui32Base) -{ - // - // Return the type field of the peripheral properties. This returns - // zero for all parts that did not have a peripheral property. - // - return(HWREG(ui32Base + USB_O_PP) & USB_PP_TYPE_M); -} - -//***************************************************************************** -// -//! Configures and enables the clocking to the USB controller's PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Div specifies the divider for the internal USB PHY clock. -//! \param ui32Flags configures the internal USB PHY clock and specifies the -//! clock source for a ULPI-connected PHY. -//! -//! This function configures and enables the USB PHY clock. In addition, for -//! systems that use a ULPI-connected external PHY, this function configures -//! the source for the PHY clock. The \e ui32Flags parameter specifies the -//! clock source with the following values: -//! -//! - \b USB_CLOCK_INTERNAL uses the internal PLL combined with the \e ui32Div -//! value to generate the USB clock that is used by the internal USB PHY. In -//! addition, when using an external ULPI-connected USB PHY, the specified -//! clock is output on the USB0CLK pin. -//! - \b USB_CLOCK_EXTERNAL specifies that USB0CLK is an input from the -//! ULPI-connected external PHY. -//! -//! The \e ui32Div parameter is used to specify a divider for the internal -//! clock if the \b USB_CLOCK_INTERNAL is specified and is ignored if -//! \b USB_CLOCK_EXTERNAL is specified. When the \b USB_CLOCK_INTERNAL is -//! specified, the \e ui32Div value must be set so that the PLL_VCO/\e ui32Div -//! results in a 60-MHz clock. -//! -//! \b Example: Enable the USB clock with a 480-MHz PLL setting. -//! -//! \verbatim -//! // -//! // Enable the USB clock using a 480-MHz PLL. -//! // (480-MHz/8 = 60-MHz) -//! // -//! USBClockEnable(USB0_BASE, 8, USB_CLOCK_INTERNAL); -//! \endverbatim -//! -//! \note The ability to configure the USB PHY clock is not available on -//! all Tiva devices. Please consult the data sheet for the Tiva -//! device that you are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBClockEnable(uint32_t ui32Base, uint32_t ui32Div, uint32_t ui32Flags) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Configure and enable the USB clock input. - // - HWREG(ui32Base + USB_O_CC) = (ui32Div - 1) | ui32Flags; -} - -//***************************************************************************** -// -//! Disables the clocking of the USB controller's PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function disables the USB PHY clock. This function should not be -//! called in applications where the USB controller is used. -//! -//! \b Example: Disable the USB PHY clock input. -//! -//! \verbatim -//! // -//! // Disable clocking of the USB controller's PHY. -//! // -//! USBClockDisable(USB0_BASE); -//! \endverbatim -//! -//! \note The ability to configure the USB PHY clock is not available on all -//! Tiva devices. Please consult the data sheet for the Tiva device -//! that you are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBClockDisable(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Disable the USB clock input. - // - HWREG(ui32Base + USB_O_CC) = 0; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** -//***************************************************************************** -// -//! \addtogroup usb_dma -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -//! Enable interrupts for a specified integrated USB DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel interrupt to enable. -//! -//! This function enables the USB DMA channel interrupt based on the -//! \e ui32Channel parameter. The \e ui32Channel value is a zero-based -//! index of the USB DMA channel. Once enabled, the USBDMAChannelIntStatus() -//! function returns if a DMA channel has generated an interrupt. -//! -//! \b Example: Enable the USB DMA channel 3 interrupt. -//! -//! \verbatim -//! // -//! // Enable the USB DMA channel 3 interrupt -//! // -//! USBDMAChannelIntEnable(USB0_BASE, 3); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelIntEnable(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Enable the specified DMA channel interrupts. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) |= USB_DMACTL0_IE; -} - -//***************************************************************************** -// -//! Disable interrupts for a specified integrated USB DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which USB DMA channel interrupt to disable. -//! -//! This function disables the USB DMA channel interrupt based on the -//! \e ui32Channel parameter. The \e ui32Channel value is a zero-based -//! index of the USB DMA channel. -//! -//! \b Example: Disable the USB DMA channel 3 interrupt. -//! -//! \verbatim -//! // -//! // Disable the USB DMA channel 3 interrupt -//! // -//! USBDMAChannelIntDisable(USB0_BASE, 3); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelIntDisable(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Enable the specified DMA channel interrupts. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= ~USB_DMACTL0_IE; -} - -//***************************************************************************** -// -//! Return the current status of the integrated USB DMA interrupts. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current bit-mapped interrupt status for all USB -//! DMA channel interrupt sources. Calling this function automatically clears -//! all currently pending USB DMA interrupts. -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \b Example: Get the pending USB DMA interrupts. -//! -//! \verbatim -//! uint32_t ui32Ints; -//! -//! // -//! // Get the pending USB DMA interrupts. -//! // -//! ui32Ints = USBDMAChannelIntStatus(USB0_BASE); -//! \endverbatim -//! -//! \return The bit-mapped interrupts for the DMA channels. -// -//***************************************************************************** -uint32_t -USBDMAChannelIntStatus(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - return(HWREG(ui32Base + USB_O_DMAINTR)); -} - -//***************************************************************************** -// -//! Enables integrated USB DMA for a specified channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies the USB DMA channel to enable. -//! -//! This function enables the USB DMA channel passed in the \e ui32Channel -//! parameter. The \e ui32Channel value is a zero-based index of the USB DMA -//! channel. -//! -//! \b Example: Enable USB DMA channel 2. -//! -//! \verbatim -//! // -//! // Enable USB DMA channel 2. -//! // -//! USBDMAChannelEnable(2); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelEnable(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Enable the USB DMA channel. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) |= - USB_DMACTL0_ENABLE; -} - -//***************************************************************************** -// -//! Disables integrated USB DMA for a specified channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies the USB DMA channel to disable. -//! -//! This function disables the USB DMA channel passed in the \e ui32Channel -//! parameter. The \e ui32Channel parameter is a zero-based index of the DMA -//! channel. -//! -//! \b Example: Disable USB DMA channel 2. -//! -//! \verbatim -//! // -//! // Disable USB DMA channel 2. -//! // -//! USBDMAChannelDisable(2); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelDisable(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Disable the USB DMA channel. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= - ~USB_DMACTL0_ENABLE; -} - -//***************************************************************************** -// -//! Assigns and configures an endpoint to a specified integrated USB DMA -//! channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to access. -//! \param ui32Endpoint is the endpoint to assign to the USB DMA channel. -//! \param ui32Config is used to specify the configuration of the USB DMA -//! channel. -//! -//! This function assigns an endpoint and configures the settings for a -//! USB DMA channel. The \e ui32Endpoint parameter is one of the -//! \b USB_EP_* values and the \e ui32Channel value is a zero-based index of -//! the DMA channel to configure. The \e ui32Config parameter is a combination -//! of the \b USB_DMA_CFG_* values using the following guidelines. -//! -//! Use one of the following to set the DMA burst mode: -//! - \b USB_DMA_CFG_BURST_NONE disables bursting. -//! - \b USB_DMA_CFG_BURST_4 sets the DMA burst size to 4 words. -//! - \b USB_DMA_CFG_BURST_8 sets the DMA burst size to 8 words. -//! - \b USB_DMA_CFG_BURST_16 sets the DMA burst size to 16 words. -//! -//! Use one of the following to set the DMA mode: -//! - \b USB_DMA_CFG_MODE_0 is typically used when only a single packet is -//! being sent via DMA and triggers one completion interrupt per packet. -//! - \b USB_DMA_CFG_MODE_1 is typically used when multiple packets are being -//! sent via DMA and triggers one completion interrupt per transfer. -//! -//! Use one of the following to set the direction of the transfer: -//! - \b USB_DMA_CFG_DIR_RX selects a DMA transfer from the endpoint to a -//! memory location. -//! - \b USB_DMA_CFG_DIR_TX selects a DMA transfer to the endpoint from a -//! memory location. -//! -//! The following two optional settings allow an application to immediately -//! enable the DMA transfer and/or DMA interrupts when configuring the DMA -//! channel: -//! - \b USB_DMA_CFG_INT_EN enables interrupts for this channel immediately so -//! that an added call to USBDMAChannelIntEnable() is not necessary. -//! - \b USB_DMA_CFG_EN enables the DMA channel immediately so that an added -//! call to USBDMAChannelEnable() is not necessary. -//! -//! \b Example: Assign channel 0 to endpoint 1 in DMA mode 0, 4 word burst, -//! enable interrupts and immediately enable the transfer. -//! -//! \verbatim -//! // -//! // Assign channel 0 to endpoint 1 in DMA mode 0, 4 word bursts, -//! // enable interrupts and immediately enable the transfer. -//! // -//! USBDMAChannelConfigSet(USB0_BASE, 0, USB_EP_1, -//! (USB_DMA_CFG_BURST_4 | USB_DMA_CFG_MODE0 | -//! USB_DMA_CFG_DIR_RX | USB_DMA_CFG_INT_EN | -//! USB_DMA_CFG_EN)); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelConfigSet(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Endpoint, uint32_t ui32Config) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - ASSERT((ui32Endpoint & ~USB_EP_7) == 0); - - // - // Reset this USB DMA channel. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) = 0; - - // - // Set the configuration of the requested channel. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) = - ui32Config | ui32Endpoint; -} - -//***************************************************************************** -// -//! Returns the current status for an integrated USB DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to query. -//! -//! This function returns the current status for the USB DMA channel specified -//! by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based -//! index of the USB DMA channel to query. -//! -//! \b Example: Get the current USB DMA status for channel 2. -//! -//! \verbatim -//! uint32_t ui32Status; -//! -//! // -//! // Get the current USB DMA status for channel 2. -//! // -//! ui32Status = USBDMAChannelStatus(USB0_BASE, 2); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return Returns zero or \b USB_DMACTL0_ERR if there is a pending error -//! condition on a DMA channel. -// -//***************************************************************************** -uint32_t -USBDMAChannelStatus(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Return a non-zero value if there is a pending error condition. - // - return(HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) & - USB_DMACTL0_ERR); -} - -//***************************************************************************** -// -//! Clears the integrated USB DMA status for a specified channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to clear. -//! \param ui32Status holds the status bits to clear. -//! -//! This function clears the USB DMA channel status for the channel specified -//! by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based -//! index of the USB DMA channel to query. The \e ui32Status parameter -//! specifies the status bits to clear and must be the valid values that are -//! returned from a call to the USBDMAChannelStatus() function. -//! -//! \b Example: Clear the current USB DMA status for channel 2. -//! -//! \verbatim -//! // -//! // Clear the any pending USB DMA status for channel 2. -//! // -//! USBDMAChannelStatusClear(USB0_BASE, 2, USBDMAChannelStatus(USB0_BASE, 2)); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelStatusClear(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Status) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // The only status is the error bit. - // - ui32Status &= USB_DMACTL0_ERR; - - // - // Clear the specified error condition. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= ~ui32Status; -} - -//***************************************************************************** -// -//! Sets the source or destination address for an integrated USB DMA transfer -//! on a specified channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to configure. -//! \param pvAddress specifies the source or destination address for the USB -//! DMA transfer. -//! -//! This function sets the source or destination address for the USB DMA -//! channel number specified in the \e ui32Channel parameter. The -//! \e ui32Channel value is a zero-based index of the USB DMA channel. The -//! \e pvAddress parameter is a source address if the transfer type for the DMA -//! channel is transmit and a destination address if the transfer type is -//! receive. -//! -//! \b Example: Set the transfer address for USB DMA channel 1. -//! -//! \verbatim -//! void *pvBuffer; -//! -//! // -//! // Set the address for USB DMA channel 1. -//! // -//! USBDMAChannelAddressSet(USB0_BASE, 1, pvBuffer); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelAddressSet(uint32_t ui32Base, uint32_t ui32Channel, - void *pvAddress) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Set the DMA address. - // - HWREG(ui32Base + USB_O_DMAADDR0 + (0x10 * ui32Channel)) = - (uint32_t)pvAddress; -} - -//***************************************************************************** -// -//! Returns the source or destination address for the specified integrated USB -//! DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies the USB DMA channel. -//! -//! This function returns the DMA address for the channel number specified -//! in the \e ui32Channel parameter. The \e ui32Channel value is a zero-based -//! index of the DMA channel to query. This function must not be used on -//! devices that return \b USB_CONTROLLER_VER_0 from the USBControllerVersion() -//! function. -//! -//! \b Example: Get the transfer address for USB DMA channel 1. -//! -//! \verbatim -//! void *pvBuffer; -//! -//! // -//! // Retrieve the current DMA address for channel 1. -//! // -//! pvBuffer = USBDMAChannelAddressGet(USB0_BASE, 1); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return The current DMA address for a USB DMA channel. -// -//***************************************************************************** -void * -USBDMAChannelAddressGet(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Return the current DMA address. - // - return((void *)HWREG(ui32Base + USB_O_DMAADDR0 + (0x10 * ui32Channel))); -} - -//***************************************************************************** -// -//! Sets the transfer count for an integrated USB DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to access. -//! \param ui32Count specifies the number of bytes to transfer. -//! -//! This function sets the USB DMA transfer count in bytes for the channel -//! number specified in the \e ui32Channel parameter. The \e ui32Channel -//! value is a zero-based index of the DMA channel. -//! -//! \b Example: Set the transfer count to 512 bytes for USB DMA channel 1. -//! -//! \verbatim -//! // -//! // Set the transfer count to 512 bytes for USB DMA channel 1. -//! // -//! USBDMAChannelCountSet(USB0_BASE, 1, 512); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelCountSet(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Count) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Set the USB DMA count for the channel. - // - HWREG(ui32Base + USB_O_DMACOUNT0 + (0x10 * ui32Channel)) = ui32Count; -} - -//***************************************************************************** -// -//! Returns the transfer count for an integrated USB DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to access. -//! -//! This function returns the USB DMA transfer count in bytes for the channel -//! number specified in the \e ui32Channel parameter. The \e ui32Channel value -//! is a zero-based index of the DMA channel to query. -//! -//! \b Example: Get the transfer count for USB DMA channel 1. -//! -//! \verbatim -//! uint32_t ui32Count; -//! -//! // -//! // Get the transfer count for USB DMA channel 1. -//! // -//! ui32Count = USBDMAChannelCountGet(USB0_BASE, 1); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return The current count for a USB DMA channel. -// -//***************************************************************************** -uint32_t -USBDMAChannelCountGet(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Return the current DMA count. - // - return(HWREG(ui32Base + USB_O_DMACOUNT0 + (0x10 * ui32Channel))); -} - -//***************************************************************************** -// -//! Returns the available number of integrated USB DMA channels. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the total number of DMA channels available when using -//! the integrated USB DMA controller. This function returns 0 if the -//! integrated controller is not present. -//! -//! \b Example: Get the number of integrated DMA channels. -//! -//! \verbatim -//! uint32_t ui32Count; -//! -//! // -//! // Get the number of integrated DMA channels. -//! // -//! ui32Count = USBDMANumChannels(USB0_BASE); -//! \endverbatim -//! -//! \return The number of integrated USB DMA channels or zero if the -//! integrated USB DMA controller is not present. -// -//***************************************************************************** -uint32_t -USBDMANumChannels(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Return the number of DMA channels for the integrated DMA controller. - // - return(HWREG(ui32Base + USB_O_RAMINFO) >> USB_RAMINFO_DMACHAN_S); -} -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** -//***************************************************************************** -// -//! \addtogroup usb_ulpi -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -//! Configures the USB controller's ULPI function. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Config contains the configuration options. -//! -//! This function is used to configure the USB controller's ULPI function. -//! The configuration options are set in the \e ui32Config parameter and are a -//! logical OR of the following values: -//! -//! - \b USB_ULPI_EXTVBUS enables the external ULPI PHY as the source for VBUS -//! signaling. -//! - \b USB_ULPI_EXTVBUS_IND enables the external ULPI PHY to detect external -//! VBUS over-current condition. -//! -//! \b Example: Enable ULPI PHY with full VBUS control. -//! -//! \verbatim -//! // -//! // Enable ULPI PHY with full VBUS control. -//! // -//! USBULPIConfig(USB0_BASE, USB_ULPI_EXTVBUS | USB_ULPI_EXTVBUS_IND); -//! \endverbatim -//! -//! \note The USB ULPI feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBULPIConfig(uint32_t ui32Base, uint32_t ui32Config) -{ - HWREGB(ui32Base + USB_O_ULPIVBUSCTL) = (uint8_t)ui32Config; -} - -//***************************************************************************** -// -//! Enables the USB controller's ULPI function. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function enables the USB controller's ULPI function and must be -//! called before attempting to access an external ULPI-connected USB PHY. -//! -//! \b Example: Enable ULPI function. -//! -//! \verbatim -//! // -//! // Enable ULPI function. -//! // -//! USBULPIEnable(USB0_BASE); -//! \endverbatim -//! -//! \note The USB ULPI feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBULPIEnable(uint32_t ui32Base) -{ - HWREG(ui32Base + USB_O_PC) |= USB_PC_ULPIEN; -} - -//***************************************************************************** -// -//! Disables the USB controller's ULPI function. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function disables the USB controller's ULPI function. Accesses to -//! the external ULPI-connected PHY cannot succeed after this function has been -//! called. -//! -//! \b Example: Disable ULPI function. -//! -//! \verbatim -//! // -//! // Disable ULPI function. -//! // -//! USBULPIDisable(USB0_BASE); -//! \endverbatim -//! -//! \note The USB ULPI feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBULPIDisable(uint32_t ui32Base) -{ - HWREG(ui32Base + USB_O_PC) &= ~USB_PC_ULPIEN; -} - -//***************************************************************************** -// -//! Reads a register from an external ULPI-connected USB PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui8Reg specifies the register address to read. -//! -//! This function reads the register address specified in the \e ui8Reg -//! parameter using the ULPI function. This function is blocking and only -//! returns when the read access completes. The function does not return if -//! there is not a ULPI-connected USB PHY present. -//! -//! \b Example: Read a register from the ULPI PHY. -//! -//! \verbatim -//! uint8_t ui8Value; -//! -//! // -//! // Read a register from the ULPI PHY register at 0x10. -//! // -//! ui8Value = USBULPIRegRead(USB0_BASE, 0x10); -//! \endverbatim -//! -//! \note The USB ULPI feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return The value of the requested ULPI register. -// -//***************************************************************************** -uint8_t -USBULPIRegRead(uint32_t ui32Base, uint8_t ui8Reg) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Set the register address and initiate a read access. - // - HWREGB(ui32Base + USB_O_ULPIREGADDR) = ui8Reg; - HWREGB(ui32Base + USB_O_ULPIREGCTL) = - USB_ULPIREGCTL_RDWR | USB_ULPIREGCTL_REGACC; - - // - // Wait for the access to complete. - // - while((HWREGB(ui32Base + USB_O_ULPIREGCTL) & USB_ULPIREGCTL_REGCMPLT) == 0) - { - } - - // - // Clear the register access complete flag. - // - HWREGB(ui32Base + USB_O_ULPIREGCTL) = 0; - - return(HWREGB(ui32Base + USB_O_ULPIREGDATA)); -} - -//***************************************************************************** -// -//! Writes a value to a register on an external ULPI-connected USB PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui8Reg specifies the register address to write. -//! \param ui8Data specifies the data to write. -//! -//! This function writes the register address specified in the \e ui8Reg -//! parameter with the value specified in the \e ui8Data parameter using the -//! ULPI function. This function is blocking and only returns when the -//! write access completes. The function does not return if there is not a -//! ULPI-connected USB PHY present. -//! -//! \b Example: Write a register from the external ULPI PHY. -//! -//! \verbatim -//! // -//! // Write the ULPI PHY register at 0x10 with 0x20. -//! // -//! USBULPIRegWrite(USB0_BASE, 0x10, 0x20); -//! \endverbatim -//! -//! \note The USB ULPI feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBULPIRegWrite(uint32_t ui32Base, uint8_t ui8Reg, uint8_t ui8Data) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Set the register address and initiate a read access. - // - HWREGB(ui32Base + USB_O_ULPIREGADDR) = ui8Reg; - HWREGB(ui32Base + USB_O_ULPIREGDATA) = ui8Data; - HWREGB(ui32Base + USB_O_ULPIREGCTL) = USB_ULPIREGCTL_REGACC; - - // - // Wait for the access to complete. - // - while((HWREGB(ui32Base + USB_O_ULPIREGCTL) & USB_ULPIREGCTL_REGCMPLT) == 0) - { - } - - // - // Clear the register access complete flag. - // - HWREGB(ui32Base + USB_O_ULPIREGCTL) = 0; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** -//***************************************************************************** -// -//! \addtogroup usb_lpm -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -//! Sends an LPM request to a device at a specified address and endpoint number. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Address is the target device address for the LPM request. -//! \param ui32Endpoint is the target endpoint for the LPM request. -//! -//! This function sends an LPM request to a connected device in host mode. -//! The \e ui32Address parameter specifies the device address and has a range -//! of values from 1 to 127. The \e ui32Endpoint parameter specifies the -//! endpoint on the device to which to send the LPM request and must be one of -//! the \b USB_EP_* values. The function returns before the LPM request is -//! sent, requiring the caller to poll the USBLPMIntStatus() function or wait -//! for an interrupt to signal completion of the LPM transaction. This -//! function must only be called after the USBHostLPMConfig() has configured -//! the LPM transaction settings. -//! -//! \b Example: Send an LPM request to the device at address 1 on endpoint 0. -//! -//! \verbatim -//! // -//! // Send an LPM request to the device at address 1 on endpoint 0. -//! // -//! USBHostLPMSend(USB0_BASE, 1, USB_EP_0); -//! \endverbatim -//! -//! \note This function must only be called in host mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostLPMSend(uint32_t ui32Base, uint32_t ui32Address, uint32_t ui32Endpoint) -{ - uint32_t ui32Reg; - - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Address < 127); - - // - // Set the address and endpoint. - // - HWREGB(ui32Base + USB_O_LPMFADDR) = ui32Address; - - ui32Reg = HWREGH(ui32Base + USB_O_LPMATTR) & ~USB_LPMATTR_ENDPT_M; - ui32Reg |= (USBEPToIndex(ui32Endpoint) << USB_LPMATTR_ENDPT_S); - - HWREGH(ui32Base + USB_O_LPMATTR) = ui32Reg; - - // - // Send the LPM transaction. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_TXLPM; -} - -//***************************************************************************** -// -//! Sets the global configuration for all LPM requests. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32ResumeTime specifies the resume signaling duration in 75us -//! increments. -//! \param ui32Config specifies the combination of configuration options for -//! LPM transactions. -//! -//! This function sets the global configuration options for LPM transactions -//! and must be called at least once before ever calling USBHostLPMSend(). The -//! \e ui32ResumeTime specifies the length of time that the host drives resume -//! signaling on the bus in microseconds. The valid values -//! for \e ui32ResumeTime are from 50us to 1175us in 75us increments. The -//! remaining configuration is specified by the \e ui32Config parameter and -//! includes the following options: -//! -//! - \b USB_HOST_LPM_RMTWAKE allows the device to signal a remote wake from -//! the LPM state. -//! - \b USB_HOST_LPM_L1 is the LPM mode to enter and must always be included -//! in the configuration. -//! -//! \b Example: Set the LPM configuration to allow remote wake with a resume -//! duration of 500us. -//! -//! \verbatim -//! // -//! // Set the LPM configuration to allow remote wake with a resume -//! // duration of 500us. -//! // -//! USBHostLPMConfig(USB0_BASE, 500, USB_HOST_LPM_RMTWAKE | USB_HOST_LPM_L1); -//! \endverbatim -//! -//! \note This function must only be called in host mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostLPMConfig(uint32_t ui32Base, uint32_t ui32ResumeTime, - uint32_t ui32Config) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32ResumeTime <= 1175); - ASSERT(ui32ResumeTime >= 50); - - // - // Set the Host Initiated Resume Duration, Remote wake and Suspend mode. - // - HWREGH(ui32Base + USB_O_LPMATTR) = - ui32Config | ((ui32ResumeTime - 50) / 75) << USB_LPMATTR_HIRD_S; -} - -//***************************************************************************** -// -//! Initiates resume signaling to wake a device from LPM suspend mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! In host mode, this function initiates resume signaling to wake a device -//! that has entered an LPM-triggered low power mode. This LPM-triggered low -//! power mode is entered when the USBHostLPMSend() is called to put a specific -//! device into a low power state. -//! -//! \b Example: Initiate resume signaling. -//! -//! \verbatim -//! // -//! // Initiate resume signaling. -//! // -//! USBHostLPMResume(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in host mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostLPMResume(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Send Resume signaling. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_RES; -} - -//***************************************************************************** -// -//! Initiates remote wake signaling to request the device to leave LPM -//! suspend mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function initiates remote wake signaling to request that the host -//! wake a device that has entered an LPM-triggered low power mode. -//! -//! \b Example: Initiate remote wake signaling. -//! -//! \verbatim -//! // -//! // Initiate remote wake signaling. -//! // -//! USBDevLPMRemoteWake(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in device mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevLPMRemoteWake(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Send remote wake signaling. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_RES; -} - -//***************************************************************************** -// -//! Configures the USB device mode response to LPM requests. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Config is the combination of configuration options for LPM -//! transactions in device mode. -//! -//! This function sets the global configuration options for LPM -//! transactions in device mode and must be called before ever calling -//! USBDevLPMEnable() to set the configuration for LPM transactions. The -//! configuration options in device mode are specified in the \e ui32Config -//! parameter and include one of the following: -//! -//! - \b USB_DEV_LPM_NONE disables the USB controller from responding to LPM -//! transactions. -//! - \b USB_DEV_LPM_EN enables the USB controller to respond to LPM -//! and extended transactions. -//! - \b USB_DEV_LPM_EXTONLY enables the USB controller to respond to -//! extended transactions, but not LPM transactions. -//! -//! The \e ui32Config option can also optionally include the -//! \b USB_DEV_LPM_NAK value to cause the USB controller to NAK all -//! transactions other than an LPM transaction once the USB controller is in -//! LPM suspend mode. If this value is not included in the \e ui32Config -//! parameter, the USB controller does not respond in suspend mode. -//! -//! The USB controller does not enter LPM suspend mode until the application -//! calls the USBDevLPMEnable() function. -//! -//! \b Example: Enable LPM transactions and NAK while in LPM suspend mode. -//! -//! \verbatim -//! // -//! // Enable LPM transactions and NAK while in LPM suspend mode. -//! // -//! USBDevLPMConfig(USB0_BASE, USB_DEV_LPM_NAK | USB_DEV_LPM_EN); -//! \endverbatim -//! -//! \note This function must only be called in device mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevLPMConfig(uint32_t ui32Base, uint32_t ui32Config) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Set the device LPM configuration. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Enables the USB controller to respond to LPM suspend requests. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function is used to automatically respond to an LPM sleep request from -//! the USB host controller. If there is no data pending in any transmit -//! FIFOs, then the USB controller acknowledges the packet and enters the -//! LPM L1 state and generates the \b USB_INTLPM_ACK interrupt. If the USB -//! controller has pending transmit data in at least one FIFO, then the USB -//! controller responds with NYET and signals the \b USB_INTLPM_INCOMPLETE or -//! \b USB_INTLPM_NYET depending on if data is pending in receive or transmit -//! FIFOs. A call to USBDevLPMEnable() is required after every -//! LPM resume event to re-enable LPM mode. -//! -//! \b Example: Enable LPM suspend mode. -//! -//! \verbatim -//! // -//! // Enable LPM suspend mode. -//! // -//! USBDevLPMEnable(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in device mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevLPMEnable(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Enable L1 mode on the next LPM transaction. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) |= - USB_LPMCNTRL_EN_LPMEXT | USB_LPMCNTRL_TXLPM; -} - -//***************************************************************************** -// -//! Disables the USB controller from responding to LPM suspend requests. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function disables the USB controller from responding to LPM -//! transactions. When the device enters LPM L1 mode, the USB controller -//! automatically disables responding to further LPM transactions. -//! -//! \note If LPM transactions were enabled before calling this function, then -//! an LPM request can still occur before this function returns. As a result, -//! the application must continue to handle LPM requests until this function -//! returns. -//! -//! \b Example: Disable LPM suspend mode. -//! -//! \verbatim -//! // -//! // Disable LPM suspend mode. -//! // -//! USBDevLPMDisable(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in device mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevLPMDisable(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Disable auto entering L1 mode on LPM transactions. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) &= ~USB_LPMCNTRL_TXLPM; -} - -//***************************************************************************** -// -//! Returns the current link state setting. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current link state setting for the USB -//! controller. When the controller is operating as a host, this link -//! state is sent with an LPM request. When the controller is acting -//! as a device, this link state was received by the last LPM transaction -//! whether it was acknowledged or stalled because the requested -//! LPM mode is not supported. -//! -//! \b Example: Get the link state for the last LPM transaction. -//! -//! \verbatim -//! uint32_t ui32LinkState; -//! -//! // -//! // Get the endpoint number that received the LPM request. -//! // -//! ui32LinkState = USBLPMLinkStateGet(USB0_BASE); -//! -//! // -//! // Check if this was a supported link state. -//! // -//! if(ui32LinkState == USB_HOST_LPM_L1) -//! { -//! // -//! // Handle the supported L1 link state. -//! // -//! } -//! else -//! { -//! // -//! // Handle the unsupported link state. -//! // -//! } -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return The current LPM link state. -// -//***************************************************************************** -uint32_t -USBLPMLinkStateGet(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - return(HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_LS_M); -} - -//***************************************************************************** -// -//! Returns the current LPM endpoint value. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current LPM endpoint value. The meaning of the -//! value depends on the mode of operation of the USB controller. When in -//! device mode, the value returned is the endpoint that received the last -//! LPM transaction. When in host mode this is the endpoint that was last -//! sent an LPM transaction, or the endpoint that is configured to be sent when -//! the LPM transaction is triggered. The value returned is in the -//! \b USB_EP_[0-7] value and a direct endpoint index. -//! -//! \b Example: Get the endpoint for the last LPM transaction. -//! -//! \verbatim -//! uint32_t ui32Endpoint; -//! -//! // -//! // Get the endpoint number that received the LPM request. -//! // -//! ui32LinkState = USBLPMEndpointGet(USB0_BASE); -//! -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. Please -//! consult the data sheet for the Tiva device that you are using to determine -//! if this feature is available. -//! -//! \return The last endpoint to receive an LPM request in device mode or the -//! endpoint that the host sends an LPM request as one of the \b USB_EP_[0-7] -//! values. -// -//***************************************************************************** -uint32_t -USBLPMEndpointGet(uint32_t ui32Base) -{ - uint32_t ui32Endpoint; - - ASSERT(ui32Base == USB0_BASE); - - ui32Endpoint = (HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_ENDPT_M) >> - USB_LPMATTR_ENDPT_S; - - return(IndexToUSBEP(ui32Endpoint)); -} - -//***************************************************************************** -// -//! Returns if remote wake is currently enabled. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current state of the remote wake setting for host -//! or device mode operation. If the controller is acting as a host this -//! returns the current setting that is sent to devices when LPM requests are -//! sent to a device. If the controller is in device mode, this function -//! returns the state of the last LPM request sent from the host and indicates -//! if the host enabled remote wakeup. -//! -//! \b Example: Issue remote wake if remote wake is enabled. -//! -//! \verbatim -//! -//! if(USBLPMRemoteWakeEnabled(USB0_BASE)) -//! { -//! USBDevLPMRemoteWake(USB0_BASE); -//! } -//! -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return The \b true if remote wake is enabled or \b false if it is not. -// -//***************************************************************************** -bool -USBLPMRemoteWakeEnabled(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - if(HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_RMTWAK) - { - return(true); - } - return(false); -} - -//***************************************************************************** -// -//! Returns the current LPM interrupt status. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current LPM interrupt status for the USB -//! controller. -//! -//! The valid interrupt status bits when the USB controller is acting as a host -//! are the following: -//! -//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM -//! transaction. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low -//! power state. -//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout -//! occurred or there were bit errors in the response for three attempts. -//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. -//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM -//! transaction. -//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction. -//! -//! The valid interrupt status bits when the USB controller is acting as a -//! device are the following: -//! -//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an -//! unsupported link state field. The transaction was stalled, but the -//! requested link state can still be read using the USBLPMLinkStateGet() -//! function. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low -//! power state. -//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM -//! transaction with a NYET because data was still in the transmit FIFOs. -//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and -//! is now in the LPM suspend mode. -//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction -//! with a NYET because LPM transactions are not yet enabled by a call to -//! USBDevLPMEnable(). -//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM -//! transaction. -//! -//! \note This call clears the source of all LPM status interrupts, so the -//! caller must take care to save the value returned because a subsequent call -//! to USBLPMIntStatus() does not return the previous value. -//! -//! \b Example: Get the current LPM interrupt status. -//! -//! \verbatim -//! uint32_t ui32LPMIntStatus; -//! -//! // -//! // Get the current LPM interrupt status. -//! // -//! ui32LPMIntStatus = USBLPMIntStatus(USB0_BASE); -//! -//! // -//! // Check if an LPM transaction was acknowledged. -//! // -//! if(ui32LPMIntStatus & USB_INTLPM_ACK) -//! { -//! // -//! // Handle entering LPM suspend mode. -//! // -//! ... -//! } -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return The current LPM interrupt status. -// -//***************************************************************************** -uint32_t -USBLPMIntStatus(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Return the current raw interrupt status. - // - return(HWREGB(ui32Base + USB_O_LPMRIS)); -} - -//***************************************************************************** -// -//! Enables LPM interrupts. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Ints specifies which LPM interrupts to enable. -//! -//! This function enables a set of LPM interrupts so that they can trigger a -//! USB interrupt. The \e ui32Ints parameter specifies which of the -//! \b USB_INTLPM_* to enable. -//! -//! The valid interrupt status bits when the USB controller is acting as a host -//! are the following: -//! -//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM -//! transaction. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power -//! state. -//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout -//! occurred or there were bit errors in the response for three attempts. -//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. -//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM -//! transaction. -//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction. -//! -//! The valid interrupt status bits when the USB controller is acting as a -//! device are the following: -//! -//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an -//! unsupported link state field. The transaction was stalled, but the -//! requested link state can still be read using the USBLPMLinkStateGet() -//! function. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low -//! power state. -//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM -//! transaction with a NYET because data was still in the transmit FIFOs. -//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and -//! is now in the LPM suspend mode. -//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction -//! with a NYET because LPM transactions are not yet enabled by a call to -//! USBDevLPMEnable(). -//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM -//! transaction. -//! -//! \b Example: Enable all LPM interrupt sources. -//! -//! \verbatim -//! // -//! // Enable all LPM interrupt sources. -//! // -//! USBLPMIntEnable(USB0_BASE, USB_INTLPM_ERROR | USB_INTLPM_RESUME | -//! USB_INTLPM_INCOMPLETE | USB_INTLPM_ACK | -//! USB_INTLPM_NYET | USB_INTLPM_STALL); -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBLPMIntEnable(uint32_t ui32Base, uint32_t ui32Ints) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Enable the requested interrupts. - // - HWREGB(ui32Base + USB_O_LPMIM) |= ui32Ints; -} - -//***************************************************************************** -// -//! Disables LPM interrupts. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Ints specifies which LPM interrupts to disable. -//! -//! This function disables the LPM interrupts specified in the \e ui32Ints -//! parameter, preventing them from triggering a USB interrupt. -//! -//! The valid interrupt status bits when the USB controller is acting as a host -//! are the following: -//! -//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM -//! transaction. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power -//! state. -//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout -//! occurred or there were bit errors in the response for three attempts. -//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. -//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM -//! transaction. -//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction. -//! -//! The valid interrupt status bits when the USB controller is acting as a -//! device are the following: -//! -//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an -//! unsupported link state field. The transaction was stalled, but the -//! requested link state can still be read using the USBLPMLinkStateGet() -//! function. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low -//! power state. -//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM -//! transaction with a NYET because data was still in the transmit FIFOs. -//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and -//! is now in the LPM suspend mode. -//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction -//! with a NYET because LPM transactions are not yet enabled by a call to -//! USBDevLPMEnable(). -//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM -//! transaction. -//! -//! \b Example: Disable all LPM interrupt sources. -//! -//! \verbatim -//! // -//! // Disable all LPM interrupt sources. -//! // -//! USBLPMIntDisable(USB0_BASE, USB_INTLPM_ERROR | USB_INTLPM_RESUME | -//! USB_INTLPM_INCOMPLETE | USB_INTLPM_ACK | -//! USB_INTLPM_NYET | USB_INTLPM_STALL); -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBLPMIntDisable(uint32_t ui32Base, uint32_t ui32Ints) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Disable the requested interrupts. - // - HWREGB(ui32Base + USB_O_LPMIM) &= ~ui32Ints; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/usb.h b/bsp/tm4c129x-dk/libraries/driverlib/usb.h deleted file mode 100644 index 1fed815842adf29e0e6b67382f6c7fac397388b0..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/usb.h +++ /dev/null @@ -1,658 +0,0 @@ -//***************************************************************************** -// -// usb.h - Prototypes for the USB Interface Driver. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_USB_H__ -#define __DRIVERLIB_USB_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to USBIntEnableControl() and -// USBIntDisableControl() as the ui32Flags parameter, and are returned from -// USBIntStatusControl(). -// -//***************************************************************************** -#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources -#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts -#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error -#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected -#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected -#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected -#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected -#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected -#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled -#define USB_INTCTRL_RESET 0x00000004 // Reset signaled -#define USB_INTCTRL_RESUME 0x00000002 // Resume detected -#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected -#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid -#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected - -//***************************************************************************** -// -// The following are values that can be passed to USBIntEnableEndpoint() and -// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from -// USBIntStatusEndpoint(). -// -//***************************************************************************** -#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts -#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts -#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt -#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt -#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt -#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt -#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt -#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt -#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt -#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt -#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt -#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt -#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt -#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt -#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt -#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt -#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt - -#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts -#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt - -#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts -#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt - -#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts -#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt -#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt -#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt -#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt -#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt -#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt -#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt -#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt -#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt -#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt -#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt -#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt -#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt -#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt -#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt - -#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt - -//***************************************************************************** -// -// The following are values that are returned from USBSpeedGet(). -// -//***************************************************************************** -#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined -#define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed -#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed -#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed - -//***************************************************************************** -// -// The following are values that are returned from USBEndpointStatus(). The -// USB_HOST_* values are used when the USB controller is in host mode and the -// USB_DEV_* values are used when the USB controller is in device mode. -// -//***************************************************************************** -#define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts -#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received -#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond -#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received -#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error - // (ISOC Mode) -#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the - // specified timeout period -#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a - // device -#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full -#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready -#define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts -#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the - // specified timeout period -#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device - // (ISOC mode) -#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received -#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a - // device -#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty -#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted -#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the - // specified timeout period -#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet -#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a - // device -#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received -#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready -#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous - // transfer -#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint -#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data -#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to - // a full FIFO -#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full -#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready -#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data - // to come -#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint -#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready -#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty -#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted -#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before - // Data End seen -#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint -#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending -#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready - -//***************************************************************************** -// -// The following are values that can be passed to USBHostEndpointConfig() and -// USBDevEndpointConfigSet() as the ui32Flags parameter. -// -//***************************************************************************** -#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled -#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled -#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled -#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 -#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 -#define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for - // high-speed Bulk and Interrupt - // endpoints in device mode. -#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint -#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint -#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint -#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint -#define USB_EP_MODE_MASK 0x00000300 // Mode Mask -#define USB_EP_SPEED_LOW 0x00000000 // Low Speed -#define USB_EP_SPEED_FULL 0x00001000 // Full Speed -#define USB_EP_SPEED_HIGH 0x00004000 // High Speed -#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint -#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint -#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint -#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint - -//***************************************************************************** -// -// The following are values that can be passed to USBHostPwrConfig() as the -// ui32Flags parameter. -// -//***************************************************************************** -#define USB_HOST_PWRFLT_LOW 0x00000010 -#define USB_HOST_PWRFLT_HIGH 0x00000030 -#define USB_HOST_PWRFLT_EP_NONE 0x00000000 -#define USB_HOST_PWRFLT_EP_TRI 0x00000140 -#define USB_HOST_PWRFLT_EP_LOW 0x00000240 -#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 -#define USB_HOST_PWREN_MAN_LOW 0x00000000 -#define USB_HOST_PWREN_MAN_HIGH 0x00000001 -#define USB_HOST_PWREN_AUTOLOW 0x00000002 -#define USB_HOST_PWREN_AUTOHIGH 0x00000003 -#define USB_HOST_PWREN_FILTER 0x00010000 - -//***************************************************************************** -// -// The following are the valid values that can be passed to the -// USBHostLPMConfig() function in the ui32Config parameter. -// -//***************************************************************************** -#define USB_HOST_LPM_RMTWAKE 0x00000100 -#define USB_HOST_LPM_L1 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that can be passed to the -// USBDevLPMConfig() function in the ui32Config parameter. -// -//***************************************************************************** -#define USB_DEV_LPM_NAK 0x00000010 -#define USB_DEV_LPM_NONE 0x00000000 -#define USB_DEV_LPM_EN 0x0000000c -#define USB_DEV_LPM_EXTONLY 0x00000004 - -//***************************************************************************** -// -// The following are the valid values that are returned from the -// USBLPMLinkStateGet() function. -// -//***************************************************************************** -#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 -#define USB_DEV_LPM_LS_L1 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that are passed to the USBLPMIntEnable() -// or USBLPMIntDisable() functions or are returned from the USBLPMIntStatus() -// function. -// -//***************************************************************************** -#define USB_INTLPM_ERROR 0x00000020 -#define USB_INTLPM_RESUME 0x00000010 -#define USB_INTLPM_INCOMPLETE 0x00000008 -#define USB_INTLPM_ACK 0x00000004 -#define USB_INTLPM_NYET 0x00000002 -#define USB_INTLPM_STALL 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that are passed to the USBClockEnable() -// functions. -// -//***************************************************************************** -#define USB_CLOCK_INTERNAL 0x00000200 -#define USB_CLOCK_EXTERNAL 0x00000300 - -//***************************************************************************** -// -// The configuration options used with the USBULPIConfig() API. -// -//***************************************************************************** -#define USB_ULPI_EXTVBUS 0x00000001 -#define USB_ULPI_EXTVBUS_IND 0x00000002 - -//***************************************************************************** -// -// The following are special values that can be passed to -// USBHostEndpointConfig() as the ui32NAKPollInterval parameter. -// -//***************************************************************************** -#define MAX_NAK_LIMIT 31 // Maximum NAK interval -#define DISABLE_NAK_LIMIT 0 // No NAK timeouts - -//***************************************************************************** -// -// This value specifies the maximum size of transfers on endpoint 0 as 64 -// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. -// -//***************************************************************************** -#define MAX_PACKET_SIZE_EP0 64 - -//***************************************************************************** -// -// These values are used to indicate which endpoint to access. -// -//***************************************************************************** -#define USB_EP_0 0x00000000 // Endpoint 0 -#define USB_EP_1 0x00000010 // Endpoint 1 -#define USB_EP_2 0x00000020 // Endpoint 2 -#define USB_EP_3 0x00000030 // Endpoint 3 -#define USB_EP_4 0x00000040 // Endpoint 4 -#define USB_EP_5 0x00000050 // Endpoint 5 -#define USB_EP_6 0x00000060 // Endpoint 6 -#define USB_EP_7 0x00000070 // Endpoint 7 -#define NUM_USB_EP 8 // Number of supported endpoints - -//***************************************************************************** -// -// These macros allow conversion between 0-based endpoint indices and the -// USB_EP_x values required when calling various USB APIs. -// -//***************************************************************************** -#define IndexToUSBEP(x) ((x) << 4) -#define USBEPToIndex(x) ((x) >> 4) - -//***************************************************************************** -// -// The following are values that can be passed to USBFIFOConfigSet() as the -// ui32FIFOSize parameter. -// -//***************************************************************************** -#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO -#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO -#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO -#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO -#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO -#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO -#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO -#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO -#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO - -//***************************************************************************** -// -// This macro allow conversion from a FIFO size label as defined above to -// a number of bytes -// -//***************************************************************************** -#define USBFIFOSizeToBytes(x) (8 << (x)) - -//***************************************************************************** -// -// The following are values that can be passed to USBEndpointDataSend() as the -// ui32TransType parameter. -// -//***************************************************************************** -#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction -#define USB_TRANS_IN 0x00000102 // Normal IN transaction -#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for - // endpoint 0 in device mode) -#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint - // 0) -#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint - // 0) - -//***************************************************************************** -// -// The following are values are returned by the USBModeGet function. -// -//***************************************************************************** -#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host - // mode. -#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in - // Device mode. -#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not - // set. -#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of - // the cable. -#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of - // the cable. -#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of - // the cable Session Valid. -#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of - // the cable A valid. -#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of - // the cable. -#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of - // the cable. -#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of - // the cable. -#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of - // the cable. -#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. - -//***************************************************************************** -// -// The values for the USBDMAChannelIntEnable() and USBDMAChannelIntStatus() -// APIs. -// -//***************************************************************************** -#define USB_DMA_INT_CH8 0x00000080 -#define USB_DMA_INT_CH7 0x00000040 -#define USB_DMA_INT_CH6 0x00000020 -#define USB_DMA_INT_CH5 0x00000010 -#define USB_DMA_INT_CH4 0x00000008 -#define USB_DMA_INT_CH3 0x00000004 -#define USB_DMA_INT_CH2 0x00000002 -#define USB_DMA_INT_CH1 0x00000001 - -//***************************************************************************** -// -// The values for the USBDMAChannelStatus() API. -// -//***************************************************************************** -#define USB_DMA_STATUS_ERROR 0x00000100 - -//***************************************************************************** -// -// The valid return values for the USBControllerVersion() API. -// -//***************************************************************************** -#define USB_CONTROLLER_VER_0 0x00000000 // This is for Blizzard class - // devices. -#define USB_CONTROLLER_VER_1 0x00000001 // This is for Snowflake class - // devices. - -//***************************************************************************** -// -// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or -// USBDMAChannelConfig(). -// -//***************************************************************************** -#define USB_DMA_CFG_BURST_NONE 0x00000000 -#define USB_DMA_CFG_BURST_4 0x00000200 -#define USB_DMA_CFG_BURST_8 0x00000400 -#define USB_DMA_CFG_BURST_16 0x00000600 -#define USB_DMA_CFG_INT_EN 0x00000008 -#define USB_DMA_CFG_MODE_0 0x00000000 -#define USB_DMA_CFG_MODE_1 0x00000004 -#define USB_DMA_CFG_DIR_RX 0x00000000 -#define USB_DMA_CFG_DIR_TX 0x00000002 -#define USB_DMA_CFG_EN 0x00000001 - -//***************************************************************************** -// -// The following are values that can be passed to USBModeConfig() as the -// ui3Mode parameter. -// -//***************************************************************************** -#define USB_MODE_HOST_VBUS 0x00000004 -#define USB_MODE_HOST 0x00000002 -#define USB_MODE_DEV_VBUS 0x00000005 -#define USB_MODE_DEV 0x00000003 -#define USB_MODE_OTG 0x00000000 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern uint32_t USBDevAddrGet(uint32_t ui32Base); -extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address); -extern void USBDevConnect(uint32_t ui32Base); -extern void USBDevDisconnect(uint32_t ui32Base); -extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, - uint32_t ui32Flags); -extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t *pui32MaxPacketSize, - uint32_t *pui32Flags); -extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, - bool bIsLastPacket); -extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint); -extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Config); -extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint8_t *pui8Data, uint32_t *pui32Size); -extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, - uint8_t *pui8Data, uint32_t ui32Size); -extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32TransType); -extern void USBEndpointDataToggleClear(uint32_t ui32Base, - uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Count); -extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint); -extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint); -extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t *pui32FIFOAddress, - uint32_t *pui32FIFOSize, uint32_t ui32Flags); -extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, - uint32_t ui32Flags); -extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern uint32_t USBFrameNumberGet(uint32_t ui32Base); -extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Addr, uint32_t ui32Flags); -extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, - uint32_t ui32NAKPollInterval, - uint32_t ui32TargetEndpoint, - uint32_t ui32Flags); -extern void USBHostEndpointDataAck(uint32_t ui32Base, - uint32_t ui32Endpoint); -extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, - bool bDataToggle, uint32_t ui32Flags); -extern void USBHostEndpointStatusClear(uint32_t ui32Base, - uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Addr, uint32_t ui32Flags); -extern void USBHostPwrDisable(uint32_t ui32Base); -extern void USBHostPwrEnable(uint32_t ui32Base); -extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags); -extern void USBHostPwrFaultDisable(uint32_t ui32Base); -extern void USBHostPwrFaultEnable(uint32_t ui32Base); -extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint); -extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint); -extern void USBHostRequestStatus(uint32_t ui32Base); -extern void USBHostReset(uint32_t ui32Base, bool bStart); -extern void USBHostResume(uint32_t ui32Base, bool bStart); -extern uint32_t USBHostSpeedGet(uint32_t ui32Base); -extern void USBHostSuspend(uint32_t ui32Base); -extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t USBIntStatusControl(uint32_t ui32Base); -extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base); -extern void USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void USBIntUnregister(uint32_t ui32Base); -extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart); -extern uint32_t USBModeGet(uint32_t ui32Base); -extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Channel); -extern uint32_t USBControllerVersion(uint32_t ui32Base); -extern uint32_t USBDMAChannelIntStatus(uint32_t ui32Base); -extern void USBDMAChannelConfigSet(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Endpoint, uint32_t ui32Config); -extern void USBDMAChannelAddressSet(uint32_t ui32Base, uint32_t ui32Channel, - void *pvAddress); -extern void *USBDMAChannelAddressGet(uint32_t ui32Base, uint32_t ui32Channel); -extern void USBDMAChannelCountSet(uint32_t ui32Base, uint32_t ui32Count, - uint32_t ui32Channel); -extern uint32_t USBDMAChannelCountGet(uint32_t ui32Base, uint32_t ui32Channel); -extern uint32_t USBDMANumChannels(uint32_t ui32Base); -extern void USBDMAChannelAssign(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Channel, uint32_t ui32Flags); -extern void USBDMAChannelIntEnable(uint32_t ui32Base, uint32_t ui32Channel); -extern void USBDMAChannelIntDisable(uint32_t ui32Base, uint32_t ui32Channel); -extern void USBDMAChannelEnable(uint32_t ui32Base, uint32_t ui32Channel); -extern void USBDMAChannelDisable(uint32_t ui32Base, uint32_t ui32Channel); -extern uint32_t USBDMAChannelStatus(uint32_t ui32Base, uint32_t ui32Channel); -extern void USBDMAChannelStatusClear(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Status); -extern void USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBHostEndpointPing(uint32_t ui32Base, uint32_t ui32Endpoint, - bool bEnable); -extern void USBHostLPMSend(uint32_t ui32Base, uint32_t ui32Address, - uint32_t uiEndpoint); -extern void USBHostLPMConfig(uint32_t ui32Base, uint32_t ui32ResumeTime, - uint32_t ui32Config); -extern bool USBLPMRemoteWakeEnabled(uint32_t ui32Base); -extern void USBHostLPMResume(uint32_t ui32Base); -extern void USBDevLPMRemoteWake(uint32_t ui32Base); -extern void USBDevLPMConfig(uint32_t ui32Base, uint32_t ui32Config); -extern void USBDevLPMEnable(uint32_t ui32Base); -extern void USBDevLPMDisable(uint32_t ui32Base); -extern uint32_t USBLPMLinkStateGet(uint32_t ui32Base); -extern uint32_t USBLPMEndpointGet(uint32_t ui32Base); -extern uint32_t USBLPMIntStatus(uint32_t ui32Base); -extern void USBLPMIntDisable(uint32_t ui32Base, uint32_t ui32Ints); -extern void USBLPMIntEnable(uint32_t ui32Base, uint32_t ui32Ints); -extern void USBHighSpeed(uint32_t ui32Base, bool bEnable); -extern uint32_t USBDevSpeedGet(uint32_t ui32Base); -extern void USBClockEnable(uint32_t ui32Base, uint32_t ui32Div, - uint32_t ui32Flags); -extern void USBClockDisable(uint32_t ui32Base); -extern void USBULPIConfig(uint32_t ui32Base, uint32_t ui32Config); -extern void USBULPIEnable(uint32_t ui32Base); -extern void USBULPIDisable(uint32_t ui32Base); -extern uint8_t USBULPIRegRead(uint32_t ui32Base, uint8_t ui8Reg); -extern void USBULPIRegWrite(uint32_t ui32Base, uint8_t ui8Reg, - uint8_t ui8Data); -extern void USBHostMode(uint32_t ui32Base); -extern void USBDevMode(uint32_t ui32Base); -extern void USBOTGMode(uint32_t ui32Base); -extern void USBModeConfig(uint32_t ui32Base, uint32_t ui32Mode); -extern void USBPHYPowerOff(uint32_t ui32Base); -extern void USBPHYPowerOn(uint32_t ui32Base); -extern uint32_t USBNumEndpointsGet(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_USB_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/watchdog.c b/bsp/tm4c129x-dk/libraries/driverlib/watchdog.c deleted file mode 100644 index e1761ff74707c1ac66de2e51fec42bb36e20cb96..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/watchdog.c +++ /dev/null @@ -1,622 +0,0 @@ -//***************************************************************************** -// -// watchdog.c - Driver for the Watchdog Timer Module. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup watchdog_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_watchdog.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/watchdog.h" - -//***************************************************************************** -// -//! Determines if the watchdog timer is enabled. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function checks to see if the watchdog timer is enabled. -//! -//! \return Returns \b true if the watchdog timer is enabled and \b false -//! if it is not. -// -//***************************************************************************** -bool -WatchdogRunning(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // See if the watchdog timer module is enabled, and return. - // - return(HWREG(ui32Base + WDT_O_CTL) & WDT_CTL_INTEN); -} - -//***************************************************************************** -// -//! Enables the watchdog timer. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function enables the watchdog timer counter and interrupt. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Enable the watchdog timer module. - // - HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN; -} - -//***************************************************************************** -// -//! Enables the watchdog timer reset. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function enables the capability of the watchdog timer to issue a reset -//! to the processor after a second timeout condition. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogResetEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Enable the watchdog reset. - // - HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_RESEN; -} - -//***************************************************************************** -// -//! Disables the watchdog timer reset. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function disables the capability of the watchdog timer to issue a -//! reset to the processor after a second timeout condition. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogResetDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Disable the watchdog reset. - // - HWREG(ui32Base + WDT_O_CTL) &= ~(WDT_CTL_RESEN); -} - -//***************************************************************************** -// -//! Enables the watchdog timer lock mechanism. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function locks out write access to the watchdog timer registers. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogLock(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK - // register causes the lock to go into effect. - // - HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_LOCKED; -} - -//***************************************************************************** -// -//! Disables the watchdog timer lock mechanism. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function enables write access to the watchdog timer registers. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogUnlock(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Unlock watchdog register writes. - // - HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_UNLOCK; -} - -//***************************************************************************** -// -//! Gets the state of the watchdog timer lock mechanism. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function returns the lock state of the watchdog timer registers. -//! -//! \return Returns \b true if the watchdog timer registers are locked, and -//! \b false if they are not locked. -// -//***************************************************************************** -bool -WatchdogLockState(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Get the lock state. - // - return((HWREG(ui32Base + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); -} - -//***************************************************************************** -// -//! Sets the watchdog timer reload value. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! \param ui32LoadVal is the load value for the watchdog timer. -//! -//! This function configures the value to load into the watchdog timer when the -//! count reaches zero for the first time; if the watchdog timer is running -//! when this function is called, then the value is immediately loaded into the -//! watchdog timer counter. If the \e ui32LoadVal parameter is 0, then an -//! interrupt is immediately generated. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Set the load register. - // - HWREG(ui32Base + WDT_O_LOAD) = ui32LoadVal; -} - -//***************************************************************************** -// -//! Gets the watchdog timer reload value. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function gets the value that is loaded into the watchdog timer when -//! the count reaches zero for the first time. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -WatchdogReloadGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Get the load register. - // - return(HWREG(ui32Base + WDT_O_LOAD)); -} - -//***************************************************************************** -// -//! Gets the current watchdog timer value. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function reads the current value of the watchdog timer. -//! -//! \return Returns the current value of the watchdog timer. -// -//***************************************************************************** -uint32_t -WatchdogValueGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Get the current watchdog timer register value. - // - return(HWREG(ui32Base + WDT_O_VALUE)); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the watchdog timer interrupt. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! \param pfnHandler is a pointer to the function to be called when the -//! watchdog timer interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function also enables the global interrupt in the interrupt controller; the -//! watchdog timer interrupt must be enabled via WatchdogEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! WatchdogIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note For parts with a watchdog timer module that has the ability to -//! generate an NMI instead of a standard interrupt, this function registers -//! the standard watchdog interrupt handler. To register the NMI watchdog -//! handler, use IntRegister() to register the handler for the -//! \b FAULT_NMI interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Register the interrupt handler. - // - IntRegister(INT_WATCHDOG_TM4C123, pfnHandler); - - // - // Enable the watchdog timer interrupt. - // - IntEnable(INT_WATCHDOG_TM4C123); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the watchdog timer interrupt. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function does the actual unregistering of the interrupt handler. This -//! function clears the handler to be called when a watchdog timer interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note For parts with a watchdog timer module that has the ability to -//! generate an NMI instead of a standard interrupt, this function unregisters -//! the standard watchdog interrupt handler. To unregister the NMI watchdog -//! handler, use IntUnregister() to unregister the handler for the -//! \b FAULT_NMI interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Disable the interrupt. - // - IntDisable(INT_WATCHDOG_TM4C123); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_WATCHDOG_TM4C123); -} - -//***************************************************************************** -// -//! Enables the watchdog timer interrupt. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function enables the watchdog timer interrupt. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Enable the watchdog interrupt. - // - HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN; -} - -//***************************************************************************** -// -//! Gets the current watchdog timer interrupt status. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the watchdog timer module. -//! Either the raw interrupt status or the status of interrupt that is allowed -//! to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, where a 1 indicates that the -//! watchdog interrupt is active, and a 0 indicates that it is not active. -// -//***************************************************************************** -uint32_t -WatchdogIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + WDT_O_MIS)); - } - else - { - return(HWREG(ui32Base + WDT_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the watchdog timer interrupt. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! The watchdog timer interrupt source is cleared, so that it no longer -//! asserts. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). This function has no effect if the watchdog -//! timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Clear the interrupt source. - // - HWREG(ui32Base + WDT_O_ICR) = WDT_RIS_WDTRIS; -} - -//***************************************************************************** -// -//! Sets the type of interrupt generated by the watchdog. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! \param ui32Type is the type of interrupt to generate. -//! -//! This function sets the type of interrupt that is generated if the watchdog -//! timer expires. \e ui32Type can be either \b WATCHDOG_INT_TYPE_INT to -//! generate a standard interrupt (the default) or \b WATCHDOG_INT_TYPE_NMI to -//! generate a non-maskable interrupt (NMI). -//! -//! When configured to generate an NMI, the watchdog interrupt must still be -//! enabled with WatchdogIntEnable(), and it must still be cleared inside the -//! NMI handler with WatchdogIntClear(). -//! -//! \note The ability to select an NMI interrupt varies with the Tiva part -//! in use. Please consult the datasheet for the part you are using to -//! determine whether this support is available. This function has no effect if -//! the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) || - (ui32Type == WATCHDOG_INT_TYPE_NMI)); - - // - // Set the interrupt type. - // - HWREG(ui32Base + WDT_O_CTL) = (HWREG(ui32Base + WDT_O_CTL) & - ~WDT_CTL_INTTYPE) | ui32Type; -} - -//***************************************************************************** -// -//! Enables stalling of the watchdog timer during debug events. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function allows the watchdog timer to stop counting when the processor -//! is stopped by the debugger. By doing so, the watchdog is prevented from -//! expiring (typically almost immediately from a human time perspective) and -//! resetting the system (if reset is enabled). The watchdog instead expires -//! after the appropriate number of processor cycles have been executed while -//! debugging (or at the appropriate time after the processor has been -//! restarted). -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogStallEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Enable timer stalling. - // - HWREG(ui32Base + WDT_O_TEST) |= WDT_TEST_STALL; -} - -//***************************************************************************** -// -//! Disables stalling of the watchdog timer during debug events. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function disables the debug mode stall of the watchdog timer. By -//! doing so, the watchdog timer continues to count regardless of the processor -//! debug state. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogStallDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Disable timer stalling. - // - HWREG(ui32Base + WDT_O_TEST) &= ~(WDT_TEST_STALL); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/watchdog.h b/bsp/tm4c129x-dk/libraries/driverlib/watchdog.h deleted file mode 100644 index a14a4fb04cc59487cd29c0e44d0458bf69c03c8f..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/watchdog.h +++ /dev/null @@ -1,95 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_WATCHDOG_H__ -#define __DRIVERLIB_WATCHDOG_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The type of interrupt that can be generated by the watchdog. -// -//***************************************************************************** -#define WATCHDOG_INT_TYPE_INT 0x00000000 -#define WATCHDOG_INT_TYPE_NMI 0x00000004 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern bool WatchdogRunning(uint32_t ui32Base); -extern void WatchdogEnable(uint32_t ui32Base); -extern void WatchdogResetEnable(uint32_t ui32Base); -extern void WatchdogResetDisable(uint32_t ui32Base); -extern void WatchdogLock(uint32_t ui32Base); -extern void WatchdogUnlock(uint32_t ui32Base); -extern bool WatchdogLockState(uint32_t ui32Base); -extern void WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal); -extern uint32_t WatchdogReloadGet(uint32_t ui32Base); -extern uint32_t WatchdogValueGet(uint32_t ui32Base); -extern void WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void WatchdogIntUnregister(uint32_t ui32Base); -extern void WatchdogIntEnable(uint32_t ui32Base); -extern uint32_t WatchdogIntStatus(uint32_t ui32Base, bool bMasked); -extern void WatchdogIntClear(uint32_t ui32Base); -extern void WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type); -extern void WatchdogStallEnable(uint32_t ui32Base); -extern void WatchdogStallDisable(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_WATCHDOG_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/asmdefs.h b/bsp/tm4c129x-dk/libraries/inc/asmdefs.h deleted file mode 100644 index b0e4cc217ca36d33d776c12d627c159f73920917..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/asmdefs.h +++ /dev/null @@ -1,227 +0,0 @@ -//***************************************************************************** -// -// asmdefs.h - Macros to allow assembly code be portable among toolchains. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __ASMDEFS_H__ -#define __ASMDEFS_H__ - -//***************************************************************************** -// -// The defines required for code_red. -// -//***************************************************************************** -#ifdef codered - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // codered - -//***************************************************************************** -// -// The defines required for EW-ARM. -// -//***************************************************************************** -#ifdef ewarm - -// -// Section headers. -// -#define __LIBRARY__ module -#define __TEXT__ rseg CODE:CODE(2) -#define __DATA__ rseg DATA:DATA(2) -#define __BSS__ rseg DATA:DATA(2) -#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) - -// -// Assembler nmenonics. -// -#define __ALIGN__ alignrom 2 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ thumb -#define __WORD__ dcd -#define __INLINE_DATA__ data - -#endif // ewarm - -//***************************************************************************** -// -// The defines required for GCC. -// -//***************************************************************************** -#if defined(gcc) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // gcc - -//***************************************************************************** -// -// The defines required for RV-MDK. -// -//***************************************************************************** -#ifdef rvmdk - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - thumb - require8 - preserve8 - -// -// Section headers. -// -#define __LIBRARY__ ; -#define __TEXT__ area ||.text||, code, readonly, align=2 -#define __DATA__ area ||.data||, data, align=2 -#define __BSS__ area ||.bss||, noinit, align=2 -#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 - -// -// Assembler nmenonics. -// -#define __ALIGN__ align 4 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ -#define __WORD__ dcd -#define __INLINE_DATA__ - -#endif // rvmdk - -//***************************************************************************** -// -// The defines required for Sourcery G++. -// -//***************************************************************************** -#if defined(sourcerygxx) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // sourcerygxx - -#endif // __ASMDEF_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_adc.h b/bsp/tm4c129x-dk/libraries/inc/hw_adc.h deleted file mode 100644 index 41f8a33e4df5434f5b442412631fe04723dd74f1..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_adc.h +++ /dev/null @@ -1,1306 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following are defines for the ADC register offsets. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // ADC Active Sample Sequencer -#define ADC_O_RIS 0x00000004 // ADC Raw Interrupt Status -#define ADC_O_IM 0x00000008 // ADC Interrupt Mask -#define ADC_O_ISC 0x0000000C // ADC Interrupt Status and Clear -#define ADC_O_OSTAT 0x00000010 // ADC Overflow Status -#define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select -#define ADC_O_USTAT 0x00000018 // ADC Underflow Status -#define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select -#define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority -#define ADC_O_SPC 0x00000024 // ADC Sample Phase Control -#define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence - // Initiate -#define ADC_O_SAC 0x00000030 // ADC Sample Averaging Control -#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt - // Status and Clear -#define ADC_O_CTL 0x00000038 // ADC Control -#define ADC_O_SSMUX0 0x00000040 // ADC Sample Sequence Input - // Multiplexer Select 0 -#define ADC_O_SSCTL0 0x00000044 // ADC Sample Sequence Control 0 -#define ADC_O_SSFIFO0 0x00000048 // ADC Sample Sequence Result FIFO - // 0 -#define ADC_O_SSFSTAT0 0x0000004C // ADC Sample Sequence FIFO 0 - // Status -#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation -#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital - // Comparator Select -#define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended - // Input Multiplexer Select 0 -#define ADC_O_SSTSH0 0x0000005C // ADC Sample Sequence 0 Sample and - // Hold Time -#define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input - // Multiplexer Select 1 -#define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1 -#define ADC_O_SSFIFO1 0x00000068 // ADC Sample Sequence Result FIFO - // 1 -#define ADC_O_SSFSTAT1 0x0000006C // ADC Sample Sequence FIFO 1 - // Status -#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation -#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital - // Comparator Select -#define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended - // Input Multiplexer Select 1 -#define ADC_O_SSTSH1 0x0000007C // ADC Sample Sequence 1 Sample and - // Hold Time -#define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input - // Multiplexer Select 2 -#define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2 -#define ADC_O_SSFIFO2 0x00000088 // ADC Sample Sequence Result FIFO - // 2 -#define ADC_O_SSFSTAT2 0x0000008C // ADC Sample Sequence FIFO 2 - // Status -#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation -#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital - // Comparator Select -#define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended - // Input Multiplexer Select 2 -#define ADC_O_SSTSH2 0x0000009C // ADC Sample Sequence 2 Sample and - // Hold Time -#define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input - // Multiplexer Select 3 -#define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3 -#define ADC_O_SSFIFO3 0x000000A8 // ADC Sample Sequence Result FIFO - // 3 -#define ADC_O_SSFSTAT3 0x000000AC // ADC Sample Sequence FIFO 3 - // Status -#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation -#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital - // Comparator Select -#define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended - // Input Multiplexer Select 3 -#define ADC_O_SSTSH3 0x000000BC // ADC Sample Sequence 3 Sample and - // Hold Time -#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset - // Initial Conditions -#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0 -#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1 -#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2 -#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3 -#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4 -#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5 -#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6 -#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7 -#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0 -#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1 -#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2 -#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3 -#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4 -#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5 -#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6 -#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7 -#define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties -#define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration -#define ADC_O_CC 0x00000FC8 // ADC Clock Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_BUSY 0x00010000 // ADC Busy -#define ADC_ACTSS_ADEN3 0x00000800 // ADC SS3 DMA Enable -#define ADC_ACTSS_ADEN2 0x00000400 // ADC SS2 DMA Enable -#define ADC_ACTSS_ADEN1 0x00000200 // ADC SS1 DMA Enable -#define ADC_ACTSS_ADEN0 0x00000100 // ADC SS1 DMA Enable -#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable -#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable -#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable -#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt - // Status -#define ADC_RIS_DMAINR3 0x00000800 // SS3 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR2 0x00000400 // SS2 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR1 0x00000200 // SS1 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR0 0x00000100 // SS0 DMA Raw Interrupt Status -#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status -#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status -#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status -#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_IM register. -// -//***************************************************************************** -#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on - // SS3 -#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on - // SS2 -#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on - // SS1 -#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on - // SS0 -#define ADC_IM_DMAMASK3 0x00000800 // SS3 DMA Interrupt Mask -#define ADC_IM_DMAMASK2 0x00000400 // SS2 DMA Interrupt Mask -#define ADC_IM_DMAMASK1 0x00000200 // SS1 DMA Interrupt Mask -#define ADC_IM_DMAMASK0 0x00000100 // SS0 DMA Interrupt Mask -#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask -#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask -#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask -#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ISC register. -// -//***************************************************************************** -#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt - // Status on SS3 -#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt - // Status on SS2 -#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt - // Status on SS1 -#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt - // Status on SS0 -#define ADC_ISC_DMAIN3 0x00000800 // SS3 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN2 0x00000400 // SS2 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN1 0x00000200 // SS1 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN0 0x00000100 // SS0 DMA Interrupt Status and - // Clear -#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear -#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear -#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear -#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow -#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow -#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow -#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2 -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO Pins) -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM generator 0 -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM generator 1 -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM generator 2 -#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM generator 3 -#define ADC_EMUX_EM3_NEVER 0x0000E000 // Never Trigger -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) -#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2 -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO Pins) -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM generator 0 -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM generator 1 -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM generator 2 -#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM generator 3 -#define ADC_EMUX_EM2_NEVER 0x00000E00 // Never Trigger -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) -#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2 -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO Pins) -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM generator 0 -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM generator 1 -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM generator 2 -#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM generator 3 -#define ADC_EMUX_EM1_NEVER 0x000000E0 // Never Trigger -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) -#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2 -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO Pins) -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM generator 0 -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM generator 1 -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM generator 2 -#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM generator 3 -#define ADC_EMUX_EM0_NEVER 0x0000000E // Never Trigger -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow -#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow -#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow -#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_TSSEL register. -// -//***************************************************************************** -#define ADC_TSSEL_PS3_M 0x30000000 // Generator 3 PWM Module Trigger - // Select -#define ADC_TSSEL_PS3_0 0x00000000 // Use Generator 3 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS3_1 0x10000000 // Use Generator 3 (and its - // trigger) in PWM module 1 -#define ADC_TSSEL_PS2_M 0x00300000 // Generator 2 PWM Module Trigger - // Select -#define ADC_TSSEL_PS2_0 0x00000000 // Use Generator 2 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS2_1 0x00100000 // Use Generator 2 (and its - // trigger) in PWM module 1 -#define ADC_TSSEL_PS1_M 0x00003000 // Generator 1 PWM Module Trigger - // Select -#define ADC_TSSEL_PS1_0 0x00000000 // Use Generator 1 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS1_1 0x00001000 // Use Generator 1 (and its - // trigger) in PWM module 1 -#define ADC_TSSEL_PS0_M 0x00000030 // Generator 0 PWM Module Trigger - // Select -#define ADC_TSSEL_PS0_0 0x00000000 // Use Generator 0 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS0_1 0x00000010 // Use Generator 0 (and its - // trigger) in PWM module 1 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority -#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority -#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority -#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SPC register. -// -//***************************************************************************** -#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference -#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 -#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 -#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 -#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 -#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 -#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 -#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 -#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 -#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 -#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 -#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 -#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 -#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 -#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 -#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 -#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize -#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait -#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate -#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate -#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate -#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCISC register. -// -//***************************************************************************** -#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt - // Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_CTL register. -// -//***************************************************************************** -#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select -#define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage - // references -#define ADC_CTL_VREF_EXT_3V 0x00000001 // The external VREFA+ and VREFA- - // inputs are the voltage - // references - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX0 register. -// -//***************************************************************************** -#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select -#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select -#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select -#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select -#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX0_MUX7_S 28 -#define ADC_SSMUX0_MUX6_S 24 -#define ADC_SSMUX0_MUX5_S 20 -#define ADC_SSMUX0_MUX4_S 16 -#define ADC_SSMUX0_MUX3_S 12 -#define ADC_SSMUX0_MUX2_S 8 -#define ADC_SSMUX0_MUX1_S 4 -#define ADC_SSMUX0_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL0 register. -// -//***************************************************************************** -#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select -#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable -#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence -#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Differential Input - // Select -#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select -#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable -#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence -#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Differential Input - // Select -#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select -#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable -#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence -#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Differential Input - // Select -#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select -#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable -#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence -#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Differential Input - // Select -#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. -// -//***************************************************************************** -#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. -// -//***************************************************************************** -#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT0_HPTR_S 4 -#define ADC_SSFSTAT0_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP0 register. -// -//***************************************************************************** -#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator - // Operation -#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator - // Operation -#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator - // Operation -#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator - // Operation -#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC0 register. -// -//***************************************************************************** -#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator - // Select -#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator - // Select -#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator - // Select -#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator - // Select -#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC0_S6DCSEL_S 24 -#define ADC_SSDC0_S5DCSEL_S 20 -#define ADC_SSDC0_S4DCSEL_S 16 -#define ADC_SSDC0_S3DCSEL_S 12 -#define ADC_SSDC0_S2DCSEL_S 8 -#define ADC_SSDC0_S1DCSEL_S 4 -#define ADC_SSDC0_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX0 register. -// -//***************************************************************************** -#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH0 register. -// -//***************************************************************************** -#define ADC_SSTSH0_TSH7_M 0xF0000000 // 8th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH6_M 0x0F000000 // 7th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH5_M 0x00F00000 // 6th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH4_M 0x000F0000 // 5th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH7_S 28 -#define ADC_SSTSH0_TSH6_S 24 -#define ADC_SSTSH0_TSH5_S 20 -#define ADC_SSTSH0_TSH4_S 16 -#define ADC_SSTSH0_TSH3_S 12 -#define ADC_SSTSH0_TSH2_S 8 -#define ADC_SSTSH0_TSH1_S 4 -#define ADC_SSTSH0_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX1 register. -// -//***************************************************************************** -#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX1_MUX3_S 12 -#define ADC_SSMUX1_MUX2_S 8 -#define ADC_SSMUX1_MUX1_S 4 -#define ADC_SSMUX1_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL1 register. -// -//***************************************************************************** -#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. -// -//***************************************************************************** -#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. -// -//***************************************************************************** -#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT1_HPTR_S 4 -#define ADC_SSFSTAT1_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP1 register. -// -//***************************************************************************** -#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC1 register. -// -//***************************************************************************** -#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC1_S2DCSEL_S 8 -#define ADC_SSDC1_S1DCSEL_S 4 -#define ADC_SSDC1_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX1 register. -// -//***************************************************************************** -#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH1 register. -// -//***************************************************************************** -#define ADC_SSTSH1_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH3_S 12 -#define ADC_SSTSH1_TSH2_S 8 -#define ADC_SSTSH1_TSH1_S 4 -#define ADC_SSTSH1_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX2 register. -// -//***************************************************************************** -#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX2_MUX3_S 12 -#define ADC_SSMUX2_MUX2_S 8 -#define ADC_SSMUX2_MUX1_S 4 -#define ADC_SSMUX2_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL2 register. -// -//***************************************************************************** -#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. -// -//***************************************************************************** -#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. -// -//***************************************************************************** -#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT2_HPTR_S 4 -#define ADC_SSFSTAT2_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP2 register. -// -//***************************************************************************** -#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC2 register. -// -//***************************************************************************** -#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC2_S2DCSEL_S 8 -#define ADC_SSDC2_S1DCSEL_S 4 -#define ADC_SSDC2_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX2 register. -// -//***************************************************************************** -#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH2 register. -// -//***************************************************************************** -#define ADC_SSTSH2_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH3_S 12 -#define ADC_SSTSH2_TSH2_S 8 -#define ADC_SSTSH2_TSH1_S 4 -#define ADC_SSTSH2_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX3 register. -// -//***************************************************************************** -#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX3_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL3 register. -// -//***************************************************************************** -#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL3_IE0 0x00000004 // Sample Interrupt Enable -#define ADC_SSCTL3_END0 0x00000002 // End of Sequence -#define ADC_SSCTL3_D0 0x00000001 // Sample Differential Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. -// -//***************************************************************************** -#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. -// -//***************************************************************************** -#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT3_HPTR_S 4 -#define ADC_SSFSTAT3_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP3 register. -// -//***************************************************************************** -#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC3 register. -// -//***************************************************************************** -#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX3 register. -// -//***************************************************************************** -#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH3 register. -// -//***************************************************************************** -#define ADC_SSTSH3_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH3_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCRIC register. -// -//***************************************************************************** -#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 -#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 -#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 -#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 -#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 -#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 -#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 -#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 -#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 -#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 -#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 -#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 -#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 -#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 -#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 -#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL0 register. -// -//***************************************************************************** -#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL1 register. -// -//***************************************************************************** -#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL2 register. -// -//***************************************************************************** -#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL3 register. -// -//***************************************************************************** -#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL4 register. -// -//***************************************************************************** -#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL5 register. -// -//***************************************************************************** -#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL6 register. -// -//***************************************************************************** -#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL7 register. -// -//***************************************************************************** -#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP0 register. -// -//***************************************************************************** -#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP0_COMP1_S 16 -#define ADC_DCCMP0_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP1 register. -// -//***************************************************************************** -#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP1_COMP1_S 16 -#define ADC_DCCMP1_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP2 register. -// -//***************************************************************************** -#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP2_COMP1_S 16 -#define ADC_DCCMP2_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP3 register. -// -//***************************************************************************** -#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP3_COMP1_S 16 -#define ADC_DCCMP3_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP4 register. -// -//***************************************************************************** -#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP4_COMP1_S 16 -#define ADC_DCCMP4_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP5 register. -// -//***************************************************************************** -#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP5_COMP1_S 16 -#define ADC_DCCMP5_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP6 register. -// -//***************************************************************************** -#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP6_COMP1_S 16 -#define ADC_DCCMP6_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP7 register. -// -//***************************************************************************** -#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP7_COMP1_S 16 -#define ADC_DCCMP7_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PP register. -// -//***************************************************************************** -#define ADC_PP_APSHT 0x01000000 // Application-Programmable - // Sample-and-Hold Time -#define ADC_PP_TS 0x00800000 // Temperature Sensor -#define ADC_PP_RSL_M 0x007C0000 // Resolution -#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture -#define ADC_PP_TYPE_SAR 0x00000000 // SAR -#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count -#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count -#define ADC_PP_MCR_M 0x0000000F // Maximum Conversion Rate -#define ADC_PP_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as - // defined by TADC and NSH -#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate -#define ADC_PP_MSR_125K 0x00000001 // 125 ksps -#define ADC_PP_MSR_250K 0x00000003 // 250 ksps -#define ADC_PP_MSR_500K 0x00000005 // 500 ksps -#define ADC_PP_MSR_1M 0x00000007 // 1 Msps -#define ADC_PP_RSL_S 18 -#define ADC_PP_DC_S 10 -#define ADC_PP_CH_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PC register. -// -//***************************************************************************** -#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate -#define ADC_PC_SR_125K 0x00000001 // 125 ksps -#define ADC_PC_SR_250K 0x00000003 // 250 ksps -#define ADC_PC_SR_500K 0x00000005 // 500 ksps -#define ADC_PC_SR_1M 0x00000007 // 1 Msps -#define ADC_PC_MCR_M 0x0000000F // Conversion Rate -#define ADC_PC_MCR_1_8 0x00000001 // Eighth conversion rate. After a - // conversion completes, the logic - // pauses for 112 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_1_4 0x00000003 // Quarter conversion rate. After a - // conversion completes, the logic - // pauses for 48 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_1_2 0x00000005 // Half conversion rate. After a - // conversion completes, the logic - // pauses for 16 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as - // defined by TADC and NSH - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_CC register. -// -//***************************************************************************** -#define ADC_CC_CLKDIV_M 0x000003F0 // PLL VCO Clock Divisor -#define ADC_CC_CS_M 0x0000000F // ADC Clock Source -#define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV -#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC -#define ADC_CC_CS_MOSC 0x00000002 // MOSC -#define ADC_CC_CLKDIV_S 4 - -#endif // __HW_ADC_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_aes.h b/bsp/tm4c129x-dk/libraries/inc/hw_aes.h deleted file mode 100644 index 79d56113d65d213d247d0f3b2f7ce159dd788380..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_aes.h +++ /dev/null @@ -1,545 +0,0 @@ -//***************************************************************************** -// -// hw_aes.h - Macros used when accessing the AES hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_AES_H__ -#define __HW_AES_H__ - -//***************************************************************************** -// -// The following are defines for the AES register offsets. -// -//***************************************************************************** -#define AES_O_KEY2_6 0x00000000 // AES Key 2_6 -#define AES_O_KEY2_7 0x00000004 // AES Key 2_7 -#define AES_O_KEY2_4 0x00000008 // AES Key 2_4 -#define AES_O_KEY2_5 0x0000000C // AES Key 2_5 -#define AES_O_KEY2_2 0x00000010 // AES Key 2_2 -#define AES_O_KEY2_3 0x00000014 // AES Key 2_3 -#define AES_O_KEY2_0 0x00000018 // AES Key 2_0 -#define AES_O_KEY2_1 0x0000001C // AES Key 2_1 -#define AES_O_KEY1_6 0x00000020 // AES Key 1_6 -#define AES_O_KEY1_7 0x00000024 // AES Key 1_7 -#define AES_O_KEY1_4 0x00000028 // AES Key 1_4 -#define AES_O_KEY1_5 0x0000002C // AES Key 1_5 -#define AES_O_KEY1_2 0x00000030 // AES Key 1_2 -#define AES_O_KEY1_3 0x00000034 // AES Key 1_3 -#define AES_O_KEY1_0 0x00000038 // AES Key 1_0 -#define AES_O_KEY1_1 0x0000003C // AES Key 1_1 -#define AES_O_IV_IN_0 0x00000040 // AES Initialization Vector Input - // 0 -#define AES_O_IV_IN_1 0x00000044 // AES Initialization Vector Input - // 1 -#define AES_O_IV_IN_2 0x00000048 // AES Initialization Vector Input - // 2 -#define AES_O_IV_IN_3 0x0000004C // AES Initialization Vector Input - // 3 -#define AES_O_CTRL 0x00000050 // AES Control -#define AES_O_C_LENGTH_0 0x00000054 // AES Crypto Data Length 0 -#define AES_O_C_LENGTH_1 0x00000058 // AES Crypto Data Length 1 -#define AES_O_AUTH_LENGTH 0x0000005C // AES Authentication Data Length -#define AES_O_DATA_IN_0 0x00000060 // AES Data RW Plaintext/Ciphertext - // 0 -#define AES_O_DATA_IN_1 0x00000064 // AES Data RW Plaintext/Ciphertext - // 1 -#define AES_O_DATA_IN_2 0x00000068 // AES Data RW Plaintext/Ciphertext - // 2 -#define AES_O_DATA_IN_3 0x0000006C // AES Data RW Plaintext/Ciphertext - // 3 -#define AES_O_TAG_OUT_0 0x00000070 // AES Hash Tag Out 0 -#define AES_O_TAG_OUT_1 0x00000074 // AES Hash Tag Out 1 -#define AES_O_TAG_OUT_2 0x00000078 // AES Hash Tag Out 2 -#define AES_O_TAG_OUT_3 0x0000007C // AES Hash Tag Out 3 -#define AES_O_REVISION 0x00000080 // AES IP Revision Identifier -#define AES_O_SYSCONFIG 0x00000084 // AES System Configuration -#define AES_O_SYSSTATUS 0x00000088 // AES System Status -#define AES_O_IRQSTATUS 0x0000008C // AES Interrupt Status -#define AES_O_IRQENABLE 0x00000090 // AES Interrupt Enable -#define AES_O_DIRTYBITS 0x00000094 // AES Dirty Bits -#define AES_O_DMAIM 0xFFFFA020 // AES DMA Interrupt Mask -#define AES_O_DMARIS 0xFFFFA024 // AES DMA Raw Interrupt Status -#define AES_O_DMAMIS 0xFFFFA028 // AES DMA Masked Interrupt Status -#define AES_O_DMAIC 0xFFFFA02C // AES DMA Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_6 register. -// -//***************************************************************************** -#define AES_KEY2_6_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_6_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_7 register. -// -//***************************************************************************** -#define AES_KEY2_7_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_7_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_4 register. -// -//***************************************************************************** -#define AES_KEY2_4_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_4_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_5 register. -// -//***************************************************************************** -#define AES_KEY2_5_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_5_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_2 register. -// -//***************************************************************************** -#define AES_KEY2_2_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_2_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_3 register. -// -//***************************************************************************** -#define AES_KEY2_3_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_3_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_0 register. -// -//***************************************************************************** -#define AES_KEY2_0_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_0_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_1 register. -// -//***************************************************************************** -#define AES_KEY2_1_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_1_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_6 register. -// -//***************************************************************************** -#define AES_KEY1_6_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_6_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_7 register. -// -//***************************************************************************** -#define AES_KEY1_7_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_7_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_4 register. -// -//***************************************************************************** -#define AES_KEY1_4_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_4_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_5 register. -// -//***************************************************************************** -#define AES_KEY1_5_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_5_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_2 register. -// -//***************************************************************************** -#define AES_KEY1_2_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_2_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_3 register. -// -//***************************************************************************** -#define AES_KEY1_3_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_3_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_0 register. -// -//***************************************************************************** -#define AES_KEY1_0_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_0_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_1 register. -// -//***************************************************************************** -#define AES_KEY1_1_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_1_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_0 register. -// -//***************************************************************************** -#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // Initialization Vector Input -#define AES_IV_IN_0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_1 register. -// -//***************************************************************************** -#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // Initialization Vector Input -#define AES_IV_IN_1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_2 register. -// -//***************************************************************************** -#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // Initialization Vector Input -#define AES_IV_IN_2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_3 register. -// -//***************************************************************************** -#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // Initialization Vector Input -#define AES_IV_IN_3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_CTRL register. -// -//***************************************************************************** -#define AES_CTRL_CTXTRDY 0x80000000 // Context Data Registers Ready -#define AES_CTRL_SVCTXTRDY 0x40000000 // AES TAG/IV Block(s) Ready -#define AES_CTRL_SAVE_CONTEXT 0x20000000 // TAG or Result IV Save -#define AES_CTRL_CCM_M_M 0x01C00000 // Counter with CBC-MAC (CCM) -#define AES_CTRL_CCM_L_M 0x00380000 // L Value -#define AES_CTRL_CCM_L_2 0x00080000 // width = 2 -#define AES_CTRL_CCM_L_4 0x00180000 // width = 4 -#define AES_CTRL_CCM_L_8 0x00380000 // width = 8 -#define AES_CTRL_CCM 0x00040000 // AES-CCM Mode Enable -#define AES_CTRL_GCM_M 0x00030000 // AES-GCM Mode Enable -#define AES_CTRL_GCM_NOP 0x00000000 // No operation -#define AES_CTRL_GCM_HLY0ZERO 0x00010000 // GHASH with H loaded and - // Y0-encrypted forced to zero -#define AES_CTRL_GCM_HLY0CALC 0x00020000 // GHASH with H loaded and - // Y0-encrypted calculated - // internally -#define AES_CTRL_GCM_HY0CALC 0x00030000 // Autonomous GHASH (both H and - // Y0-encrypted calculated - // internally) -#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC Enable -#define AES_CTRL_F9 0x00004000 // AES f9 Mode Enable -#define AES_CTRL_F8 0x00002000 // AES f8 Mode Enable -#define AES_CTRL_XTS_M 0x00001800 // AES-XTS Operation Enabled -#define AES_CTRL_XTS_NOP 0x00000000 // No operation -#define AES_CTRL_XTS_TWEAKJL 0x00000800 // Previous/intermediate tweak - // value and j loaded (value is - // loaded via IV, j is loaded via - // the AAD length register) -#define AES_CTRL_XTS_K2IJL 0x00001000 // Key2, n and j are loaded (n is - // loaded via IV, j is loaded via - // the AAD length register) -#define AES_CTRL_XTS_K2ILJ0 0x00001800 // Key2 and n are loaded; j=0 (n is - // loaded via IV) -#define AES_CTRL_CFB 0x00000400 // Full block AES cipher feedback - // mode (CFB128) Enable -#define AES_CTRL_ICM 0x00000200 // AES Integer Counter Mode (ICM) - // Enable -#define AES_CTRL_CTR_WIDTH_M 0x00000180 // AES-CTR Mode Counter Width -#define AES_CTRL_CTR_WIDTH_32 0x00000000 // Counter is 32 bits -#define AES_CTRL_CTR_WIDTH_64 0x00000080 // Counter is 64 bits -#define AES_CTRL_CTR_WIDTH_96 0x00000100 // Counter is 96 bits -#define AES_CTRL_CTR_WIDTH_128 0x00000180 // Counter is 128 bits -#define AES_CTRL_CTR 0x00000040 // Counter Mode -#define AES_CTRL_MODE 0x00000020 // ECB/CBC Mode -#define AES_CTRL_KEY_SIZE_M 0x00000018 // Key Size -#define AES_CTRL_KEY_SIZE_128 0x00000008 // Key is 128 bits -#define AES_CTRL_KEY_SIZE_192 0x00000010 // Key is 192 bits -#define AES_CTRL_KEY_SIZE_256 0x00000018 // Key is 256 bits -#define AES_CTRL_DIRECTION 0x00000004 // Encryption/Decryption Selection -#define AES_CTRL_INPUT_READY 0x00000002 // Input Ready Status -#define AES_CTRL_OUTPUT_READY 0x00000001 // Output Ready Status -#define AES_CTRL_CCM_M_S 22 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_C_LENGTH_0 -// register. -// -//***************************************************************************** -#define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF // Data Length -#define AES_C_LENGTH_0_LENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_C_LENGTH_1 -// register. -// -//***************************************************************************** -#define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF // Data Length -#define AES_C_LENGTH_1_LENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_AUTH_LENGTH -// register. -// -//***************************************************************************** -#define AES_AUTH_LENGTH_AUTH_M 0xFFFFFFFF // Authentication Data Length -#define AES_AUTH_LENGTH_AUTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_0 -// register. -// -//***************************************************************************** -#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Secure Data RW - // Plaintext/Ciphertext -#define AES_DATA_IN_0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_1 -// register. -// -//***************************************************************************** -#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Secure Data RW - // Plaintext/Ciphertext -#define AES_DATA_IN_1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_2 -// register. -// -//***************************************************************************** -#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Secure Data RW - // Plaintext/Ciphertext -#define AES_DATA_IN_2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_3 -// register. -// -//***************************************************************************** -#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Secure Data RW - // Plaintext/Ciphertext -#define AES_DATA_IN_3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_0 -// register. -// -//***************************************************************************** -#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash Result -#define AES_TAG_OUT_0_HASH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_1 -// register. -// -//***************************************************************************** -#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash Result -#define AES_TAG_OUT_1_HASH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_2 -// register. -// -//***************************************************************************** -#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash Result -#define AES_TAG_OUT_2_HASH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_3 -// register. -// -//***************************************************************************** -#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash Result -#define AES_TAG_OUT_3_HASH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_REVISION register. -// -//***************************************************************************** -#define AES_REVISION_M 0xFFFFFFFF // Revision number -#define AES_REVISION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_SYSCONFIG -// register. -// -//***************************************************************************** -#define AES_SYSCONFIG_K3 0x00001000 // K3 Select -#define AES_SYSCONFIG_KEYENC 0x00000800 // Key Encoding -#define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT \ - 0x00000200 // Map Context Out on Data Out - // Enable -#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ - 0x00000100 // DMA Request Context Out Enable -#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ - 0x00000080 // DMA Request Context In Enable -#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ - 0x00000040 // DMA Request Data Out Enable -#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ - 0x00000020 // DMA Request Data In Enable -#define AES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_SYSSTATUS -// register. -// -//***************************************************************************** -#define AES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IRQSTATUS -// register. -// -//***************************************************************************** -#define AES_IRQSTATUS_CONTEXT_OUT \ - 0x00000008 // Context Output Interrupt Status -#define AES_IRQSTATUS_DATA_OUT 0x00000004 // Data Out Interrupt Status -#define AES_IRQSTATUS_DATA_IN 0x00000002 // Data In Interrupt Status -#define AES_IRQSTATUS_CONTEXT_IN \ - 0x00000001 // Context In Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IRQENABLE -// register. -// -//***************************************************************************** -#define AES_IRQENABLE_CONTEXT_OUT \ - 0x00000008 // Context Out Interrupt Enable -#define AES_IRQENABLE_DATA_OUT 0x00000004 // Data Out Interrupt Enable -#define AES_IRQENABLE_DATA_IN 0x00000002 // Data In Interrupt Enable -#define AES_IRQENABLE_CONTEXT_IN \ - 0x00000001 // Context In Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DIRTYBITS -// register. -// -//***************************************************************************** -#define AES_DIRTYBITS_S_DIRTY 0x00000002 // AES Dirty Bit -#define AES_DIRTYBITS_S_ACCESS 0x00000001 // AES Access Bit - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DMAIM register. -// -//***************************************************************************** -#define AES_DMAIM_DOUT 0x00000008 // Data Out DMA Done Interrupt Mask -#define AES_DMAIM_DIN 0x00000004 // Data In DMA Done Interrupt Mask -#define AES_DMAIM_COUT 0x00000002 // Context Out DMA Done Interrupt - // Mask -#define AES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DMARIS register. -// -//***************************************************************************** -#define AES_DMARIS_DOUT 0x00000008 // Data Out DMA Done Raw Interrupt - // Status -#define AES_DMARIS_DIN 0x00000004 // Data In DMA Done Raw Interrupt - // Status -#define AES_DMARIS_COUT 0x00000002 // Context Out DMA Done Raw - // Interrupt Status -#define AES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DMAMIS register. -// -//***************************************************************************** -#define AES_DMAMIS_DOUT 0x00000008 // Data Out DMA Done Masked - // Interrupt Status -#define AES_DMAMIS_DIN 0x00000004 // Data In DMA Done Masked - // Interrupt Status -#define AES_DMAMIS_COUT 0x00000002 // Context Out DMA Done Masked - // Interrupt Status -#define AES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DMAIC register. -// -//***************************************************************************** -#define AES_DMAIC_DOUT 0x00000008 // Data Out DMA Done Interrupt - // Clear -#define AES_DMAIC_DIN 0x00000004 // Data In DMA Done Interrupt Clear -#define AES_DMAIC_COUT 0x00000002 // Context Out DMA Done Masked - // Interrupt Status -#define AES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -#endif // __HW_AES_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_can.h b/bsp/tm4c129x-dk/libraries/inc/hw_can.h deleted file mode 100644 index 398a83d6cb1b0b550650997faaf7bde9a531caf5..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_can.h +++ /dev/null @@ -1,462 +0,0 @@ -//***************************************************************************** -// -// hw_can.h - Defines and macros used when accessing the CAN controllers. -// -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_CAN_H__ -#define __HW_CAN_H__ - -//***************************************************************************** -// -// The following are defines for the CAN register offsets. -// -//***************************************************************************** -#define CAN_O_CTL 0x00000000 // CAN Control -#define CAN_O_STS 0x00000004 // CAN Status -#define CAN_O_ERR 0x00000008 // CAN Error Counter -#define CAN_O_BIT 0x0000000C // CAN Bit Timing -#define CAN_O_INT 0x00000010 // CAN Interrupt -#define CAN_O_TST 0x00000014 // CAN Test -#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler - // Extension -#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request -#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask -#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1 -#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2 -#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1 -#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2 -#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control -#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1 -#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2 -#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1 -#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2 -#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request -#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask -#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1 -#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2 -#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1 -#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2 -#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control -#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1 -#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2 -#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1 -#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2 -#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1 -#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2 -#define CAN_O_NWDA1 0x00000120 // CAN New Data 1 -#define CAN_O_NWDA2 0x00000124 // CAN New Data 2 -#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending -#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending -#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid -#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test Mode Enable -#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable -#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission -#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable -#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable -#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus-Off Status -#define CAN_STS_EWARN 0x00000040 // Warning Status -#define CAN_STS_EPASS 0x00000020 // Error Passive -#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully -#define CAN_STS_TXOK 0x00000008 // Transmitted a Message - // Successfully -#define CAN_STS_LEC_M 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No Error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error -#define CAN_STS_LEC_FORM 0x00000002 // Format Error -#define CAN_STS_LEC_ACK 0x00000003 // ACK Error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error -#define CAN_STS_LEC_CRC 0x00000006 // CRC Error -#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Received Error Passive -#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter -#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter -#define CAN_ERR_REC_S 8 -#define CAN_ERR_TEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point -#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point -#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width -#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler -#define CAN_BIT_TSEG2_S 12 -#define CAN_BIT_TSEG1_S 8 -#define CAN_BIT_SJW_S 6 -#define CAN_BIT_BRP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // Receive Observation -#define CAN_TST_TX_M 0x00000060 // Transmit Control -#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point -#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low -#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High -#define CAN_TST_LBACK 0x00000010 // Loopback Mode -#define CAN_TST_SILENT 0x00000008 // Silent Mode -#define CAN_TST_BASIC 0x00000004 // Basic Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension -#define CAN_BRPE_BRPE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CRQ register. -// -//***************************************************************************** -#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF1CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CMSK register. -// -//***************************************************************************** -#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. -// -//***************************************************************************** -#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF1MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. -// -//***************************************************************************** -#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF1MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. -// -//***************************************************************************** -#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF1ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. -// -//***************************************************************************** -#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF1ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MCTL register. -// -//***************************************************************************** -#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF1MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA1 register. -// -//***************************************************************************** -#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA2 register. -// -//***************************************************************************** -#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB1 register. -// -//***************************************************************************** -#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB2 register. -// -//***************************************************************************** -#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CRQ register. -// -//***************************************************************************** -#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF2CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CMSK register. -// -//***************************************************************************** -#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. -// -//***************************************************************************** -#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF2MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. -// -//***************************************************************************** -#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF2MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. -// -//***************************************************************************** -#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF2ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. -// -//***************************************************************************** -#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF2ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MCTL register. -// -//***************************************************************************** -#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF2MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA1 register. -// -//***************************************************************************** -#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA2 register. -// -//***************************************************************************** -#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB1 register. -// -//***************************************************************************** -#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB2 register. -// -//***************************************************************************** -#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ1_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ2_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA1_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA2_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1INT register. -// -//***************************************************************************** -#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG1INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2INT register. -// -//***************************************************************************** -#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG2INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1VAL register. -// -//***************************************************************************** -#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG1VAL_MSGVAL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2VAL register. -// -//***************************************************************************** -#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG2VAL_MSGVAL_S 0 - -#endif // __HW_CAN_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_ccm.h b/bsp/tm4c129x-dk/libraries/inc/hw_ccm.h deleted file mode 100644 index 9664ceea75a5fd90c35b5755ff6249b61fb01b30..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_ccm.h +++ /dev/null @@ -1,115 +0,0 @@ -//***************************************************************************** -// -// hw_ccm.h - Macros used when accessing the CCM hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_CCM_H__ -#define __HW_CCM_H__ - -//***************************************************************************** -// -// The following are defines for the EC register offsets. -// -//***************************************************************************** -#define CCM_O_CRCCTRL 0x00000400 // CRC Control -#define CCM_O_CRCSEED 0x00000410 // CRC SEED/Context -#define CCM_O_CRCDIN 0x00000414 // CRC Data Input -#define CCM_O_CRCRSLTPP 0x00000418 // CRC Post Processing Result - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCCTRL register. -// -//***************************************************************************** -#define CCM_CRCCTRL_INIT_M 0x00006000 // CRC Initialization -#define CCM_CRCCTRL_INIT_SEED 0x00000000 // Use the CRCSEED register context - // as the starting value -#define CCM_CRCCTRL_INIT_0 0x00004000 // Initialize to all '0s' -#define CCM_CRCCTRL_INIT_1 0x00006000 // Initialize to all '1s' -#define CCM_CRCCTRL_SIZE 0x00001000 // Input Data Size -#define CCM_CRCCTRL_RESINV 0x00000200 // Result Inverse Enable -#define CCM_CRCCTRL_OBR 0x00000100 // Output Reverse Enable -#define CCM_CRCCTRL_BR 0x00000080 // Bit reverse enable -#define CCM_CRCCTRL_ENDIAN_M 0x00000030 // Endian Control -#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000 // Configuration unchanged. (B3, - // B2, B1, B0) -#define CCM_CRCCTRL_ENDIAN_SHW 0x00000010 // Bytes are swapped in half-words - // but half-words are not swapped - // (B2, B3, B0, B1) -#define CCM_CRCCTRL_ENDIAN_SHWNB \ - 0x00000020 // Half-words are swapped but bytes - // are not swapped in half-word. - // (B1, B0, B3, B2) -#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030 // Bytes are swapped in half-words - // and half-words are swapped. (B0, - // B1, B2, B3) -#define CCM_CRCCTRL_TYPE_M 0x0000000F // Operation Type -#define CCM_CRCCTRL_TYPE_P8055 0x00000000 // Polynomial 0x8005 -#define CCM_CRCCTRL_TYPE_P1021 0x00000001 // Polynomial 0x1021 -#define CCM_CRCCTRL_TYPE_P4C11DB7 \ - 0x00000002 // Polynomial 0x4C11DB7 -#define CCM_CRCCTRL_TYPE_P1EDC6F41 \ - 0x00000003 // Polynomial 0x1EDC6F41 -#define CCM_CRCCTRL_TYPE_TCPCHKSUM \ - 0x00000008 // TCP checksum - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCSEED register. -// -//***************************************************************************** -#define CCM_CRCSEED_SEED_M 0xFFFFFFFF // SEED/Context Value -#define CCM_CRCSEED_SEED_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCDIN register. -// -//***************************************************************************** -#define CCM_CRCDIN_DATAIN_M 0xFFFFFFFF // Data Input -#define CCM_CRCDIN_DATAIN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCRSLTPP -// register. -// -//***************************************************************************** -#define CCM_CRCRSLTPP_RSLTPP_M 0xFFFFFFFF // Post Processing Result -#define CCM_CRCRSLTPP_RSLTPP_S 0 - -#endif // __HW_CCM_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_comp.h b/bsp/tm4c129x-dk/libraries/inc/hw_comp.h deleted file mode 100644 index 24616aa954f64c0f6c1255e6b63013e5864e406b..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_comp.h +++ /dev/null @@ -1,211 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following are defines for the Comparator register offsets. -// -//***************************************************************************** -#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked - // Interrupt Status -#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt - // Status -#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt - // Enable -#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference - // Voltage Control -#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0 -#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0 -#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1 -#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1 -#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2 -#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2 -#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral - // Properties - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACMIS register. -// -//***************************************************************************** -#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt - // Status -#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt - // Status -#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACRIS register. -// -//***************************************************************************** -#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status -#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status -#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACINTEN register. -// -//***************************************************************************** -#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable -#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable -#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACREFCTL -// register. -// -//***************************************************************************** -#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable -#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range -#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref -#define COMP_ACREFCTL_VREF_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. -// -//***************************************************************************** -#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL0 register. -// -//***************************************************************************** -#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. -// -//***************************************************************************** -#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL1 register. -// -//***************************************************************************** -#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT2 register. -// -//***************************************************************************** -#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL2 register. -// -//***************************************************************************** -#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_PP register. -// -//***************************************************************************** -#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present -#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present -#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present -#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present -#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present -#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present - -#endif // __HW_COMP_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_des.h b/bsp/tm4c129x-dk/libraries/inc/hw_des.h deleted file mode 100644 index 775c3a745c77cd1c7cb051de186d2c1b4426ecaf..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_des.h +++ /dev/null @@ -1,310 +0,0 @@ -//***************************************************************************** -// -// hw_des.h - Macros used when accessing the DES hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_DES_H__ -#define __HW_DES_H__ - -//***************************************************************************** -// -// The following are defines for the DES register offsets. -// -//***************************************************************************** -#define DES_O_KEY3_L 0x00000000 // DES Key 3 LSW for 192-Bit Key -#define DES_O_KEY3_H 0x00000004 // DES Key 3 MSW for 192-Bit Key -#define DES_O_KEY2_L 0x00000008 // DES Key 2 LSW for 128-Bit Key -#define DES_O_KEY2_H 0x0000000C // DES Key 2 MSW for 128-Bit Key -#define DES_O_KEY1_L 0x00000010 // DES Key 1 LSW for 64-Bit Key -#define DES_O_KEY1_H 0x00000014 // DES Key 1 MSW for 64-Bit Key -#define DES_O_IV_L 0x00000018 // DES Initialization Vector -#define DES_O_IV_H 0x0000001C // DES Initialization Vector -#define DES_O_CTRL 0x00000020 // DES Control -#define DES_O_LENGTH 0x00000024 // DES Cryptographic Data Length -#define DES_O_DATA_L 0x00000028 // DES LSW Data RW -#define DES_O_DATA_H 0x0000002C // DES MSW Data RW -#define DES_O_REVISION 0x00000030 // DES Revision Number -#define DES_O_SYSCONFIG 0x00000034 // DES System Configuration -#define DES_O_SYSSTATUS 0x00000038 // DES System Status -#define DES_O_IRQSTATUS 0x0000003C // DES Interrupt Status -#define DES_O_IRQENABLE 0x00000040 // DES Interrupt Enable -#define DES_O_DIRTYBITS 0x00000044 // DES Dirty Bits -#define DES_O_DMAIM 0xFFFF8030 // DES DMA Interrupt Mask -#define DES_O_DMARIS 0xFFFF8034 // DES DMA Raw Interrupt Status -#define DES_O_DMAMIS 0xFFFF8038 // DES DMA Masked Interrupt Status -#define DES_O_DMAIC 0xFFFF803C // DES DMA Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY3_L register. -// -//***************************************************************************** -#define DES_KEY3_L_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY3_L_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY3_H register. -// -//***************************************************************************** -#define DES_KEY3_H_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY3_H_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY2_L register. -// -//***************************************************************************** -#define DES_KEY2_L_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY2_L_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY2_H register. -// -//***************************************************************************** -#define DES_KEY2_H_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY2_H_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY1_L register. -// -//***************************************************************************** -#define DES_KEY1_L_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY1_L_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY1_H register. -// -//***************************************************************************** -#define DES_KEY1_H_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY1_H_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IV_L register. -// -//***************************************************************************** -#define DES_IV_L_M 0xFFFFFFFF // Initialization vector for CBC, - // CFB modes (LSW) -#define DES_IV_L_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IV_H register. -// -//***************************************************************************** -#define DES_IV_H_M 0xFFFFFFFF // Initialization vector for CBC, - // CFB modes (MSW) -#define DES_IV_H_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_CTRL register. -// -//***************************************************************************** -#define DES_CTRL_CONTEXT 0x80000000 // If 1, this read-only status bit - // indicates that the context data - // registers can be overwritten and - // the host is permitted to write - // the next context -#define DES_CTRL_MODE_M 0x00000030 // Select CBC, ECB or CFB mode0x0: - // ECB mode0x1: CBC mode0x2: CFB - // mode0x3: reserved -#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES - // encryption/decryption -#define DES_CTRL_DIRECTION 0x00000004 // Select encryption/decryption - // 0x0: decryption is selected0x1: - // Encryption is selected -#define DES_CTRL_INPUT_READY 0x00000002 // When 1, ready to encrypt/decrypt - // data -#define DES_CTRL_OUTPUT_READY 0x00000001 // When 1, Data decrypted/encrypted - // ready -#define DES_CTRL_MODE_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_LENGTH register. -// -//***************************************************************************** -#define DES_LENGTH_M 0xFFFFFFFF // Cryptographic data length in - // bytes for all modes -#define DES_LENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DATA_L register. -// -//***************************************************************************** -#define DES_DATA_L_M 0xFFFFFFFF // Data for encryption/decryption, - // LSW -#define DES_DATA_L_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DATA_H register. -// -//***************************************************************************** -#define DES_DATA_H_M 0xFFFFFFFF // Data for encryption/decryption, - // MSW -#define DES_DATA_H_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_REVISION register. -// -//***************************************************************************** -#define DES_REVISION_M 0xFFFFFFFF // Revision number -#define DES_REVISION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_SYSCONFIG -// register. -// -//***************************************************************************** -#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ - 0x00000080 // DMA Request Context In Enable -#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ - 0x00000040 // DMA Request Data Out Enable -#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ - 0x00000020 // DMA Request Data In Enable -#define DES_SYSCONFIG_SIDLE_M 0x0000000C // Sidle mode -#define DES_SYSCONFIG_SIDLE_FORCE \ - 0x00000000 // Force-idle mode -#define DES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_SYSSTATUS -// register. -// -//***************************************************************************** -#define DES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IRQSTATUS -// register. -// -//***************************************************************************** -#define DES_IRQSTATUS_DATA_OUT 0x00000004 // This bit indicates data output - // interrupt is active and triggers - // the interrupt output -#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input - // interrupt is active and triggers - // the interrupt output -#define DES_IRQSTATUS_CONTEX_IN 0x00000001 // This bit indicates context - // interrupt is active and triggers - // the interrupt output - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IRQENABLE -// register. -// -//***************************************************************************** -#define DES_IRQENABLE_M_DATA_OUT \ - 0x00000004 // If this bit is set to 1 the data - // output interrupt is enabled -#define DES_IRQENABLE_M_DATA_IN 0x00000002 // If this bit is set to 1 the data - // input interrupt is enabled -#define DES_IRQENABLE_M_CONTEX_IN \ - 0x00000001 // If this bit is set to 1 the - // context interrupt is enabled - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DIRTYBITS -// register. -// -//***************************************************************************** -#define DES_DIRTYBITS_S_DIRTY 0x00000002 // This bit is set to 1 by the - // module if any of the DES_* - // registers is written -#define DES_DIRTYBITS_S_ACCESS 0x00000001 // This bit is set to 1 by the - // module if any of the DES_* - // registers is read - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DMAIM register. -// -//***************************************************************************** -#define DES_DMAIM_DOUT 0x00000004 // Data Out DMA Done Interrupt Mask -#define DES_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask -#define DES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DMARIS register. -// -//***************************************************************************** -#define DES_DMARIS_DOUT 0x00000004 // Data Out DMA Done Raw Interrupt - // Status -#define DES_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt - // Status -#define DES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DMAMIS register. -// -//***************************************************************************** -#define DES_DMAMIS_DOUT 0x00000004 // Data Out DMA Done Masked - // Interrupt Status -#define DES_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked - // Interrupt Status -#define DES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DMAIC register. -// -//***************************************************************************** -#define DES_DMAIC_DOUT 0x00000004 // Data Out DMA Done Interrupt - // Clear -#define DES_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear -#define DES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -#endif // __HW_DES_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_eeprom.h b/bsp/tm4c129x-dk/libraries/inc/hw_eeprom.h deleted file mode 100644 index 2118c958e6823f022b2eb088a990defe73170c94..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_eeprom.h +++ /dev/null @@ -1,251 +0,0 @@ -//***************************************************************************** -// -// hw_eeprom.h - Macros used when accessing the EEPROM controller. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_EEPROM_H__ -#define __HW_EEPROM_H__ - -//***************************************************************************** -// -// The following are defines for the EEPROM register offsets. -// -//***************************************************************************** -#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information -#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block -#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset -#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write -#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment -#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status -#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and - // Status -#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock -#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection -#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password -#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password -#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password -#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt -#define EEPROM_EEHIDE0 0x400AF050 // EEPROM Block Hide 0 -#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide -#define EEPROM_EEHIDE1 0x400AF054 // EEPROM Block Hide 1 -#define EEPROM_EEHIDE2 0x400AF058 // EEPROM Block Hide 2 -#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase -#define EEPROM_PP 0x400AFFC0 // EEPROM Peripheral Properties - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EESIZE register. -// -//***************************************************************************** -#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words -#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks -#define EEPROM_EESIZE_WORDCNT_S 0 -#define EEPROM_EESIZE_BLKCNT_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEBLOCK register. -// -//***************************************************************************** -#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block -#define EEPROM_EEBLOCK_BLOCK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEOFFSET -// register. -// -//***************************************************************************** -#define EEPROM_EEOFFSET_OFFSET_M \ - 0x0000000F // Current Address Offset -#define EEPROM_EEOFFSET_OFFSET_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EERDWR register. -// -//***************************************************************************** -#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data -#define EEPROM_EERDWR_VALUE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EERDWRINC -// register. -// -//***************************************************************************** -#define EEPROM_EERDWRINC_VALUE_M \ - 0xFFFFFFFF // EEPROM Read or Write Data with - // Increment -#define EEPROM_EERDWRINC_VALUE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEDONE register. -// -//***************************************************************************** -#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working -#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase -#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy -#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission -#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EESUPP register. -// -//***************************************************************************** -#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried -#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEUNLOCK -// register. -// -//***************************************************************************** -#define EEPROM_EEUNLOCK_UNLOCK_M \ - 0xFFFFFFFF // EEPROM Unlock - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPROT register. -// -//***************************************************************************** -#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control -#define EEPROM_EEPROT_PROT_RWNPW \ - 0x00000000 // This setting is the default. If - // there is no password, the block - // is not protected and is readable - // and writable -#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the - // block is readable or writable - // only when unlocked -#define EEPROM_EEPROT_PROT_RONPW \ - 0x00000002 // If there is no password, the - // block is readable, not writable -#define EEPROM_EEPROT_ACC 0x00000008 // Access Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS0 register. -// -//***************************************************************************** -#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS0_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS1 register. -// -//***************************************************************************** -#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS1_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS2 register. -// -//***************************************************************************** -#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS2_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEINT register. -// -//***************************************************************************** -#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE0 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE0_HN_M 0xFFFFFFFE // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE register. -// -//***************************************************************************** -#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE1 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE1_HN_M 0xFFFFFFFF // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE2 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE2_HN_M 0xFFFFFFFF // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEDBGME register. -// -//***************************************************************************** -#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase -#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key -#define EEPROM_EEDBGME_KEY_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_PP register. -// -//***************************************************************************** -#define EEPROM_PP_SIZE_M 0x0000FFFF // EEPROM Size -#define EEPROM_PP_SIZE_64 0x00000000 // 64 bytes of EEPROM -#define EEPROM_PP_SIZE_128 0x00000001 // 128 bytes of EEPROM -#define EEPROM_PP_SIZE_256 0x00000003 // 256 bytes of EEPROM -#define EEPROM_PP_SIZE_512 0x00000007 // 512 bytes of EEPROM -#define EEPROM_PP_SIZE_1K 0x0000000F // 1 KB of EEPROM -#define EEPROM_PP_SIZE_2K 0x0000001F // 2 KB of EEPROM -#define EEPROM_PP_SIZE_3K 0x0000003F // 3 KB of EEPROM -#define EEPROM_PP_SIZE_4K 0x0000007F // 4 KB of EEPROM -#define EEPROM_PP_SIZE_5K 0x000000FF // 5 KB of EEPROM -#define EEPROM_PP_SIZE_6K 0x000001FF // 6 KB of EEPROM -#define EEPROM_PP_SIZE_S 0 - -#endif // __HW_EEPROM_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_emac.h b/bsp/tm4c129x-dk/libraries/inc/hw_emac.h deleted file mode 100644 index a836da9d2120d6d7e0abab5338608ad72ac7d9a7..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_emac.h +++ /dev/null @@ -1,1874 +0,0 @@ -//***************************************************************************** -// -// hw_emac.h - Macros used when accessing the EMAC hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_EMAC_H__ -#define __HW_EMAC_H__ - -//***************************************************************************** -// -// The following are defines for the EMAC register offsets. -// -//***************************************************************************** -#define EMAC_O_CFG 0x00000000 // Ethernet MAC Configuration -#define EMAC_O_FRAMEFLTR 0x00000004 // Ethernet MAC Frame Filter -#define EMAC_O_HASHTBLH 0x00000008 // Ethernet MAC Hash Table High -#define EMAC_O_HASHTBLL 0x0000000C // Ethernet MAC Hash Table Low -#define EMAC_O_MIIADDR 0x00000010 // Ethernet MAC MII Address -#define EMAC_O_MIIDATA 0x00000014 // Ethernet MAC MII Data Register -#define EMAC_O_FLOWCTL 0x00000018 // Ethernet MAC Flow Control -#define EMAC_O_VLANTG 0x0000001C // Ethernet MAC VLAN Tag -#define EMAC_O_STATUS 0x00000024 // Ethernet MAC Status -#define EMAC_O_RWUFF 0x00000028 // Ethernet MAC Remote Wake-Up - // Frame Filter -#define EMAC_O_PMTCTLSTAT 0x0000002C // Ethernet MAC PMT Control and - // Status Register -#define EMAC_O_LPICTLSTAT 0x00000030 // Ethernet MAC Low Power Idle - // Control and Status Register -#define EMAC_O_LPITIMERCTL 0x00000034 // Ethernet MAC Low Power Idle - // Timer Control Register -#define EMAC_O_RIS 0x00000038 // Ethernet MAC Raw Interrupt - // Status -#define EMAC_O_IM 0x0000003C // Ethernet MAC Interrupt Mask -#define EMAC_O_ADDR0H 0x00000040 // Ethernet MAC Address 0 High -#define EMAC_O_ADDR0L 0x00000044 // Ethernet MAC Address 0 Low - // Register -#define EMAC_O_ADDR1H 0x00000048 // Ethernet MAC Address 1 High -#define EMAC_O_ADDR1L 0x0000004C // Ethernet MAC Address 1 Low -#define EMAC_O_ADDR2H 0x00000050 // Ethernet MAC Address 2 High -#define EMAC_O_ADDR2L 0x00000054 // Ethernet MAC Address 2 Low -#define EMAC_O_ADDR3H 0x00000058 // Ethernet MAC Address 3 High -#define EMAC_O_ADDR3L 0x0000005C // Ethernet MAC Address 3 Low -#define EMAC_O_WDOGTO 0x000000DC // Ethernet MAC Watchdog Timeout -#define EMAC_O_MMCCTRL 0x00000100 // Ethernet MAC MMC Control -#define EMAC_O_MMCRXRIS 0x00000104 // Ethernet MAC MMC Receive Raw - // Interrupt Status -#define EMAC_O_MMCTXRIS 0x00000108 // Ethernet MAC MMC Transmit Raw - // Interrupt Status -#define EMAC_O_MMCRXIM 0x0000010C // Ethernet MAC MMC Receive - // Interrupt Mask -#define EMAC_O_MMCTXIM 0x00000110 // Ethernet MAC MMC Transmit - // Interrupt Mask -#define EMAC_O_TXCNTGB 0x00000118 // Ethernet MAC Transmit Frame - // Count for Good and Bad Frames -#define EMAC_O_TXCNTSCOL 0x0000014C // Ethernet MAC Transmit Frame - // Count for Frames Transmitted - // after Single Collision -#define EMAC_O_TXCNTMCOL 0x00000150 // Ethernet MAC Transmit Frame - // Count for Frames Transmitted - // after Multiple Collisions -#define EMAC_O_TXOCTCNTG 0x00000164 // Ethernet MAC Transmit Octet - // Count Good -#define EMAC_O_RXCNTGB 0x00000180 // Ethernet MAC Receive Frame Count - // for Good and Bad Frames -#define EMAC_O_RXCNTCRCERR 0x00000194 // Ethernet MAC Receive Frame Count - // for CRC Error Frames -#define EMAC_O_RXCNTALGNERR 0x00000198 // Ethernet MAC Receive Frame Count - // for Alignment Error Frames -#define EMAC_O_RXCNTGUNI 0x000001C4 // Ethernet MAC Receive Frame Count - // for Good Unicast Frames -#define EMAC_O_VLNINCREP 0x00000584 // Ethernet MAC VLAN Tag Inclusion - // or Replacement -#define EMAC_O_VLANHASH 0x00000588 // Ethernet MAC VLAN Hash Table -#define EMAC_O_TIMSTCTRL 0x00000700 // Ethernet MAC Timestamp Control -#define EMAC_O_SUBSECINC 0x00000704 // Ethernet MAC Sub-Second - // Increment -#define EMAC_O_TIMSEC 0x00000708 // Ethernet MAC System Time - - // Seconds -#define EMAC_O_TIMNANO 0x0000070C // Ethernet MAC System Time - - // Nanoseconds -#define EMAC_O_TIMSECU 0x00000710 // Ethernet MAC System Time - - // Seconds Update -#define EMAC_O_TIMNANOU 0x00000714 // Ethernet MAC System Time - - // Nanoseconds Update -#define EMAC_O_TIMADD 0x00000718 // Ethernet MAC Timestamp Addend -#define EMAC_O_TARGSEC 0x0000071C // Ethernet MAC Target Time Seconds -#define EMAC_O_TARGNANO 0x00000720 // Ethernet MAC Target Time - // Nanoseconds -#define EMAC_O_HWORDSEC 0x00000724 // Ethernet MAC System Time-Higher - // Word Seconds -#define EMAC_O_TIMSTAT 0x00000728 // Ethernet MAC Timestamp Status -#define EMAC_O_PPSCTRL 0x0000072C // Ethernet MAC PPS Control -#define EMAC_O_PPS0INTVL 0x00000760 // Ethernet MAC PPS0 Interval -#define EMAC_O_PPS0WIDTH 0x00000764 // Ethernet MAC PPS0 Width -#define EMAC_O_DMABUSMOD 0x00000C00 // Ethernet MAC DMA Bus Mode -#define EMAC_O_TXPOLLD 0x00000C04 // Ethernet MAC Transmit Poll - // Demand -#define EMAC_O_RXPOLLD 0x00000C08 // Ethernet MAC Receive Poll Demand -#define EMAC_O_RXDLADDR 0x00000C0C // Ethernet MAC Receive Descriptor - // List Address -#define EMAC_O_TXDLADDR 0x00000C10 // Ethernet MAC Transmit Descriptor - // List Address -#define EMAC_O_DMARIS 0x00000C14 // Ethernet MAC DMA Interrupt - // Status -#define EMAC_O_DMAOPMODE 0x00000C18 // Ethernet MAC DMA Operation Mode -#define EMAC_O_DMAIM 0x00000C1C // Ethernet MAC DMA Interrupt Mask - // Register -#define EMAC_O_MFBOC 0x00000C20 // Ethernet MAC Missed Frame and - // Buffer Overflow Counter -#define EMAC_O_RXINTWDT 0x00000C24 // Ethernet MAC Receive Interrupt - // Watchdog Timer -#define EMAC_O_HOSTXDESC 0x00000C48 // Ethernet MAC Current Host - // Transmit Descriptor -#define EMAC_O_HOSRXDESC 0x00000C4C // Ethernet MAC Current Host - // Receive Descriptor -#define EMAC_O_HOSTXBA 0x00000C50 // Ethernet MAC Current Host - // Transmit Buffer Address -#define EMAC_O_HOSRXBA 0x00000C54 // Ethernet MAC Current Host - // Receive Buffer Address -#define EMAC_O_PP 0x00000FC0 // Ethernet MAC Peripheral Property - // Register -#define EMAC_O_PC 0x00000FC4 // Ethernet MAC Peripheral - // Configuration Register -#define EMAC_O_CC 0x00000FC8 // Ethernet MAC Clock Configuration - // Register -#define EMAC_O_EPHYRIS 0x00000FD0 // Ethernet PHY Raw Interrupt - // Status -#define EMAC_O_EPHYIM 0x00000FD4 // Ethernet PHY Interrupt Mask -#define EMAC_O_EPHYMISC 0x00000FD8 // Ethernet PHY Masked Interrupt - // Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_CFG register. -// -//***************************************************************************** -#define EMAC_CFG_TWOKPEN 0x08000000 // IEEE 802 -#define EMAC_CFG_CST 0x02000000 // CRC Stripping for Type Frames -#define EMAC_CFG_WDDIS 0x00800000 // Watchdog Disable -#define EMAC_CFG_JD 0x00400000 // Jabber Disable -#define EMAC_CFG_JFEN 0x00100000 // Jumbo Frame Enable -#define EMAC_CFG_IFG_M 0x000E0000 // Inter-Frame Gap (IFG) -#define EMAC_CFG_IFG_96 0x00000000 // 96 bit times -#define EMAC_CFG_IFG_88 0x00020000 // 88 bit times -#define EMAC_CFG_IFG_80 0x00040000 // 80 bit times -#define EMAC_CFG_IFG_72 0x00060000 // 72 bit times -#define EMAC_CFG_IFG_64 0x00080000 // 64 bit times -#define EMAC_CFG_IFG_56 0x000A0000 // 56 bit times -#define EMAC_CFG_IFG_48 0x000C0000 // 48 bit times -#define EMAC_CFG_IFG_40 0x000E0000 // 40 bit times -#define EMAC_CFG_DISCRS 0x00010000 // Disable Carrier Sense During - // Transmission -#define EMAC_CFG_PS 0x00008000 // Port Select -#define EMAC_CFG_FES 0x00004000 // Speed -#define EMAC_CFG_DRO 0x00002000 // Disable Receive Own -#define EMAC_CFG_LOOPBM 0x00001000 // Loopback Mode -#define EMAC_CFG_DUPM 0x00000800 // Duplex Mode -#define EMAC_CFG_IPC 0x00000400 // Checksum Offload -#define EMAC_CFG_DR 0x00000200 // Disable Retry -#define EMAC_CFG_ACS 0x00000080 // Automatic Pad or CRC Stripping -#define EMAC_CFG_BL_M 0x00000060 // Back-Off Limit -#define EMAC_CFG_BL_1024 0x00000000 // k = min (n,10) -#define EMAC_CFG_BL_256 0x00000020 // k = min (n,8) -#define EMAC_CFG_BL_8 0x00000040 // k = min (n,4) -#define EMAC_CFG_BL_2 0x00000060 // k = min (n,1) -#define EMAC_CFG_DC 0x00000010 // Deferral Check -#define EMAC_CFG_TE 0x00000008 // Transmitter Enable -#define EMAC_CFG_RE 0x00000004 // Receiver Enable -#define EMAC_CFG_PRELEN_M 0x00000003 // Preamble Length for Transmit - // Frames -#define EMAC_CFG_PRELEN_7 0x00000000 // 7 bytes of preamble -#define EMAC_CFG_PRELEN_5 0x00000001 // 5 bytes of preamble -#define EMAC_CFG_PRELEN_3 0x00000002 // 3 bytes of preamble - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_FRAMEFLTR -// register. -// -//***************************************************************************** -#define EMAC_FRAMEFLTR_RA 0x80000000 // Receive All -#define EMAC_FRAMEFLTR_VTFE 0x00010000 // VLAN Tag Filter Enable -#define EMAC_FRAMEFLTR_HPF 0x00000400 // Hash or Perfect Filter -#define EMAC_FRAMEFLTR_SAF 0x00000200 // Source Address Filter Enable -#define EMAC_FRAMEFLTR_SAIF 0x00000100 // Source Address (SA) Inverse - // Filtering -#define EMAC_FRAMEFLTR_PCF_M 0x000000C0 // Pass Control Frames -#define EMAC_FRAMEFLTR_PCF_ALL 0x00000000 // The MAC filters all control - // frames from reaching application -#define EMAC_FRAMEFLTR_PCF_PAUSE \ - 0x00000040 // MAC forwards all control frames - // except PAUSE control frames to - // application even if they fail - // the address filter -#define EMAC_FRAMEFLTR_PCF_NONE 0x00000080 // MAC forwards all control frames - // to application even if they fail - // the address Filter -#define EMAC_FRAMEFLTR_PCF_ADDR 0x000000C0 // MAC forwards control frames that - // pass the address Filter -#define EMAC_FRAMEFLTR_DBF 0x00000020 // Disable Broadcast Frames -#define EMAC_FRAMEFLTR_PM 0x00000010 // Pass All Multicast -#define EMAC_FRAMEFLTR_DAIF 0x00000008 // Destination Address (DA) Inverse - // Filtering -#define EMAC_FRAMEFLTR_HMC 0x00000004 // Hash Multicast -#define EMAC_FRAMEFLTR_HUC 0x00000002 // Hash Unicast -#define EMAC_FRAMEFLTR_PR 0x00000001 // Promiscuous Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HASHTBLH -// register. -// -//***************************************************************************** -#define EMAC_HASHTBLH_HTH_M 0xFFFFFFFF // Hash Table High -#define EMAC_HASHTBLH_HTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HASHTBLL -// register. -// -//***************************************************************************** -#define EMAC_HASHTBLL_HTL_M 0xFFFFFFFF // Hash Table Low -#define EMAC_HASHTBLL_HTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MIIADDR register. -// -//***************************************************************************** -#define EMAC_MIIADDR_PLA_M 0x0000F800 // Physical Layer Address -#define EMAC_MIIADDR_MII_M 0x000007C0 // MII Register -#define EMAC_MIIADDR_CR_M 0x0000003C // Clock Reference Frequency - // Selection -#define EMAC_MIIADDR_CR_60_100 0x00000000 // The frequency of the System - // Clock is 60 to 100 MHz providing - // a MDIO clock of SYSCLK/42 -#define EMAC_MIIADDR_CR_100_150 0x00000004 // The frequency of the System - // Clock is 100 to 150 MHz - // providing a MDIO clock of - // SYSCLK/62 -#define EMAC_MIIADDR_CR_20_35 0x00000008 // The frequency of the System - // Clock is 20-35 MHz providing a - // MDIO clock of System Clock/16 -#define EMAC_MIIADDR_CR_35_60 0x0000000C // The frequency of the System - // Clock is 35 to 60 MHz providing - // a MDIO clock of System Clock/26 -#define EMAC_MIIADDR_MIIW 0x00000002 // MII Write -#define EMAC_MIIADDR_MIIB 0x00000001 // MII Busy -#define EMAC_MIIADDR_PLA_S 11 -#define EMAC_MIIADDR_MII_S 6 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MIIDATA register. -// -//***************************************************************************** -#define EMAC_MIIDATA_DATA_M 0x0000FFFF // MII Data -#define EMAC_MIIDATA_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_FLOWCTL register. -// -//***************************************************************************** -#define EMAC_FLOWCTL_PT_M 0xFFFF0000 // Pause Time -#define EMAC_FLOWCTL_DZQP 0x00000080 // Disable Zero-Quanta Pause -#define EMAC_FLOWCTL_UP 0x00000008 // Unicast Pause Frame Detect -#define EMAC_FLOWCTL_RFE 0x00000004 // Receive Flow Control Enable -#define EMAC_FLOWCTL_TFE 0x00000002 // Transmit Flow Control Enable -#define EMAC_FLOWCTL_FCBBPA 0x00000001 // Flow Control Busy or - // Back-pressure Activate -#define EMAC_FLOWCTL_PT_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_VLANTG register. -// -//***************************************************************************** -#define EMAC_VLANTG_VTHM 0x00080000 // VLAN Tag Hash Table Match Enable -#define EMAC_VLANTG_ESVL 0x00040000 // Enable S-VLAN -#define EMAC_VLANTG_VTIM 0x00020000 // VLAN Tag Inverse Match Enable -#define EMAC_VLANTG_ETV 0x00010000 // Enable 12-Bit VLAN Tag - // Comparison -#define EMAC_VLANTG_VL_M 0x0000FFFF // VLAN Tag Identifier for Receive - // Frames -#define EMAC_VLANTG_VL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_STATUS register. -// -//***************************************************************************** -#define EMAC_STATUS_TXFF 0x02000000 // TX/RX Controller TX FIFO Full - // Status -#define EMAC_STATUS_TXFE 0x01000000 // TX/RX Controller TX FIFO Not - // Empty Status -#define EMAC_STATUS_TWC 0x00400000 // TX/RX Controller TX FIFO Write - // Controller Active Status -#define EMAC_STATUS_TRC_M 0x00300000 // TX/RX Controller's TX FIFO Read - // Controller Status -#define EMAC_STATUS_TRC_IDLE 0x00000000 // IDLE state -#define EMAC_STATUS_TRC_READ 0x00100000 // READ state (transferring data to - // MAC transmitter) -#define EMAC_STATUS_TRC_WAIT 0x00200000 // Waiting for TX Status from MAC - // transmitter -#define EMAC_STATUS_TRC_WRFLUSH 0x00300000 // Writing the received TX Status - // or flushing the TX FIFO -#define EMAC_STATUS_TXPAUSED 0x00080000 // MAC Transmitter PAUSE -#define EMAC_STATUS_TFC_M 0x00060000 // MAC Transmit Frame Controller - // Status -#define EMAC_STATUS_TFC_IDLE 0x00000000 // IDLE state -#define EMAC_STATUS_TFC_STATUS 0x00020000 // Waiting for status of previous - // frame or IFG or backoff period - // to be over -#define EMAC_STATUS_TFC_PAUSE 0x00040000 // Generating and transmitting a - // PAUSE control frame (in the - // full-duplex mode) -#define EMAC_STATUS_TFC_INPUT 0x00060000 // Transferring input frame for - // transmission -#define EMAC_STATUS_TPE 0x00010000 // MAC MII Transmit Protocol Engine - // Status -#define EMAC_STATUS_RXF_M 0x00000300 // TX/RX Controller RX FIFO - // Fill-level Status -#define EMAC_STATUS_RXF_EMPTY 0x00000000 // RX FIFO Empty -#define EMAC_STATUS_RXF_BELOW 0x00000100 // RX FIFO fill level is below the - // flow-control deactivate - // threshold -#define EMAC_STATUS_RXF_ABOVE 0x00000200 // RX FIFO fill level is above the - // flow-control activate threshold -#define EMAC_STATUS_RXF_FULL 0x00000300 // RX FIFO Full -#define EMAC_STATUS_RRC_M 0x00000060 // TX/RX Controller Read Controller - // State -#define EMAC_STATUS_RRC_IDLE 0x00000000 // IDLE state -#define EMAC_STATUS_RRC_STATUS 0x00000020 // Reading frame data -#define EMAC_STATUS_RRC_DATA 0x00000040 // Reading frame status (or - // timestamp) -#define EMAC_STATUS_RRC_FLUSH 0x00000060 // Flushing the frame data and - // status -#define EMAC_STATUS_RWC 0x00000010 // TX/RX Controller RX FIFO Write - // Controller Active Status -#define EMAC_STATUS_RFCFC_M 0x00000006 // MAC Receive Frame Controller - // FIFO Status -#define EMAC_STATUS_RPE 0x00000001 // MAC MII Receive Protocol Engine - // Status -#define EMAC_STATUS_RFCFC_S 1 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RWUFF register. -// -//***************************************************************************** -#define EMAC_RWUFF_WAKEUPFIL_M 0xFFFFFFFF // Remote Wake-Up Frame Filter -#define EMAC_RWUFF_WAKEUPFIL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PMTCTLSTAT -// register. -// -//***************************************************************************** -#define EMAC_PMTCTLSTAT_WUPFRRST \ - 0x80000000 // Wake-Up Frame Filter Register - // Pointer Reset -#define EMAC_PMTCTLSTAT_RWKPTR_M \ - 0x07000000 // Remote Wake-Up FIFO Pointer -#define EMAC_PMTCTLSTAT_GLBLUCAST \ - 0x00000200 // Global Unicast -#define EMAC_PMTCTLSTAT_WUPRX 0x00000040 // Wake-Up Frame Received -#define EMAC_PMTCTLSTAT_MGKPRX 0x00000020 // Magic Packet Received -#define EMAC_PMTCTLSTAT_WUPFREN 0x00000004 // Wake-Up Frame Enable -#define EMAC_PMTCTLSTAT_MGKPKTEN \ - 0x00000002 // Magic Packet Enable -#define EMAC_PMTCTLSTAT_PWRDWN 0x00000001 // Power Down -#define EMAC_PMTCTLSTAT_RWKPTR_S \ - 24 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_LPICTLSTAT -// register. -// -//***************************************************************************** -#define EMAC_LPICTLSTAT_LPITXA 0x00080000 // LPI TX Automate -#define EMAC_LPICTLSTAT_PLSEN 0x00040000 // PHY Link Status Enable -#define EMAC_LPICTLSTAT_PLS 0x00020000 // PHY Link Status -#define EMAC_LPICTLSTAT_LPIEN 0x00010000 // LPI Enable -#define EMAC_LPICTLSTAT_RLPIST 0x00000200 // Receive LPI State -#define EMAC_LPICTLSTAT_TLPIST 0x00000100 // Transmit LPI State -#define EMAC_LPICTLSTAT_RLPIEX 0x00000008 // Receive LPI Exit -#define EMAC_LPICTLSTAT_RLPIEN 0x00000004 // Receive LPI Entry -#define EMAC_LPICTLSTAT_TLPIEX 0x00000002 // Transmit LPI Exit -#define EMAC_LPICTLSTAT_TLPIEN 0x00000001 // Transmit LPI Entry - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_LPITIMERCTL -// register. -// -//***************************************************************************** -#define EMAC_LPITIMERCTL_LST_M 0x03FF0000 // Low Power Idle LS Timer -#define EMAC_LPITIMERCTL_LST_S 16 -#define EMAC_LPITIMERCTL_TWT_M 0x0000FFFF // Low Power Idle TW Timer -#define EMAC_LPITIMERCTL_TWT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RIS register. -// -//***************************************************************************** -#define EMAC_RIS_LPI 0x00000400 // LPI Interrupt Status -#define EMAC_RIS_TS 0x00000200 // Timestamp Interrupt Status -#define EMAC_RIS_MMCTX 0x00000040 // MMC Transmit Interrupt Status -#define EMAC_RIS_MMCRX 0x00000020 // MMC Receive Interrupt Status -#define EMAC_RIS_MMC 0x00000010 // MMC Interrupt Status -#define EMAC_RIS_PMT 0x00000008 // PMT Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_IM register. -// -//***************************************************************************** -#define EMAC_IM_LPI 0x00000400 // LPI Interrupt Mask -#define EMAC_IM_TSI 0x00000200 // Timestamp Interrupt Mask -#define EMAC_IM_PMT 0x00000008 // PMT Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR0H register. -// -//***************************************************************************** -#define EMAC_ADDR0H_AE 0x80000000 // Address Enable -#define EMAC_ADDR0H_ADDRHI_M 0x0000FFFF // MAC Address0 [47:32] -#define EMAC_ADDR0H_ADDRHI_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR0L register. -// -//***************************************************************************** -#define EMAC_ADDR0L_ADDRLO_M 0xFFFFFFFF // MAC Address0 [31:0] -#define EMAC_ADDR0L_ADDRLO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR1H register. -// -//***************************************************************************** -#define EMAC_ADDR1H_AE 0x80000000 // Address Enable -#define EMAC_ADDR1H_SA 0x40000000 // Source Address -#define EMAC_ADDR1H_MBC_M 0x3F000000 // Mask Byte Control -#define EMAC_ADDR1H_ADDRHI_M 0x0000FFFF // MAC Address1 [47:32] -#define EMAC_ADDR1H_MBC_S 24 -#define EMAC_ADDR1H_ADDRHI_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR1L register. -// -//***************************************************************************** -#define EMAC_ADDR1L_ADDRLO_M 0xFFFFFFFF // MAC Address1 [31:0] -#define EMAC_ADDR1L_ADDRLO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR2H register. -// -//***************************************************************************** -#define EMAC_ADDR2H_AE 0x80000000 // Address Enable -#define EMAC_ADDR2H_SA 0x40000000 // Source Address -#define EMAC_ADDR2H_MBC_M 0x3F000000 // Mask Byte Control -#define EMAC_ADDR2H_ADDRHI_M 0x0000FFFF // MAC Address2 [47:32] -#define EMAC_ADDR2H_MBC_S 24 -#define EMAC_ADDR2H_ADDRHI_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR2L register. -// -//***************************************************************************** -#define EMAC_ADDR2L_ADDRLO_M 0xFFFFFFFF // MAC Address2 [31:0] -#define EMAC_ADDR2L_ADDRLO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR3H register. -// -//***************************************************************************** -#define EMAC_ADDR3H_AE 0x80000000 // Address Enable -#define EMAC_ADDR3H_SA 0x40000000 // Source Address -#define EMAC_ADDR3H_MBC_M 0x3F000000 // Mask Byte Control -#define EMAC_ADDR3H_ADDRHI_M 0x0000FFFF // MAC Address3 [47:32] -#define EMAC_ADDR3H_MBC_S 24 -#define EMAC_ADDR3H_ADDRHI_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR3L register. -// -//***************************************************************************** -#define EMAC_ADDR3L_ADDRLO_M 0xFFFFFFFF // MAC Address3 [31:0] -#define EMAC_ADDR3L_ADDRLO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_WDOGTO register. -// -//***************************************************************************** -#define EMAC_WDOGTO_PWE 0x00010000 // Programmable Watchdog Enable -#define EMAC_WDOGTO_WTO_M 0x00003FFF // Watchdog Timeout -#define EMAC_WDOGTO_WTO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MMCCTRL register. -// -//***************************************************************************** -#define EMAC_MMCCTRL_UCDBC 0x00000100 // Update MMC Counters for Dropped - // Broadcast Frames -#define EMAC_MMCCTRL_CNTPRSTLVL 0x00000020 // Full/Half Preset Level Value -#define EMAC_MMCCTRL_CNTPRST 0x00000010 // Counters Preset -#define EMAC_MMCCTRL_CNTFREEZ 0x00000008 // MMC Counter Freeze -#define EMAC_MMCCTRL_RSTONRD 0x00000004 // Reset on Read -#define EMAC_MMCCTRL_CNTSTPRO 0x00000002 // Counters Stop Rollover -#define EMAC_MMCCTRL_CNTRST 0x00000001 // Counters Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MMCRXRIS -// register. -// -//***************************************************************************** -#define EMAC_MMCRXRIS_UCGF 0x00020000 // MMC Receive Unicast Good Frame - // Counter Interrupt Status -#define EMAC_MMCRXRIS_ALGNERR 0x00000040 // MMC Receive Alignment Error - // Frame Counter Interrupt Status -#define EMAC_MMCRXRIS_CRCERR 0x00000020 // MMC Receive CRC Error Frame - // Counter Interrupt Status -#define EMAC_MMCRXRIS_GBF 0x00000001 // MMC Receive Good Bad Frame - // Counter Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MMCTXRIS -// register. -// -//***************************************************************************** -#define EMAC_MMCTXRIS_OCTCNT 0x00100000 // Octet Counter Interrupt Status -#define EMAC_MMCTXRIS_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision - // Good Frame Counter Interrupt - // Status -#define EMAC_MMCTXRIS_SCOLLGF 0x00004000 // MMC Transmit Single Collision - // Good Frame Counter Interrupt - // Status -#define EMAC_MMCTXRIS_GBF 0x00000002 // MMC Transmit Good Bad Frame - // Counter Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MMCRXIM register. -// -//***************************************************************************** -#define EMAC_MMCRXIM_UCGF 0x00020000 // MMC Receive Unicast Good Frame - // Counter Interrupt Mask -#define EMAC_MMCRXIM_ALGNERR 0x00000040 // MMC Receive Alignment Error - // Frame Counter Interrupt Mask -#define EMAC_MMCRXIM_CRCERR 0x00000020 // MMC Receive CRC Error Frame - // Counter Interrupt Mask -#define EMAC_MMCRXIM_GBF 0x00000001 // MMC Receive Good Bad Frame - // Counter Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MMCTXIM register. -// -//***************************************************************************** -#define EMAC_MMCTXIM_OCTCNT 0x00100000 // MMC Transmit Good Octet Counter - // Interrupt Mask -#define EMAC_MMCTXIM_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision - // Good Frame Counter Interrupt - // Mask -#define EMAC_MMCTXIM_SCOLLGF 0x00004000 // MMC Transmit Single Collision - // Good Frame Counter Interrupt - // Mask -#define EMAC_MMCTXIM_GBF 0x00000002 // MMC Transmit Good Bad Frame - // Counter Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXCNTGB register. -// -//***************************************************************************** -#define EMAC_TXCNTGB_TXFRMGB_M 0xFFFFFFFF // This field indicates the number - // of good and bad frames - // transmitted, exclusive of - // retried frames -#define EMAC_TXCNTGB_TXFRMGB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXCNTSCOL -// register. -// -//***************************************************************************** -#define EMAC_TXCNTSCOL_TXSNGLCOLG_M \ - 0xFFFFFFFF // This field indicates the number - // of successfully transmitted - // frames after a single collision - // in the half-duplex mode -#define EMAC_TXCNTSCOL_TXSNGLCOLG_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXCNTMCOL -// register. -// -//***************************************************************************** -#define EMAC_TXCNTMCOL_TXMULTCOLG_M \ - 0xFFFFFFFF // This field indicates the number - // of successfully transmitted - // frames after multiple collisions - // in the half-duplex mode -#define EMAC_TXCNTMCOL_TXMULTCOLG_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXOCTCNTG -// register. -// -//***************************************************************************** -#define EMAC_TXOCTCNTG_TXOCTG_M 0xFFFFFFFF // This field indicates the number - // of bytes transmitted, exclusive - // of preamble, in good frames -#define EMAC_TXOCTCNTG_TXOCTG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXCNTGB register. -// -//***************************************************************************** -#define EMAC_RXCNTGB_RXFRMGB_M 0xFFFFFFFF // This field indicates the number - // of received good and bad frames -#define EMAC_RXCNTGB_RXFRMGB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXCNTCRCERR -// register. -// -//***************************************************************************** -#define EMAC_RXCNTCRCERR_RXCRCERR_M \ - 0xFFFFFFFF // This field indicates the number - // of frames received with CRC - // error -#define EMAC_RXCNTCRCERR_RXCRCERR_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXCNTALGNERR -// register. -// -//***************************************************************************** -#define EMAC_RXCNTALGNERR_RXALGNERR_M \ - 0xFFFFFFFF // This field indicates the number - // of frames received with - // alignment (dribble) error -#define EMAC_RXCNTALGNERR_RXALGNERR_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXCNTGUNI -// register. -// -//***************************************************************************** -#define EMAC_RXCNTGUNI_RXUCASTG_M \ - 0xFFFFFFFF // This field indicates the number - // of received good unicast frames -#define EMAC_RXCNTGUNI_RXUCASTG_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_VLNINCREP -// register. -// -//***************************************************************************** -#define EMAC_VLNINCREP_CSVL 0x00080000 // C-VLAN or S-VLAN -#define EMAC_VLNINCREP_VLP 0x00040000 // VLAN Priority Control -#define EMAC_VLNINCREP_VLC_M 0x00030000 // VLAN Tag Control in Transmit - // Frames -#define EMAC_VLNINCREP_VLC_NONE 0x00000000 // No VLAN tag deletion, insertion, - // or replacement -#define EMAC_VLNINCREP_VLC_TAGDEL \ - 0x00010000 // VLAN tag deletion -#define EMAC_VLNINCREP_VLC_TAGINS \ - 0x00020000 // VLAN tag insertion -#define EMAC_VLNINCREP_VLC_TAGREP \ - 0x00030000 // VLAN tag replacement -#define EMAC_VLNINCREP_VLT_M 0x0000FFFF // VLAN Tag for Transmit Frames -#define EMAC_VLNINCREP_VLT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_VLANHASH -// register. -// -//***************************************************************************** -#define EMAC_VLANHASH_VLHT_M 0x0000FFFF // VLAN Hash Table -#define EMAC_VLANHASH_VLHT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMSTCTRL -// register. -// -//***************************************************************************** -#define EMAC_TIMSTCTRL_PTPFLTR 0x00040000 // Enable MAC address for PTP Frame - // Filtering -#define EMAC_TIMSTCTRL_SELPTP_M 0x00030000 // Select PTP packets for Taking - // Snapshots -#define EMAC_TIMSTCTRL_TSMAST 0x00008000 // Enable Snapshot for Messages - // Relevant to Master -#define EMAC_TIMSTCTRL_TSEVNT 0x00004000 // Enable Timestamp Snapshot for - // Event Messages -#define EMAC_TIMSTCTRL_PTPIPV4 0x00002000 // Enable Processing of PTP Frames - // Sent over IPv4-UDP -#define EMAC_TIMSTCTRL_PTPIPV6 0x00001000 // Enable Processing of PTP Frames - // Sent Over IPv6-UDP -#define EMAC_TIMSTCTRL_PTPETH 0x00000800 // Enable Processing of PTP Over - // Ethernet Frames -#define EMAC_TIMSTCTRL_PTPVER2 0x00000400 // Enable PTP Packet Processing For - // Version 2 Format -#define EMAC_TIMSTCTRL_DGTLBIN 0x00000200 // Timestamp Digital or Binary - // Rollover Control -#define EMAC_TIMSTCTRL_ALLF 0x00000100 // Enable Timestamp For All Frames -#define EMAC_TIMSTCTRL_ADDREGUP 0x00000020 // Addend Register Update -#define EMAC_TIMSTCTRL_INTTRIG 0x00000010 // Timestamp Interrupt Trigger - // Enable -#define EMAC_TIMSTCTRL_TSUPDT 0x00000008 // Timestamp Update -#define EMAC_TIMSTCTRL_TSINIT 0x00000004 // Timestamp Initialize -#define EMAC_TIMSTCTRL_TSFCUPDT 0x00000002 // Timestamp Fine or Coarse Update -#define EMAC_TIMSTCTRL_TSEN 0x00000001 // Timestamp Enable -#define EMAC_TIMSTCTRL_SELPTP_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_SUBSECINC -// register. -// -//***************************************************************************** -#define EMAC_SUBSECINC_SSINC_M 0x000000FF // Sub-second Increment Value -#define EMAC_SUBSECINC_SSINC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMSEC register. -// -//***************************************************************************** -#define EMAC_TIMSEC_TSS_M 0xFFFFFFFF // Timestamp Second -#define EMAC_TIMSEC_TSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMNANO register. -// -//***************************************************************************** -#define EMAC_TIMNANO_TSSS_M 0x7FFFFFFF // Timestamp Sub-Seconds -#define EMAC_TIMNANO_TSSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMSECU register. -// -//***************************************************************************** -#define EMAC_TIMSECU_TSS_M 0xFFFFFFFF // Timestamp Second -#define EMAC_TIMSECU_TSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMNANOU -// register. -// -//***************************************************************************** -#define EMAC_TIMNANOU_ADDSUB 0x80000000 // Add or subtract time -#define EMAC_TIMNANOU_TSSS_M 0x7FFFFFFF // Timestamp Sub-Second -#define EMAC_TIMNANOU_TSSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMADD register. -// -//***************************************************************************** -#define EMAC_TIMADD_TSAR_M 0xFFFFFFFF // Timestamp Addend Register -#define EMAC_TIMADD_TSAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TARGSEC register. -// -//***************************************************************************** -#define EMAC_TARGSEC_TSTR_M 0xFFFFFFFF // Target Time Seconds Register -#define EMAC_TARGSEC_TSTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TARGNANO -// register. -// -//***************************************************************************** -#define EMAC_TARGNANO_TRGTBUSY 0x80000000 // Target Time Register Busy -#define EMAC_TARGNANO_TTSLO_M 0x7FFFFFFF // Target Timestamp Low Register -#define EMAC_TARGNANO_TTSLO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HWORDSEC -// register. -// -//***************************************************************************** -#define EMAC_HWORDSEC_TSHWR_M 0x0000FFFF // Target Timestamp Higher Word - // Register -#define EMAC_HWORDSEC_TSHWR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMSTAT register. -// -//***************************************************************************** -#define EMAC_TIMSTAT_TSTARGT 0x00000002 // Timestamp Target Time Reached -#define EMAC_TIMSTAT_TSSOVF 0x00000001 // Timestamp Seconds Overflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PPSCTRL register. -// -//***************************************************************************** -#define EMAC_PPSCTRL_TRGMODS0_M 0x00000060 // Target Time Register Mode for - // PPS0 Output -#define EMAC_PPSCTRL_TRGMODS0_INTONLY \ - 0x00000000 // Indicates that the Target Time - // registers are programmed only - // for generating the interrupt - // event -#define EMAC_PPSCTRL_TRGMODS0_INTPPS0 \ - 0x00000040 // Indicates that the Target Time - // registers are programmed for - // generating the interrupt event - // and starting or stopping the - // generation of the EN0PPS output - // signal -#define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY \ - 0x00000060 // Indicates that the Target Time - // registers are programmed only - // for starting or stopping the - // generation of the EN0PPS output - // signal. No interrupt is asserted -#define EMAC_PPSCTRL_PPSEN0 0x00000010 // Flexible PPS Output Mode Enable -#define EMAC_PPSCTRL_PPSCTRL_M 0x0000000F // EN0PPS Output Frequency Control - // (PPSCTRL) or Command Control - // (PPSCMD) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PPS0INTVL -// register. -// -//***************************************************************************** -#define EMAC_PPS0INTVL_PPS0INT_M \ - 0xFFFFFFFF // PPS0 Output Signal Interval -#define EMAC_PPS0INTVL_PPS0INT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PPS0WIDTH -// register. -// -//***************************************************************************** -#define EMAC_PPS0WIDTH_M 0xFFFFFFFF // EN0PPS Output Signal Width -#define EMAC_PPS0WIDTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_DMABUSMOD -// register. -// -//***************************************************************************** -#define EMAC_DMABUSMOD_RIB 0x80000000 // Rebuild Burst -#define EMAC_DMABUSMOD_TXPR 0x08000000 // Transmit Priority -#define EMAC_DMABUSMOD_MB 0x04000000 // Mixed Burst -#define EMAC_DMABUSMOD_AAL 0x02000000 // Address Aligned Beats -#define EMAC_DMABUSMOD_8XPBL 0x01000000 // 8 x Programmable Burst Length - // (PBL) Mode -#define EMAC_DMABUSMOD_USP 0x00800000 // Use Separate Programmable Burst - // Length (PBL) -#define EMAC_DMABUSMOD_RPBL_M 0x007E0000 // RX DMA Programmable Burst Length - // (PBL) -#define EMAC_DMABUSMOD_FB 0x00010000 // Fixed Burst -#define EMAC_DMABUSMOD_PR_M 0x0000C000 // Priority Ratio -#define EMAC_DMABUSMOD_PBL_M 0x00003F00 // Programmable Burst Length -#define EMAC_DMABUSMOD_ATDS 0x00000080 // Alternate Descriptor Size -#define EMAC_DMABUSMOD_DSL_M 0x0000007C // Descriptor Skip Length -#define EMAC_DMABUSMOD_DA 0x00000002 // DMA Arbitration Scheme -#define EMAC_DMABUSMOD_SWR 0x00000001 // DMA Software Reset -#define EMAC_DMABUSMOD_RPBL_S 17 -#define EMAC_DMABUSMOD_PR_S 14 -#define EMAC_DMABUSMOD_PBL_S 8 -#define EMAC_DMABUSMOD_DSL_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXPOLLD register. -// -//***************************************************************************** -#define EMAC_TXPOLLD_TPD_M 0xFFFFFFFF // Transmit Poll Demand -#define EMAC_TXPOLLD_TPD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXPOLLD register. -// -//***************************************************************************** -#define EMAC_RXPOLLD_RPD_M 0xFFFFFFFF // Receive Poll Demand -#define EMAC_RXPOLLD_RPD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXDLADDR -// register. -// -//***************************************************************************** -#define EMAC_RXDLADDR_STRXLIST_M \ - 0xFFFFFFFC // Start of Receive List -#define EMAC_RXDLADDR_STRXLIST_S \ - 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXDLADDR -// register. -// -//***************************************************************************** -#define EMAC_TXDLADDR_TXDLADDR_M \ - 0xFFFFFFFC // Start of Transmit List Base - // Address -#define EMAC_TXDLADDR_TXDLADDR_S \ - 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_DMARIS register. -// -//***************************************************************************** -#define EMAC_DMARIS_LPI 0x40000000 // LPI Trigger Interrupt Status -#define EMAC_DMARIS_TT 0x20000000 // Timestamp Trigger Interrupt - // Status -#define EMAC_DMARIS_PMT 0x10000000 // MAC PMT Interrupt Status -#define EMAC_DMARIS_MMC 0x08000000 // MAC MMC Interrupt -#define EMAC_DMARIS_AE_M 0x03800000 // Access Error -#define EMAC_DMARIS_AE_RXDMAWD 0x00000000 // Error during RX DMA Write Data - // Transfer -#define EMAC_DMARIS_AE_TXDMARD 0x01800000 // Error during TX DMA Read Data - // Transfer -#define EMAC_DMARIS_AE_RXDMADW 0x02000000 // Error during RX DMA Descriptor - // Write Access -#define EMAC_DMARIS_AE_TXDMADW 0x02800000 // Error during TX DMA Descriptor - // Write Access -#define EMAC_DMARIS_AE_RXDMADR 0x03000000 // Error during RX DMA Descriptor - // Read Access -#define EMAC_DMARIS_AE_TXDMADR 0x03800000 // Error during TX DMA Descriptor - // Read Access -#define EMAC_DMARIS_TS_M 0x00700000 // Transmit Process State -#define EMAC_DMARIS_TS_STOP 0x00000000 // Stopped; Reset or Stop transmit - // command processed -#define EMAC_DMARIS_TS_RUNTXTD 0x00100000 // Running; Fetching transmit - // transfer descriptor -#define EMAC_DMARIS_TS_STATUS 0x00200000 // Running; Waiting for status -#define EMAC_DMARIS_TS_RUNTX 0x00300000 // Running; Reading data from host - // memory buffer and queuing it to - // transmit buffer (TX FIFO) -#define EMAC_DMARIS_TS_TSTAMP 0x00400000 // Writing Timestamp -#define EMAC_DMARIS_TS_SUSPEND 0x00600000 // Suspended; Transmit descriptor - // unavailable or transmit buffer - // underflow -#define EMAC_DMARIS_TS_RUNCTD 0x00700000 // Running; Closing transmit - // descriptor -#define EMAC_DMARIS_RS_M 0x000E0000 // Received Process State -#define EMAC_DMARIS_RS_STOP 0x00000000 // Stopped: Reset or stop receive - // command issued -#define EMAC_DMARIS_RS_RUNRXTD 0x00020000 // Running: Fetching receive - // transfer descriptor -#define EMAC_DMARIS_RS_RUNRXD 0x00060000 // Running: Waiting for receive - // packet -#define EMAC_DMARIS_RS_SUSPEND 0x00080000 // Suspended: Receive descriptor - // unavailable -#define EMAC_DMARIS_RS_RUNCRD 0x000A0000 // Running: Closing receive - // descriptor -#define EMAC_DMARIS_RS_TSWS 0x000C0000 // Writing Timestamp -#define EMAC_DMARIS_RS_RUNTXD 0x000E0000 // Running: Transferring the - // receive packet data from receive - // buffer to host memory -#define EMAC_DMARIS_NIS 0x00010000 // Normal Interrupt Summary -#define EMAC_DMARIS_AIS 0x00008000 // Abnormal Interrupt Summary -#define EMAC_DMARIS_ERI 0x00004000 // Early Receive Interrupt -#define EMAC_DMARIS_FBI 0x00002000 // Fatal Bus Error Interrupt -#define EMAC_DMARIS_ETI 0x00000400 // Early Transmit Interrupt -#define EMAC_DMARIS_RWT 0x00000200 // Receive Watchdog Timeout -#define EMAC_DMARIS_RPS 0x00000100 // Receive Process Stopped -#define EMAC_DMARIS_RU 0x00000080 // Receive Buffer Unavailable -#define EMAC_DMARIS_RI 0x00000040 // Receive Interrupt -#define EMAC_DMARIS_UNF 0x00000020 // Transmit Underflow -#define EMAC_DMARIS_OVF 0x00000010 // Receive Overflow -#define EMAC_DMARIS_TJT 0x00000008 // Transmit Jabber Timeout -#define EMAC_DMARIS_TU 0x00000004 // Transmit Buffer Unavailable -#define EMAC_DMARIS_TPS 0x00000002 // Transmit Process Stopped -#define EMAC_DMARIS_TI 0x00000001 // Transmit Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_DMAOPMODE -// register. -// -//***************************************************************************** -#define EMAC_DMAOPMODE_DT 0x04000000 // Disable Dropping of TCP/IP - // Checksum Error Frames -#define EMAC_DMAOPMODE_RSF 0x02000000 // Receive Store and Forward -#define EMAC_DMAOPMODE_DFF 0x01000000 // Disable Flushing of Received - // Frames -#define EMAC_DMAOPMODE_TSF 0x00200000 // Transmit Store and Forward -#define EMAC_DMAOPMODE_FTF 0x00100000 // Flush Transmit FIFO -#define EMAC_DMAOPMODE_TTC_M 0x0001C000 // Transmit Threshold Control -#define EMAC_DMAOPMODE_TTC_64 0x00000000 // 64 bytes -#define EMAC_DMAOPMODE_TTC_128 0x00004000 // 128 bytes -#define EMAC_DMAOPMODE_TTC_192 0x00008000 // 192 bytes -#define EMAC_DMAOPMODE_TTC_256 0x0000C000 // 256 bytes -#define EMAC_DMAOPMODE_TTC_40 0x00010000 // 40 bytes -#define EMAC_DMAOPMODE_TTC_32 0x00014000 // 32 bytes -#define EMAC_DMAOPMODE_TTC_24 0x00018000 // 24 bytes -#define EMAC_DMAOPMODE_TTC_16 0x0001C000 // 16 bytes -#define EMAC_DMAOPMODE_ST 0x00002000 // Start or Stop Transmission - // Command -#define EMAC_DMAOPMODE_FEF 0x00000080 // Forward Error Frames -#define EMAC_DMAOPMODE_FUF 0x00000040 // Forward Undersized Good Frames -#define EMAC_DMAOPMODE_DGF 0x00000020 // Drop Giant Frame Enable -#define EMAC_DMAOPMODE_RTC_M 0x00000018 // Receive Threshold Control -#define EMAC_DMAOPMODE_RTC_64 0x00000000 // 64 bytes -#define EMAC_DMAOPMODE_RTC_32 0x00000008 // 32 bytes -#define EMAC_DMAOPMODE_RTC_96 0x00000010 // 96 bytes -#define EMAC_DMAOPMODE_RTC_128 0x00000018 // 128 bytes -#define EMAC_DMAOPMODE_OSF 0x00000004 // Operate on Second Frame -#define EMAC_DMAOPMODE_SR 0x00000002 // Start or Stop Receive - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_DMAIM register. -// -//***************************************************************************** -#define EMAC_DMAIM_NIE 0x00010000 // Normal Interrupt Summary Enable -#define EMAC_DMAIM_AIE 0x00008000 // Abnormal Interrupt Summary - // Enable -#define EMAC_DMAIM_ERE 0x00004000 // Early Receive Interrupt Enable -#define EMAC_DMAIM_FBE 0x00002000 // Fatal Bus Error Enable -#define EMAC_DMAIM_ETE 0x00000400 // Early Transmit Interrupt Enable -#define EMAC_DMAIM_RWE 0x00000200 // Receive Watchdog Timeout Enable -#define EMAC_DMAIM_RSE 0x00000100 // Receive Stopped Enable -#define EMAC_DMAIM_RUE 0x00000080 // Receive Buffer Unavailable - // Enable -#define EMAC_DMAIM_RIE 0x00000040 // Receive Interrupt Enable -#define EMAC_DMAIM_UNE 0x00000020 // Underflow Interrupt Enable -#define EMAC_DMAIM_OVE 0x00000010 // Overflow Interrupt Enable -#define EMAC_DMAIM_TJE 0x00000008 // Transmit Jabber Timeout Enable -#define EMAC_DMAIM_TUE 0x00000004 // Transmit Buffer Unvailable - // Enable -#define EMAC_DMAIM_TSE 0x00000002 // Transmit Stopped Enable -#define EMAC_DMAIM_TIE 0x00000001 // Transmit Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MFBOC register. -// -//***************************************************************************** -#define EMAC_MFBOC_OVFCNTOVF 0x10000000 // Overflow Bit for FIFO Overflow - // Counter -#define EMAC_MFBOC_OVFFRMCNT_M 0x0FFE0000 // Overflow Frame Counter -#define EMAC_MFBOC_MISCNTOVF 0x00010000 // Overflow bit for Missed Frame - // Counter -#define EMAC_MFBOC_MISFRMCNT_M 0x0000FFFF // Missed Frame Counter -#define EMAC_MFBOC_OVFFRMCNT_S 17 -#define EMAC_MFBOC_MISFRMCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXINTWDT -// register. -// -//***************************************************************************** -#define EMAC_RXINTWDT_RIWT_M 0x000000FF // Receive Interrupt Watchdog Timer - // Count -#define EMAC_RXINTWDT_RIWT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HOSTXDESC -// register. -// -//***************************************************************************** -#define EMAC_HOSTXDESC_CURTXDESC_M \ - 0xFFFFFFFF // Host Transmit Descriptor Address - // Pointer -#define EMAC_HOSTXDESC_CURTXDESC_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HOSRXDESC -// register. -// -//***************************************************************************** -#define EMAC_HOSRXDESC_CURRXDESC_M \ - 0xFFFFFFFF // Host Receive Descriptor Address - // Pointer -#define EMAC_HOSRXDESC_CURRXDESC_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HOSTXBA register. -// -//***************************************************************************** -#define EMAC_HOSTXBA_CURTXBUFA_M \ - 0xFFFFFFFF // Host Transmit Buffer Address - // Pointer -#define EMAC_HOSTXBA_CURTXBUFA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HOSRXBA register. -// -//***************************************************************************** -#define EMAC_HOSRXBA_CURRXBUFA_M \ - 0xFFFFFFFF // Host Receive Buffer Address - // Pointer -#define EMAC_HOSRXBA_CURRXBUFA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PP register. -// -//***************************************************************************** -#define EMAC_PP_MACTYPE_M 0x00000700 // Ethernet MAC Type -#define EMAC_PP_MACTYPE_1 0x00000100 // Tiva TM4E129x-class MAC -#define EMAC_PP_PHYTYPE_M 0x00000007 // Ethernet PHY Type -#define EMAC_PP_PHYTYPE_NONE 0x00000000 // No PHY -#define EMAC_PP_PHYTYPE_1 0x00000003 // Snowflake class PHY - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PC register. -// -//***************************************************************************** -#define EMAC_PC_PHYEXT 0x80000000 // PHY Select -#define EMAC_PC_PINTFS_M 0x70000000 // Ethernet Interface Select -#define EMAC_PC_PINTFS_IMII 0x00000000 // MII (default) Used for internal - // PHY or external PHY connected - // via MII -#define EMAC_PC_PINTFS_RMII 0x40000000 // RMII: Used for external PHY - // connected via RMII -#define EMAC_PC_DIGRESTART 0x02000000 // PHY Soft Restart -#define EMAC_PC_NIBDETDIS 0x01000000 // Odd Nibble TXER Detection - // Disable -#define EMAC_PC_RXERIDLE 0x00800000 // RXER Detection During Idle -#define EMAC_PC_ISOMIILL 0x00400000 // Isolate MII in Link Loss -#define EMAC_PC_LRR 0x00200000 // Link Loss Recovery -#define EMAC_PC_TDRRUN 0x00100000 // TDR Auto Run -#define EMAC_PC_FASTLDMODE_M 0x000F8000 // Fast Link Down Mode -#define EMAC_PC_POLSWAP 0x00004000 // Polarity Swap -#define EMAC_PC_MDISWAP 0x00002000 // MDI Swap -#define EMAC_PC_RBSTMDIX 0x00001000 // Robust Auto MDI-X -#define EMAC_PC_FASTMDIX 0x00000800 // Fast Auto MDI-X -#define EMAC_PC_MDIXEN 0x00000400 // MDIX Enable -#define EMAC_PC_FASTRXDV 0x00000200 // Fast RXDV Detection -#define EMAC_PC_FASTLUPD 0x00000100 // FAST Link-Up in Parallel Detect -#define EMAC_PC_EXTFD 0x00000080 // Extended Full Duplex Ability -#define EMAC_PC_FASTANEN 0x00000040 // Fast Auto Negotiation Enable -#define EMAC_PC_FASTANSEL_M 0x00000030 // Fast Auto Negotiation Select -#define EMAC_PC_ANEN 0x00000008 // Auto Negotiation Enable -#define EMAC_PC_ANMODE_M 0x00000006 // Auto Negotiation Mode -#define EMAC_PC_ANMODE_10HD 0x00000000 // When ANEN = 0x0, the mode is - // 10Base-T, Half-Duplex -#define EMAC_PC_ANMODE_10FD 0x00000002 // When ANEN = 0x0, the mode is - // 10Base-T, Full-Duplex -#define EMAC_PC_ANMODE_100HD 0x00000004 // When ANEN = 0x0, the mode is - // 100Base-TX, Half-Duplex -#define EMAC_PC_ANMODE_100FD 0x00000006 // When ANEN = 0x0, the mode is - // 100Base-TX, Full-Duplex -#define EMAC_PC_PHYHOLD 0x00000001 // Ethernet PHY Hold -#define EMAC_PC_FASTLDMODE_S 15 -#define EMAC_PC_FASTANSEL_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_CC register. -// -//***************************************************************************** -#define EMAC_CC_PTPCEN 0x00040000 // PTP Clock Reference Enable -#define EMAC_CC_POL 0x00020000 // LED Polarity Control -#define EMAC_CC_CLKEN 0x00010000 // EN0RREF_CLK Signal Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_EPHYRIS register. -// -//***************************************************************************** -#define EMAC_EPHYRIS_INT 0x00000001 // Ethernet PHY Raw Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_EPHYIM register. -// -//***************************************************************************** -#define EMAC_EPHYIM_INT 0x00000001 // Ethernet PHY Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_EPHYMISC -// register. -// -//***************************************************************************** -#define EMAC_EPHYMISC_INT 0x00000001 // Ethernet PHY Status and Clear - // register - -//***************************************************************************** -// -// The following are defines for the EPHY register offsets. -// -//***************************************************************************** -#define EPHY_BMCR 0x00000000 // Ethernet PHY Basic Mode Control -#define EPHY_BMSR 0x00000001 // Ethernet PHY Basic Mode Status -#define EPHY_ID1 0x00000002 // Ethernet PHY Identifier Register - // 1 -#define EPHY_ID2 0x00000003 // Ethernet PHY Identifier Register - // 2 -#define EPHY_ANA 0x00000004 // Ethernet PHY Auto-Negotiation - // Advertisement -#define EPHY_ANLPA 0x00000005 // Ethernet PHY Auto-Negotiation - // Link Partner Ability -#define EPHY_ANER 0x00000006 // Ethernet PHY Auto-Negotiation - // Expansion -#define EPHY_ANNPTR 0x00000007 // Ethernet PHY Auto-Negotiation - // Next Page TX -#define EPHY_ANLNPTR 0x00000008 // Ethernet PHY Auto-Negotiation - // Link Partner Ability Next Page -#define EPHY_CFG1 0x00000009 // Ethernet PHY Configuration 1 -#define EPHY_CFG2 0x0000000A // Ethernet PHY Configuration 2 -#define EPHY_CFG3 0x0000000B // Ethernet PHY Configuration 3 -#define EPHY_REGCTL 0x0000000D // Ethernet PHY Register Control -#define EPHY_ADDAR 0x0000000E // Ethernet PHY Address or Data -#define EPHY_STS 0x00000010 // Ethernet PHY Status -#define EPHY_SCR 0x00000011 // Ethernet PHY Specific Control -#define EPHY_MISR1 0x00000012 // Ethernet PHY MII Interrupt - // Status 1 -#define EPHY_MISR2 0x00000013 // Ethernet PHY MII Interrupt - // Status 2 -#define EPHY_FCSCR 0x00000014 // Ethernet PHY False Carrier Sense - // Counter -#define EPHY_RXERCNT 0x00000015 // Ethernet PHY Receive Error Count -#define EPHY_BISTCR 0x00000016 // Ethernet PHY BIST Control -#define EPHY_LEDCR 0x00000018 // Ethernet PHY LED Control -#define EPHY_CTL 0x00000019 // Ethernet PHY Control -#define EPHY_10BTSC 0x0000001A // Ethernet PHY 10Base-T - // Status/Control - MR26 -#define EPHY_BICSR1 0x0000001B // Ethernet PHY BIST Control and - // Status 1 -#define EPHY_BICSR2 0x0000001C // Ethernet PHY BIST Control and - // Status 2 -#define EPHY_CDCR 0x0000001E // Ethernet PHY Cable Diagnostic - // Control -#define EPHY_RCR 0x0000001F // Ethernet PHY Reset Control -#define EPHY_LEDCFG 0x00000025 // Ethernet PHY LED Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_BMCR register. -// -//***************************************************************************** -#define EPHY_BMCR_MIIRESET 0x00008000 // MII Register reset -#define EPHY_BMCR_MIILOOPBK 0x00004000 // MII Loopback -#define EPHY_BMCR_SPEED 0x00002000 // Speed Select -#define EPHY_BMCR_ANEN 0x00001000 // Auto-Negotiate Enable -#define EPHY_BMCR_PWRDWN 0x00000800 // Power Down -#define EPHY_BMCR_ISOLATE 0x00000400 // Port Isolate -#define EPHY_BMCR_RESTARTAN 0x00000200 // Restart Auto-Negotiation -#define EPHY_BMCR_DUPLEXM 0x00000100 // Duplex Mode -#define EPHY_BMCR_COLLTST 0x00000080 // Collision Test - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_BMSR register. -// -//***************************************************************************** -#define EPHY_BMSR_100BTXFD 0x00004000 // 100Base-TX Full Duplex Capable -#define EPHY_BMSR_100BTXHD 0x00002000 // 100Base-TX Half Duplex Capable -#define EPHY_BMSR_10BTFD 0x00001000 // 10 Base-T Full Duplex Capable -#define EPHY_BMSR_10BTHD 0x00000800 // 10 Base-T Half Duplex Capable -#define EPHY_BMSR_MFPRESUP 0x00000040 // Preamble Suppression Capable -#define EPHY_BMSR_ANC 0x00000020 // Auto-Negotiation Complete -#define EPHY_BMSR_RFAULT 0x00000010 // Remote Fault -#define EPHY_BMSR_ANEN 0x00000008 // Auto Negotiation Enabled -#define EPHY_BMSR_LINKSTAT 0x00000004 // Link Status -#define EPHY_BMSR_JABBER 0x00000002 // Jabber Detect -#define EPHY_BMSR_EXTEN 0x00000001 // Extended Capability Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ID1 register. -// -//***************************************************************************** -#define EPHY_ID1_OUIMSB_M 0x0000FFFF // OUI Most Significant Bits -#define EPHY_ID1_OUIMSB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ID2 register. -// -//***************************************************************************** -#define EPHY_ID2_OUILSB_M 0x0000FC00 // OUI Least Significant Bits -#define EPHY_ID2_VNDRMDL_M 0x000003F0 // Vendor Model Number -#define EPHY_ID2_MDLREV_M 0x0000000F // Model Revision Number -#define EPHY_ID2_OUILSB_S 10 -#define EPHY_ID2_VNDRMDL_S 4 -#define EPHY_ID2_MDLREV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ANA register. -// -//***************************************************************************** -#define EPHY_ANA_NP 0x00008000 // Next Page Indication -#define EPHY_ANA_RF 0x00002000 // Remote Fault -#define EPHY_ANA_ASMDUP 0x00000800 // Asymmetric PAUSE support for - // Full Duplex Links -#define EPHY_ANA_PAUSE 0x00000400 // PAUSE Support for Full Duplex - // Links -#define EPHY_ANA_100BT4 0x00000200 // 100Base-T4 Support -#define EPHY_ANA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support -#define EPHY_ANA_100BTX 0x00000080 // 100Base-TX Support -#define EPHY_ANA_10BTFD 0x00000040 // 10Base-T Full Duplex Support -#define EPHY_ANA_10BT 0x00000020 // 10Base-T Support -#define EPHY_ANA_SELECT_M 0x0000001F // Protocol Selection -#define EPHY_ANA_SELECT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ANLPA register. -// -//***************************************************************************** -#define EPHY_ANLPA_NP 0x00008000 // Next Page Indication -#define EPHY_ANLPA_ACK 0x00004000 // Acknowledge -#define EPHY_ANLPA_RF 0x00002000 // Remote Fault -#define EPHY_ANLPA_ASMDUP 0x00000800 // Asymmetric PAUSE -#define EPHY_ANLPA_PAUSE 0x00000400 // PAUSE -#define EPHY_ANLPA_100BT4 0x00000200 // 100Base-T4 Support -#define EPHY_ANLPA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support -#define EPHY_ANLPA_100BTX 0x00000080 // 100Base-TX Support -#define EPHY_ANLPA_10BTFD 0x00000040 // 10Base-T Full Duplex Support -#define EPHY_ANLPA_10BT 0x00000020 // 10Base-T Support -#define EPHY_ANLPA_SELECT_M 0x0000001F // Protocol Selection -#define EPHY_ANLPA_SELECT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ANER register. -// -//***************************************************************************** -#define EPHY_ANER_PDF 0x00000010 // Parallel Detection Fault -#define EPHY_ANER_LPNPABLE 0x00000008 // Link Partner Next Page Able -#define EPHY_ANER_NPABLE 0x00000004 // Next Page Able -#define EPHY_ANER_PAGERX 0x00000002 // Link Code Word Page Received -#define EPHY_ANER_LPANABLE 0x00000001 // Link Partner Auto-Negotiation - // Able - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ANNPTR register. -// -//***************************************************************************** -#define EPHY_ANNPTR_NP 0x00008000 // Next Page Indication -#define EPHY_ANNPTR_MP 0x00002000 // Message Page -#define EPHY_ANNPTR_ACK2 0x00001000 // Acknowledge 2 -#define EPHY_ANNPTR_TOGTX 0x00000800 // Toggle -#define EPHY_ANNPTR_CODE_M 0x000007FF // Code -#define EPHY_ANNPTR_CODE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ANLNPTR register. -// -//***************************************************************************** -#define EPHY_ANLNPTR_NP 0x00008000 // Next Page Indication -#define EPHY_ANLNPTR_ACK 0x00004000 // Acknowledge -#define EPHY_ANLNPTR_MP 0x00002000 // Message Page -#define EPHY_ANLNPTR_ACK2 0x00001000 // Acknowledge 2 -#define EPHY_ANLNPTR_TOG 0x00000800 // Toggle -#define EPHY_ANLNPTR_CODE_M 0x000007FF // Code -#define EPHY_ANLNPTR_CODE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_CFG1 register. -// -//***************************************************************************** -#define EPHY_CFG1_DONE 0x00008000 // Configuration Done -#define EPHY_CFG1_TDRAR 0x00000100 // TDR Auto-Run at Link Down -#define EPHY_CFG1_LLR 0x00000080 // Link Loss Recovery -#define EPHY_CFG1_FAMDIX 0x00000040 // Fast Auto MDI/MDIX -#define EPHY_CFG1_RAMDIX 0x00000020 // Robust Auto MDI/MDIX -#define EPHY_CFG1_FASTANEN 0x00000010 // Fast Auto Negotiation Enable -#define EPHY_CFG1_FANSEL_M 0x0000000C // Fast Auto-Negotiation Select - // Configuration -#define EPHY_CFG1_FANSEL_BLT80 0x00000000 // Break Link Timer: 80 ms -#define EPHY_CFG1_FANSEL_BLT120 0x00000004 // Break Link Timer: 120 ms -#define EPHY_CFG1_FANSEL_BLT240 0x00000008 // Break Link Timer: 240 ms -#define EPHY_CFG1_FRXDVDET 0x00000002 // FAST RXDV Detection - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_CFG2 register. -// -//***************************************************************************** -#define EPHY_CFG2_FLUPPD 0x00000040 // Fast Link-Up in Parallel Detect - // Mode -#define EPHY_CFG2_EXTFD 0x00000020 // Extended Full-Duplex Ability -#define EPHY_CFG2_ENLEDLINK 0x00000010 // Enhanced LED Functionality -#define EPHY_CFG2_ISOMIILL 0x00000008 // Isolate MII outputs when - // Enhanced Link is not Achievable -#define EPHY_CFG2_RXERRIDLE 0x00000004 // Detection of Receive Symbol - // Error During IDLE State -#define EPHY_CFG2_ODDNDETDIS 0x00000002 // Detection of Transmit Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_CFG3 register. -// -//***************************************************************************** -#define EPHY_CFG3_POLSWAP 0x00000080 // Polarity Swap -#define EPHY_CFG3_MDIMDIXS 0x00000040 // MDI/MDIX Swap -#define EPHY_CFG3_FLDWNM_M 0x0000001F // Fast Link Down Modes -#define EPHY_CFG3_FLDWNM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_REGCTL register. -// -//***************************************************************************** -#define EPHY_REGCTL_FUNC_M 0x0000C000 // Function -#define EPHY_REGCTL_FUNC_ADDR 0x00000000 // Address -#define EPHY_REGCTL_FUNC_DATANI 0x00004000 // Data, no post increment -#define EPHY_REGCTL_FUNC_DATAPIRW \ - 0x00008000 // Data, post increment on read and - // write -#define EPHY_REGCTL_FUNC_DATAPIWO \ - 0x0000C000 // Data, post increment on write - // only -#define EPHY_REGCTL_DEVAD_M 0x0000001F // Device Address -#define EPHY_REGCTL_DEVAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ADDAR register. -// -//***************************************************************************** -#define EPHY_ADDAR_ADDRDATA_M 0x0000FFFF // Address or Data -#define EPHY_ADDAR_ADDRDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_STS register. -// -//***************************************************************************** -#define EPHY_STS_MDIXM 0x00004000 // MDI-X Mode -#define EPHY_STS_RXLERR 0x00002000 // Receive Error Latch -#define EPHY_STS_POLSTAT 0x00001000 // Polarity Status -#define EPHY_STS_FCSL 0x00000800 // False Carrier Sense Latch -#define EPHY_STS_SD 0x00000400 // Signal Detect -#define EPHY_STS_DL 0x00000200 // Descrambler Lock -#define EPHY_STS_PAGERX 0x00000100 // Link Code Page Received -#define EPHY_STS_MIIREQ 0x00000080 // MII Interrupt Pending -#define EPHY_STS_RF 0x00000040 // Remote Fault -#define EPHY_STS_JD 0x00000020 // Jabber Detect -#define EPHY_STS_ANS 0x00000010 // Auto-Negotiation Status -#define EPHY_STS_MIILB 0x00000008 // MII Loopback Status -#define EPHY_STS_DUPLEX 0x00000004 // Duplex Status -#define EPHY_STS_SPEED 0x00000002 // Speed Status -#define EPHY_STS_LINK 0x00000001 // Link Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_SCR register. -// -//***************************************************************************** -#define EPHY_SCR_DISCLK 0x00008000 // Disable CLK -#define EPHY_SCR_PSEN 0x00004000 // Power Saving Modes Enable -#define EPHY_SCR_PSMODE_M 0x00003000 // Power Saving Modes -#define EPHY_SCR_PSMODE_NORMAL 0x00000000 // Normal: Normal operation mode. - // PHY is fully functional -#define EPHY_SCR_PSMODE_LOWPWR 0x00001000 // IEEE Power Down -#define EPHY_SCR_PSMODE_ACTWOL 0x00002000 // Active Sleep -#define EPHY_SCR_PSMODE_PASWOL 0x00003000 // Passive Sleep -#define EPHY_SCR_SBPYASS 0x00000800 // Scrambler Bypass -#define EPHY_SCR_LBFIFO_M 0x00000300 // Loopback FIFO Depth -#define EPHY_SCR_LBFIFO_4 0x00000000 // Four nibble FIFO -#define EPHY_SCR_LBFIFO_5 0x00000100 // Five nibble FIFO -#define EPHY_SCR_LBFIFO_6 0x00000200 // Six nibble FIFO -#define EPHY_SCR_LBFIFO_8 0x00000300 // Eight nibble FIFO -#define EPHY_SCR_COLFDM 0x00000010 // Collision in Full-Duplex Mode -#define EPHY_SCR_TINT 0x00000004 // Test Interrupt -#define EPHY_SCR_INTEN 0x00000002 // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_MISR1 register. -// -//***************************************************************************** -#define EPHY_MISR1_LINKSTAT 0x00002000 // Change of Link Status Interrupt -#define EPHY_MISR1_SPEED 0x00001000 // Change of Speed Status Interrupt -#define EPHY_MISR1_DUPLEXM 0x00000800 // Change of Duplex Status - // Interrupt -#define EPHY_MISR1_ANC 0x00000400 // Auto-Negotiation Complete - // Interrupt -#define EPHY_MISR1_FCHF 0x00000200 // False Carrier Counter Half-Full - // Interrupt -#define EPHY_MISR1_RXHF 0x00000100 // Receive Error Counter Half-Full - // Interrupt -#define EPHY_MISR1_LINKSTATEN 0x00000020 // Link Status Interrupt Enable -#define EPHY_MISR1_SPEEDEN 0x00000010 // Speed Change Interrupt Enable -#define EPHY_MISR1_DUPLEXMEN 0x00000008 // Duplex Status Interrupt Enable -#define EPHY_MISR1_ANCEN 0x00000004 // Auto-Negotiation Complete - // Interrupt Enable -#define EPHY_MISR1_FCHFEN 0x00000002 // False Carrier Counter Register - // half-full Interrupt Enable -#define EPHY_MISR1_RXHFEN 0x00000001 // Receive Error Counter Register - // Half-Full Event Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_MISR2 register. -// -//***************************************************************************** -#define EPHY_MISR2_ANERR 0x00004000 // Auto-Negotiation Error Interrupt -#define EPHY_MISR2_PAGERX 0x00002000 // Page Receive Interrupt -#define EPHY_MISR2_LBFIFO 0x00001000 // Loopback FIFO Overflow/Underflow - // Event Interrupt -#define EPHY_MISR2_MDICO 0x00000800 // MDI/MDIX Crossover Status - // Changed Interrupt -#define EPHY_MISR2_SLEEP 0x00000400 // Sleep Mode Event Interrupt -#define EPHY_MISR2_POLINT 0x00000200 // Polarity Changed Interrupt -#define EPHY_MISR2_JABBER 0x00000100 // Jabber Detect Event Interrupt -#define EPHY_MISR2_ANERREN 0x00000040 // Auto-Negotiation Error Interrupt - // Enable -#define EPHY_MISR2_PAGERXEN 0x00000020 // Page Receive Interrupt Enable -#define EPHY_MISR2_LBFIFOEN 0x00000010 // Loopback FIFO Overflow/Underflow - // Interrupt Enable -#define EPHY_MISR2_MDICOEN 0x00000008 // MDI/MDIX Crossover Status - // Changed Interrupt Enable -#define EPHY_MISR2_SLEEPEN 0x00000004 // Sleep Mode Event Interrupt - // Enable -#define EPHY_MISR2_POLINTEN 0x00000002 // Polarity Changed Interrupt - // Enable -#define EPHY_MISR2_JABBEREN 0x00000001 // Jabber Detect Event Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_FCSCR register. -// -//***************************************************************************** -#define EPHY_FCSCR_FCSCNT_M 0x000000FF // False Carrier Event Counter -#define EPHY_FCSCR_FCSCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_RXERCNT register. -// -//***************************************************************************** -#define EPHY_RXERCNT_RXERRCNT_M 0x0000FFFF // Receive Error Count -#define EPHY_RXERCNT_RXERRCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_BISTCR register. -// -//***************************************************************************** -#define EPHY_BISTCR_PRBSM 0x00004000 // PRBS Single/Continuous Mode -#define EPHY_BISTCR_PRBSPKT 0x00002000 // Generated PRBS Packets -#define EPHY_BISTCR_PKTEN 0x00001000 // Packet Generation Enable -#define EPHY_BISTCR_PRBSCHKLK 0x00000800 // PRBS Checker Lock Indication -#define EPHY_BISTCR_PRBSCHKSYNC 0x00000400 // PRBS Checker Lock Sync Loss - // Indication -#define EPHY_BISTCR_PKTGENSTAT 0x00000200 // Packet Generator Status - // Indication -#define EPHY_BISTCR_PWRMODE 0x00000100 // Power Mode Indication -#define EPHY_BISTCR_TXMIILB 0x00000040 // Transmit Data in MII Loopback - // Mode -#define EPHY_BISTCR_LBMODE_M 0x0000001F // Loopback Mode Select -#define EPHY_BISTCR_LBMODE_NPCSIN \ - 0x00000001 // Near-end loopback: PCS Input - // Loopback -#define EPHY_BISTCR_LBMODE_NPCSOUT \ - 0x00000002 // Near-end loopback: PCS Output - // Loopback (In 100Base-TX only) -#define EPHY_BISTCR_LBMODE_NDIG 0x00000004 // Near-end loopback: Digital - // Loopback -#define EPHY_BISTCR_LBMODE_NANA 0x00000008 // Near-end loopback: Analog - // Loopback (requires 100 Ohm - // termination) -#define EPHY_BISTCR_LBMODE_FREV 0x00000010 // Far-end Loopback: Reverse - // Loopback - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_LEDCR register. -// -//***************************************************************************** -#define EPHY_LEDCR_BLINKRATE_M 0x00000600 // LED Blinking Rate (ON/OFF - // duration): -#define EPHY_LEDCR_BLINKRATE_20HZ \ - 0x00000000 // 20 Hz (50 ms) -#define EPHY_LEDCR_BLINKRATE_10HZ \ - 0x00000200 // 10 Hz (100 ms) -#define EPHY_LEDCR_BLINKRATE_5HZ \ - 0x00000400 // 5 Hz (200 ms) -#define EPHY_LEDCR_BLINKRATE_2HZ \ - 0x00000600 // 2 Hz (500 ms) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_CTL register. -// -//***************************************************************************** -#define EPHY_CTL_AUTOMDI 0x00008000 // Auto-MDIX Enable -#define EPHY_CTL_FORCEMDI 0x00004000 // Force MDIX -#define EPHY_CTL_PAUSERX 0x00002000 // Pause Receive Negotiated Status -#define EPHY_CTL_PAUSETX 0x00001000 // Pause Transmit Negotiated Status -#define EPHY_CTL_MIILNKSTAT 0x00000800 // MII Link Status -#define EPHY_CTL_BYPLEDSTRCH 0x00000080 // Bypass LED Stretching - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_10BTSC register. -// -//***************************************************************************** -#define EPHY_10BTSC_RXTHEN 0x00002000 // Lower Receiver Threshold Enable -#define EPHY_10BTSC_SQUELCH_M 0x00001E00 // Squelch Configuration -#define EPHY_10BTSC_NLPDIS 0x00000080 // Normal Link Pulse (NLP) - // Transmission Control -#define EPHY_10BTSC_POLSTAT 0x00000010 // 10 Mb Polarity Status -#define EPHY_10BTSC_JABBERD 0x00000001 // Jabber Disable -#define EPHY_10BTSC_SQUELCH_S 9 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_BICSR1 register. -// -//***************************************************************************** -#define EPHY_BICSR1_ERRCNT_M 0x0000FF00 // BIST Error Count -#define EPHY_BICSR1_IPGLENGTH_M 0x000000FF // BIST IPG Length -#define EPHY_BICSR1_ERRCNT_S 8 -#define EPHY_BICSR1_IPGLENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_BICSR2 register. -// -//***************************************************************************** -#define EPHY_BICSR2_PKTLENGTH_M 0x000007FF // BIST Packet Length -#define EPHY_BICSR2_PKTLENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_CDCR register. -// -//***************************************************************************** -#define EPHY_CDCR_START 0x00008000 // Cable Diagnostic Process Start -#define EPHY_CDCR_LINKQUAL_M 0x00000300 // Link Quality Indication -#define EPHY_CDCR_LINKQUAL_GOOD 0x00000100 // Good Quality Link Indication -#define EPHY_CDCR_LINKQUAL_MILD 0x00000200 // Mid- Quality Link Indication -#define EPHY_CDCR_LINKQUAL_POOR 0x00000300 // Poor Quality Link Indication -#define EPHY_CDCR_DONE 0x00000002 // Cable Diagnostic Process Done -#define EPHY_CDCR_FAIL 0x00000001 // Cable Diagnostic Process Fail - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_RCR register. -// -//***************************************************************************** -#define EPHY_RCR_SWRST 0x00008000 // Software Reset -#define EPHY_RCR_SWRESTART 0x00004000 // Software Restart - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_LEDCFG register. -// -//***************************************************************************** -#define EPHY_LEDCFG_LED2_M 0x00000F00 // LED2 Configuration -#define EPHY_LEDCFG_LED2_LINK 0x00000000 // Link OK -#define EPHY_LEDCFG_LED2_RXTX 0x00000100 // RX/TX Activity -#define EPHY_LEDCFG_LED2_TX 0x00000200 // TX Activity -#define EPHY_LEDCFG_LED2_RX 0x00000300 // RX Activity -#define EPHY_LEDCFG_LED2_COL 0x00000400 // Collision -#define EPHY_LEDCFG_LED2_100BT 0x00000500 // 100-Base TX -#define EPHY_LEDCFG_LED2_10BT 0x00000600 // 10-Base TX -#define EPHY_LEDCFG_LED2_FD 0x00000700 // Full Duplex -#define EPHY_LEDCFG_LED2_LINKTXRX \ - 0x00000800 // Link OK/Blink on TX/RX Activity -#define EPHY_LEDCFG_LED1_M 0x000000F0 // LED1 Configuration -#define EPHY_LEDCFG_LED1_LINK 0x00000000 // Link OK -#define EPHY_LEDCFG_LED1_RXTX 0x00000010 // RX/TX Activity -#define EPHY_LEDCFG_LED1_TX 0x00000020 // TX Activity -#define EPHY_LEDCFG_LED1_RX 0x00000030 // RX Activity -#define EPHY_LEDCFG_LED1_COL 0x00000040 // Collision -#define EPHY_LEDCFG_LED1_100BT 0x00000050 // 100-Base TX -#define EPHY_LEDCFG_LED1_10BT 0x00000060 // 10-Base TX -#define EPHY_LEDCFG_LED1_FD 0x00000070 // Full Duplex -#define EPHY_LEDCFG_LED1_LINKTXRX \ - 0x00000080 // Link OK/Blink on TX/RX Activity -#define EPHY_LEDCFG_LED0_M 0x0000000F // LED0 Configuration -#define EPHY_LEDCFG_LED0_LINK 0x00000000 // Link OK -#define EPHY_LEDCFG_LED0_RXTX 0x00000001 // RX/TX Activity -#define EPHY_LEDCFG_LED0_TX 0x00000002 // TX Activity -#define EPHY_LEDCFG_LED0_RX 0x00000003 // RX Activity -#define EPHY_LEDCFG_LED0_COL 0x00000004 // Collision -#define EPHY_LEDCFG_LED0_100BT 0x00000005 // 100-Base TX -#define EPHY_LEDCFG_LED0_10BT 0x00000006 // 10-Base TX -#define EPHY_LEDCFG_LED0_FD 0x00000007 // Full Duplex -#define EPHY_LEDCFG_LED0_LINKTXRX \ - 0x00000008 // Link OK/Blink on TX/RX Activity - -//***************************************************************************** -// -// The following definitions are deprecated. -// -//***************************************************************************** -#ifndef DEPRECATED - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the -// EMAC_O_PPSCTRL register. -// -//***************************************************************************** -#define EMAC_PPSCTRL_PPSCTRL_1HZ \ - 0x00000000 // When the PPSEN0 bit = 0x0, the - // EN0PPS signal is 1 pulse of the - // PTP reference clock.(of width - // clk_ptp_i) every second -#define EMAC_PPSCTRL_PPSCTRL_2HZ \ - 0x00000001 // When the PPSEN0 bit = 0x0, the - // binary rollover is 2 Hz, and the - // digital rollover is 1 Hz -#define EMAC_PPSCTRL_PPSCTRL_4HZ \ - 0x00000002 // When the PPSEN0 bit = 0x0, the - // binary rollover is 4 Hz, and the - // digital rollover is 2 Hz -#define EMAC_PPSCTRL_PPSCTRL_8HZ \ - 0x00000003 // When thePPSEN0 bit = 0x0, the - // binary rollover is 8 Hz, and the - // digital rollover is 4 Hz, -#define EMAC_PPSCTRL_PPSCTRL_16HZ \ - 0x00000004 // When thePPSEN0 bit = 0x0, the - // binary rollover is 16 Hz, and - // the digital rollover is 8 Hz -#define EMAC_PPSCTRL_PPSCTRL_32HZ \ - 0x00000005 // When thePPSEN0 bit = 0x0, the - // binary rollover is 32 Hz, and - // the digital rollover is 16 Hz -#define EMAC_PPSCTRL_PPSCTRL_64HZ \ - 0x00000006 // When thePPSEN0 bit = 0x0, the - // binary rollover is 64 Hz, and - // the digital rollover is 32 Hz -#define EMAC_PPSCTRL_PPSCTRL_128HZ \ - 0x00000007 // When thePPSEN0 bit = 0x0, the - // binary rollover is 128 Hz, and - // the digital rollover is 64 Hz -#define EMAC_PPSCTRL_PPSCTRL_256HZ \ - 0x00000008 // When thePPSEN0 bit = 0x0, the - // binary rollover is 256 Hz, and - // the digital rollover is 128 Hz -#define EMAC_PPSCTRL_PPSCTRL_512HZ \ - 0x00000009 // When thePPSEN0 bit = 0x0, the - // binary rollover is 512 Hz, and - // the digital rollover is 256 Hz -#define EMAC_PPSCTRL_PPSCTRL_1024HZ \ - 0x0000000A // When the PPSEN0 bit = 0x0, the - // binary rollover is 1.024 kHz, - // and the digital rollover is 512 - // Hz -#define EMAC_PPSCTRL_PPSCTRL_2048HZ \ - 0x0000000B // When thePPSEN0 bit = 0x0, the - // binary rollover is 2.048 kHz, - // and the digital rollover is - // 1.024 kHz -#define EMAC_PPSCTRL_PPSCTRL_4096HZ \ - 0x0000000C // When thePPSEN0 bit = 0x0, the - // binary rollover is 4.096 kHz, - // and the digital rollover is - // 2.048 kHz -#define EMAC_PPSCTRL_PPSCTRL_8192HZ \ - 0x0000000D // When thePPSEN0 bit = 0x0, the - // binary rollover is 8.192 kHz, - // and the digital rollover is - // 4.096 kHz -#define EMAC_PPSCTRL_PPSCTRL_16384HZ \ - 0x0000000E // When thePPSEN0 bit = 0x0, the - // binary rollover is 16.384 kHz, - // and the digital rollover is - // 8.092 kHz -#define EMAC_PPSCTRL_PPSCTRL_32768HZ \ - 0x0000000F // When thePPSEN0 bit = 0x0, the - // binary rollover is 32.768 KHz, - // and the digital rollover is - // 16.384 KHz - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the EMAC_O_CC -// register. -// -//***************************************************************************** -#define EMAC_CC_CS_PA7 0x00000001 // GPIO - -#endif - -#endif // __HW_EMAC_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_epi.h b/bsp/tm4c129x-dk/libraries/inc/hw_epi.h deleted file mode 100644 index ea9f0655629e6b73b3cb40157b46113e0429fc3b..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_epi.h +++ /dev/null @@ -1,933 +0,0 @@ -//***************************************************************************** -// -// hw_epi.h - Macros for use in accessing the EPI registers. -// -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_EPI_H__ -#define __HW_EPI_H__ - -//***************************************************************************** -// -// The following are defines for the External Peripheral Interface register -// offsets. -// -//***************************************************************************** -#define EPI_O_CFG 0x00000000 // EPI Configuration -#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate -#define EPI_O_BAUD2 0x00000008 // EPI Main Baud Rate -#define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration -#define EPI_O_GPCFG 0x00000010 // EPI General-Purpose - // Configuration -#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration -#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration -#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2 -#define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2 -#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map -#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0 -#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0 -#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0 -#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1 -#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1 -#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1 -#define EPI_O_STAT 0x00000060 // EPI Status -#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count -#define EPI_O_READFIFO0 0x00000070 // EPI Read FIFO -#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1 -#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2 -#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3 -#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4 -#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5 -#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6 -#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7 -#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects -#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count -#define EPI_O_DMATXCNT 0x00000208 // EPI DMA Transmit Count -#define EPI_O_IM 0x00000210 // EPI Interrupt Mask -#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status -#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status -#define EPI_O_EISC 0x0000021C // EPI Error and Interrupt Status - // and Clear -#define EPI_O_HB8CFG3 0x00000308 // EPI Host-Bus 8 Configuration 3 -#define EPI_O_HB16CFG3 0x00000308 // EPI Host-Bus 16 Configuration 3 -#define EPI_O_HB16CFG4 0x0000030C // EPI Host-Bus 16 Configuration 4 -#define EPI_O_HB8CFG4 0x0000030C // EPI Host-Bus 8 Configuration 4 -#define EPI_O_HB8TIME 0x00000310 // EPI Host-Bus 8 Timing Extension -#define EPI_O_HB16TIME 0x00000310 // EPI Host-Bus 16 Timing Extension -#define EPI_O_HB8TIME2 0x00000314 // EPI Host-Bus 8 Timing Extension -#define EPI_O_HB16TIME2 0x00000314 // EPI Host-Bus 16 Timing Extension -#define EPI_O_HB16TIME3 0x00000318 // EPI Host-Bus 16 Timing Extension -#define EPI_O_HB8TIME3 0x00000318 // EPI Host-Bus 8 Timing Extension -#define EPI_O_HB8TIME4 0x0000031C // EPI Host-Bus 8 Timing Extension -#define EPI_O_HB16TIME4 0x0000031C // EPI Host-Bus 16 Timing Extension -#define EPI_O_HBPSRAM 0x00000360 // EPI Host-Bus PSRAM - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_CFG register. -// -//***************************************************************************** -#define EPI_CFG_INTDIV 0x00000100 // Integer Clock Divider Enable -#define EPI_CFG_BLKEN 0x00000010 // Block Enable -#define EPI_CFG_MODE_M 0x0000000F // Mode Select -#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose -#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM -#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8) -#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_BAUD register. -// -//***************************************************************************** -#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1 -#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0 -#define EPI_BAUD_COUNT1_S 16 -#define EPI_BAUD_COUNT0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_BAUD2 register. -// -//***************************************************************************** -#define EPI_BAUD2_COUNT1_M 0xFFFF0000 // CS3n Baud Rate Counter 1 -#define EPI_BAUD2_COUNT0_M 0x0000FFFF // CS2n Baud Rate Counter 0 -#define EPI_BAUD2_COUNT1_S 16 -#define EPI_BAUD2_COUNT0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG register. -// -//***************************************************************************** -#define EPI_HB16CFG_CLKGATE 0x80000000 // Clock Gated -#define EPI_HB16CFG_CLKGATEI 0x40000000 // Clock Gated Idle -#define EPI_HB16CFG_CLKINV 0x20000000 // Invert Output Clock Enable -#define EPI_HB16CFG_RDYEN 0x10000000 // Input Ready Enable -#define EPI_HB16CFG_IRDYINV 0x08000000 // Input Ready Invert -#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable -#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable -#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity -#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity -#define EPI_HB16CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity -#define EPI_HB16CFG_WRCRE 0x00040000 // PSRAM Configuration Register - // Write -#define EPI_HB16CFG_RDCRE 0x00020000 // PSRAM Configuration Register - // Read -#define EPI_HB16CFG_BURST 0x00010000 // Burst Mode -#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait -#define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States -#define EPI_HB16CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States -#define EPI_HB16CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration -#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode -#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0] -#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0] -#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0] -#define EPI_HB16CFG_MAXWAIT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_GPCFG register. -// -//***************************************************************************** -#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin -#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated -#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame -#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count -#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes -#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size -#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address -#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide -#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size - // cannot be used with 24-bit data -#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size - // cannot be used with data sizes - // other than 8 -#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus -#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7) -#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15) -#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23) -#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31) -#define EPI_GPCFG_FRMCNT_S 22 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_SDRAMCFG register. -// -//***************************************************************************** -#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range -#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz -#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz -#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz -#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter -#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode -#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM -#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB) -#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB) -#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB) -#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB) -#define EPI_SDRAMCFG_RFSH_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG register. -// -//***************************************************************************** -#define EPI_HB8CFG_CLKGATE 0x80000000 // Clock Gated -#define EPI_HB8CFG_CLKGATEI 0x40000000 // Clock Gated when Idle -#define EPI_HB8CFG_CLKINV 0x20000000 // Invert Output Clock Enable -#define EPI_HB8CFG_RDYEN 0x10000000 // Input Ready Enable -#define EPI_HB8CFG_IRDYINV 0x08000000 // Input Ready Invert -#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable -#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable -#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity -#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity -#define EPI_HB8CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity -#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait -#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States -#define EPI_HB8CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States -#define EPI_HB8CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode -#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0] -#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0] -#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0] -#define EPI_HB8CFG_MAXWAIT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG2 register. -// -//***************************************************************************** -#define EPI_HB8CFG2_CSCFGEXT 0x08000000 // Chip Select Extended - // Configuration -#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and - // Multiple Sub-Mode Configuration - // enable -#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration -#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration -#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration -#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration -#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration -#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity -#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity -#define EPI_HB8CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity -#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States -#define EPI_HB8CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States -#define EPI_HB8CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode -#define EPI_HB8CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG2_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG2 register. -// -//***************************************************************************** -#define EPI_HB16CFG2_CSCFGEXT 0x08000000 // Chip Select Extended - // Configuration -#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and - // Multiple Sub-Mode Configuration - // enable -#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration -#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration -#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration -#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration -#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration -#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity -#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity -#define EPI_HB16CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity -#define EPI_HB16CFG2_WRCRE 0x00040000 // CS1n PSRAM Configuration - // Register Write -#define EPI_HB16CFG2_RDCRE 0x00020000 // CS1n PSRAM Configuration - // Register Read -#define EPI_HB16CFG2_BURST 0x00010000 // CS1n Burst Mode -#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States -#define EPI_HB16CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States -#define EPI_HB16CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode -#define EPI_HB16CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG2_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_ADDRMAP register. -// -//***************************************************************************** -#define EPI_ADDRMAP_ECSZ_M 0x00000C00 // External Code Size -#define EPI_ADDRMAP_ECSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_ECSZ_64KB 0x00000400 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_ECSZ_16MB 0x00000800 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_ECSZ_256MB 0x00000C00 // 256MB; lower address range: - // 0x000.0000 to 0x0FFF.FFFF -#define EPI_ADDRMAP_ECADR_M 0x00000300 // External Code Address -#define EPI_ADDRMAP_ECADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_ECADR_1000 0x00000100 // At 0x1000.0000 -#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size -#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range: - // 0x000.0000 to 0xFFF.FFFF -#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address -#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000 -#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000 -#define EPI_ADDRMAP_EPADR_HBQS 0x00000030 // Only to be used with Host Bus - // quad chip select. In quad chip - // select mode, CS2n maps to - // 0xA000.0000 and CS3n maps to - // 0xC000.0000 -#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size -#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range: - // 0x000.0000 to 0xFFF.FFFF -#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address -#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000 -#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000 -#define EPI_ADDRMAP_ERADR_HBQS 0x00000003 // Only to be used with Host Bus - // quad chip select. In quad chip - // select mode, CS0n maps to - // 0x6000.0000 and CS1n maps to - // 0x8000.0000 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RSIZE0 register. -// -//***************************************************************************** -#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size -#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits) -#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits) -#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RADDR0 register. -// -//***************************************************************************** -#define EPI_RADDR0_ADDR_M 0xFFFFFFFF // Current Address -#define EPI_RADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RPSTD0 register. -// -//***************************************************************************** -#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count -#define EPI_RPSTD0_POSTCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RSIZE1 register. -// -//***************************************************************************** -#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size -#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits) -#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits) -#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RADDR1 register. -// -//***************************************************************************** -#define EPI_RADDR1_ADDR_M 0xFFFFFFFF // Current Address -#define EPI_RADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RPSTD1 register. -// -//***************************************************************************** -#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count -#define EPI_RPSTD1_POSTCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_STAT register. -// -//***************************************************************************** -#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full -#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty -#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence -#define EPI_STAT_WBUSY 0x00000020 // Write Busy -#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy -#define EPI_STAT_ACTIVE 0x00000001 // Register Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RFIFOCNT register. -// -//***************************************************************************** -#define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count -#define EPI_RFIFOCNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO0 -// register. -// -//***************************************************************************** -#define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO1 -// register. -// -//***************************************************************************** -#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO2 -// register. -// -//***************************************************************************** -#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO3 -// register. -// -//***************************************************************************** -#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO4 -// register. -// -//***************************************************************************** -#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO4_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO5 -// register. -// -//***************************************************************************** -#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO5_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO6 -// register. -// -//***************************************************************************** -#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO6_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO7 -// register. -// -//***************************************************************************** -#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO7_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_FIFOLVL register. -// -//***************************************************************************** -#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error -#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error -#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO -#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Interrupt is triggered while - // WRFIFO is empty. -#define EPI_FIFOLVL_WRFIFO_2 0x00000020 // Interrupt is triggered until - // there are only two slots - // available. Thus, trigger is - // deasserted when there are two - // WRFIFO entries present. This - // configuration is optimized for - // bursts of 2 -#define EPI_FIFOLVL_WRFIFO_1 0x00000030 // Interrupt is triggered until - // there is one WRFIFO entry - // available. This configuration - // expects only single writes -#define EPI_FIFOLVL_WRFIFO_NFULL \ - 0x00000040 // Trigger interrupt when WRFIFO is - // not full, meaning trigger will - // continue to assert until there - // are four entries in the WRFIFO -#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO -#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty -#define EPI_FIFOLVL_RDFIFO_1 0x00000001 // Trigger when there are 1 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_2 0x00000002 // Trigger when there are 2 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_4 0x00000003 // Trigger when there are 4 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_6 0x00000004 // Trigger when there are 6 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_7 0x00000005 // Trigger when there are 7 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_8 0x00000006 // Trigger when there are 8 entries - // in the NBRFIFO - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_WFIFOCNT register. -// -//***************************************************************************** -#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions -#define EPI_WFIFOCNT_WTAV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_DMATXCNT register. -// -//***************************************************************************** -#define EPI_DMATXCNT_TXCNT_M 0x0000FFFF // DMA Count -#define EPI_DMATXCNT_TXCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_IM register. -// -//***************************************************************************** -#define EPI_IM_DMAWRIM 0x00000010 // Write uDMA Interrupt Mask -#define EPI_IM_DMARDIM 0x00000008 // Read uDMA Interrupt Mask -#define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask -#define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask -#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RIS register. -// -//***************************************************************************** -#define EPI_RIS_DMAWRRIS 0x00000010 // Write uDMA Raw Interrupt Status -#define EPI_RIS_DMARDRIS 0x00000008 // Read uDMA Raw Interrupt Status -#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status -#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status -#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_MIS register. -// -//***************************************************************************** -#define EPI_MIS_DMAWRMIS 0x00000010 // Write uDMA Masked Interrupt - // Status -#define EPI_MIS_DMARDMIS 0x00000008 // Read uDMA Masked Interrupt - // Status -#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status -#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status -#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_EISC register. -// -//***************************************************************************** -#define EPI_EISC_DMAWRIC 0x00000010 // Write uDMA Interrupt Clear -#define EPI_EISC_DMARDIC 0x00000008 // Read uDMA Interrupt Clear -#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error -#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error -#define EPI_EISC_TOUT 0x00000001 // Timeout Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG3 register. -// -//***************************************************************************** -#define EPI_HB8CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity -#define EPI_HB8CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB8CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity -#define EPI_HB8CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States -#define EPI_HB8CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG3_RDWS_M 0x00000030 // CS2n Read Wait States -#define EPI_HB8CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode -#define EPI_HB8CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG3_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG3 register. -// -//***************************************************************************** -#define EPI_HB16CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity -#define EPI_HB16CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB16CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity -#define EPI_HB16CFG3_WRCRE 0x00040000 // CS2n PSRAM Configuration - // Register Write -#define EPI_HB16CFG3_RDCRE 0x00020000 // CS2n PSRAM Configuration - // Register Read -#define EPI_HB16CFG3_BURST 0x00010000 // CS2n Burst Mode -#define EPI_HB16CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States -#define EPI_HB16CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG3_RDWS_M 0x00000030 // CS2n Read Wait States -#define EPI_HB16CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode -#define EPI_HB16CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG3_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG4 register. -// -//***************************************************************************** -#define EPI_HB16CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity -#define EPI_HB16CFG4_RDHIGH 0x00100000 // CS3n READ Strobe Polarity -#define EPI_HB16CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity -#define EPI_HB16CFG4_WRCRE 0x00040000 // CS3n PSRAM Configuration - // Register Write -#define EPI_HB16CFG4_RDCRE 0x00020000 // CS3n PSRAM Configuration - // Register Read -#define EPI_HB16CFG4_BURST 0x00010000 // CS3n Burst Mode -#define EPI_HB16CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States -#define EPI_HB16CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG4_RDWS_M 0x00000030 // CS3n Read Wait States -#define EPI_HB16CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode -#define EPI_HB16CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG4_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG4 register. -// -//***************************************************************************** -#define EPI_HB8CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity -#define EPI_HB8CFG4_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB8CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity -#define EPI_HB8CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States -#define EPI_HB8CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG4_RDWS_M 0x00000030 // CS3n Read Wait States -#define EPI_HB8CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode -#define EPI_HB8CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG4_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME register. -// -//***************************************************************************** -#define EPI_HB8TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay -#define EPI_HB8TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture - // Width -#define EPI_HB8TIME_WRWSM 0x00000010 // Write Wait State Minus One -#define EPI_HB8TIME_RDWSM 0x00000001 // Read Wait State Minus One -#define EPI_HB8TIME_IRDYDLY_S 24 -#define EPI_HB8TIME_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME register. -// -//***************************************************************************** -#define EPI_HB16TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay -#define EPI_HB16TIME_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture - // Width -#define EPI_HB16TIME_WRWSM 0x00000010 // Write Wait State Minus One -#define EPI_HB16TIME_RDWSM 0x00000001 // Read Wait State Minus One -#define EPI_HB16TIME_IRDYDLY_S 24 -#define EPI_HB16TIME_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME2 register. -// -//***************************************************************************** -#define EPI_HB8TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay -#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000 // CS1n Inter-transfer Capture - // Width -#define EPI_HB8TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One -#define EPI_HB8TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One -#define EPI_HB8TIME2_IRDYDLY_S 24 -#define EPI_HB8TIME2_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME2 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay -#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME2_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME2_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME2_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME2_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME2_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME2_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME2_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME2_CAPWIDTH_M \ - 0x00003000 // CS1n Inter-transfer Capture - // Width -#define EPI_HB16TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One -#define EPI_HB16TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One -#define EPI_HB16TIME2_IRDYDLY_S 24 -#define EPI_HB16TIME2_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME3 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay -#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME3_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME3_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME3_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME3_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME3_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME3_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME3_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME3_CAPWIDTH_M \ - 0x00003000 // CS2n Inter-transfer Capture - // Width -#define EPI_HB16TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One -#define EPI_HB16TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One -#define EPI_HB16TIME3_IRDYDLY_S 24 -#define EPI_HB16TIME3_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME3 register. -// -//***************************************************************************** -#define EPI_HB8TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay -#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000 // CS2n Inter-transfer Capture - // Width -#define EPI_HB8TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One -#define EPI_HB8TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One -#define EPI_HB8TIME3_IRDYDLY_S 24 -#define EPI_HB8TIME3_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME4 register. -// -//***************************************************************************** -#define EPI_HB8TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay -#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000 // CS3n Inter-transfer Capture - // Width -#define EPI_HB8TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One -#define EPI_HB8TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One -#define EPI_HB8TIME4_IRDYDLY_S 24 -#define EPI_HB8TIME4_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME4 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay -#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME4_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME4_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME4_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME4_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME4_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME4_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME4_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME4_CAPWIDTH_M \ - 0x00003000 // CS3n Inter-transfer Capture - // Width -#define EPI_HB16TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One -#define EPI_HB16TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One -#define EPI_HB16TIME4_IRDYDLY_S 24 -#define EPI_HB16TIME4_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HBPSRAM register. -// -//***************************************************************************** -#define EPI_HBPSRAM_CR_M 0x001FFFFF // PSRAM Config Register -#define EPI_HBPSRAM_CR_S 0 - -//***************************************************************************** -// -// The following definitions are deprecated. -// -//***************************************************************************** -#ifndef DEPRECATED - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the EPI_O_FIFOLVL -// register. -// -//***************************************************************************** -#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are up to 3 - // spaces available in the WFIFO -#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are up to 2 - // spaces available in the WFIFO -#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space - // available in the WFIFO -#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries - // in the NBRFIFO - -#endif - -#endif // __HW_EPI_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_fan.h b/bsp/tm4c129x-dk/libraries/inc/hw_fan.h deleted file mode 100644 index 9c191cf0af6b2a598b5d3cf923e5486fa7680dab..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_fan.h +++ /dev/null @@ -1,49 +0,0 @@ -//***************************************************************************** -// -// hw_fan.h - Macros used when accessing the fan control hardware. -// -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_FAN_H__ -#define __HW_FAN_H__ - -//***************************************************************************** -// -// The following are defines for the Fan Control register offsets. -// -//***************************************************************************** - -#endif // __HW_FAN_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_flash.h b/bsp/tm4c129x-dk/libraries/inc/hw_flash.h deleted file mode 100644 index e38e85b59d0bac83af4d473395c4437c3c599ffe..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_flash.h +++ /dev/null @@ -1,625 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following are defines for the FLASH register offsets. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Flash Memory Address -#define FLASH_FMD 0x400FD004 // Flash Memory Data -#define FLASH_FMC 0x400FD008 // Flash Memory Control -#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt - // Status -#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask -#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked - // Interrupt Status and Clear -#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2 -#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid -#define FLASH_FLPEKEY 0x400FD03C // Flash Program/Erase Key -#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n -#define FLASH_PP 0x400FDFC0 // Flash Peripheral Properties -#define FLASH_FSIZE 0x400FDFC0 // Flash Size -#define FLASH_SSIZE 0x400FDFC4 // SRAM Size -#define FLASH_CONF 0x400FDFC8 // Flash Configuration Register -#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map -#define FLASH_DMASZ 0x400FDFD0 // Flash DMA Address Size -#define FLASH_DMAST 0x400FDFD4 // Flash DMA Starting Address -#define FLASH_RVP 0x400FE0D4 // Reset Vector Pointer -#define FLASH_RMCTL 0x400FE0F0 // ROM Control -#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration -#define FLASH_USERREG0 0x400FE1E0 // User Register 0 -#define FLASH_USERREG1 0x400FE1E4 // User Register 1 -#define FLASH_USERREG2 0x400FE1E8 // User Register 2 -#define FLASH_USERREG3 0x400FE1EC // User Register 3 -#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read - // Enable 0 -#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read - // Enable 1 -#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read - // Enable 2 -#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read - // Enable 3 -#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read - // Enable 4 -#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read - // Enable 5 -#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read - // Enable 6 -#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read - // Enable 7 -#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read - // Enable 8 -#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read - // Enable 9 -#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read - // Enable 10 -#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read - // Enable 11 -#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read - // Enable 12 -#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read - // Enable 13 -#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read - // Enable 14 -#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read - // Enable 15 -#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program - // Enable 0 -#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program - // Enable 1 -#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program - // Enable 2 -#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program - // Enable 3 -#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program - // Enable 4 -#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program - // Enable 5 -#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program - // Enable 6 -#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program - // Enable 7 -#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program - // Enable 8 -#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program - // Enable 9 -#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program - // Enable 10 -#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program - // Enable 11 -#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program - // Enable 12 -#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program - // Enable 13 -#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program - // Enable 14 -#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program - // Enable 15 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMA register. -// -//***************************************************************************** -#define FLASH_FMA_OFFSET_M 0x000FFFFF // Address Offset -#define FLASH_FMA_OFFSET_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMD register. -// -//***************************************************************************** -#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value -#define FLASH_FMD_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit Register Value -#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory -#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory -#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw - // Interrupt Status -#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt - // Status -#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt - // Status -#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt - // Status -#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status -#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status -#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask -#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask -#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask -#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask -#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask -#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask -#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCMISC register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt - // Status and Clear -#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and - // Clear -#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt - // Status and Clear -#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMC2 register. -// -//***************************************************************************** -#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FWBVAL register. -// -//***************************************************************************** -#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FLPEKEY register. -// -//***************************************************************************** -#define FLASH_FLPEKEY_PEKEY_M 0x0000FFFF // Key Value -#define FLASH_FLPEKEY_PEKEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FWBN register. -// -//***************************************************************************** -#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_PP register. -// -//***************************************************************************** -#define FLASH_PP_PFC 0x40000000 // Prefetch Buffer Mode -#define FLASH_PP_FMM 0x20000000 // Flash Mirror Mode -#define FLASH_PP_DFA 0x10000000 // DMA Flash Access -#define FLASH_PP_EESS_M 0x00780000 // EEPROM Sector Size of the - // physical bank -#define FLASH_PP_EESS_1KB 0x00000000 // 1 KB -#define FLASH_PP_EESS_2KB 0x00080000 // 2 KB -#define FLASH_PP_EESS_4KB 0x00100000 // 4 KB -#define FLASH_PP_EESS_8KB 0x00180000 // 8 KB -#define FLASH_PP_MAINSS_M 0x00070000 // Flash Sector Size of the - // physical bank -#define FLASH_PP_MAINSS_1KB 0x00000000 // 1 KB -#define FLASH_PP_MAINSS_2KB 0x00010000 // 2 KB -#define FLASH_PP_MAINSS_4KB 0x00020000 // 4 KB -#define FLASH_PP_MAINSS_8KB 0x00030000 // 8 KB -#define FLASH_PP_MAINSS_16KB 0x00040000 // 16 KB -#define FLASH_PP_SIZE_M 0x0000FFFF // Flash Size -#define FLASH_PP_SIZE_512KB 0x000000FF // 512 KB of Flash -#define FLASH_PP_SIZE_1MB 0x000001FF // 1024 KB of Flash - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FSIZE register. -// -//***************************************************************************** -#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size -#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash -#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash -#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash -#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_SSIZE register. -// -//***************************************************************************** -#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size -#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM -#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM -#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM -#define FLASH_SSIZE_SIZE_256KB 0x000003FF // 256 KB of SRAM - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CONF register. -// -//***************************************************************************** -#define FLASH_CONF_FMME 0x40000000 // Flash Mirror Mode Enable -#define FLASH_CONF_SPFE 0x20000000 // Single Prefetch Mode Enable -#define FLASH_CONF_CLRTV 0x00100000 // Clear Valid Tags -#define FLASH_CONF_FPFON 0x00020000 // Force Prefetch On -#define FLASH_CONF_FPFOFF 0x00010000 // Force Prefetch Off - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_ROMSWMAP register. -// -//***************************************************************************** -#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present -#define FLASH_ROMSWMAP_SW0EN_M 0x00000003 // ROM SW Region 0 Availability -#define FLASH_ROMSWMAP_SW0EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW0EN_CORE \ - 0x00000001 // Region available to core -#define FLASH_ROMSWMAP_SW1EN_M 0x0000000C // ROM SW Region 1 Availability -#define FLASH_ROMSWMAP_SW1EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW1EN_CORE \ - 0x00000004 // Region available to core -#define FLASH_ROMSWMAP_SW2EN_M 0x00000030 // ROM SW Region 2 Availability -#define FLASH_ROMSWMAP_SW2EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW2EN_CORE \ - 0x00000010 // Region available to core -#define FLASH_ROMSWMAP_SW3EN_M 0x000000C0 // ROM SW Region 3 Availability -#define FLASH_ROMSWMAP_SW3EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW3EN_CORE \ - 0x00000040 // Region available to core -#define FLASH_ROMSWMAP_SW4EN_M 0x00000300 // ROM SW Region 4 Availability -#define FLASH_ROMSWMAP_SW4EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW4EN_CORE \ - 0x00000100 // Region available to core -#define FLASH_ROMSWMAP_SW5EN_M 0x00000C00 // ROM SW Region 5 Availability -#define FLASH_ROMSWMAP_SW5EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW5EN_CORE \ - 0x00000400 // Region available to core -#define FLASH_ROMSWMAP_SW6EN_M 0x00003000 // ROM SW Region 6 Availability -#define FLASH_ROMSWMAP_SW6EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW6EN_CORE \ - 0x00001000 // Region available to core -#define FLASH_ROMSWMAP_SW7EN_M 0x0000C000 // ROM SW Region 7 Availability -#define FLASH_ROMSWMAP_SW7EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW7EN_CORE \ - 0x00004000 // Region available to core - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_DMASZ register. -// -//***************************************************************************** -#define FLASH_DMASZ_SIZE_M 0x0003FFFF // uDMA-accessible Memory Size -#define FLASH_DMASZ_SIZE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_DMAST register. -// -//***************************************************************************** -#define FLASH_DMAST_ADDR_M 0x1FFFF800 // Contains the starting address of - // the flash region accessible by - // uDMA if the FLASHPP register DFA - // bit is set -#define FLASH_DMAST_ADDR_S 11 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_RVP register. -// -//***************************************************************************** -#define FLASH_RVP_RV_M 0xFFFFFFFF // Reset Vector Pointer Address -#define FLASH_RVP_RV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_RMCTL register. -// -//***************************************************************************** -#define FLASH_RMCTL_BA 0x00000001 // Boot Alias - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_BOOTCFG register. -// -//***************************************************************************** -#define FLASH_BOOTCFG_NW 0x80000000 // Not Written -#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port -#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A -#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B -#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C -#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D -#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E -#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F -#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G -#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H -#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin -#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0 -#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1 -#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2 -#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3 -#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4 -#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5 -#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6 -#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7 -#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity -#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable -#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select -#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1 -#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG0 register. -// -//***************************************************************************** -#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG1 register. -// -//***************************************************************************** -#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG2 register. -// -//***************************************************************************** -#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG3 register. -// -//***************************************************************************** -#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE8 register. -// -//***************************************************************************** -#define FLASH_FMPRE8_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE8_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE9 register. -// -//***************************************************************************** -#define FLASH_FMPRE9_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE9_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE10 register. -// -//***************************************************************************** -#define FLASH_FMPRE10_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE10_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE11 register. -// -//***************************************************************************** -#define FLASH_FMPRE11_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE11_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE12 register. -// -//***************************************************************************** -#define FLASH_FMPRE12_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE12_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE13 register. -// -//***************************************************************************** -#define FLASH_FMPRE13_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE13_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE14 register. -// -//***************************************************************************** -#define FLASH_FMPRE14_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE14_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE15 register. -// -//***************************************************************************** -#define FLASH_FMPRE15_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE15_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE8 register. -// -//***************************************************************************** -#define FLASH_FMPPE8_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE8_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE9 register. -// -//***************************************************************************** -#define FLASH_FMPPE9_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE9_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE10 register. -// -//***************************************************************************** -#define FLASH_FMPPE10_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE10_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE11 register. -// -//***************************************************************************** -#define FLASH_FMPPE11_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE11_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE12 register. -// -//***************************************************************************** -#define FLASH_FMPPE12_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE12_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE13 register. -// -//***************************************************************************** -#define FLASH_FMPPE13_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE13_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE14 register. -// -//***************************************************************************** -#define FLASH_FMPPE14_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE14_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE15 register. -// -//***************************************************************************** -#define FLASH_FMPPE15_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE15_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the erase size of the FLASH block that is -// erased by an erase operation, and the protect size is the size of the FLASH -// block that is protected by each protection register. -// -//***************************************************************************** -#define FLASH_PROTECT_SIZE 0x00000800 -#define FLASH_ERASE_SIZE 0x00000400 - -#endif // __HW_FLASH_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_gpio.h b/bsp/tm4c129x-dk/libraries/inc/hw_gpio.h deleted file mode 100644 index 9e95aed4355c92d49aabc2d60f8ed90a8287abb6..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_gpio.h +++ /dev/null @@ -1,213 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// The following are defines for the GPIO register offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // GPIO Data -#define GPIO_O_DIR 0x00000400 // GPIO Direction -#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense -#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges -#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event -#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask -#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status -#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status -#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear -#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select -#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select -#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select -#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select -#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select -#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select -#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select -#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select -#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable -#define GPIO_O_LOCK 0x00000520 // GPIO Lock -#define GPIO_O_CR 0x00000524 // GPIO Commit -#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select -#define GPIO_O_PCTL 0x0000052C // GPIO Port Control -#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control -#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control -#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt -#define GPIO_O_DR12R 0x0000053C // GPIO 12-mA Drive Select -#define GPIO_O_WAKEPEN 0x00000540 // GPIO Wake Pin Enable -#define GPIO_O_WAKELVL 0x00000544 // GPIO Wake Level -#define GPIO_O_WAKESTAT 0x00000548 // GPIO Wake Status -#define GPIO_O_PP 0x00000FC0 // GPIO Peripheral Property -#define GPIO_O_PC 0x00000FC4 // GPIO Peripheral Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_IM register. -// -//***************************************************************************** -#define GPIO_IM_DMAIME 0x00000100 // GPIO uDMA Done Interrupt Mask - // Enable -#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable -#define GPIO_IM_GPIO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_RIS register. -// -//***************************************************************************** -#define GPIO_RIS_DMARIS 0x00000100 // GPIO uDMA Done Interrupt Raw - // Status -#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status -#define GPIO_RIS_GPIO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_MIS register. -// -//***************************************************************************** -#define GPIO_MIS_DMAMIS 0x00000100 // GPIO uDMA Done Masked Interrupt - // Status -#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status -#define GPIO_MIS_GPIO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_ICR register. -// -//***************************************************************************** -#define GPIO_ICR_DMAIC 0x00000100 // GPIO uDMA Interrupt Clear -#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear -#define GPIO_ICR_GPIO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_LOCK register. -// -//***************************************************************************** -#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock -#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked - // and may be modified -#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked - // and may not be modified -#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_SI register. -// -//***************************************************************************** -#define GPIO_SI_SUM 0x00000001 // Summary Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_DR12R register. -// -//***************************************************************************** -#define GPIO_DR12R_DRV12_M 0x000000FF // Output Pad 12-mA Drive Enable -#define GPIO_DR12R_DRV12_12MA 0x00000001 // The corresponding GPIO pin has - // 12-mA drive. This encoding is - // only valid if the GPIOPP EDE bit - // is set and the appropriate - // GPIOPC EDM bit field is - // programmed to 0x3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_WAKEPEN register. -// -//***************************************************************************** -#define GPIO_WAKEPEN_WAKEP4 0x00000010 // P[4] Wake Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_WAKELVL register. -// -//***************************************************************************** -#define GPIO_WAKELVL_WAKELVL4 0x00000010 // P[4] Wake Level - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_WAKESTAT -// register. -// -//***************************************************************************** -#define GPIO_WAKESTAT_STAT4 0x00000010 // P[4] Wake Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_PP register. -// -//***************************************************************************** -#define GPIO_PP_EDE 0x00000001 // Extended Drive Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_PC register. -// -//***************************************************************************** -#define GPIO_PC_EDM7_M 0x0000C000 // Extended Drive Mode Bit 7 -#define GPIO_PC_EDM6_M 0x00003000 // Extended Drive Mode Bit 6 -#define GPIO_PC_EDM5_M 0x00000C00 // Extended Drive Mode Bit 5 -#define GPIO_PC_EDM4_M 0x00000300 // Extended Drive Mode Bit 4 -#define GPIO_PC_EDM3_M 0x000000C0 // Extended Drive Mode Bit 3 -#define GPIO_PC_EDM2_M 0x00000030 // Extended Drive Mode Bit 2 -#define GPIO_PC_EDM1_M 0x0000000C // Extended Drive Mode Bit 1 -#define GPIO_PC_EDM0_M 0x00000003 // Extended Drive Mode Bit 0 -#define GPIO_PC_EDM0_DISABLE 0x00000000 // Drive values of 2, 4 and 8 mA - // are maintained. GPIO n Drive - // Select (GPIODRnR) registers - // function as normal -#define GPIO_PC_EDM0_6MA 0x00000001 // An additional 6 mA option is - // provided -#define GPIO_PC_EDM0_PLUS2MA 0x00000003 // A 2 mA driver is always enabled; - // setting the corresponding - // GPIODR4R register bit adds 2 mA - // and setting the corresponding - // GPIODR8R of GPIODR12R register - // bit adds an additional 4 mA -#define GPIO_PC_EDM7_S 14 -#define GPIO_PC_EDM6_S 12 -#define GPIO_PC_EDM5_S 10 -#define GPIO_PC_EDM4_S 8 -#define GPIO_PC_EDM3_S 6 -#define GPIO_PC_EDM2_S 4 -#define GPIO_PC_EDM1_S 2 - -#endif // __HW_GPIO_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_hibernate.h b/bsp/tm4c129x-dk/libraries/inc/hw_hibernate.h deleted file mode 100644 index ce469a20e1e30d4771add0725def7a5c742f9e66..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_hibernate.h +++ /dev/null @@ -1,483 +0,0 @@ -//***************************************************************************** -// -// hw_hibernate.h - Defines and Macros for the Hibernation module. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_HIBERNATE_H__ -#define __HW_HIBERNATE_H__ - -//***************************************************************************** -// -// The following are defines for the Hibernation module register addresses. -// -//***************************************************************************** -#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter -#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0 -#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load -#define HIB_CTL 0x400FC010 // Hibernation Control -#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask -#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status -#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt - // Status -#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear -#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim -#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds -#define HIB_IO 0x400FC02C // Hibernation IO Configuration -#define HIB_DATA 0x400FC030 // Hibernation Data -#define HIB_CALCTL 0x400FC300 // Hibernation Calendar Control -#define HIB_CAL0 0x400FC310 // Hibernation Calendar 0 -#define HIB_CAL1 0x400FC314 // Hibernation Calendar 1 -#define HIB_CALLD0 0x400FC320 // Hibernation Calendar Load 0 -#define HIB_CALLD1 0x400FC324 // Hibernation Calendar Load -#define HIB_CALM0 0x400FC330 // Hibernation Calendar Match 0 -#define HIB_CALM1 0x400FC334 // Hibernation Calendar Match 1 -#define HIB_LOCK 0x400FC360 // Hibernation Lock -#define HIB_TPCTL 0x400FC400 // HIB Tamper Control -#define HIB_TPSTAT 0x400FC404 // HIB Tamper Status -#define HIB_TPIO 0x400FC410 // HIB Tamper I/O Control -#define HIB_TPLOG0 0x400FC4E0 // HIB Tamper Log 0 -#define HIB_TPLOG1 0x400FC4E4 // HIB Tamper Log 1 -#define HIB_TPLOG2 0x400FC4E8 // HIB Tamper Log 2 -#define HIB_TPLOG3 0x400FC4EC // HIB Tamper Log 3 -#define HIB_TPLOG4 0x400FC4F0 // HIB Tamper Log 4 -#define HIB_TPLOG5 0x400FC4F4 // HIB Tamper Log 5 -#define HIB_TPLOG6 0x400FC4F8 // HIB Tamper Log 6 -#define HIB_TPLOG7 0x400FC4FC // HIB Tamper Log 7 -#define HIB_PP 0x400FCFC0 // Hibernation Peripheral - // Properties -#define HIB_CC 0x400FCFC8 // Hibernation Clock Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCC register. -// -//***************************************************************************** -#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter -#define HIB_RTCC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCM0 register. -// -//***************************************************************************** -#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 -#define HIB_RTCM0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCLD register. -// -//***************************************************************************** -#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load -#define HIB_RTCLD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CTL register. -// -//***************************************************************************** -#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable -#define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear -#define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select -#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability -#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass -#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery - // Comparator -#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts -#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) -#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts -#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts -#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status -#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery -#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered -#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable -#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable -#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable -#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable -#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request -#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IM register. -// -//***************************************************************************** -#define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask -#define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Mask -#define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask -#define HIB_IM_WC 0x00000010 // External Write Complete/Capable - // Interrupt Mask -#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask -#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt - // Mask -#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RIS register. -// -//***************************************************************************** -#define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status -#define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw - // Interrupt Status -#define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt - // Status -#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw - // Interrupt Status -#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt - // Status -#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw - // Interrupt Status -#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_MIS register. -// -//***************************************************************************** -#define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask -#define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Mask -#define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask -#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked - // Interrupt Status -#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked - // Interrupt Status -#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked - // Interrupt Status -#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IC register. -// -//***************************************************************************** -#define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear -#define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Clear -#define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear -#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt - // Clear -#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear -#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt - // Clear -#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCT register. -// -//***************************************************************************** -#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value -#define HIB_RTCT_TRIM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCSS register. -// -//***************************************************************************** -#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match -#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count -#define HIB_RTCSS_RTCSSM_S 16 -#define HIB_RTCSS_RTCSSC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IO register. -// -//***************************************************************************** -#define HIB_IO_IOWRC 0x80000000 // I/O Write Complete -#define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable -#define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_DATA register. -// -//***************************************************************************** -#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data -#define HIB_DATA_RTD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALCTL register. -// -//***************************************************************************** -#define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode -#define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CAL0 register. -// -//***************************************************************************** -#define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load -#define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CAL0_HR_M 0x001F0000 // Hours -#define HIB_CAL0_MIN_M 0x00003F00 // Minutes -#define HIB_CAL0_SEC_M 0x0000003F // Seconds -#define HIB_CAL0_HR_S 16 -#define HIB_CAL0_MIN_S 8 -#define HIB_CAL0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CAL1 register. -// -//***************************************************************************** -#define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load -#define HIB_CAL1_DOW_M 0x07000000 // Day of Week -#define HIB_CAL1_YEAR_M 0x007F0000 // Year Value -#define HIB_CAL1_MON_M 0x00000F00 // Month -#define HIB_CAL1_DOM_M 0x0000001F // Day of Month -#define HIB_CAL1_DOW_S 24 -#define HIB_CAL1_YEAR_S 16 -#define HIB_CAL1_MON_S 8 -#define HIB_CAL1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALLD0 register. -// -//***************************************************************************** -#define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CALLD0_HR_M 0x001F0000 // Hours -#define HIB_CALLD0_MIN_M 0x00003F00 // Minutes -#define HIB_CALLD0_SEC_M 0x0000003F // Seconds -#define HIB_CALLD0_HR_S 16 -#define HIB_CALLD0_MIN_S 8 -#define HIB_CALLD0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALLD1 register. -// -//***************************************************************************** -#define HIB_CALLD1_DOW_M 0x07000000 // Day of Week -#define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value -#define HIB_CALLD1_MON_M 0x00000F00 // Month -#define HIB_CALLD1_DOM_M 0x0000001F // Day of Month -#define HIB_CALLD1_DOW_S 24 -#define HIB_CALLD1_YEAR_S 16 -#define HIB_CALLD1_MON_S 8 -#define HIB_CALLD1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALM0 register. -// -//***************************************************************************** -#define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CALM0_HR_M 0x001F0000 // Hours -#define HIB_CALM0_MIN_M 0x00003F00 // Minutes -#define HIB_CALM0_SEC_M 0x0000003F // Seconds -#define HIB_CALM0_HR_S 16 -#define HIB_CALM0_MIN_S 8 -#define HIB_CALM0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALM1 register. -// -//***************************************************************************** -#define HIB_CALM1_DOM_M 0x0000001F // Day of Month -#define HIB_CALM1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_LOCK register. -// -//***************************************************************************** -#define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock -#define HIB_LOCK_HIBLOCK_KEY 0xA3359554 // Hibernate Lock Key -#define HIB_LOCK_HIBLOCK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPCTL register. -// -//***************************************************************************** -#define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper - // Event -#define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event -#define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on - // tamper event -#define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB - // memory on tamper event -#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB - // memory on tamper event -#define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper - // event -#define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear -#define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPSTAT register. -// -//***************************************************************************** -#define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status -#define HIB_TPSTAT_STATE_DISABLED \ - 0x00000000 // Tamper disabled -#define HIB_TPSTAT_STATE_CONFIGED \ - 0x00000004 // Tamper configured -#define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred -#define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status -#define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPIO register. -// -//***************************************************************************** -#define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering -#define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level -#define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable -#define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering -#define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level -#define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable -#define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering -#define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level -#define HIB_TPIO_EN1 0x00000100 // TMPR1Enable -#define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering -#define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level -#define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG0 register. -// -//***************************************************************************** -#define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG0_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG1 register. -// -//***************************************************************************** -#define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG2 register. -// -//***************************************************************************** -#define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG2_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG3 register. -// -//***************************************************************************** -#define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG4 register. -// -//***************************************************************************** -#define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG4_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG5 register. -// -//***************************************************************************** -#define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG6 register. -// -//***************************************************************************** -#define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG6_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG7 register. -// -//***************************************************************************** -#define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_PP register. -// -//***************************************************************************** -#define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence -#define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CC register. -// -//***************************************************************************** -#define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable - -#endif // __HW_HIBERNATE_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_i2c.h b/bsp/tm4c129x-dk/libraries/inc/hw_i2c.h deleted file mode 100644 index d9d00b5d57075ac2a1360406b2946f5901cbb0e6..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_i2c.h +++ /dev/null @@ -1,470 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following are defines for the I2C register offsets. -// -//***************************************************************************** -#define I2C_O_MSA 0x00000000 // I2C Master Slave Address -#define I2C_O_MCS 0x00000004 // I2C Master Control/Status -#define I2C_O_MDR 0x00000008 // I2C Master Data -#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period -#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask -#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status -#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt - // Status -#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear -#define I2C_O_MCR 0x00000020 // I2C Master Configuration -#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout - // Count -#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor -#define I2C_O_MBLEN 0x00000030 // I2C Master Burst Length -#define I2C_O_MBCNT 0x00000034 // I2C Master Burst Count -#define I2C_O_MCR2 0x00000038 // I2C Master Configuration 2 -#define I2C_O_SOAR 0x00000800 // I2C Slave Own Address -#define I2C_O_SCSR 0x00000804 // I2C Slave Control/Status -#define I2C_O_SDR 0x00000808 // I2C Slave Data -#define I2C_O_SIMR 0x0000080C // I2C Slave Interrupt Mask -#define I2C_O_SRIS 0x00000810 // I2C Slave Raw Interrupt Status -#define I2C_O_SMIS 0x00000814 // I2C Slave Masked Interrupt - // Status -#define I2C_O_SICR 0x00000818 // I2C Slave Interrupt Clear -#define I2C_O_SOAR2 0x0000081C // I2C Slave Own Address 2 -#define I2C_O_SACKCTL 0x00000820 // I2C Slave ACK Control -#define I2C_O_FIFODATA 0x00000F00 // I2C FIFO Data -#define I2C_O_FIFOCTL 0x00000F04 // I2C FIFO Control -#define I2C_O_FIFOSTATUS 0x00000F08 // I2C FIFO Status -#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties -#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MSA register. -// -//***************************************************************************** -#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address -#define I2C_MSA_RS 0x00000001 // Receive not send -#define I2C_MSA_SA_S 1 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCS register. -// -//***************************************************************************** -#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error -#define I2C_MCS_BURST 0x00000040 // Burst Enable -#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy -#define I2C_MCS_IDLE 0x00000020 // I2C Idle -#define I2C_MCS_QCMD 0x00000020 // Quick Command -#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost -#define I2C_MCS_HS 0x00000010 // High-Speed Enable -#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable -#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data -#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address -#define I2C_MCS_STOP 0x00000004 // Generate STOP -#define I2C_MCS_ERROR 0x00000002 // Error -#define I2C_MCS_START 0x00000002 // Generate START -#define I2C_MCS_RUN 0x00000001 // I2C Master Enable -#define I2C_MCS_BUSY 0x00000001 // I2C Busy - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MDR register. -// -//***************************************************************************** -#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data - // transferred during a transaction -#define I2C_MDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MTPR register. -// -//***************************************************************************** -#define I2C_MTPR_PULSEL_M 0x00070000 // Glitch Suppression Pulse Width -#define I2C_MTPR_PULSEL_BYPASS 0x00000000 // Bypass -#define I2C_MTPR_PULSEL_1 0x00010000 // 1 clock -#define I2C_MTPR_PULSEL_2 0x00020000 // 2 clocks -#define I2C_MTPR_PULSEL_3 0x00030000 // 3 clocks -#define I2C_MTPR_PULSEL_4 0x00040000 // 4 clocks -#define I2C_MTPR_PULSEL_8 0x00050000 // 8 clocks -#define I2C_MTPR_PULSEL_16 0x00060000 // 16 clocks -#define I2C_MTPR_PULSEL_31 0x00070000 // 31 clocks -#define I2C_MTPR_HS 0x00000080 // High-Speed Enable -#define I2C_MTPR_TPR_M 0x0000007F // Timer Period -#define I2C_MTPR_TPR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MIMR register. -// -//***************************************************************************** -#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt - // Mask -#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask -#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask -#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask -#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask -#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MRIS register. -// -//***************************************************************************** -#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt - // Status -#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt - // Status -#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt - // Status -#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt - // Status -#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt - // Status -#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt - // Status -#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt - // Status -#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status -#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt - // Status -#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MMIS register. -// -//***************************************************************************** -#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask -#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask -#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status -#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status -#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt - // Status -#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MICR register. -// -//***************************************************************************** -#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt - // Clear -#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt - // Clear -#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt - // Clear -#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt - // Clear -#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear -#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear -#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear -#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt - // Clear -#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear -#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear -#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear -#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCR register. -// -//***************************************************************************** -#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable -#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable -#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable -#define I2C_MCR_LPBK 0x00000001 // I2C Loopback - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. -// -//***************************************************************************** -#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count -#define I2C_MCLKOCNT_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBMON register. -// -//***************************************************************************** -#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status -#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBLEN register. -// -//***************************************************************************** -#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length -#define I2C_MBLEN_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBCNT register. -// -//***************************************************************************** -#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count -#define I2C_MBCNT_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCR2 register. -// -//***************************************************************************** -#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width -#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass -#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock -#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks -#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks -#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks -#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks -#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks -#define I2C_MCR2_GFPW_31 0x00000070 // 31 clocks - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR register. -// -//***************************************************************************** -#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address -#define I2C_SOAR_OAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SCSR register. -// -//***************************************************************************** -#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write -#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status -#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched -#define I2C_SCSR_FBR 0x00000004 // First Byte Received -#define I2C_SCSR_RXFIFO 0x00000004 // RX FIFO Enable -#define I2C_SCSR_TXFIFO 0x00000002 // TX FIFO Enable -#define I2C_SCSR_TREQ 0x00000002 // Transmit Request -#define I2C_SCSR_DA 0x00000001 // Device Active -#define I2C_SCSR_RREQ 0x00000001 // Receive Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SDR register. -// -//***************************************************************************** -#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer -#define I2C_SDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SIMR register. -// -//***************************************************************************** -#define I2C_SIMR_RXFFIM 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask -#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask -#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask -#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask -#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SRIS register. -// -//***************************************************************************** -#define I2C_SRIS_RXFFRIS 0x00000100 // Receive FIFO Full Raw Interrupt - // Status -#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt - // Status -#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt - // Status -#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status -#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt - // Status -#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt - // Status -#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SMIS register. -// -//***************************************************************************** -#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt - // Status -#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt - // Status -#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt - // Status -#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt - // Status -#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SICR register. -// -//***************************************************************************** -#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask -#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask -#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear -#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear -#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear -#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear -#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR2 register. -// -//***************************************************************************** -#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable -#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 -#define I2C_SOAR2_OAR2_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SACKCTL register. -// -//***************************************************************************** -#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value -#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFODATA register. -// -//***************************************************************************** -#define I2C_FIFODATA_DATA_M 0x000000FF // I2C TX FIFO Write Data Byte -#define I2C_FIFODATA_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOCTL register. -// -//***************************************************************************** -#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment -#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush -#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable -#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger -#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment -#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush -#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable -#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger -#define I2C_FIFOCTL_RXTRIG_S 16 -#define I2C_FIFOCTL_TXTRIG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOSTATUS -// register. -// -//***************************************************************************** -#define I2C_FIFOSTATUS_RXABVTRIG \ - 0x00040000 // RX FIFO Above Trigger Level -#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full -#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty -#define I2C_FIFOSTATUS_TXBLWTRIG \ - 0x00000004 // TX FIFO Below Trigger Level -#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full -#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PP register. -// -//***************************************************************************** -#define I2C_PP_HS 0x00000001 // High-Speed Capable - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PC register. -// -//***************************************************************************** -#define I2C_PC_HS 0x00000001 // High-Speed Capable - -#endif // __HW_I2C_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_ints.h b/bsp/tm4c129x-dk/libraries/inc/hw_ints.h deleted file mode 100644 index c75a84a6bbb45847200bf663f4cc6bc6efda731d..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_ints.h +++ /dev/null @@ -1,491 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series -// MCUs. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following are defines for the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// TM4C123 Class Interrupts -// -//***************************************************************************** -#define INT_GPIOA_TM4C123 16 // GPIO Port A -#define INT_GPIOB_TM4C123 17 // GPIO Port B -#define INT_GPIOC_TM4C123 18 // GPIO Port C -#define INT_GPIOD_TM4C123 19 // GPIO Port D -#define INT_GPIOE_TM4C123 20 // GPIO Port E -#define INT_UART0_TM4C123 21 // UART0 -#define INT_UART1_TM4C123 22 // UART1 -#define INT_SSI0_TM4C123 23 // SSI0 -#define INT_I2C0_TM4C123 24 // I2C0 -#define INT_PWM0_FAULT_TM4C123 25 // PWM0 Fault -#define INT_PWM0_0_TM4C123 26 // PWM0 Generator 0 -#define INT_PWM0_1_TM4C123 27 // PWM0 Generator 1 -#define INT_PWM0_2_TM4C123 28 // PWM0 Generator 2 -#define INT_QEI0_TM4C123 29 // QEI0 -#define INT_ADC0SS0_TM4C123 30 // ADC0 Sequence 0 -#define INT_ADC0SS1_TM4C123 31 // ADC0 Sequence 1 -#define INT_ADC0SS2_TM4C123 32 // ADC0 Sequence 2 -#define INT_ADC0SS3_TM4C123 33 // ADC0 Sequence 3 -#define INT_WATCHDOG_TM4C123 34 // Watchdog Timers 0 and 1 -#define INT_TIMER0A_TM4C123 35 // 16/32-Bit Timer 0A -#define INT_TIMER0B_TM4C123 36 // 16/32-Bit Timer 0B -#define INT_TIMER1A_TM4C123 37 // 16/32-Bit Timer 1A -#define INT_TIMER1B_TM4C123 38 // 16/32-Bit Timer 1B -#define INT_TIMER2A_TM4C123 39 // 16/32-Bit Timer 2A -#define INT_TIMER2B_TM4C123 40 // 16/32-Bit Timer 2B -#define INT_COMP0_TM4C123 41 // Analog Comparator 0 -#define INT_COMP1_TM4C123 42 // Analog Comparator 1 -#define INT_COMP2_TM4C123 43 // Analog Comparator 2 -#define INT_SYSCTL_TM4C123 44 // System Control -#define INT_FLASH_TM4C123 45 // Flash Memory Control and EEPROM - // Control -#define INT_GPIOF_TM4C123 46 // GPIO Port F -#define INT_GPIOG_TM4C123 47 // GPIO Port G -#define INT_GPIOH_TM4C123 48 // GPIO Port H -#define INT_UART2_TM4C123 49 // UART2 -#define INT_SSI1_TM4C123 50 // SSI1 -#define INT_TIMER3A_TM4C123 51 // 16/32-Bit Timer 3A -#define INT_TIMER3B_TM4C123 52 // Timer 3B -#define INT_I2C1_TM4C123 53 // I2C1 -#define INT_QEI1_TM4C123 54 // QEI1 -#define INT_CAN0_TM4C123 55 // CAN0 -#define INT_CAN1_TM4C123 56 // CAN1 -#define INT_HIBERNATE_TM4C123 59 // Hibernation Module -#define INT_USB0_TM4C123 60 // USB -#define INT_PWM0_3_TM4C123 61 // PWM Generator 3 -#define INT_UDMA_TM4C123 62 // uDMA Software -#define INT_UDMAERR_TM4C123 63 // uDMA Error -#define INT_ADC1SS0_TM4C123 64 // ADC1 Sequence 0 -#define INT_ADC1SS1_TM4C123 65 // ADC1 Sequence 1 -#define INT_ADC1SS2_TM4C123 66 // ADC1 Sequence 2 -#define INT_ADC1SS3_TM4C123 67 // ADC1 Sequence 3 -#define INT_GPIOJ_TM4C123 70 // GPIO Port J -#define INT_GPIOK_TM4C123 71 // GPIO Port K -#define INT_GPIOL_TM4C123 72 // GPIO Port L -#define INT_SSI2_TM4C123 73 // SSI2 -#define INT_SSI3_TM4C123 74 // SSI3 -#define INT_UART3_TM4C123 75 // UART3 -#define INT_UART4_TM4C123 76 // UART4 -#define INT_UART5_TM4C123 77 // UART5 -#define INT_UART6_TM4C123 78 // UART6 -#define INT_UART7_TM4C123 79 // UART7 -#define INT_I2C2_TM4C123 84 // I2C2 -#define INT_I2C3_TM4C123 85 // I2C3 -#define INT_TIMER4A_TM4C123 86 // 16/32-Bit Timer 4A -#define INT_TIMER4B_TM4C123 87 // 16/32-Bit Timer 4B -#define INT_TIMER5A_TM4C123 108 // 16/32-Bit Timer 5A -#define INT_TIMER5B_TM4C123 109 // 16/32-Bit Timer 5B -#define INT_WTIMER0A_TM4C123 110 // 32/64-Bit Timer 0A -#define INT_WTIMER0B_TM4C123 111 // 32/64-Bit Timer 0B -#define INT_WTIMER1A_TM4C123 112 // 32/64-Bit Timer 1A -#define INT_WTIMER1B_TM4C123 113 // 32/64-Bit Timer 1B -#define INT_WTIMER2A_TM4C123 114 // 32/64-Bit Timer 2A -#define INT_WTIMER2B_TM4C123 115 // 32/64-Bit Timer 2B -#define INT_WTIMER3A_TM4C123 116 // 32/64-Bit Timer 3A -#define INT_WTIMER3B_TM4C123 117 // 32/64-Bit Timer 3B -#define INT_WTIMER4A_TM4C123 118 // 32/64-Bit Timer 4A -#define INT_WTIMER4B_TM4C123 119 // 32/64-Bit Timer 4B -#define INT_WTIMER5A_TM4C123 120 // 32/64-Bit Timer 5A -#define INT_WTIMER5B_TM4C123 121 // 32/64-Bit Timer 5B -#define INT_SYSEXC_TM4C123 122 // System Exception (imprecise) -#define INT_I2C4_TM4C123 125 // I2C4 -#define INT_I2C5_TM4C123 126 // I2C5 -#define INT_GPIOM_TM4C123 127 // GPIO Port M -#define INT_GPION_TM4C123 128 // GPIO Port N -#define INT_GPIOP0_TM4C123 132 // GPIO Port P (Summary or P0) -#define INT_GPIOP1_TM4C123 133 // GPIO Port P1 -#define INT_GPIOP2_TM4C123 134 // GPIO Port P2 -#define INT_GPIOP3_TM4C123 135 // GPIO Port P3 -#define INT_GPIOP4_TM4C123 136 // GPIO Port P4 -#define INT_GPIOP5_TM4C123 137 // GPIO Port P5 -#define INT_GPIOP6_TM4C123 138 // GPIO Port P6 -#define INT_GPIOP7_TM4C123 139 // GPIO Port P7 -#define INT_GPIOQ0_TM4C123 140 // GPIO Port Q (Summary or Q0) -#define INT_GPIOQ1_TM4C123 141 // GPIO Port Q1 -#define INT_GPIOQ2_TM4C123 142 // GPIO Port Q2 -#define INT_GPIOQ3_TM4C123 143 // GPIO Port Q3 -#define INT_GPIOQ4_TM4C123 144 // GPIO Port Q4 -#define INT_GPIOQ5_TM4C123 145 // GPIO Port Q5 -#define INT_GPIOQ6_TM4C123 146 // GPIO Port Q6 -#define INT_GPIOQ7_TM4C123 147 // GPIO Port Q7 -#define INT_PWM1_0_TM4C123 150 // PWM1 Generator 0 -#define INT_PWM1_1_TM4C123 151 // PWM1 Generator 1 -#define INT_PWM1_2_TM4C123 152 // PWM1 Generator 2 -#define INT_PWM1_3_TM4C123 153 // PWM1 Generator 3 -#define INT_PWM1_FAULT_TM4C123 154 // PWM1 Fault -#define NUM_INTERRUPTS_TM4C123 155 - -//***************************************************************************** -// -// TM4C129 Class Interrupts -// -//***************************************************************************** -#define INT_GPIOA_TM4C129 16 // GPIO Port A -#define INT_GPIOB_TM4C129 17 // GPIO Port B -#define INT_GPIOC_TM4C129 18 // GPIO Port C -#define INT_GPIOD_TM4C129 19 // GPIO Port D -#define INT_GPIOE_TM4C129 20 // GPIO Port E -#define INT_UART0_TM4C129 21 // UART0 -#define INT_UART1_TM4C129 22 // UART1 -#define INT_SSI0_TM4C129 23 // SSI0 -#define INT_I2C0_TM4C129 24 // I2C0 -#define INT_PWM0_FAULT_TM4C129 25 // PWM Fault -#define INT_PWM0_0_TM4C129 26 // PWM Generator 0 -#define INT_PWM0_1_TM4C129 27 // PWM Generator 1 -#define INT_PWM0_2_TM4C129 28 // PWM Generator 2 -#define INT_QEI0_TM4C129 29 // QEI0 -#define INT_ADC0SS0_TM4C129 30 // ADC0 Sequence 0 -#define INT_ADC0SS1_TM4C129 31 // ADC0 Sequence 1 -#define INT_ADC0SS2_TM4C129 32 // ADC0 Sequence 2 -#define INT_ADC0SS3_TM4C129 33 // ADC0 Sequence 3 -#define INT_WATCHDOG_TM4C129 34 // Watchdog Timers 0 and 1 -#define INT_TIMER0A_TM4C129 35 // 16/32-Bit Timer 0A -#define INT_TIMER0B_TM4C129 36 // 16/32-Bit Timer 0B -#define INT_TIMER1A_TM4C129 37 // 16/32-Bit Timer 1A -#define INT_TIMER1B_TM4C129 38 // 16/32-Bit Timer 1B -#define INT_TIMER2A_TM4C129 39 // 16/32-Bit Timer 2A -#define INT_TIMER2B_TM4C129 40 // 16/32-Bit Timer 2B -#define INT_COMP0_TM4C129 41 // Analog Comparator 0 -#define INT_COMP1_TM4C129 42 // Analog Comparator 1 -#define INT_COMP2_TM4C129 43 // Analog Comparator 2 -#define INT_SYSCTL_TM4C129 44 // System Control -#define INT_FLASH_TM4C129 45 // Flash Memory Control -#define INT_GPIOF_TM4C129 46 // GPIO Port F -#define INT_GPIOG_TM4C129 47 // GPIO Port G -#define INT_GPIOH_TM4C129 48 // GPIO Port H -#define INT_UART2_TM4C129 49 // UART2 -#define INT_SSI1_TM4C129 50 // SSI1 -#define INT_TIMER3A_TM4C129 51 // 16/32-Bit Timer 3A -#define INT_TIMER3B_TM4C129 52 // 16/32-Bit Timer 3B -#define INT_I2C1_TM4C129 53 // I2C1 -#define INT_CAN0_TM4C129 54 // CAN 0 -#define INT_CAN1_TM4C129 55 // CAN1 -#define INT_EMAC0_TM4C129 56 // Ethernet MAC -#define INT_HIBERNATE_TM4C129 57 // HIB -#define INT_USB0_TM4C129 58 // USB MAC -#define INT_PWM0_3_TM4C129 59 // PWM Generator 3 -#define INT_UDMA_TM4C129 60 // uDMA 0 Software -#define INT_UDMAERR_TM4C129 61 // uDMA 0 Error -#define INT_ADC1SS0_TM4C129 62 // ADC1 Sequence 0 -#define INT_ADC1SS1_TM4C129 63 // ADC1 Sequence 1 -#define INT_ADC1SS2_TM4C129 64 // ADC1 Sequence 2 -#define INT_ADC1SS3_TM4C129 65 // ADC1 Sequence 3 -#define INT_EPI0_TM4C129 66 // EPI 0 -#define INT_GPIOJ_TM4C129 67 // GPIO Port J -#define INT_GPIOK_TM4C129 68 // GPIO Port K -#define INT_GPIOL_TM4C129 69 // GPIO Port L -#define INT_SSI2_TM4C129 70 // SSI 2 -#define INT_SSI3_TM4C129 71 // SSI 3 -#define INT_UART3_TM4C129 72 // UART 3 -#define INT_UART4_TM4C129 73 // UART 4 -#define INT_UART5_TM4C129 74 // UART 5 -#define INT_UART6_TM4C129 75 // UART 6 -#define INT_UART7_TM4C129 76 // UART 7 -#define INT_I2C2_TM4C129 77 // I2C 2 -#define INT_I2C3_TM4C129 78 // I2C 3 -#define INT_TIMER4A_TM4C129 79 // Timer 4A -#define INT_TIMER4B_TM4C129 80 // Timer 4B -#define INT_TIMER5A_TM4C129 81 // Timer 5A -#define INT_TIMER5B_TM4C129 82 // Timer 5B -#define INT_SYSEXC_TM4C129 83 // Floating-Point Exception - // (imprecise) -#define INT_I2C4_TM4C129 86 // I2C 4 -#define INT_I2C5_TM4C129 87 // I2C 5 -#define INT_GPIOM_TM4C129 88 // GPIO Port M -#define INT_GPION_TM4C129 89 // GPIO Port N -#define INT_TAMPER0_TM4C129 91 // Tamper -#define INT_GPIOP0_TM4C129 92 // GPIO Port P (Summary or P0) -#define INT_GPIOP1_TM4C129 93 // GPIO Port P1 -#define INT_GPIOP2_TM4C129 94 // GPIO Port P2 -#define INT_GPIOP3_TM4C129 95 // GPIO Port P3 -#define INT_GPIOP4_TM4C129 96 // GPIO Port P4 -#define INT_GPIOP5_TM4C129 97 // GPIO Port P5 -#define INT_GPIOP6_TM4C129 98 // GPIO Port P6 -#define INT_GPIOP7_TM4C129 99 // GPIO Port P7 -#define INT_GPIOQ0_TM4C129 100 // GPIO Port Q (Summary or Q0) -#define INT_GPIOQ1_TM4C129 101 // GPIO Port Q1 -#define INT_GPIOQ2_TM4C129 102 // GPIO Port Q2 -#define INT_GPIOQ3_TM4C129 103 // GPIO Port Q3 -#define INT_GPIOQ4_TM4C129 104 // GPIO Port Q4 -#define INT_GPIOQ5_TM4C129 105 // GPIO Port Q5 -#define INT_GPIOQ6_TM4C129 106 // GPIO Port Q6 -#define INT_GPIOQ7_TM4C129 107 // GPIO Port Q7 -#define INT_GPIOR_TM4C129 108 // GPIO Port R -#define INT_GPIOS_TM4C129 109 // GPIO Port S -#define INT_SHA0_TM4C129 110 // SHA/MD5 -#define INT_AES0_TM4C129 111 // AES -#define INT_DES0_TM4C129 112 // DES -#define INT_LCD0_TM4C129 113 // LCD -#define INT_TIMER6A_TM4C129 114 // 16/32-Bit Timer 6A -#define INT_TIMER6B_TM4C129 115 // 16/32-Bit Timer 6B -#define INT_TIMER7A_TM4C129 116 // 16/32-Bit Timer 7A -#define INT_TIMER7B_TM4C129 117 // 16/32-Bit Timer 7B -#define INT_I2C6_TM4C129 118 // I2C 6 -#define INT_I2C7_TM4C129 119 // I2C 7 -#define INT_ONEWIRE0_TM4C129 121 // 1-Wire -#define INT_I2C8_TM4C129 125 // I2C 8 -#define INT_I2C9_TM4C129 126 // I2C 9 -#define INT_GPIOT_TM4C129 127 // GPIO T -#define NUM_INTERRUPTS_TM4C129 129 - -//***************************************************************************** -// -// TM4C123 Interrupt Class Definition -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \ - defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \ - defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \ - defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \ - defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \ - defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \ - defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \ - defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \ - defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \ - defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \ - defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \ - defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \ - defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \ - defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \ - defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \ - defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \ - defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \ - defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \ - defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \ - defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \ - defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \ - defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \ - defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \ - defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \ - defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \ - defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \ - defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \ - defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR) -#define INT_RESOLVE(intname, class) intname##TM4C123 - -//***************************************************************************** -// -// TM4C129 Interrupt Class Definition -// -//***************************************************************************** -#elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \ - defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \ - defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \ - defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \ - defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \ - defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \ - defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \ - defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \ - defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \ - defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \ - defined(PART_TM4C129XNCZAD) -#define INT_RESOLVE(intname, class) intname##TM4C129 -#else -#define INT_DEVICE_CLASS "UNKNOWN" -#endif - -//***************************************************************************** -// -// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name. -// -//***************************************************************************** -#define INT_CONCAT(intname, class) INT_RESOLVE(intname, class) - -//***************************************************************************** -// -// The following are defines for the interrupt assignments. -// -//***************************************************************************** -#define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS) -#define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS) -#define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS) -#define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS) -#define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS) -#define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS) -#define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS) -#define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS) -#define INT_AES0 INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS) -#define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS) -#define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS) -#define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS) -#define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS) -#define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS) -#define INT_DES0 INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS) -#define INT_EMAC0 INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS) -#define INT_EPI0 INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS) -#define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS) -#define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS) -#define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS) -#define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS) -#define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS) -#define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS) -#define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS) -#define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS) -#define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS) -#define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS) -#define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS) -#define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS) -#define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS) -#define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS) -#define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS) -#define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS) -#define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS) -#define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS) -#define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS) -#define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS) -#define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS) -#define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS) -#define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS) -#define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS) -#define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS) -#define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS) -#define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS) -#define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS) -#define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS) -#define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS) -#define INT_GPIOR INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS) -#define INT_GPIOS INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS) -#define INT_GPIOT INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS) -#define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS) -#define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS) -#define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS) -#define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS) -#define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS) -#define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS) -#define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS) -#define INT_I2C6 INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS) -#define INT_I2C7 INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS) -#define INT_I2C8 INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS) -#define INT_I2C9 INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS) -#define INT_LCD0 INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS) -#define INT_ONEWIRE0 INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS) -#define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS) -#define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS) -#define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS) -#define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS) -#define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS) -#define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS) -#define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS) -#define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS) -#define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS) -#define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS) -#define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS) -#define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS) -#define INT_SHA0 INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS) -#define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS) -#define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS) -#define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS) -#define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS) -#define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS) -#define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS) -#define INT_TAMPER0 INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS) -#define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS) -#define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS) -#define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS) -#define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS) -#define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS) -#define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS) -#define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS) -#define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS) -#define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS) -#define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS) -#define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS) -#define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS) -#define INT_TIMER6A INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS) -#define INT_TIMER6B INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS) -#define INT_TIMER7A INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS) -#define INT_TIMER7B INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS) -#define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS) -#define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS) -#define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS) -#define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS) -#define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS) -#define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS) -#define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS) -#define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS) -#define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS) -#define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS) -#define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS) -#define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS) -#define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS) -#define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS) -#define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS) -#define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS) -#define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS) -#define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS) -#define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS) -#define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS) -#define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS) -#define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS) -#define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS) -#define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS) - -//***************************************************************************** -// -// The following are defines for the total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS) - -//***************************************************************************** -// -// The following are defines for the total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_lcd.h b/bsp/tm4c129x-dk/libraries/inc/hw_lcd.h deleted file mode 100644 index bf0be0ae2fe8c6dbc86e4613795103faa6e382ba..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_lcd.h +++ /dev/null @@ -1,575 +0,0 @@ -//***************************************************************************** -// -// hw_lcd.h - Defines and macros used when accessing the LCD controller. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_LCD_H__ -#define __HW_LCD_H__ - -//***************************************************************************** -// -// The following are defines for the LCD register offsets. -// -//***************************************************************************** -#define LCD_O_PID 0x00000000 // LCD PID Register Format -#define LCD_O_CTL 0x00000004 // LCD Control -#define LCD_O_LIDDCTL 0x0000000C // LCD LIDD Control -#define LCD_O_LIDDCS0CFG 0x00000010 // LCD LIDD CS0 Configuration -#define LCD_O_LIDDCS0ADDR 0x00000014 // LIDD CS0 Read/Write Address -#define LCD_O_LIDDCS0DATA 0x00000018 // LIDD CS0 Data Read/Write - // Initiation -#define LCD_O_LIDDCS1CFG 0x0000001C // LIDD CS1 Configuration -#define LCD_O_LIDDCS1ADDR 0x00000020 // LIDD CS1 Address Read/Write - // Initiation -#define LCD_O_LIDDCS1DATA 0x00000024 // LIDD CS1 Data Read/Write - // Initiation -#define LCD_O_RASTRCTL 0x00000028 // LCD Raster Control -#define LCD_O_RASTRTIM0 0x0000002C // LCD Raster Timing 0 -#define LCD_O_RASTRTIM1 0x00000030 // LCD Raster Timing 1 -#define LCD_O_RASTRTIM2 0x00000034 // LCD Raster Timing 2 -#define LCD_O_RASTRSUBP1 0x00000038 // LCD Raster Subpanel Display 1 -#define LCD_O_RASTRSUBP2 0x0000003C // LCD Raster Subpanel Display 2 -#define LCD_O_DMACTL 0x00000040 // LCD DMA Control -#define LCD_O_DMABAFB0 0x00000044 // LCD DMA Frame Buffer 0 Base - // Address -#define LCD_O_DMACAFB0 0x00000048 // LCD DMA Frame Buffer 0 Ceiling - // Address -#define LCD_O_DMABAFB1 0x0000004C // LCD DMA Frame Buffer 1 Base - // Address -#define LCD_O_DMACAFB1 0x00000050 // LCD DMA Frame Buffer 1 Ceiling - // Address -#define LCD_O_SYSCFG 0x00000054 // LCD System Configuration - // Register -#define LCD_O_RISSET 0x00000058 // LCD Interrupt Raw Status and Set - // Register -#define LCD_O_MISCLR 0x0000005C // LCD Interrupt Status and Clear -#define LCD_O_IM 0x00000060 // LCD Interrupt Mask -#define LCD_O_IENC 0x00000064 // LCD Interrupt Enable Clear -#define LCD_O_CLKEN 0x0000006C // LCD Clock Enable -#define LCD_O_CLKRESET 0x00000070 // LCD Clock Resets - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_PID register. -// -//***************************************************************************** -#define LCD_PID_MAJOR_M 0x00000700 // Major Release Number -#define LCD_PID_MINOR_M 0x0000003F // Minor Release Number -#define LCD_PID_MAJOR_S 8 -#define LCD_PID_MINOR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_CTL register. -// -//***************************************************************************** -#define LCD_CTL_CLKDIV_M 0x0000FF00 // Clock Divisor -#define LCD_CTL_UFLOWRST 0x00000002 // Underflow Restart -#define LCD_CTL_LCDMODE 0x00000001 // LCD Mode Select -#define LCD_CTL_CLKDIV_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCTL register. -// -//***************************************************************************** -#define LCD_LIDDCTL_DMACS 0x00000200 // CS0/CS1 Select for LIDD DMA - // Writes -#define LCD_LIDDCTL_DMAEN 0x00000100 // LIDD DMA Enable -#define LCD_LIDDCTL_CS1E1 0x00000080 // Chip Select 1 (CS1)/Enable 1(E1) - // Polarity Control -#define LCD_LIDDCTL_CS0E0 0x00000040 // Chip Select 0 (CS0)/Enable 0 - // (E0) Polarity Control -#define LCD_LIDDCTL_WRDIRINV 0x00000020 // Write Strobe (WR) /Direction - // (DIR) Polarity Control -#define LCD_LIDDCTL_RDEN 0x00000010 // Read Strobe (RD) /Direct Enable - // (EN) Polarity Control -#define LCD_LIDDCTL_ALE 0x00000008 // Address Latch Enable (ALE) - // Polarity Control -#define LCD_LIDDCTL_MODE_M 0x00000007 // LIDD Mode Select -#define LCD_LIDDCTL_MODE_SYNCM68 \ - 0x00000000 // Synchronous Motorola 6800 Mode -#define LCD_LIDDCTL_MODE_ASYNCM68 \ - 0x00000001 // Asynchronous Motorola 6800 Mode -#define LCD_LIDDCTL_MODE_SYNCM80 \ - 0x00000002 // Synchronous Intel 8080 mode -#define LCD_LIDDCTL_MODE_ASYNCM80 \ - 0x00000003 // Asynchronous Intel 8080 mode -#define LCD_LIDDCTL_MODE_ASYNCHIT \ - 0x00000004 // Asynchronous Hitachi mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS0CFG -// register. -// -//***************************************************************************** -#define LCD_LIDDCS0CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles -#define LCD_LIDDCS0CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration - // Cycles -#define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles -#define LCD_LIDDCS0CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles -#define LCD_LIDDCS0CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles -#define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles -#define LCD_LIDDCS0CFG_GAP_M 0x00000003 // Field value defines the number - // of LCDMCLK cycles (GAP +1) - // between the end of one CS0 - // (LCDAC) device access and the - // start of another CS0 (LCDAC) - // device access unless the two - // accesses are both reads -#define LCD_LIDDCS0CFG_WRSU_S 27 -#define LCD_LIDDCS0CFG_WRDUR_S 21 -#define LCD_LIDDCS0CFG_WRHOLD_S 17 -#define LCD_LIDDCS0CFG_RDSU_S 12 -#define LCD_LIDDCS0CFG_RDDUR_S 6 -#define LCD_LIDDCS0CFG_RDHOLD_S 2 -#define LCD_LIDDCS0CFG_GAP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR -// register. -// -//***************************************************************************** -#define LCD_LIDDCS0ADDR_CS0ADDR_M \ - 0x0000FFFF // LCD Address -#define LCD_LIDDCS0ADDR_CS0ADDR_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS0DATA -// register. -// -//***************************************************************************** -#define LCD_LIDDCS0DATA_CS0DATA_M \ - 0x0000FFFF // LCD Data Read/Write -#define LCD_LIDDCS0DATA_CS0DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS1CFG -// register. -// -//***************************************************************************** -#define LCD_LIDDCS1CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles -#define LCD_LIDDCS1CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration - // Cycles -#define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles -#define LCD_LIDDCS1CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles -#define LCD_LIDDCS1CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles -#define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles -#define LCD_LIDDCS1CFG_GAP_M 0x00000003 // Field value defines the number - // of LCDMCLK cycles (GAP + 1) - // between the end of one CS1 - // (LCDAC) device access and the - // start of another CS0 (LCDAC) - // device access unless the two - // accesses are both reads -#define LCD_LIDDCS1CFG_WRSU_S 27 -#define LCD_LIDDCS1CFG_WRDUR_S 21 -#define LCD_LIDDCS1CFG_WRHOLD_S 17 -#define LCD_LIDDCS1CFG_RDSU_S 12 -#define LCD_LIDDCS1CFG_RDDUR_S 6 -#define LCD_LIDDCS1CFG_RDHOLD_S 2 -#define LCD_LIDDCS1CFG_GAP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR -// register. -// -//***************************************************************************** -#define LCD_LIDDCS1ADDR_CS1ADDR_M \ - 0x0000FFFF // LCD Address Bus -#define LCD_LIDDCS1ADDR_CS1ADDR_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS1DATA -// register. -// -//***************************************************************************** -#define LCD_LIDDCS1DATA_CS0DATA_M \ - 0x0000FFFF // LCD Data Read/Write Initiation -#define LCD_LIDDCS1DATA_CS0DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRCTL register. -// -//***************************************************************************** -#define LCD_RASTRCTL_TFT24UPCK 0x04000000 // 24-bit TFT Mode Packing -#define LCD_RASTRCTL_TFT24 0x02000000 // 24-Bit TFT Mode -#define LCD_RASTRCTL_FRMBUFSZ 0x01000000 // Frame Buffer Select -#define LCD_RASTRCTL_TFTMAP 0x00800000 // TFT Mode Alternate Signal - // Mapping for Palettized - // Framebuffer -#define LCD_RASTRCTL_NIBMODE 0x00400000 // Nibble Mode -#define LCD_RASTRCTL_PALMODE_M 0x00300000 // Pallette Loading Mode -#define LCD_RASTRCTL_PALMODE_PALDAT \ - 0x00000000 // Palette and data loading, reset - // value -#define LCD_RASTRCTL_PALMODE_PAL \ - 0x00100000 // Palette loading only -#define LCD_RASTRCTL_PALMODE_DAT \ - 0x00200000 // Data loading only -#define LCD_RASTRCTL_REQDLY_M 0x000FF000 // Palette Loading Delay -#define LCD_RASTRCTL_MONO8B 0x00000200 // Mono 8-Bit -#define LCD_RASTRCTL_RDORDER 0x00000100 // Raster Data Order Select -#define LCD_RASTRCTL_LCDTFT 0x00000080 // LCD TFT -#define LCD_RASTRCTL_LCDBW 0x00000002 // LCD Monochrome -#define LCD_RASTRCTL_LCDEN 0x00000001 // LCD Controller Enable for Raster - // Operations -#define LCD_RASTRCTL_REQDLY_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRTIM0 -// register. -// -//***************************************************************************** -#define LCD_RASTRTIM0_HBP_M 0xFF000000 // Horizontal Back Porch Lowbits -#define LCD_RASTRTIM0_HFP_M 0x00FF0000 // Horizontal Front Porch Lowbits -#define LCD_RASTRTIM0_HSW_M 0x0000FC00 // Horizontal Sync Pulse Width - // Lowbits -#define LCD_RASTRTIM0_PPL_M 0x000003F0 // Pixels-per-line LSB[9:4] -#define LCD_RASTRTIM0_MSBPPL 0x00000008 // Pixels-per-line MSB[10] -#define LCD_RASTRTIM0_HBP_S 24 -#define LCD_RASTRTIM0_HFP_S 16 -#define LCD_RASTRTIM0_HSW_S 10 -#define LCD_RASTRTIM0_PPL_S 4 -#define LCD_RASTRTIM0_MSBPPL_S 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRTIM1 -// register. -// -//***************************************************************************** -#define LCD_RASTRTIM1_VBP_M 0xFF000000 // Vertical Back Porch -#define LCD_RASTRTIM1_VFP_M 0x00FF0000 // Vertical Front Porch -#define LCD_RASTRTIM1_VSW_M 0x0000FC00 // Vertical Sync Width Pulse -#define LCD_RASTRTIM1_LPP_M 0x000003FF // Lines Per Panel -#define LCD_RASTRTIM1_VBP_S 24 -#define LCD_RASTRTIM1_VFP_S 16 -#define LCD_RASTRTIM1_VSW_S 10 -#define LCD_RASTRTIM1_LPP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRTIM2 -// register. -// -//***************************************************************************** -#define LCD_RASTRTIM2_HSW_M 0x78000000 // Bits 9:6 of the horizontal sync - // width field -#define LCD_RASTRTIM2_MSBLPP 0x04000000 // MSB of Lines Per Panel -#define LCD_RASTRTIM2_PXLCLKCTL 0x02000000 // Hsync/Vsync Pixel Clock Control - // On/Off -#define LCD_RASTRTIM2_PSYNCRF 0x01000000 // Program HSYNC/VSYNC Rise or Fall -#define LCD_RASTRTIM2_INVOE 0x00800000 // Invert Output Enable -#define LCD_RASTRTIM2_INVPXLCLK 0x00400000 // Invert Pixel Clock -#define LCD_RASTRTIM2_IHS 0x00200000 // Invert Hysync -#define LCD_RASTRTIM2_IVS 0x00100000 // Invert Vsync -#define LCD_RASTRTIM2_ACBI_M 0x000F0000 // AC Bias Pins Transitions per - // Interrupt -#define LCD_RASTRTIM2_ACBF_M 0x0000FF00 // AC Bias Pin Frequency -#define LCD_RASTRTIM2_MSBHBP_M 0x00000030 // Bits 9:8 of the horizontal back - // porch field -#define LCD_RASTRTIM2_MSBHFP_M 0x00000003 // Bits 9:8 of the horizontal front - // porch field -#define LCD_RASTRTIM2_HSW_S 27 -#define LCD_RASTRTIM2_MSBLPP_S 26 -#define LCD_RASTRTIM2_ACBI_S 16 -#define LCD_RASTRTIM2_ACBF_S 8 -#define LCD_RASTRTIM2_MSBHBP_S 4 -#define LCD_RASTRTIM2_MSBHFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRSUBP1 -// register. -// -//***************************************************************************** -#define LCD_RASTRSUBP1_SPEN 0x80000000 // Sub Panel Enable -#define LCD_RASTRSUBP1_HOLS 0x20000000 // High or Low Signal -#define LCD_RASTRSUBP1_LPPT_M 0x03FF0000 // Line Per Panel Threshold -#define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF // Default Pixel Data LSB[15:0] -#define LCD_RASTRSUBP1_LPPT_S 16 -#define LCD_RASTRSUBP1_DPDLSB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRSUBP2 -// register. -// -//***************************************************************************** -#define LCD_RASTRSUBP2_LPPTMSB 0x00000100 // Lines Per Panel Threshold Bit 10 -#define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF // Default Pixel Data MSB [23:16] -#define LCD_RASTRSUBP2_DPDMSB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_DMACTL register. -// -//***************************************************************************** -#define LCD_DMACTL_FIFORDY_M 0x00000700 // DMA FIFO threshold -#define LCD_DMACTL_FIFORDY_8 0x00000000 // 8 words -#define LCD_DMACTL_FIFORDY_16 0x00000100 // 16 words -#define LCD_DMACTL_FIFORDY_32 0x00000200 // 32 words -#define LCD_DMACTL_FIFORDY_64 0x00000300 // 64 words -#define LCD_DMACTL_FIFORDY_128 0x00000400 // 128 words -#define LCD_DMACTL_FIFORDY_256 0x00000500 // 256 words -#define LCD_DMACTL_FIFORDY_512 0x00000600 // 512 words -#define LCD_DMACTL_BURSTSZ_M 0x00000070 // Burst Size setting for DMA - // transfers (all DMA transfers are - // 32 bits wide): -#define LCD_DMACTL_BURSTSZ_4 0x00000020 // burst size of 4 -#define LCD_DMACTL_BURSTSZ_8 0x00000030 // burst size of 8 -#define LCD_DMACTL_BURSTSZ_16 0x00000040 // burst size of 16 -#define LCD_DMACTL_BYTESWAP 0x00000008 // This bit controls the bytelane - // ordering of the data on the - // output of the DMA module -#define LCD_DMACTL_BIGDEND 0x00000002 // Big Endian Enable -#define LCD_DMACTL_FMODE 0x00000001 // Frame Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_DMABAFB0 register. -// -//***************************************************************************** -#define LCD_DMABAFB0_FB0BA_M 0xFFFFFFFC // Frame Buffer 0 Base Address - // pointer -#define LCD_DMABAFB0_FB0BA_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_DMACAFB0 register. -// -//***************************************************************************** -#define LCD_DMACAFB0_FB0CA_M 0xFFFFFFFC // Frame Buffer 0 Ceiling Address - // pointer -#define LCD_DMACAFB0_FB0CA_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_DMABAFB1 register. -// -//***************************************************************************** -#define LCD_DMABAFB1_FB1BA_M 0xFFFFFFFC // Frame Buffer 1 Base Address - // pointer -#define LCD_DMABAFB1_FB1BA_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_DMACAFB1 register. -// -//***************************************************************************** -#define LCD_DMACAFB1_FB1CA_M 0xFFFFFFFC // Frame Buffer 1 Ceiling Address - // pointer -#define LCD_DMACAFB1_FB1CA_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_SYSCFG register. -// -//***************************************************************************** -#define LCD_SYSCFG_STDBY_M 0x00000030 // Standby Mode -#define LCD_SYSCFG_STDBY_FORCE 0x00000000 // Force-standby mode: local - // initiator is unconditionally - // placed in standby state. Backup - // mode, for debug only -#define LCD_SYSCFG_STDBY_NONE 0x00000010 // No-standby mode: local initiator - // is unconditionally placed out of - // standby state. Backup mode, for - // debug only -#define LCD_SYSCFG_STDBY_SMART 0x00000020 // Smart-standby mode: local - // initiator standby status depends - // on local conditions, that is, - // the module's functional - // requirement from the initiator. - // IP module shall not generate - // (initiator-related) wakeup - // events -#define LCD_SYSCFG_IDLEMODE_M 0x0000000C // Idle Mode -#define LCD_SYSCFG_IDLEMODE_FORCE \ - 0x00000000 // Force-idle mode: local target's - // idle state follows - // (acknowledges) the system's idle - // requests unconditionally, that - // is, regardless of the IP - // module's internal requirements. - // Backup mode, for debug only -#define LCD_SYSCFG_IDLEMODE_NONE \ - 0x00000004 // No-idle mode: local target never - // enters idle state. Backup mode, - // for debug only -#define LCD_SYSCFG_IDLEMODE_SMART \ - 0x00000008 // Smart-idle mode: local target's - // idle state eventually follows - // (acknowledges) the system's idle - // requests, depending on the IP - // module's internal requirements. - // IP module shall not generate - // (IRQ- or DMA-requestrelated) - // wakeup events - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RISSET register. -// -//***************************************************************************** -#define LCD_RISSET_EOF1 0x00000200 // DMA End-of-Frame 1 Raw Interrupt - // Status and Set -#define LCD_RISSET_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt - // Status and Set -#define LCD_RISSET_PALLOAD 0x00000040 // DMA Palette Loaded Raw Interrupt - // Status and Set -#define LCD_RISSET_FIFOU 0x00000020 // DMA FIFO Underflow Raw Interrupt - // Status and Set -#define LCD_RISSET_ACBS 0x00000008 // AC Bias Count Raw Interrupt - // Status and Set -#define LCD_RISSET_SYNCS 0x00000004 // Frame Synchronization Lost Raw - // Interrupt Status and Set -#define LCD_RISSET_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt -#define LCD_RISSET_DONE 0x00000001 // Raster or LIDD Frame Done - // (shared, depends on whether - // Raster or LIDD mode enabled) Raw - // Interrupt Status and Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_MISCLR register. -// -//***************************************************************************** -#define LCD_MISCLR_EOF1 0x00000200 // DMA End-of-Frame 1 Enabled - // Interrupt and Clear -#define LCD_MISCLR_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt - // and Clear -#define LCD_MISCLR_PALLOAD 0x00000040 // DMA Palette Loaded Enabled - // Interrupt and Clear -#define LCD_MISCLR_FIFOU 0x00000020 // DMA FIFO Underflow Enabled - // Interrupt and Clear -#define LCD_MISCLR_ACBS 0x00000008 // AC Bias Count Enabled Interrupt - // and Clear -#define LCD_MISCLR_SYNCS 0x00000004 // Frame Synchronization Lost - // Enabled Interrupt and Clear -#define LCD_MISCLR_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt -#define LCD_MISCLR_DONE 0x00000001 // Raster or LIDD Frame Done - // (shared, depends on whether - // Raster or LIDD mode enabled) - // Enabled Interrupt and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_IM register. -// -//***************************************************************************** -#define LCD_IM_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt - // Enable Set -#define LCD_IM_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt - // Enable Set -#define LCD_IM_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt - // Enable Set -#define LCD_IM_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt - // Enable Set -#define LCD_IM_ACBS 0x00000008 // AC Bias Count Interrupt Enable - // Set -#define LCD_IM_SYNCS 0x00000004 // Frame Synchronization Lost - // Interrupt Enable Set -#define LCD_IM_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt - // Enable Set -#define LCD_IM_DONE 0x00000001 // Raster or LIDD Frame Done - // (shared, depends on whether - // Raster or LIDD mode enabled) - // Interrupt Enable Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_IENC register. -// -//***************************************************************************** -#define LCD_IENC_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt - // Enable Clear -#define LCD_IENC_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt - // Enable Clear -#define LCD_IENC_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt - // Enable Clear -#define LCD_IENC_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt - // Enable Clear -#define LCD_IENC_ACBS 0x00000008 // AC Bias Count Interrupt Enable - // Clear -#define LCD_IENC_SYNCS 0x00000004 // Frame Synchronization Lost - // Interrupt Enable Clear -#define LCD_IENC_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt - // Enable Clear -#define LCD_IENC_DONE 0x00000001 // Raster or LIDD Frame Done - // (shared, depends on whether - // Raster or LIDD mode enabled) - // Interrupt Enable Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_CLKEN register. -// -//***************************************************************************** -#define LCD_CLKEN_DMA 0x00000004 // DMA Clock Enable -#define LCD_CLKEN_LIDD 0x00000002 // LIDD Submodule Clock Enable -#define LCD_CLKEN_CORE 0x00000001 // LCD Core Clock Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_CLKRESET register. -// -//***************************************************************************** -#define LCD_CLKRESET_MAIN 0x00000008 // Software Reset for the entire - // LCD module -#define LCD_CLKRESET_DMA 0x00000004 // Software Reset for the DMA - // submodule -#define LCD_CLKRESET_LIDD 0x00000002 // Software Reset for the LIDD - // submodule (character displays) -#define LCD_CLKRESET_CORE 0x00000001 // Software Reset for the Core, - // which encompasses the Raster - // Active Matrix and Passive Matrix - // logic - -#endif // __HW_LCD_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_memmap.h b/bsp/tm4c129x-dk/libraries/inc/hw_memmap.h deleted file mode 100644 index 87033ab8230b4d779b6c69ee741a1eecb680caee..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_memmap.h +++ /dev/null @@ -1,151 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of the device. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following are defines for the base address of the memories and -// peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG0_BASE 0x40000000 // Watchdog0 -#define WATCHDOG1_BASE 0x40001000 // Watchdog1 -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI0_BASE 0x40008000 // SSI0 -#define SSI1_BASE 0x40009000 // SSI1 -#define SSI2_BASE 0x4000A000 // SSI2 -#define SSI3_BASE 0x4000B000 // SSI3 -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define UART2_BASE 0x4000E000 // UART2 -#define UART3_BASE 0x4000F000 // UART3 -#define UART4_BASE 0x40010000 // UART4 -#define UART5_BASE 0x40011000 // UART5 -#define UART6_BASE 0x40012000 // UART6 -#define UART7_BASE 0x40013000 // UART7 -#define I2C0_BASE 0x40020000 // I2C0 -#define I2C1_BASE 0x40021000 // I2C1 -#define I2C2_BASE 0x40022000 // I2C2 -#define I2C3_BASE 0x40023000 // I2C3 -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F -#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G -#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H -#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM) -#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM) -#define QEI0_BASE 0x4002C000 // QEI0 -#define QEI1_BASE 0x4002D000 // QEI1 -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define TIMER3_BASE 0x40033000 // Timer3 -#define TIMER4_BASE 0x40034000 // Timer4 -#define TIMER5_BASE 0x40035000 // Timer5 -#define WTIMER0_BASE 0x40036000 // Wide Timer0 -#define WTIMER1_BASE 0x40037000 // Wide Timer1 -#define ADC0_BASE 0x40038000 // ADC0 -#define ADC1_BASE 0x40039000 // ADC1 -#define COMP_BASE 0x4003C000 // Analog comparators -#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J -#define CAN0_BASE 0x40040000 // CAN0 -#define CAN1_BASE 0x40041000 // CAN1 -#define WTIMER2_BASE 0x4004C000 // Wide Timer2 -#define WTIMER3_BASE 0x4004D000 // Wide Timer3 -#define WTIMER4_BASE 0x4004E000 // Wide Timer4 -#define WTIMER5_BASE 0x4004F000 // Wide Timer5 -#define USB0_BASE 0x40050000 // USB 0 Controller -#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) -#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed) -#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed) -#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed) -#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed) -#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed) -#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) -#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) -#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed) -#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K -#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L -#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M -#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N -#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P -#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q -#define GPIO_PORTR_BASE 0x40067000 // General-Purpose Input/Outputs - // (GPIOs) -#define GPIO_PORTS_BASE 0x40068000 // General-Purpose Input/Outputs - // (GPIOs) -#define GPIO_PORTT_BASE 0x40069000 // General-Purpose Input/Outputs - // (GPIOs) -#define EEPROM_BASE 0x400AF000 // EEPROM memory -#define ONEWIRE0_BASE 0x400B6000 // 1-Wire Master Module -#define I2C8_BASE 0x400B8000 // I2C8 -#define I2C9_BASE 0x400B9000 // I2C9 -#define I2C4_BASE 0x400C0000 // I2C4 -#define I2C5_BASE 0x400C1000 // I2C5 -#define I2C6_BASE 0x400C2000 // I2C6 -#define I2C7_BASE 0x400C3000 // I2C7 -#define EPI0_BASE 0x400D0000 // EPI0 -#define TIMER6_BASE 0x400E0000 // General-Purpose Timers -#define TIMER7_BASE 0x400E1000 // General-Purpose Timers -#define EMAC0_BASE 0x400EC000 // Ethernet Controller -#define SYSEXC_BASE 0x400F9000 // System Exception Module -#define HIB_BASE 0x400FC000 // Hibernation Module -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define UDMA_BASE 0x400FF000 // uDMA Controller -#define CCM0_BASE 0x44030000 // Cyclical Redundancy Check (CRC) -#define SHAMD5_BASE 0x44034000 // SHA/MD5 Accelerator -#define AES_BASE 0x44036000 // Advance Encryption - // Hardware-Accelerated Module -#define DES_BASE 0x44038000 // Data Encryption Standard - // Accelerator (DES) -#define LCD0_BASE 0x44050000 // LCD Controller -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_nvic.h b/bsp/tm4c129x-dk/libraries/inc/hw_nvic.h deleted file mode 100644 index be8becf0fb877eb659a1b73b033bf6081c7e124c..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_nvic.h +++ /dev/null @@ -1,1414 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following are defines for the NVIC register addresses. -// -//***************************************************************************** -#define NVIC_ACTLR 0xE000E008 // Auxiliary Control -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status - // Register -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable -#define NVIC_EN1 0xE000E104 // Interrupt 32-63 Set Enable -#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable -#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable -#define NVIC_EN4 0xE000E110 // Interrupt 128-159 Set Enable -#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable -#define NVIC_DIS1 0xE000E184 // Interrupt 32-63 Clear Enable -#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable -#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable -#define NVIC_DIS4 0xE000E190 // Interrupt 128-159 Clear Enable -#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending -#define NVIC_PEND1 0xE000E204 // Interrupt 32-63 Set Pending -#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending -#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending -#define NVIC_PEND4 0xE000E210 // Interrupt 128-159 Set Pending -#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending -#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-63 Clear Pending -#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending -#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending -#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-159 Clear Pending -#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit -#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-63 Active Bit -#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit -#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit -#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-159 Active Bit -#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority -#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority -#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority -#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority -#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority -#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority -#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority -#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority -#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority -#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority -#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority -#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority -#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority -#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority -#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority -#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority -#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority -#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority -#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority -#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority -#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority -#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority -#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority -#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority -#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority -#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority -#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority -#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority -#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority -#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority -#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority -#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority -#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority -#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority -#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority -#define NVIC_CPUID 0xE000ED00 // CPU ID Base -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset -#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset - // Control -#define NVIC_SYS_CTRL 0xE000ED10 // System Control -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control -#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 -#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 -#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address -#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size -#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 -#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size - // Alias 1 -#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 -#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size - // Alias 2 -#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 -#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size - // Alias 3 -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt -#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control -#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address -#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTLR register. -// -//***************************************************************************** -#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating - // Point -#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple - // Cycle Instructions - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CURRENT -// register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN2 register. -// -//***************************************************************************** -#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN3 register. -// -//***************************************************************************** -#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN4 register. -// -//***************************************************************************** -#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS2 register. -// -//***************************************************************************** -#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS3 register. -// -//***************************************************************************** -#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS4 register. -// -//***************************************************************************** -#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND2 register. -// -//***************************************************************************** -#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND3 register. -// -//***************************************************************************** -#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND4 register. -// -//***************************************************************************** -#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND2 register. -// -//***************************************************************************** -#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND3 register. -// -//***************************************************************************** -#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND4 register. -// -//***************************************************************************** -#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE2 register. -// -//***************************************************************************** -#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE3 register. -// -//***************************************************************************** -#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE4 register. -// -//***************************************************************************** -#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI11 register. -// -//***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI12 register. -// -//***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI13 register. -// -//***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI14 register. -// -//***************************************************************************** -#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask -#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask -#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask -#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask -#define NVIC_PRI14_INTD_S 29 -#define NVIC_PRI14_INTC_S 21 -#define NVIC_PRI14_INTB_S 13 -#define NVIC_PRI14_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI15 register. -// -//***************************************************************************** -#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask -#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask -#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask -#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask -#define NVIC_PRI15_INTD_S 29 -#define NVIC_PRI15_INTC_S 21 -#define NVIC_PRI15_INTB_S 13 -#define NVIC_PRI15_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI16 register. -// -//***************************************************************************** -#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask -#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask -#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask -#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask -#define NVIC_PRI16_INTD_S 29 -#define NVIC_PRI16_INTC_S 21 -#define NVIC_PRI16_INTB_S 13 -#define NVIC_PRI16_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI17 register. -// -//***************************************************************************** -#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask -#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask -#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask -#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask -#define NVIC_PRI17_INTD_S 29 -#define NVIC_PRI17_INTC_S 21 -#define NVIC_PRI17_INTB_S 13 -#define NVIC_PRI17_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI18 register. -// -//***************************************************************************** -#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask -#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask -#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask -#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask -#define NVIC_PRI18_INTD_S 29 -#define NVIC_PRI18_INTC_S 21 -#define NVIC_PRI18_INTB_S 13 -#define NVIC_PRI18_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI19 register. -// -//***************************************************************************** -#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask -#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask -#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask -#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask -#define NVIC_PRI19_INTD_S 29 -#define NVIC_PRI19_INTC_S 21 -#define NVIC_PRI19_INTB_S 13 -#define NVIC_PRI19_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI20 register. -// -//***************************************************************************** -#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask -#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask -#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask -#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask -#define NVIC_PRI20_INTD_S 29 -#define NVIC_PRI20_INTC_S 21 -#define NVIC_PRI20_INTB_S 13 -#define NVIC_PRI20_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI21 register. -// -//***************************************************************************** -#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask -#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask -#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask -#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask -#define NVIC_PRI21_INTD_S 29 -#define NVIC_PRI21_INTC_S 21 -#define NVIC_PRI21_INTB_S 13 -#define NVIC_PRI21_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI22 register. -// -//***************************************************************************** -#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask -#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask -#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask -#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask -#define NVIC_PRI22_INTD_S 29 -#define NVIC_PRI22_INTC_S 21 -#define NVIC_PRI22_INTB_S 13 -#define NVIC_PRI22_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI23 register. -// -//***************************************************************************** -#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask -#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask -#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask -#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask -#define NVIC_PRI23_INTD_S 29 -#define NVIC_PRI23_INTC_S 21 -#define NVIC_PRI23_INTB_S 13 -#define NVIC_PRI23_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI24 register. -// -//***************************************************************************** -#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask -#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask -#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask -#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask -#define NVIC_PRI24_INTD_S 29 -#define NVIC_PRI24_INTC_S 21 -#define NVIC_PRI24_INTB_S 13 -#define NVIC_PRI24_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI25 register. -// -//***************************************************************************** -#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask -#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask -#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask -#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask -#define NVIC_PRI25_INTD_S 29 -#define NVIC_PRI25_INTC_S 21 -#define NVIC_PRI25_INTB_S 13 -#define NVIC_PRI25_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI26 register. -// -//***************************************************************************** -#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask -#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask -#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask -#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask -#define NVIC_PRI26_INTD_S 29 -#define NVIC_PRI26_INTC_S 21 -#define NVIC_PRI26_INTB_S 13 -#define NVIC_PRI26_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI27 register. -// -//***************************************************************************** -#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask -#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask -#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask -#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask -#define NVIC_PRI27_INTD_S 29 -#define NVIC_PRI27_INTC_S 21 -#define NVIC_PRI27_INTB_S 13 -#define NVIC_PRI27_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI28 register. -// -//***************************************************************************** -#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask -#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask -#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask -#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask -#define NVIC_PRI28_INTD_S 29 -#define NVIC_PRI28_INTC_S 21 -#define NVIC_PRI28_INTB_S 13 -#define NVIC_PRI28_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI29 register. -// -//***************************************************************************** -#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask -#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask -#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask -#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask -#define NVIC_PRI29_INTD_S 29 -#define NVIC_PRI29_INTC_S 21 -#define NVIC_PRI29_INTB_S 13 -#define NVIC_PRI29_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI30 register. -// -//***************************************************************************** -#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask -#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask -#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask -#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask -#define NVIC_PRI30_INTD_S 29 -#define NVIC_PRI30_INTC_S 21 -#define NVIC_PRI30_INTB_S 13 -#define NVIC_PRI30_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI31 register. -// -//***************************************************************************** -#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask -#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask -#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask -#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask -#define NVIC_PRI31_INTD_S 29 -#define NVIC_PRI31_INTC_S 21 -#define NVIC_PRI31_INTB_S 13 -#define NVIC_PRI31_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI32 register. -// -//***************************************************************************** -#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask -#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask -#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask -#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask -#define NVIC_PRI32_INTD_S 29 -#define NVIC_PRI32_INTC_S 21 -#define NVIC_PRI32_INTB_S 13 -#define NVIC_PRI32_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI33 register. -// -//***************************************************************************** -#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt - // [4n+3] -#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt - // [4n+2] -#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt - // [4n+1] -#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt - // [4n] -#define NVIC_PRI33_INTD_S 29 -#define NVIC_PRI33_INTC_S 21 -#define NVIC_PRI33_INTB_S 13 -#define NVIC_PRI33_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI34 register. -// -//***************************************************************************** -#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt - // [4n+3] -#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt - // [4n+2] -#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt - // [4n+1] -#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt - // [4n] -#define NVIC_PRI34_INTD_S 29 -#define NVIC_PRI34_INTC_S 21 -#define NVIC_PRI34_INTB_S 13 -#define NVIC_PRI34_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI -#define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault -#define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault -#define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault -#define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault -#define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall -#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV -#define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset -#define NVIC_VTABLE_OFFSET_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception - // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and - // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL -// register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending -#define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage - // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy - // State Preservation -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address - // Register Valid -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on - // Floating-Point Lazy State - // Preservation -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_HFAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DEBUG_STAT -// register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_ADDR -// register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPAC register. -// -//***************************************************************************** -#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access - // Privilege -#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied -#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only -#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access -#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access - // Privilege -#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied -#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only -#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_NUMBER -// register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE_ADDR_S 5 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access -#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none -#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only -#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw -#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none -#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro -#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable -#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable -#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable -#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable -#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable -#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable -#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable -#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable -#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable -#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable -#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable -#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes -#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes -#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes -#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes -#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes -#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes -#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes -#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes -#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes -#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes -#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes -#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes -#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes -#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes -#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes -#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes -#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes -#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes -#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes -#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes -#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes -#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes -#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes -#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes -#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes -#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes -#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes -#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes -#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE1_ADDR_S 5 -#define NVIC_MPU_BASE1_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR1_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR1_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR1_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE2_ADDR_S 5 -#define NVIC_MPU_BASE2_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR2_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR2_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR2_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE3_ADDR_S 5 -#define NVIC_MPU_BASE3_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR3_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR3_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR3_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read -#define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction - // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available -#define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID -#define NVIC_SW_TRIG_INTID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPCC register. -// -//***************************************************************************** -#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation - // Enable -#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable -#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready -#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready -#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready -#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready -#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode -#define NVIC_FPCC_USER 0x00000002 // User Privilege Level -#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPCA register. -// -//***************************************************************************** -#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address -#define NVIC_FPCA_ADDRESS_S 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPDSC register. -// -//***************************************************************************** -#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default -#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default -#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default -#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default -#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode -#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) - // mode -#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity - // (RM) mode -#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode - -#endif // __HW_NVIC_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_onewire.h b/bsp/tm4c129x-dk/libraries/inc/hw_onewire.h deleted file mode 100644 index bf810b7ce93a0fc4c6e005c7ce724ccaf428ad1f..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_onewire.h +++ /dev/null @@ -1,223 +0,0 @@ -//***************************************************************************** -// -// hw_onewire.h - Macros used when accessing the One wire hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_ONEWIRE_H__ -#define __HW_ONEWIRE_H__ - -//***************************************************************************** -// -// The following are defines for the One wire register offsets. -// -//***************************************************************************** -#define ONEWIRE_O_CS 0x00000000 // 1-Wire Control and Status -#define ONEWIRE_O_TIM 0x00000004 // 1-Wire Timing Override -#define ONEWIRE_O_DATW 0x00000008 // 1-Wire Data Write -#define ONEWIRE_O_DATR 0x0000000C // 1-Wire Data Read -#define ONEWIRE_O_IM 0x00000100 // 1-Wire Interrupt Mask -#define ONEWIRE_O_RIS 0x00000104 // 1-Wire Raw Interrupt Status -#define ONEWIRE_O_MIS 0x00000108 // 1-Wire Masked Interrupt Status -#define ONEWIRE_O_ICR 0x0000010C // 1-Wire Interrupt Clear -#define ONEWIRE_O_DMA 0x00000120 // 1-Wire uDMA Control -#define ONEWIRE_O_PP 0x00000FC0 // 1-Wire Peripheral Properties - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_CS register. -// -//***************************************************************************** -#define ONEWIRE_CS_USEALT 0x80000000 // Two Wire Enable -#define ONEWIRE_CS_ALTP 0x40000000 // Alternate Polarity Enable -#define ONEWIRE_CS_BSIZE_M 0x00070000 // Last Byte Size -#define ONEWIRE_CS_BSIZE_8 0x00000000 // 8 bits (1 byte) -#define ONEWIRE_CS_BSIZE_1 0x00010000 // 1 bit -#define ONEWIRE_CS_BSIZE_2 0x00020000 // 2 bits -#define ONEWIRE_CS_BSIZE_3 0x00030000 // 3 bits -#define ONEWIRE_CS_BSIZE_4 0x00040000 // 4 bits -#define ONEWIRE_CS_BSIZE_5 0x00050000 // 5 bits -#define ONEWIRE_CS_BSIZE_6 0x00060000 // 6 bits -#define ONEWIRE_CS_BSIZE_7 0x00070000 // 7 bits -#define ONEWIRE_CS_STUCK 0x00000400 // STUCK Status -#define ONEWIRE_CS_NOATR 0x00000200 // Answer-to-Reset Status -#define ONEWIRE_CS_BUSY 0x00000100 // Busy Status -#define ONEWIRE_CS_SKATR 0x00000080 // Skip Answer-to-Reset Enable -#define ONEWIRE_CS_LSAM 0x00000040 // Late Sample Enable -#define ONEWIRE_CS_ODRV 0x00000020 // Overdrive Enable -#define ONEWIRE_CS_SZ_M 0x00000018 // Data Operation Size -#define ONEWIRE_CS_OP_M 0x00000006 // Operation Request -#define ONEWIRE_CS_OP_NONE 0x00000000 // No operation -#define ONEWIRE_CS_OP_RD 0x00000002 // Read -#define ONEWIRE_CS_OP_WR 0x00000004 // Write -#define ONEWIRE_CS_OP_WRRD 0x00000006 // Write/Read -#define ONEWIRE_CS_RST 0x00000001 // Reset Request -#define ONEWIRE_CS_SZ_S 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_TIM register. -// -//***************************************************************************** -#define ONEWIRE_TIM_W1TIM_M 0xF0000000 // Value '1' Timing -#define ONEWIRE_TIM_W0TIM_M 0x0F800000 // Value '0' Timing -#define ONEWIRE_TIM_W0REST_M 0x00780000 // Rest Time -#define ONEWIRE_TIM_W1SAM_M 0x00078000 // Sample Time -#define ONEWIRE_TIM_ATRSAM_M 0x00007800 // Answer-to-Reset Sample -#define ONEWIRE_TIM_ATRTIM_M 0x000007C0 // Answer-to-Reset/Rest Period -#define ONEWIRE_TIM_RSTTIM_M 0x0000003F // Reset Low Time -#define ONEWIRE_TIM_W1TIM_S 28 -#define ONEWIRE_TIM_W0TIM_S 23 -#define ONEWIRE_TIM_W0REST_S 19 -#define ONEWIRE_TIM_W1SAM_S 15 -#define ONEWIRE_TIM_ATRSAM_S 11 -#define ONEWIRE_TIM_ATRTIM_S 6 -#define ONEWIRE_TIM_RSTTIM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_DATW register. -// -//***************************************************************************** -#define ONEWIRE_DATW_B3_M 0xFF000000 // Upper Data Byte -#define ONEWIRE_DATW_B2_M 0x00FF0000 // Upper Middle Data Byte -#define ONEWIRE_DATW_B1_M 0x0000FF00 // Lower Middle Data Byte -#define ONEWIRE_DATW_B0_M 0x000000FF // Lowest Data Byte -#define ONEWIRE_DATW_B3_S 24 -#define ONEWIRE_DATW_B2_S 16 -#define ONEWIRE_DATW_B1_S 8 -#define ONEWIRE_DATW_B0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_DATR register. -// -//***************************************************************************** -#define ONEWIRE_DATR_B3_M 0xFF000000 // Upper Data Byte -#define ONEWIRE_DATR_B2_M 0x00FF0000 // Upper Middle Data Byte -#define ONEWIRE_DATR_B1_M 0x0000FF00 // Lower Middle Data Byte -#define ONEWIRE_DATR_B0_M 0x000000FF // Lowest Data Byte -#define ONEWIRE_DATR_B3_S 24 -#define ONEWIRE_DATR_B2_S 16 -#define ONEWIRE_DATR_B1_S 8 -#define ONEWIRE_DATR_B0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_IM register. -// -//***************************************************************************** -#define ONEWIRE_IM_DMA 0x00000010 // DMA Done Interrupt Mask -#define ONEWIRE_IM_STUCK 0x00000008 // Stuck Status Interrupt Mask -#define ONEWIRE_IM_NOATR 0x00000004 // No Answer-to-Reset Interrupt - // Mask -#define ONEWIRE_IM_OPC 0x00000002 // Operation Complete Interrupt - // Mask -#define ONEWIRE_IM_RST 0x00000001 // Reset Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_RIS register. -// -//***************************************************************************** -#define ONEWIRE_RIS_DMA 0x00000010 // DMA Done Raw Interrupt Status -#define ONEWIRE_RIS_STUCK 0x00000008 // Stuck Status Raw Interrupt - // Status -#define ONEWIRE_RIS_NOATR 0x00000004 // No Answer-to-Reset Raw Interrupt - // Status -#define ONEWIRE_RIS_OPC 0x00000002 // Operation Complete Raw Interrupt - // Status -#define ONEWIRE_RIS_RST 0x00000001 // Reset Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_MIS register. -// -//***************************************************************************** -#define ONEWIRE_MIS_DMA 0x00000010 // DMA Done Masked Interrupt Status -#define ONEWIRE_MIS_STUCK 0x00000008 // Stuck Status Masked Interrupt - // Status -#define ONEWIRE_MIS_NOATR 0x00000004 // No Answer-to-Reset Masked - // Interrupt Status -#define ONEWIRE_MIS_OPC 0x00000002 // Operation Complete Masked - // Interrupt Status -#define ONEWIRE_MIS_RST 0x00000001 // Reset Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_ICR register. -// -//***************************************************************************** -#define ONEWIRE_ICR_DMA 0x00000010 // DMA Done Interrupt Clear -#define ONEWIRE_ICR_STUCK 0x00000008 // Stuck Status Interrupt Clear -#define ONEWIRE_ICR_NOATR 0x00000004 // No Answer-to-Reset Interrupt - // Clear -#define ONEWIRE_ICR_OPC 0x00000002 // Operation Complete Interrupt - // Clear -#define ONEWIRE_ICR_RST 0x00000001 // Reset Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_DMA register. -// -//***************************************************************************** -#define ONEWIRE_DMA_SG 0x00000008 // Scatter-Gather Enable -#define ONEWIRE_DMA_DMAOP_M 0x00000006 // uDMA Operation -#define ONEWIRE_DMA_DMAOP_DIS 0x00000000 // uDMA disabled -#define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002 // uDMA single read: 1-Wire - // requests uDMA to read - // ONEWIREDATR register after each - // read transaction -#define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004 // uDMA multiple write: 1-Wire - // requests uDMA to load whenever - // the ONEWIREDATW register is - // empty -#define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006 // uDMA multiple read: An initial - // read occurs and subsequent reads - // start after uDMA has read the - // ONEWIREDATR register -#define ONEWIRE_DMA_RST 0x00000001 // uDMA Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_PP register. -// -//***************************************************************************** -#define ONEWIRE_PP_DMAP 0x00000010 // uDMA Present -#define ONEWIRE_PP_CNT_M 0x00000003 // 1-Wire Bus Count -#define ONEWIRE_PP_CNT_S 0 - -#endif // __HW_ONEWIRE_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_pwm.h b/bsp/tm4c129x-dk/libraries/inc/hw_pwm.h deleted file mode 100644 index 2167aad93abe84c3bc765d2a8392275167a93bcd..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_pwm.h +++ /dev/null @@ -1,1885 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// The following are defines for the PWM register offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion -#define PWM_O_FAULT 0x00000010 // PWM Output Fault -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable -#define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear -#define PWM_O_STATUS 0x00000020 // PWM Status -#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value -#define PWM_O_ENUPD 0x00000028 // PWM Enable Update -#define PWM_O_0_CTL 0x00000040 // PWM0 Control -#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger - // Enable -#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status -#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear -#define PWM_O_0_LOAD 0x00000050 // PWM0 Load -#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter -#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A -#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B -#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control -#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control -#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control -#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay -#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band - // Falling-Edge-Delay -#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0 -#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1 -#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period -#define PWM_O_1_CTL 0x00000080 // PWM1 Control -#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger - // Enable -#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status -#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear -#define PWM_O_1_LOAD 0x00000090 // PWM1 Load -#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter -#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A -#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B -#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control -#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control -#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control -#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay -#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band - // Falling-Edge-Delay -#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0 -#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1 -#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period -#define PWM_O_2_CTL 0x000000C0 // PWM2 Control -#define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger - // Enable -#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status -#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear -#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load -#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter -#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A -#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B -#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control -#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control -#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control -#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay -#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band - // Falling-Edge-Delay -#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0 -#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1 -#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period -#define PWM_O_3_CTL 0x00000100 // PWM3 Control -#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger - // Enable -#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status -#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear -#define PWM_O_3_LOAD 0x00000110 // PWM3 Load -#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter -#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A -#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B -#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control -#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control -#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control -#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay -#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band - // Falling-Edge-Delay -#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0 -#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1 -#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period -#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense -#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0 -#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1 -#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense -#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0 -#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1 -#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense -#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0 -#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1 -#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense -#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0 -#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1 -#define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties -#define PWM_O_CC 0x00000FC8 // PWM Clock Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_CTL register. -// -//***************************************************************************** -#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 -#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 -#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 -#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_SYNC register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter -#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ENABLE register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM7EN 0x00000080 // MnPWM7 Output Enable -#define PWM_ENABLE_PWM6EN 0x00000040 // MnPWM6 Output Enable -#define PWM_ENABLE_PWM5EN 0x00000020 // MnPWM5 Output Enable -#define PWM_ENABLE_PWM4EN 0x00000010 // MnPWM4 Output Enable -#define PWM_ENABLE_PWM3EN 0x00000008 // MnPWM3 Output Enable -#define PWM_ENABLE_PWM2EN 0x00000004 // MnPWM2 Output Enable -#define PWM_ENABLE_PWM1EN 0x00000002 // MnPWM1 Output Enable -#define PWM_ENABLE_PWM0EN 0x00000001 // MnPWM0 Output Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INVERT register. -// -//***************************************************************************** -#define PWM_INVERT_PWM7INV 0x00000080 // Invert MnPWM7 Signal -#define PWM_INVERT_PWM6INV 0x00000040 // Invert MnPWM6 Signal -#define PWM_INVERT_PWM5INV 0x00000020 // Invert MnPWM5 Signal -#define PWM_INVERT_PWM4INV 0x00000010 // Invert MnPWM4 Signal -#define PWM_INVERT_PWM3INV 0x00000008 // Invert MnPWM3 Signal -#define PWM_INVERT_PWM2INV 0x00000004 // Invert MnPWM2 Signal -#define PWM_INVERT_PWM1INV 0x00000002 // Invert MnPWM1 Signal -#define PWM_INVERT_PWM0INV 0x00000001 // Invert MnPWM0 Signal - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_FAULT register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT7 0x00000080 // MnPWM7 Fault -#define PWM_FAULT_FAULT6 0x00000040 // MnPWM6 Fault -#define PWM_FAULT_FAULT5 0x00000020 // MnPWM5 Fault -#define PWM_FAULT_FAULT4 0x00000010 // MnPWM4 Fault -#define PWM_FAULT_FAULT3 0x00000008 // MnPWM3 Fault -#define PWM_FAULT_FAULT2 0x00000004 // MnPWM2 Fault -#define PWM_FAULT_FAULT1 0x00000002 // MnPWM1 Fault -#define PWM_FAULT_FAULT0 0x00000001 // MnPWM0 Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INTEN register. -// -//***************************************************************************** -#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3 -#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2 -#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 -#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 -#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable -#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable -#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable -#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_RIS register. -// -//***************************************************************************** -#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3 -#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2 -#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 -#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 -#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted -#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted -#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted -#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ISC register. -// -//***************************************************************************** -#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted -#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted -#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted -#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted -#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status -#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status -#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status -#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_STATUS register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status -#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status -#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status -#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_FAULTVAL register. -// -//***************************************************************************** -#define PWM_FAULTVAL_PWM7 0x00000080 // MnPWM7 Fault Value -#define PWM_FAULTVAL_PWM6 0x00000040 // MnPWM6 Fault Value -#define PWM_FAULTVAL_PWM5 0x00000020 // MnPWM5 Fault Value -#define PWM_FAULTVAL_PWM4 0x00000010 // MnPWM4 Fault Value -#define PWM_FAULTVAL_PWM3 0x00000008 // MnPWM3 Fault Value -#define PWM_FAULTVAL_PWM2 0x00000004 // MnPWM2 Fault Value -#define PWM_FAULTVAL_PWM1 0x00000002 // MnPWM1 Fault Value -#define PWM_FAULTVAL_PWM0 0x00000001 // MnPWM0 Fault Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ENUPD register. -// -//***************************************************************************** -#define PWM_ENUPD_ENUPD7_M 0x0000C000 // MnPWM7 Enable Update Mode -#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized -#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized -#define PWM_ENUPD_ENUPD6_M 0x00003000 // MnPWM6 Enable Update Mode -#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized -#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized -#define PWM_ENUPD_ENUPD5_M 0x00000C00 // MnPWM5 Enable Update Mode -#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized -#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized -#define PWM_ENUPD_ENUPD4_M 0x00000300 // MnPWM4 Enable Update Mode -#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized -#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized -#define PWM_ENUPD_ENUPD3_M 0x000000C0 // MnPWM3 Enable Update Mode -#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized -#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized -#define PWM_ENUPD_ENUPD2_M 0x00000030 // MnPWM2 Enable Update Mode -#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized -#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized -#define PWM_ENUPD_ENUPD1_M 0x0000000C // MnPWM1 Enable Update Mode -#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized -#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized -#define PWM_ENUPD_ENUPD0_M 0x00000003 // MnPWM0 Enable Update Mode -#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized -#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CTL register. -// -//***************************************************************************** -#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_0_CTL_MODE 0x00000002 // Counter Mode -#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_INTEN register. -// -//***************************************************************************** -#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_RIS register. -// -//***************************************************************************** -#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_ISC register. -// -//***************************************************************************** -#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_LOAD register. -// -//***************************************************************************** -#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_0_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_COUNT register. -// -//***************************************************************************** -#define PWM_0_COUNT_M 0x0000FFFF // Counter Value -#define PWM_0_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CMPA register. -// -//***************************************************************************** -#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value -#define PWM_0_CMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CMPB register. -// -//***************************************************************************** -#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value -#define PWM_0_CMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_GENA register. -// -//***************************************************************************** -#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_0_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_0_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_0_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_0_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_0_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_0_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_0_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_0_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_GENB register. -// -//***************************************************************************** -#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_0_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_0_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_0_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_0_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_0_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_0_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_0_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_0_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBCTL register. -// -//***************************************************************************** -#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBRISE register. -// -//***************************************************************************** -#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay -#define PWM_0_DBRISE_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBFALL register. -// -//***************************************************************************** -#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay -#define PWM_0_DBFALL_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period -#define PWM_0_MINFLTPER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CTL register. -// -//***************************************************************************** -#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_1_CTL_MODE 0x00000002 // Counter Mode -#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_INTEN register. -// -//***************************************************************************** -#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_RIS register. -// -//***************************************************************************** -#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_ISC register. -// -//***************************************************************************** -#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_LOAD register. -// -//***************************************************************************** -#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_1_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_COUNT register. -// -//***************************************************************************** -#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_1_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CMPA register. -// -//***************************************************************************** -#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_1_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CMPB register. -// -//***************************************************************************** -#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_1_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_GENA register. -// -//***************************************************************************** -#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_1_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_1_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_1_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_1_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_1_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_1_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_1_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_1_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_GENB register. -// -//***************************************************************************** -#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_1_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_1_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_1_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_1_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_1_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_1_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_1_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_1_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBCTL register. -// -//***************************************************************************** -#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBRISE register. -// -//***************************************************************************** -#define PWM_1_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_1_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBFALL register. -// -//***************************************************************************** -#define PWM_1_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_1_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_1_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CTL register. -// -//***************************************************************************** -#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_2_CTL_MODE 0x00000002 // Counter Mode -#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_INTEN register. -// -//***************************************************************************** -#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_RIS register. -// -//***************************************************************************** -#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_ISC register. -// -//***************************************************************************** -#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_LOAD register. -// -//***************************************************************************** -#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_2_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_COUNT register. -// -//***************************************************************************** -#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_2_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CMPA register. -// -//***************************************************************************** -#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_2_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CMPB register. -// -//***************************************************************************** -#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_2_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_GENA register. -// -//***************************************************************************** -#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_2_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_2_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_2_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_2_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_2_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_2_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_2_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_2_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_GENB register. -// -//***************************************************************************** -#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_2_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_2_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_2_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_2_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_2_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_2_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_2_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_2_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBCTL register. -// -//***************************************************************************** -#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBRISE register. -// -//***************************************************************************** -#define PWM_2_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_2_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBFALL register. -// -//***************************************************************************** -#define PWM_2_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_2_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_2_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CTL register. -// -//***************************************************************************** -#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_3_CTL_MODE 0x00000002 // Counter Mode -#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_INTEN register. -// -//***************************************************************************** -#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_RIS register. -// -//***************************************************************************** -#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_ISC register. -// -//***************************************************************************** -#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_LOAD register. -// -//***************************************************************************** -#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_3_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_COUNT register. -// -//***************************************************************************** -#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_3_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CMPA register. -// -//***************************************************************************** -#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_3_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CMPB register. -// -//***************************************************************************** -#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_3_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_GENA register. -// -//***************************************************************************** -#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_3_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_3_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_3_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_3_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_3_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_3_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_3_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_3_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_GENB register. -// -//***************************************************************************** -#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_3_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_3_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_3_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_3_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_3_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_3_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_3_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_3_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBCTL register. -// -//***************************************************************************** -#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBRISE register. -// -//***************************************************************************** -#define PWM_3_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_3_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBFALL register. -// -//***************************************************************************** -#define PWM_3_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_3_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_3_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSEN register. -// -//***************************************************************************** -#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSEN register. -// -//***************************************************************************** -#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSEN register. -// -//***************************************************************************** -#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSEN register. -// -//***************************************************************************** -#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_PP register. -// -//***************************************************************************** -#define PWM_PP_GCNT_M 0x0000000F // Generators -#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs (per PWM unit) -#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization -#define PWM_PP_EFAULT 0x00000200 // Extended Fault -#define PWM_PP_ONE 0x00000400 // One-Shot Mode -#define PWM_PP_GCNT_S 0 -#define PWM_PP_FCNT_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_CC register. -// -//***************************************************************************** -#define PWM_CC_USEPWM 0x00000100 // Use PWM Clock Divisor -#define PWM_CC_PWMDIV_M 0x00000007 // PWM Clock Divider -#define PWM_CC_PWMDIV_2 0x00000000 // /2 -#define PWM_CC_PWMDIV_4 0x00000001 // /4 -#define PWM_CC_PWMDIV_8 0x00000002 // /8 -#define PWM_CC_PWMDIV_16 0x00000003 // /16 -#define PWM_CC_PWMDIV_32 0x00000004 // /32 -#define PWM_CC_PWMDIV_64 0x00000005 // /64 - -//***************************************************************************** -// -// The following are defines for the PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg -#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition -#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition -#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base -#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CTL register. -// -//***************************************************************************** -#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_X_CTL_MODE 0x00000002 // Counter Mode -#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_INTEN register. -// -//***************************************************************************** -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_RIS register. -// -//***************************************************************************** -#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_ISC register. -// -//***************************************************************************** -#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_LOAD register. -// -//***************************************************************************** -#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_X_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_COUNT register. -// -//***************************************************************************** -#define PWM_X_COUNT_M 0x0000FFFF // Counter Value -#define PWM_X_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CMPA register. -// -//***************************************************************************** -#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value -#define PWM_X_CMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CMPB register. -// -//***************************************************************************** -#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value -#define PWM_X_CMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_GENA register. -// -//***************************************************************************** -#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_X_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_X_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_X_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_X_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_X_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_X_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_X_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_X_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_GENB register. -// -//***************************************************************************** -#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_X_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_X_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_X_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_X_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_X_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_X_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_X_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_X_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBCTL register. -// -//***************************************************************************** -#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBRISE register. -// -//***************************************************************************** -#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay -#define PWM_X_DBRISE_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBFALL register. -// -//***************************************************************************** -#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay -#define PWM_X_DBFALL_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period -#define PWM_X_MINFLTPER_S 0 - -//***************************************************************************** -// -// The following are defines for the PWM Generator extended offsets. -// -//***************************************************************************** -#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense -#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status -#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status -#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base -#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base -#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base -#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSEN register. -// -//***************************************************************************** -#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -#endif // __HW_PWM_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_qei.h b/bsp/tm4c129x-dk/libraries/inc/hw_qei.h deleted file mode 100644 index a86f5259bddbdeb2a9915b15d01c5041f87fc900..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_qei.h +++ /dev/null @@ -1,178 +0,0 @@ -//***************************************************************************** -// -// hw_qei.h - Macros used when accessing the QEI hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_QEI_H__ -#define __HW_QEI_H__ - -//***************************************************************************** -// -// The following are defines for the QEI register offsets. -// -//***************************************************************************** -#define QEI_O_CTL 0x00000000 // QEI Control -#define QEI_O_STAT 0x00000004 // QEI Status -#define QEI_O_POS 0x00000008 // QEI Position -#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position -#define QEI_O_LOAD 0x00000010 // QEI Timer Load -#define QEI_O_TIME 0x00000014 // QEI Timer -#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter -#define QEI_O_SPEED 0x0000001C // QEI Velocity -#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable -#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status -#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_CTL register. -// -//***************************************************************************** -#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count -#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter -#define QEI_CTL_STALLEN 0x00001000 // Stall QEI -#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse -#define QEI_CTL_INVB 0x00000400 // Invert PhB -#define QEI_CTL_INVA 0x00000200 // Invert PhA -#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity -#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 -#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 -#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 -#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 -#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 -#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 -#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 -#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 -#define QEI_CTL_VELEN 0x00000020 // Capture Velocity -#define QEI_CTL_RESMODE 0x00000010 // Reset Mode -#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode -#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode -#define QEI_CTL_SWAP 0x00000002 // Swap Signals -#define QEI_CTL_ENABLE 0x00000001 // Enable QEI -#define QEI_CTL_FILTCNT_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation -#define QEI_STAT_ERROR 0x00000001 // Error Detected - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator - // Value -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator - // Value -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Velocity -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable -#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt - // Enable -#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable -#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected -#define QEI_RIS_DIR 0x00000004 // Direction Change Detected -#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired -#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_ISC register. -// -//***************************************************************************** -#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt -#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt -#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt -#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt - -#endif // __HW_QEI_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_shamd5.h b/bsp/tm4c129x-dk/libraries/inc/hw_shamd5.h deleted file mode 100644 index d34c76092cf6aeef80dedb29f5930e3744a20460..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_shamd5.h +++ /dev/null @@ -1,548 +0,0 @@ -//***************************************************************************** -// -// hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_SHAMD5_H__ -#define __HW_SHAMD5_H__ - -//***************************************************************************** -// -// The following are defines for the SHA/MD5 register offsets. -// -//***************************************************************************** -#define SHAMD5_O_ODIGEST_A 0x00000000 // SHA Outer Digest A -#define SHAMD5_O_ODIGEST_B 0x00000004 // SHA Outer Digest B -#define SHAMD5_O_ODIGEST_C 0x00000008 // SHA Outer Digest C -#define SHAMD5_O_ODIGEST_D 0x0000000C // SHA Outer Digest D -#define SHAMD5_O_ODIGEST_E 0x00000010 // SHA Outer Digest E -#define SHAMD5_O_ODIGEST_F 0x00000014 // SHA Outer Digest F -#define SHAMD5_O_ODIGEST_G 0x00000018 // SHA Outer Digest G -#define SHAMD5_O_ODIGEST_H 0x0000001C // SHA Outer Digest H -#define SHAMD5_O_IDIGEST_A 0x00000020 // SHA Inner Digest A -#define SHAMD5_O_IDIGEST_B 0x00000024 // SHA Inner Digest B -#define SHAMD5_O_IDIGEST_C 0x00000028 // SHA Inner Digest C -#define SHAMD5_O_IDIGEST_D 0x0000002C // SHA Inner Digest D -#define SHAMD5_O_IDIGEST_E 0x00000030 // SHA Inner Digest E -#define SHAMD5_O_IDIGEST_F 0x00000034 // SHA Inner Digest F -#define SHAMD5_O_IDIGEST_G 0x00000038 // SHA Inner Digest G -#define SHAMD5_O_IDIGEST_H 0x0000003C // SHA Inner Digest H -#define SHAMD5_O_DIGEST_COUNT 0x00000040 // SHA Digest Count -#define SHAMD5_O_MODE 0x00000044 // SHA Mode -#define SHAMD5_O_LENGTH 0x00000048 // SHA Length -#define SHAMD5_O_DATA_0_IN 0x00000080 // SHA Data 0 Input -#define SHAMD5_O_DATA_1_IN 0x00000084 // SHA Data 1 Input -#define SHAMD5_O_DATA_2_IN 0x00000088 // SHA Data 2 Input -#define SHAMD5_O_DATA_3_IN 0x0000008C // SHA Data 3 Input -#define SHAMD5_O_DATA_4_IN 0x00000090 // SHA Data 4 Input -#define SHAMD5_O_DATA_5_IN 0x00000094 // SHA Data 5 Input -#define SHAMD5_O_DATA_6_IN 0x00000098 // SHA Data 6 Input -#define SHAMD5_O_DATA_7_IN 0x0000009C // SHA Data 7 Input -#define SHAMD5_O_DATA_8_IN 0x000000A0 // SHA Data 8 Input -#define SHAMD5_O_DATA_9_IN 0x000000A4 // SHA Data 9 Input -#define SHAMD5_O_DATA_10_IN 0x000000A8 // SHA Data 10 Input -#define SHAMD5_O_DATA_11_IN 0x000000AC // SHA Data 11 Input -#define SHAMD5_O_DATA_12_IN 0x000000B0 // SHA Data 12 Input -#define SHAMD5_O_DATA_13_IN 0x000000B4 // SHA Data 13 Input -#define SHAMD5_O_DATA_14_IN 0x000000B8 // SHA Data 14 Input -#define SHAMD5_O_DATA_15_IN 0x000000BC // SHA Data 15 Input -#define SHAMD5_O_REVISION 0x00000100 // SHA Revision -#define SHAMD5_O_SYSCONFIG 0x00000110 // SHA System Configuration -#define SHAMD5_O_SYSSTATUS 0x00000114 // SHA System Status -#define SHAMD5_O_IRQSTATUS 0x00000118 // SHA Interrupt Status -#define SHAMD5_O_IRQENABLE 0x0000011C // SHA Interrupt Enable -#define SHAMD5_O_DMAIM 0xFFFFC010 // SHA DMA Interrupt Mask -#define SHAMD5_O_DMARIS 0xFFFFC014 // SHA DMA Raw Interrupt Status -#define SHAMD5_O_DMAMIS 0xFFFFC018 // SHA DMA Masked Interrupt Status -#define SHAMD5_O_DMAIC 0xFFFFC01C // SHA DMA Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_A_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_B_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_C_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_D_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_E_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_F_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_G_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_H_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_A_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_B_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_C_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_D_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_E_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_F_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_G_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_H_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT -// register. -// -//***************************************************************************** -#define SHAMD5_DIGEST_COUNT_M 0xFFFFFFFF // Digest Count -#define SHAMD5_DIGEST_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_MODE register. -// -//***************************************************************************** -#define SHAMD5_MODE_HMAC_OUTER_HASH \ - 0x00000080 // HMAC Outer Hash Processing - // Enable -#define SHAMD5_MODE_HMAC_KEY_PROC \ - 0x00000020 // HMAC Key Processing Enable -#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding, the - // Hash/HMAC will be 'closed' at - // the end of the block, as per - // MD5/SHA-1/SHA-2 specification -#define SHAMD5_MODE_ALGO_CONSTANT \ - 0x00000008 // The initial digest register will - // be overwritten with the - // algorithm constants for the - // selected algorithm when hashing - // and the initial digest count - // register will be reset to 0 -#define SHAMD5_MODE_ALGO_M 0x00000007 // Hash Algorithm -#define SHAMD5_MODE_ALGO_MD5 0x00000000 // MD5 -#define SHAMD5_MODE_ALGO_SHA1 0x00000002 // SHA-1 -#define SHAMD5_MODE_ALGO_SHA224 0x00000004 // SHA-224 -#define SHAMD5_MODE_ALGO_SHA256 0x00000006 // SHA-256 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_LENGTH -// register. -// -//***************************************************************************** -#define SHAMD5_LENGTH_M 0xFFFFFFFF // Block Length/Remaining Byte - // Count -#define SHAMD5_LENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_0_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_1_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_2_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_3_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_4_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_5_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_6_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_7_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_8_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_9_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_10_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_10_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_11_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_11_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_12_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_12_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_13_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_13_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_14_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_14_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_15_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_15_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_REVISION -// register. -// -//***************************************************************************** -#define SHAMD5_REVISION_M 0xFFFFFFFF // Revision Number -#define SHAMD5_REVISION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG -// register. -// -//***************************************************************************** -#define SHAMD5_SYSCONFIG_SADVANCED \ - 0x00000080 // Advanced Mode Enable -#define SHAMD5_SYSCONFIG_SIDLE_M \ - 0x00000030 // Sidle mode -#define SHAMD5_SYSCONFIG_SIDLE_FORCE \ - 0x00000000 // Force-idle mode -#define SHAMD5_SYSCONFIG_DMA_EN 0x00000008 // uDMA Request Enable -#define SHAMD5_SYSCONFIG_IT_EN 0x00000004 // Interrupt Enable -#define SHAMD5_SYSCONFIG_SOFTRESET \ - 0x00000002 // Soft reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS -// register. -// -//***************************************************************************** -#define SHAMD5_SYSSTATUS_RESETDONE \ - 0x00000001 // Reset done status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS -// register. -// -//***************************************************************************** -#define SHAMD5_IRQSTATUS_CONTEXT_READY \ - 0x00000008 // Context Ready Status -#define SHAMD5_IRQSTATUS_INPUT_READY \ - 0x00000002 // Input Ready Status -#define SHAMD5_IRQSTATUS_OUTPUT_READY \ - 0x00000001 // Output Ready Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE -// register. -// -//***************************************************************************** -#define SHAMD5_IRQENABLE_CONTEXT_READY \ - 0x00000008 // Mask for context ready interrupt -#define SHAMD5_IRQENABLE_INPUT_READY \ - 0x00000002 // Mask for input ready interrupt -#define SHAMD5_IRQENABLE_OUTPUT_READY \ - 0x00000001 // Mask for output ready interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DMAIM register. -// -//***************************************************************************** -#define SHAMD5_DMAIM_COUT 0x00000004 // Context Out DMA Done Interrupt - // Mask -#define SHAMD5_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask -#define SHAMD5_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DMARIS -// register. -// -//***************************************************************************** -#define SHAMD5_DMARIS_COUT 0x00000004 // Context Out DMA Done Raw - // Interrupt Status -#define SHAMD5_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt - // Status -#define SHAMD5_DMARIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DMAMIS -// register. -// -//***************************************************************************** -#define SHAMD5_DMAMIS_COUT 0x00000004 // Context Out DMA Done Masked - // Interrupt Status -#define SHAMD5_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked - // Interrupt Status -#define SHAMD5_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DMAIC register. -// -//***************************************************************************** -#define SHAMD5_DMAIC_COUT 0x00000004 // Context Out DMA Done Masked - // Interrupt Status -#define SHAMD5_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear -#define SHAMD5_DMAIC_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -#endif // __HW_SHAMD5_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_ssi.h b/bsp/tm4c129x-dk/libraries/inc/hw_ssi.h deleted file mode 100644 index 36a92cf1e4a16bbcaade40a87a8729839946b8ff..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_ssi.h +++ /dev/null @@ -1,237 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following are defines for the SSI register offsets. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // SSI Control 0 -#define SSI_O_CR1 0x00000004 // SSI Control 1 -#define SSI_O_DR 0x00000008 // SSI Data -#define SSI_O_SR 0x0000000C // SSI Status -#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale -#define SSI_O_IM 0x00000014 // SSI Interrupt Mask -#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status -#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status -#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear -#define SSI_O_DMACTL 0x00000024 // SSI DMA Control -#define SSI_O_PP 0x00000FC0 // SSI Peripheral Properties -#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR0 register. -// -//***************************************************************************** -#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate -#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase -#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity -#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select -#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format -#define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format -#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format -#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select -#define SSI_CR0_DSS_4 0x00000003 // 4-bit data -#define SSI_CR0_DSS_5 0x00000004 // 5-bit data -#define SSI_CR0_DSS_6 0x00000005 // 6-bit data -#define SSI_CR0_DSS_7 0x00000006 // 7-bit data -#define SSI_CR0_DSS_8 0x00000007 // 8-bit data -#define SSI_CR0_DSS_9 0x00000008 // 9-bit data -#define SSI_CR0_DSS_10 0x00000009 // 10-bit data -#define SSI_CR0_DSS_11 0x0000000A // 11-bit data -#define SSI_CR0_DSS_12 0x0000000B // 12-bit data -#define SSI_CR0_DSS_13 0x0000000C // 13-bit data -#define SSI_CR0_DSS_14 0x0000000D // 14-bit data -#define SSI_CR0_DSS_15 0x0000000E // 15-bit data -#define SSI_CR0_DSS_16 0x0000000F // 16-bit data -#define SSI_CR0_SCR_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR1 register. -// -//***************************************************************************** -#define SSI_CR1_EOM 0x00000800 // Stop Frame (End of Message) -#define SSI_CR1_FSSHLDFRM 0x00000400 // FSS Hold Frame -#define SSI_CR1_HSCLKEN 0x00000200 // High Speed Clock Enable -#define SSI_CR1_DIR 0x00000100 // SSI Direction of Operation -#define SSI_CR1_MODE_M 0x000000C0 // SSI Mode -#define SSI_CR1_MODE_LEGACY 0x00000000 // Legacy SSI mode -#define SSI_CR1_MODE_BI 0x00000040 // Bi-SSI mode -#define SSI_CR1_MODE_QUAD 0x00000080 // Quad-SSI Mode -#define SSI_CR1_MODE_ADVANCED 0x000000C0 // Advanced SSI Mode with 8-bit - // packet size -#define SSI_CR1_EOT 0x00000010 // End of Transmission -#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select -#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port - // Enable -#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_DR register. -// -//***************************************************************************** -#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data -#define SSI_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_SR register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI Busy Bit -#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full -#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty -#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full -#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CPSR register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor -#define SSI_CPSR_CPSDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_IM register. -// -//***************************************************************************** -#define SSI_IM_EOTIM 0x00000040 // End of Transmit Interrupt Mask -#define SSI_IM_DMATXIM 0x00000020 // SSI Transmit DMA Interrupt Mask -#define SSI_IM_DMARXIM 0x00000010 // SSI Receive DMA Interrupt Mask -#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask -#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask -#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt - // Mask -#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_RIS register. -// -//***************************************************************************** -#define SSI_RIS_EOTRIS 0x00000040 // End of Transmit Raw Interrupt - // Status -#define SSI_RIS_DMATXRIS 0x00000020 // SSI Transmit DMA Raw Interrupt - // Status -#define SSI_RIS_DMARXRIS 0x00000010 // SSI Receive DMA Raw Interrupt - // Status -#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt - // Status -#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt - // Status -#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw - // Interrupt Status -#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_MIS register. -// -//***************************************************************************** -#define SSI_MIS_EOTMIS 0x00000040 // End of Transmit Masked Interrupt - // Status -#define SSI_MIS_DMATXMIS 0x00000020 // SSI Transmit DMA Masked - // Interrupt Status -#define SSI_MIS_DMARXMIS 0x00000010 // SSI Receive DMA Masked Interrupt - // Status -#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked - // Interrupt Status -#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked - // Interrupt Status -#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked - // Interrupt Status -#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_ICR register. -// -//***************************************************************************** -#define SSI_ICR_EOTIC 0x00000040 // End of Transmit Interrupt Clear -#define SSI_ICR_DMATXIC 0x00000020 // SSI Transmit DMA Interrupt Clear -#define SSI_ICR_DMARXIC 0x00000010 // SSI Receive DMA Interrupt Clear -#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt - // Clear -#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_DMACTL register. -// -//***************************************************************************** -#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_PP register. -// -//***************************************************************************** -#define SSI_PP_FSSHLDFRM 0x00000008 // FSS Hold Frame Capability -#define SSI_PP_MODE_M 0x00000006 // Mode of Operation -#define SSI_PP_MODE_LEGACY 0x00000000 // Legacy SSI mode -#define SSI_PP_MODE_ADVBI 0x00000002 // Legacy mode, Advanced SSI mode - // and Bi-SSI mode enabled -#define SSI_PP_MODE_ADVBIQUAD 0x00000004 // Legacy mode, Advanced mode, - // Bi-SSI and Quad-SSI mode enabled -#define SSI_PP_HSCLK 0x00000001 // High Speed Capability - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CC register. -// -//***************************************************************************** -#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source -#define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock - // source and divisor factor) -#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC - -#endif // __HW_SSI_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_sysctl.h b/bsp/tm4c129x-dk/libraries/inc/hw_sysctl.h deleted file mode 100644 index cab5049da58c3d6a1b34f7d959f4f665ef695255..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_sysctl.h +++ /dev/null @@ -1,3749 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following are defines for the System Control register addresses. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400FE000 // Device Identification 0 -#define SYSCTL_DID1 0x400FE004 // Device Identification 1 -#define SYSCTL_DC0 0x400FE008 // Device Capabilities 0 -#define SYSCTL_DC1 0x400FE010 // Device Capabilities 1 -#define SYSCTL_DC2 0x400FE014 // Device Capabilities 2 -#define SYSCTL_DC3 0x400FE018 // Device Capabilities 3 -#define SYSCTL_DC4 0x400FE01C // Device Capabilities 4 -#define SYSCTL_DC5 0x400FE020 // Device Capabilities 5 -#define SYSCTL_DC6 0x400FE024 // Device Capabilities 6 -#define SYSCTL_DC7 0x400FE028 // Device Capabilities 7 -#define SYSCTL_DC8 0x400FE02C // Device Capabilities 8 -#define SYSCTL_PBORCTL 0x400FE030 // Brown-Out Reset Control -#define SYSCTL_PTBOCTL 0x400FE038 // Power-Temp Brown Out Control -#define SYSCTL_SRCR0 0x400FE040 // Software Reset Control 0 -#define SYSCTL_SRCR1 0x400FE044 // Software Reset Control 1 -#define SYSCTL_SRCR2 0x400FE048 // Software Reset Control 2 -#define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status -#define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control -#define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and - // Clear -#define SYSCTL_RESC 0x400FE05C // Reset Cause -#define SYSCTL_PWRTC 0x400FE060 // Power-Temperature Cause -#define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration -#define SYSCTL_NMIC 0x400FE064 // NMI Cause Register -#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus - // Control -#define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2 -#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control -#define SYSCTL_RSCLKCFG 0x400FE0B0 // Run and Sleep Mode Configuration - // Register -#define SYSCTL_MEMTIM0 0x400FE0C0 // Memory Timing Parameter Register - // 0 for Main Flash and EEPROM -#define SYSCTL_RCGC0 0x400FE100 // Run Mode Clock Gating Control - // Register 0 -#define SYSCTL_RCGC1 0x400FE104 // Run Mode Clock Gating Control - // Register 1 -#define SYSCTL_RCGC2 0x400FE108 // Run Mode Clock Gating Control - // Register 2 -#define SYSCTL_SCGC0 0x400FE110 // Sleep Mode Clock Gating Control - // Register 0 -#define SYSCTL_SCGC1 0x400FE114 // Sleep Mode Clock Gating Control - // Register 1 -#define SYSCTL_SCGC2 0x400FE118 // Sleep Mode Clock Gating Control - // Register 2 -#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep Mode Clock Gating - // Control Register 0 -#define SYSCTL_DCGC1 0x400FE124 // Deep-Sleep Mode Clock Gating - // Control Register 1 -#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating - // Control Register 2 -#define SYSCTL_ALTCLKCFG 0x400FE138 // Alternate Clock Configuration -#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration -#define SYSCTL_DSCLKCFG 0x400FE144 // Deep Sleep Clock Configuration - // Register -#define SYSCTL_DIVSCLK 0x400FE148 // Divisor and Source Clock - // Configuration -#define SYSCTL_SYSPROP 0x400FE14C // System Properties -#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator - // Calibration -#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator - // Statistics -#define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0 -#define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1 -#define SYSCTL_PLLSTAT 0x400FE168 // PLL Status -#define SYSCTL_SLPPWRCFG 0x400FE188 // Sleep Power Configuration -#define SYSCTL_DSLPPWRCFG 0x400FE18C // Deep-Sleep Power Configuration -#define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 -#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information -#define SYSCTL_LDOSPCTL 0x400FE1B4 // LDO Sleep Power Control -#define SYSCTL_LDODPCTL 0x400FE1BC // LDO Deep-Sleep Power Control -#define SYSCTL_RESBEHAVCTL 0x400FE1D8 // Reset Behavior Control Register -#define SYSCTL_HSSR 0x400FE1F4 // Hardware System Service Request -#define SYSCTL_USBPDS 0x400FE280 // USB Power Domain Status -#define SYSCTL_USBMPC 0x400FE284 // USB Memory Power Control -#define SYSCTL_EMACPDS 0x400FE288 // Ethernet MAC Power Domain Status -#define SYSCTL_EMACMPC 0x400FE28C // Ethernet MAC Memory Power - // Control -#define SYSCTL_LCDMPC 0x400FE294 // LCD Memory Power Control -#define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral - // Present -#define SYSCTL_PPTIMER 0x400FE304 // 16/32-Bit General-Purpose Timer - // Peripheral Present -#define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output - // Peripheral Present -#define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access - // Peripheral Present -#define SYSCTL_PPEPI 0x400FE310 // EPI Peripheral Present -#define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present -#define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous - // Receiver/Transmitter Peripheral - // Present -#define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface - // Peripheral Present -#define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit - // Peripheral Present -#define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral - // Present -#define SYSCTL_PPEPHY 0x400FE330 // Ethernet PHY Peripheral Present -#define SYSCTL_PPCAN 0x400FE334 // Controller Area Network - // Peripheral Present -#define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter - // Peripheral Present -#define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral - // Present -#define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral - // Present -#define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface - // Peripheral Present -#define SYSCTL_PPLPC 0x400FE348 // Low Pin Count Interface - // Peripheral Present -#define SYSCTL_PPPECI 0x400FE350 // Platform Environment Control - // Interface Peripheral Present -#define SYSCTL_PPFAN 0x400FE354 // Fan Control Peripheral Present -#define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present -#define SYSCTL_PPWTIMER 0x400FE35C // 32/64-Bit Wide General-Purpose - // Timer Peripheral Present -#define SYSCTL_PPRTS 0x400FE370 // Remote Temperature Sensor - // Peripheral Present -#define SYSCTL_PPCCM 0x400FE374 // CRC and Cryptographic Modules - // Peripheral Present -#define SYSCTL_PPLCD 0x400FE390 // LCD Peripheral Present -#define SYSCTL_PPOWIRE 0x400FE398 // 1-Wire Peripheral Present -#define SYSCTL_PPEMAC 0x400FE39C // Ethernet MAC Peripheral Present -#define SYSCTL_PPHIM 0x400FE3A4 // Human Interface Master - // Peripheral Present -#define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset -#define SYSCTL_SRTIMER 0x400FE504 // 16/32-Bit General-Purpose Timer - // Software Reset -#define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output - // Software Reset -#define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access - // Software Reset -#define SYSCTL_SREPI 0x400FE510 // EPI Software Reset -#define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset -#define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous - // Receiver/Transmitter Software - // Reset -#define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface - // Software Reset -#define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit - // Software Reset -#define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software - // Reset -#define SYSCTL_SREPHY 0x400FE530 // Ethernet PHY Software Reset -#define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software - // Reset -#define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter - // Software Reset -#define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset -#define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software - // Reset -#define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface - // Software Reset -#define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset -#define SYSCTL_SRWTIMER 0x400FE55C // 32/64-Bit Wide General-Purpose - // Timer Software Reset -#define SYSCTL_SRCCM 0x400FE574 // CRC and Cryptographic Modules - // Software Reset -#define SYSCTL_SRLCD 0x400FE590 // LCD Controller Software Reset -#define SYSCTL_SROWIRE 0x400FE598 // 1-Wire Software Reset -#define SYSCTL_SREMAC 0x400FE59C // Ethernet MAC Software Reset -#define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock - // Gating Control -#define SYSCTL_RCGCTIMER 0x400FE604 // 16/32-Bit General-Purpose Timer - // Run Mode Clock Gating Control -#define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run - // Mode Clock Gating Control -#define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run - // Mode Clock Gating Control -#define SYSCTL_RCGCEPI 0x400FE610 // EPI Run Mode Clock Gating - // Control -#define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous - // Receiver/Transmitter Run Mode - // Clock Gating Control -#define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run - // Mode Clock Gating Control -#define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run - // Mode Clock Gating Control -#define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode - // Clock Gating Control -#define SYSCTL_RCGCEPHY 0x400FE630 // Ethernet PHY Run Mode Clock - // Gating Control -#define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode - // Clock Gating Control -#define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run - // Mode Clock Gating Control -#define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock - // Gating Control -#define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode - // Clock Gating Control -#define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run - // Mode Clock Gating Control -#define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER 0x400FE65C // 32/64-Bit Wide General-Purpose - // Timer Run Mode Clock Gating - // Control -#define SYSCTL_RCGCCCM 0x400FE674 // CRC and Cryptographic Modules - // Run Mode Clock Gating Control -#define SYSCTL_RCGCLCD 0x400FE690 // LCD Controller Run Mode Clock - // Gating Control -#define SYSCTL_RCGCOWIRE 0x400FE698 // 1-Wire Run Mode Clock Gating - // Control -#define SYSCTL_RCGCEMAC 0x400FE69C // Ethernet MAC Run Mode Clock - // Gating Control -#define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCTIMER 0x400FE704 // 16/32-Bit General-Purpose Timer - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep - // Mode Clock Gating Control -#define SYSCTL_SCGCEPI 0x400FE710 // EPI Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous - // Receiver/Transmitter Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep - // Mode Clock Gating Control -#define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCEPHY 0x400FE730 // Ethernet PHY Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep - // Mode Clock Gating Control -#define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER 0x400FE75C // 32/64-Bit Wide General-Purpose - // Timer Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCCCM 0x400FE774 // CRC and Cryptographic Modules - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCLCD 0x400FE790 // LCD Controller Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCOWIRE 0x400FE798 // 1-Wire Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCEMAC 0x400FE79C // Ethernet MAC Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCTIMER 0x400FE804 // 16/32-Bit General-Purpose Timer - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCEPI 0x400FE810 // EPI Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous - // Receiver/Transmitter Deep-Sleep - // Mode Clock Gating Control -#define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep - // Mode Clock Gating Control -#define SYSCTL_DCGCEPHY 0x400FE830 // Ethernet PHY Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep - // Mode Clock Gating Control -#define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep - // Mode Clock Gating Control -#define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER 0x400FE85C // 32/64-Bit Wide General-Purpose - // Timer Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCCCM 0x400FE874 // CRC and Cryptographic Modules - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCLCD 0x400FE890 // LCD Controller Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCOWIRE 0x400FE898 // 1-Wire Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCEMAC 0x400FE89C // Ethernet MAC Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control -#define SYSCTL_PCTIMER 0x400FE904 // 16/32-Bit General-Purpose Timer - // Power Control -#define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output - // Power Control -#define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power - // Control -#define SYSCTL_PCEPI 0x400FE910 // External Peripheral Interface - // Power Control -#define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control -#define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous - // Receiver/Transmitter Power - // Control -#define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface - // Power Control -#define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power - // Control -#define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power - // Control -#define SYSCTL_PCEPHY 0x400FE930 // Ethernet PHY Power Control -#define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power - // Control -#define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter - // Power Control -#define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control -#define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power - // Control -#define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface - // Power Control -#define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control -#define SYSCTL_PCCCM 0x400FE974 // CRC and Cryptographic Modules - // Power Control -#define SYSCTL_PCLCD 0x400FE990 // LCD Controller Power Control -#define SYSCTL_PCOWIRE 0x400FE998 // 1-Wire Power Control -#define SYSCTL_PCEMAC 0x400FE99C // Ethernet MAC Power Control -#define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready -#define SYSCTL_PRTIMER 0x400FEA04 // 16/32-Bit General-Purpose Timer - // Peripheral Ready -#define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output - // Peripheral Ready -#define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access - // Peripheral Ready -#define SYSCTL_PREPI 0x400FEA10 // EPI Peripheral Ready -#define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready -#define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous - // Receiver/Transmitter Peripheral - // Ready -#define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface - // Peripheral Ready -#define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit - // Peripheral Ready -#define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral - // Ready -#define SYSCTL_PREPHY 0x400FEA30 // Ethernet PHY Peripheral Ready -#define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network - // Peripheral Ready -#define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter - // Peripheral Ready -#define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral - // Ready -#define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral - // Ready -#define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface - // Peripheral Ready -#define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready -#define SYSCTL_PRWTIMER 0x400FEA5C // 32/64-Bit Wide General-Purpose - // Timer Peripheral Ready -#define SYSCTL_PRCCM 0x400FEA74 // CRC and Cryptographic Modules - // Peripheral Ready -#define SYSCTL_PRLCD 0x400FEA90 // LCD Controller Peripheral Ready -#define SYSCTL_PROWIRE 0x400FEA98 // 1-Wire Peripheral Ready -#define SYSCTL_PREMAC 0x400FEA9C // Ethernet MAC Peripheral Ready -#define SYSCTL_UNIQUEID0 0x400FEF20 // Unique ID 0 -#define SYSCTL_UNIQUEID1 0x400FEF24 // Unique ID 1 -#define SYSCTL_UNIQUEID2 0x400FEF28 // Unique ID 2 -#define SYSCTL_UNIQUEID3 0x400FEF2C // Unique ID 3 -#define SYSCTL_CCMCGREQ 0x44030204 // Cryptographic Modules Clock - // Gating Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version -#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 - // register format. -#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_TM4C123 \ - 0x00050000 // Tiva TM4C123x and TM4E123x - // microcontrollers -#define SYSCTL_DID0_CLASS_TM4C129 \ - 0x000A0000 // Tiva(TM) TM4C129-class - // microcontrollers -#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision -#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) -#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer - // revision) -#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer - // revision) -#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision -#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major - // revision update -#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change -#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version -#define SYSCTL_DID1_VER_1 0x10000000 // fury_ib -#define SYSCTL_DID1_FAM_M 0x0F000000 // Family -#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers -#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number -#define SYSCTL_DID1_PRTNO_TM4C1230C3PM \ - 0x00220000 // TM4C1230C3PM -#define SYSCTL_DID1_PRTNO_TM4C1230D5PM \ - 0x00230000 // TM4C1230D5PM -#define SYSCTL_DID1_PRTNO_TM4C1230E6PM \ - 0x00200000 // TM4C1230E6PM -#define SYSCTL_DID1_PRTNO_TM4C1230H6PM \ - 0x00210000 // TM4C1230H6PM -#define SYSCTL_DID1_PRTNO_TM4C1231C3PM \ - 0x00180000 // TM4C1231C3PM -#define SYSCTL_DID1_PRTNO_TM4C1231D5PM \ - 0x00190000 // TM4C1231D5PM -#define SYSCTL_DID1_PRTNO_TM4C1231D5PZ \ - 0x00360000 // TM4C1231D5PZ -#define SYSCTL_DID1_PRTNO_TM4C1231E6PM \ - 0x00100000 // TM4C1231E6PM -#define SYSCTL_DID1_PRTNO_TM4C1231E6PZ \ - 0x00300000 // TM4C1231E6PZ -#define SYSCTL_DID1_PRTNO_TM4C1231H6PGE \ - 0x00350000 // TM4C1231H6PGE -#define SYSCTL_DID1_PRTNO_TM4C1231H6PM \ - 0x00110000 // TM4C1231H6PM -#define SYSCTL_DID1_PRTNO_TM4C1231H6PZ \ - 0x00310000 // TM4C1231H6PZ -#define SYSCTL_DID1_PRTNO_TM4C1232C3PM \ - 0x00080000 // TM4C1232C3PM -#define SYSCTL_DID1_PRTNO_TM4C1232D5PM \ - 0x00090000 // TM4C1232D5PM -#define SYSCTL_DID1_PRTNO_TM4C1232E6PM \ - 0x000A0000 // TM4C1232E6PM -#define SYSCTL_DID1_PRTNO_TM4C1232H6PM \ - 0x000B0000 // TM4C1232H6PM -#define SYSCTL_DID1_PRTNO_TM4C1233C3PM \ - 0x00010000 // TM4C1233C3PM -#define SYSCTL_DID1_PRTNO_TM4C1233D5PM \ - 0x00020000 // TM4C1233D5PM -#define SYSCTL_DID1_PRTNO_TM4C1233D5PZ \ - 0x00D00000 // TM4C1233D5PZ -#define SYSCTL_DID1_PRTNO_TM4C1233E6PM \ - 0x00030000 // TM4C1233E6PM -#define SYSCTL_DID1_PRTNO_TM4C1233E6PZ \ - 0x00D10000 // TM4C1233E6PZ -#define SYSCTL_DID1_PRTNO_TM4C1233H6PGE \ - 0x00D60000 // TM4C1233H6PGE -#define SYSCTL_DID1_PRTNO_TM4C1233H6PM \ - 0x00040000 // TM4C1233H6PM -#define SYSCTL_DID1_PRTNO_TM4C1233H6PZ \ - 0x00D20000 // TM4C1233H6PZ -#define SYSCTL_DID1_PRTNO_TM4C1236D5PM \ - 0x00520000 // TM4C1236D5PM -#define SYSCTL_DID1_PRTNO_TM4C1236E6PM \ - 0x00500000 // TM4C1236E6PM -#define SYSCTL_DID1_PRTNO_TM4C1236H6PM \ - 0x00510000 // TM4C1236H6PM -#define SYSCTL_DID1_PRTNO_TM4C1237D5PM \ - 0x00480000 // TM4C1237D5PM -#define SYSCTL_DID1_PRTNO_TM4C1237D5PZ \ - 0x00660000 // TM4C1237D5PZ -#define SYSCTL_DID1_PRTNO_TM4C1237E6PM \ - 0x00400000 // TM4C1237E6PM -#define SYSCTL_DID1_PRTNO_TM4C1237E6PZ \ - 0x00600000 // TM4C1237E6PZ -#define SYSCTL_DID1_PRTNO_TM4C1237H6PGE \ - 0x00650000 // TM4C1237H6PGE -#define SYSCTL_DID1_PRTNO_TM4C1237H6PM \ - 0x00410000 // TM4C1237H6PM -#define SYSCTL_DID1_PRTNO_TM4C1237H6PZ \ - 0x00610000 // TM4C1237H6PZ -#define SYSCTL_DID1_PRTNO_TM4C123AE6PM \ - 0x00800000 // TM4C123AE6PM -#define SYSCTL_DID1_PRTNO_TM4C123AH6PM \ - 0x00830000 // TM4C123AH6PM -#define SYSCTL_DID1_PRTNO_TM4C123BE6PM \ - 0x00700000 // TM4C123BE6PM -#define SYSCTL_DID1_PRTNO_TM4C123BE6PZ \ - 0x00C30000 // TM4C123BE6PZ -#define SYSCTL_DID1_PRTNO_TM4C123BH6PGE \ - 0x00C60000 // TM4C123BH6PGE -#define SYSCTL_DID1_PRTNO_TM4C123BH6PM \ - 0x00730000 // TM4C123BH6PM -#define SYSCTL_DID1_PRTNO_TM4C123BH6PZ \ - 0x00C40000 // TM4C123BH6PZ -#define SYSCTL_DID1_PRTNO_TM4C123BH6ZRB \ - 0x00E90000 // TM4C123BH6ZRB -#define SYSCTL_DID1_PRTNO_TM4C123FE6PM \ - 0x00B00000 // TM4C123FE6PM -#define SYSCTL_DID1_PRTNO_TM4C123FH6PM \ - 0x00B10000 // TM4C123FH6PM -#define SYSCTL_DID1_PRTNO_TM4C123GE6PM \ - 0x00A00000 // TM4C123GE6PM -#define SYSCTL_DID1_PRTNO_TM4C123GE6PZ \ - 0x00C00000 // TM4C123GE6PZ -#define SYSCTL_DID1_PRTNO_TM4C123GH6PGE \ - 0x00C50000 // TM4C123GH6PGE -#define SYSCTL_DID1_PRTNO_TM4C123GH6PM \ - 0x00A10000 // TM4C123GH6PM -#define SYSCTL_DID1_PRTNO_TM4C123GH6PZ \ - 0x00C10000 // TM4C123GH6PZ -#define SYSCTL_DID1_PRTNO_TM4C123GH6ZRB \ - 0x00E30000 // TM4C123GH6ZRB -#define SYSCTL_DID1_PRTNO_TM4C1290NCPDT \ - 0x00190000 // TM4C1290NCPDT -#define SYSCTL_DID1_PRTNO_TM4C1290NCZAD \ - 0x001B0000 // TM4C1290NCZAD -#define SYSCTL_DID1_PRTNO_TM4C1292NCPDT \ - 0x001C0000 // TM4C1292NCPDT -#define SYSCTL_DID1_PRTNO_TM4C1292NCZAD \ - 0x001E0000 // TM4C1292NCZAD -#define SYSCTL_DID1_PRTNO_TM4C1294KCPDT \ - 0x00340000 // TM4C1294KCPDT -#define SYSCTL_DID1_PRTNO_TM4C1294NCPDT \ - 0x001F0000 // TM4C1294NCPDT -#define SYSCTL_DID1_PRTNO_TM4C1294NCZAD \ - 0x00210000 // TM4C1294NCZAD -#define SYSCTL_DID1_PRTNO_TM4C1297NCZAD \ - 0x00220000 // TM4C1297NCZAD -#define SYSCTL_DID1_PRTNO_TM4C1299KCZAD \ - 0x00360000 // TM4C1299KCZAD -#define SYSCTL_DID1_PRTNO_TM4C1299NCZAD \ - 0x00230000 // TM4C1299NCZAD -#define SYSCTL_DID1_PRTNO_TM4C129CNCPDT \ - 0x00240000 // TM4C129CNCPDT -#define SYSCTL_DID1_PRTNO_TM4C129CNCZAD \ - 0x00260000 // TM4C129CNCZAD -#define SYSCTL_DID1_PRTNO_TM4C129DNCPDT \ - 0x00270000 // TM4C129DNCPDT -#define SYSCTL_DID1_PRTNO_TM4C129DNCZAD \ - 0x00290000 // TM4C129DNCZAD -#define SYSCTL_DID1_PRTNO_TM4C129EKCPDT \ - 0x00350000 // TM4C129EKCPDT -#define SYSCTL_DID1_PRTNO_TM4C129ENCPDT \ - 0x002D0000 // TM4C129ENCPDT -#define SYSCTL_DID1_PRTNO_TM4C129ENCZAD \ - 0x002F0000 // TM4C129ENCZAD -#define SYSCTL_DID1_PRTNO_TM4C129LNCZAD \ - 0x00300000 // TM4C129LNCZAD -#define SYSCTL_DID1_PRTNO_TM4C129XKCZAD \ - 0x00370000 // TM4C129XKCZAD -#define SYSCTL_DID1_PRTNO_TM4C129XNCZAD \ - 0x00320000 // TM4C129XNCZAD -#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin LQFP package -#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin LQFP package -#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin LQFP package -#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin BGA package -#define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package -#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range -#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range -#define SYSCTL_DID1_TEMP_IE 0x00000060 // Available in both industrial - // temperature range (-40C to 85C) - // and extended temperature range - // (-40C to 105C) devices. See -#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type -#define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package -#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package -#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance -#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM -#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash -#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash -#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash -#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash -#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present -#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present -#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present -#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present -#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present -#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present -#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present -#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider -#define SYSCTL_DC1_MINSYSDIV_80 0x00002000 // Specifies an 80-MHz CPU clock - // with a PLL divider of 2.5 -#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock - // with a PLL divider of 4 -#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock - // with a PLL divider of 5 -#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a - // PLL divider of 8 -#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a - // PLL divider of 10 -#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed -#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second -#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second -#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second -#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second -#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed -#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second -#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second -#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second -#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second -#define SYSCTL_DC1_MPU 0x00000080 // MPU Present -#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present -#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present -#define SYSCTL_DC1_PLL 0x00000010 // PLL Present -#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present -#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present -#define SYSCTL_DC1_SWD 0x00000002 // SWD Present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present -#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present -#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present -#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present -#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed -#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present -#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed -#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present -#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present -#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present -#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present -#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present -#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present -#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present -#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available -#define SYSCTL_DC3_CCP5 0x20000000 // T2CCP1 Pin Present -#define SYSCTL_DC3_CCP4 0x10000000 // T2CCP0 Pin Present -#define SYSCTL_DC3_CCP3 0x08000000 // T1CCP1 Pin Present -#define SYSCTL_DC3_CCP2 0x04000000 // T1CCP0 Pin Present -#define SYSCTL_DC3_CCP1 0x02000000 // T0CCP1 Pin Present -#define SYSCTL_DC3_CCP0 0x01000000 // T0CCP0 Pin Present -#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present -#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present -#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present -#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present -#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present -#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present -#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present -#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present -#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present -#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present -#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present -#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present -#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present -#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable -#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate -#define SYSCTL_DC4_CCP7 0x00008000 // T3CCP1 Pin Present -#define SYSCTL_DC4_CCP6 0x00004000 // T3CCP0 Pin Present -#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present -#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present -#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present -#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present -#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present -#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC5 register. -// -//***************************************************************************** -#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present -#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present -#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present -#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present -#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active -#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active -#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present -#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present -#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present -#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present -#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present -#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present -#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present -#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC6 register. -// -//***************************************************************************** -#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present -#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present -#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only -#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host -#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC7 register. -// -//***************************************************************************** -#define SYSCTL_DC7_DMACH30 0x40000000 // DMA Channel 30 -#define SYSCTL_DC7_DMACH29 0x20000000 // DMA Channel 29 -#define SYSCTL_DC7_DMACH28 0x10000000 // DMA Channel 28 -#define SYSCTL_DC7_DMACH27 0x08000000 // DMA Channel 27 -#define SYSCTL_DC7_DMACH26 0x04000000 // DMA Channel 26 -#define SYSCTL_DC7_DMACH25 0x02000000 // DMA Channel 25 -#define SYSCTL_DC7_DMACH24 0x01000000 // DMA Channel 24 -#define SYSCTL_DC7_DMACH23 0x00800000 // DMA Channel 23 -#define SYSCTL_DC7_DMACH22 0x00400000 // DMA Channel 22 -#define SYSCTL_DC7_DMACH21 0x00200000 // DMA Channel 21 -#define SYSCTL_DC7_DMACH20 0x00100000 // DMA Channel 20 -#define SYSCTL_DC7_DMACH19 0x00080000 // DMA Channel 19 -#define SYSCTL_DC7_DMACH18 0x00040000 // DMA Channel 18 -#define SYSCTL_DC7_DMACH17 0x00020000 // DMA Channel 17 -#define SYSCTL_DC7_DMACH16 0x00010000 // DMA Channel 16 -#define SYSCTL_DC7_DMACH15 0x00008000 // DMA Channel 15 -#define SYSCTL_DC7_DMACH14 0x00004000 // DMA Channel 14 -#define SYSCTL_DC7_DMACH13 0x00002000 // DMA Channel 13 -#define SYSCTL_DC7_DMACH12 0x00001000 // DMA Channel 12 -#define SYSCTL_DC7_DMACH11 0x00000800 // DMA Channel 11 -#define SYSCTL_DC7_DMACH10 0x00000400 // DMA Channel 10 -#define SYSCTL_DC7_DMACH9 0x00000200 // DMA Channel 9 -#define SYSCTL_DC7_DMACH8 0x00000100 // DMA Channel 8 -#define SYSCTL_DC7_DMACH7 0x00000080 // DMA Channel 7 -#define SYSCTL_DC7_DMACH6 0x00000040 // DMA Channel 6 -#define SYSCTL_DC7_DMACH5 0x00000020 // DMA Channel 5 -#define SYSCTL_DC7_DMACH4 0x00000010 // DMA Channel 4 -#define SYSCTL_DC7_DMACH3 0x00000008 // DMA Channel 3 -#define SYSCTL_DC7_DMACH2 0x00000004 // DMA Channel 2 -#define SYSCTL_DC7_DMACH1 0x00000002 // DMA Channel 1 -#define SYSCTL_DC7_DMACH0 0x00000001 // DMA Channel 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC8 register. -// -//***************************************************************************** -#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present -#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present -#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present -#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present -#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present -#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present -#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present -#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present -#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present -#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present -#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present -#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present -#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present -#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present -#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present -#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present -#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present -#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present -#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present -#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present -#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present -#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present -#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present -#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present -#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present -#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present -#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present -#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present -#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present -#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present -#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present -#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR0 0x00000004 // VDD under BOR0 Event Action -#define SYSCTL_PBORCTL_BOR1 0x00000002 // VDD under BOR1 Event Action - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PTBOCTL register. -// -//***************************************************************************** -#define SYSCTL_PTBOCTL_VDDA_UBOR_M \ - 0x00000300 // VDDA under BOR Event Action -#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE \ - 0x00000000 // No Action -#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT \ - 0x00000100 // System control interrupt -#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI \ - 0x00000200 // NMI -#define SYSCTL_PTBOCTL_VDDA_UBOR_RST \ - 0x00000300 // Reset -#define SYSCTL_PTBOCTL_VDD_UBOR_M \ - 0x00000003 // VDD (VDDS) under BOR Event - // Action -#define SYSCTL_PTBOCTL_VDD_UBOR_NONE \ - 0x00000000 // No Action -#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT \ - 0x00000001 // System control interrupt -#define SYSCTL_PTBOCTL_VDD_UBOR_NMI \ - 0x00000002 // NMI -#define SYSCTL_PTBOCTL_VDD_UBOR_RST \ - 0x00000003 // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR0 register. -// -//***************************************************************************** -#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control -#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control -#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control -#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control -#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control -#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control -#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control -#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR1 register. -// -//***************************************************************************** -#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control -#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control -#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control -#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control -#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control -#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control -#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control -#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control -#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control -#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control -#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control -#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control -#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control -#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control -#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control -#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR2 register. -// -//***************************************************************************** -#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control -#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control -#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control -#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control -#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control -#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control -#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control -#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control -#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control -#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control -#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RIS register. -// -//***************************************************************************** -#define SYSCTL_RIS_BOR0RIS 0x00000800 // VDD under BOR0 Raw Interrupt - // Status -#define SYSCTL_RIS_VDDARIS 0x00000400 // VDDA Power OK Event Raw - // Interrupt Status -#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt - // Status -#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt - // Status -#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status -#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw - // Interrupt Status -#define SYSCTL_RIS_BOR1RIS 0x00000002 // VDD under BOR1 Raw Interrupt - // Status -#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_IMC register. -// -//***************************************************************************** -#define SYSCTL_IMC_BOR0IM 0x00000800 // VDD under BOR0 Interrupt Mask -#define SYSCTL_IMC_VDDAIM 0x00000400 // VDDA Power OK Interrupt Mask -#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask -#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask -#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask -#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure - // Interrupt Mask -#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask -#define SYSCTL_IMC_BOR1IM 0x00000002 // VDD under BOR1 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MISC register. -// -//***************************************************************************** -#define SYSCTL_MISC_BOR0MIS 0x00000800 // VDD under BOR0 Masked Interrupt - // Status -#define SYSCTL_MISC_VDDAMIS 0x00000400 // VDDA Power OK Masked Interrupt - // Status -#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt - // Status -#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt - // Status -#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status -#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked - // Interrupt Status -#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status -#define SYSCTL_MISC_BOR1MIS 0x00000002 // VDD under BOR1 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset -#define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset -#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset -#define SYSCTL_RESC_SW 0x00000010 // Software Reset -#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset -#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset -#define SYSCTL_RESC_EXT 0x00000001 // External Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PWRTC register. -// -//***************************************************************************** -#define SYSCTL_PWRTC_VDDA_UBOR 0x00000010 // VDDA Under BOR Status -#define SYSCTL_PWRTC_VDD_UBOR 0x00000001 // VDD Under BOR Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating -#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor -#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider -#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor -#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass -#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value -#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz -#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz -#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz -#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz -#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz -#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz -#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz -#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz -#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz (USB) -#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz (USB) -#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz (USB) -#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz (USB) -#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 -#define SYSCTL_RCC_OSCSRC_30 0x00000030 // LFIOSC -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable -#define SYSCTL_RCC_SYSDIV_S 23 -#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_NMIC register. -// -//***************************************************************************** -#define SYSCTL_NMIC_MOSCFAIL 0x00010000 // MOSC Failure NMI -#define SYSCTL_NMIC_TAMPER 0x00000200 // Tamper Event NMI -#define SYSCTL_NMIC_WDT1 0x00000020 // Watch Dog Timer (WDT) 1 NMI -#define SYSCTL_NMIC_WDT0 0x00000008 // Watch Dog Timer (WDT) 0 NMI -#define SYSCTL_NMIC_POWER 0x00000004 // Power/Brown Out Event NMI -#define SYSCTL_NMIC_EXTERNAL 0x00000001 // External Pin NMI - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL -// register. -// -//***************************************************************************** -#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance - // Bus - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCC2 register. -// -//***************************************************************************** -#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 -#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200 - // MHz -#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 -#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2 -#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL -#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 -#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 -#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 -#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC -#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC -#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 -#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // LFIOSC -#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz -#define SYSCTL_RCC2_SYSDIV2_S 23 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. -// -//***************************************************************************** -#define SYSCTL_MOSCCTL_OSCRNG 0x00000010 // Oscillator Range -#define SYSCTL_MOSCCTL_PWRDN 0x00000008 // Power Down -#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected -#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action -#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RSCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000 // Memory Timing Register Update -#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000 // New PLLFREQ Accept -#define SYSCTL_RSCLKCFG_ACG 0x20000000 // Auto Clock Gating -#define SYSCTL_RSCLKCFG_USEPLL 0x10000000 // Use PLL -#define SYSCTL_RSCLKCFG_PLLSRC_M \ - 0x0F000000 // PLL Source -#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC \ - 0x00000000 // PIOSC is PLL input clock source -#define SYSCTL_RSCLKCFG_PLLSRC_MOSC \ - 0x03000000 // MOSC is the PLL input clock - // source -#define SYSCTL_RSCLKCFG_OSCSRC_M \ - 0x00F00000 // Oscillator Source -#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC \ - 0x00000000 // PIOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC \ - 0x00200000 // LFIOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_MOSC \ - 0x00300000 // MOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_RTC \ - 0x00400000 // Hibernation Module RTC - // Oscillator (RTCOSC) -#define SYSCTL_RSCLKCFG_OSYSDIV_M \ - 0x000FFC00 // Oscillator System Clock Divisor -#define SYSCTL_RSCLKCFG_PSYSDIV_M \ - 0x000003FF // PLL System Clock Divisor -#define SYSCTL_RSCLKCFG_OSYSDIV_S \ - 10 -#define SYSCTL_RSCLKCFG_PSYSDIV_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register. -// -//***************************************************************************** -#define SYSCTL_MEMTIM0_EBCHT_M 0x03C00000 // EEPROM Clock High Time -#define SYSCTL_MEMTIM0_EBCHT_0_5 \ - 0x00000000 // 1/2 system clock period -#define SYSCTL_MEMTIM0_EBCHT_1 0x00400000 // 1 system clock period -#define SYSCTL_MEMTIM0_EBCHT_1_5 \ - 0x00800000 // 1.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_2 0x00C00000 // 2 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_2_5 \ - 0x01000000 // 2.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_3 0x01400000 // 3 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_3_5 \ - 0x01800000 // 3.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_4 0x01C00000 // 4 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_4_5 \ - 0x02000000 // 4.5 system clock periods -#define SYSCTL_MEMTIM0_EBCE 0x00200000 // EEPROM Bank Clock Edge -#define SYSCTL_MEMTIM0_MB1 0x00100010 // Must be one -#define SYSCTL_MEMTIM0_EWS_M 0x000F0000 // EEPROM Wait States -#define SYSCTL_MEMTIM0_FBCHT_M 0x000003C0 // Flash Bank Clock High Time -#define SYSCTL_MEMTIM0_FBCHT_0_5 \ - 0x00000000 // 1/2 system clock period -#define SYSCTL_MEMTIM0_FBCHT_1 0x00000040 // 1 system clock period -#define SYSCTL_MEMTIM0_FBCHT_1_5 \ - 0x00000080 // 1.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_2 0x000000C0 // 2 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_2_5 \ - 0x00000100 // 2.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_3 0x00000140 // 3 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_3_5 \ - 0x00000180 // 3.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_4 0x000001C0 // 4 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_4_5 \ - 0x00000200 // 4.5 system clock periods -#define SYSCTL_MEMTIM0_FBCE 0x00000020 // Flash Bank Clock Edge -#define SYSCTL_MEMTIM0_FWS_M 0x0000000F // Flash Wait State -#define SYSCTL_MEMTIM0_EWS_S 16 -#define SYSCTL_MEMTIM0_FWS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC0 register. -// -//***************************************************************************** -#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control -#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control -#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control -#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control -#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed -#define SYSCTL_RCGC0_ADC1SPD_125K \ - 0x00000000 // 125K samples/second -#define SYSCTL_RCGC0_ADC1SPD_250K \ - 0x00000400 // 250K samples/second -#define SYSCTL_RCGC0_ADC1SPD_500K \ - 0x00000800 // 500K samples/second -#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second -#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed -#define SYSCTL_RCGC0_ADC0SPD_125K \ - 0x00000000 // 125K samples/second -#define SYSCTL_RCGC0_ADC0SPD_250K \ - 0x00000100 // 250K samples/second -#define SYSCTL_RCGC0_ADC0SPD_500K \ - 0x00000200 // 500K samples/second -#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second -#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC1 register. -// -//***************************************************************************** -#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating -#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating -#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control -#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control -#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control -#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC2 register. -// -//***************************************************************************** -#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control -#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control -#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control -#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control -#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC0 register. -// -//***************************************************************************** -#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control -#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control -#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control -#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control -#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed -#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC1 register. -// -//***************************************************************************** -#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating -#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating -#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control -#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control -#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control -#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC2 register. -// -//***************************************************************************** -#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control -#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control -#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control -#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control -#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC0 register. -// -//***************************************************************************** -#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control -#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control -#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control -#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control -#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC1 register. -// -//***************************************************************************** -#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating -#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating -#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control -#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control -#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control -#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC2 register. -// -//***************************************************************************** -#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control -#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control -#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control -#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control -#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_ALTCLKCFG_ALTCLK_M \ - 0x0000000F // Alternate Clock Source -#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC \ - 0x00000000 // PIOSC -#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC \ - 0x00000003 // Hibernation Module Real-time - // clock output (RTCOSC) -#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC \ - 0x00000004 // Low-frequency internal - // oscillator (LFIOSC) - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override -#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source -#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC -#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC -#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // LFIOSC -#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz -#define SYSCTL_DSLPCLKCFG_PIOSCPD \ - 0x00000002 // PIOSC Power Down Request -#define SYSCTL_DSLPCLKCFG_D_S 23 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000 // PIOSC Power Down -#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000 // MOSC Disable Power Down -#define SYSCTL_DSCLKCFG_DSOSCSRC_M \ - 0x00F00000 // Deep Sleep Oscillator Source -#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC \ - 0x00000000 // PIOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC \ - 0x00200000 // LFIOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC \ - 0x00300000 // MOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC \ - 0x00400000 // Hibernation Module RTCOSC -#define SYSCTL_DSCLKCFG_DSSYSDIV_M \ - 0x000003FF // Deep Sleep Clock Divisor -#define SYSCTL_DSCLKCFG_DSSYSDIV_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DIVSCLK register. -// -//***************************************************************************** -#define SYSCTL_DIVSCLK_EN 0x80000000 // DIVSCLK Enable -#define SYSCTL_DIVSCLK_SRC_M 0x00030000 // Clock Source -#define SYSCTL_DIVSCLK_SRC_SYSCLK \ - 0x00000000 // System Clock -#define SYSCTL_DIVSCLK_SRC_PIOSC \ - 0x00010000 // PIOSC -#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000 // MOSC -#define SYSCTL_DIVSCLK_DIV_M 0x000000FF // Divisor Value -#define SYSCTL_DIVSCLK_DIV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SYSPROP register. -// -//***************************************************************************** -#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PIOSCCAL -// register. -// -//***************************************************************************** -#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value -#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration -#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim -#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value -#define SYSCTL_PIOSCCAL_UT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT -// register. -// -//***************************************************************************** -#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value -#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result -#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been - // attempted -#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation - // completed to meet 1% accuracy -#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation - // failed to meet 1% accuracy -#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value -#define SYSCTL_PIOSCSTAT_DT_S 16 -#define SYSCTL_PIOSCSTAT_CT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 -// register. -// -//***************************************************************************** -#define SYSCTL_PLLFREQ0_PLLPWR 0x00800000 // PLL Power -#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value -#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value -#define SYSCTL_PLLFREQ0_MFRAC_S 10 -#define SYSCTL_PLLFREQ0_MINT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 -// register. -// -//***************************************************************************** -#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value -#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value -#define SYSCTL_PLLFREQ1_Q_S 8 -#define SYSCTL_PLLFREQ1_N_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. -// -//***************************************************************************** -#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG -// register. -// -//***************************************************************************** -#define SYSCTL_SLPPWRCFG_FLASHPM_M \ - 0x00000030 // Flash Power Modes -#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \ - 0x00000020 // Low Power Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_M \ - 0x00000003 // SRAM Power Modes -#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \ - 0x00000001 // Standby Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_LP \ - 0x00000003 // Low Power Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200 // LDO Sleep Mode -#define SYSCTL_DSLPPWRCFG_TSPD 0x00000100 // Temperature Sense Power Down -#define SYSCTL_DSLPPWRCFG_FLASHPM_M \ - 0x00000030 // Flash Power Modes -#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \ - 0x00000020 // Low Power Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_M \ - 0x00000003 // SRAM Power Modes -#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \ - 0x00000001 // Standby Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \ - 0x00000003 // Low Power Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC9 register. -// -//***************************************************************************** -#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present -#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present -#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present -#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present -#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present -#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present -#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present -#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present -#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present -#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present -#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present -#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present -#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present -#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present -#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present -#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. -// -//***************************************************************************** -#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer - // Available - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_LDOSPCTL -// register. -// -//***************************************************************************** -#define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable -#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage -#define SYSCTL_LDOSPCTL_VLDO_0_90V \ - 0x00000012 // 0.90 V -#define SYSCTL_LDOSPCTL_VLDO_0_95V \ - 0x00000013 // 0.95 V -#define SYSCTL_LDOSPCTL_VLDO_1_00V \ - 0x00000014 // 1.00 V -#define SYSCTL_LDOSPCTL_VLDO_1_05V \ - 0x00000015 // 1.05 V -#define SYSCTL_LDOSPCTL_VLDO_1_10V \ - 0x00000016 // 1.10 V -#define SYSCTL_LDOSPCTL_VLDO_1_15V \ - 0x00000017 // 1.15 V -#define SYSCTL_LDOSPCTL_VLDO_1_20V \ - 0x00000018 // 1.20 V - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_LDODPCTL -// register. -// -//***************************************************************************** -#define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable -#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage -#define SYSCTL_LDODPCTL_VLDO_0_90V \ - 0x00000012 // 0.90 V -#define SYSCTL_LDODPCTL_VLDO_0_95V \ - 0x00000013 // 0.95 V -#define SYSCTL_LDODPCTL_VLDO_1_00V \ - 0x00000014 // 1.00 V -#define SYSCTL_LDODPCTL_VLDO_1_05V \ - 0x00000015 // 1.05 V -#define SYSCTL_LDODPCTL_VLDO_1_10V \ - 0x00000016 // 1.10 V -#define SYSCTL_LDODPCTL_VLDO_1_15V \ - 0x00000017 // 1.15 V -#define SYSCTL_LDODPCTL_VLDO_1_20V \ - 0x00000018 // 1.20 V -#define SYSCTL_LDODPCTL_VLDO_1_25V \ - 0x00000019 // 1.25 V -#define SYSCTL_LDODPCTL_VLDO_1_30V \ - 0x0000001A // 1.30 V -#define SYSCTL_LDODPCTL_VLDO_1_35V \ - 0x0000001B // 1.35 V - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL -// register. -// -//***************************************************************************** -#define SYSCTL_RESBEHAVCTL_WDOG1_M \ - 0x000000C0 // Watchdog 1 Reset Operation -#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST \ - 0x00000080 // Watchdog 1 issues a system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_WDOG1_POR \ - 0x000000C0 // Watchdog 1 issues a simulated - // POR sequence. Application starts - // less than 500 us after - // deassertion (Default) -#define SYSCTL_RESBEHAVCTL_WDOG0_M \ - 0x00000030 // Watchdog 0 Reset Operation -#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST \ - 0x00000020 // Watchdog 0 issues a system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_WDOG0_POR \ - 0x00000030 // Watchdog 0 issues a simulated - // POR sequence. Application starts - // less than 500 us after - // deassertion (Default) -#define SYSCTL_RESBEHAVCTL_BOR_M \ - 0x0000000C // BOR Reset operation -#define SYSCTL_RESBEHAVCTL_BOR_SYSRST \ - 0x00000008 // Brown Out Reset issues system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_BOR_POR \ - 0x0000000C // Brown Out Reset issues a - // simulated POR sequence. The - // application starts less than 500 - // us after deassertion (Default) -#define SYSCTL_RESBEHAVCTL_EXTRES_M \ - 0x00000003 // External RST Pin Operation -#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST \ - 0x00000002 // External RST assertion issues a - // system reset. The application - // starts within 10 us -#define SYSCTL_RESBEHAVCTL_EXTRES_POR \ - 0x00000003 // External RST assertion issues a - // simulated POR sequence. - // Application starts less than 500 - // us after deassertion (Default) - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_HSSR register. -// -//***************************************************************************** -#define SYSCTL_HSSR_KEY_M 0xFF000000 // Write Key -#define SYSCTL_HSSR_CDOFF_M 0x00FFFFFF // Command Descriptor Pointer -#define SYSCTL_HSSR_KEY_S 24 -#define SYSCTL_HSSR_CDOFF_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_USBPDS register. -// -//***************************************************************************** -#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C // Memory Array Power Status -#define SYSCTL_USBPDS_MEMSTAT_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_USBPDS_MEMSTAT_RETAIN \ - 0x00000004 // SRAM Retention -#define SYSCTL_USBPDS_MEMSTAT_ON \ - 0x0000000C // Array On -#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003 // Power Domain Status -#define SYSCTL_USBPDS_PWRSTAT_OFF \ - 0x00000000 // OFF -#define SYSCTL_USBPDS_PWRSTAT_ON \ - 0x00000003 // ON - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_USBMPC register. -// -//***************************************************************************** -#define SYSCTL_USBMPC_PWRCTL_M 0x00000003 // Memory Array Power Control -#define SYSCTL_USBMPC_PWRCTL_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_USBMPC_PWRCTL_RETAIN \ - 0x00000001 // SRAM Retention -#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003 // Array On - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_EMACPDS register. -// -//***************************************************************************** -#define SYSCTL_EMACPDS_MEMSTAT_M \ - 0x0000000C // Memory Array Power Status -#define SYSCTL_EMACPDS_MEMSTAT_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_EMACPDS_MEMSTAT_ON \ - 0x0000000C // Array On -#define SYSCTL_EMACPDS_PWRSTAT_M \ - 0x00000003 // Power Domain Status -#define SYSCTL_EMACPDS_PWRSTAT_OFF \ - 0x00000000 // OFF -#define SYSCTL_EMACPDS_PWRSTAT_ON \ - 0x00000003 // ON - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_EMACMPC register. -// -//***************************************************************************** -#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003 // Memory Array Power Control -#define SYSCTL_EMACMPC_PWRCTL_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_EMACMPC_PWRCTL_ON \ - 0x00000003 // Array On - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_LCDMPC register. -// -//***************************************************************************** -#define SYSCTL_LCDMPC_PWRCTL_M 0x00000003 // Memory Array Power Control -#define SYSCTL_LCDMPC_PWRCTL_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003 // Array On - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPWD register. -// -//***************************************************************************** -#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present -#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPTIMER register. -// -//***************************************************************************** -#define SYSCTL_PPTIMER_P7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Present -#define SYSCTL_PPTIMER_P6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Present -#define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Present -#define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Present -#define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Present -#define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Present -#define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Present -#define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPGPIO register. -// -//***************************************************************************** -#define SYSCTL_PPGPIO_P17 0x00020000 // GPIO Port T Present -#define SYSCTL_PPGPIO_P16 0x00010000 // GPIO Port S Present -#define SYSCTL_PPGPIO_P15 0x00008000 // GPIO Port R Present -#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present -#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present -#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present -#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present -#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present -#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present -#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present -#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present -#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present -#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present -#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present -#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present -#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present -#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present -#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPDMA register. -// -//***************************************************************************** -#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEPI register. -// -//***************************************************************************** -#define SYSCTL_PPEPI_P0 0x00000001 // EPI Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPHIB register. -// -//***************************************************************************** -#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPUART register. -// -//***************************************************************************** -#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present -#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present -#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present -#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present -#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present -#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present -#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present -#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPSSI register. -// -//***************************************************************************** -#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present -#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present -#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present -#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPI2C register. -// -//***************************************************************************** -#define SYSCTL_PPI2C_P9 0x00000200 // I2C Module 9 Present -#define SYSCTL_PPI2C_P8 0x00000100 // I2C Module 8 Present -#define SYSCTL_PPI2C_P7 0x00000080 // I2C Module 7 Present -#define SYSCTL_PPI2C_P6 0x00000040 // I2C Module 6 Present -#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present -#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present -#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present -#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present -#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present -#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPUSB register. -// -//***************************************************************************** -#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEPHY register. -// -//***************************************************************************** -#define SYSCTL_PPEPHY_P0 0x00000001 // Ethernet PHY Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPCAN register. -// -//***************************************************************************** -#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present -#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPADC register. -// -//***************************************************************************** -#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present -#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPACMP register. -// -//***************************************************************************** -#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPPWM register. -// -//***************************************************************************** -#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present -#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPQEI register. -// -//***************************************************************************** -#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present -#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPLPC register. -// -//***************************************************************************** -#define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPPECI register. -// -//***************************************************************************** -#define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPFAN register. -// -//***************************************************************************** -#define SYSCTL_PPFAN_P0 0x00000001 // FAN Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_PPWTIMER_P5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Present -#define SYSCTL_PPWTIMER_P4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Present -#define SYSCTL_PPWTIMER_P3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Present -#define SYSCTL_PPWTIMER_P2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Present -#define SYSCTL_PPWTIMER_P1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Present -#define SYSCTL_PPWTIMER_P0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPRTS register. -// -//***************************************************************************** -#define SYSCTL_PPRTS_P0 0x00000001 // RTS Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPCCM register. -// -//***************************************************************************** -#define SYSCTL_PPCCM_P0 0x00000001 // CRC and Cryptographic Modules - // Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPLCD register. -// -//***************************************************************************** -#define SYSCTL_PPLCD_P0 0x00000001 // LCD Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPOWIRE register. -// -//***************************************************************************** -#define SYSCTL_PPOWIRE_P0 0x00000001 // 1-Wire Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEMAC register. -// -//***************************************************************************** -#define SYSCTL_PPEMAC_P0 0x00000001 // Ethernet Controller Module - // Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPHIM register. -// -//***************************************************************************** -#define SYSCTL_PPHIM_P0 0x00000001 // HIM Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRWD register. -// -//***************************************************************************** -#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset -#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRTIMER register. -// -//***************************************************************************** -#define SYSCTL_SRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Software Reset -#define SYSCTL_SRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Software Reset -#define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Software Reset -#define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Software Reset -#define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Software Reset -#define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Software Reset -#define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Software Reset -#define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRGPIO register. -// -//***************************************************************************** -#define SYSCTL_SRGPIO_R17 0x00020000 // GPIO Port T Software Reset -#define SYSCTL_SRGPIO_R16 0x00010000 // GPIO Port S Software Reset -#define SYSCTL_SRGPIO_R15 0x00008000 // GPIO Port R Software Reset -#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset -#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset -#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset -#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset -#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset -#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset -#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset -#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset -#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset -#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset -#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset -#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset -#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset -#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset -#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRDMA register. -// -//***************************************************************************** -#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREPI register. -// -//***************************************************************************** -#define SYSCTL_SREPI_R0 0x00000001 // EPI Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRHIB register. -// -//***************************************************************************** -#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software - // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRUART register. -// -//***************************************************************************** -#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset -#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset -#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset -#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset -#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset -#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset -#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset -#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRSSI register. -// -//***************************************************************************** -#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset -#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset -#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset -#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRI2C register. -// -//***************************************************************************** -#define SYSCTL_SRI2C_R9 0x00000200 // I2C Module 9 Software Reset -#define SYSCTL_SRI2C_R8 0x00000100 // I2C Module 8 Software Reset -#define SYSCTL_SRI2C_R7 0x00000080 // I2C Module 7 Software Reset -#define SYSCTL_SRI2C_R6 0x00000040 // I2C Module 6 Software Reset -#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset -#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset -#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset -#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset -#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset -#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRUSB register. -// -//***************************************************************************** -#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREPHY register. -// -//***************************************************************************** -#define SYSCTL_SREPHY_R0 0x00000001 // Ethernet PHY Module Software - // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCAN register. -// -//***************************************************************************** -#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset -#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRADC register. -// -//***************************************************************************** -#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset -#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRACMP register. -// -//***************************************************************************** -#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRPWM register. -// -//***************************************************************************** -#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset -#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRQEI register. -// -//***************************************************************************** -#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset -#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_SRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Software Reset -#define SYSCTL_SRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Software Reset -#define SYSCTL_SRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Software Reset -#define SYSCTL_SRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Software Reset -#define SYSCTL_SRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Software Reset -#define SYSCTL_SRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCCM register. -// -//***************************************************************************** -#define SYSCTL_SRCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRLCD register. -// -//***************************************************************************** -#define SYSCTL_SRLCD_R0 0x00000001 // LCD Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SROWIRE register. -// -//***************************************************************************** -#define SYSCTL_SROWIRE_R0 0x00000001 // 1-Wire Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREMAC register. -// -//***************************************************************************** -#define SYSCTL_SREMAC_R0 0x00000001 // Ethernet Controller MAC Module 0 - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCWD register. -// -//***************************************************************************** -#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Run Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCGPIO_R17 0x00020000 // GPIO Port T Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R16 0x00010000 // GPIO Port S Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R15 0x00008000 // GPIO Port R Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_RCGCEPI_R0 0x00000001 // EPI Module Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_RCGCI2C_R9 0x00000200 // I2C Module 9 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R8 0x00000100 // I2C Module 8 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R7 0x00000080 // I2C Module 7 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R6 0x00000040 // I2C Module 6 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEPHY_R0 0x00000001 // Ethernet PHY Module Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCADC register. -// -//***************************************************************************** -#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_RCGCCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Run Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCLCD register. -// -//***************************************************************************** -#define SYSCTL_RCGCLCD_R0 0x00000001 // LCD Controller Module 0 Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCOWIRE -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCOWIRE_R0 0x00000001 // 1-Wire Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEMAC_R0 0x00000001 // Ethernet MAC Module 0 Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCWD register. -// -//***************************************************************************** -#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCTIMER_S7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCGPIO_S17 0x00020000 // GPIO Port T Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S16 0x00010000 // GPIO Port S Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S15 0x00008000 // GPIO Port R Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_SCGCEPI_S0 0x00000001 // EPI Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_SCGCI2C_S9 0x00000200 // I2C Module 9 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S8 0x00000100 // I2C Module 8 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S7 0x00000080 // I2C Module 7 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S6 0x00000040 // I2C Module 6 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEPHY_S0 0x00000001 // PHY Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCADC register. -// -//***************************************************************************** -#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCWTIMER_S5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER_S4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER_S3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER_S2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER_S1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER_S0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_SCGCCCM_S0 0x00000001 // CRC and Cryptographic Modules - // Sleep Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCLCD register. -// -//***************************************************************************** -#define SYSCTL_SCGCLCD_S0 0x00000001 // LCD Controller Module 0 Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCOWIRE -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCOWIRE_S0 0x00000001 // 1-Wire Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEMAC_S0 0x00000001 // Ethernet MAC Module 0 Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCWD register. -// -//***************************************************************************** -#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCTIMER_D7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCGPIO_D17 0x00020000 // GPIO Port T Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D16 0x00010000 // GPIO Port S Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D15 0x00008000 // GPIO Port R Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_DCGCEPI_D0 0x00000001 // EPI Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_DCGCI2C_D9 0x00000200 // I2C Module 9 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D8 0x00000100 // I2C Module 8 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D7 0x00000080 // I2C Module 7 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D6 0x00000040 // I2C Module 6 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEPHY_D0 0x00000001 // PHY Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCADC register. -// -//***************************************************************************** -#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 - // Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCWTIMER_D5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER_D4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER_D3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER_D2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER_D1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER_D0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_DCGCCCM_D0 0x00000001 // CRC and Cryptographic Modules - // Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCLCD register. -// -//***************************************************************************** -#define SYSCTL_DCGCLCD_D0 0x00000001 // LCD Controller Module 0 - // Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCOWIRE -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCOWIRE_D0 0x00000001 // 1-Wire Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEMAC_D0 0x00000001 // Ethernet MAC Module 0 Deep-Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCWD register. -// -//***************************************************************************** -#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control -#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCTIMER register. -// -//***************************************************************************** -#define SYSCTL_PCTIMER_P7 0x00000080 // General-Purpose Timer 7 Power - // Control -#define SYSCTL_PCTIMER_P6 0x00000040 // General-Purpose Timer 6 Power - // Control -#define SYSCTL_PCTIMER_P5 0x00000020 // General-Purpose Timer 5 Power - // Control -#define SYSCTL_PCTIMER_P4 0x00000010 // General-Purpose Timer 4 Power - // Control -#define SYSCTL_PCTIMER_P3 0x00000008 // General-Purpose Timer 3 Power - // Control -#define SYSCTL_PCTIMER_P2 0x00000004 // General-Purpose Timer 2 Power - // Control -#define SYSCTL_PCTIMER_P1 0x00000002 // General-Purpose Timer 1 Power - // Control -#define SYSCTL_PCTIMER_P0 0x00000001 // General-Purpose Timer 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCGPIO register. -// -//***************************************************************************** -#define SYSCTL_PCGPIO_P17 0x00020000 // GPIO Port T Power Control -#define SYSCTL_PCGPIO_P16 0x00010000 // GPIO Port S Power Control -#define SYSCTL_PCGPIO_P15 0x00008000 // GPIO Port R Power Control -#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control -#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control -#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control -#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control -#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control -#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control -#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control -#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control -#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control -#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control -#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control -#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control -#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control -#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control -#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCDMA register. -// -//***************************************************************************** -#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEPI register. -// -//***************************************************************************** -#define SYSCTL_PCEPI_P0 0x00000001 // EPI Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCHIB register. -// -//***************************************************************************** -#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCUART register. -// -//***************************************************************************** -#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control -#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control -#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control -#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control -#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control -#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control -#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control -#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCSSI register. -// -//***************************************************************************** -#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control -#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control -#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control -#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCI2C register. -// -//***************************************************************************** -#define SYSCTL_PCI2C_P9 0x00000200 // I2C Module 9 Power Control -#define SYSCTL_PCI2C_P8 0x00000100 // I2C Module 8 Power Control -#define SYSCTL_PCI2C_P7 0x00000080 // I2C Module 7 Power Control -#define SYSCTL_PCI2C_P6 0x00000040 // I2C Module 6 Power Control -#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control -#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control -#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control -#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control -#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control -#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCUSB register. -// -//***************************************************************************** -#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEPHY register. -// -//***************************************************************************** -#define SYSCTL_PCEPHY_P0 0x00000001 // Ethernet PHY Module Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCCAN register. -// -//***************************************************************************** -#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control -#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCADC register. -// -//***************************************************************************** -#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control -#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCACMP register. -// -//***************************************************************************** -#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCPWM register. -// -//***************************************************************************** -#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCQEI register. -// -//***************************************************************************** -#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCCCM register. -// -//***************************************************************************** -#define SYSCTL_PCCCM_P0 0x00000001 // CRC and Cryptographic Modules - // Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCLCD register. -// -//***************************************************************************** -#define SYSCTL_PCLCD_P0 0x00000001 // LCD Controller Module 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCOWIRE register. -// -//***************************************************************************** -#define SYSCTL_PCOWIRE_P0 0x00000001 // 1-Wire Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEMAC register. -// -//***************************************************************************** -#define SYSCTL_PCEMAC_P0 0x00000001 // Ethernet MAC Module 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRWD register. -// -//***************************************************************************** -#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral - // Ready -#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRTIMER register. -// -//***************************************************************************** -#define SYSCTL_PRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Peripheral Ready -#define SYSCTL_PRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Peripheral Ready -#define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Peripheral Ready -#define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Peripheral Ready -#define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Peripheral Ready -#define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Peripheral Ready -#define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Peripheral Ready -#define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRGPIO register. -// -//***************************************************************************** -#define SYSCTL_PRGPIO_R17 0x00020000 // GPIO Port T Peripheral Ready -#define SYSCTL_PRGPIO_R16 0x00010000 // GPIO Port S Peripheral Ready -#define SYSCTL_PRGPIO_R15 0x00008000 // GPIO Port R Peripheral Ready -#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready -#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready -#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready -#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready -#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready -#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready -#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready -#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready -#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready -#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready -#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready -#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready -#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready -#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready -#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRDMA register. -// -//***************************************************************************** -#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREPI register. -// -//***************************************************************************** -#define SYSCTL_PREPI_R0 0x00000001 // EPI Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRHIB register. -// -//***************************************************************************** -#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRUART register. -// -//***************************************************************************** -#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready -#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready -#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready -#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready -#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready -#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready -#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready -#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRSSI register. -// -//***************************************************************************** -#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready -#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready -#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready -#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRI2C register. -// -//***************************************************************************** -#define SYSCTL_PRI2C_R9 0x00000200 // I2C Module 9 Peripheral Ready -#define SYSCTL_PRI2C_R8 0x00000100 // I2C Module 8 Peripheral Ready -#define SYSCTL_PRI2C_R7 0x00000080 // I2C Module 7 Peripheral Ready -#define SYSCTL_PRI2C_R6 0x00000040 // I2C Module 6 Peripheral Ready -#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready -#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready -#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready -#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready -#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready -#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRUSB register. -// -//***************************************************************************** -#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREPHY register. -// -//***************************************************************************** -#define SYSCTL_PREPHY_R0 0x00000001 // Ethernet PHY Module Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRCAN register. -// -//***************************************************************************** -#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready -#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRADC register. -// -//***************************************************************************** -#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready -#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRACMP register. -// -//***************************************************************************** -#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 - // Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRPWM register. -// -//***************************************************************************** -#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready -#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRQEI register. -// -//***************************************************************************** -#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready -#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_PRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Peripheral Ready -#define SYSCTL_PRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Peripheral Ready -#define SYSCTL_PRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Peripheral Ready -#define SYSCTL_PRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Peripheral Ready -#define SYSCTL_PRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Peripheral Ready -#define SYSCTL_PRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRCCM register. -// -//***************************************************************************** -#define SYSCTL_PRCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRLCD register. -// -//***************************************************************************** -#define SYSCTL_PRLCD_R0 0x00000001 // LCD Controller Module 0 - // Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PROWIRE register. -// -//***************************************************************************** -#define SYSCTL_PROWIRE_R0 0x00000001 // 1-Wire Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREMAC register. -// -//***************************************************************************** -#define SYSCTL_PREMAC_R0 0x00000001 // Ethernet MAC Module 0 Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_UNIQUEID0 -// register. -// -//***************************************************************************** -#define SYSCTL_UNIQUEID0_ID_M 0xFFFFFFFF // Unique ID -#define SYSCTL_UNIQUEID0_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_UNIQUEID1 -// register. -// -//***************************************************************************** -#define SYSCTL_UNIQUEID1_ID_M 0xFFFFFFFF // Unique ID -#define SYSCTL_UNIQUEID1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_UNIQUEID2 -// register. -// -//***************************************************************************** -#define SYSCTL_UNIQUEID2_ID_M 0xFFFFFFFF // Unique ID -#define SYSCTL_UNIQUEID2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_UNIQUEID3 -// register. -// -//***************************************************************************** -#define SYSCTL_UNIQUEID3_ID_M 0xFFFFFFFF // Unique ID -#define SYSCTL_UNIQUEID3_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_CCMCGREQ -// register. -// -//***************************************************************************** -#define SYSCTL_CCMCGREQ_DESCFG 0x00000004 // DES Clock Gating Request -#define SYSCTL_CCMCGREQ_AESCFG 0x00000002 // AES Clock Gating Request -#define SYSCTL_CCMCGREQ_SHACFG 0x00000001 // SHA/MD5 Clock Gating Request - -//***************************************************************************** -// -// The following definitions are deprecated. -// -//***************************************************************************** -#ifndef DEPRECATED - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the SYSCTL_DID0 -// register. -// -//***************************************************************************** -#define SYSCTL_DID0_CLASS_BLIZZARD \ - 0x00050000 // Tiva(TM) C Series TM4C123-class - // microcontrollers -#define SYSCTL_DID0_CLASS_SNOWFLAKE \ - 0x000A0000 // Tiva(TM) C Series TM4C129-class - // microcontrollers - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the SYSCTL_RESC -// register. -// -//***************************************************************************** -#define SYSCTL_RESC_HIB 0x00000040 // HIB Reset - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the SYSCTL_PWRTC -// register. -// -//***************************************************************************** -#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010 // VDDA Under BOR0 Status -#define SYSCTL_PWRTC_VDD_UBOR0 0x00000001 // VDD Under BOR0 Status - -#endif - -#endif // __HW_SYSCTL_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_sysexc.h b/bsp/tm4c129x-dk/libraries/inc/hw_sysexc.h deleted file mode 100644 index 314d17a8a1452e7e607682858e0cbef64b8b2aa1..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_sysexc.h +++ /dev/null @@ -1,132 +0,0 @@ -//***************************************************************************** -// -// hw_sysexc.h - Macros used when accessing the system exception module. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_SYSEXC_H__ -#define __HW_SYSEXC_H__ - -//***************************************************************************** -// -// The following are defines for the System Exception Module register -// addresses. -// -//***************************************************************************** -#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt - // Status -#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask -#define SYSEXC_MIS 0x400F9008 // System Exception Masked - // Interrupt Status -#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_RIS register. -// -//***************************************************************************** -#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception - // Raw Interrupt Status -#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation - // Raw Interrupt Status -#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0 - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal - // Exception Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_IM register. -// -//***************************************************************************** -#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception - // Interrupt Mask -#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow - // Exception Interrupt Mask -#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow - // Exception Interrupt Mask -#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation - // Interrupt Mask -#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0 - // Exception Interrupt Mask -#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal - // Exception Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_MIS register. -// -//***************************************************************************** -#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception - // Masked Interrupt Status -#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation - // Masked Interrupt Status -#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0 - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal - // Exception Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_IC register. -// -//***************************************************************************** -#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception - // Interrupt Clear -#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow - // Exception Interrupt Clear -#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow - // Exception Interrupt Clear -#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation - // Interrupt Clear -#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0 - // Exception Interrupt Clear -#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal - // Exception Interrupt Clear - -#endif // __HW_SYSEXC_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_timer.h b/bsp/tm4c129x-dk/libraries/inc/hw_timer.h deleted file mode 100644 index 47a857567a84ab1b7ce64f2bc35e233e1bde13f5..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_timer.h +++ /dev/null @@ -1,700 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following are defines for the Timer register offsets. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // GPTM Configuration -#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode -#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode -#define TIMER_O_CTL 0x0000000C // GPTM Control -#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize -#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask -#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status -#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status -#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear -#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load -#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load -#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match -#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match -#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale -#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale -#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match -#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match -#define TIMER_O_TAR 0x00000048 // GPTM Timer A -#define TIMER_O_TBR 0x0000004C // GPTM Timer B -#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value -#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value -#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide -#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot -#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot -#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value -#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value -#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event -#define TIMER_O_ADCEV 0x00000070 // GPTM ADC Event -#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties -#define TIMER_O_CC 0x00000FC8 // GPTM Clock Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_M 0x00000007 // GPTM Configuration -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this - // value selects the 32-bit timer - // configuration -#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this - // value selects the 32-bit - // real-time clock (RTC) counter - // configuration -#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this - // value selects the 16-bit timer - // configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMR register. -// -//***************************************************************************** -#define TIMER_TAMR_TCACT_M 0x0000E000 // Timer Compare Action Select -#define TIMER_TAMR_TCACT_NONE 0x00000000 // Disable compare operations -#define TIMER_TAMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out -#define TIMER_TAMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out -#define TIMER_TAMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out -#define TIMER_TAMR_TCACT_SETTOGTO \ - 0x00008000 // Set CCP immediately and toggle - // on Time-Out -#define TIMER_TAMR_TCACT_CLRTOGTO \ - 0x0000A000 // Clear CCP immediately and toggle - // on Time-Out -#define TIMER_TAMR_TCACT_SETCLRTO \ - 0x0000C000 // Set CCP immediately and clear on - // Time-Out -#define TIMER_TAMR_TCACT_CLRSETTO \ - 0x0000E000 // Clear CCP immediately and set on - // Time-Out -#define TIMER_TAMR_TACINTD 0x00001000 // One-shot/Periodic Interrupt - // Disable -#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy - // Operation -#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register - // Update -#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt - // Enable -#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write -#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode -#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger -#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt - // Enable -#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction -#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode - // Select -#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode -#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode -#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMR register. -// -//***************************************************************************** -#define TIMER_TBMR_TCACT_M 0x0000E000 // Timer Compare Action Select -#define TIMER_TBMR_TCACT_NONE 0x00000000 // Disable compare operations -#define TIMER_TBMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out -#define TIMER_TBMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out -#define TIMER_TBMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out -#define TIMER_TBMR_TCACT_SETTOGTO \ - 0x00008000 // Set CCP immediately and toggle - // on Time-Out -#define TIMER_TBMR_TCACT_CLRTOGTO \ - 0x0000A000 // Clear CCP immediately and toggle - // on Time-Out -#define TIMER_TBMR_TCACT_SETCLRTO \ - 0x0000C000 // Set CCP immediately and clear on - // Time-Out -#define TIMER_TBMR_TCACT_CLRSETTO \ - 0x0000E000 // Clear CCP immediately and set on - // Time-Out -#define TIMER_TBMR_TBCINTD 0x00001000 // One-Shot/Periodic Interrupt - // Disable -#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy - // Operation -#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register - // Update -#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt - // Enable -#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write -#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode -#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger -#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt - // Enable -#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction -#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode - // Select -#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode -#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode -#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level -#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger - // Enable -#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode -#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges -#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable -#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable -#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level -#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger - // Enable -#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable -#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode -#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges -#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable -#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_SYNC register. -// -//***************************************************************************** -#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer - // 5 -#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not - // affected -#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 5 is - // triggered -#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 5 is - // triggered -#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 5 is triggered -#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer - // 4 -#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not - // affected -#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 4 is - // triggered -#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 4 is - // triggered -#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 4 is triggered -#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer - // 3 -#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not - // affected -#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 3 is - // triggered -#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 3 is - // triggered -#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 3 is triggered -#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer - // 2 -#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not - // affected -#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 2 is - // triggered -#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 2 is - // triggered -#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 2 is triggered -#define TIMER_SYNC_SYNCT7_M 0x0000C000 // Synchronize GPTM Timer 7 -#define TIMER_SYNC_SYNCT7_NONE 0x00000000 // GPT7 is not affected -#define TIMER_SYNC_SYNCT7_TA 0x00004000 // A timeout event for Timer A of - // GPTM7 is triggered -#define TIMER_SYNC_SYNCT7_TB 0x00008000 // A timeout event for Timer B of - // GPTM7 is triggered -#define TIMER_SYNC_SYNCT7_TATB 0x0000C000 // A timeout event for both Timer A - // and Timer B of GPTM7 is - // triggered -#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer - // 1 -#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not - // affected -#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 1 is - // triggered -#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 1 is - // triggered -#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 1 is triggered -#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer - // 0 -#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not - // affected -#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 0 is - // triggered -#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 0 is - // triggered -#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 0 is triggered -#define TIMER_SYNC_SYNCT6_M 0x00003000 // Synchronize GPTM Timer 6 -#define TIMER_SYNC_SYNCT6_NONE 0x00000000 // GPTM6 is not affected -#define TIMER_SYNC_SYNCT6_TA 0x00001000 // A timeout event for Timer A of - // GPTM6 is triggered -#define TIMER_SYNC_SYNCT6_TB 0x00002000 // A timeout event for Timer B of - // GPTM6 is triggered -#define TIMER_SYNC_SYNCT6_TATB 0x00003000 // A timeout event for both Timer A - // and Timer B of GPTM6 is - // triggered -#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5 -#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected -#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of - // GPTM5 is triggered -#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of - // GPTM5 is triggered -#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A - // and Timer B of GPTM5 is - // triggered -#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4 -#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected -#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of - // GPTM4 is triggered -#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of - // GPTM4 is triggered -#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A - // and Timer B of GPTM4 is - // triggered -#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3 -#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected -#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of - // GPTM3 is triggered -#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of - // GPTM3 is triggered -#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A - // and Timer B of GPTM3 is - // triggered -#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2 -#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected -#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of - // GPTM2 is triggered -#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of - // GPTM2 is triggered -#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A - // and Timer B of GPTM2 is - // triggered -#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1 -#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected -#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of - // GPTM1 is triggered -#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of - // GPTM1 is triggered -#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A - // and Timer B of GPTM1 is - // triggered -#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0 -#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected -#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of - // GPTM0 is triggered -#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of - // GPTM0 is triggered -#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A - // and Timer B of GPTM0 is - // triggered - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit Wide GPTM Write Update - // Error Interrupt Mask -#define TIMER_IMR_DMABIM 0x00002000 // GPTM Timer B DMA Done Interrupt - // Mask -#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt - // Mask -#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event - // Interrupt Mask -#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match - // Interrupt Mask -#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt - // Mask -#define TIMER_IMR_DMAAIM 0x00000020 // GPTM Timer A DMA Done Interrupt - // Mask -#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt - // Mask -#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask -#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event - // Interrupt Mask -#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match - // Interrupt Mask -#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit Wide GPTM Write Update - // Error Raw Interrupt Status -#define TIMER_RIS_DMABRIS 0x00002000 // GPTM Timer B DMA Done Raw - // Interrupt Status -#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt -#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event - // Raw Interrupt -#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match - // Raw Interrupt -#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw - // Interrupt -#define TIMER_RIS_DMAARIS 0x00000020 // GPTM Timer A DMA Done Raw - // Interrupt Status -#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt -#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt -#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event - // Raw Interrupt -#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match - // Raw Interrupt -#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_MIS register. -// -//***************************************************************************** -#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit Wide GPTM Write Update - // Error Masked Interrupt Status -#define TIMER_MIS_DMABMIS 0x00002000 // GPTM Timer B DMA Done Masked - // Interrupt -#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked - // Interrupt -#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event - // Masked Interrupt -#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match - // Masked Interrupt -#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked - // Interrupt -#define TIMER_MIS_DMAAMIS 0x00000020 // GPTM Timer A DMA Done Masked - // Interrupt -#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked - // Interrupt -#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt -#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event - // Masked Interrupt -#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match - // Masked Interrupt -#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit Wide GPTM Write Update - // Error Interrupt Clear -#define TIMER_ICR_DMABINT 0x00002000 // GPTM Timer B DMA Done Interrupt - // Clear -#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt - // Clear -#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event - // Interrupt Clear -#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match - // Interrupt Clear -#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt - // Clear -#define TIMER_ICR_DMAAINT 0x00000020 // GPTM Timer A DMA Done Interrupt - // Clear -#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt - // Clear -#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear -#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event - // Interrupt Clear -#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match - // Interrupt Clear -#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load - // Register -#define TIMER_TAILR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load - // Register -#define TIMER_TBILR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register -#define TIMER_TAMATCHR_TAMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register -#define TIMER_TBMATCHR_TBMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPR register. -// -//***************************************************************************** -#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte -#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale -#define TIMER_TAPR_TAPSRH_S 8 -#define TIMER_TAPR_TAPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPR register. -// -//***************************************************************************** -#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte -#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale -#define TIMER_TBPR_TBPSRH_S 8 -#define TIMER_TBPR_TBPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPMR register. -// -//***************************************************************************** -#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High - // Byte -#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match -#define TIMER_TAPMR_TAPSMRH_S 8 -#define TIMER_TAPMR_TAPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPMR register. -// -//***************************************************************************** -#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High - // Byte -#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match -#define TIMER_TBPMR_TBPSMRH_S 8 -#define TIMER_TBPMR_TBPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register -#define TIMER_TAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register -#define TIMER_TBR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAV register. -// -//***************************************************************************** -#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value -#define TIMER_TAV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBV register. -// -//***************************************************************************** -#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value -#define TIMER_TBV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RTCPD register. -// -//***************************************************************************** -#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value -#define TIMER_RTCPD_RTCPD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPS register. -// -//***************************************************************************** -#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot -#define TIMER_TAPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPS register. -// -//***************************************************************************** -#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TBPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPV register. -// -//***************************************************************************** -#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TAPV_PSV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPV register. -// -//***************************************************************************** -#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value -#define TIMER_TBPV_PSV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_DMAEV register. -// -//***************************************************************************** -#define TIMER_DMAEV_TBMDMAEN 0x00000800 // GPTM B Mode Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_CBEDMAEN 0x00000400 // GPTM B Capture Event DMA Trigger - // Enable -#define TIMER_DMAEV_CBMDMAEN 0x00000200 // GPTM B Capture Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_TBTODMAEN 0x00000100 // GPTM B Time-Out Event DMA - // Trigger Enable -#define TIMER_DMAEV_TAMDMAEN 0x00000010 // GPTM A Mode Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_RTCDMAEN 0x00000008 // GPTM A RTC Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_CAEDMAEN 0x00000004 // GPTM A Capture Event DMA Trigger - // Enable -#define TIMER_DMAEV_CAMDMAEN 0x00000002 // GPTM A Capture Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_TATODMAEN 0x00000001 // GPTM A Time-Out Event DMA - // Trigger Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ADCEV register. -// -//***************************************************************************** -#define TIMER_ADCEV_TBMADCEN 0x00000800 // GPTM B Mode Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_CBEADCEN 0x00000400 // GPTM B Capture Event ADC Trigger - // Enable -#define TIMER_ADCEV_CBMADCEN 0x00000200 // GPTM B Capture Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_TBTOADCEN 0x00000100 // GPTM B Time-Out Event ADC - // Trigger Enable -#define TIMER_ADCEV_TAMADCEN 0x00000010 // GPTM A Mode Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_RTCADCEN 0x00000008 // GPTM RTC Match Event ADC Trigger - // Enable -#define TIMER_ADCEV_CAEADCEN 0x00000004 // GPTM A Capture Event ADC Trigger - // Enable -#define TIMER_ADCEV_CAMADCEN 0x00000002 // GPTM A Capture Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_TATOADCEN 0x00000001 // GPTM A Time-Out Event ADC - // Trigger Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_PP register. -// -//***************************************************************************** -#define TIMER_PP_ALTCLK 0x00000040 // Alternate Clock Source -#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start -#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers -#define TIMER_PP_SIZE_M 0x0000000F // Count Size -#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are - // 16 bits each with an 8-bit - // prescale counter -#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are - // 32 bits each with a 16-bit - // prescale counter - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CC register. -// -//***************************************************************************** -#define TIMER_CC_ALTCLK 0x00000001 // Alternate Clock Source - -#endif // __HW_TIMER_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_types.h b/bsp/tm4c129x-dk/libraries/inc/hw_types.h deleted file mode 100644 index ec493b5061a475aef624bc69d58c73ec94c3a1c1..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_types.h +++ /dev/null @@ -1,147 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile uint32_t *)(x))) -#define HWREGH(x) \ - (*((volatile uint16_t *)(x))) -#define HWREGB(x) \ - (*((volatile uint8_t *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ - (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ - (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ - (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -//***************************************************************************** -// -// Helper Macros for determining silicon revisions, etc. -// -// These macros will be used by Driverlib at "run-time" to create necessary -// conditional code blocks that will allow a single version of the Driverlib -// "binary" code to support multiple(all) Tiva silicon revisions. -// -// It is expected that these macros will be used inside of a standard 'C' -// conditional block of code, e.g. -// -// if(CLASS_IS_TM4C123) -// { -// do some TM4C123-class specific code here. -// } -// -// By default, these macros will be defined as run-time checks of the -// appropriate register(s) to allow creation of run-time conditional code -// blocks for a common DriverLib across the entire Tiva family. -// -// However, if code-space optimization is required, these macros can be "hard- -// coded" for a specific version of Tiva silicon. Many compilers will then -// detect the "hard-coded" conditionals, and appropriately optimize the code -// blocks, eliminating any "unreachable" code. This would result in a smaller -// Driverlib, thus producing a smaller final application size, but at the cost -// of limiting the Driverlib binary to a specific Tiva silicon revision. -// -//***************************************************************************** -#ifndef CLASS_IS_TM4C123 -#define CLASS_IS_TM4C123 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ - (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C123)) -#endif - -#ifndef CLASS_IS_TM4C129 -#define CLASS_IS_TM4C129 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ - (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C129)) -#endif - -#ifndef REVISION_IS_A0 -#define REVISION_IS_A0 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ - (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) -#endif - -#ifndef REVISION_IS_A1 -#define REVISION_IS_A1 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ - (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) -#endif - -#ifndef REVISION_IS_A2 -#define REVISION_IS_A2 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ - (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2)) -#endif - -#ifndef REVISION_IS_B0 -#define REVISION_IS_B0 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ - (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0)) -#endif - -#ifndef REVISION_IS_B1 -#define REVISION_IS_B1 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ - (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1)) -#endif - -//***************************************************************************** -// -// For TivaWare 2.1, we removed all references to Tiva IC codenames from the -// source. To ensure that existing customer code doesn't break as a result -// of this change, make sure that the old definitions are still available at -// least for the time being. -// -//***************************************************************************** -#ifndef DEPRECATED -#define CLASS_IS_BLIZZARD CLASS_IS_TM4C123 -#define CLASS_IS_SNOWFLAKE CLASS_IS_TM4C123 -#endif - -#endif // __HW_TYPES_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_uart.h b/bsp/tm4c129x-dk/libraries/inc/hw_uart.h deleted file mode 100644 index 1c40b79f3db950f3c64f9d9f3fc9228a2642c0a9..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_uart.h +++ /dev/null @@ -1,367 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// The following are defines for the UART register offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // UART Data -#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear -#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear -#define UART_O_FR 0x00000018 // UART Flag -#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register -#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor -#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate - // Divisor -#define UART_O_LCRH 0x0000002C // UART Line Control -#define UART_O_CTL 0x00000030 // UART Control -#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select -#define UART_O_IM 0x00000038 // UART Interrupt Mask -#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status -#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status -#define UART_O_ICR 0x00000044 // UART Interrupt Clear -#define UART_O_DMACTL 0x00000048 // UART DMA Control -#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address -#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask -#define UART_O_PP 0x00000FC0 // UART Peripheral Properties -#define UART_O_CC 0x00000FC8 // UART Clock Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DR register. -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // UART Overrun Error -#define UART_DR_BE 0x00000400 // UART Break Error -#define UART_DR_PE 0x00000200 // UART Parity Error -#define UART_DR_FE 0x00000100 // UART Framing Error -#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received -#define UART_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RSR register. -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // UART Overrun Error -#define UART_RSR_BE 0x00000004 // UART Break Error -#define UART_RSR_PE 0x00000002 // UART Parity Error -#define UART_RSR_FE 0x00000001 // UART Framing Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ECR register. -// -//***************************************************************************** -#define UART_ECR_DATA_M 0x000000FF // Error Clear -#define UART_ECR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FR register. -// -//***************************************************************************** -#define UART_FR_RI 0x00000100 // Ring Indicator -#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty -#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full -#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full -#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy -#define UART_FR_DCD 0x00000004 // Data Carrier Detect -#define UART_FR_DSR 0x00000002 // Data Set Ready -#define UART_FR_CTS 0x00000001 // Clear To Send - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ILPR register. -// -//***************************************************************************** -#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor -#define UART_ILPR_ILPDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IBRD register. -// -//***************************************************************************** -#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor -#define UART_IBRD_DIVINT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FBRD register. -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor -#define UART_FBRD_DIVFRAC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCRH register. -// -//***************************************************************************** -#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length -#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) -#define UART_LCRH_WLEN_6 0x00000020 // 6 bits -#define UART_LCRH_WLEN_7 0x00000040 // 7 bits -#define UART_LCRH_WLEN_8 0x00000060 // 8 bits -#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs -#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select -#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select -#define UART_LCRH_PEN 0x00000002 // UART Parity Enable -#define UART_LCRH_BRK 0x00000001 // UART Send Break - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CTL register. -// -//***************************************************************************** -#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send -#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send -#define UART_CTL_RTS 0x00000800 // Request to Send -#define UART_CTL_DTR 0x00000400 // Data Terminal Ready -#define UART_CTL_RXE 0x00000200 // UART Receive Enable -#define UART_CTL_TXE 0x00000100 // UART Transmit Enable -#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable -#define UART_CTL_HSE 0x00000020 // High-Speed Enable -#define UART_CTL_EOT 0x00000010 // End of Transmission -#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support -#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode -#define UART_CTL_SIREN 0x00000002 // UART SIR Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IFLS register. -// -//***************************************************************************** -#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO - // Level Select -#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full -#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full -#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) -#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full -#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full -#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO - // Level Select -#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full -#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full -#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) -#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full -#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IM register. -// -//***************************************************************************** -#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask -#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask -#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask -#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt - // Mask -#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt - // Mask -#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt - // Mask -#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt - // Mask -#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask -#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem - // Interrupt Mask -#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Mask -#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem - // Interrupt Mask -#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem - // Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RIS register. -// -//***************************************************************************** -#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt - // Status -#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status -#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status -#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw - // Interrupt Status -#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt - // Status -#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt - // Status -#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt - // Status -#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt - // Status -#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw - // Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt - // Status -#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt - // Status -#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw - // Interrupt Status -#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem - // Raw Interrupt Status -#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw - // Interrupt Status -#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_MIS register. -// -//***************************************************************************** -#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt - // Status -#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt - // Status -#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt - // Status -#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked - // Interrupt Status -#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked - // Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked - // Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked - // Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked - // Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked - // Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt - // Status -#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt - // Status -#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked - // Interrupt Status -#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem - // Masked Interrupt Status -#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked - // Interrupt Status -#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ICR register. -// -//***************************************************************************** -#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear -#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear -#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear -#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt - // Clear -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear -#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem - // Interrupt Clear -#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Clear -#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem - // Interrupt Clear -#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem - // Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DMACTL register. -// -//***************************************************************************** -#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error -#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_9BITADDR -// register. -// -//***************************************************************************** -#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode -#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode -#define UART_9BITADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_9BITAMASK -// register. -// -//***************************************************************************** -#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode -#define UART_9BITAMASK_MASK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_PP register. -// -//***************************************************************************** -#define UART_PP_MSE 0x00000008 // Modem Support Extended -#define UART_PP_MS 0x00000004 // Modem Support -#define UART_PP_NB 0x00000002 // 9-Bit Support -#define UART_PP_SC 0x00000001 // Smart Card Support - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CC register. -// -//***************************************************************************** -#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source -#define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock - // source and divisor factor) -#define UART_CC_CS_PIOSC 0x00000005 // PIOSC - -#endif // __HW_UART_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_udma.h b/bsp/tm4c129x-dk/libraries/inc/hw_udma.h deleted file mode 100644 index 1d52b0090194e2600649a724fd3c3779e0acb2e7..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_udma.h +++ /dev/null @@ -1,414 +0,0 @@ -//***************************************************************************** -// -// hw_udma.h - Macros for use in accessing the UDMA registers. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_UDMA_H__ -#define __HW_UDMA_H__ - -//***************************************************************************** -// -// The following are defines for the Micro Direct Memory Access register -// addresses. -// -//***************************************************************************** -#define UDMA_STAT 0x400FF000 // DMA Status -#define UDMA_CFG 0x400FF004 // DMA Configuration -#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer -#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control - // Base Pointer -#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request - // Status -#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request -#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set -#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear -#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set -#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear -#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set -#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear -#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate - // Set -#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate - // Clear -#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set -#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear -#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear -#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment -#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status -#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0 -#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1 -#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2 -#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_STAT register. -// -//***************************************************************************** -#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 -#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status -#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle -#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data -#define UDMA_STAT_STATE_RD_SRCENDP \ - 0x00000020 // Reading source end pointer -#define UDMA_STAT_STATE_RD_DSTENDP \ - 0x00000030 // Reading destination end pointer -#define UDMA_STAT_STATE_RD_SRCDAT \ - 0x00000040 // Reading source data -#define UDMA_STAT_STATE_WR_DSTDAT \ - 0x00000050 // Writing destination data -#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to - // clear -#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data -#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled -#define UDMA_STAT_STATE_DONE 0x00000090 // Done -#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined -#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status -#define UDMA_STAT_DMACHANS_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CFG register. -// -//***************************************************************************** -#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CTLBASE register. -// -//***************************************************************************** -#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address -#define UDMA_CTLBASE_ADDR_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTBASE register. -// -//***************************************************************************** -#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address - // Pointer -#define UDMA_ALTBASE_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_WAITSTAT register. -// -//***************************************************************************** -#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_SWREQ register. -// -//***************************************************************************** -#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_USEBURSTSET -// register. -// -//***************************************************************************** -#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_USEBURSTCLR -// register. -// -//***************************************************************************** -#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_REQMASKSET -// register. -// -//***************************************************************************** -#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_REQMASKCLR -// register. -// -//***************************************************************************** -#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ENASET register. -// -//***************************************************************************** -#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ENACLR register. -// -//***************************************************************************** -#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTSET register. -// -//***************************************************************************** -#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTCLR register. -// -//***************************************************************************** -#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_PRIOSET register. -// -//***************************************************************************** -#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_PRIOCLR register. -// -//***************************************************************************** -#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ERRCLR register. -// -//***************************************************************************** -#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHASGN register. -// -//***************************************************************************** -#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select -#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel - // assignment -#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel - // assignment - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHIS register. -// -//***************************************************************************** -#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP0 register. -// -//***************************************************************************** -#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select -#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select -#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select -#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select -#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select -#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select -#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select -#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select -#define UDMA_CHMAP0_CH7SEL_S 28 -#define UDMA_CHMAP0_CH6SEL_S 24 -#define UDMA_CHMAP0_CH5SEL_S 20 -#define UDMA_CHMAP0_CH4SEL_S 16 -#define UDMA_CHMAP0_CH3SEL_S 12 -#define UDMA_CHMAP0_CH2SEL_S 8 -#define UDMA_CHMAP0_CH1SEL_S 4 -#define UDMA_CHMAP0_CH0SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP1 register. -// -//***************************************************************************** -#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select -#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select -#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select -#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select -#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select -#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select -#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select -#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select -#define UDMA_CHMAP1_CH15SEL_S 28 -#define UDMA_CHMAP1_CH14SEL_S 24 -#define UDMA_CHMAP1_CH13SEL_S 20 -#define UDMA_CHMAP1_CH12SEL_S 16 -#define UDMA_CHMAP1_CH11SEL_S 12 -#define UDMA_CHMAP1_CH10SEL_S 8 -#define UDMA_CHMAP1_CH9SEL_S 4 -#define UDMA_CHMAP1_CH8SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP2 register. -// -//***************************************************************************** -#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select -#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select -#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select -#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select -#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select -#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select -#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select -#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select -#define UDMA_CHMAP2_CH23SEL_S 28 -#define UDMA_CHMAP2_CH22SEL_S 24 -#define UDMA_CHMAP2_CH21SEL_S 20 -#define UDMA_CHMAP2_CH20SEL_S 16 -#define UDMA_CHMAP2_CH19SEL_S 12 -#define UDMA_CHMAP2_CH18SEL_S 8 -#define UDMA_CHMAP2_CH17SEL_S 4 -#define UDMA_CHMAP2_CH16SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP3 register. -// -//***************************************************************************** -#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select -#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select -#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select -#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select -#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select -#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select -#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select -#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select -#define UDMA_CHMAP3_CH31SEL_S 28 -#define UDMA_CHMAP3_CH30SEL_S 24 -#define UDMA_CHMAP3_CH29SEL_S 20 -#define UDMA_CHMAP3_CH28SEL_S 16 -#define UDMA_CHMAP3_CH27SEL_S 12 -#define UDMA_CHMAP3_CH26SEL_S 8 -#define UDMA_CHMAP3_CH25SEL_S 4 -#define UDMA_CHMAP3_CH24SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the Micro Direct Memory Access (uDMA) offsets. -// -//***************************************************************************** -#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End - // Pointer -#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address - // End Pointer -#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_SRCENDP register. -// -//***************************************************************************** -#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer -#define UDMA_SRCENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_DSTENDP register. -// -//***************************************************************************** -#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer -#define UDMA_DSTENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHCTL register. -// -//***************************************************************************** -#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment -#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word -#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word -#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment -#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word -#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment -#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word -#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word -#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment -#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word -#define UDMA_CHCTL_DSTPROT0 0x00200000 // Destination Privilege Access -#define UDMA_CHCTL_SRCPROT0 0x00040000 // Source Privilege Access -#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers -#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst -#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_CHCTL_XFERMODE_STOP \ - 0x00000000 // Stop -#define UDMA_CHCTL_XFERMODE_BASIC \ - 0x00000001 // Basic -#define UDMA_CHCTL_XFERMODE_AUTO \ - 0x00000002 // Auto-Request -#define UDMA_CHCTL_XFERMODE_PINGPONG \ - 0x00000003 // Ping-Pong -#define UDMA_CHCTL_XFERMODE_MEM_SG \ - 0x00000004 // Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_MEM_SGA \ - 0x00000005 // Alternate Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SG \ - 0x00000006 // Peripheral Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SGA \ - 0x00000007 // Alternate Peripheral - // Scatter-Gather -#define UDMA_CHCTL_XFERSIZE_S 4 - -#endif // __HW_UDMA_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_usb.h b/bsp/tm4c129x-dk/libraries/inc/hw_usb.h deleted file mode 100644 index 7aa3b50a29fea792771f981197a5b2f8b126099f..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_usb.h +++ /dev/null @@ -1,3032 +0,0 @@ -//***************************************************************************** -// -// hw_usb.h - Macros for use in accessing the USB registers. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_USB_H__ -#define __HW_USB_H__ - -//***************************************************************************** -// -// The following are defines for the Univeral Serial Bus register offsets. -// -//***************************************************************************** -#define USB_O_FADDR 0x00000000 // USB Device Functional Address -#define USB_O_POWER 0x00000001 // USB Power -#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status -#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status -#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable -#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable -#define USB_O_IS 0x0000000A // USB General Interrupt Status -#define USB_O_IE 0x0000000B // USB Interrupt Enable -#define USB_O_FRAME 0x0000000C // USB Frame Value -#define USB_O_EPIDX 0x0000000E // USB Endpoint Index -#define USB_O_TEST 0x0000000F // USB Test Mode -#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 -#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 -#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 -#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 -#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4 -#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 -#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 -#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 -#define USB_O_DEVCTL 0x00000060 // USB Device Control -#define USB_O_CCONF 0x00000061 // USB Common Configuration -#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing -#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing -#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address -#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address -#define USB_O_ULPIVBUSCTL 0x00000070 // USB ULPI VBUS Control -#define USB_O_ULPIREGDATA 0x00000074 // USB ULPI Register Data -#define USB_O_ULPIREGADDR 0x00000075 // USB ULPI Register Address -#define USB_O_ULPIREGCTL 0x00000076 // USB ULPI Register Control -#define USB_O_EPINFO 0x00000078 // USB Endpoint Information -#define USB_O_RAMINFO 0x00000079 // USB RAM Information -#define USB_O_CONTIM 0x0000007A // USB Connect Timing -#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing -#define USB_O_HSEOF 0x0000007C // USB High-Speed Last Transaction - // to End of Frame Timing -#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction - // to End of Frame Timing -#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction - // to End of Frame Timing -#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address - // Endpoint 0 -#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address - // Endpoint 0 -#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 -#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address - // Endpoint 1 -#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address - // Endpoint 1 -#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 -#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address - // Endpoint 1 -#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint - // 1 -#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 -#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address - // Endpoint 2 -#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address - // Endpoint 2 -#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 -#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address - // Endpoint 2 -#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint - // 2 -#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 -#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address - // Endpoint 3 -#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address - // Endpoint 3 -#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 -#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address - // Endpoint 3 -#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint - // 3 -#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 -#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address - // Endpoint 4 -#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address - // Endpoint 4 -#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4 -#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address - // Endpoint 4 -#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint - // 4 -#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4 -#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address - // Endpoint 5 -#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address - // Endpoint 5 -#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5 -#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address - // Endpoint 5 -#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint - // 5 -#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5 -#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address - // Endpoint 6 -#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address - // Endpoint 6 -#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6 -#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address - // Endpoint 6 -#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint - // 6 -#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6 -#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address - // Endpoint 7 -#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address - // Endpoint 7 -#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7 -#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address - // Endpoint 7 -#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint - // 7 -#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 -#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint - // 0 Low -#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint - // 0 High -#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint - // 0 -#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 -#define USB_O_NAKLMT 0x0000010B // USB NAK Limit -#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data - // Endpoint 1 -#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status - // Endpoint 1 Low -#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status - // Endpoint 1 High -#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data - // Endpoint 1 -#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status - // Endpoint 1 Low -#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status - // Endpoint 1 High -#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint - // 1 -#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type - // Endpoint 1 -#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval - // Endpoint 1 -#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type - // Endpoint 1 -#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling - // Interval Endpoint 1 -#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data - // Endpoint 2 -#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status - // Endpoint 2 Low -#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status - // Endpoint 2 High -#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data - // Endpoint 2 -#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status - // Endpoint 2 Low -#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status - // Endpoint 2 High -#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint - // 2 -#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type - // Endpoint 2 -#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval - // Endpoint 2 -#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type - // Endpoint 2 -#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling - // Interval Endpoint 2 -#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data - // Endpoint 3 -#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status - // Endpoint 3 Low -#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status - // Endpoint 3 High -#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data - // Endpoint 3 -#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status - // Endpoint 3 Low -#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status - // Endpoint 3 High -#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint - // 3 -#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type - // Endpoint 3 -#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval - // Endpoint 3 -#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type - // Endpoint 3 -#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling - // Interval Endpoint 3 -#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data - // Endpoint 4 -#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status - // Endpoint 4 Low -#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status - // Endpoint 4 High -#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data - // Endpoint 4 -#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status - // Endpoint 4 Low -#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status - // Endpoint 4 High -#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint - // 4 -#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type - // Endpoint 4 -#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval - // Endpoint 4 -#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type - // Endpoint 4 -#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling - // Interval Endpoint 4 -#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data - // Endpoint 5 -#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status - // Endpoint 5 Low -#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status - // Endpoint 5 High -#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data - // Endpoint 5 -#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status - // Endpoint 5 Low -#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status - // Endpoint 5 High -#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint - // 5 -#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type - // Endpoint 5 -#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval - // Endpoint 5 -#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type - // Endpoint 5 -#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling - // Interval Endpoint 5 -#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data - // Endpoint 6 -#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status - // Endpoint 6 Low -#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status - // Endpoint 6 High -#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data - // Endpoint 6 -#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status - // Endpoint 6 Low -#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status - // Endpoint 6 High -#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint - // 6 -#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type - // Endpoint 6 -#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval - // Endpoint 6 -#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type - // Endpoint 6 -#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling - // Interval Endpoint 6 -#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data - // Endpoint 7 -#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status - // Endpoint 7 Low -#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status - // Endpoint 7 High -#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data - // Endpoint 7 -#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status - // Endpoint 7 Low -#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status - // Endpoint 7 High -#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint - // 7 -#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type - // Endpoint 7 -#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval - // Endpoint 7 -#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type - // Endpoint 7 -#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling - // Interval Endpoint 7 -#define USB_O_DMAINTR 0x00000200 // USB DMA Interrupt -#define USB_O_DMACTL0 0x00000204 // USB DMA Control 0 -#define USB_O_DMAADDR0 0x00000208 // USB DMA Address 0 -#define USB_O_DMACOUNT0 0x0000020C // USB DMA Count 0 -#define USB_O_DMACTL1 0x00000214 // USB DMA Control 1 -#define USB_O_DMAADDR1 0x00000218 // USB DMA Address 1 -#define USB_O_DMACOUNT1 0x0000021C // USB DMA Count 1 -#define USB_O_DMACTL2 0x00000224 // USB DMA Control 2 -#define USB_O_DMAADDR2 0x00000228 // USB DMA Address 2 -#define USB_O_DMACOUNT2 0x0000022C // USB DMA Count 2 -#define USB_O_DMACTL3 0x00000234 // USB DMA Control 3 -#define USB_O_DMAADDR3 0x00000238 // USB DMA Address 3 -#define USB_O_DMACOUNT3 0x0000023C // USB DMA Count 3 -#define USB_O_DMACTL4 0x00000244 // USB DMA Control 4 -#define USB_O_DMAADDR4 0x00000248 // USB DMA Address 4 -#define USB_O_DMACOUNT4 0x0000024C // USB DMA Count 4 -#define USB_O_DMACTL5 0x00000254 // USB DMA Control 5 -#define USB_O_DMAADDR5 0x00000258 // USB DMA Address 5 -#define USB_O_DMACOUNT5 0x0000025C // USB DMA Count 5 -#define USB_O_DMACTL6 0x00000264 // USB DMA Control 6 -#define USB_O_DMAADDR6 0x00000268 // USB DMA Address 6 -#define USB_O_DMACOUNT6 0x0000026C // USB DMA Count 6 -#define USB_O_DMACTL7 0x00000274 // USB DMA Control 7 -#define USB_O_DMAADDR7 0x00000278 // USB DMA Address 7 -#define USB_O_DMACOUNT7 0x0000027C // USB DMA Count 7 -#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in - // Block Transfer Endpoint 1 -#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in - // Block Transfer Endpoint 2 -#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in - // Block Transfer Endpoint 3 -#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in - // Block Transfer Endpoint 4 -#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in - // Block Transfer Endpoint 5 -#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in - // Block Transfer Endpoint 6 -#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in - // Block Transfer Endpoint 7 -#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer - // Disable -#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet - // Buffer Disable -#define USB_O_CTO 0x00000344 // USB Chirp Timeout -#define USB_O_HHSRTN 0x00000346 // USB High Speed to UTM Operating - // Delay -#define USB_O_HSBT 0x00000348 // USB High Speed Time-out Adder -#define USB_O_LPMATTR 0x00000360 // USB LPM Attributes -#define USB_O_LPMCNTRL 0x00000362 // USB LPM Control -#define USB_O_LPMIM 0x00000363 // USB LPM Interrupt Mask -#define USB_O_LPMRIS 0x00000364 // USB LPM Raw Interrupt Status -#define USB_O_LPMFADDR 0x00000365 // USB LPM Function Address -#define USB_O_EPC 0x00000400 // USB External Power Control -#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw - // Interrupt Status -#define USB_O_EPCIM 0x00000408 // USB External Power Control - // Interrupt Mask -#define USB_O_EPCISC 0x0000040C // USB External Power Control - // Interrupt Status and Clear -#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt - // Status -#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask -#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt - // Status and Clear -#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and - // Status -#define USB_O_VDC 0x00000430 // USB VBUS Droop Control -#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw - // Interrupt Status -#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt - // Mask -#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt - // Status and Clear -#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw - // Interrupt Status -#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt - // Mask -#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt - // Status and Clear -#define USB_O_DMASEL 0x00000450 // USB DMA Select -#define USB_O_PP 0x00000FC0 // USB Peripheral Properties -#define USB_O_PC 0x00000FC4 // USB Peripheral Configuration -#define USB_O_CC 0x00000FC8 // USB Clock Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FADDR register. -// -//***************************************************************************** -#define USB_FADDR_M 0x0000007F // Function Address -#define USB_FADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_POWER register. -// -//***************************************************************************** -#define USB_POWER_ISOUP 0x00000080 // Isochronous Update -#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect -#define USB_POWER_HSENAB 0x00000020 // High Speed Enable -#define USB_POWER_HSMODE 0x00000010 // High Speed Enable -#define USB_POWER_RESET 0x00000008 // RESET Signaling -#define USB_POWER_RESUME 0x00000004 // RESUME Signaling -#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode -#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIS register. -// -//***************************************************************************** -#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt -#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt -#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt -#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt -#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt -#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt -#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt -#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIS register. -// -//***************************************************************************** -#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt -#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt -#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt -#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt -#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt -#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt -#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIE register. -// -//***************************************************************************** -#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable -#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable -#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable -#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable -#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable -#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable -#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable -#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIE register. -// -//***************************************************************************** -#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable -#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable -#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable -#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable -#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable -#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable -#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IS register. -// -//***************************************************************************** -#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) -#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) -#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) -#define USB_IS_CONN 0x00000010 // Session Connect -#define USB_IS_SOF 0x00000008 // Start of Frame -#define USB_IS_BABBLE 0x00000004 // Babble Detected -#define USB_IS_RESET 0x00000004 // RESET Signaling Detected -#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected -#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IE register. -// -//***************************************************************************** -#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG - // only) -#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG - // only) -#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt -#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt -#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt -#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt -#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt -#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt -#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FRAME register. -// -//***************************************************************************** -#define USB_FRAME_M 0x000007FF // Frame Number -#define USB_FRAME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPIDX register. -// -//***************************************************************************** -#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index -#define USB_EPIDX_EPIDX_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TEST register. -// -//***************************************************************************** -#define USB_TEST_FORCEH 0x00000080 // Force Host Mode -#define USB_TEST_FIFOACC 0x00000040 // FIFO Access -#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode -#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode -#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable -#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable -#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable -#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO0 register. -// -//***************************************************************************** -#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO0_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO1 register. -// -//***************************************************************************** -#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO1_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO2 register. -// -//***************************************************************************** -#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO2_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO3 register. -// -//***************************************************************************** -#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO3_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO4 register. -// -//***************************************************************************** -#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO4_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO5 register. -// -//***************************************************************************** -#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO5_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO6 register. -// -//***************************************************************************** -#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO6_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO7 register. -// -//***************************************************************************** -#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO7_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DEVCTL register. -// -//***************************************************************************** -#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) -#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected -#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected -#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) -#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd -#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid -#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid -#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid -#define USB_DEVCTL_HOST 0x00000004 // Host Mode -#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) -#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CCONF register. -// -//***************************************************************************** -#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable -#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. -// -//***************************************************************************** -#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. -// -//***************************************************************************** -#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFIFOADD -// register. -// -//***************************************************************************** -#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address -#define USB_TXFIFOADD_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFIFOADD -// register. -// -//***************************************************************************** -#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address -#define USB_RXFIFOADD_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL -// register. -// -//***************************************************************************** -#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ - 0x00000002 // Use External VBUS Indicator -#define USB_ULPIVBUSCTL_USEEXTVBUS \ - 0x00000001 // Use External VBUS - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGDATA -// register. -// -//***************************************************************************** -#define USB_ULPIREGDATA_REGDATA_M \ - 0x000000FF // Register Data -#define USB_ULPIREGDATA_REGDATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGADDR -// register. -// -//***************************************************************************** -#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address -#define USB_ULPIREGADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGCTL -// register. -// -//***************************************************************************** -#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control -#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete -#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPINFO register. -// -//***************************************************************************** -#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints -#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints -#define USB_EPINFO_RXEP_S 4 -#define USB_EPINFO_TXEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RAMINFO register. -// -//***************************************************************************** -#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels -#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width -#define USB_RAMINFO_DMACHAN_S 4 -#define USB_RAMINFO_RAMBITS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CONTIM register. -// -//***************************************************************************** -#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait -#define USB_CONTIM_WTID_M 0x0000000F // Wait ID -#define USB_CONTIM_WTCON_S 4 -#define USB_CONTIM_WTID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VPLEN register. -// -//***************************************************************************** -#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length -#define USB_VPLEN_VPLEN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HSEOF register. -// -//***************************************************************************** -#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap -#define USB_HSEOF_HSEOFG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FSEOF register. -// -//***************************************************************************** -#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap -#define USB_FSEOF_FSEOFG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LSEOF register. -// -//***************************************************************************** -#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap -#define USB_LSEOF_LSEOFG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR0 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT0 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT0_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT7_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT7_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CSRL0 register. -// -//***************************************************************************** -#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout -#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear -#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet -#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear -#define USB_CSRL0_REQPKT 0x00000020 // Request Packet -#define USB_CSRL0_STALL 0x00000020 // Send Stall -#define USB_CSRL0_SETEND 0x00000010 // Setup End -#define USB_CSRL0_ERROR 0x00000010 // Error -#define USB_CSRL0_DATAEND 0x00000008 // Data End -#define USB_CSRL0_SETUP 0x00000008 // Setup Packet -#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled -#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready -#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CSRH0 register. -// -//***************************************************************************** -#define USB_CSRH0_DISPING 0x00000008 // PING Disable -#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_CSRH0_DT 0x00000002 // Data Toggle -#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_COUNT0 register. -// -//***************************************************************************** -#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count -#define USB_COUNT0_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TYPE0 register. -// -//***************************************************************************** -#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed -#define USB_TYPE0_SPEED_HIGH 0x00000040 // High -#define USB_TYPE0_SPEED_FULL 0x00000080 // Full -#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_NAKLMT register. -// -//***************************************************************************** -#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit -#define USB_NAKLMT_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP1 register. -// -//***************************************************************************** -#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP1_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL1 register. -// -//***************************************************************************** -#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL1_STALL 0x00000010 // Send STALL -#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL1_ERROR 0x00000004 // Error -#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH1 register. -// -//***************************************************************************** -#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH1_MODE 0x00000020 // Mode -#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH1_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP1 register. -// -//***************************************************************************** -#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP1_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL1 register. -// -//***************************************************************************** -#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL1_STALL 0x00000020 // Send STALL -#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL1_OVER 0x00000004 // Overrun -#define USB_RXCSRL1_ERROR 0x00000004 // Error -#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH1 register. -// -//***************************************************************************** -#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH1_DT 0x00000002 // Data Toggle -#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. -// -//***************************************************************************** -#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT1_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE1 register. -// -//***************************************************************************** -#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE1_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL1 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL1_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL1_TXPOLL_S \ - 0 -#define USB_TXINTERVAL1_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE1 register. -// -//***************************************************************************** -#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE1_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL1 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL1_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL1_TXPOLL_S \ - 0 -#define USB_RXINTERVAL1_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP2 register. -// -//***************************************************************************** -#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL2 register. -// -//***************************************************************************** -#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL2_STALL 0x00000010 // Send STALL -#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL2_ERROR 0x00000004 // Error -#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH2 register. -// -//***************************************************************************** -#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH2_MODE 0x00000020 // Mode -#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH2_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP2 register. -// -//***************************************************************************** -#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL2 register. -// -//***************************************************************************** -#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL2_STALL 0x00000020 // Send STALL -#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL2_ERROR 0x00000004 // Error -#define USB_RXCSRL2_OVER 0x00000004 // Overrun -#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH2 register. -// -//***************************************************************************** -#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH2_DT 0x00000002 // Data Toggle -#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. -// -//***************************************************************************** -#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT2_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE2 register. -// -//***************************************************************************** -#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL2_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL2_NAKLMT_S \ - 0 -#define USB_TXINTERVAL2_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE2 register. -// -//***************************************************************************** -#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL2_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL2_TXPOLL_S \ - 0 -#define USB_RXINTERVAL2_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP3 register. -// -//***************************************************************************** -#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL3 register. -// -//***************************************************************************** -#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL3_STALL 0x00000010 // Send STALL -#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL3_ERROR 0x00000004 // Error -#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH3 register. -// -//***************************************************************************** -#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH3_MODE 0x00000020 // Mode -#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH3_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP3 register. -// -//***************************************************************************** -#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL3 register. -// -//***************************************************************************** -#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL3_STALL 0x00000020 // Send STALL -#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL3_ERROR 0x00000004 // Error -#define USB_RXCSRL3_OVER 0x00000004 // Overrun -#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH3 register. -// -//***************************************************************************** -#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH3_DT 0x00000002 // Data Toggle -#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. -// -//***************************************************************************** -#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT3_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE3 register. -// -//***************************************************************************** -#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL3_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL3_TXPOLL_S \ - 0 -#define USB_TXINTERVAL3_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE3 register. -// -//***************************************************************************** -#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL3_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL3_TXPOLL_S \ - 0 -#define USB_RXINTERVAL3_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP4 register. -// -//***************************************************************************** -#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL4 register. -// -//***************************************************************************** -#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL4_STALL 0x00000010 // Send STALL -#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL4_ERROR 0x00000004 // Error -#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH4 register. -// -//***************************************************************************** -#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH4_MODE 0x00000020 // Mode -#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH4_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP4 register. -// -//***************************************************************************** -#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL4 register. -// -//***************************************************************************** -#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL4_STALL 0x00000020 // Send STALL -#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL4_OVER 0x00000004 // Overrun -#define USB_RXCSRL4_ERROR 0x00000004 // Error -#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH4 register. -// -//***************************************************************************** -#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH4_DT 0x00000002 // Data Toggle -#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. -// -//***************************************************************************** -#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE4 register. -// -//***************************************************************************** -#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL4_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL4_NAKLMT_S \ - 0 -#define USB_TXINTERVAL4_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE4 register. -// -//***************************************************************************** -#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL4_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL4_NAKLMT_S \ - 0 -#define USB_RXINTERVAL4_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP5 register. -// -//***************************************************************************** -#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL5 register. -// -//***************************************************************************** -#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL5_STALL 0x00000010 // Send STALL -#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL5_ERROR 0x00000004 // Error -#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH5 register. -// -//***************************************************************************** -#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH5_MODE 0x00000020 // Mode -#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH5_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP5 register. -// -//***************************************************************************** -#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL5 register. -// -//***************************************************************************** -#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL5_STALL 0x00000020 // Send STALL -#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL5_ERROR 0x00000004 // Error -#define USB_RXCSRL5_OVER 0x00000004 // Overrun -#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH5 register. -// -//***************************************************************************** -#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH5_DT 0x00000002 // Data Toggle -#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. -// -//***************************************************************************** -#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT5_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE5 register. -// -//***************************************************************************** -#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE5_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL5 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL5_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL5_NAKLMT_S \ - 0 -#define USB_TXINTERVAL5_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE5 register. -// -//***************************************************************************** -#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE5_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL5 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL5_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL5_TXPOLL_S \ - 0 -#define USB_RXINTERVAL5_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP6 register. -// -//***************************************************************************** -#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL6 register. -// -//***************************************************************************** -#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL6_STALL 0x00000010 // Send STALL -#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL6_ERROR 0x00000004 // Error -#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH6 register. -// -//***************************************************************************** -#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH6_MODE 0x00000020 // Mode -#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH6_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP6 register. -// -//***************************************************************************** -#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL6 register. -// -//***************************************************************************** -#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL6_STALL 0x00000020 // Send STALL -#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL6_ERROR 0x00000004 // Error -#define USB_RXCSRL6_OVER 0x00000004 // Overrun -#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH6 register. -// -//***************************************************************************** -#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH6_DT 0x00000002 // Data Toggle -#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. -// -//***************************************************************************** -#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE6 register. -// -//***************************************************************************** -#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL6_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL6_TXPOLL_S \ - 0 -#define USB_TXINTERVAL6_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE6 register. -// -//***************************************************************************** -#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL6_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL6_NAKLMT_S \ - 0 -#define USB_RXINTERVAL6_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP7 register. -// -//***************************************************************************** -#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL7 register. -// -//***************************************************************************** -#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL7_STALL 0x00000010 // Send STALL -#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL7_ERROR 0x00000004 // Error -#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH7 register. -// -//***************************************************************************** -#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH7_MODE 0x00000020 // Mode -#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH7_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP7 register. -// -//***************************************************************************** -#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL7 register. -// -//***************************************************************************** -#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL7_STALL 0x00000020 // Send STALL -#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL7_ERROR 0x00000004 // Error -#define USB_RXCSRL7_OVER 0x00000004 // Overrun -#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH7 register. -// -//***************************************************************************** -#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH7_DT 0x00000002 // Data Toggle -#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. -// -//***************************************************************************** -#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE7 register. -// -//***************************************************************************** -#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL7_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL7_NAKLMT_S \ - 0 -#define USB_TXINTERVAL7_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE7 register. -// -//***************************************************************************** -#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL7_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL7_NAKLMT_S \ - 0 -#define USB_RXINTERVAL7_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAINTR register. -// -//***************************************************************************** -#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt -#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt -#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt -#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt -#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt -#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt -#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt -#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL0 register. -// -//***************************************************************************** -#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL0_DIR 0x00000002 // DMA Direction -#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL0_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR0 register. -// -//***************************************************************************** -#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR0_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT0 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT0_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL1 register. -// -//***************************************************************************** -#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL1_DIR 0x00000002 // DMA Direction -#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL1_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR1 register. -// -//***************************************************************************** -#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR1_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT1 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT1_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL2 register. -// -//***************************************************************************** -#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL2_DIR 0x00000002 // DMA Direction -#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL2_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR2 register. -// -//***************************************************************************** -#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR2_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT2 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT2_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL3 register. -// -//***************************************************************************** -#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL3_DIR 0x00000002 // DMA Direction -#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL3_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR3 register. -// -//***************************************************************************** -#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR3_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT3 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT3_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL4 register. -// -//***************************************************************************** -#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL4_DIR 0x00000002 // DMA Direction -#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL4_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR4 register. -// -//***************************************************************************** -#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR4_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT4 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT4_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL5 register. -// -//***************************************************************************** -#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL5_DIR 0x00000002 // DMA Direction -#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL5_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR5 register. -// -//***************************************************************************** -#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR5_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT5 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT5_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL6 register. -// -//***************************************************************************** -#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL6_DIR 0x00000002 // DMA Direction -#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL6_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR6 register. -// -//***************************************************************************** -#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR6_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT6 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT6_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL7 register. -// -//***************************************************************************** -#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL7_DIR 0x00000002 // DMA Direction -#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL7_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR7 register. -// -//***************************************************************************** -#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR7_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT7 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT7_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT1_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT2_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT3_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT5_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer - // Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer - // Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CTO register. -// -//***************************************************************************** -#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value -#define USB_CTO_CCTV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HHSRTN register. -// -//***************************************************************************** -#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating - // Delay -#define USB_HHSRTN_HHSRTN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HSBT register. -// -//***************************************************************************** -#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder -#define USB_HSBT_HSBT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMATTR register. -// -//***************************************************************************** -#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint -#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake -#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration -#define USB_LPMATTR_LS_M 0x0000000F // Link State -#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) -#define USB_LPMATTR_ENDPT_S 12 -#define USB_LPMATTR_HIRD_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMCNTRL register. -// -//***************************************************************************** -#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK -#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable -#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions - // are not supported. In this case, - // the USB does not respond to LPM - // transactions and LPM - // transactions cause a timeout -#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but - // extended transactions are - // supported. In this case, the USB - // does respond to an LPM - // transaction with a STALL -#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended - // transactions. In this case, the - // USB responds with a NYET or an - // ACK as determined by the value - // of TXLPM and other conditions -#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume -#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMIM register. -// -//***************************************************************************** -#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask -#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask -#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask -#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask -#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask -#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMRIS register. -// -//***************************************************************************** -#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status -#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status -#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status -#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status -#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status -#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMFADDR register. -// -//***************************************************************************** -#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address -#define USB_LPMFADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPC register. -// -//***************************************************************************** -#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action -#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged -#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate -#define USB_EPC_PFLTACT_LOW 0x00000200 // Low -#define USB_EPC_PFLTACT_HIGH 0x00000300 // High -#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable -#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense -#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable -#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable -#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable - // Configuration -#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low -#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High -#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low - // (OTG only) -#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High - // (OTG only) - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCRIS register. -// -//***************************************************************************** -#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCIM register. -// -//***************************************************************************** -#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCISC register. -// -//***************************************************************************** -#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRRIS register. -// -//***************************************************************************** -#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRIM register. -// -//***************************************************************************** -#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRISC register. -// -//***************************************************************************** -#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_GPCS register. -// -//***************************************************************************** -#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode -#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin -#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low -#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high -#define USB_GPCS_DEVMOD_HOSTVBUS \ - 0x00000004 // Use USB0VBUS and force USB0ID - // low -#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID - // high -#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode -#define USB_GPCS_DEVMOD 0x00000001 // Device Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDC register. -// -//***************************************************************************** -#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCRIS register. -// -//***************************************************************************** -#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCIM register. -// -//***************************************************************************** -#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCISC register. -// -//***************************************************************************** -#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IDVRIS register. -// -//***************************************************************************** -#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IDVIM register. -// -//***************************************************************************** -#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IDVISC register. -// -//***************************************************************************** -#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMASEL register. -// -//***************************************************************************** -#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select -#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select -#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select -#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select -#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select -#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select -#define USB_DMASEL_DMACTX_S 20 -#define USB_DMASEL_DMACRX_S 16 -#define USB_DMASEL_DMABTX_S 12 -#define USB_DMASEL_DMABRX_S 8 -#define USB_DMASEL_DMAATX_S 4 -#define USB_DMASEL_DMAARX_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_PP register. -// -//***************************************************************************** -#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count -#define USB_PP_USB_M 0x000000C0 // USB Capability -#define USB_PP_USB_DEVICE 0x00000040 // DEVICE -#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST -#define USB_PP_USB_OTG 0x000000C0 // OTG -#define USB_PP_ULPI 0x00000020 // ULPI Present -#define USB_PP_PHY 0x00000010 // PHY Present -#define USB_PP_TYPE_M 0x0000000F // Controller Type -#define USB_PP_TYPE_0 0x00000000 // The first-generation USB - // controller -#define USB_PP_TYPE_1 0x00000001 // Second-generation USB - // controller.The controller - // implemented in post Icestorm - // devices that use the 3.0 version - // of the Mentor controller -#define USB_PP_ECNT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_PC register. -// -//***************************************************************************** -#define USB_PC_ULPIEN 0x00010000 // ULPI Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CC register. -// -//***************************************************************************** -#define USB_CC_CLKEN 0x00000200 // USB Clock Enable -#define USB_CC_CSD 0x00000100 // Clock Source/Direction -#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor -#define USB_CC_CLKDIV_S 0 - -#endif // __HW_USB_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_watchdog.h b/bsp/tm4c129x-dk/libraries/inc/hw_watchdog.h deleted file mode 100644 index 783b6f07f64c9fb6aa8d82ccc14b1bfe3d9b066d..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_watchdog.h +++ /dev/null @@ -1,122 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following are defines for the Watchdog Timer register offsets. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Watchdog Load -#define WDT_O_VALUE 0x00000004 // Watchdog Value -#define WDT_O_CTL 0x00000008 // Watchdog Control -#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear -#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status -#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status -#define WDT_O_TEST 0x00000418 // Watchdog Test -#define WDT_O_LOCK 0x00000C00 // Watchdog Lock - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOAD register. -// -//***************************************************************************** -#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value -#define WDT_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_VALUE register. -// -//***************************************************************************** -#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value -#define WDT_VALUE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_CTL register. -// -//***************************************************************************** -#define WDT_CTL_WRC 0x80000000 // Write Complete -#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type -#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable -#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_ICR register. -// -//***************************************************************************** -#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear -#define WDT_ICR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_RIS register. -// -//***************************************************************************** -#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_MIS register. -// -//***************************************************************************** -#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock -#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WDT_LOCK_LOCKED 0x00000001 // Locked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -#endif // __HW_WATCHDOG_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/tm4c1294ncpdt.h b/bsp/tm4c129x-dk/libraries/inc/tm4c1294ncpdt.h deleted file mode 100644 index 458eaac3955eee1f6844440cfac411c7f7bf825f..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/inc/tm4c1294ncpdt.h +++ /dev/null @@ -1,15610 +0,0 @@ -//***************************************************************************** -// -// tm4c1294ncpdt.h - TM4C1294NCPDT Register Definitions -// -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __TM4C1294NCPDT_H__ -#define __TM4C1294NCPDT_H__ - -//***************************************************************************** -// -// Interrupt assignments -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 -#define INT_UART1 22 // UART1 -#define INT_SSI0 23 // SSI0 -#define INT_I2C0 24 // I2C0 -#define INT_PWM0_FAULT 25 // PWM Fault -#define INT_PWM0_0 26 // PWM Generator 0 -#define INT_PWM0_1 27 // PWM Generator 1 -#define INT_PWM0_2 28 // PWM Generator 2 -#define INT_QEI0 29 // QEI0 -#define INT_ADC0SS0 30 // ADC0 Sequence 0 -#define INT_ADC0SS1 31 // ADC0 Sequence 1 -#define INT_ADC0SS2 32 // ADC0 Sequence 2 -#define INT_ADC0SS3 33 // ADC0 Sequence 3 -#define INT_WATCHDOG 34 // Watchdog Timers 0 and 1 -#define INT_TIMER0A 35 // 16/32-Bit Timer 0A -#define INT_TIMER0B 36 // 16/32-Bit Timer 0B -#define INT_TIMER1A 37 // 16/32-Bit Timer 1A -#define INT_TIMER1B 38 // 16/32-Bit Timer 1B -#define INT_TIMER2A 39 // 16/32-Bit Timer 2A -#define INT_TIMER2B 40 // 16/32-Bit Timer 2B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control -#define INT_FLASH 45 // Flash Memory Control -#define INT_GPIOF 46 // GPIO Port F -#define INT_GPIOG 47 // GPIO Port G -#define INT_GPIOH 48 // GPIO Port H -#define INT_UART2 49 // UART2 -#define INT_SSI1 50 // SSI1 -#define INT_TIMER3A 51 // 16/32-Bit Timer 3A -#define INT_TIMER3B 52 // 16/32-Bit Timer 3B -#define INT_I2C1 53 // I2C1 -#define INT_CAN0 54 // CAN 0 -#define INT_CAN1 55 // CAN1 -#define INT_EMAC0 56 // Ethernet MAC -#define INT_HIBERNATE 57 // HIB -#define INT_USB0 58 // USB MAC -#define INT_PWM0_3 59 // PWM Generator 3 -#define INT_UDMA 60 // uDMA 0 Software -#define INT_UDMAERR 61 // uDMA 0 Error -#define INT_ADC1SS0 62 // ADC1 Sequence 0 -#define INT_ADC1SS1 63 // ADC1 Sequence 1 -#define INT_ADC1SS2 64 // ADC1 Sequence 2 -#define INT_ADC1SS3 65 // ADC1 Sequence 3 -#define INT_EPI0 66 // EPI 0 -#define INT_GPIOJ 67 // GPIO Port J -#define INT_GPIOK 68 // GPIO Port K -#define INT_GPIOL 69 // GPIO Port L -#define INT_SSI2 70 // SSI 2 -#define INT_SSI3 71 // SSI 3 -#define INT_UART3 72 // UART 3 -#define INT_UART4 73 // UART 4 -#define INT_UART5 74 // UART 5 -#define INT_UART6 75 // UART 6 -#define INT_UART7 76 // UART 7 -#define INT_I2C2 77 // I2C 2 -#define INT_I2C3 78 // I2C 3 -#define INT_TIMER4A 79 // Timer 4A -#define INT_TIMER4B 80 // Timer 4B -#define INT_TIMER5A 81 // Timer 5A -#define INT_TIMER5B 82 // Timer 5B -#define INT_SYSEXC 83 // Floating-Point Exception - // (imprecise) -#define INT_I2C4 86 // I2C 4 -#define INT_I2C5 87 // I2C 5 -#define INT_GPIOM 88 // GPIO Port M -#define INT_GPION 89 // GPIO Port N -#define INT_TAMPER0 91 // Tamper -#define INT_GPIOP0 92 // GPIO Port P (Summary or P0) -#define INT_GPIOP1 93 // GPIO Port P1 -#define INT_GPIOP2 94 // GPIO Port P2 -#define INT_GPIOP3 95 // GPIO Port P3 -#define INT_GPIOP4 96 // GPIO Port P4 -#define INT_GPIOP5 97 // GPIO Port P5 -#define INT_GPIOP6 98 // GPIO Port P6 -#define INT_GPIOP7 99 // GPIO Port P7 -#define INT_GPIOQ0 100 // GPIO Port Q (Summary or Q0) -#define INT_GPIOQ1 101 // GPIO Port Q1 -#define INT_GPIOQ2 102 // GPIO Port Q2 -#define INT_GPIOQ3 103 // GPIO Port Q3 -#define INT_GPIOQ4 104 // GPIO Port Q4 -#define INT_GPIOQ5 105 // GPIO Port Q5 -#define INT_GPIOQ6 106 // GPIO Port Q6 -#define INT_GPIOQ7 107 // GPIO Port Q7 -#define INT_TIMER6A 114 // 16/32-Bit Timer 6A -#define INT_TIMER6B 115 // 16/32-Bit Timer 6B -#define INT_TIMER7A 116 // 16/32-Bit Timer 7A -#define INT_TIMER7B 117 // 16/32-Bit Timer 7B -#define INT_I2C6 118 // I2C 6 -#define INT_I2C7 119 // I2C 7 -#define INT_I2C8 125 // I2C 8 -#define INT_I2C9 126 // I2C 9 - -//***************************************************************************** -// -// Watchdog Timer registers (WATCHDOG0) -// -//***************************************************************************** -#define WATCHDOG0_LOAD_R (*((volatile uint32_t *)0x40000000)) -#define WATCHDOG0_VALUE_R (*((volatile uint32_t *)0x40000004)) -#define WATCHDOG0_CTL_R (*((volatile uint32_t *)0x40000008)) -#define WATCHDOG0_ICR_R (*((volatile uint32_t *)0x4000000C)) -#define WATCHDOG0_RIS_R (*((volatile uint32_t *)0x40000010)) -#define WATCHDOG0_MIS_R (*((volatile uint32_t *)0x40000014)) -#define WATCHDOG0_TEST_R (*((volatile uint32_t *)0x40000418)) -#define WATCHDOG0_LOCK_R (*((volatile uint32_t *)0x40000C00)) - -//***************************************************************************** -// -// Watchdog Timer registers (WATCHDOG1) -// -//***************************************************************************** -#define WATCHDOG1_LOAD_R (*((volatile uint32_t *)0x40001000)) -#define WATCHDOG1_VALUE_R (*((volatile uint32_t *)0x40001004)) -#define WATCHDOG1_CTL_R (*((volatile uint32_t *)0x40001008)) -#define WATCHDOG1_ICR_R (*((volatile uint32_t *)0x4000100C)) -#define WATCHDOG1_RIS_R (*((volatile uint32_t *)0x40001010)) -#define WATCHDOG1_MIS_R (*((volatile uint32_t *)0x40001014)) -#define WATCHDOG1_TEST_R (*((volatile uint32_t *)0x40001418)) -#define WATCHDOG1_LOCK_R (*((volatile uint32_t *)0x40001C00)) - -//***************************************************************************** -// -// SSI registers (SSI0) -// -//***************************************************************************** -#define SSI0_CR0_R (*((volatile uint32_t *)0x40008000)) -#define SSI0_CR1_R (*((volatile uint32_t *)0x40008004)) -#define SSI0_DR_R (*((volatile uint32_t *)0x40008008)) -#define SSI0_SR_R (*((volatile uint32_t *)0x4000800C)) -#define SSI0_CPSR_R (*((volatile uint32_t *)0x40008010)) -#define SSI0_IM_R (*((volatile uint32_t *)0x40008014)) -#define SSI0_RIS_R (*((volatile uint32_t *)0x40008018)) -#define SSI0_MIS_R (*((volatile uint32_t *)0x4000801C)) -#define SSI0_ICR_R (*((volatile uint32_t *)0x40008020)) -#define SSI0_DMACTL_R (*((volatile uint32_t *)0x40008024)) -#define SSI0_PP_R (*((volatile uint32_t *)0x40008FC0)) -#define SSI0_CC_R (*((volatile uint32_t *)0x40008FC8)) - -//***************************************************************************** -// -// SSI registers (SSI1) -// -//***************************************************************************** -#define SSI1_CR0_R (*((volatile uint32_t *)0x40009000)) -#define SSI1_CR1_R (*((volatile uint32_t *)0x40009004)) -#define SSI1_DR_R (*((volatile uint32_t *)0x40009008)) -#define SSI1_SR_R (*((volatile uint32_t *)0x4000900C)) -#define SSI1_CPSR_R (*((volatile uint32_t *)0x40009010)) -#define SSI1_IM_R (*((volatile uint32_t *)0x40009014)) -#define SSI1_RIS_R (*((volatile uint32_t *)0x40009018)) -#define SSI1_MIS_R (*((volatile uint32_t *)0x4000901C)) -#define SSI1_ICR_R (*((volatile uint32_t *)0x40009020)) -#define SSI1_DMACTL_R (*((volatile uint32_t *)0x40009024)) -#define SSI1_PP_R (*((volatile uint32_t *)0x40009FC0)) -#define SSI1_CC_R (*((volatile uint32_t *)0x40009FC8)) - -//***************************************************************************** -// -// SSI registers (SSI2) -// -//***************************************************************************** -#define SSI2_CR0_R (*((volatile uint32_t *)0x4000A000)) -#define SSI2_CR1_R (*((volatile uint32_t *)0x4000A004)) -#define SSI2_DR_R (*((volatile uint32_t *)0x4000A008)) -#define SSI2_SR_R (*((volatile uint32_t *)0x4000A00C)) -#define SSI2_CPSR_R (*((volatile uint32_t *)0x4000A010)) -#define SSI2_IM_R (*((volatile uint32_t *)0x4000A014)) -#define SSI2_RIS_R (*((volatile uint32_t *)0x4000A018)) -#define SSI2_MIS_R (*((volatile uint32_t *)0x4000A01C)) -#define SSI2_ICR_R (*((volatile uint32_t *)0x4000A020)) -#define SSI2_DMACTL_R (*((volatile uint32_t *)0x4000A024)) -#define SSI2_PP_R (*((volatile uint32_t *)0x4000AFC0)) -#define SSI2_CC_R (*((volatile uint32_t *)0x4000AFC8)) - -//***************************************************************************** -// -// SSI registers (SSI3) -// -//***************************************************************************** -#define SSI3_CR0_R (*((volatile uint32_t *)0x4000B000)) -#define SSI3_CR1_R (*((volatile uint32_t *)0x4000B004)) -#define SSI3_DR_R (*((volatile uint32_t *)0x4000B008)) -#define SSI3_SR_R (*((volatile uint32_t *)0x4000B00C)) -#define SSI3_CPSR_R (*((volatile uint32_t *)0x4000B010)) -#define SSI3_IM_R (*((volatile uint32_t *)0x4000B014)) -#define SSI3_RIS_R (*((volatile uint32_t *)0x4000B018)) -#define SSI3_MIS_R (*((volatile uint32_t *)0x4000B01C)) -#define SSI3_ICR_R (*((volatile uint32_t *)0x4000B020)) -#define SSI3_DMACTL_R (*((volatile uint32_t *)0x4000B024)) -#define SSI3_PP_R (*((volatile uint32_t *)0x4000BFC0)) -#define SSI3_CC_R (*((volatile uint32_t *)0x4000BFC8)) - -//***************************************************************************** -// -// UART registers (UART0) -// -//***************************************************************************** -#define UART0_DR_R (*((volatile uint32_t *)0x4000C000)) -#define UART0_RSR_R (*((volatile uint32_t *)0x4000C004)) -#define UART0_ECR_R (*((volatile uint32_t *)0x4000C004)) -#define UART0_FR_R (*((volatile uint32_t *)0x4000C018)) -#define UART0_ILPR_R (*((volatile uint32_t *)0x4000C020)) -#define UART0_IBRD_R (*((volatile uint32_t *)0x4000C024)) -#define UART0_FBRD_R (*((volatile uint32_t *)0x4000C028)) -#define UART0_LCRH_R (*((volatile uint32_t *)0x4000C02C)) -#define UART0_CTL_R (*((volatile uint32_t *)0x4000C030)) -#define UART0_IFLS_R (*((volatile uint32_t *)0x4000C034)) -#define UART0_IM_R (*((volatile uint32_t *)0x4000C038)) -#define UART0_RIS_R (*((volatile uint32_t *)0x4000C03C)) -#define UART0_MIS_R (*((volatile uint32_t *)0x4000C040)) -#define UART0_ICR_R (*((volatile uint32_t *)0x4000C044)) -#define UART0_DMACTL_R (*((volatile uint32_t *)0x4000C048)) -#define UART0_9BITADDR_R (*((volatile uint32_t *)0x4000C0A4)) -#define UART0_9BITAMASK_R (*((volatile uint32_t *)0x4000C0A8)) -#define UART0_PP_R (*((volatile uint32_t *)0x4000CFC0)) -#define UART0_CC_R (*((volatile uint32_t *)0x4000CFC8)) - -//***************************************************************************** -// -// UART registers (UART1) -// -//***************************************************************************** -#define UART1_DR_R (*((volatile uint32_t *)0x4000D000)) -#define UART1_RSR_R (*((volatile uint32_t *)0x4000D004)) -#define UART1_ECR_R (*((volatile uint32_t *)0x4000D004)) -#define UART1_FR_R (*((volatile uint32_t *)0x4000D018)) -#define UART1_ILPR_R (*((volatile uint32_t *)0x4000D020)) -#define UART1_IBRD_R (*((volatile uint32_t *)0x4000D024)) -#define UART1_FBRD_R (*((volatile uint32_t *)0x4000D028)) -#define UART1_LCRH_R (*((volatile uint32_t *)0x4000D02C)) -#define UART1_CTL_R (*((volatile uint32_t *)0x4000D030)) -#define UART1_IFLS_R (*((volatile uint32_t *)0x4000D034)) -#define UART1_IM_R (*((volatile uint32_t *)0x4000D038)) -#define UART1_RIS_R (*((volatile uint32_t *)0x4000D03C)) -#define UART1_MIS_R (*((volatile uint32_t *)0x4000D040)) -#define UART1_ICR_R (*((volatile uint32_t *)0x4000D044)) -#define UART1_DMACTL_R (*((volatile uint32_t *)0x4000D048)) -#define UART1_9BITADDR_R (*((volatile uint32_t *)0x4000D0A4)) -#define UART1_9BITAMASK_R (*((volatile uint32_t *)0x4000D0A8)) -#define UART1_PP_R (*((volatile uint32_t *)0x4000DFC0)) -#define UART1_CC_R (*((volatile uint32_t *)0x4000DFC8)) - -//***************************************************************************** -// -// UART registers (UART2) -// -//***************************************************************************** -#define UART2_DR_R (*((volatile uint32_t *)0x4000E000)) -#define UART2_RSR_R (*((volatile uint32_t *)0x4000E004)) -#define UART2_ECR_R (*((volatile uint32_t *)0x4000E004)) -#define UART2_FR_R (*((volatile uint32_t *)0x4000E018)) -#define UART2_ILPR_R (*((volatile uint32_t *)0x4000E020)) -#define UART2_IBRD_R (*((volatile uint32_t *)0x4000E024)) -#define UART2_FBRD_R (*((volatile uint32_t *)0x4000E028)) -#define UART2_LCRH_R (*((volatile uint32_t *)0x4000E02C)) -#define UART2_CTL_R (*((volatile uint32_t *)0x4000E030)) -#define UART2_IFLS_R (*((volatile uint32_t *)0x4000E034)) -#define UART2_IM_R (*((volatile uint32_t *)0x4000E038)) -#define UART2_RIS_R (*((volatile uint32_t *)0x4000E03C)) -#define UART2_MIS_R (*((volatile uint32_t *)0x4000E040)) -#define UART2_ICR_R (*((volatile uint32_t *)0x4000E044)) -#define UART2_DMACTL_R (*((volatile uint32_t *)0x4000E048)) -#define UART2_9BITADDR_R (*((volatile uint32_t *)0x4000E0A4)) -#define UART2_9BITAMASK_R (*((volatile uint32_t *)0x4000E0A8)) -#define UART2_PP_R (*((volatile uint32_t *)0x4000EFC0)) -#define UART2_CC_R (*((volatile uint32_t *)0x4000EFC8)) - -//***************************************************************************** -// -// UART registers (UART3) -// -//***************************************************************************** -#define UART3_DR_R (*((volatile uint32_t *)0x4000F000)) -#define UART3_RSR_R (*((volatile uint32_t *)0x4000F004)) -#define UART3_ECR_R (*((volatile uint32_t *)0x4000F004)) -#define UART3_FR_R (*((volatile uint32_t *)0x4000F018)) -#define UART3_ILPR_R (*((volatile uint32_t *)0x4000F020)) -#define UART3_IBRD_R (*((volatile uint32_t *)0x4000F024)) -#define UART3_FBRD_R (*((volatile uint32_t *)0x4000F028)) -#define UART3_LCRH_R (*((volatile uint32_t *)0x4000F02C)) -#define UART3_CTL_R (*((volatile uint32_t *)0x4000F030)) -#define UART3_IFLS_R (*((volatile uint32_t *)0x4000F034)) -#define UART3_IM_R (*((volatile uint32_t *)0x4000F038)) -#define UART3_RIS_R (*((volatile uint32_t *)0x4000F03C)) -#define UART3_MIS_R (*((volatile uint32_t *)0x4000F040)) -#define UART3_ICR_R (*((volatile uint32_t *)0x4000F044)) -#define UART3_DMACTL_R (*((volatile uint32_t *)0x4000F048)) -#define UART3_9BITADDR_R (*((volatile uint32_t *)0x4000F0A4)) -#define UART3_9BITAMASK_R (*((volatile uint32_t *)0x4000F0A8)) -#define UART3_PP_R (*((volatile uint32_t *)0x4000FFC0)) -#define UART3_CC_R (*((volatile uint32_t *)0x4000FFC8)) - -//***************************************************************************** -// -// UART registers (UART4) -// -//***************************************************************************** -#define UART4_DR_R (*((volatile uint32_t *)0x40010000)) -#define UART4_RSR_R (*((volatile uint32_t *)0x40010004)) -#define UART4_ECR_R (*((volatile uint32_t *)0x40010004)) -#define UART4_FR_R (*((volatile uint32_t *)0x40010018)) -#define UART4_ILPR_R (*((volatile uint32_t *)0x40010020)) -#define UART4_IBRD_R (*((volatile uint32_t *)0x40010024)) -#define UART4_FBRD_R (*((volatile uint32_t *)0x40010028)) -#define UART4_LCRH_R (*((volatile uint32_t *)0x4001002C)) -#define UART4_CTL_R (*((volatile uint32_t *)0x40010030)) -#define UART4_IFLS_R (*((volatile uint32_t *)0x40010034)) -#define UART4_IM_R (*((volatile uint32_t *)0x40010038)) -#define UART4_RIS_R (*((volatile uint32_t *)0x4001003C)) -#define UART4_MIS_R (*((volatile uint32_t *)0x40010040)) -#define UART4_ICR_R (*((volatile uint32_t *)0x40010044)) -#define UART4_DMACTL_R (*((volatile uint32_t *)0x40010048)) -#define UART4_9BITADDR_R (*((volatile uint32_t *)0x400100A4)) -#define UART4_9BITAMASK_R (*((volatile uint32_t *)0x400100A8)) -#define UART4_PP_R (*((volatile uint32_t *)0x40010FC0)) -#define UART4_CC_R (*((volatile uint32_t *)0x40010FC8)) - -//***************************************************************************** -// -// UART registers (UART5) -// -//***************************************************************************** -#define UART5_DR_R (*((volatile uint32_t *)0x40011000)) -#define UART5_RSR_R (*((volatile uint32_t *)0x40011004)) -#define UART5_ECR_R (*((volatile uint32_t *)0x40011004)) -#define UART5_FR_R (*((volatile uint32_t *)0x40011018)) -#define UART5_ILPR_R (*((volatile uint32_t *)0x40011020)) -#define UART5_IBRD_R (*((volatile uint32_t *)0x40011024)) -#define UART5_FBRD_R (*((volatile uint32_t *)0x40011028)) -#define UART5_LCRH_R (*((volatile uint32_t *)0x4001102C)) -#define UART5_CTL_R (*((volatile uint32_t *)0x40011030)) -#define UART5_IFLS_R (*((volatile uint32_t *)0x40011034)) -#define UART5_IM_R (*((volatile uint32_t *)0x40011038)) -#define UART5_RIS_R (*((volatile uint32_t *)0x4001103C)) -#define UART5_MIS_R (*((volatile uint32_t *)0x40011040)) -#define UART5_ICR_R (*((volatile uint32_t *)0x40011044)) -#define UART5_DMACTL_R (*((volatile uint32_t *)0x40011048)) -#define UART5_9BITADDR_R (*((volatile uint32_t *)0x400110A4)) -#define UART5_9BITAMASK_R (*((volatile uint32_t *)0x400110A8)) -#define UART5_PP_R (*((volatile uint32_t *)0x40011FC0)) -#define UART5_CC_R (*((volatile uint32_t *)0x40011FC8)) - -//***************************************************************************** -// -// UART registers (UART6) -// -//***************************************************************************** -#define UART6_DR_R (*((volatile uint32_t *)0x40012000)) -#define UART6_RSR_R (*((volatile uint32_t *)0x40012004)) -#define UART6_ECR_R (*((volatile uint32_t *)0x40012004)) -#define UART6_FR_R (*((volatile uint32_t *)0x40012018)) -#define UART6_ILPR_R (*((volatile uint32_t *)0x40012020)) -#define UART6_IBRD_R (*((volatile uint32_t *)0x40012024)) -#define UART6_FBRD_R (*((volatile uint32_t *)0x40012028)) -#define UART6_LCRH_R (*((volatile uint32_t *)0x4001202C)) -#define UART6_CTL_R (*((volatile uint32_t *)0x40012030)) -#define UART6_IFLS_R (*((volatile uint32_t *)0x40012034)) -#define UART6_IM_R (*((volatile uint32_t *)0x40012038)) -#define UART6_RIS_R (*((volatile uint32_t *)0x4001203C)) -#define UART6_MIS_R (*((volatile uint32_t *)0x40012040)) -#define UART6_ICR_R (*((volatile uint32_t *)0x40012044)) -#define UART6_DMACTL_R (*((volatile uint32_t *)0x40012048)) -#define UART6_9BITADDR_R (*((volatile uint32_t *)0x400120A4)) -#define UART6_9BITAMASK_R (*((volatile uint32_t *)0x400120A8)) -#define UART6_PP_R (*((volatile uint32_t *)0x40012FC0)) -#define UART6_CC_R (*((volatile uint32_t *)0x40012FC8)) - -//***************************************************************************** -// -// UART registers (UART7) -// -//***************************************************************************** -#define UART7_DR_R (*((volatile uint32_t *)0x40013000)) -#define UART7_RSR_R (*((volatile uint32_t *)0x40013004)) -#define UART7_ECR_R (*((volatile uint32_t *)0x40013004)) -#define UART7_FR_R (*((volatile uint32_t *)0x40013018)) -#define UART7_ILPR_R (*((volatile uint32_t *)0x40013020)) -#define UART7_IBRD_R (*((volatile uint32_t *)0x40013024)) -#define UART7_FBRD_R (*((volatile uint32_t *)0x40013028)) -#define UART7_LCRH_R (*((volatile uint32_t *)0x4001302C)) -#define UART7_CTL_R (*((volatile uint32_t *)0x40013030)) -#define UART7_IFLS_R (*((volatile uint32_t *)0x40013034)) -#define UART7_IM_R (*((volatile uint32_t *)0x40013038)) -#define UART7_RIS_R (*((volatile uint32_t *)0x4001303C)) -#define UART7_MIS_R (*((volatile uint32_t *)0x40013040)) -#define UART7_ICR_R (*((volatile uint32_t *)0x40013044)) -#define UART7_DMACTL_R (*((volatile uint32_t *)0x40013048)) -#define UART7_9BITADDR_R (*((volatile uint32_t *)0x400130A4)) -#define UART7_9BITAMASK_R (*((volatile uint32_t *)0x400130A8)) -#define UART7_PP_R (*((volatile uint32_t *)0x40013FC0)) -#define UART7_CC_R (*((volatile uint32_t *)0x40013FC8)) - -//***************************************************************************** -// -// I2C registers (I2C0) -// -//***************************************************************************** -#define I2C0_MSA_R (*((volatile uint32_t *)0x40020000)) -#define I2C0_MCS_R (*((volatile uint32_t *)0x40020004)) -#define I2C0_MDR_R (*((volatile uint32_t *)0x40020008)) -#define I2C0_MTPR_R (*((volatile uint32_t *)0x4002000C)) -#define I2C0_MIMR_R (*((volatile uint32_t *)0x40020010)) -#define I2C0_MRIS_R (*((volatile uint32_t *)0x40020014)) -#define I2C0_MMIS_R (*((volatile uint32_t *)0x40020018)) -#define I2C0_MICR_R (*((volatile uint32_t *)0x4002001C)) -#define I2C0_MCR_R (*((volatile uint32_t *)0x40020020)) -#define I2C0_MCLKOCNT_R (*((volatile uint32_t *)0x40020024)) -#define I2C0_MBMON_R (*((volatile uint32_t *)0x4002002C)) -#define I2C0_MBLEN_R (*((volatile uint32_t *)0x40020030)) -#define I2C0_MBCNT_R (*((volatile uint32_t *)0x40020034)) -#define I2C0_SOAR_R (*((volatile uint32_t *)0x40020800)) -#define I2C0_SCSR_R (*((volatile uint32_t *)0x40020804)) -#define I2C0_SDR_R (*((volatile uint32_t *)0x40020808)) -#define I2C0_SIMR_R (*((volatile uint32_t *)0x4002080C)) -#define I2C0_SRIS_R (*((volatile uint32_t *)0x40020810)) -#define I2C0_SMIS_R (*((volatile uint32_t *)0x40020814)) -#define I2C0_SICR_R (*((volatile uint32_t *)0x40020818)) -#define I2C0_SOAR2_R (*((volatile uint32_t *)0x4002081C)) -#define I2C0_SACKCTL_R (*((volatile uint32_t *)0x40020820)) -#define I2C0_FIFODATA_R (*((volatile uint32_t *)0x40020F00)) -#define I2C0_FIFOCTL_R (*((volatile uint32_t *)0x40020F04)) -#define I2C0_FIFOSTATUS_R (*((volatile uint32_t *)0x40020F08)) -#define I2C0_PP_R (*((volatile uint32_t *)0x40020FC0)) -#define I2C0_PC_R (*((volatile uint32_t *)0x40020FC4)) - -//***************************************************************************** -// -// I2C registers (I2C1) -// -//***************************************************************************** -#define I2C1_MSA_R (*((volatile uint32_t *)0x40021000)) -#define I2C1_MCS_R (*((volatile uint32_t *)0x40021004)) -#define I2C1_MDR_R (*((volatile uint32_t *)0x40021008)) -#define I2C1_MTPR_R (*((volatile uint32_t *)0x4002100C)) -#define I2C1_MIMR_R (*((volatile uint32_t *)0x40021010)) -#define I2C1_MRIS_R (*((volatile uint32_t *)0x40021014)) -#define I2C1_MMIS_R (*((volatile uint32_t *)0x40021018)) -#define I2C1_MICR_R (*((volatile uint32_t *)0x4002101C)) -#define I2C1_MCR_R (*((volatile uint32_t *)0x40021020)) -#define I2C1_MCLKOCNT_R (*((volatile uint32_t *)0x40021024)) -#define I2C1_MBMON_R (*((volatile uint32_t *)0x4002102C)) -#define I2C1_MBLEN_R (*((volatile uint32_t *)0x40021030)) -#define I2C1_MBCNT_R (*((volatile uint32_t *)0x40021034)) -#define I2C1_SOAR_R (*((volatile uint32_t *)0x40021800)) -#define I2C1_SCSR_R (*((volatile uint32_t *)0x40021804)) -#define I2C1_SDR_R (*((volatile uint32_t *)0x40021808)) -#define I2C1_SIMR_R (*((volatile uint32_t *)0x4002180C)) -#define I2C1_SRIS_R (*((volatile uint32_t *)0x40021810)) -#define I2C1_SMIS_R (*((volatile uint32_t *)0x40021814)) -#define I2C1_SICR_R (*((volatile uint32_t *)0x40021818)) -#define I2C1_SOAR2_R (*((volatile uint32_t *)0x4002181C)) -#define I2C1_SACKCTL_R (*((volatile uint32_t *)0x40021820)) -#define I2C1_FIFODATA_R (*((volatile uint32_t *)0x40021F00)) -#define I2C1_FIFOCTL_R (*((volatile uint32_t *)0x40021F04)) -#define I2C1_FIFOSTATUS_R (*((volatile uint32_t *)0x40021F08)) -#define I2C1_PP_R (*((volatile uint32_t *)0x40021FC0)) -#define I2C1_PC_R (*((volatile uint32_t *)0x40021FC4)) - -//***************************************************************************** -// -// I2C registers (I2C2) -// -//***************************************************************************** -#define I2C2_MSA_R (*((volatile uint32_t *)0x40022000)) -#define I2C2_MCS_R (*((volatile uint32_t *)0x40022004)) -#define I2C2_MDR_R (*((volatile uint32_t *)0x40022008)) -#define I2C2_MTPR_R (*((volatile uint32_t *)0x4002200C)) -#define I2C2_MIMR_R (*((volatile uint32_t *)0x40022010)) -#define I2C2_MRIS_R (*((volatile uint32_t *)0x40022014)) -#define I2C2_MMIS_R (*((volatile uint32_t *)0x40022018)) -#define I2C2_MICR_R (*((volatile uint32_t *)0x4002201C)) -#define I2C2_MCR_R (*((volatile uint32_t *)0x40022020)) -#define I2C2_MCLKOCNT_R (*((volatile uint32_t *)0x40022024)) -#define I2C2_MBMON_R (*((volatile uint32_t *)0x4002202C)) -#define I2C2_MBLEN_R (*((volatile uint32_t *)0x40022030)) -#define I2C2_MBCNT_R (*((volatile uint32_t *)0x40022034)) -#define I2C2_SOAR_R (*((volatile uint32_t *)0x40022800)) -#define I2C2_SCSR_R (*((volatile uint32_t *)0x40022804)) -#define I2C2_SDR_R (*((volatile uint32_t *)0x40022808)) -#define I2C2_SIMR_R (*((volatile uint32_t *)0x4002280C)) -#define I2C2_SRIS_R (*((volatile uint32_t *)0x40022810)) -#define I2C2_SMIS_R (*((volatile uint32_t *)0x40022814)) -#define I2C2_SICR_R (*((volatile uint32_t *)0x40022818)) -#define I2C2_SOAR2_R (*((volatile uint32_t *)0x4002281C)) -#define I2C2_SACKCTL_R (*((volatile uint32_t *)0x40022820)) -#define I2C2_FIFODATA_R (*((volatile uint32_t *)0x40022F00)) -#define I2C2_FIFOCTL_R (*((volatile uint32_t *)0x40022F04)) -#define I2C2_FIFOSTATUS_R (*((volatile uint32_t *)0x40022F08)) -#define I2C2_PP_R (*((volatile uint32_t *)0x40022FC0)) -#define I2C2_PC_R (*((volatile uint32_t *)0x40022FC4)) - -//***************************************************************************** -// -// I2C registers (I2C3) -// -//***************************************************************************** -#define I2C3_MSA_R (*((volatile uint32_t *)0x40023000)) -#define I2C3_MCS_R (*((volatile uint32_t *)0x40023004)) -#define I2C3_MDR_R (*((volatile uint32_t *)0x40023008)) -#define I2C3_MTPR_R (*((volatile uint32_t *)0x4002300C)) -#define I2C3_MIMR_R (*((volatile uint32_t *)0x40023010)) -#define I2C3_MRIS_R (*((volatile uint32_t *)0x40023014)) -#define I2C3_MMIS_R (*((volatile uint32_t *)0x40023018)) -#define I2C3_MICR_R (*((volatile uint32_t *)0x4002301C)) -#define I2C3_MCR_R (*((volatile uint32_t *)0x40023020)) -#define I2C3_MCLKOCNT_R (*((volatile uint32_t *)0x40023024)) -#define I2C3_MBMON_R (*((volatile uint32_t *)0x4002302C)) -#define I2C3_MBLEN_R (*((volatile uint32_t *)0x40023030)) -#define I2C3_MBCNT_R (*((volatile uint32_t *)0x40023034)) -#define I2C3_SOAR_R (*((volatile uint32_t *)0x40023800)) -#define I2C3_SCSR_R (*((volatile uint32_t *)0x40023804)) -#define I2C3_SDR_R (*((volatile uint32_t *)0x40023808)) -#define I2C3_SIMR_R (*((volatile uint32_t *)0x4002380C)) -#define I2C3_SRIS_R (*((volatile uint32_t *)0x40023810)) -#define I2C3_SMIS_R (*((volatile uint32_t *)0x40023814)) -#define I2C3_SICR_R (*((volatile uint32_t *)0x40023818)) -#define I2C3_SOAR2_R (*((volatile uint32_t *)0x4002381C)) -#define I2C3_SACKCTL_R (*((volatile uint32_t *)0x40023820)) -#define I2C3_FIFODATA_R (*((volatile uint32_t *)0x40023F00)) -#define I2C3_FIFOCTL_R (*((volatile uint32_t *)0x40023F04)) -#define I2C3_FIFOSTATUS_R (*((volatile uint32_t *)0x40023F08)) -#define I2C3_PP_R (*((volatile uint32_t *)0x40023FC0)) -#define I2C3_PC_R (*((volatile uint32_t *)0x40023FC4)) - -//***************************************************************************** -// -// PWM registers (PWM0) -// -//***************************************************************************** -#define PWM0_CTL_R (*((volatile uint32_t *)0x40028000)) -#define PWM0_SYNC_R (*((volatile uint32_t *)0x40028004)) -#define PWM0_ENABLE_R (*((volatile uint32_t *)0x40028008)) -#define PWM0_INVERT_R (*((volatile uint32_t *)0x4002800C)) -#define PWM0_FAULT_R (*((volatile uint32_t *)0x40028010)) -#define PWM0_INTEN_R (*((volatile uint32_t *)0x40028014)) -#define PWM0_RIS_R (*((volatile uint32_t *)0x40028018)) -#define PWM0_ISC_R (*((volatile uint32_t *)0x4002801C)) -#define PWM0_STATUS_R (*((volatile uint32_t *)0x40028020)) -#define PWM0_FAULTVAL_R (*((volatile uint32_t *)0x40028024)) -#define PWM0_ENUPD_R (*((volatile uint32_t *)0x40028028)) -#define PWM0_0_CTL_R (*((volatile uint32_t *)0x40028040)) -#define PWM0_0_INTEN_R (*((volatile uint32_t *)0x40028044)) -#define PWM0_0_RIS_R (*((volatile uint32_t *)0x40028048)) -#define PWM0_0_ISC_R (*((volatile uint32_t *)0x4002804C)) -#define PWM0_0_LOAD_R (*((volatile uint32_t *)0x40028050)) -#define PWM0_0_COUNT_R (*((volatile uint32_t *)0x40028054)) -#define PWM0_0_CMPA_R (*((volatile uint32_t *)0x40028058)) -#define PWM0_0_CMPB_R (*((volatile uint32_t *)0x4002805C)) -#define PWM0_0_GENA_R (*((volatile uint32_t *)0x40028060)) -#define PWM0_0_GENB_R (*((volatile uint32_t *)0x40028064)) -#define PWM0_0_DBCTL_R (*((volatile uint32_t *)0x40028068)) -#define PWM0_0_DBRISE_R (*((volatile uint32_t *)0x4002806C)) -#define PWM0_0_DBFALL_R (*((volatile uint32_t *)0x40028070)) -#define PWM0_0_FLTSRC0_R (*((volatile uint32_t *)0x40028074)) -#define PWM0_0_FLTSRC1_R (*((volatile uint32_t *)0x40028078)) -#define PWM0_0_MINFLTPER_R (*((volatile uint32_t *)0x4002807C)) -#define PWM0_1_CTL_R (*((volatile uint32_t *)0x40028080)) -#define PWM0_1_INTEN_R (*((volatile uint32_t *)0x40028084)) -#define PWM0_1_RIS_R (*((volatile uint32_t *)0x40028088)) -#define PWM0_1_ISC_R (*((volatile uint32_t *)0x4002808C)) -#define PWM0_1_LOAD_R (*((volatile uint32_t *)0x40028090)) -#define PWM0_1_COUNT_R (*((volatile uint32_t *)0x40028094)) -#define PWM0_1_CMPA_R (*((volatile uint32_t *)0x40028098)) -#define PWM0_1_CMPB_R (*((volatile uint32_t *)0x4002809C)) -#define PWM0_1_GENA_R (*((volatile uint32_t *)0x400280A0)) -#define PWM0_1_GENB_R (*((volatile uint32_t *)0x400280A4)) -#define PWM0_1_DBCTL_R (*((volatile uint32_t *)0x400280A8)) -#define PWM0_1_DBRISE_R (*((volatile uint32_t *)0x400280AC)) -#define PWM0_1_DBFALL_R (*((volatile uint32_t *)0x400280B0)) -#define PWM0_1_FLTSRC0_R (*((volatile uint32_t *)0x400280B4)) -#define PWM0_1_FLTSRC1_R (*((volatile uint32_t *)0x400280B8)) -#define PWM0_1_MINFLTPER_R (*((volatile uint32_t *)0x400280BC)) -#define PWM0_2_CTL_R (*((volatile uint32_t *)0x400280C0)) -#define PWM0_2_INTEN_R (*((volatile uint32_t *)0x400280C4)) -#define PWM0_2_RIS_R (*((volatile uint32_t *)0x400280C8)) -#define PWM0_2_ISC_R (*((volatile uint32_t *)0x400280CC)) -#define PWM0_2_LOAD_R (*((volatile uint32_t *)0x400280D0)) -#define PWM0_2_COUNT_R (*((volatile uint32_t *)0x400280D4)) -#define PWM0_2_CMPA_R (*((volatile uint32_t *)0x400280D8)) -#define PWM0_2_CMPB_R (*((volatile uint32_t *)0x400280DC)) -#define PWM0_2_GENA_R (*((volatile uint32_t *)0x400280E0)) -#define PWM0_2_GENB_R (*((volatile uint32_t *)0x400280E4)) -#define PWM0_2_DBCTL_R (*((volatile uint32_t *)0x400280E8)) -#define PWM0_2_DBRISE_R (*((volatile uint32_t *)0x400280EC)) -#define PWM0_2_DBFALL_R (*((volatile uint32_t *)0x400280F0)) -#define PWM0_2_FLTSRC0_R (*((volatile uint32_t *)0x400280F4)) -#define PWM0_2_FLTSRC1_R (*((volatile uint32_t *)0x400280F8)) -#define PWM0_2_MINFLTPER_R (*((volatile uint32_t *)0x400280FC)) -#define PWM0_3_CTL_R (*((volatile uint32_t *)0x40028100)) -#define PWM0_3_INTEN_R (*((volatile uint32_t *)0x40028104)) -#define PWM0_3_RIS_R (*((volatile uint32_t *)0x40028108)) -#define PWM0_3_ISC_R (*((volatile uint32_t *)0x4002810C)) -#define PWM0_3_LOAD_R (*((volatile uint32_t *)0x40028110)) -#define PWM0_3_COUNT_R (*((volatile uint32_t *)0x40028114)) -#define PWM0_3_CMPA_R (*((volatile uint32_t *)0x40028118)) -#define PWM0_3_CMPB_R (*((volatile uint32_t *)0x4002811C)) -#define PWM0_3_GENA_R (*((volatile uint32_t *)0x40028120)) -#define PWM0_3_GENB_R (*((volatile uint32_t *)0x40028124)) -#define PWM0_3_DBCTL_R (*((volatile uint32_t *)0x40028128)) -#define PWM0_3_DBRISE_R (*((volatile uint32_t *)0x4002812C)) -#define PWM0_3_DBFALL_R (*((volatile uint32_t *)0x40028130)) -#define PWM0_3_FLTSRC0_R (*((volatile uint32_t *)0x40028134)) -#define PWM0_3_FLTSRC1_R (*((volatile uint32_t *)0x40028138)) -#define PWM0_3_MINFLTPER_R (*((volatile uint32_t *)0x4002813C)) -#define PWM0_0_FLTSEN_R (*((volatile uint32_t *)0x40028800)) -#define PWM0_0_FLTSTAT0_R (*((volatile uint32_t *)0x40028804)) -#define PWM0_0_FLTSTAT1_R (*((volatile uint32_t *)0x40028808)) -#define PWM0_1_FLTSEN_R (*((volatile uint32_t *)0x40028880)) -#define PWM0_1_FLTSTAT0_R (*((volatile uint32_t *)0x40028884)) -#define PWM0_1_FLTSTAT1_R (*((volatile uint32_t *)0x40028888)) -#define PWM0_2_FLTSEN_R (*((volatile uint32_t *)0x40028900)) -#define PWM0_2_FLTSTAT0_R (*((volatile uint32_t *)0x40028904)) -#define PWM0_2_FLTSTAT1_R (*((volatile uint32_t *)0x40028908)) -#define PWM0_3_FLTSEN_R (*((volatile uint32_t *)0x40028980)) -#define PWM0_3_FLTSTAT0_R (*((volatile uint32_t *)0x40028984)) -#define PWM0_3_FLTSTAT1_R (*((volatile uint32_t *)0x40028988)) -#define PWM0_PP_R (*((volatile uint32_t *)0x40028FC0)) -#define PWM0_CC_R (*((volatile uint32_t *)0x40028FC8)) - -//***************************************************************************** -// -// QEI registers (QEI0) -// -//***************************************************************************** -#define QEI0_CTL_R (*((volatile uint32_t *)0x4002C000)) -#define QEI0_STAT_R (*((volatile uint32_t *)0x4002C004)) -#define QEI0_POS_R (*((volatile uint32_t *)0x4002C008)) -#define QEI0_MAXPOS_R (*((volatile uint32_t *)0x4002C00C)) -#define QEI0_LOAD_R (*((volatile uint32_t *)0x4002C010)) -#define QEI0_TIME_R (*((volatile uint32_t *)0x4002C014)) -#define QEI0_COUNT_R (*((volatile uint32_t *)0x4002C018)) -#define QEI0_SPEED_R (*((volatile uint32_t *)0x4002C01C)) -#define QEI0_INTEN_R (*((volatile uint32_t *)0x4002C020)) -#define QEI0_RIS_R (*((volatile uint32_t *)0x4002C024)) -#define QEI0_ISC_R (*((volatile uint32_t *)0x4002C028)) - -//***************************************************************************** -// -// Timer registers (TIMER0) -// -//***************************************************************************** -#define TIMER0_CFG_R (*((volatile uint32_t *)0x40030000)) -#define TIMER0_TAMR_R (*((volatile uint32_t *)0x40030004)) -#define TIMER0_TBMR_R (*((volatile uint32_t *)0x40030008)) -#define TIMER0_CTL_R (*((volatile uint32_t *)0x4003000C)) -#define TIMER0_SYNC_R (*((volatile uint32_t *)0x40030010)) -#define TIMER0_IMR_R (*((volatile uint32_t *)0x40030018)) -#define TIMER0_RIS_R (*((volatile uint32_t *)0x4003001C)) -#define TIMER0_MIS_R (*((volatile uint32_t *)0x40030020)) -#define TIMER0_ICR_R (*((volatile uint32_t *)0x40030024)) -#define TIMER0_TAILR_R (*((volatile uint32_t *)0x40030028)) -#define TIMER0_TBILR_R (*((volatile uint32_t *)0x4003002C)) -#define TIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40030030)) -#define TIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40030034)) -#define TIMER0_TAPR_R (*((volatile uint32_t *)0x40030038)) -#define TIMER0_TBPR_R (*((volatile uint32_t *)0x4003003C)) -#define TIMER0_TAPMR_R (*((volatile uint32_t *)0x40030040)) -#define TIMER0_TBPMR_R (*((volatile uint32_t *)0x40030044)) -#define TIMER0_TAR_R (*((volatile uint32_t *)0x40030048)) -#define TIMER0_TBR_R (*((volatile uint32_t *)0x4003004C)) -#define TIMER0_TAV_R (*((volatile uint32_t *)0x40030050)) -#define TIMER0_TBV_R (*((volatile uint32_t *)0x40030054)) -#define TIMER0_RTCPD_R (*((volatile uint32_t *)0x40030058)) -#define TIMER0_TAPS_R (*((volatile uint32_t *)0x4003005C)) -#define TIMER0_TBPS_R (*((volatile uint32_t *)0x40030060)) -#define TIMER0_DMAEV_R (*((volatile uint32_t *)0x4003006C)) -#define TIMER0_ADCEV_R (*((volatile uint32_t *)0x40030070)) -#define TIMER0_PP_R (*((volatile uint32_t *)0x40030FC0)) -#define TIMER0_CC_R (*((volatile uint32_t *)0x40030FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER1) -// -//***************************************************************************** -#define TIMER1_CFG_R (*((volatile uint32_t *)0x40031000)) -#define TIMER1_TAMR_R (*((volatile uint32_t *)0x40031004)) -#define TIMER1_TBMR_R (*((volatile uint32_t *)0x40031008)) -#define TIMER1_CTL_R (*((volatile uint32_t *)0x4003100C)) -#define TIMER1_SYNC_R (*((volatile uint32_t *)0x40031010)) -#define TIMER1_IMR_R (*((volatile uint32_t *)0x40031018)) -#define TIMER1_RIS_R (*((volatile uint32_t *)0x4003101C)) -#define TIMER1_MIS_R (*((volatile uint32_t *)0x40031020)) -#define TIMER1_ICR_R (*((volatile uint32_t *)0x40031024)) -#define TIMER1_TAILR_R (*((volatile uint32_t *)0x40031028)) -#define TIMER1_TBILR_R (*((volatile uint32_t *)0x4003102C)) -#define TIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40031030)) -#define TIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40031034)) -#define TIMER1_TAPR_R (*((volatile uint32_t *)0x40031038)) -#define TIMER1_TBPR_R (*((volatile uint32_t *)0x4003103C)) -#define TIMER1_TAPMR_R (*((volatile uint32_t *)0x40031040)) -#define TIMER1_TBPMR_R (*((volatile uint32_t *)0x40031044)) -#define TIMER1_TAR_R (*((volatile uint32_t *)0x40031048)) -#define TIMER1_TBR_R (*((volatile uint32_t *)0x4003104C)) -#define TIMER1_TAV_R (*((volatile uint32_t *)0x40031050)) -#define TIMER1_TBV_R (*((volatile uint32_t *)0x40031054)) -#define TIMER1_RTCPD_R (*((volatile uint32_t *)0x40031058)) -#define TIMER1_TAPS_R (*((volatile uint32_t *)0x4003105C)) -#define TIMER1_TBPS_R (*((volatile uint32_t *)0x40031060)) -#define TIMER1_DMAEV_R (*((volatile uint32_t *)0x4003106C)) -#define TIMER1_ADCEV_R (*((volatile uint32_t *)0x40031070)) -#define TIMER1_PP_R (*((volatile uint32_t *)0x40031FC0)) -#define TIMER1_CC_R (*((volatile uint32_t *)0x40031FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER2) -// -//***************************************************************************** -#define TIMER2_CFG_R (*((volatile uint32_t *)0x40032000)) -#define TIMER2_TAMR_R (*((volatile uint32_t *)0x40032004)) -#define TIMER2_TBMR_R (*((volatile uint32_t *)0x40032008)) -#define TIMER2_CTL_R (*((volatile uint32_t *)0x4003200C)) -#define TIMER2_SYNC_R (*((volatile uint32_t *)0x40032010)) -#define TIMER2_IMR_R (*((volatile uint32_t *)0x40032018)) -#define TIMER2_RIS_R (*((volatile uint32_t *)0x4003201C)) -#define TIMER2_MIS_R (*((volatile uint32_t *)0x40032020)) -#define TIMER2_ICR_R (*((volatile uint32_t *)0x40032024)) -#define TIMER2_TAILR_R (*((volatile uint32_t *)0x40032028)) -#define TIMER2_TBILR_R (*((volatile uint32_t *)0x4003202C)) -#define TIMER2_TAMATCHR_R (*((volatile uint32_t *)0x40032030)) -#define TIMER2_TBMATCHR_R (*((volatile uint32_t *)0x40032034)) -#define TIMER2_TAPR_R (*((volatile uint32_t *)0x40032038)) -#define TIMER2_TBPR_R (*((volatile uint32_t *)0x4003203C)) -#define TIMER2_TAPMR_R (*((volatile uint32_t *)0x40032040)) -#define TIMER2_TBPMR_R (*((volatile uint32_t *)0x40032044)) -#define TIMER2_TAR_R (*((volatile uint32_t *)0x40032048)) -#define TIMER2_TBR_R (*((volatile uint32_t *)0x4003204C)) -#define TIMER2_TAV_R (*((volatile uint32_t *)0x40032050)) -#define TIMER2_TBV_R (*((volatile uint32_t *)0x40032054)) -#define TIMER2_RTCPD_R (*((volatile uint32_t *)0x40032058)) -#define TIMER2_TAPS_R (*((volatile uint32_t *)0x4003205C)) -#define TIMER2_TBPS_R (*((volatile uint32_t *)0x40032060)) -#define TIMER2_DMAEV_R (*((volatile uint32_t *)0x4003206C)) -#define TIMER2_ADCEV_R (*((volatile uint32_t *)0x40032070)) -#define TIMER2_PP_R (*((volatile uint32_t *)0x40032FC0)) -#define TIMER2_CC_R (*((volatile uint32_t *)0x40032FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER3) -// -//***************************************************************************** -#define TIMER3_CFG_R (*((volatile uint32_t *)0x40033000)) -#define TIMER3_TAMR_R (*((volatile uint32_t *)0x40033004)) -#define TIMER3_TBMR_R (*((volatile uint32_t *)0x40033008)) -#define TIMER3_CTL_R (*((volatile uint32_t *)0x4003300C)) -#define TIMER3_SYNC_R (*((volatile uint32_t *)0x40033010)) -#define TIMER3_IMR_R (*((volatile uint32_t *)0x40033018)) -#define TIMER3_RIS_R (*((volatile uint32_t *)0x4003301C)) -#define TIMER3_MIS_R (*((volatile uint32_t *)0x40033020)) -#define TIMER3_ICR_R (*((volatile uint32_t *)0x40033024)) -#define TIMER3_TAILR_R (*((volatile uint32_t *)0x40033028)) -#define TIMER3_TBILR_R (*((volatile uint32_t *)0x4003302C)) -#define TIMER3_TAMATCHR_R (*((volatile uint32_t *)0x40033030)) -#define TIMER3_TBMATCHR_R (*((volatile uint32_t *)0x40033034)) -#define TIMER3_TAPR_R (*((volatile uint32_t *)0x40033038)) -#define TIMER3_TBPR_R (*((volatile uint32_t *)0x4003303C)) -#define TIMER3_TAPMR_R (*((volatile uint32_t *)0x40033040)) -#define TIMER3_TBPMR_R (*((volatile uint32_t *)0x40033044)) -#define TIMER3_TAR_R (*((volatile uint32_t *)0x40033048)) -#define TIMER3_TBR_R (*((volatile uint32_t *)0x4003304C)) -#define TIMER3_TAV_R (*((volatile uint32_t *)0x40033050)) -#define TIMER3_TBV_R (*((volatile uint32_t *)0x40033054)) -#define TIMER3_RTCPD_R (*((volatile uint32_t *)0x40033058)) -#define TIMER3_TAPS_R (*((volatile uint32_t *)0x4003305C)) -#define TIMER3_TBPS_R (*((volatile uint32_t *)0x40033060)) -#define TIMER3_DMAEV_R (*((volatile uint32_t *)0x4003306C)) -#define TIMER3_ADCEV_R (*((volatile uint32_t *)0x40033070)) -#define TIMER3_PP_R (*((volatile uint32_t *)0x40033FC0)) -#define TIMER3_CC_R (*((volatile uint32_t *)0x40033FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER4) -// -//***************************************************************************** -#define TIMER4_CFG_R (*((volatile uint32_t *)0x40034000)) -#define TIMER4_TAMR_R (*((volatile uint32_t *)0x40034004)) -#define TIMER4_TBMR_R (*((volatile uint32_t *)0x40034008)) -#define TIMER4_CTL_R (*((volatile uint32_t *)0x4003400C)) -#define TIMER4_SYNC_R (*((volatile uint32_t *)0x40034010)) -#define TIMER4_IMR_R (*((volatile uint32_t *)0x40034018)) -#define TIMER4_RIS_R (*((volatile uint32_t *)0x4003401C)) -#define TIMER4_MIS_R (*((volatile uint32_t *)0x40034020)) -#define TIMER4_ICR_R (*((volatile uint32_t *)0x40034024)) -#define TIMER4_TAILR_R (*((volatile uint32_t *)0x40034028)) -#define TIMER4_TBILR_R (*((volatile uint32_t *)0x4003402C)) -#define TIMER4_TAMATCHR_R (*((volatile uint32_t *)0x40034030)) -#define TIMER4_TBMATCHR_R (*((volatile uint32_t *)0x40034034)) -#define TIMER4_TAPR_R (*((volatile uint32_t *)0x40034038)) -#define TIMER4_TBPR_R (*((volatile uint32_t *)0x4003403C)) -#define TIMER4_TAPMR_R (*((volatile uint32_t *)0x40034040)) -#define TIMER4_TBPMR_R (*((volatile uint32_t *)0x40034044)) -#define TIMER4_TAR_R (*((volatile uint32_t *)0x40034048)) -#define TIMER4_TBR_R (*((volatile uint32_t *)0x4003404C)) -#define TIMER4_TAV_R (*((volatile uint32_t *)0x40034050)) -#define TIMER4_TBV_R (*((volatile uint32_t *)0x40034054)) -#define TIMER4_RTCPD_R (*((volatile uint32_t *)0x40034058)) -#define TIMER4_TAPS_R (*((volatile uint32_t *)0x4003405C)) -#define TIMER4_TBPS_R (*((volatile uint32_t *)0x40034060)) -#define TIMER4_DMAEV_R (*((volatile uint32_t *)0x4003406C)) -#define TIMER4_ADCEV_R (*((volatile uint32_t *)0x40034070)) -#define TIMER4_PP_R (*((volatile uint32_t *)0x40034FC0)) -#define TIMER4_CC_R (*((volatile uint32_t *)0x40034FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER5) -// -//***************************************************************************** -#define TIMER5_CFG_R (*((volatile uint32_t *)0x40035000)) -#define TIMER5_TAMR_R (*((volatile uint32_t *)0x40035004)) -#define TIMER5_TBMR_R (*((volatile uint32_t *)0x40035008)) -#define TIMER5_CTL_R (*((volatile uint32_t *)0x4003500C)) -#define TIMER5_SYNC_R (*((volatile uint32_t *)0x40035010)) -#define TIMER5_IMR_R (*((volatile uint32_t *)0x40035018)) -#define TIMER5_RIS_R (*((volatile uint32_t *)0x4003501C)) -#define TIMER5_MIS_R (*((volatile uint32_t *)0x40035020)) -#define TIMER5_ICR_R (*((volatile uint32_t *)0x40035024)) -#define TIMER5_TAILR_R (*((volatile uint32_t *)0x40035028)) -#define TIMER5_TBILR_R (*((volatile uint32_t *)0x4003502C)) -#define TIMER5_TAMATCHR_R (*((volatile uint32_t *)0x40035030)) -#define TIMER5_TBMATCHR_R (*((volatile uint32_t *)0x40035034)) -#define TIMER5_TAPR_R (*((volatile uint32_t *)0x40035038)) -#define TIMER5_TBPR_R (*((volatile uint32_t *)0x4003503C)) -#define TIMER5_TAPMR_R (*((volatile uint32_t *)0x40035040)) -#define TIMER5_TBPMR_R (*((volatile uint32_t *)0x40035044)) -#define TIMER5_TAR_R (*((volatile uint32_t *)0x40035048)) -#define TIMER5_TBR_R (*((volatile uint32_t *)0x4003504C)) -#define TIMER5_TAV_R (*((volatile uint32_t *)0x40035050)) -#define TIMER5_TBV_R (*((volatile uint32_t *)0x40035054)) -#define TIMER5_RTCPD_R (*((volatile uint32_t *)0x40035058)) -#define TIMER5_TAPS_R (*((volatile uint32_t *)0x4003505C)) -#define TIMER5_TBPS_R (*((volatile uint32_t *)0x40035060)) -#define TIMER5_DMAEV_R (*((volatile uint32_t *)0x4003506C)) -#define TIMER5_ADCEV_R (*((volatile uint32_t *)0x40035070)) -#define TIMER5_PP_R (*((volatile uint32_t *)0x40035FC0)) -#define TIMER5_CC_R (*((volatile uint32_t *)0x40035FC8)) - -//***************************************************************************** -// -// ADC registers (ADC0) -// -//***************************************************************************** -#define ADC0_ACTSS_R (*((volatile uint32_t *)0x40038000)) -#define ADC0_RIS_R (*((volatile uint32_t *)0x40038004)) -#define ADC0_IM_R (*((volatile uint32_t *)0x40038008)) -#define ADC0_ISC_R (*((volatile uint32_t *)0x4003800C)) -#define ADC0_OSTAT_R (*((volatile uint32_t *)0x40038010)) -#define ADC0_EMUX_R (*((volatile uint32_t *)0x40038014)) -#define ADC0_USTAT_R (*((volatile uint32_t *)0x40038018)) -#define ADC0_TSSEL_R (*((volatile uint32_t *)0x4003801C)) -#define ADC0_SSPRI_R (*((volatile uint32_t *)0x40038020)) -#define ADC0_SPC_R (*((volatile uint32_t *)0x40038024)) -#define ADC0_PSSI_R (*((volatile uint32_t *)0x40038028)) -#define ADC0_SAC_R (*((volatile uint32_t *)0x40038030)) -#define ADC0_DCISC_R (*((volatile uint32_t *)0x40038034)) -#define ADC0_CTL_R (*((volatile uint32_t *)0x40038038)) -#define ADC0_SSMUX0_R (*((volatile uint32_t *)0x40038040)) -#define ADC0_SSCTL0_R (*((volatile uint32_t *)0x40038044)) -#define ADC0_SSFIFO0_R (*((volatile uint32_t *)0x40038048)) -#define ADC0_SSFSTAT0_R (*((volatile uint32_t *)0x4003804C)) -#define ADC0_SSOP0_R (*((volatile uint32_t *)0x40038050)) -#define ADC0_SSDC0_R (*((volatile uint32_t *)0x40038054)) -#define ADC0_SSEMUX0_R (*((volatile uint32_t *)0x40038058)) -#define ADC0_SSTSH0_R (*((volatile uint32_t *)0x4003805C)) -#define ADC0_SSMUX1_R (*((volatile uint32_t *)0x40038060)) -#define ADC0_SSCTL1_R (*((volatile uint32_t *)0x40038064)) -#define ADC0_SSFIFO1_R (*((volatile uint32_t *)0x40038068)) -#define ADC0_SSFSTAT1_R (*((volatile uint32_t *)0x4003806C)) -#define ADC0_SSOP1_R (*((volatile uint32_t *)0x40038070)) -#define ADC0_SSDC1_R (*((volatile uint32_t *)0x40038074)) -#define ADC0_SSEMUX1_R (*((volatile uint32_t *)0x40038078)) -#define ADC0_SSTSH1_R (*((volatile uint32_t *)0x4003807C)) -#define ADC0_SSMUX2_R (*((volatile uint32_t *)0x40038080)) -#define ADC0_SSCTL2_R (*((volatile uint32_t *)0x40038084)) -#define ADC0_SSFIFO2_R (*((volatile uint32_t *)0x40038088)) -#define ADC0_SSFSTAT2_R (*((volatile uint32_t *)0x4003808C)) -#define ADC0_SSOP2_R (*((volatile uint32_t *)0x40038090)) -#define ADC0_SSDC2_R (*((volatile uint32_t *)0x40038094)) -#define ADC0_SSEMUX2_R (*((volatile uint32_t *)0x40038098)) -#define ADC0_SSTSH2_R (*((volatile uint32_t *)0x4003809C)) -#define ADC0_SSMUX3_R (*((volatile uint32_t *)0x400380A0)) -#define ADC0_SSCTL3_R (*((volatile uint32_t *)0x400380A4)) -#define ADC0_SSFIFO3_R (*((volatile uint32_t *)0x400380A8)) -#define ADC0_SSFSTAT3_R (*((volatile uint32_t *)0x400380AC)) -#define ADC0_SSOP3_R (*((volatile uint32_t *)0x400380B0)) -#define ADC0_SSDC3_R (*((volatile uint32_t *)0x400380B4)) -#define ADC0_SSEMUX3_R (*((volatile uint32_t *)0x400380B8)) -#define ADC0_SSTSH3_R (*((volatile uint32_t *)0x400380BC)) -#define ADC0_DCRIC_R (*((volatile uint32_t *)0x40038D00)) -#define ADC0_DCCTL0_R (*((volatile uint32_t *)0x40038E00)) -#define ADC0_DCCTL1_R (*((volatile uint32_t *)0x40038E04)) -#define ADC0_DCCTL2_R (*((volatile uint32_t *)0x40038E08)) -#define ADC0_DCCTL3_R (*((volatile uint32_t *)0x40038E0C)) -#define ADC0_DCCTL4_R (*((volatile uint32_t *)0x40038E10)) -#define ADC0_DCCTL5_R (*((volatile uint32_t *)0x40038E14)) -#define ADC0_DCCTL6_R (*((volatile uint32_t *)0x40038E18)) -#define ADC0_DCCTL7_R (*((volatile uint32_t *)0x40038E1C)) -#define ADC0_DCCMP0_R (*((volatile uint32_t *)0x40038E40)) -#define ADC0_DCCMP1_R (*((volatile uint32_t *)0x40038E44)) -#define ADC0_DCCMP2_R (*((volatile uint32_t *)0x40038E48)) -#define ADC0_DCCMP3_R (*((volatile uint32_t *)0x40038E4C)) -#define ADC0_DCCMP4_R (*((volatile uint32_t *)0x40038E50)) -#define ADC0_DCCMP5_R (*((volatile uint32_t *)0x40038E54)) -#define ADC0_DCCMP6_R (*((volatile uint32_t *)0x40038E58)) -#define ADC0_DCCMP7_R (*((volatile uint32_t *)0x40038E5C)) -#define ADC0_PP_R (*((volatile uint32_t *)0x40038FC0)) -#define ADC0_PC_R (*((volatile uint32_t *)0x40038FC4)) -#define ADC0_CC_R (*((volatile uint32_t *)0x40038FC8)) - -//***************************************************************************** -// -// ADC registers (ADC1) -// -//***************************************************************************** -#define ADC1_ACTSS_R (*((volatile uint32_t *)0x40039000)) -#define ADC1_RIS_R (*((volatile uint32_t *)0x40039004)) -#define ADC1_IM_R (*((volatile uint32_t *)0x40039008)) -#define ADC1_ISC_R (*((volatile uint32_t *)0x4003900C)) -#define ADC1_OSTAT_R (*((volatile uint32_t *)0x40039010)) -#define ADC1_EMUX_R (*((volatile uint32_t *)0x40039014)) -#define ADC1_USTAT_R (*((volatile uint32_t *)0x40039018)) -#define ADC1_TSSEL_R (*((volatile uint32_t *)0x4003901C)) -#define ADC1_SSPRI_R (*((volatile uint32_t *)0x40039020)) -#define ADC1_SPC_R (*((volatile uint32_t *)0x40039024)) -#define ADC1_PSSI_R (*((volatile uint32_t *)0x40039028)) -#define ADC1_SAC_R (*((volatile uint32_t *)0x40039030)) -#define ADC1_DCISC_R (*((volatile uint32_t *)0x40039034)) -#define ADC1_CTL_R (*((volatile uint32_t *)0x40039038)) -#define ADC1_SSMUX0_R (*((volatile uint32_t *)0x40039040)) -#define ADC1_SSCTL0_R (*((volatile uint32_t *)0x40039044)) -#define ADC1_SSFIFO0_R (*((volatile uint32_t *)0x40039048)) -#define ADC1_SSFSTAT0_R (*((volatile uint32_t *)0x4003904C)) -#define ADC1_SSOP0_R (*((volatile uint32_t *)0x40039050)) -#define ADC1_SSDC0_R (*((volatile uint32_t *)0x40039054)) -#define ADC1_SSEMUX0_R (*((volatile uint32_t *)0x40039058)) -#define ADC1_SSTSH0_R (*((volatile uint32_t *)0x4003905C)) -#define ADC1_SSMUX1_R (*((volatile uint32_t *)0x40039060)) -#define ADC1_SSCTL1_R (*((volatile uint32_t *)0x40039064)) -#define ADC1_SSFIFO1_R (*((volatile uint32_t *)0x40039068)) -#define ADC1_SSFSTAT1_R (*((volatile uint32_t *)0x4003906C)) -#define ADC1_SSOP1_R (*((volatile uint32_t *)0x40039070)) -#define ADC1_SSDC1_R (*((volatile uint32_t *)0x40039074)) -#define ADC1_SSEMUX1_R (*((volatile uint32_t *)0x40039078)) -#define ADC1_SSTSH1_R (*((volatile uint32_t *)0x4003907C)) -#define ADC1_SSMUX2_R (*((volatile uint32_t *)0x40039080)) -#define ADC1_SSCTL2_R (*((volatile uint32_t *)0x40039084)) -#define ADC1_SSFIFO2_R (*((volatile uint32_t *)0x40039088)) -#define ADC1_SSFSTAT2_R (*((volatile uint32_t *)0x4003908C)) -#define ADC1_SSOP2_R (*((volatile uint32_t *)0x40039090)) -#define ADC1_SSDC2_R (*((volatile uint32_t *)0x40039094)) -#define ADC1_SSEMUX2_R (*((volatile uint32_t *)0x40039098)) -#define ADC1_SSTSH2_R (*((volatile uint32_t *)0x4003909C)) -#define ADC1_SSMUX3_R (*((volatile uint32_t *)0x400390A0)) -#define ADC1_SSCTL3_R (*((volatile uint32_t *)0x400390A4)) -#define ADC1_SSFIFO3_R (*((volatile uint32_t *)0x400390A8)) -#define ADC1_SSFSTAT3_R (*((volatile uint32_t *)0x400390AC)) -#define ADC1_SSOP3_R (*((volatile uint32_t *)0x400390B0)) -#define ADC1_SSDC3_R (*((volatile uint32_t *)0x400390B4)) -#define ADC1_SSEMUX3_R (*((volatile uint32_t *)0x400390B8)) -#define ADC1_SSTSH3_R (*((volatile uint32_t *)0x400390BC)) -#define ADC1_DCRIC_R (*((volatile uint32_t *)0x40039D00)) -#define ADC1_DCCTL0_R (*((volatile uint32_t *)0x40039E00)) -#define ADC1_DCCTL1_R (*((volatile uint32_t *)0x40039E04)) -#define ADC1_DCCTL2_R (*((volatile uint32_t *)0x40039E08)) -#define ADC1_DCCTL3_R (*((volatile uint32_t *)0x40039E0C)) -#define ADC1_DCCTL4_R (*((volatile uint32_t *)0x40039E10)) -#define ADC1_DCCTL5_R (*((volatile uint32_t *)0x40039E14)) -#define ADC1_DCCTL6_R (*((volatile uint32_t *)0x40039E18)) -#define ADC1_DCCTL7_R (*((volatile uint32_t *)0x40039E1C)) -#define ADC1_DCCMP0_R (*((volatile uint32_t *)0x40039E40)) -#define ADC1_DCCMP1_R (*((volatile uint32_t *)0x40039E44)) -#define ADC1_DCCMP2_R (*((volatile uint32_t *)0x40039E48)) -#define ADC1_DCCMP3_R (*((volatile uint32_t *)0x40039E4C)) -#define ADC1_DCCMP4_R (*((volatile uint32_t *)0x40039E50)) -#define ADC1_DCCMP5_R (*((volatile uint32_t *)0x40039E54)) -#define ADC1_DCCMP6_R (*((volatile uint32_t *)0x40039E58)) -#define ADC1_DCCMP7_R (*((volatile uint32_t *)0x40039E5C)) -#define ADC1_PP_R (*((volatile uint32_t *)0x40039FC0)) -#define ADC1_PC_R (*((volatile uint32_t *)0x40039FC4)) -#define ADC1_CC_R (*((volatile uint32_t *)0x40039FC8)) - -//***************************************************************************** -// -// Comparator registers (COMP) -// -//***************************************************************************** -#define COMP_ACMIS_R (*((volatile uint32_t *)0x4003C000)) -#define COMP_ACRIS_R (*((volatile uint32_t *)0x4003C004)) -#define COMP_ACINTEN_R (*((volatile uint32_t *)0x4003C008)) -#define COMP_ACREFCTL_R (*((volatile uint32_t *)0x4003C010)) -#define COMP_ACSTAT0_R (*((volatile uint32_t *)0x4003C020)) -#define COMP_ACCTL0_R (*((volatile uint32_t *)0x4003C024)) -#define COMP_ACSTAT1_R (*((volatile uint32_t *)0x4003C040)) -#define COMP_ACCTL1_R (*((volatile uint32_t *)0x4003C044)) -#define COMP_ACSTAT2_R (*((volatile uint32_t *)0x4003C060)) -#define COMP_ACCTL2_R (*((volatile uint32_t *)0x4003C064)) -#define COMP_PP_R (*((volatile uint32_t *)0x4003CFC0)) - -//***************************************************************************** -// -// CAN registers (CAN0) -// -//***************************************************************************** -#define CAN0_CTL_R (*((volatile uint32_t *)0x40040000)) -#define CAN0_STS_R (*((volatile uint32_t *)0x40040004)) -#define CAN0_ERR_R (*((volatile uint32_t *)0x40040008)) -#define CAN0_BIT_R (*((volatile uint32_t *)0x4004000C)) -#define CAN0_INT_R (*((volatile uint32_t *)0x40040010)) -#define CAN0_TST_R (*((volatile uint32_t *)0x40040014)) -#define CAN0_BRPE_R (*((volatile uint32_t *)0x40040018)) -#define CAN0_IF1CRQ_R (*((volatile uint32_t *)0x40040020)) -#define CAN0_IF1CMSK_R (*((volatile uint32_t *)0x40040024)) -#define CAN0_IF1MSK1_R (*((volatile uint32_t *)0x40040028)) -#define CAN0_IF1MSK2_R (*((volatile uint32_t *)0x4004002C)) -#define CAN0_IF1ARB1_R (*((volatile uint32_t *)0x40040030)) -#define CAN0_IF1ARB2_R (*((volatile uint32_t *)0x40040034)) -#define CAN0_IF1MCTL_R (*((volatile uint32_t *)0x40040038)) -#define CAN0_IF1DA1_R (*((volatile uint32_t *)0x4004003C)) -#define CAN0_IF1DA2_R (*((volatile uint32_t *)0x40040040)) -#define CAN0_IF1DB1_R (*((volatile uint32_t *)0x40040044)) -#define CAN0_IF1DB2_R (*((volatile uint32_t *)0x40040048)) -#define CAN0_IF2CRQ_R (*((volatile uint32_t *)0x40040080)) -#define CAN0_IF2CMSK_R (*((volatile uint32_t *)0x40040084)) -#define CAN0_IF2MSK1_R (*((volatile uint32_t *)0x40040088)) -#define CAN0_IF2MSK2_R (*((volatile uint32_t *)0x4004008C)) -#define CAN0_IF2ARB1_R (*((volatile uint32_t *)0x40040090)) -#define CAN0_IF2ARB2_R (*((volatile uint32_t *)0x40040094)) -#define CAN0_IF2MCTL_R (*((volatile uint32_t *)0x40040098)) -#define CAN0_IF2DA1_R (*((volatile uint32_t *)0x4004009C)) -#define CAN0_IF2DA2_R (*((volatile uint32_t *)0x400400A0)) -#define CAN0_IF2DB1_R (*((volatile uint32_t *)0x400400A4)) -#define CAN0_IF2DB2_R (*((volatile uint32_t *)0x400400A8)) -#define CAN0_TXRQ1_R (*((volatile uint32_t *)0x40040100)) -#define CAN0_TXRQ2_R (*((volatile uint32_t *)0x40040104)) -#define CAN0_NWDA1_R (*((volatile uint32_t *)0x40040120)) -#define CAN0_NWDA2_R (*((volatile uint32_t *)0x40040124)) -#define CAN0_MSG1INT_R (*((volatile uint32_t *)0x40040140)) -#define CAN0_MSG2INT_R (*((volatile uint32_t *)0x40040144)) -#define CAN0_MSG1VAL_R (*((volatile uint32_t *)0x40040160)) -#define CAN0_MSG2VAL_R (*((volatile uint32_t *)0x40040164)) - -//***************************************************************************** -// -// CAN registers (CAN1) -// -//***************************************************************************** -#define CAN1_CTL_R (*((volatile uint32_t *)0x40041000)) -#define CAN1_STS_R (*((volatile uint32_t *)0x40041004)) -#define CAN1_ERR_R (*((volatile uint32_t *)0x40041008)) -#define CAN1_BIT_R (*((volatile uint32_t *)0x4004100C)) -#define CAN1_INT_R (*((volatile uint32_t *)0x40041010)) -#define CAN1_TST_R (*((volatile uint32_t *)0x40041014)) -#define CAN1_BRPE_R (*((volatile uint32_t *)0x40041018)) -#define CAN1_IF1CRQ_R (*((volatile uint32_t *)0x40041020)) -#define CAN1_IF1CMSK_R (*((volatile uint32_t *)0x40041024)) -#define CAN1_IF1MSK1_R (*((volatile uint32_t *)0x40041028)) -#define CAN1_IF1MSK2_R (*((volatile uint32_t *)0x4004102C)) -#define CAN1_IF1ARB1_R (*((volatile uint32_t *)0x40041030)) -#define CAN1_IF1ARB2_R (*((volatile uint32_t *)0x40041034)) -#define CAN1_IF1MCTL_R (*((volatile uint32_t *)0x40041038)) -#define CAN1_IF1DA1_R (*((volatile uint32_t *)0x4004103C)) -#define CAN1_IF1DA2_R (*((volatile uint32_t *)0x40041040)) -#define CAN1_IF1DB1_R (*((volatile uint32_t *)0x40041044)) -#define CAN1_IF1DB2_R (*((volatile uint32_t *)0x40041048)) -#define CAN1_IF2CRQ_R (*((volatile uint32_t *)0x40041080)) -#define CAN1_IF2CMSK_R (*((volatile uint32_t *)0x40041084)) -#define CAN1_IF2MSK1_R (*((volatile uint32_t *)0x40041088)) -#define CAN1_IF2MSK2_R (*((volatile uint32_t *)0x4004108C)) -#define CAN1_IF2ARB1_R (*((volatile uint32_t *)0x40041090)) -#define CAN1_IF2ARB2_R (*((volatile uint32_t *)0x40041094)) -#define CAN1_IF2MCTL_R (*((volatile uint32_t *)0x40041098)) -#define CAN1_IF2DA1_R (*((volatile uint32_t *)0x4004109C)) -#define CAN1_IF2DA2_R (*((volatile uint32_t *)0x400410A0)) -#define CAN1_IF2DB1_R (*((volatile uint32_t *)0x400410A4)) -#define CAN1_IF2DB2_R (*((volatile uint32_t *)0x400410A8)) -#define CAN1_TXRQ1_R (*((volatile uint32_t *)0x40041100)) -#define CAN1_TXRQ2_R (*((volatile uint32_t *)0x40041104)) -#define CAN1_NWDA1_R (*((volatile uint32_t *)0x40041120)) -#define CAN1_NWDA2_R (*((volatile uint32_t *)0x40041124)) -#define CAN1_MSG1INT_R (*((volatile uint32_t *)0x40041140)) -#define CAN1_MSG2INT_R (*((volatile uint32_t *)0x40041144)) -#define CAN1_MSG1VAL_R (*((volatile uint32_t *)0x40041160)) -#define CAN1_MSG2VAL_R (*((volatile uint32_t *)0x40041164)) - -//***************************************************************************** -// -// Univeral Serial Bus registers (USB0) -// -//***************************************************************************** -#define USB0_FADDR_R (*((volatile uint8_t *)0x40050000)) -#define USB0_POWER_R (*((volatile uint8_t *)0x40050001)) -#define USB0_TXIS_R (*((volatile uint16_t *)0x40050002)) -#define USB0_RXIS_R (*((volatile uint16_t *)0x40050004)) -#define USB0_TXIE_R (*((volatile uint16_t *)0x40050006)) -#define USB0_RXIE_R (*((volatile uint16_t *)0x40050008)) -#define USB0_IS_R (*((volatile uint8_t *)0x4005000A)) -#define USB0_IE_R (*((volatile uint8_t *)0x4005000B)) -#define USB0_FRAME_R (*((volatile uint16_t *)0x4005000C)) -#define USB0_EPIDX_R (*((volatile uint8_t *)0x4005000E)) -#define USB0_TEST_R (*((volatile uint8_t *)0x4005000F)) -#define USB0_FIFO0_R (*((volatile uint32_t *)0x40050020)) -#define USB0_FIFO1_R (*((volatile uint32_t *)0x40050024)) -#define USB0_FIFO2_R (*((volatile uint32_t *)0x40050028)) -#define USB0_FIFO3_R (*((volatile uint32_t *)0x4005002C)) -#define USB0_FIFO4_R (*((volatile uint32_t *)0x40050030)) -#define USB0_FIFO5_R (*((volatile uint32_t *)0x40050034)) -#define USB0_FIFO6_R (*((volatile uint32_t *)0x40050038)) -#define USB0_FIFO7_R (*((volatile uint32_t *)0x4005003C)) -#define USB0_DEVCTL_R (*((volatile uint8_t *)0x40050060)) -#define USB0_CCONF_R (*((volatile uint8_t *)0x40050061)) -#define USB0_TXFIFOSZ_R (*((volatile uint8_t *)0x40050062)) -#define USB0_RXFIFOSZ_R (*((volatile uint8_t *)0x40050063)) -#define USB0_TXFIFOADD_R (*((volatile uint16_t *)0x40050064)) -#define USB0_RXFIFOADD_R (*((volatile uint16_t *)0x40050066)) -#define USB0_ULPIVBUSCTL_R (*((volatile uint8_t *)0x40050070)) -#define USB0_ULPIREGDATA_R (*((volatile uint8_t *)0x40050074)) -#define USB0_ULPIREGADDR_R (*((volatile uint8_t *)0x40050075)) -#define USB0_ULPIREGCTL_R (*((volatile uint8_t *)0x40050076)) -#define USB0_EPINFO_R (*((volatile uint8_t *)0x40050078)) -#define USB0_RAMINFO_R (*((volatile uint8_t *)0x40050079)) -#define USB0_CONTIM_R (*((volatile uint8_t *)0x4005007A)) -#define USB0_VPLEN_R (*((volatile uint8_t *)0x4005007B)) -#define USB0_HSEOF_R (*((volatile uint8_t *)0x4005007C)) -#define USB0_FSEOF_R (*((volatile uint8_t *)0x4005007D)) -#define USB0_LSEOF_R (*((volatile uint8_t *)0x4005007E)) -#define USB0_TXFUNCADDR0_R (*((volatile uint8_t *)0x40050080)) -#define USB0_TXHUBADDR0_R (*((volatile uint8_t *)0x40050082)) -#define USB0_TXHUBPORT0_R (*((volatile uint8_t *)0x40050083)) -#define USB0_TXFUNCADDR1_R (*((volatile uint8_t *)0x40050088)) -#define USB0_TXHUBADDR1_R (*((volatile uint8_t *)0x4005008A)) -#define USB0_TXHUBPORT1_R (*((volatile uint8_t *)0x4005008B)) -#define USB0_RXFUNCADDR1_R (*((volatile uint8_t *)0x4005008C)) -#define USB0_RXHUBADDR1_R (*((volatile uint8_t *)0x4005008E)) -#define USB0_RXHUBPORT1_R (*((volatile uint8_t *)0x4005008F)) -#define USB0_TXFUNCADDR2_R (*((volatile uint8_t *)0x40050090)) -#define USB0_TXHUBADDR2_R (*((volatile uint8_t *)0x40050092)) -#define USB0_TXHUBPORT2_R (*((volatile uint8_t *)0x40050093)) -#define USB0_RXFUNCADDR2_R (*((volatile uint8_t *)0x40050094)) -#define USB0_RXHUBADDR2_R (*((volatile uint8_t *)0x40050096)) -#define USB0_RXHUBPORT2_R (*((volatile uint8_t *)0x40050097)) -#define USB0_TXFUNCADDR3_R (*((volatile uint8_t *)0x40050098)) -#define USB0_TXHUBADDR3_R (*((volatile uint8_t *)0x4005009A)) -#define USB0_TXHUBPORT3_R (*((volatile uint8_t *)0x4005009B)) -#define USB0_RXFUNCADDR3_R (*((volatile uint8_t *)0x4005009C)) -#define USB0_RXHUBADDR3_R (*((volatile uint8_t *)0x4005009E)) -#define USB0_RXHUBPORT3_R (*((volatile uint8_t *)0x4005009F)) -#define USB0_TXFUNCADDR4_R (*((volatile uint8_t *)0x400500A0)) -#define USB0_TXHUBADDR4_R (*((volatile uint8_t *)0x400500A2)) -#define USB0_TXHUBPORT4_R (*((volatile uint8_t *)0x400500A3)) -#define USB0_RXFUNCADDR4_R (*((volatile uint8_t *)0x400500A4)) -#define USB0_RXHUBADDR4_R (*((volatile uint8_t *)0x400500A6)) -#define USB0_RXHUBPORT4_R (*((volatile uint8_t *)0x400500A7)) -#define USB0_TXFUNCADDR5_R (*((volatile uint8_t *)0x400500A8)) -#define USB0_TXHUBADDR5_R (*((volatile uint8_t *)0x400500AA)) -#define USB0_TXHUBPORT5_R (*((volatile uint8_t *)0x400500AB)) -#define USB0_RXFUNCADDR5_R (*((volatile uint8_t *)0x400500AC)) -#define USB0_RXHUBADDR5_R (*((volatile uint8_t *)0x400500AE)) -#define USB0_RXHUBPORT5_R (*((volatile uint8_t *)0x400500AF)) -#define USB0_TXFUNCADDR6_R (*((volatile uint8_t *)0x400500B0)) -#define USB0_TXHUBADDR6_R (*((volatile uint8_t *)0x400500B2)) -#define USB0_TXHUBPORT6_R (*((volatile uint8_t *)0x400500B3)) -#define USB0_RXFUNCADDR6_R (*((volatile uint8_t *)0x400500B4)) -#define USB0_RXHUBADDR6_R (*((volatile uint8_t *)0x400500B6)) -#define USB0_RXHUBPORT6_R (*((volatile uint8_t *)0x400500B7)) -#define USB0_TXFUNCADDR7_R (*((volatile uint8_t *)0x400500B8)) -#define USB0_TXHUBADDR7_R (*((volatile uint8_t *)0x400500BA)) -#define USB0_TXHUBPORT7_R (*((volatile uint8_t *)0x400500BB)) -#define USB0_RXFUNCADDR7_R (*((volatile uint8_t *)0x400500BC)) -#define USB0_RXHUBADDR7_R (*((volatile uint8_t *)0x400500BE)) -#define USB0_RXHUBPORT7_R (*((volatile uint8_t *)0x400500BF)) -#define USB0_CSRL0_R (*((volatile uint8_t *)0x40050102)) -#define USB0_CSRH0_R (*((volatile uint8_t *)0x40050103)) -#define USB0_COUNT0_R (*((volatile uint8_t *)0x40050108)) -#define USB0_TYPE0_R (*((volatile uint8_t *)0x4005010A)) -#define USB0_NAKLMT_R (*((volatile uint8_t *)0x4005010B)) -#define USB0_TXMAXP1_R (*((volatile uint16_t *)0x40050110)) -#define USB0_TXCSRL1_R (*((volatile uint8_t *)0x40050112)) -#define USB0_TXCSRH1_R (*((volatile uint8_t *)0x40050113)) -#define USB0_RXMAXP1_R (*((volatile uint16_t *)0x40050114)) -#define USB0_RXCSRL1_R (*((volatile uint8_t *)0x40050116)) -#define USB0_RXCSRH1_R (*((volatile uint8_t *)0x40050117)) -#define USB0_RXCOUNT1_R (*((volatile uint16_t *)0x40050118)) -#define USB0_TXTYPE1_R (*((volatile uint8_t *)0x4005011A)) -#define USB0_TXINTERVAL1_R (*((volatile uint8_t *)0x4005011B)) -#define USB0_RXTYPE1_R (*((volatile uint8_t *)0x4005011C)) -#define USB0_RXINTERVAL1_R (*((volatile uint8_t *)0x4005011D)) -#define USB0_TXMAXP2_R (*((volatile uint16_t *)0x40050120)) -#define USB0_TXCSRL2_R (*((volatile uint8_t *)0x40050122)) -#define USB0_TXCSRH2_R (*((volatile uint8_t *)0x40050123)) -#define USB0_RXMAXP2_R (*((volatile uint16_t *)0x40050124)) -#define USB0_RXCSRL2_R (*((volatile uint8_t *)0x40050126)) -#define USB0_RXCSRH2_R (*((volatile uint8_t *)0x40050127)) -#define USB0_RXCOUNT2_R (*((volatile uint16_t *)0x40050128)) -#define USB0_TXTYPE2_R (*((volatile uint8_t *)0x4005012A)) -#define USB0_TXINTERVAL2_R (*((volatile uint8_t *)0x4005012B)) -#define USB0_RXTYPE2_R (*((volatile uint8_t *)0x4005012C)) -#define USB0_RXINTERVAL2_R (*((volatile uint8_t *)0x4005012D)) -#define USB0_TXMAXP3_R (*((volatile uint16_t *)0x40050130)) -#define USB0_TXCSRL3_R (*((volatile uint8_t *)0x40050132)) -#define USB0_TXCSRH3_R (*((volatile uint8_t *)0x40050133)) -#define USB0_RXMAXP3_R (*((volatile uint16_t *)0x40050134)) -#define USB0_RXCSRL3_R (*((volatile uint8_t *)0x40050136)) -#define USB0_RXCSRH3_R (*((volatile uint8_t *)0x40050137)) -#define USB0_RXCOUNT3_R (*((volatile uint16_t *)0x40050138)) -#define USB0_TXTYPE3_R (*((volatile uint8_t *)0x4005013A)) -#define USB0_TXINTERVAL3_R (*((volatile uint8_t *)0x4005013B)) -#define USB0_RXTYPE3_R (*((volatile uint8_t *)0x4005013C)) -#define USB0_RXINTERVAL3_R (*((volatile uint8_t *)0x4005013D)) -#define USB0_TXMAXP4_R (*((volatile uint16_t *)0x40050140)) -#define USB0_TXCSRL4_R (*((volatile uint8_t *)0x40050142)) -#define USB0_TXCSRH4_R (*((volatile uint8_t *)0x40050143)) -#define USB0_RXMAXP4_R (*((volatile uint16_t *)0x40050144)) -#define USB0_RXCSRL4_R (*((volatile uint8_t *)0x40050146)) -#define USB0_RXCSRH4_R (*((volatile uint8_t *)0x40050147)) -#define USB0_RXCOUNT4_R (*((volatile uint16_t *)0x40050148)) -#define USB0_TXTYPE4_R (*((volatile uint8_t *)0x4005014A)) -#define USB0_TXINTERVAL4_R (*((volatile uint8_t *)0x4005014B)) -#define USB0_RXTYPE4_R (*((volatile uint8_t *)0x4005014C)) -#define USB0_RXINTERVAL4_R (*((volatile uint8_t *)0x4005014D)) -#define USB0_TXMAXP5_R (*((volatile uint16_t *)0x40050150)) -#define USB0_TXCSRL5_R (*((volatile uint8_t *)0x40050152)) -#define USB0_TXCSRH5_R (*((volatile uint8_t *)0x40050153)) -#define USB0_RXMAXP5_R (*((volatile uint16_t *)0x40050154)) -#define USB0_RXCSRL5_R (*((volatile uint8_t *)0x40050156)) -#define USB0_RXCSRH5_R (*((volatile uint8_t *)0x40050157)) -#define USB0_RXCOUNT5_R (*((volatile uint16_t *)0x40050158)) -#define USB0_TXTYPE5_R (*((volatile uint8_t *)0x4005015A)) -#define USB0_TXINTERVAL5_R (*((volatile uint8_t *)0x4005015B)) -#define USB0_RXTYPE5_R (*((volatile uint8_t *)0x4005015C)) -#define USB0_RXINTERVAL5_R (*((volatile uint8_t *)0x4005015D)) -#define USB0_TXMAXP6_R (*((volatile uint16_t *)0x40050160)) -#define USB0_TXCSRL6_R (*((volatile uint8_t *)0x40050162)) -#define USB0_TXCSRH6_R (*((volatile uint8_t *)0x40050163)) -#define USB0_RXMAXP6_R (*((volatile uint16_t *)0x40050164)) -#define USB0_RXCSRL6_R (*((volatile uint8_t *)0x40050166)) -#define USB0_RXCSRH6_R (*((volatile uint8_t *)0x40050167)) -#define USB0_RXCOUNT6_R (*((volatile uint16_t *)0x40050168)) -#define USB0_TXTYPE6_R (*((volatile uint8_t *)0x4005016A)) -#define USB0_TXINTERVAL6_R (*((volatile uint8_t *)0x4005016B)) -#define USB0_RXTYPE6_R (*((volatile uint8_t *)0x4005016C)) -#define USB0_RXINTERVAL6_R (*((volatile uint8_t *)0x4005016D)) -#define USB0_TXMAXP7_R (*((volatile uint16_t *)0x40050170)) -#define USB0_TXCSRL7_R (*((volatile uint8_t *)0x40050172)) -#define USB0_TXCSRH7_R (*((volatile uint8_t *)0x40050173)) -#define USB0_RXMAXP7_R (*((volatile uint16_t *)0x40050174)) -#define USB0_RXCSRL7_R (*((volatile uint8_t *)0x40050176)) -#define USB0_RXCSRH7_R (*((volatile uint8_t *)0x40050177)) -#define USB0_RXCOUNT7_R (*((volatile uint16_t *)0x40050178)) -#define USB0_TXTYPE7_R (*((volatile uint8_t *)0x4005017A)) -#define USB0_TXINTERVAL7_R (*((volatile uint8_t *)0x4005017B)) -#define USB0_RXTYPE7_R (*((volatile uint8_t *)0x4005017C)) -#define USB0_RXINTERVAL7_R (*((volatile uint8_t *)0x4005017D)) -#define USB0_DMAINTR_R (*((volatile uint8_t *)0x40050200)) -#define USB0_DMACTL0_R (*((volatile uint16_t *)0x40050204)) -#define USB0_DMAADDR0_R (*((volatile uint32_t *)0x40050208)) -#define USB0_DMACOUNT0_R (*((volatile uint32_t *)0x4005020C)) -#define USB0_DMACTL1_R (*((volatile uint16_t *)0x40050214)) -#define USB0_DMAADDR1_R (*((volatile uint32_t *)0x40050218)) -#define USB0_DMACOUNT1_R (*((volatile uint32_t *)0x4005021C)) -#define USB0_DMACTL2_R (*((volatile uint16_t *)0x40050224)) -#define USB0_DMAADDR2_R (*((volatile uint32_t *)0x40050228)) -#define USB0_DMACOUNT2_R (*((volatile uint32_t *)0x4005022C)) -#define USB0_DMACTL3_R (*((volatile uint16_t *)0x40050234)) -#define USB0_DMAADDR3_R (*((volatile uint32_t *)0x40050238)) -#define USB0_DMACOUNT3_R (*((volatile uint32_t *)0x4005023C)) -#define USB0_DMACTL4_R (*((volatile uint16_t *)0x40050244)) -#define USB0_DMAADDR4_R (*((volatile uint32_t *)0x40050248)) -#define USB0_DMACOUNT4_R (*((volatile uint32_t *)0x4005024C)) -#define USB0_DMACTL5_R (*((volatile uint16_t *)0x40050254)) -#define USB0_DMAADDR5_R (*((volatile uint32_t *)0x40050258)) -#define USB0_DMACOUNT5_R (*((volatile uint32_t *)0x4005025C)) -#define USB0_DMACTL6_R (*((volatile uint16_t *)0x40050264)) -#define USB0_DMAADDR6_R (*((volatile uint32_t *)0x40050268)) -#define USB0_DMACOUNT6_R (*((volatile uint32_t *)0x4005026C)) -#define USB0_DMACTL7_R (*((volatile uint16_t *)0x40050274)) -#define USB0_DMAADDR7_R (*((volatile uint32_t *)0x40050278)) -#define USB0_DMACOUNT7_R (*((volatile uint32_t *)0x4005027C)) -#define USB0_RQPKTCOUNT1_R (*((volatile uint16_t *)0x40050304)) -#define USB0_RQPKTCOUNT2_R (*((volatile uint16_t *)0x40050308)) -#define USB0_RQPKTCOUNT3_R (*((volatile uint16_t *)0x4005030C)) -#define USB0_RQPKTCOUNT4_R (*((volatile uint16_t *)0x40050310)) -#define USB0_RQPKTCOUNT5_R (*((volatile uint16_t *)0x40050314)) -#define USB0_RQPKTCOUNT6_R (*((volatile uint16_t *)0x40050318)) -#define USB0_RQPKTCOUNT7_R (*((volatile uint16_t *)0x4005031C)) -#define USB0_RXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050340)) -#define USB0_TXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050342)) -#define USB0_CTO_R (*((volatile uint16_t *)0x40050344)) -#define USB0_HHSRTN_R (*((volatile uint16_t *)0x40050346)) -#define USB0_HSBT_R (*((volatile uint16_t *)0x40050348)) -#define USB0_LPMATTR_R (*((volatile uint16_t *)0x40050360)) -#define USB0_LPMCNTRL_R (*((volatile uint8_t *)0x40050362)) -#define USB0_LPMIM_R (*((volatile uint8_t *)0x40050363)) -#define USB0_LPMRIS_R (*((volatile uint8_t *)0x40050364)) -#define USB0_LPMFADDR_R (*((volatile uint8_t *)0x40050365)) -#define USB0_EPC_R (*((volatile uint32_t *)0x40050400)) -#define USB0_EPCRIS_R (*((volatile uint32_t *)0x40050404)) -#define USB0_EPCIM_R (*((volatile uint32_t *)0x40050408)) -#define USB0_EPCISC_R (*((volatile uint32_t *)0x4005040C)) -#define USB0_DRRIS_R (*((volatile uint32_t *)0x40050410)) -#define USB0_DRIM_R (*((volatile uint32_t *)0x40050414)) -#define USB0_DRISC_R (*((volatile uint32_t *)0x40050418)) -#define USB0_GPCS_R (*((volatile uint32_t *)0x4005041C)) -#define USB0_VDC_R (*((volatile uint32_t *)0x40050430)) -#define USB0_VDCRIS_R (*((volatile uint32_t *)0x40050434)) -#define USB0_VDCIM_R (*((volatile uint32_t *)0x40050438)) -#define USB0_VDCISC_R (*((volatile uint32_t *)0x4005043C)) -#define USB0_PP_R (*((volatile uint32_t *)0x40050FC0)) -#define USB0_PC_R (*((volatile uint32_t *)0x40050FC4)) -#define USB0_CC_R (*((volatile uint32_t *)0x40050FC8)) - -//***************************************************************************** -// -// GPIO registers (PORTA AHB) -// -//***************************************************************************** -#define GPIO_PORTA_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x40058000) -#define GPIO_PORTA_AHB_DATA_R (*((volatile uint32_t *)0x400583FC)) -#define GPIO_PORTA_AHB_DIR_R (*((volatile uint32_t *)0x40058400)) -#define GPIO_PORTA_AHB_IS_R (*((volatile uint32_t *)0x40058404)) -#define GPIO_PORTA_AHB_IBE_R (*((volatile uint32_t *)0x40058408)) -#define GPIO_PORTA_AHB_IEV_R (*((volatile uint32_t *)0x4005840C)) -#define GPIO_PORTA_AHB_IM_R (*((volatile uint32_t *)0x40058410)) -#define GPIO_PORTA_AHB_RIS_R (*((volatile uint32_t *)0x40058414)) -#define GPIO_PORTA_AHB_MIS_R (*((volatile uint32_t *)0x40058418)) -#define GPIO_PORTA_AHB_ICR_R (*((volatile uint32_t *)0x4005841C)) -#define GPIO_PORTA_AHB_AFSEL_R (*((volatile uint32_t *)0x40058420)) -#define GPIO_PORTA_AHB_DR2R_R (*((volatile uint32_t *)0x40058500)) -#define GPIO_PORTA_AHB_DR4R_R (*((volatile uint32_t *)0x40058504)) -#define GPIO_PORTA_AHB_DR8R_R (*((volatile uint32_t *)0x40058508)) -#define GPIO_PORTA_AHB_ODR_R (*((volatile uint32_t *)0x4005850C)) -#define GPIO_PORTA_AHB_PUR_R (*((volatile uint32_t *)0x40058510)) -#define GPIO_PORTA_AHB_PDR_R (*((volatile uint32_t *)0x40058514)) -#define GPIO_PORTA_AHB_SLR_R (*((volatile uint32_t *)0x40058518)) -#define GPIO_PORTA_AHB_DEN_R (*((volatile uint32_t *)0x4005851C)) -#define GPIO_PORTA_AHB_LOCK_R (*((volatile uint32_t *)0x40058520)) -#define GPIO_PORTA_AHB_CR_R (*((volatile uint32_t *)0x40058524)) -#define GPIO_PORTA_AHB_AMSEL_R (*((volatile uint32_t *)0x40058528)) -#define GPIO_PORTA_AHB_PCTL_R (*((volatile uint32_t *)0x4005852C)) -#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile uint32_t *)0x40058530)) -#define GPIO_PORTA_AHB_DMACTL_R (*((volatile uint32_t *)0x40058534)) -#define GPIO_PORTA_AHB_SI_R (*((volatile uint32_t *)0x40058538)) -#define GPIO_PORTA_AHB_DR12R_R (*((volatile uint32_t *)0x4005853C)) -#define GPIO_PORTA_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x40058540)) -#define GPIO_PORTA_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x40058544)) -#define GPIO_PORTA_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x40058548)) -#define GPIO_PORTA_AHB_PP_R (*((volatile uint32_t *)0x40058FC0)) -#define GPIO_PORTA_AHB_PC_R (*((volatile uint32_t *)0x40058FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTB AHB) -// -//***************************************************************************** -#define GPIO_PORTB_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x40059000) -#define GPIO_PORTB_AHB_DATA_R (*((volatile uint32_t *)0x400593FC)) -#define GPIO_PORTB_AHB_DIR_R (*((volatile uint32_t *)0x40059400)) -#define GPIO_PORTB_AHB_IS_R (*((volatile uint32_t *)0x40059404)) -#define GPIO_PORTB_AHB_IBE_R (*((volatile uint32_t *)0x40059408)) -#define GPIO_PORTB_AHB_IEV_R (*((volatile uint32_t *)0x4005940C)) -#define GPIO_PORTB_AHB_IM_R (*((volatile uint32_t *)0x40059410)) -#define GPIO_PORTB_AHB_RIS_R (*((volatile uint32_t *)0x40059414)) -#define GPIO_PORTB_AHB_MIS_R (*((volatile uint32_t *)0x40059418)) -#define GPIO_PORTB_AHB_ICR_R (*((volatile uint32_t *)0x4005941C)) -#define GPIO_PORTB_AHB_AFSEL_R (*((volatile uint32_t *)0x40059420)) -#define GPIO_PORTB_AHB_DR2R_R (*((volatile uint32_t *)0x40059500)) -#define GPIO_PORTB_AHB_DR4R_R (*((volatile uint32_t *)0x40059504)) -#define GPIO_PORTB_AHB_DR8R_R (*((volatile uint32_t *)0x40059508)) -#define GPIO_PORTB_AHB_ODR_R (*((volatile uint32_t *)0x4005950C)) -#define GPIO_PORTB_AHB_PUR_R (*((volatile uint32_t *)0x40059510)) -#define GPIO_PORTB_AHB_PDR_R (*((volatile uint32_t *)0x40059514)) -#define GPIO_PORTB_AHB_SLR_R (*((volatile uint32_t *)0x40059518)) -#define GPIO_PORTB_AHB_DEN_R (*((volatile uint32_t *)0x4005951C)) -#define GPIO_PORTB_AHB_LOCK_R (*((volatile uint32_t *)0x40059520)) -#define GPIO_PORTB_AHB_CR_R (*((volatile uint32_t *)0x40059524)) -#define GPIO_PORTB_AHB_AMSEL_R (*((volatile uint32_t *)0x40059528)) -#define GPIO_PORTB_AHB_PCTL_R (*((volatile uint32_t *)0x4005952C)) -#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile uint32_t *)0x40059530)) -#define GPIO_PORTB_AHB_DMACTL_R (*((volatile uint32_t *)0x40059534)) -#define GPIO_PORTB_AHB_SI_R (*((volatile uint32_t *)0x40059538)) -#define GPIO_PORTB_AHB_DR12R_R (*((volatile uint32_t *)0x4005953C)) -#define GPIO_PORTB_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x40059540)) -#define GPIO_PORTB_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x40059544)) -#define GPIO_PORTB_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x40059548)) -#define GPIO_PORTB_AHB_PP_R (*((volatile uint32_t *)0x40059FC0)) -#define GPIO_PORTB_AHB_PC_R (*((volatile uint32_t *)0x40059FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTC AHB) -// -//***************************************************************************** -#define GPIO_PORTC_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005A000) -#define GPIO_PORTC_AHB_DATA_R (*((volatile uint32_t *)0x4005A3FC)) -#define GPIO_PORTC_AHB_DIR_R (*((volatile uint32_t *)0x4005A400)) -#define GPIO_PORTC_AHB_IS_R (*((volatile uint32_t *)0x4005A404)) -#define GPIO_PORTC_AHB_IBE_R (*((volatile uint32_t *)0x4005A408)) -#define GPIO_PORTC_AHB_IEV_R (*((volatile uint32_t *)0x4005A40C)) -#define GPIO_PORTC_AHB_IM_R (*((volatile uint32_t *)0x4005A410)) -#define GPIO_PORTC_AHB_RIS_R (*((volatile uint32_t *)0x4005A414)) -#define GPIO_PORTC_AHB_MIS_R (*((volatile uint32_t *)0x4005A418)) -#define GPIO_PORTC_AHB_ICR_R (*((volatile uint32_t *)0x4005A41C)) -#define GPIO_PORTC_AHB_AFSEL_R (*((volatile uint32_t *)0x4005A420)) -#define GPIO_PORTC_AHB_DR2R_R (*((volatile uint32_t *)0x4005A500)) -#define GPIO_PORTC_AHB_DR4R_R (*((volatile uint32_t *)0x4005A504)) -#define GPIO_PORTC_AHB_DR8R_R (*((volatile uint32_t *)0x4005A508)) -#define GPIO_PORTC_AHB_ODR_R (*((volatile uint32_t *)0x4005A50C)) -#define GPIO_PORTC_AHB_PUR_R (*((volatile uint32_t *)0x4005A510)) -#define GPIO_PORTC_AHB_PDR_R (*((volatile uint32_t *)0x4005A514)) -#define GPIO_PORTC_AHB_SLR_R (*((volatile uint32_t *)0x4005A518)) -#define GPIO_PORTC_AHB_DEN_R (*((volatile uint32_t *)0x4005A51C)) -#define GPIO_PORTC_AHB_LOCK_R (*((volatile uint32_t *)0x4005A520)) -#define GPIO_PORTC_AHB_CR_R (*((volatile uint32_t *)0x4005A524)) -#define GPIO_PORTC_AHB_AMSEL_R (*((volatile uint32_t *)0x4005A528)) -#define GPIO_PORTC_AHB_PCTL_R (*((volatile uint32_t *)0x4005A52C)) -#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005A530)) -#define GPIO_PORTC_AHB_DMACTL_R (*((volatile uint32_t *)0x4005A534)) -#define GPIO_PORTC_AHB_SI_R (*((volatile uint32_t *)0x4005A538)) -#define GPIO_PORTC_AHB_DR12R_R (*((volatile uint32_t *)0x4005A53C)) -#define GPIO_PORTC_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005A540)) -#define GPIO_PORTC_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005A544)) -#define GPIO_PORTC_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005A548)) -#define GPIO_PORTC_AHB_PP_R (*((volatile uint32_t *)0x4005AFC0)) -#define GPIO_PORTC_AHB_PC_R (*((volatile uint32_t *)0x4005AFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTD AHB) -// -//***************************************************************************** -#define GPIO_PORTD_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005B000) -#define GPIO_PORTD_AHB_DATA_R (*((volatile uint32_t *)0x4005B3FC)) -#define GPIO_PORTD_AHB_DIR_R (*((volatile uint32_t *)0x4005B400)) -#define GPIO_PORTD_AHB_IS_R (*((volatile uint32_t *)0x4005B404)) -#define GPIO_PORTD_AHB_IBE_R (*((volatile uint32_t *)0x4005B408)) -#define GPIO_PORTD_AHB_IEV_R (*((volatile uint32_t *)0x4005B40C)) -#define GPIO_PORTD_AHB_IM_R (*((volatile uint32_t *)0x4005B410)) -#define GPIO_PORTD_AHB_RIS_R (*((volatile uint32_t *)0x4005B414)) -#define GPIO_PORTD_AHB_MIS_R (*((volatile uint32_t *)0x4005B418)) -#define GPIO_PORTD_AHB_ICR_R (*((volatile uint32_t *)0x4005B41C)) -#define GPIO_PORTD_AHB_AFSEL_R (*((volatile uint32_t *)0x4005B420)) -#define GPIO_PORTD_AHB_DR2R_R (*((volatile uint32_t *)0x4005B500)) -#define GPIO_PORTD_AHB_DR4R_R (*((volatile uint32_t *)0x4005B504)) -#define GPIO_PORTD_AHB_DR8R_R (*((volatile uint32_t *)0x4005B508)) -#define GPIO_PORTD_AHB_ODR_R (*((volatile uint32_t *)0x4005B50C)) -#define GPIO_PORTD_AHB_PUR_R (*((volatile uint32_t *)0x4005B510)) -#define GPIO_PORTD_AHB_PDR_R (*((volatile uint32_t *)0x4005B514)) -#define GPIO_PORTD_AHB_SLR_R (*((volatile uint32_t *)0x4005B518)) -#define GPIO_PORTD_AHB_DEN_R (*((volatile uint32_t *)0x4005B51C)) -#define GPIO_PORTD_AHB_LOCK_R (*((volatile uint32_t *)0x4005B520)) -#define GPIO_PORTD_AHB_CR_R (*((volatile uint32_t *)0x4005B524)) -#define GPIO_PORTD_AHB_AMSEL_R (*((volatile uint32_t *)0x4005B528)) -#define GPIO_PORTD_AHB_PCTL_R (*((volatile uint32_t *)0x4005B52C)) -#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005B530)) -#define GPIO_PORTD_AHB_DMACTL_R (*((volatile uint32_t *)0x4005B534)) -#define GPIO_PORTD_AHB_SI_R (*((volatile uint32_t *)0x4005B538)) -#define GPIO_PORTD_AHB_DR12R_R (*((volatile uint32_t *)0x4005B53C)) -#define GPIO_PORTD_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005B540)) -#define GPIO_PORTD_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005B544)) -#define GPIO_PORTD_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005B548)) -#define GPIO_PORTD_AHB_PP_R (*((volatile uint32_t *)0x4005BFC0)) -#define GPIO_PORTD_AHB_PC_R (*((volatile uint32_t *)0x4005BFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTE AHB) -// -//***************************************************************************** -#define GPIO_PORTE_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005C000) -#define GPIO_PORTE_AHB_DATA_R (*((volatile uint32_t *)0x4005C3FC)) -#define GPIO_PORTE_AHB_DIR_R (*((volatile uint32_t *)0x4005C400)) -#define GPIO_PORTE_AHB_IS_R (*((volatile uint32_t *)0x4005C404)) -#define GPIO_PORTE_AHB_IBE_R (*((volatile uint32_t *)0x4005C408)) -#define GPIO_PORTE_AHB_IEV_R (*((volatile uint32_t *)0x4005C40C)) -#define GPIO_PORTE_AHB_IM_R (*((volatile uint32_t *)0x4005C410)) -#define GPIO_PORTE_AHB_RIS_R (*((volatile uint32_t *)0x4005C414)) -#define GPIO_PORTE_AHB_MIS_R (*((volatile uint32_t *)0x4005C418)) -#define GPIO_PORTE_AHB_ICR_R (*((volatile uint32_t *)0x4005C41C)) -#define GPIO_PORTE_AHB_AFSEL_R (*((volatile uint32_t *)0x4005C420)) -#define GPIO_PORTE_AHB_DR2R_R (*((volatile uint32_t *)0x4005C500)) -#define GPIO_PORTE_AHB_DR4R_R (*((volatile uint32_t *)0x4005C504)) -#define GPIO_PORTE_AHB_DR8R_R (*((volatile uint32_t *)0x4005C508)) -#define GPIO_PORTE_AHB_ODR_R (*((volatile uint32_t *)0x4005C50C)) -#define GPIO_PORTE_AHB_PUR_R (*((volatile uint32_t *)0x4005C510)) -#define GPIO_PORTE_AHB_PDR_R (*((volatile uint32_t *)0x4005C514)) -#define GPIO_PORTE_AHB_SLR_R (*((volatile uint32_t *)0x4005C518)) -#define GPIO_PORTE_AHB_DEN_R (*((volatile uint32_t *)0x4005C51C)) -#define GPIO_PORTE_AHB_LOCK_R (*((volatile uint32_t *)0x4005C520)) -#define GPIO_PORTE_AHB_CR_R (*((volatile uint32_t *)0x4005C524)) -#define GPIO_PORTE_AHB_AMSEL_R (*((volatile uint32_t *)0x4005C528)) -#define GPIO_PORTE_AHB_PCTL_R (*((volatile uint32_t *)0x4005C52C)) -#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005C530)) -#define GPIO_PORTE_AHB_DMACTL_R (*((volatile uint32_t *)0x4005C534)) -#define GPIO_PORTE_AHB_SI_R (*((volatile uint32_t *)0x4005C538)) -#define GPIO_PORTE_AHB_DR12R_R (*((volatile uint32_t *)0x4005C53C)) -#define GPIO_PORTE_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005C540)) -#define GPIO_PORTE_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005C544)) -#define GPIO_PORTE_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005C548)) -#define GPIO_PORTE_AHB_PP_R (*((volatile uint32_t *)0x4005CFC0)) -#define GPIO_PORTE_AHB_PC_R (*((volatile uint32_t *)0x4005CFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTF AHB) -// -//***************************************************************************** -#define GPIO_PORTF_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005D000) -#define GPIO_PORTF_AHB_DATA_R (*((volatile uint32_t *)0x4005D3FC)) -#define GPIO_PORTF_AHB_DIR_R (*((volatile uint32_t *)0x4005D400)) -#define GPIO_PORTF_AHB_IS_R (*((volatile uint32_t *)0x4005D404)) -#define GPIO_PORTF_AHB_IBE_R (*((volatile uint32_t *)0x4005D408)) -#define GPIO_PORTF_AHB_IEV_R (*((volatile uint32_t *)0x4005D40C)) -#define GPIO_PORTF_AHB_IM_R (*((volatile uint32_t *)0x4005D410)) -#define GPIO_PORTF_AHB_RIS_R (*((volatile uint32_t *)0x4005D414)) -#define GPIO_PORTF_AHB_MIS_R (*((volatile uint32_t *)0x4005D418)) -#define GPIO_PORTF_AHB_ICR_R (*((volatile uint32_t *)0x4005D41C)) -#define GPIO_PORTF_AHB_AFSEL_R (*((volatile uint32_t *)0x4005D420)) -#define GPIO_PORTF_AHB_DR2R_R (*((volatile uint32_t *)0x4005D500)) -#define GPIO_PORTF_AHB_DR4R_R (*((volatile uint32_t *)0x4005D504)) -#define GPIO_PORTF_AHB_DR8R_R (*((volatile uint32_t *)0x4005D508)) -#define GPIO_PORTF_AHB_ODR_R (*((volatile uint32_t *)0x4005D50C)) -#define GPIO_PORTF_AHB_PUR_R (*((volatile uint32_t *)0x4005D510)) -#define GPIO_PORTF_AHB_PDR_R (*((volatile uint32_t *)0x4005D514)) -#define GPIO_PORTF_AHB_SLR_R (*((volatile uint32_t *)0x4005D518)) -#define GPIO_PORTF_AHB_DEN_R (*((volatile uint32_t *)0x4005D51C)) -#define GPIO_PORTF_AHB_LOCK_R (*((volatile uint32_t *)0x4005D520)) -#define GPIO_PORTF_AHB_CR_R (*((volatile uint32_t *)0x4005D524)) -#define GPIO_PORTF_AHB_AMSEL_R (*((volatile uint32_t *)0x4005D528)) -#define GPIO_PORTF_AHB_PCTL_R (*((volatile uint32_t *)0x4005D52C)) -#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005D530)) -#define GPIO_PORTF_AHB_DMACTL_R (*((volatile uint32_t *)0x4005D534)) -#define GPIO_PORTF_AHB_SI_R (*((volatile uint32_t *)0x4005D538)) -#define GPIO_PORTF_AHB_DR12R_R (*((volatile uint32_t *)0x4005D53C)) -#define GPIO_PORTF_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005D540)) -#define GPIO_PORTF_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005D544)) -#define GPIO_PORTF_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005D548)) -#define GPIO_PORTF_AHB_PP_R (*((volatile uint32_t *)0x4005DFC0)) -#define GPIO_PORTF_AHB_PC_R (*((volatile uint32_t *)0x4005DFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTG AHB) -// -//***************************************************************************** -#define GPIO_PORTG_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005E000) -#define GPIO_PORTG_AHB_DATA_R (*((volatile uint32_t *)0x4005E3FC)) -#define GPIO_PORTG_AHB_DIR_R (*((volatile uint32_t *)0x4005E400)) -#define GPIO_PORTG_AHB_IS_R (*((volatile uint32_t *)0x4005E404)) -#define GPIO_PORTG_AHB_IBE_R (*((volatile uint32_t *)0x4005E408)) -#define GPIO_PORTG_AHB_IEV_R (*((volatile uint32_t *)0x4005E40C)) -#define GPIO_PORTG_AHB_IM_R (*((volatile uint32_t *)0x4005E410)) -#define GPIO_PORTG_AHB_RIS_R (*((volatile uint32_t *)0x4005E414)) -#define GPIO_PORTG_AHB_MIS_R (*((volatile uint32_t *)0x4005E418)) -#define GPIO_PORTG_AHB_ICR_R (*((volatile uint32_t *)0x4005E41C)) -#define GPIO_PORTG_AHB_AFSEL_R (*((volatile uint32_t *)0x4005E420)) -#define GPIO_PORTG_AHB_DR2R_R (*((volatile uint32_t *)0x4005E500)) -#define GPIO_PORTG_AHB_DR4R_R (*((volatile uint32_t *)0x4005E504)) -#define GPIO_PORTG_AHB_DR8R_R (*((volatile uint32_t *)0x4005E508)) -#define GPIO_PORTG_AHB_ODR_R (*((volatile uint32_t *)0x4005E50C)) -#define GPIO_PORTG_AHB_PUR_R (*((volatile uint32_t *)0x4005E510)) -#define GPIO_PORTG_AHB_PDR_R (*((volatile uint32_t *)0x4005E514)) -#define GPIO_PORTG_AHB_SLR_R (*((volatile uint32_t *)0x4005E518)) -#define GPIO_PORTG_AHB_DEN_R (*((volatile uint32_t *)0x4005E51C)) -#define GPIO_PORTG_AHB_LOCK_R (*((volatile uint32_t *)0x4005E520)) -#define GPIO_PORTG_AHB_CR_R (*((volatile uint32_t *)0x4005E524)) -#define GPIO_PORTG_AHB_AMSEL_R (*((volatile uint32_t *)0x4005E528)) -#define GPIO_PORTG_AHB_PCTL_R (*((volatile uint32_t *)0x4005E52C)) -#define GPIO_PORTG_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005E530)) -#define GPIO_PORTG_AHB_DMACTL_R (*((volatile uint32_t *)0x4005E534)) -#define GPIO_PORTG_AHB_SI_R (*((volatile uint32_t *)0x4005E538)) -#define GPIO_PORTG_AHB_DR12R_R (*((volatile uint32_t *)0x4005E53C)) -#define GPIO_PORTG_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005E540)) -#define GPIO_PORTG_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005E544)) -#define GPIO_PORTG_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005E548)) -#define GPIO_PORTG_AHB_PP_R (*((volatile uint32_t *)0x4005EFC0)) -#define GPIO_PORTG_AHB_PC_R (*((volatile uint32_t *)0x4005EFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTH AHB) -// -//***************************************************************************** -#define GPIO_PORTH_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005F000) -#define GPIO_PORTH_AHB_DATA_R (*((volatile uint32_t *)0x4005F3FC)) -#define GPIO_PORTH_AHB_DIR_R (*((volatile uint32_t *)0x4005F400)) -#define GPIO_PORTH_AHB_IS_R (*((volatile uint32_t *)0x4005F404)) -#define GPIO_PORTH_AHB_IBE_R (*((volatile uint32_t *)0x4005F408)) -#define GPIO_PORTH_AHB_IEV_R (*((volatile uint32_t *)0x4005F40C)) -#define GPIO_PORTH_AHB_IM_R (*((volatile uint32_t *)0x4005F410)) -#define GPIO_PORTH_AHB_RIS_R (*((volatile uint32_t *)0x4005F414)) -#define GPIO_PORTH_AHB_MIS_R (*((volatile uint32_t *)0x4005F418)) -#define GPIO_PORTH_AHB_ICR_R (*((volatile uint32_t *)0x4005F41C)) -#define GPIO_PORTH_AHB_AFSEL_R (*((volatile uint32_t *)0x4005F420)) -#define GPIO_PORTH_AHB_DR2R_R (*((volatile uint32_t *)0x4005F500)) -#define GPIO_PORTH_AHB_DR4R_R (*((volatile uint32_t *)0x4005F504)) -#define GPIO_PORTH_AHB_DR8R_R (*((volatile uint32_t *)0x4005F508)) -#define GPIO_PORTH_AHB_ODR_R (*((volatile uint32_t *)0x4005F50C)) -#define GPIO_PORTH_AHB_PUR_R (*((volatile uint32_t *)0x4005F510)) -#define GPIO_PORTH_AHB_PDR_R (*((volatile uint32_t *)0x4005F514)) -#define GPIO_PORTH_AHB_SLR_R (*((volatile uint32_t *)0x4005F518)) -#define GPIO_PORTH_AHB_DEN_R (*((volatile uint32_t *)0x4005F51C)) -#define GPIO_PORTH_AHB_LOCK_R (*((volatile uint32_t *)0x4005F520)) -#define GPIO_PORTH_AHB_CR_R (*((volatile uint32_t *)0x4005F524)) -#define GPIO_PORTH_AHB_AMSEL_R (*((volatile uint32_t *)0x4005F528)) -#define GPIO_PORTH_AHB_PCTL_R (*((volatile uint32_t *)0x4005F52C)) -#define GPIO_PORTH_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005F530)) -#define GPIO_PORTH_AHB_DMACTL_R (*((volatile uint32_t *)0x4005F534)) -#define GPIO_PORTH_AHB_SI_R (*((volatile uint32_t *)0x4005F538)) -#define GPIO_PORTH_AHB_DR12R_R (*((volatile uint32_t *)0x4005F53C)) -#define GPIO_PORTH_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005F540)) -#define GPIO_PORTH_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005F544)) -#define GPIO_PORTH_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005F548)) -#define GPIO_PORTH_AHB_PP_R (*((volatile uint32_t *)0x4005FFC0)) -#define GPIO_PORTH_AHB_PC_R (*((volatile uint32_t *)0x4005FFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTJ AHB) -// -//***************************************************************************** -#define GPIO_PORTJ_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x40060000) -#define GPIO_PORTJ_AHB_DATA_R (*((volatile uint32_t *)0x400603FC)) -#define GPIO_PORTJ_AHB_DIR_R (*((volatile uint32_t *)0x40060400)) -#define GPIO_PORTJ_AHB_IS_R (*((volatile uint32_t *)0x40060404)) -#define GPIO_PORTJ_AHB_IBE_R (*((volatile uint32_t *)0x40060408)) -#define GPIO_PORTJ_AHB_IEV_R (*((volatile uint32_t *)0x4006040C)) -#define GPIO_PORTJ_AHB_IM_R (*((volatile uint32_t *)0x40060410)) -#define GPIO_PORTJ_AHB_RIS_R (*((volatile uint32_t *)0x40060414)) -#define GPIO_PORTJ_AHB_MIS_R (*((volatile uint32_t *)0x40060418)) -#define GPIO_PORTJ_AHB_ICR_R (*((volatile uint32_t *)0x4006041C)) -#define GPIO_PORTJ_AHB_AFSEL_R (*((volatile uint32_t *)0x40060420)) -#define GPIO_PORTJ_AHB_DR2R_R (*((volatile uint32_t *)0x40060500)) -#define GPIO_PORTJ_AHB_DR4R_R (*((volatile uint32_t *)0x40060504)) -#define GPIO_PORTJ_AHB_DR8R_R (*((volatile uint32_t *)0x40060508)) -#define GPIO_PORTJ_AHB_ODR_R (*((volatile uint32_t *)0x4006050C)) -#define GPIO_PORTJ_AHB_PUR_R (*((volatile uint32_t *)0x40060510)) -#define GPIO_PORTJ_AHB_PDR_R (*((volatile uint32_t *)0x40060514)) -#define GPIO_PORTJ_AHB_SLR_R (*((volatile uint32_t *)0x40060518)) -#define GPIO_PORTJ_AHB_DEN_R (*((volatile uint32_t *)0x4006051C)) -#define GPIO_PORTJ_AHB_LOCK_R (*((volatile uint32_t *)0x40060520)) -#define GPIO_PORTJ_AHB_CR_R (*((volatile uint32_t *)0x40060524)) -#define GPIO_PORTJ_AHB_AMSEL_R (*((volatile uint32_t *)0x40060528)) -#define GPIO_PORTJ_AHB_PCTL_R (*((volatile uint32_t *)0x4006052C)) -#define GPIO_PORTJ_AHB_ADCCTL_R (*((volatile uint32_t *)0x40060530)) -#define GPIO_PORTJ_AHB_DMACTL_R (*((volatile uint32_t *)0x40060534)) -#define GPIO_PORTJ_AHB_SI_R (*((volatile uint32_t *)0x40060538)) -#define GPIO_PORTJ_AHB_DR12R_R (*((volatile uint32_t *)0x4006053C)) -#define GPIO_PORTJ_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x40060540)) -#define GPIO_PORTJ_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x40060544)) -#define GPIO_PORTJ_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x40060548)) -#define GPIO_PORTJ_AHB_PP_R (*((volatile uint32_t *)0x40060FC0)) -#define GPIO_PORTJ_AHB_PC_R (*((volatile uint32_t *)0x40060FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTK) -// -//***************************************************************************** -#define GPIO_PORTK_DATA_BITS_R ((volatile uint32_t *)0x40061000) -#define GPIO_PORTK_DATA_R (*((volatile uint32_t *)0x400613FC)) -#define GPIO_PORTK_DIR_R (*((volatile uint32_t *)0x40061400)) -#define GPIO_PORTK_IS_R (*((volatile uint32_t *)0x40061404)) -#define GPIO_PORTK_IBE_R (*((volatile uint32_t *)0x40061408)) -#define GPIO_PORTK_IEV_R (*((volatile uint32_t *)0x4006140C)) -#define GPIO_PORTK_IM_R (*((volatile uint32_t *)0x40061410)) -#define GPIO_PORTK_RIS_R (*((volatile uint32_t *)0x40061414)) -#define GPIO_PORTK_MIS_R (*((volatile uint32_t *)0x40061418)) -#define GPIO_PORTK_ICR_R (*((volatile uint32_t *)0x4006141C)) -#define GPIO_PORTK_AFSEL_R (*((volatile uint32_t *)0x40061420)) -#define GPIO_PORTK_DR2R_R (*((volatile uint32_t *)0x40061500)) -#define GPIO_PORTK_DR4R_R (*((volatile uint32_t *)0x40061504)) -#define GPIO_PORTK_DR8R_R (*((volatile uint32_t *)0x40061508)) -#define GPIO_PORTK_ODR_R (*((volatile uint32_t *)0x4006150C)) -#define GPIO_PORTK_PUR_R (*((volatile uint32_t *)0x40061510)) -#define GPIO_PORTK_PDR_R (*((volatile uint32_t *)0x40061514)) -#define GPIO_PORTK_SLR_R (*((volatile uint32_t *)0x40061518)) -#define GPIO_PORTK_DEN_R (*((volatile uint32_t *)0x4006151C)) -#define GPIO_PORTK_LOCK_R (*((volatile uint32_t *)0x40061520)) -#define GPIO_PORTK_CR_R (*((volatile uint32_t *)0x40061524)) -#define GPIO_PORTK_AMSEL_R (*((volatile uint32_t *)0x40061528)) -#define GPIO_PORTK_PCTL_R (*((volatile uint32_t *)0x4006152C)) -#define GPIO_PORTK_ADCCTL_R (*((volatile uint32_t *)0x40061530)) -#define GPIO_PORTK_DMACTL_R (*((volatile uint32_t *)0x40061534)) -#define GPIO_PORTK_SI_R (*((volatile uint32_t *)0x40061538)) -#define GPIO_PORTK_DR12R_R (*((volatile uint32_t *)0x4006153C)) -#define GPIO_PORTK_WAKEPEN_R (*((volatile uint32_t *)0x40061540)) -#define GPIO_PORTK_WAKELVL_R (*((volatile uint32_t *)0x40061544)) -#define GPIO_PORTK_WAKESTAT_R (*((volatile uint32_t *)0x40061548)) -#define GPIO_PORTK_PP_R (*((volatile uint32_t *)0x40061FC0)) -#define GPIO_PORTK_PC_R (*((volatile uint32_t *)0x40061FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTL) -// -//***************************************************************************** -#define GPIO_PORTL_DATA_BITS_R ((volatile uint32_t *)0x40062000) -#define GPIO_PORTL_DATA_R (*((volatile uint32_t *)0x400623FC)) -#define GPIO_PORTL_DIR_R (*((volatile uint32_t *)0x40062400)) -#define GPIO_PORTL_IS_R (*((volatile uint32_t *)0x40062404)) -#define GPIO_PORTL_IBE_R (*((volatile uint32_t *)0x40062408)) -#define GPIO_PORTL_IEV_R (*((volatile uint32_t *)0x4006240C)) -#define GPIO_PORTL_IM_R (*((volatile uint32_t *)0x40062410)) -#define GPIO_PORTL_RIS_R (*((volatile uint32_t *)0x40062414)) -#define GPIO_PORTL_MIS_R (*((volatile uint32_t *)0x40062418)) -#define GPIO_PORTL_ICR_R (*((volatile uint32_t *)0x4006241C)) -#define GPIO_PORTL_AFSEL_R (*((volatile uint32_t *)0x40062420)) -#define GPIO_PORTL_DR2R_R (*((volatile uint32_t *)0x40062500)) -#define GPIO_PORTL_DR4R_R (*((volatile uint32_t *)0x40062504)) -#define GPIO_PORTL_DR8R_R (*((volatile uint32_t *)0x40062508)) -#define GPIO_PORTL_ODR_R (*((volatile uint32_t *)0x4006250C)) -#define GPIO_PORTL_PUR_R (*((volatile uint32_t *)0x40062510)) -#define GPIO_PORTL_PDR_R (*((volatile uint32_t *)0x40062514)) -#define GPIO_PORTL_SLR_R (*((volatile uint32_t *)0x40062518)) -#define GPIO_PORTL_DEN_R (*((volatile uint32_t *)0x4006251C)) -#define GPIO_PORTL_LOCK_R (*((volatile uint32_t *)0x40062520)) -#define GPIO_PORTL_CR_R (*((volatile uint32_t *)0x40062524)) -#define GPIO_PORTL_AMSEL_R (*((volatile uint32_t *)0x40062528)) -#define GPIO_PORTL_PCTL_R (*((volatile uint32_t *)0x4006252C)) -#define GPIO_PORTL_ADCCTL_R (*((volatile uint32_t *)0x40062530)) -#define GPIO_PORTL_DMACTL_R (*((volatile uint32_t *)0x40062534)) -#define GPIO_PORTL_SI_R (*((volatile uint32_t *)0x40062538)) -#define GPIO_PORTL_DR12R_R (*((volatile uint32_t *)0x4006253C)) -#define GPIO_PORTL_WAKEPEN_R (*((volatile uint32_t *)0x40062540)) -#define GPIO_PORTL_WAKELVL_R (*((volatile uint32_t *)0x40062544)) -#define GPIO_PORTL_WAKESTAT_R (*((volatile uint32_t *)0x40062548)) -#define GPIO_PORTL_PP_R (*((volatile uint32_t *)0x40062FC0)) -#define GPIO_PORTL_PC_R (*((volatile uint32_t *)0x40062FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTM) -// -//***************************************************************************** -#define GPIO_PORTM_DATA_BITS_R ((volatile uint32_t *)0x40063000) -#define GPIO_PORTM_DATA_R (*((volatile uint32_t *)0x400633FC)) -#define GPIO_PORTM_DIR_R (*((volatile uint32_t *)0x40063400)) -#define GPIO_PORTM_IS_R (*((volatile uint32_t *)0x40063404)) -#define GPIO_PORTM_IBE_R (*((volatile uint32_t *)0x40063408)) -#define GPIO_PORTM_IEV_R (*((volatile uint32_t *)0x4006340C)) -#define GPIO_PORTM_IM_R (*((volatile uint32_t *)0x40063410)) -#define GPIO_PORTM_RIS_R (*((volatile uint32_t *)0x40063414)) -#define GPIO_PORTM_MIS_R (*((volatile uint32_t *)0x40063418)) -#define GPIO_PORTM_ICR_R (*((volatile uint32_t *)0x4006341C)) -#define GPIO_PORTM_AFSEL_R (*((volatile uint32_t *)0x40063420)) -#define GPIO_PORTM_DR2R_R (*((volatile uint32_t *)0x40063500)) -#define GPIO_PORTM_DR4R_R (*((volatile uint32_t *)0x40063504)) -#define GPIO_PORTM_DR8R_R (*((volatile uint32_t *)0x40063508)) -#define GPIO_PORTM_ODR_R (*((volatile uint32_t *)0x4006350C)) -#define GPIO_PORTM_PUR_R (*((volatile uint32_t *)0x40063510)) -#define GPIO_PORTM_PDR_R (*((volatile uint32_t *)0x40063514)) -#define GPIO_PORTM_SLR_R (*((volatile uint32_t *)0x40063518)) -#define GPIO_PORTM_DEN_R (*((volatile uint32_t *)0x4006351C)) -#define GPIO_PORTM_LOCK_R (*((volatile uint32_t *)0x40063520)) -#define GPIO_PORTM_CR_R (*((volatile uint32_t *)0x40063524)) -#define GPIO_PORTM_AMSEL_R (*((volatile uint32_t *)0x40063528)) -#define GPIO_PORTM_PCTL_R (*((volatile uint32_t *)0x4006352C)) -#define GPIO_PORTM_ADCCTL_R (*((volatile uint32_t *)0x40063530)) -#define GPIO_PORTM_DMACTL_R (*((volatile uint32_t *)0x40063534)) -#define GPIO_PORTM_SI_R (*((volatile uint32_t *)0x40063538)) -#define GPIO_PORTM_DR12R_R (*((volatile uint32_t *)0x4006353C)) -#define GPIO_PORTM_WAKEPEN_R (*((volatile uint32_t *)0x40063540)) -#define GPIO_PORTM_WAKELVL_R (*((volatile uint32_t *)0x40063544)) -#define GPIO_PORTM_WAKESTAT_R (*((volatile uint32_t *)0x40063548)) -#define GPIO_PORTM_PP_R (*((volatile uint32_t *)0x40063FC0)) -#define GPIO_PORTM_PC_R (*((volatile uint32_t *)0x40063FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTN) -// -//***************************************************************************** -#define GPIO_PORTN_DATA_BITS_R ((volatile uint32_t *)0x40064000) -#define GPIO_PORTN_DATA_R (*((volatile uint32_t *)0x400643FC)) -#define GPIO_PORTN_DIR_R (*((volatile uint32_t *)0x40064400)) -#define GPIO_PORTN_IS_R (*((volatile uint32_t *)0x40064404)) -#define GPIO_PORTN_IBE_R (*((volatile uint32_t *)0x40064408)) -#define GPIO_PORTN_IEV_R (*((volatile uint32_t *)0x4006440C)) -#define GPIO_PORTN_IM_R (*((volatile uint32_t *)0x40064410)) -#define GPIO_PORTN_RIS_R (*((volatile uint32_t *)0x40064414)) -#define GPIO_PORTN_MIS_R (*((volatile uint32_t *)0x40064418)) -#define GPIO_PORTN_ICR_R (*((volatile uint32_t *)0x4006441C)) -#define GPIO_PORTN_AFSEL_R (*((volatile uint32_t *)0x40064420)) -#define GPIO_PORTN_DR2R_R (*((volatile uint32_t *)0x40064500)) -#define GPIO_PORTN_DR4R_R (*((volatile uint32_t *)0x40064504)) -#define GPIO_PORTN_DR8R_R (*((volatile uint32_t *)0x40064508)) -#define GPIO_PORTN_ODR_R (*((volatile uint32_t *)0x4006450C)) -#define GPIO_PORTN_PUR_R (*((volatile uint32_t *)0x40064510)) -#define GPIO_PORTN_PDR_R (*((volatile uint32_t *)0x40064514)) -#define GPIO_PORTN_SLR_R (*((volatile uint32_t *)0x40064518)) -#define GPIO_PORTN_DEN_R (*((volatile uint32_t *)0x4006451C)) -#define GPIO_PORTN_LOCK_R (*((volatile uint32_t *)0x40064520)) -#define GPIO_PORTN_CR_R (*((volatile uint32_t *)0x40064524)) -#define GPIO_PORTN_AMSEL_R (*((volatile uint32_t *)0x40064528)) -#define GPIO_PORTN_PCTL_R (*((volatile uint32_t *)0x4006452C)) -#define GPIO_PORTN_ADCCTL_R (*((volatile uint32_t *)0x40064530)) -#define GPIO_PORTN_DMACTL_R (*((volatile uint32_t *)0x40064534)) -#define GPIO_PORTN_SI_R (*((volatile uint32_t *)0x40064538)) -#define GPIO_PORTN_DR12R_R (*((volatile uint32_t *)0x4006453C)) -#define GPIO_PORTN_WAKEPEN_R (*((volatile uint32_t *)0x40064540)) -#define GPIO_PORTN_WAKELVL_R (*((volatile uint32_t *)0x40064544)) -#define GPIO_PORTN_WAKESTAT_R (*((volatile uint32_t *)0x40064548)) -#define GPIO_PORTN_PP_R (*((volatile uint32_t *)0x40064FC0)) -#define GPIO_PORTN_PC_R (*((volatile uint32_t *)0x40064FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTP) -// -//***************************************************************************** -#define GPIO_PORTP_DATA_BITS_R ((volatile uint32_t *)0x40065000) -#define GPIO_PORTP_DATA_R (*((volatile uint32_t *)0x400653FC)) -#define GPIO_PORTP_DIR_R (*((volatile uint32_t *)0x40065400)) -#define GPIO_PORTP_IS_R (*((volatile uint32_t *)0x40065404)) -#define GPIO_PORTP_IBE_R (*((volatile uint32_t *)0x40065408)) -#define GPIO_PORTP_IEV_R (*((volatile uint32_t *)0x4006540C)) -#define GPIO_PORTP_IM_R (*((volatile uint32_t *)0x40065410)) -#define GPIO_PORTP_RIS_R (*((volatile uint32_t *)0x40065414)) -#define GPIO_PORTP_MIS_R (*((volatile uint32_t *)0x40065418)) -#define GPIO_PORTP_ICR_R (*((volatile uint32_t *)0x4006541C)) -#define GPIO_PORTP_AFSEL_R (*((volatile uint32_t *)0x40065420)) -#define GPIO_PORTP_DR2R_R (*((volatile uint32_t *)0x40065500)) -#define GPIO_PORTP_DR4R_R (*((volatile uint32_t *)0x40065504)) -#define GPIO_PORTP_DR8R_R (*((volatile uint32_t *)0x40065508)) -#define GPIO_PORTP_ODR_R (*((volatile uint32_t *)0x4006550C)) -#define GPIO_PORTP_PUR_R (*((volatile uint32_t *)0x40065510)) -#define GPIO_PORTP_PDR_R (*((volatile uint32_t *)0x40065514)) -#define GPIO_PORTP_SLR_R (*((volatile uint32_t *)0x40065518)) -#define GPIO_PORTP_DEN_R (*((volatile uint32_t *)0x4006551C)) -#define GPIO_PORTP_LOCK_R (*((volatile uint32_t *)0x40065520)) -#define GPIO_PORTP_CR_R (*((volatile uint32_t *)0x40065524)) -#define GPIO_PORTP_AMSEL_R (*((volatile uint32_t *)0x40065528)) -#define GPIO_PORTP_PCTL_R (*((volatile uint32_t *)0x4006552C)) -#define GPIO_PORTP_ADCCTL_R (*((volatile uint32_t *)0x40065530)) -#define GPIO_PORTP_DMACTL_R (*((volatile uint32_t *)0x40065534)) -#define GPIO_PORTP_SI_R (*((volatile uint32_t *)0x40065538)) -#define GPIO_PORTP_DR12R_R (*((volatile uint32_t *)0x4006553C)) -#define GPIO_PORTP_WAKEPEN_R (*((volatile uint32_t *)0x40065540)) -#define GPIO_PORTP_WAKELVL_R (*((volatile uint32_t *)0x40065544)) -#define GPIO_PORTP_WAKESTAT_R (*((volatile uint32_t *)0x40065548)) -#define GPIO_PORTP_PP_R (*((volatile uint32_t *)0x40065FC0)) -#define GPIO_PORTP_PC_R (*((volatile uint32_t *)0x40065FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTQ) -// -//***************************************************************************** -#define GPIO_PORTQ_DATA_BITS_R ((volatile uint32_t *)0x40066000) -#define GPIO_PORTQ_DATA_R (*((volatile uint32_t *)0x400663FC)) -#define GPIO_PORTQ_DIR_R (*((volatile uint32_t *)0x40066400)) -#define GPIO_PORTQ_IS_R (*((volatile uint32_t *)0x40066404)) -#define GPIO_PORTQ_IBE_R (*((volatile uint32_t *)0x40066408)) -#define GPIO_PORTQ_IEV_R (*((volatile uint32_t *)0x4006640C)) -#define GPIO_PORTQ_IM_R (*((volatile uint32_t *)0x40066410)) -#define GPIO_PORTQ_RIS_R (*((volatile uint32_t *)0x40066414)) -#define GPIO_PORTQ_MIS_R (*((volatile uint32_t *)0x40066418)) -#define GPIO_PORTQ_ICR_R (*((volatile uint32_t *)0x4006641C)) -#define GPIO_PORTQ_AFSEL_R (*((volatile uint32_t *)0x40066420)) -#define GPIO_PORTQ_DR2R_R (*((volatile uint32_t *)0x40066500)) -#define GPIO_PORTQ_DR4R_R (*((volatile uint32_t *)0x40066504)) -#define GPIO_PORTQ_DR8R_R (*((volatile uint32_t *)0x40066508)) -#define GPIO_PORTQ_ODR_R (*((volatile uint32_t *)0x4006650C)) -#define GPIO_PORTQ_PUR_R (*((volatile uint32_t *)0x40066510)) -#define GPIO_PORTQ_PDR_R (*((volatile uint32_t *)0x40066514)) -#define GPIO_PORTQ_SLR_R (*((volatile uint32_t *)0x40066518)) -#define GPIO_PORTQ_DEN_R (*((volatile uint32_t *)0x4006651C)) -#define GPIO_PORTQ_LOCK_R (*((volatile uint32_t *)0x40066520)) -#define GPIO_PORTQ_CR_R (*((volatile uint32_t *)0x40066524)) -#define GPIO_PORTQ_AMSEL_R (*((volatile uint32_t *)0x40066528)) -#define GPIO_PORTQ_PCTL_R (*((volatile uint32_t *)0x4006652C)) -#define GPIO_PORTQ_ADCCTL_R (*((volatile uint32_t *)0x40066530)) -#define GPIO_PORTQ_DMACTL_R (*((volatile uint32_t *)0x40066534)) -#define GPIO_PORTQ_SI_R (*((volatile uint32_t *)0x40066538)) -#define GPIO_PORTQ_DR12R_R (*((volatile uint32_t *)0x4006653C)) -#define GPIO_PORTQ_WAKEPEN_R (*((volatile uint32_t *)0x40066540)) -#define GPIO_PORTQ_WAKELVL_R (*((volatile uint32_t *)0x40066544)) -#define GPIO_PORTQ_WAKESTAT_R (*((volatile uint32_t *)0x40066548)) -#define GPIO_PORTQ_PP_R (*((volatile uint32_t *)0x40066FC0)) -#define GPIO_PORTQ_PC_R (*((volatile uint32_t *)0x40066FC4)) - -//***************************************************************************** -// -// EEPROM registers (EEPROM) -// -//***************************************************************************** -#define EEPROM_EESIZE_R (*((volatile uint32_t *)0x400AF000)) -#define EEPROM_EEBLOCK_R (*((volatile uint32_t *)0x400AF004)) -#define EEPROM_EEOFFSET_R (*((volatile uint32_t *)0x400AF008)) -#define EEPROM_EERDWR_R (*((volatile uint32_t *)0x400AF010)) -#define EEPROM_EERDWRINC_R (*((volatile uint32_t *)0x400AF014)) -#define EEPROM_EEDONE_R (*((volatile uint32_t *)0x400AF018)) -#define EEPROM_EESUPP_R (*((volatile uint32_t *)0x400AF01C)) -#define EEPROM_EEUNLOCK_R (*((volatile uint32_t *)0x400AF020)) -#define EEPROM_EEPROT_R (*((volatile uint32_t *)0x400AF030)) -#define EEPROM_EEPASS0_R (*((volatile uint32_t *)0x400AF034)) -#define EEPROM_EEPASS1_R (*((volatile uint32_t *)0x400AF038)) -#define EEPROM_EEPASS2_R (*((volatile uint32_t *)0x400AF03C)) -#define EEPROM_EEINT_R (*((volatile uint32_t *)0x400AF040)) -#define EEPROM_EEHIDE0_R (*((volatile uint32_t *)0x400AF050)) -#define EEPROM_EEHIDE1_R (*((volatile uint32_t *)0x400AF054)) -#define EEPROM_EEHIDE2_R (*((volatile uint32_t *)0x400AF058)) -#define EEPROM_EEDBGME_R (*((volatile uint32_t *)0x400AF080)) -#define EEPROM_PP_R (*((volatile uint32_t *)0x400AFFC0)) - -//***************************************************************************** -// -// I2C registers (I2C8) -// -//***************************************************************************** -#define I2C8_MSA_R (*((volatile uint32_t *)0x400B8000)) -#define I2C8_MCS_R (*((volatile uint32_t *)0x400B8004)) -#define I2C8_MDR_R (*((volatile uint32_t *)0x400B8008)) -#define I2C8_MTPR_R (*((volatile uint32_t *)0x400B800C)) -#define I2C8_MIMR_R (*((volatile uint32_t *)0x400B8010)) -#define I2C8_MRIS_R (*((volatile uint32_t *)0x400B8014)) -#define I2C8_MMIS_R (*((volatile uint32_t *)0x400B8018)) -#define I2C8_MICR_R (*((volatile uint32_t *)0x400B801C)) -#define I2C8_MCR_R (*((volatile uint32_t *)0x400B8020)) -#define I2C8_MCLKOCNT_R (*((volatile uint32_t *)0x400B8024)) -#define I2C8_MBMON_R (*((volatile uint32_t *)0x400B802C)) -#define I2C8_MBLEN_R (*((volatile uint32_t *)0x400B8030)) -#define I2C8_MBCNT_R (*((volatile uint32_t *)0x400B8034)) -#define I2C8_SOAR_R (*((volatile uint32_t *)0x400B8800)) -#define I2C8_SCSR_R (*((volatile uint32_t *)0x400B8804)) -#define I2C8_SDR_R (*((volatile uint32_t *)0x400B8808)) -#define I2C8_SIMR_R (*((volatile uint32_t *)0x400B880C)) -#define I2C8_SRIS_R (*((volatile uint32_t *)0x400B8810)) -#define I2C8_SMIS_R (*((volatile uint32_t *)0x400B8814)) -#define I2C8_SICR_R (*((volatile uint32_t *)0x400B8818)) -#define I2C8_SOAR2_R (*((volatile uint32_t *)0x400B881C)) -#define I2C8_SACKCTL_R (*((volatile uint32_t *)0x400B8820)) -#define I2C8_FIFODATA_R (*((volatile uint32_t *)0x400B8F00)) -#define I2C8_FIFOCTL_R (*((volatile uint32_t *)0x400B8F04)) -#define I2C8_FIFOSTATUS_R (*((volatile uint32_t *)0x400B8F08)) -#define I2C8_PP_R (*((volatile uint32_t *)0x400B8FC0)) -#define I2C8_PC_R (*((volatile uint32_t *)0x400B8FC4)) - -//***************************************************************************** -// -// I2C registers (I2C9) -// -//***************************************************************************** -#define I2C9_MSA_R (*((volatile uint32_t *)0x400B9000)) -#define I2C9_MCS_R (*((volatile uint32_t *)0x400B9004)) -#define I2C9_MDR_R (*((volatile uint32_t *)0x400B9008)) -#define I2C9_MTPR_R (*((volatile uint32_t *)0x400B900C)) -#define I2C9_MIMR_R (*((volatile uint32_t *)0x400B9010)) -#define I2C9_MRIS_R (*((volatile uint32_t *)0x400B9014)) -#define I2C9_MMIS_R (*((volatile uint32_t *)0x400B9018)) -#define I2C9_MICR_R (*((volatile uint32_t *)0x400B901C)) -#define I2C9_MCR_R (*((volatile uint32_t *)0x400B9020)) -#define I2C9_MCLKOCNT_R (*((volatile uint32_t *)0x400B9024)) -#define I2C9_MBMON_R (*((volatile uint32_t *)0x400B902C)) -#define I2C9_MBLEN_R (*((volatile uint32_t *)0x400B9030)) -#define I2C9_MBCNT_R (*((volatile uint32_t *)0x400B9034)) -#define I2C9_SOAR_R (*((volatile uint32_t *)0x400B9800)) -#define I2C9_SCSR_R (*((volatile uint32_t *)0x400B9804)) -#define I2C9_SDR_R (*((volatile uint32_t *)0x400B9808)) -#define I2C9_SIMR_R (*((volatile uint32_t *)0x400B980C)) -#define I2C9_SRIS_R (*((volatile uint32_t *)0x400B9810)) -#define I2C9_SMIS_R (*((volatile uint32_t *)0x400B9814)) -#define I2C9_SICR_R (*((volatile uint32_t *)0x400B9818)) -#define I2C9_SOAR2_R (*((volatile uint32_t *)0x400B981C)) -#define I2C9_SACKCTL_R (*((volatile uint32_t *)0x400B9820)) -#define I2C9_FIFODATA_R (*((volatile uint32_t *)0x400B9F00)) -#define I2C9_FIFOCTL_R (*((volatile uint32_t *)0x400B9F04)) -#define I2C9_FIFOSTATUS_R (*((volatile uint32_t *)0x400B9F08)) -#define I2C9_PP_R (*((volatile uint32_t *)0x400B9FC0)) -#define I2C9_PC_R (*((volatile uint32_t *)0x400B9FC4)) - -//***************************************************************************** -// -// I2C registers (I2C4) -// -//***************************************************************************** -#define I2C4_MSA_R (*((volatile uint32_t *)0x400C0000)) -#define I2C4_MCS_R (*((volatile uint32_t *)0x400C0004)) -#define I2C4_MDR_R (*((volatile uint32_t *)0x400C0008)) -#define I2C4_MTPR_R (*((volatile uint32_t *)0x400C000C)) -#define I2C4_MIMR_R (*((volatile uint32_t *)0x400C0010)) -#define I2C4_MRIS_R (*((volatile uint32_t *)0x400C0014)) -#define I2C4_MMIS_R (*((volatile uint32_t *)0x400C0018)) -#define I2C4_MICR_R (*((volatile uint32_t *)0x400C001C)) -#define I2C4_MCR_R (*((volatile uint32_t *)0x400C0020)) -#define I2C4_MCLKOCNT_R (*((volatile uint32_t *)0x400C0024)) -#define I2C4_MBMON_R (*((volatile uint32_t *)0x400C002C)) -#define I2C4_MBLEN_R (*((volatile uint32_t *)0x400C0030)) -#define I2C4_MBCNT_R (*((volatile uint32_t *)0x400C0034)) -#define I2C4_SOAR_R (*((volatile uint32_t *)0x400C0800)) -#define I2C4_SCSR_R (*((volatile uint32_t *)0x400C0804)) -#define I2C4_SDR_R (*((volatile uint32_t *)0x400C0808)) -#define I2C4_SIMR_R (*((volatile uint32_t *)0x400C080C)) -#define I2C4_SRIS_R (*((volatile uint32_t *)0x400C0810)) -#define I2C4_SMIS_R (*((volatile uint32_t *)0x400C0814)) -#define I2C4_SICR_R (*((volatile uint32_t *)0x400C0818)) -#define I2C4_SOAR2_R (*((volatile uint32_t *)0x400C081C)) -#define I2C4_SACKCTL_R (*((volatile uint32_t *)0x400C0820)) -#define I2C4_FIFODATA_R (*((volatile uint32_t *)0x400C0F00)) -#define I2C4_FIFOCTL_R (*((volatile uint32_t *)0x400C0F04)) -#define I2C4_FIFOSTATUS_R (*((volatile uint32_t *)0x400C0F08)) -#define I2C4_PP_R (*((volatile uint32_t *)0x400C0FC0)) -#define I2C4_PC_R (*((volatile uint32_t *)0x400C0FC4)) - -//***************************************************************************** -// -// I2C registers (I2C5) -// -//***************************************************************************** -#define I2C5_MSA_R (*((volatile uint32_t *)0x400C1000)) -#define I2C5_MCS_R (*((volatile uint32_t *)0x400C1004)) -#define I2C5_MDR_R (*((volatile uint32_t *)0x400C1008)) -#define I2C5_MTPR_R (*((volatile uint32_t *)0x400C100C)) -#define I2C5_MIMR_R (*((volatile uint32_t *)0x400C1010)) -#define I2C5_MRIS_R (*((volatile uint32_t *)0x400C1014)) -#define I2C5_MMIS_R (*((volatile uint32_t *)0x400C1018)) -#define I2C5_MICR_R (*((volatile uint32_t *)0x400C101C)) -#define I2C5_MCR_R (*((volatile uint32_t *)0x400C1020)) -#define I2C5_MCLKOCNT_R (*((volatile uint32_t *)0x400C1024)) -#define I2C5_MBMON_R (*((volatile uint32_t *)0x400C102C)) -#define I2C5_MBLEN_R (*((volatile uint32_t *)0x400C1030)) -#define I2C5_MBCNT_R (*((volatile uint32_t *)0x400C1034)) -#define I2C5_SOAR_R (*((volatile uint32_t *)0x400C1800)) -#define I2C5_SCSR_R (*((volatile uint32_t *)0x400C1804)) -#define I2C5_SDR_R (*((volatile uint32_t *)0x400C1808)) -#define I2C5_SIMR_R (*((volatile uint32_t *)0x400C180C)) -#define I2C5_SRIS_R (*((volatile uint32_t *)0x400C1810)) -#define I2C5_SMIS_R (*((volatile uint32_t *)0x400C1814)) -#define I2C5_SICR_R (*((volatile uint32_t *)0x400C1818)) -#define I2C5_SOAR2_R (*((volatile uint32_t *)0x400C181C)) -#define I2C5_SACKCTL_R (*((volatile uint32_t *)0x400C1820)) -#define I2C5_FIFODATA_R (*((volatile uint32_t *)0x400C1F00)) -#define I2C5_FIFOCTL_R (*((volatile uint32_t *)0x400C1F04)) -#define I2C5_FIFOSTATUS_R (*((volatile uint32_t *)0x400C1F08)) -#define I2C5_PP_R (*((volatile uint32_t *)0x400C1FC0)) -#define I2C5_PC_R (*((volatile uint32_t *)0x400C1FC4)) - -//***************************************************************************** -// -// I2C registers (I2C6) -// -//***************************************************************************** -#define I2C6_MSA_R (*((volatile uint32_t *)0x400C2000)) -#define I2C6_MCS_R (*((volatile uint32_t *)0x400C2004)) -#define I2C6_MDR_R (*((volatile uint32_t *)0x400C2008)) -#define I2C6_MTPR_R (*((volatile uint32_t *)0x400C200C)) -#define I2C6_MIMR_R (*((volatile uint32_t *)0x400C2010)) -#define I2C6_MRIS_R (*((volatile uint32_t *)0x400C2014)) -#define I2C6_MMIS_R (*((volatile uint32_t *)0x400C2018)) -#define I2C6_MICR_R (*((volatile uint32_t *)0x400C201C)) -#define I2C6_MCR_R (*((volatile uint32_t *)0x400C2020)) -#define I2C6_MCLKOCNT_R (*((volatile uint32_t *)0x400C2024)) -#define I2C6_MBMON_R (*((volatile uint32_t *)0x400C202C)) -#define I2C6_MBLEN_R (*((volatile uint32_t *)0x400C2030)) -#define I2C6_MBCNT_R (*((volatile uint32_t *)0x400C2034)) -#define I2C6_SOAR_R (*((volatile uint32_t *)0x400C2800)) -#define I2C6_SCSR_R (*((volatile uint32_t *)0x400C2804)) -#define I2C6_SDR_R (*((volatile uint32_t *)0x400C2808)) -#define I2C6_SIMR_R (*((volatile uint32_t *)0x400C280C)) -#define I2C6_SRIS_R (*((volatile uint32_t *)0x400C2810)) -#define I2C6_SMIS_R (*((volatile uint32_t *)0x400C2814)) -#define I2C6_SICR_R (*((volatile uint32_t *)0x400C2818)) -#define I2C6_SOAR2_R (*((volatile uint32_t *)0x400C281C)) -#define I2C6_SACKCTL_R (*((volatile uint32_t *)0x400C2820)) -#define I2C6_FIFODATA_R (*((volatile uint32_t *)0x400C2F00)) -#define I2C6_FIFOCTL_R (*((volatile uint32_t *)0x400C2F04)) -#define I2C6_FIFOSTATUS_R (*((volatile uint32_t *)0x400C2F08)) -#define I2C6_PP_R (*((volatile uint32_t *)0x400C2FC0)) -#define I2C6_PC_R (*((volatile uint32_t *)0x400C2FC4)) - -//***************************************************************************** -// -// I2C registers (I2C7) -// -//***************************************************************************** -#define I2C7_MSA_R (*((volatile uint32_t *)0x400C3000)) -#define I2C7_MCS_R (*((volatile uint32_t *)0x400C3004)) -#define I2C7_MDR_R (*((volatile uint32_t *)0x400C3008)) -#define I2C7_MTPR_R (*((volatile uint32_t *)0x400C300C)) -#define I2C7_MIMR_R (*((volatile uint32_t *)0x400C3010)) -#define I2C7_MRIS_R (*((volatile uint32_t *)0x400C3014)) -#define I2C7_MMIS_R (*((volatile uint32_t *)0x400C3018)) -#define I2C7_MICR_R (*((volatile uint32_t *)0x400C301C)) -#define I2C7_MCR_R (*((volatile uint32_t *)0x400C3020)) -#define I2C7_MCLKOCNT_R (*((volatile uint32_t *)0x400C3024)) -#define I2C7_MBMON_R (*((volatile uint32_t *)0x400C302C)) -#define I2C7_MBLEN_R (*((volatile uint32_t *)0x400C3030)) -#define I2C7_MBCNT_R (*((volatile uint32_t *)0x400C3034)) -#define I2C7_SOAR_R (*((volatile uint32_t *)0x400C3800)) -#define I2C7_SCSR_R (*((volatile uint32_t *)0x400C3804)) -#define I2C7_SDR_R (*((volatile uint32_t *)0x400C3808)) -#define I2C7_SIMR_R (*((volatile uint32_t *)0x400C380C)) -#define I2C7_SRIS_R (*((volatile uint32_t *)0x400C3810)) -#define I2C7_SMIS_R (*((volatile uint32_t *)0x400C3814)) -#define I2C7_SICR_R (*((volatile uint32_t *)0x400C3818)) -#define I2C7_SOAR2_R (*((volatile uint32_t *)0x400C381C)) -#define I2C7_SACKCTL_R (*((volatile uint32_t *)0x400C3820)) -#define I2C7_FIFODATA_R (*((volatile uint32_t *)0x400C3F00)) -#define I2C7_FIFOCTL_R (*((volatile uint32_t *)0x400C3F04)) -#define I2C7_FIFOSTATUS_R (*((volatile uint32_t *)0x400C3F08)) -#define I2C7_PP_R (*((volatile uint32_t *)0x400C3FC0)) -#define I2C7_PC_R (*((volatile uint32_t *)0x400C3FC4)) - -//***************************************************************************** -// -// External Peripheral Interface registers (EPI0) -// -//***************************************************************************** -#define EPI0_CFG_R (*((volatile uint32_t *)0x400D0000)) -#define EPI0_BAUD_R (*((volatile uint32_t *)0x400D0004)) -#define EPI0_BAUD2_R (*((volatile uint32_t *)0x400D0008)) -#define EPI0_HB16CFG_R (*((volatile uint32_t *)0x400D0010)) -#define EPI0_GPCFG_R (*((volatile uint32_t *)0x400D0010)) -#define EPI0_SDRAMCFG_R (*((volatile uint32_t *)0x400D0010)) -#define EPI0_HB8CFG_R (*((volatile uint32_t *)0x400D0010)) -#define EPI0_HB8CFG2_R (*((volatile uint32_t *)0x400D0014)) -#define EPI0_HB16CFG2_R (*((volatile uint32_t *)0x400D0014)) -#define EPI0_ADDRMAP_R (*((volatile uint32_t *)0x400D001C)) -#define EPI0_RSIZE0_R (*((volatile uint32_t *)0x400D0020)) -#define EPI0_RADDR0_R (*((volatile uint32_t *)0x400D0024)) -#define EPI0_RPSTD0_R (*((volatile uint32_t *)0x400D0028)) -#define EPI0_RSIZE1_R (*((volatile uint32_t *)0x400D0030)) -#define EPI0_RADDR1_R (*((volatile uint32_t *)0x400D0034)) -#define EPI0_RPSTD1_R (*((volatile uint32_t *)0x400D0038)) -#define EPI0_STAT_R (*((volatile uint32_t *)0x400D0060)) -#define EPI0_RFIFOCNT_R (*((volatile uint32_t *)0x400D006C)) -#define EPI0_READFIFO0_R (*((volatile uint32_t *)0x400D0070)) -#define EPI0_READFIFO1_R (*((volatile uint32_t *)0x400D0074)) -#define EPI0_READFIFO2_R (*((volatile uint32_t *)0x400D0078)) -#define EPI0_READFIFO3_R (*((volatile uint32_t *)0x400D007C)) -#define EPI0_READFIFO4_R (*((volatile uint32_t *)0x400D0080)) -#define EPI0_READFIFO5_R (*((volatile uint32_t *)0x400D0084)) -#define EPI0_READFIFO6_R (*((volatile uint32_t *)0x400D0088)) -#define EPI0_READFIFO7_R (*((volatile uint32_t *)0x400D008C)) -#define EPI0_FIFOLVL_R (*((volatile uint32_t *)0x400D0200)) -#define EPI0_WFIFOCNT_R (*((volatile uint32_t *)0x400D0204)) -#define EPI0_DMATXCNT_R (*((volatile uint32_t *)0x400D0208)) -#define EPI0_IM_R (*((volatile uint32_t *)0x400D0210)) -#define EPI0_RIS_R (*((volatile uint32_t *)0x400D0214)) -#define EPI0_MIS_R (*((volatile uint32_t *)0x400D0218)) -#define EPI0_EISC_R (*((volatile uint32_t *)0x400D021C)) -#define EPI0_HB8CFG3_R (*((volatile uint32_t *)0x400D0308)) -#define EPI0_HB16CFG3_R (*((volatile uint32_t *)0x400D0308)) -#define EPI0_HB16CFG4_R (*((volatile uint32_t *)0x400D030C)) -#define EPI0_HB8CFG4_R (*((volatile uint32_t *)0x400D030C)) -#define EPI0_HB8TIME_R (*((volatile uint32_t *)0x400D0310)) -#define EPI0_HB16TIME_R (*((volatile uint32_t *)0x400D0310)) -#define EPI0_HB8TIME2_R (*((volatile uint32_t *)0x400D0314)) -#define EPI0_HB16TIME2_R (*((volatile uint32_t *)0x400D0314)) -#define EPI0_HB16TIME3_R (*((volatile uint32_t *)0x400D0318)) -#define EPI0_HB8TIME3_R (*((volatile uint32_t *)0x400D0318)) -#define EPI0_HB8TIME4_R (*((volatile uint32_t *)0x400D031C)) -#define EPI0_HB16TIME4_R (*((volatile uint32_t *)0x400D031C)) -#define EPI0_HBPSRAM_R (*((volatile uint32_t *)0x400D0360)) - -//***************************************************************************** -// -// Timer registers (TIMER6) -// -//***************************************************************************** -#define TIMER6_CFG_R (*((volatile uint32_t *)0x400E0000)) -#define TIMER6_TAMR_R (*((volatile uint32_t *)0x400E0004)) -#define TIMER6_TBMR_R (*((volatile uint32_t *)0x400E0008)) -#define TIMER6_CTL_R (*((volatile uint32_t *)0x400E000C)) -#define TIMER6_SYNC_R (*((volatile uint32_t *)0x400E0010)) -#define TIMER6_IMR_R (*((volatile uint32_t *)0x400E0018)) -#define TIMER6_RIS_R (*((volatile uint32_t *)0x400E001C)) -#define TIMER6_MIS_R (*((volatile uint32_t *)0x400E0020)) -#define TIMER6_ICR_R (*((volatile uint32_t *)0x400E0024)) -#define TIMER6_TAILR_R (*((volatile uint32_t *)0x400E0028)) -#define TIMER6_TBILR_R (*((volatile uint32_t *)0x400E002C)) -#define TIMER6_TAMATCHR_R (*((volatile uint32_t *)0x400E0030)) -#define TIMER6_TBMATCHR_R (*((volatile uint32_t *)0x400E0034)) -#define TIMER6_TAPR_R (*((volatile uint32_t *)0x400E0038)) -#define TIMER6_TBPR_R (*((volatile uint32_t *)0x400E003C)) -#define TIMER6_TAPMR_R (*((volatile uint32_t *)0x400E0040)) -#define TIMER6_TBPMR_R (*((volatile uint32_t *)0x400E0044)) -#define TIMER6_TAR_R (*((volatile uint32_t *)0x400E0048)) -#define TIMER6_TBR_R (*((volatile uint32_t *)0x400E004C)) -#define TIMER6_TAV_R (*((volatile uint32_t *)0x400E0050)) -#define TIMER6_TBV_R (*((volatile uint32_t *)0x400E0054)) -#define TIMER6_RTCPD_R (*((volatile uint32_t *)0x400E0058)) -#define TIMER6_TAPS_R (*((volatile uint32_t *)0x400E005C)) -#define TIMER6_TBPS_R (*((volatile uint32_t *)0x400E0060)) -#define TIMER6_DMAEV_R (*((volatile uint32_t *)0x400E006C)) -#define TIMER6_ADCEV_R (*((volatile uint32_t *)0x400E0070)) -#define TIMER6_PP_R (*((volatile uint32_t *)0x400E0FC0)) -#define TIMER6_CC_R (*((volatile uint32_t *)0x400E0FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER7) -// -//***************************************************************************** -#define TIMER7_CFG_R (*((volatile uint32_t *)0x400E1000)) -#define TIMER7_TAMR_R (*((volatile uint32_t *)0x400E1004)) -#define TIMER7_TBMR_R (*((volatile uint32_t *)0x400E1008)) -#define TIMER7_CTL_R (*((volatile uint32_t *)0x400E100C)) -#define TIMER7_SYNC_R (*((volatile uint32_t *)0x400E1010)) -#define TIMER7_IMR_R (*((volatile uint32_t *)0x400E1018)) -#define TIMER7_RIS_R (*((volatile uint32_t *)0x400E101C)) -#define TIMER7_MIS_R (*((volatile uint32_t *)0x400E1020)) -#define TIMER7_ICR_R (*((volatile uint32_t *)0x400E1024)) -#define TIMER7_TAILR_R (*((volatile uint32_t *)0x400E1028)) -#define TIMER7_TBILR_R (*((volatile uint32_t *)0x400E102C)) -#define TIMER7_TAMATCHR_R (*((volatile uint32_t *)0x400E1030)) -#define TIMER7_TBMATCHR_R (*((volatile uint32_t *)0x400E1034)) -#define TIMER7_TAPR_R (*((volatile uint32_t *)0x400E1038)) -#define TIMER7_TBPR_R (*((volatile uint32_t *)0x400E103C)) -#define TIMER7_TAPMR_R (*((volatile uint32_t *)0x400E1040)) -#define TIMER7_TBPMR_R (*((volatile uint32_t *)0x400E1044)) -#define TIMER7_TAR_R (*((volatile uint32_t *)0x400E1048)) -#define TIMER7_TBR_R (*((volatile uint32_t *)0x400E104C)) -#define TIMER7_TAV_R (*((volatile uint32_t *)0x400E1050)) -#define TIMER7_TBV_R (*((volatile uint32_t *)0x400E1054)) -#define TIMER7_RTCPD_R (*((volatile uint32_t *)0x400E1058)) -#define TIMER7_TAPS_R (*((volatile uint32_t *)0x400E105C)) -#define TIMER7_TBPS_R (*((volatile uint32_t *)0x400E1060)) -#define TIMER7_DMAEV_R (*((volatile uint32_t *)0x400E106C)) -#define TIMER7_ADCEV_R (*((volatile uint32_t *)0x400E1070)) -#define TIMER7_PP_R (*((volatile uint32_t *)0x400E1FC0)) -#define TIMER7_CC_R (*((volatile uint32_t *)0x400E1FC8)) - -//***************************************************************************** -// -// EMAC registers (EMAC0) -// -//***************************************************************************** -#define EMAC0_CFG_R (*((volatile uint32_t *)0x400EC000)) -#define EMAC0_FRAMEFLTR_R (*((volatile uint32_t *)0x400EC004)) -#define EMAC0_HASHTBLH_R (*((volatile uint32_t *)0x400EC008)) -#define EMAC0_HASHTBLL_R (*((volatile uint32_t *)0x400EC00C)) -#define EMAC0_MIIADDR_R (*((volatile uint32_t *)0x400EC010)) -#define EMAC0_MIIDATA_R (*((volatile uint32_t *)0x400EC014)) -#define EMAC0_FLOWCTL_R (*((volatile uint32_t *)0x400EC018)) -#define EMAC0_VLANTG_R (*((volatile uint32_t *)0x400EC01C)) -#define EMAC0_STATUS_R (*((volatile uint32_t *)0x400EC024)) -#define EMAC0_RWUFF_R (*((volatile uint32_t *)0x400EC028)) -#define EMAC0_PMTCTLSTAT_R (*((volatile uint32_t *)0x400EC02C)) -#define EMAC0_RIS_R (*((volatile uint32_t *)0x400EC038)) -#define EMAC0_IM_R (*((volatile uint32_t *)0x400EC03C)) -#define EMAC0_ADDR0H_R (*((volatile uint32_t *)0x400EC040)) -#define EMAC0_ADDR0L_R (*((volatile uint32_t *)0x400EC044)) -#define EMAC0_ADDR1H_R (*((volatile uint32_t *)0x400EC048)) -#define EMAC0_ADDR1L_R (*((volatile uint32_t *)0x400EC04C)) -#define EMAC0_ADDR2H_R (*((volatile uint32_t *)0x400EC050)) -#define EMAC0_ADDR2L_R (*((volatile uint32_t *)0x400EC054)) -#define EMAC0_ADDR3H_R (*((volatile uint32_t *)0x400EC058)) -#define EMAC0_ADDR3L_R (*((volatile uint32_t *)0x400EC05C)) -#define EMAC0_WDOGTO_R (*((volatile uint32_t *)0x400EC0DC)) -#define EMAC0_MMCCTRL_R (*((volatile uint32_t *)0x400EC100)) -#define EMAC0_MMCRXRIS_R (*((volatile uint32_t *)0x400EC104)) -#define EMAC0_MMCTXRIS_R (*((volatile uint32_t *)0x400EC108)) -#define EMAC0_MMCRXIM_R (*((volatile uint32_t *)0x400EC10C)) -#define EMAC0_MMCTXIM_R (*((volatile uint32_t *)0x400EC110)) -#define EMAC0_TXCNTGB_R (*((volatile uint32_t *)0x400EC118)) -#define EMAC0_TXCNTSCOL_R (*((volatile uint32_t *)0x400EC14C)) -#define EMAC0_TXCNTMCOL_R (*((volatile uint32_t *)0x400EC150)) -#define EMAC0_TXOCTCNTG_R (*((volatile uint32_t *)0x400EC164)) -#define EMAC0_RXCNTGB_R (*((volatile uint32_t *)0x400EC180)) -#define EMAC0_RXCNTCRCERR_R (*((volatile uint32_t *)0x400EC194)) -#define EMAC0_RXCNTALGNERR_R (*((volatile uint32_t *)0x400EC198)) -#define EMAC0_RXCNTGUNI_R (*((volatile uint32_t *)0x400EC1C4)) -#define EMAC0_VLNINCREP_R (*((volatile uint32_t *)0x400EC584)) -#define EMAC0_VLANHASH_R (*((volatile uint32_t *)0x400EC588)) -#define EMAC0_TIMSTCTRL_R (*((volatile uint32_t *)0x400EC700)) -#define EMAC0_SUBSECINC_R (*((volatile uint32_t *)0x400EC704)) -#define EMAC0_TIMSEC_R (*((volatile uint32_t *)0x400EC708)) -#define EMAC0_TIMNANO_R (*((volatile uint32_t *)0x400EC70C)) -#define EMAC0_TIMSECU_R (*((volatile uint32_t *)0x400EC710)) -#define EMAC0_TIMNANOU_R (*((volatile uint32_t *)0x400EC714)) -#define EMAC0_TIMADD_R (*((volatile uint32_t *)0x400EC718)) -#define EMAC0_TARGSEC_R (*((volatile uint32_t *)0x400EC71C)) -#define EMAC0_TARGNANO_R (*((volatile uint32_t *)0x400EC720)) -#define EMAC0_HWORDSEC_R (*((volatile uint32_t *)0x400EC724)) -#define EMAC0_TIMSTAT_R (*((volatile uint32_t *)0x400EC728)) -#define EMAC0_PPSCTRL_R (*((volatile uint32_t *)0x400EC72C)) -#define EMAC0_PPS0INTVL_R (*((volatile uint32_t *)0x400EC760)) -#define EMAC0_PPS0WIDTH_R (*((volatile uint32_t *)0x400EC764)) -#define EMAC0_DMABUSMOD_R (*((volatile uint32_t *)0x400ECC00)) -#define EMAC0_TXPOLLD_R (*((volatile uint32_t *)0x400ECC04)) -#define EMAC0_RXPOLLD_R (*((volatile uint32_t *)0x400ECC08)) -#define EMAC0_RXDLADDR_R (*((volatile uint32_t *)0x400ECC0C)) -#define EMAC0_TXDLADDR_R (*((volatile uint32_t *)0x400ECC10)) -#define EMAC0_DMARIS_R (*((volatile uint32_t *)0x400ECC14)) -#define EMAC0_DMAOPMODE_R (*((volatile uint32_t *)0x400ECC18)) -#define EMAC0_DMAIM_R (*((volatile uint32_t *)0x400ECC1C)) -#define EMAC0_MFBOC_R (*((volatile uint32_t *)0x400ECC20)) -#define EMAC0_RXINTWDT_R (*((volatile uint32_t *)0x400ECC24)) -#define EMAC0_HOSTXDESC_R (*((volatile uint32_t *)0x400ECC48)) -#define EMAC0_HOSRXDESC_R (*((volatile uint32_t *)0x400ECC4C)) -#define EMAC0_HOSTXBA_R (*((volatile uint32_t *)0x400ECC50)) -#define EMAC0_HOSRXBA_R (*((volatile uint32_t *)0x400ECC54)) -#define EMAC0_PP_R (*((volatile uint32_t *)0x400ECFC0)) -#define EMAC0_PC_R (*((volatile uint32_t *)0x400ECFC4)) -#define EMAC0_CC_R (*((volatile uint32_t *)0x400ECFC8)) -#define EMAC0_EPHYRIS_R (*((volatile uint32_t *)0x400ECFD0)) -#define EMAC0_EPHYIM_R (*((volatile uint32_t *)0x400ECFD4)) -#define EMAC0_EPHYMISC_R (*((volatile uint32_t *)0x400ECFD8)) - -//***************************************************************************** -// -// EPHY registers (EMAC0) -// -//***************************************************************************** -#define EPHY_BMCR 0x00000000 // Ethernet PHY Basic Mode Control -#define EPHY_BMSR 0x00000001 // Ethernet PHY Basic Mode Status -#define EPHY_ID1 0x00000002 // Ethernet PHY Identifier Register - // 1 -#define EPHY_ID2 0x00000003 // Ethernet PHY Identifier Register - // 2 -#define EPHY_ANA 0x00000004 // Ethernet PHY Auto-Negotiation - // Advertisement -#define EPHY_ANLPA 0x00000005 // Ethernet PHY Auto-Negotiation - // Link Partner Ability -#define EPHY_ANER 0x00000006 // Ethernet PHY Auto-Negotiation - // Expansion -#define EPHY_ANNPTR 0x00000007 // Ethernet PHY Auto-Negotiation - // Next Page TX -#define EPHY_ANLNPTR 0x00000008 // Ethernet PHY Auto-Negotiation - // Link Partner Ability Next Page -#define EPHY_CFG1 0x00000009 // Ethernet PHY Configuration 1 -#define EPHY_CFG2 0x0000000A // Ethernet PHY Configuration 2 -#define EPHY_CFG3 0x0000000B // Ethernet PHY Configuration 3 -#define EPHY_REGCTL 0x0000000D // Ethernet PHY Register Control -#define EPHY_ADDAR 0x0000000E // Ethernet PHY Address or Data -#define EPHY_STS 0x00000010 // Ethernet PHY Status -#define EPHY_SCR 0x00000011 // Ethernet PHY Specific Control -#define EPHY_MISR1 0x00000012 // Ethernet PHY MII Interrupt - // Status 1 -#define EPHY_MISR2 0x00000013 // Ethernet PHY MII Interrupt - // Status 2 -#define EPHY_FCSCR 0x00000014 // Ethernet PHY False Carrier Sense - // Counter -#define EPHY_RXERCNT 0x00000015 // Ethernet PHY Receive Error Count -#define EPHY_BISTCR 0x00000016 // Ethernet PHY BIST Control -#define EPHY_LEDCR 0x00000018 // Ethernet PHY LED Control -#define EPHY_CTL 0x00000019 // Ethernet PHY Control -#define EPHY_10BTSC 0x0000001A // Ethernet PHY 10Base-T - // Status/Control - MR26 -#define EPHY_BICSR1 0x0000001B // Ethernet PHY BIST Control and - // Status 1 -#define EPHY_BICSR2 0x0000001C // Ethernet PHY BIST Control and - // Status 2 -#define EPHY_CDCR 0x0000001E // Ethernet PHY Cable Diagnostic - // Control -#define EPHY_RCR 0x0000001F // Ethernet PHY Reset Control -#define EPHY_LEDCFG 0x00000025 // Ethernet PHY LED Configuration - -//***************************************************************************** -// -// System Exception Module registers (SYSEXC) -// -//***************************************************************************** -#define SYSEXC_RIS_R (*((volatile uint32_t *)0x400F9000)) -#define SYSEXC_IM_R (*((volatile uint32_t *)0x400F9004)) -#define SYSEXC_MIS_R (*((volatile uint32_t *)0x400F9008)) -#define SYSEXC_IC_R (*((volatile uint32_t *)0x400F900C)) - -//***************************************************************************** -// -// Hibernation module registers (HIB) -// -//***************************************************************************** -#define HIB_RTCC_R (*((volatile uint32_t *)0x400FC000)) -#define HIB_RTCM0_R (*((volatile uint32_t *)0x400FC004)) -#define HIB_RTCLD_R (*((volatile uint32_t *)0x400FC00C)) -#define HIB_CTL_R (*((volatile uint32_t *)0x400FC010)) -#define HIB_IM_R (*((volatile uint32_t *)0x400FC014)) -#define HIB_RIS_R (*((volatile uint32_t *)0x400FC018)) -#define HIB_MIS_R (*((volatile uint32_t *)0x400FC01C)) -#define HIB_IC_R (*((volatile uint32_t *)0x400FC020)) -#define HIB_RTCT_R (*((volatile uint32_t *)0x400FC024)) -#define HIB_RTCSS_R (*((volatile uint32_t *)0x400FC028)) -#define HIB_IO_R (*((volatile uint32_t *)0x400FC02C)) -#define HIB_DATA_R (*((volatile uint32_t *)0x400FC030)) -#define HIB_CALCTL_R (*((volatile uint32_t *)0x400FC300)) -#define HIB_CAL0_R (*((volatile uint32_t *)0x400FC310)) -#define HIB_CAL1_R (*((volatile uint32_t *)0x400FC314)) -#define HIB_CALLD0_R (*((volatile uint32_t *)0x400FC320)) -#define HIB_CALLD1_R (*((volatile uint32_t *)0x400FC324)) -#define HIB_CALM0_R (*((volatile uint32_t *)0x400FC330)) -#define HIB_CALM1_R (*((volatile uint32_t *)0x400FC334)) -#define HIB_LOCK_R (*((volatile uint32_t *)0x400FC360)) -#define HIB_TPCTL_R (*((volatile uint32_t *)0x400FC400)) -#define HIB_TPSTAT_R (*((volatile uint32_t *)0x400FC404)) -#define HIB_TPIO_R (*((volatile uint32_t *)0x400FC410)) -#define HIB_TPLOG0_R (*((volatile uint32_t *)0x400FC4E0)) -#define HIB_TPLOG1_R (*((volatile uint32_t *)0x400FC4E4)) -#define HIB_TPLOG2_R (*((volatile uint32_t *)0x400FC4E8)) -#define HIB_TPLOG3_R (*((volatile uint32_t *)0x400FC4EC)) -#define HIB_TPLOG4_R (*((volatile uint32_t *)0x400FC4F0)) -#define HIB_TPLOG5_R (*((volatile uint32_t *)0x400FC4F4)) -#define HIB_TPLOG6_R (*((volatile uint32_t *)0x400FC4F8)) -#define HIB_TPLOG7_R (*((volatile uint32_t *)0x400FC4FC)) -#define HIB_PP_R (*((volatile uint32_t *)0x400FCFC0)) -#define HIB_CC_R (*((volatile uint32_t *)0x400FCFC8)) - -//***************************************************************************** -// -// FLASH registers (FLASH CTRL) -// -//***************************************************************************** -#define FLASH_FMA_R (*((volatile uint32_t *)0x400FD000)) -#define FLASH_FMD_R (*((volatile uint32_t *)0x400FD004)) -#define FLASH_FMC_R (*((volatile uint32_t *)0x400FD008)) -#define FLASH_FCRIS_R (*((volatile uint32_t *)0x400FD00C)) -#define FLASH_FCIM_R (*((volatile uint32_t *)0x400FD010)) -#define FLASH_FCMISC_R (*((volatile uint32_t *)0x400FD014)) -#define FLASH_FMC2_R (*((volatile uint32_t *)0x400FD020)) -#define FLASH_FWBVAL_R (*((volatile uint32_t *)0x400FD030)) -#define FLASH_FLPEKEY_R (*((volatile uint32_t *)0x400FD03C)) -#define FLASH_FWBN_R (*((volatile uint32_t *)0x400FD100)) -#define FLASH_PP_R (*((volatile uint32_t *)0x400FDFC0)) -#define FLASH_SSIZE_R (*((volatile uint32_t *)0x400FDFC4)) -#define FLASH_CONF_R (*((volatile uint32_t *)0x400FDFC8)) -#define FLASH_ROMSWMAP_R (*((volatile uint32_t *)0x400FDFCC)) -#define FLASH_DMASZ_R (*((volatile uint32_t *)0x400FDFD0)) -#define FLASH_DMAST_R (*((volatile uint32_t *)0x400FDFD4)) -#define FLASH_RVP_R (*((volatile uint32_t *)0x400FE0D4)) -#define FLASH_BOOTCFG_R (*((volatile uint32_t *)0x400FE1D0)) -#define FLASH_USERREG0_R (*((volatile uint32_t *)0x400FE1E0)) -#define FLASH_USERREG1_R (*((volatile uint32_t *)0x400FE1E4)) -#define FLASH_USERREG2_R (*((volatile uint32_t *)0x400FE1E8)) -#define FLASH_USERREG3_R (*((volatile uint32_t *)0x400FE1EC)) -#define FLASH_FMPRE0_R (*((volatile uint32_t *)0x400FE200)) -#define FLASH_FMPRE1_R (*((volatile uint32_t *)0x400FE204)) -#define FLASH_FMPRE2_R (*((volatile uint32_t *)0x400FE208)) -#define FLASH_FMPRE3_R (*((volatile uint32_t *)0x400FE20C)) -#define FLASH_FMPRE4_R (*((volatile uint32_t *)0x400FE210)) -#define FLASH_FMPRE5_R (*((volatile uint32_t *)0x400FE214)) -#define FLASH_FMPRE6_R (*((volatile uint32_t *)0x400FE218)) -#define FLASH_FMPRE7_R (*((volatile uint32_t *)0x400FE21C)) -#define FLASH_FMPRE8_R (*((volatile uint32_t *)0x400FE220)) -#define FLASH_FMPRE9_R (*((volatile uint32_t *)0x400FE224)) -#define FLASH_FMPRE10_R (*((volatile uint32_t *)0x400FE228)) -#define FLASH_FMPRE11_R (*((volatile uint32_t *)0x400FE22C)) -#define FLASH_FMPRE12_R (*((volatile uint32_t *)0x400FE230)) -#define FLASH_FMPRE13_R (*((volatile uint32_t *)0x400FE234)) -#define FLASH_FMPRE14_R (*((volatile uint32_t *)0x400FE238)) -#define FLASH_FMPRE15_R (*((volatile uint32_t *)0x400FE23C)) -#define FLASH_FMPPE0_R (*((volatile uint32_t *)0x400FE400)) -#define FLASH_FMPPE1_R (*((volatile uint32_t *)0x400FE404)) -#define FLASH_FMPPE2_R (*((volatile uint32_t *)0x400FE408)) -#define FLASH_FMPPE3_R (*((volatile uint32_t *)0x400FE40C)) -#define FLASH_FMPPE4_R (*((volatile uint32_t *)0x400FE410)) -#define FLASH_FMPPE5_R (*((volatile uint32_t *)0x400FE414)) -#define FLASH_FMPPE6_R (*((volatile uint32_t *)0x400FE418)) -#define FLASH_FMPPE7_R (*((volatile uint32_t *)0x400FE41C)) -#define FLASH_FMPPE8_R (*((volatile uint32_t *)0x400FE420)) -#define FLASH_FMPPE9_R (*((volatile uint32_t *)0x400FE424)) -#define FLASH_FMPPE10_R (*((volatile uint32_t *)0x400FE428)) -#define FLASH_FMPPE11_R (*((volatile uint32_t *)0x400FE42C)) -#define FLASH_FMPPE12_R (*((volatile uint32_t *)0x400FE430)) -#define FLASH_FMPPE13_R (*((volatile uint32_t *)0x400FE434)) -#define FLASH_FMPPE14_R (*((volatile uint32_t *)0x400FE438)) -#define FLASH_FMPPE15_R (*((volatile uint32_t *)0x400FE43C)) - -//***************************************************************************** -// -// System Control registers (SYSCTL) -// -//***************************************************************************** -#define SYSCTL_DID0_R (*((volatile uint32_t *)0x400FE000)) -#define SYSCTL_DID1_R (*((volatile uint32_t *)0x400FE004)) -#define SYSCTL_PTBOCTL_R (*((volatile uint32_t *)0x400FE038)) -#define SYSCTL_RIS_R (*((volatile uint32_t *)0x400FE050)) -#define SYSCTL_IMC_R (*((volatile uint32_t *)0x400FE054)) -#define SYSCTL_MISC_R (*((volatile uint32_t *)0x400FE058)) -#define SYSCTL_RESC_R (*((volatile uint32_t *)0x400FE05C)) -#define SYSCTL_PWRTC_R (*((volatile uint32_t *)0x400FE060)) -#define SYSCTL_NMIC_R (*((volatile uint32_t *)0x400FE064)) -#define SYSCTL_MOSCCTL_R (*((volatile uint32_t *)0x400FE07C)) -#define SYSCTL_RSCLKCFG_R (*((volatile uint32_t *)0x400FE0B0)) -#define SYSCTL_MEMTIM0_R (*((volatile uint32_t *)0x400FE0C0)) -#define SYSCTL_ALTCLKCFG_R (*((volatile uint32_t *)0x400FE138)) -#define SYSCTL_DSCLKCFG_R (*((volatile uint32_t *)0x400FE144)) -#define SYSCTL_DIVSCLK_R (*((volatile uint32_t *)0x400FE148)) -#define SYSCTL_SYSPROP_R (*((volatile uint32_t *)0x400FE14C)) -#define SYSCTL_PIOSCCAL_R (*((volatile uint32_t *)0x400FE150)) -#define SYSCTL_PIOSCSTAT_R (*((volatile uint32_t *)0x400FE154)) -#define SYSCTL_PLLFREQ0_R (*((volatile uint32_t *)0x400FE160)) -#define SYSCTL_PLLFREQ1_R (*((volatile uint32_t *)0x400FE164)) -#define SYSCTL_PLLSTAT_R (*((volatile uint32_t *)0x400FE168)) -#define SYSCTL_SLPPWRCFG_R (*((volatile uint32_t *)0x400FE188)) -#define SYSCTL_DSLPPWRCFG_R (*((volatile uint32_t *)0x400FE18C)) -#define SYSCTL_NVMSTAT_R (*((volatile uint32_t *)0x400FE1A0)) -#define SYSCTL_LDOSPCTL_R (*((volatile uint32_t *)0x400FE1B4)) -#define SYSCTL_LDODPCTL_R (*((volatile uint32_t *)0x400FE1BC)) -#define SYSCTL_RESBEHAVCTL_R (*((volatile uint32_t *)0x400FE1D8)) -#define SYSCTL_HSSR_R (*((volatile uint32_t *)0x400FE1F4)) -#define SYSCTL_USBPDS_R (*((volatile uint32_t *)0x400FE280)) -#define SYSCTL_USBMPC_R (*((volatile uint32_t *)0x400FE284)) -#define SYSCTL_EMACPDS_R (*((volatile uint32_t *)0x400FE288)) -#define SYSCTL_EMACMPC_R (*((volatile uint32_t *)0x400FE28C)) -#define SYSCTL_PPWD_R (*((volatile uint32_t *)0x400FE300)) -#define SYSCTL_PPTIMER_R (*((volatile uint32_t *)0x400FE304)) -#define SYSCTL_PPGPIO_R (*((volatile uint32_t *)0x400FE308)) -#define SYSCTL_PPDMA_R (*((volatile uint32_t *)0x400FE30C)) -#define SYSCTL_PPEPI_R (*((volatile uint32_t *)0x400FE310)) -#define SYSCTL_PPHIB_R (*((volatile uint32_t *)0x400FE314)) -#define SYSCTL_PPUART_R (*((volatile uint32_t *)0x400FE318)) -#define SYSCTL_PPSSI_R (*((volatile uint32_t *)0x400FE31C)) -#define SYSCTL_PPI2C_R (*((volatile uint32_t *)0x400FE320)) -#define SYSCTL_PPUSB_R (*((volatile uint32_t *)0x400FE328)) -#define SYSCTL_PPEPHY_R (*((volatile uint32_t *)0x400FE330)) -#define SYSCTL_PPCAN_R (*((volatile uint32_t *)0x400FE334)) -#define SYSCTL_PPADC_R (*((volatile uint32_t *)0x400FE338)) -#define SYSCTL_PPACMP_R (*((volatile uint32_t *)0x400FE33C)) -#define SYSCTL_PPPWM_R (*((volatile uint32_t *)0x400FE340)) -#define SYSCTL_PPQEI_R (*((volatile uint32_t *)0x400FE344)) -#define SYSCTL_PPLPC_R (*((volatile uint32_t *)0x400FE348)) -#define SYSCTL_PPPECI_R (*((volatile uint32_t *)0x400FE350)) -#define SYSCTL_PPFAN_R (*((volatile uint32_t *)0x400FE354)) -#define SYSCTL_PPEEPROM_R (*((volatile uint32_t *)0x400FE358)) -#define SYSCTL_PPWTIMER_R (*((volatile uint32_t *)0x400FE35C)) -#define SYSCTL_PPRTS_R (*((volatile uint32_t *)0x400FE370)) -#define SYSCTL_PPCCM_R (*((volatile uint32_t *)0x400FE374)) -#define SYSCTL_PPLCD_R (*((volatile uint32_t *)0x400FE390)) -#define SYSCTL_PPOWIRE_R (*((volatile uint32_t *)0x400FE398)) -#define SYSCTL_PPEMAC_R (*((volatile uint32_t *)0x400FE39C)) -#define SYSCTL_PPHIM_R (*((volatile uint32_t *)0x400FE3A4)) -#define SYSCTL_SRWD_R (*((volatile uint32_t *)0x400FE500)) -#define SYSCTL_SRTIMER_R (*((volatile uint32_t *)0x400FE504)) -#define SYSCTL_SRGPIO_R (*((volatile uint32_t *)0x400FE508)) -#define SYSCTL_SRDMA_R (*((volatile uint32_t *)0x400FE50C)) -#define SYSCTL_SREPI_R (*((volatile uint32_t *)0x400FE510)) -#define SYSCTL_SRHIB_R (*((volatile uint32_t *)0x400FE514)) -#define SYSCTL_SRUART_R (*((volatile uint32_t *)0x400FE518)) -#define SYSCTL_SRSSI_R (*((volatile uint32_t *)0x400FE51C)) -#define SYSCTL_SRI2C_R (*((volatile uint32_t *)0x400FE520)) -#define SYSCTL_SRUSB_R (*((volatile uint32_t *)0x400FE528)) -#define SYSCTL_SREPHY_R (*((volatile uint32_t *)0x400FE530)) -#define SYSCTL_SRCAN_R (*((volatile uint32_t *)0x400FE534)) -#define SYSCTL_SRADC_R (*((volatile uint32_t *)0x400FE538)) -#define SYSCTL_SRACMP_R (*((volatile uint32_t *)0x400FE53C)) -#define SYSCTL_SRPWM_R (*((volatile uint32_t *)0x400FE540)) -#define SYSCTL_SRQEI_R (*((volatile uint32_t *)0x400FE544)) -#define SYSCTL_SREEPROM_R (*((volatile uint32_t *)0x400FE558)) -#define SYSCTL_SRCCM_R (*((volatile uint32_t *)0x400FE574)) -#define SYSCTL_SREMAC_R (*((volatile uint32_t *)0x400FE59C)) -#define SYSCTL_RCGCWD_R (*((volatile uint32_t *)0x400FE600)) -#define SYSCTL_RCGCTIMER_R (*((volatile uint32_t *)0x400FE604)) -#define SYSCTL_RCGCGPIO_R (*((volatile uint32_t *)0x400FE608)) -#define SYSCTL_RCGCDMA_R (*((volatile uint32_t *)0x400FE60C)) -#define SYSCTL_RCGCEPI_R (*((volatile uint32_t *)0x400FE610)) -#define SYSCTL_RCGCHIB_R (*((volatile uint32_t *)0x400FE614)) -#define SYSCTL_RCGCUART_R (*((volatile uint32_t *)0x400FE618)) -#define SYSCTL_RCGCSSI_R (*((volatile uint32_t *)0x400FE61C)) -#define SYSCTL_RCGCI2C_R (*((volatile uint32_t *)0x400FE620)) -#define SYSCTL_RCGCUSB_R (*((volatile uint32_t *)0x400FE628)) -#define SYSCTL_RCGCEPHY_R (*((volatile uint32_t *)0x400FE630)) -#define SYSCTL_RCGCCAN_R (*((volatile uint32_t *)0x400FE634)) -#define SYSCTL_RCGCADC_R (*((volatile uint32_t *)0x400FE638)) -#define SYSCTL_RCGCACMP_R (*((volatile uint32_t *)0x400FE63C)) -#define SYSCTL_RCGCPWM_R (*((volatile uint32_t *)0x400FE640)) -#define SYSCTL_RCGCQEI_R (*((volatile uint32_t *)0x400FE644)) -#define SYSCTL_RCGCEEPROM_R (*((volatile uint32_t *)0x400FE658)) -#define SYSCTL_RCGCCCM_R (*((volatile uint32_t *)0x400FE674)) -#define SYSCTL_RCGCEMAC_R (*((volatile uint32_t *)0x400FE69C)) -#define SYSCTL_SCGCWD_R (*((volatile uint32_t *)0x400FE700)) -#define SYSCTL_SCGCTIMER_R (*((volatile uint32_t *)0x400FE704)) -#define SYSCTL_SCGCGPIO_R (*((volatile uint32_t *)0x400FE708)) -#define SYSCTL_SCGCDMA_R (*((volatile uint32_t *)0x400FE70C)) -#define SYSCTL_SCGCEPI_R (*((volatile uint32_t *)0x400FE710)) -#define SYSCTL_SCGCHIB_R (*((volatile uint32_t *)0x400FE714)) -#define SYSCTL_SCGCUART_R (*((volatile uint32_t *)0x400FE718)) -#define SYSCTL_SCGCSSI_R (*((volatile uint32_t *)0x400FE71C)) -#define SYSCTL_SCGCI2C_R (*((volatile uint32_t *)0x400FE720)) -#define SYSCTL_SCGCUSB_R (*((volatile uint32_t *)0x400FE728)) -#define SYSCTL_SCGCEPHY_R (*((volatile uint32_t *)0x400FE730)) -#define SYSCTL_SCGCCAN_R (*((volatile uint32_t *)0x400FE734)) -#define SYSCTL_SCGCADC_R (*((volatile uint32_t *)0x400FE738)) -#define SYSCTL_SCGCACMP_R (*((volatile uint32_t *)0x400FE73C)) -#define SYSCTL_SCGCPWM_R (*((volatile uint32_t *)0x400FE740)) -#define SYSCTL_SCGCQEI_R (*((volatile uint32_t *)0x400FE744)) -#define SYSCTL_SCGCEEPROM_R (*((volatile uint32_t *)0x400FE758)) -#define SYSCTL_SCGCCCM_R (*((volatile uint32_t *)0x400FE774)) -#define SYSCTL_SCGCEMAC_R (*((volatile uint32_t *)0x400FE79C)) -#define SYSCTL_DCGCWD_R (*((volatile uint32_t *)0x400FE800)) -#define SYSCTL_DCGCTIMER_R (*((volatile uint32_t *)0x400FE804)) -#define SYSCTL_DCGCGPIO_R (*((volatile uint32_t *)0x400FE808)) -#define SYSCTL_DCGCDMA_R (*((volatile uint32_t *)0x400FE80C)) -#define SYSCTL_DCGCEPI_R (*((volatile uint32_t *)0x400FE810)) -#define SYSCTL_DCGCHIB_R (*((volatile uint32_t *)0x400FE814)) -#define SYSCTL_DCGCUART_R (*((volatile uint32_t *)0x400FE818)) -#define SYSCTL_DCGCSSI_R (*((volatile uint32_t *)0x400FE81C)) -#define SYSCTL_DCGCI2C_R (*((volatile uint32_t *)0x400FE820)) -#define SYSCTL_DCGCUSB_R (*((volatile uint32_t *)0x400FE828)) -#define SYSCTL_DCGCEPHY_R (*((volatile uint32_t *)0x400FE830)) -#define SYSCTL_DCGCCAN_R (*((volatile uint32_t *)0x400FE834)) -#define SYSCTL_DCGCADC_R (*((volatile uint32_t *)0x400FE838)) -#define SYSCTL_DCGCACMP_R (*((volatile uint32_t *)0x400FE83C)) -#define SYSCTL_DCGCPWM_R (*((volatile uint32_t *)0x400FE840)) -#define SYSCTL_DCGCQEI_R (*((volatile uint32_t *)0x400FE844)) -#define SYSCTL_DCGCEEPROM_R (*((volatile uint32_t *)0x400FE858)) -#define SYSCTL_DCGCCCM_R (*((volatile uint32_t *)0x400FE874)) -#define SYSCTL_DCGCEMAC_R (*((volatile uint32_t *)0x400FE89C)) -#define SYSCTL_PCWD_R (*((volatile uint32_t *)0x400FE900)) -#define SYSCTL_PCTIMER_R (*((volatile uint32_t *)0x400FE904)) -#define SYSCTL_PCGPIO_R (*((volatile uint32_t *)0x400FE908)) -#define SYSCTL_PCDMA_R (*((volatile uint32_t *)0x400FE90C)) -#define SYSCTL_PCEPI_R (*((volatile uint32_t *)0x400FE910)) -#define SYSCTL_PCHIB_R (*((volatile uint32_t *)0x400FE914)) -#define SYSCTL_PCUART_R (*((volatile uint32_t *)0x400FE918)) -#define SYSCTL_PCSSI_R (*((volatile uint32_t *)0x400FE91C)) -#define SYSCTL_PCI2C_R (*((volatile uint32_t *)0x400FE920)) -#define SYSCTL_PCUSB_R (*((volatile uint32_t *)0x400FE928)) -#define SYSCTL_PCEPHY_R (*((volatile uint32_t *)0x400FE930)) -#define SYSCTL_PCCAN_R (*((volatile uint32_t *)0x400FE934)) -#define SYSCTL_PCADC_R (*((volatile uint32_t *)0x400FE938)) -#define SYSCTL_PCACMP_R (*((volatile uint32_t *)0x400FE93C)) -#define SYSCTL_PCPWM_R (*((volatile uint32_t *)0x400FE940)) -#define SYSCTL_PCQEI_R (*((volatile uint32_t *)0x400FE944)) -#define SYSCTL_PCEEPROM_R (*((volatile uint32_t *)0x400FE958)) -#define SYSCTL_PCCCM_R (*((volatile uint32_t *)0x400FE974)) -#define SYSCTL_PCEMAC_R (*((volatile uint32_t *)0x400FE99C)) -#define SYSCTL_PRWD_R (*((volatile uint32_t *)0x400FEA00)) -#define SYSCTL_PRTIMER_R (*((volatile uint32_t *)0x400FEA04)) -#define SYSCTL_PRGPIO_R (*((volatile uint32_t *)0x400FEA08)) -#define SYSCTL_PRDMA_R (*((volatile uint32_t *)0x400FEA0C)) -#define SYSCTL_PREPI_R (*((volatile uint32_t *)0x400FEA10)) -#define SYSCTL_PRHIB_R (*((volatile uint32_t *)0x400FEA14)) -#define SYSCTL_PRUART_R (*((volatile uint32_t *)0x400FEA18)) -#define SYSCTL_PRSSI_R (*((volatile uint32_t *)0x400FEA1C)) -#define SYSCTL_PRI2C_R (*((volatile uint32_t *)0x400FEA20)) -#define SYSCTL_PRUSB_R (*((volatile uint32_t *)0x400FEA28)) -#define SYSCTL_PREPHY_R (*((volatile uint32_t *)0x400FEA30)) -#define SYSCTL_PRCAN_R (*((volatile uint32_t *)0x400FEA34)) -#define SYSCTL_PRADC_R (*((volatile uint32_t *)0x400FEA38)) -#define SYSCTL_PRACMP_R (*((volatile uint32_t *)0x400FEA3C)) -#define SYSCTL_PRPWM_R (*((volatile uint32_t *)0x400FEA40)) -#define SYSCTL_PRQEI_R (*((volatile uint32_t *)0x400FEA44)) -#define SYSCTL_PREEPROM_R (*((volatile uint32_t *)0x400FEA58)) -#define SYSCTL_PRCCM_R (*((volatile uint32_t *)0x400FEA74)) -#define SYSCTL_PREMAC_R (*((volatile uint32_t *)0x400FEA9C)) - -//***************************************************************************** -// -// Micro Direct Memory Access registers (UDMA) -// -//***************************************************************************** -#define UDMA_STAT_R (*((volatile uint32_t *)0x400FF000)) -#define UDMA_CFG_R (*((volatile uint32_t *)0x400FF004)) -#define UDMA_CTLBASE_R (*((volatile uint32_t *)0x400FF008)) -#define UDMA_ALTBASE_R (*((volatile uint32_t *)0x400FF00C)) -#define UDMA_WAITSTAT_R (*((volatile uint32_t *)0x400FF010)) -#define UDMA_SWREQ_R (*((volatile uint32_t *)0x400FF014)) -#define UDMA_USEBURSTSET_R (*((volatile uint32_t *)0x400FF018)) -#define UDMA_USEBURSTCLR_R (*((volatile uint32_t *)0x400FF01C)) -#define UDMA_REQMASKSET_R (*((volatile uint32_t *)0x400FF020)) -#define UDMA_REQMASKCLR_R (*((volatile uint32_t *)0x400FF024)) -#define UDMA_ENASET_R (*((volatile uint32_t *)0x400FF028)) -#define UDMA_ENACLR_R (*((volatile uint32_t *)0x400FF02C)) -#define UDMA_ALTSET_R (*((volatile uint32_t *)0x400FF030)) -#define UDMA_ALTCLR_R (*((volatile uint32_t *)0x400FF034)) -#define UDMA_PRIOSET_R (*((volatile uint32_t *)0x400FF038)) -#define UDMA_PRIOCLR_R (*((volatile uint32_t *)0x400FF03C)) -#define UDMA_ERRCLR_R (*((volatile uint32_t *)0x400FF04C)) -#define UDMA_CHASGN_R (*((volatile uint32_t *)0x400FF500)) -#define UDMA_CHMAP0_R (*((volatile uint32_t *)0x400FF510)) -#define UDMA_CHMAP1_R (*((volatile uint32_t *)0x400FF514)) -#define UDMA_CHMAP2_R (*((volatile uint32_t *)0x400FF518)) -#define UDMA_CHMAP3_R (*((volatile uint32_t *)0x400FF51C)) - -//***************************************************************************** -// -// Micro Direct Memory Access (uDMA) offsets (UDMA) -// -//***************************************************************************** -#define UDMA_SRCENDP 0x00000000 // DMA Channel Source Address End - // Pointer -#define UDMA_DSTENDP 0x00000004 // DMA Channel Destination Address - // End Pointer -#define UDMA_CHCTL 0x00000008 // DMA Channel Control Word - -//***************************************************************************** -// -// EC registers (CCM0) -// -//***************************************************************************** -#define CCM0_CRCCTRL_R (*((volatile uint32_t *)0x44030400)) -#define CCM0_CRCSEED_R (*((volatile uint32_t *)0x44030410)) -#define CCM0_CRCDIN_R (*((volatile uint32_t *)0x44030414)) -#define CCM0_CRCRSLTPP_R (*((volatile uint32_t *)0x44030418)) - -//***************************************************************************** -// -// NVIC registers (NVIC) -// -//***************************************************************************** -#define NVIC_ACTLR_R (*((volatile uint32_t *)0xE000E008)) -#define NVIC_ST_CTRL_R (*((volatile uint32_t *)0xE000E010)) -#define NVIC_ST_RELOAD_R (*((volatile uint32_t *)0xE000E014)) -#define NVIC_ST_CURRENT_R (*((volatile uint32_t *)0xE000E018)) -#define NVIC_EN0_R (*((volatile uint32_t *)0xE000E100)) -#define NVIC_EN1_R (*((volatile uint32_t *)0xE000E104)) -#define NVIC_EN2_R (*((volatile uint32_t *)0xE000E108)) -#define NVIC_EN3_R (*((volatile uint32_t *)0xE000E10C)) -#define NVIC_DIS0_R (*((volatile uint32_t *)0xE000E180)) -#define NVIC_DIS1_R (*((volatile uint32_t *)0xE000E184)) -#define NVIC_DIS2_R (*((volatile uint32_t *)0xE000E188)) -#define NVIC_DIS3_R (*((volatile uint32_t *)0xE000E18C)) -#define NVIC_PEND0_R (*((volatile uint32_t *)0xE000E200)) -#define NVIC_PEND1_R (*((volatile uint32_t *)0xE000E204)) -#define NVIC_PEND2_R (*((volatile uint32_t *)0xE000E208)) -#define NVIC_PEND3_R (*((volatile uint32_t *)0xE000E20C)) -#define NVIC_UNPEND0_R (*((volatile uint32_t *)0xE000E280)) -#define NVIC_UNPEND1_R (*((volatile uint32_t *)0xE000E284)) -#define NVIC_UNPEND2_R (*((volatile uint32_t *)0xE000E288)) -#define NVIC_UNPEND3_R (*((volatile uint32_t *)0xE000E28C)) -#define NVIC_ACTIVE0_R (*((volatile uint32_t *)0xE000E300)) -#define NVIC_ACTIVE1_R (*((volatile uint32_t *)0xE000E304)) -#define NVIC_ACTIVE2_R (*((volatile uint32_t *)0xE000E308)) -#define NVIC_ACTIVE3_R (*((volatile uint32_t *)0xE000E30C)) -#define NVIC_PRI0_R (*((volatile uint32_t *)0xE000E400)) -#define NVIC_PRI1_R (*((volatile uint32_t *)0xE000E404)) -#define NVIC_PRI2_R (*((volatile uint32_t *)0xE000E408)) -#define NVIC_PRI3_R (*((volatile uint32_t *)0xE000E40C)) -#define NVIC_PRI4_R (*((volatile uint32_t *)0xE000E410)) -#define NVIC_PRI5_R (*((volatile uint32_t *)0xE000E414)) -#define NVIC_PRI6_R (*((volatile uint32_t *)0xE000E418)) -#define NVIC_PRI7_R (*((volatile uint32_t *)0xE000E41C)) -#define NVIC_PRI8_R (*((volatile uint32_t *)0xE000E420)) -#define NVIC_PRI9_R (*((volatile uint32_t *)0xE000E424)) -#define NVIC_PRI10_R (*((volatile uint32_t *)0xE000E428)) -#define NVIC_PRI11_R (*((volatile uint32_t *)0xE000E42C)) -#define NVIC_PRI12_R (*((volatile uint32_t *)0xE000E430)) -#define NVIC_PRI13_R (*((volatile uint32_t *)0xE000E434)) -#define NVIC_PRI14_R (*((volatile uint32_t *)0xE000E438)) -#define NVIC_PRI15_R (*((volatile uint32_t *)0xE000E43C)) -#define NVIC_PRI16_R (*((volatile uint32_t *)0xE000E440)) -#define NVIC_PRI17_R (*((volatile uint32_t *)0xE000E444)) -#define NVIC_PRI18_R (*((volatile uint32_t *)0xE000E448)) -#define NVIC_PRI19_R (*((volatile uint32_t *)0xE000E44C)) -#define NVIC_PRI20_R (*((volatile uint32_t *)0xE000E450)) -#define NVIC_PRI21_R (*((volatile uint32_t *)0xE000E454)) -#define NVIC_PRI22_R (*((volatile uint32_t *)0xE000E458)) -#define NVIC_PRI23_R (*((volatile uint32_t *)0xE000E45C)) -#define NVIC_PRI24_R (*((volatile uint32_t *)0xE000E460)) -#define NVIC_PRI25_R (*((volatile uint32_t *)0xE000E464)) -#define NVIC_PRI26_R (*((volatile uint32_t *)0xE000E468)) -#define NVIC_PRI27_R (*((volatile uint32_t *)0xE000E46C)) -#define NVIC_PRI28_R (*((volatile uint32_t *)0xE000E470)) -#define NVIC_CPUID_R (*((volatile uint32_t *)0xE000ED00)) -#define NVIC_INT_CTRL_R (*((volatile uint32_t *)0xE000ED04)) -#define NVIC_VTABLE_R (*((volatile uint32_t *)0xE000ED08)) -#define NVIC_APINT_R (*((volatile uint32_t *)0xE000ED0C)) -#define NVIC_SYS_CTRL_R (*((volatile uint32_t *)0xE000ED10)) -#define NVIC_CFG_CTRL_R (*((volatile uint32_t *)0xE000ED14)) -#define NVIC_SYS_PRI1_R (*((volatile uint32_t *)0xE000ED18)) -#define NVIC_SYS_PRI2_R (*((volatile uint32_t *)0xE000ED1C)) -#define NVIC_SYS_PRI3_R (*((volatile uint32_t *)0xE000ED20)) -#define NVIC_SYS_HND_CTRL_R (*((volatile uint32_t *)0xE000ED24)) -#define NVIC_FAULT_STAT_R (*((volatile uint32_t *)0xE000ED28)) -#define NVIC_HFAULT_STAT_R (*((volatile uint32_t *)0xE000ED2C)) -#define NVIC_DEBUG_STAT_R (*((volatile uint32_t *)0xE000ED30)) -#define NVIC_MM_ADDR_R (*((volatile uint32_t *)0xE000ED34)) -#define NVIC_FAULT_ADDR_R (*((volatile uint32_t *)0xE000ED38)) -#define NVIC_CPAC_R (*((volatile uint32_t *)0xE000ED88)) -#define NVIC_MPU_TYPE_R (*((volatile uint32_t *)0xE000ED90)) -#define NVIC_MPU_CTRL_R (*((volatile uint32_t *)0xE000ED94)) -#define NVIC_MPU_NUMBER_R (*((volatile uint32_t *)0xE000ED98)) -#define NVIC_MPU_BASE_R (*((volatile uint32_t *)0xE000ED9C)) -#define NVIC_MPU_ATTR_R (*((volatile uint32_t *)0xE000EDA0)) -#define NVIC_MPU_BASE1_R (*((volatile uint32_t *)0xE000EDA4)) -#define NVIC_MPU_ATTR1_R (*((volatile uint32_t *)0xE000EDA8)) -#define NVIC_MPU_BASE2_R (*((volatile uint32_t *)0xE000EDAC)) -#define NVIC_MPU_ATTR2_R (*((volatile uint32_t *)0xE000EDB0)) -#define NVIC_MPU_BASE3_R (*((volatile uint32_t *)0xE000EDB4)) -#define NVIC_MPU_ATTR3_R (*((volatile uint32_t *)0xE000EDB8)) -#define NVIC_DBG_CTRL_R (*((volatile uint32_t *)0xE000EDF0)) -#define NVIC_DBG_XFER_R (*((volatile uint32_t *)0xE000EDF4)) -#define NVIC_DBG_DATA_R (*((volatile uint32_t *)0xE000EDF8)) -#define NVIC_DBG_INT_R (*((volatile uint32_t *)0xE000EDFC)) -#define NVIC_SW_TRIG_R (*((volatile uint32_t *)0xE000EF00)) -#define NVIC_FPCC_R (*((volatile uint32_t *)0xE000EF34)) -#define NVIC_FPCA_R (*((volatile uint32_t *)0xE000EF38)) -#define NVIC_FPDSC_R (*((volatile uint32_t *)0xE000EF3C)) - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOAD register. -// -//***************************************************************************** -#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value -#define WDT_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_VALUE register. -// -//***************************************************************************** -#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value -#define WDT_VALUE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_CTL register. -// -//***************************************************************************** -#define WDT_CTL_WRC 0x80000000 // Write Complete -#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type -#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable -#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_ICR register. -// -//***************************************************************************** -#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear -#define WDT_ICR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_RIS register. -// -//***************************************************************************** -#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_MIS register. -// -//***************************************************************************** -#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock -#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WDT_LOCK_LOCKED 0x00000001 // Locked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR0 register. -// -//***************************************************************************** -#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate -#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase -#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity -#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select -#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format -#define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format -#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select -#define SSI_CR0_DSS_4 0x00000003 // 4-bit data -#define SSI_CR0_DSS_5 0x00000004 // 5-bit data -#define SSI_CR0_DSS_6 0x00000005 // 6-bit data -#define SSI_CR0_DSS_7 0x00000006 // 7-bit data -#define SSI_CR0_DSS_8 0x00000007 // 8-bit data -#define SSI_CR0_DSS_9 0x00000008 // 9-bit data -#define SSI_CR0_DSS_10 0x00000009 // 10-bit data -#define SSI_CR0_DSS_11 0x0000000A // 11-bit data -#define SSI_CR0_DSS_12 0x0000000B // 12-bit data -#define SSI_CR0_DSS_13 0x0000000C // 13-bit data -#define SSI_CR0_DSS_14 0x0000000D // 14-bit data -#define SSI_CR0_DSS_15 0x0000000E // 15-bit data -#define SSI_CR0_DSS_16 0x0000000F // 16-bit data -#define SSI_CR0_SCR_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR1 register. -// -//***************************************************************************** -#define SSI_CR1_EOM 0x00000800 // Stop Frame (End of Message) -#define SSI_CR1_FSSHLDFRM 0x00000400 // FSS Hold Frame -#define SSI_CR1_HSCLKEN 0x00000200 // High Speed Clock Enable -#define SSI_CR1_DIR 0x00000100 // SSI Direction of Operation -#define SSI_CR1_MODE_M 0x000000C0 // SSI Mode -#define SSI_CR1_MODE_LEGACY 0x00000000 // Legacy SSI mode -#define SSI_CR1_MODE_BI 0x00000040 // Bi-SSI mode -#define SSI_CR1_MODE_QUAD 0x00000080 // Quad-SSI Mode -#define SSI_CR1_MODE_ADVANCED 0x000000C0 // Advanced SSI Mode with 8-bit - // packet size -#define SSI_CR1_EOT 0x00000010 // End of Transmission -#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select -#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port - // Enable -#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_DR register. -// -//***************************************************************************** -#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data -#define SSI_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_SR register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI Busy Bit -#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full -#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty -#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full -#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CPSR register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor -#define SSI_CPSR_CPSDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_IM register. -// -//***************************************************************************** -#define SSI_IM_EOTIM 0x00000040 // End of Transmit Interrupt Mask -#define SSI_IM_DMATXIM 0x00000020 // SSI Transmit DMA Interrupt Mask -#define SSI_IM_DMARXIM 0x00000010 // SSI Receive DMA Interrupt Mask -#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask -#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask -#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt - // Mask -#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_RIS register. -// -//***************************************************************************** -#define SSI_RIS_EOTRIS 0x00000040 // End of Transmit Raw Interrupt - // Status -#define SSI_RIS_DMATXRIS 0x00000020 // SSI Transmit DMA Raw Interrupt - // Status -#define SSI_RIS_DMARXRIS 0x00000010 // SSI Receive DMA Raw Interrupt - // Status -#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt - // Status -#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt - // Status -#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw - // Interrupt Status -#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_MIS register. -// -//***************************************************************************** -#define SSI_MIS_EOTMIS 0x00000040 // End of Transmit Masked Interrupt - // Status -#define SSI_MIS_DMATXMIS 0x00000020 // SSI Transmit DMA Masked - // Interrupt Status -#define SSI_MIS_DMARXMIS 0x00000010 // SSI Receive DMA Masked Interrupt - // Status -#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked - // Interrupt Status -#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked - // Interrupt Status -#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked - // Interrupt Status -#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_ICR register. -// -//***************************************************************************** -#define SSI_ICR_EOTIC 0x00000040 // End of Transmit Interrupt Clear -#define SSI_ICR_DMATXIC 0x00000020 // SSI Transmit DMA Interrupt Clear -#define SSI_ICR_DMARXIC 0x00000010 // SSI Receive DMA Interrupt Clear -#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt - // Clear -#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_DMACTL register. -// -//***************************************************************************** -#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_PP register. -// -//***************************************************************************** -#define SSI_PP_FSSHLDFRM 0x00000008 // FSS Hold Frame Capability -#define SSI_PP_MODE_M 0x00000006 // Mode of Operation -#define SSI_PP_MODE_LEGACY 0x00000000 // Legacy SSI mode -#define SSI_PP_MODE_ADVBI 0x00000002 // Legacy mode, Advanced SSI mode - // and Bi-SSI mode enabled -#define SSI_PP_MODE_ADVBIQUAD 0x00000004 // Legacy mode, Advanced mode, - // Bi-SSI and Quad-SSI mode enabled -#define SSI_PP_HSCLK 0x00000001 // High Speed Capability - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CC register. -// -//***************************************************************************** -#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source -#define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock - // source and divisor factor) -#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DR register. -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // UART Overrun Error -#define UART_DR_BE 0x00000400 // UART Break Error -#define UART_DR_PE 0x00000200 // UART Parity Error -#define UART_DR_FE 0x00000100 // UART Framing Error -#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received -#define UART_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RSR register. -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // UART Overrun Error -#define UART_RSR_BE 0x00000004 // UART Break Error -#define UART_RSR_PE 0x00000002 // UART Parity Error -#define UART_RSR_FE 0x00000001 // UART Framing Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ECR register. -// -//***************************************************************************** -#define UART_ECR_DATA_M 0x000000FF // Error Clear -#define UART_ECR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FR register. -// -//***************************************************************************** -#define UART_FR_RI 0x00000100 // Ring Indicator -#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty -#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full -#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full -#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy -#define UART_FR_DCD 0x00000004 // Data Carrier Detect -#define UART_FR_DSR 0x00000002 // Data Set Ready -#define UART_FR_CTS 0x00000001 // Clear To Send - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ILPR register. -// -//***************************************************************************** -#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor -#define UART_ILPR_ILPDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IBRD register. -// -//***************************************************************************** -#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor -#define UART_IBRD_DIVINT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FBRD register. -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor -#define UART_FBRD_DIVFRAC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCRH register. -// -//***************************************************************************** -#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length -#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) -#define UART_LCRH_WLEN_6 0x00000020 // 6 bits -#define UART_LCRH_WLEN_7 0x00000040 // 7 bits -#define UART_LCRH_WLEN_8 0x00000060 // 8 bits -#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs -#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select -#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select -#define UART_LCRH_PEN 0x00000002 // UART Parity Enable -#define UART_LCRH_BRK 0x00000001 // UART Send Break - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CTL register. -// -//***************************************************************************** -#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send -#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send -#define UART_CTL_RTS 0x00000800 // Request to Send -#define UART_CTL_DTR 0x00000400 // Data Terminal Ready -#define UART_CTL_RXE 0x00000200 // UART Receive Enable -#define UART_CTL_TXE 0x00000100 // UART Transmit Enable -#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable -#define UART_CTL_HSE 0x00000020 // High-Speed Enable -#define UART_CTL_EOT 0x00000010 // End of Transmission -#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support -#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode -#define UART_CTL_SIREN 0x00000002 // UART SIR Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IFLS register. -// -//***************************************************************************** -#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO - // Level Select -#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full -#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full -#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) -#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full -#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full -#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO - // Level Select -#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full -#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full -#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) -#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full -#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IM register. -// -//***************************************************************************** -#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask -#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask -#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask -#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt - // Mask -#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt - // Mask -#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt - // Mask -#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt - // Mask -#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask -#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem - // Interrupt Mask -#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Mask -#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem - // Interrupt Mask -#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem - // Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RIS register. -// -//***************************************************************************** -#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt - // Status -#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status -#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status -#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw - // Interrupt Status -#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt - // Status -#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt - // Status -#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt - // Status -#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt - // Status -#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw - // Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt - // Status -#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt - // Status -#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw - // Interrupt Status -#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem - // Raw Interrupt Status -#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw - // Interrupt Status -#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_MIS register. -// -//***************************************************************************** -#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt - // Status -#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt - // Status -#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt - // Status -#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked - // Interrupt Status -#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked - // Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked - // Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked - // Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked - // Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked - // Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt - // Status -#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt - // Status -#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked - // Interrupt Status -#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem - // Masked Interrupt Status -#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked - // Interrupt Status -#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ICR register. -// -//***************************************************************************** -#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear -#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear -#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear -#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt - // Clear -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear -#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem - // Interrupt Clear -#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Clear -#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem - // Interrupt Clear -#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem - // Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DMACTL register. -// -//***************************************************************************** -#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error -#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_9BITADDR -// register. -// -//***************************************************************************** -#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode -#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode -#define UART_9BITADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_9BITAMASK -// register. -// -//***************************************************************************** -#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode -#define UART_9BITAMASK_MASK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_PP register. -// -//***************************************************************************** -#define UART_PP_MSE 0x00000008 // Modem Support Extended -#define UART_PP_MS 0x00000004 // Modem Support -#define UART_PP_NB 0x00000002 // 9-Bit Support -#define UART_PP_SC 0x00000001 // Smart Card Support - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CC register. -// -//***************************************************************************** -#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source -#define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock - // source and divisor factor) -#define UART_CC_CS_PIOSC 0x00000005 // PIOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MSA register. -// -//***************************************************************************** -#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address -#define I2C_MSA_RS 0x00000001 // Receive not send -#define I2C_MSA_SA_S 1 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCS register. -// -//***************************************************************************** -#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error -#define I2C_MCS_BURST 0x00000040 // Burst Enable -#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy -#define I2C_MCS_IDLE 0x00000020 // I2C Idle -#define I2C_MCS_QCMD 0x00000020 // Quick Command -#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost -#define I2C_MCS_HS 0x00000010 // High-Speed Enable -#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable -#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data -#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address -#define I2C_MCS_STOP 0x00000004 // Generate STOP -#define I2C_MCS_ERROR 0x00000002 // Error -#define I2C_MCS_START 0x00000002 // Generate START -#define I2C_MCS_RUN 0x00000001 // I2C Master Enable -#define I2C_MCS_BUSY 0x00000001 // I2C Busy - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MDR register. -// -//***************************************************************************** -#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data - // transferred during a transaction -#define I2C_MDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MTPR register. -// -//***************************************************************************** -#define I2C_MTPR_PULSEL_M 0x00070000 // Glitch Suppression Pulse Width -#define I2C_MTPR_PULSEL_BYPASS 0x00000000 // Bypass -#define I2C_MTPR_PULSEL_1 0x00010000 // 1 clock -#define I2C_MTPR_PULSEL_2 0x00020000 // 2 clocks -#define I2C_MTPR_PULSEL_3 0x00030000 // 3 clocks -#define I2C_MTPR_PULSEL_4 0x00040000 // 4 clocks -#define I2C_MTPR_PULSEL_8 0x00050000 // 8 clocks -#define I2C_MTPR_PULSEL_16 0x00060000 // 16 clocks -#define I2C_MTPR_PULSEL_31 0x00070000 // 31 clocks -#define I2C_MTPR_HS 0x00000080 // High-Speed Enable -#define I2C_MTPR_TPR_M 0x0000007F // Timer Period -#define I2C_MTPR_TPR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MIMR register. -// -//***************************************************************************** -#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt - // Mask -#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask -#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask -#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask -#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask -#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MRIS register. -// -//***************************************************************************** -#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt - // Status -#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt - // Status -#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt - // Status -#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt - // Status -#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt - // Status -#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt - // Status -#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt - // Status -#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status -#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt - // Status -#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MMIS register. -// -//***************************************************************************** -#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask -#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask -#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status -#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status -#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt - // Status -#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MICR register. -// -//***************************************************************************** -#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt - // Clear -#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt - // Clear -#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt - // Clear -#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt - // Clear -#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear -#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear -#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear -#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt - // Clear -#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear -#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear -#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear -#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCR register. -// -//***************************************************************************** -#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable -#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable -#define I2C_MCR_LPBK 0x00000001 // I2C Loopback - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. -// -//***************************************************************************** -#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count -#define I2C_MCLKOCNT_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBMON register. -// -//***************************************************************************** -#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status -#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBLEN register. -// -//***************************************************************************** -#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length -#define I2C_MBLEN_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBCNT register. -// -//***************************************************************************** -#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count -#define I2C_MBCNT_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR register. -// -//***************************************************************************** -#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address -#define I2C_SOAR_OAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SCSR register. -// -//***************************************************************************** -#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write -#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status -#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched -#define I2C_SCSR_FBR 0x00000004 // First Byte Received -#define I2C_SCSR_RXFIFO 0x00000004 // RX FIFO Enable -#define I2C_SCSR_TXFIFO 0x00000002 // TX FIFO Enable -#define I2C_SCSR_TREQ 0x00000002 // Transmit Request -#define I2C_SCSR_DA 0x00000001 // Device Active -#define I2C_SCSR_RREQ 0x00000001 // Receive Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SDR register. -// -//***************************************************************************** -#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer -#define I2C_SDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SIMR register. -// -//***************************************************************************** -#define I2C_SIMR_RXFFIM 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask -#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask -#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask -#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask -#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SRIS register. -// -//***************************************************************************** -#define I2C_SRIS_RXFFRIS 0x00000100 // Receive FIFO Full Raw Interrupt - // Status -#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt - // Status -#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt - // Status -#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status -#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt - // Status -#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt - // Status -#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SMIS register. -// -//***************************************************************************** -#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt - // Status -#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt - // Status -#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt - // Status -#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt - // Status -#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SICR register. -// -//***************************************************************************** -#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask -#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask -#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear -#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear -#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear -#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear -#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR2 register. -// -//***************************************************************************** -#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable -#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 -#define I2C_SOAR2_OAR2_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SACKCTL register. -// -//***************************************************************************** -#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value -#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFODATA register. -// -//***************************************************************************** -#define I2C_FIFODATA_DATA_M 0x000000FF // I2C TX FIFO Write Data Byte -#define I2C_FIFODATA_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOCTL register. -// -//***************************************************************************** -#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment -#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush -#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable -#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger -#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment -#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush -#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable -#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger -#define I2C_FIFOCTL_RXTRIG_S 16 -#define I2C_FIFOCTL_TXTRIG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOSTATUS -// register. -// -//***************************************************************************** -#define I2C_FIFOSTATUS_RXABVTRIG \ - 0x00040000 // RX FIFO Above Trigger Level -#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full -#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty -#define I2C_FIFOSTATUS_TXBLWTRIG \ - 0x00000004 // TX FIFO Below Trigger Level -#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full -#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PP register. -// -//***************************************************************************** -#define I2C_PP_HS 0x00000001 // High-Speed Capable - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PC register. -// -//***************************************************************************** -#define I2C_PC_HS 0x00000001 // High-Speed Capable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_CTL register. -// -//***************************************************************************** -#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 -#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 -#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 -#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_SYNC register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter -#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ENABLE register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM7EN 0x00000080 // MnPWM7 Output Enable -#define PWM_ENABLE_PWM6EN 0x00000040 // MnPWM6 Output Enable -#define PWM_ENABLE_PWM5EN 0x00000020 // MnPWM5 Output Enable -#define PWM_ENABLE_PWM4EN 0x00000010 // MnPWM4 Output Enable -#define PWM_ENABLE_PWM3EN 0x00000008 // MnPWM3 Output Enable -#define PWM_ENABLE_PWM2EN 0x00000004 // MnPWM2 Output Enable -#define PWM_ENABLE_PWM1EN 0x00000002 // MnPWM1 Output Enable -#define PWM_ENABLE_PWM0EN 0x00000001 // MnPWM0 Output Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INVERT register. -// -//***************************************************************************** -#define PWM_INVERT_PWM7INV 0x00000080 // Invert MnPWM7 Signal -#define PWM_INVERT_PWM6INV 0x00000040 // Invert MnPWM6 Signal -#define PWM_INVERT_PWM5INV 0x00000020 // Invert MnPWM5 Signal -#define PWM_INVERT_PWM4INV 0x00000010 // Invert MnPWM4 Signal -#define PWM_INVERT_PWM3INV 0x00000008 // Invert MnPWM3 Signal -#define PWM_INVERT_PWM2INV 0x00000004 // Invert MnPWM2 Signal -#define PWM_INVERT_PWM1INV 0x00000002 // Invert MnPWM1 Signal -#define PWM_INVERT_PWM0INV 0x00000001 // Invert MnPWM0 Signal - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_FAULT register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT7 0x00000080 // MnPWM7 Fault -#define PWM_FAULT_FAULT6 0x00000040 // MnPWM6 Fault -#define PWM_FAULT_FAULT5 0x00000020 // MnPWM5 Fault -#define PWM_FAULT_FAULT4 0x00000010 // MnPWM4 Fault -#define PWM_FAULT_FAULT3 0x00000008 // MnPWM3 Fault -#define PWM_FAULT_FAULT2 0x00000004 // MnPWM2 Fault -#define PWM_FAULT_FAULT1 0x00000002 // MnPWM1 Fault -#define PWM_FAULT_FAULT0 0x00000001 // MnPWM0 Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INTEN register. -// -//***************************************************************************** -#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3 -#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2 -#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 -#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 -#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable -#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable -#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable -#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_RIS register. -// -//***************************************************************************** -#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3 -#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2 -#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 -#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 -#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted -#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted -#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted -#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ISC register. -// -//***************************************************************************** -#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted -#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted -#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted -#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted -#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status -#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status -#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status -#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_STATUS register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status -#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status -#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status -#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_FAULTVAL register. -// -//***************************************************************************** -#define PWM_FAULTVAL_PWM7 0x00000080 // MnPWM7 Fault Value -#define PWM_FAULTVAL_PWM6 0x00000040 // MnPWM6 Fault Value -#define PWM_FAULTVAL_PWM5 0x00000020 // MnPWM5 Fault Value -#define PWM_FAULTVAL_PWM4 0x00000010 // MnPWM4 Fault Value -#define PWM_FAULTVAL_PWM3 0x00000008 // MnPWM3 Fault Value -#define PWM_FAULTVAL_PWM2 0x00000004 // MnPWM2 Fault Value -#define PWM_FAULTVAL_PWM1 0x00000002 // MnPWM1 Fault Value -#define PWM_FAULTVAL_PWM0 0x00000001 // MnPWM0 Fault Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ENUPD register. -// -//***************************************************************************** -#define PWM_ENUPD_ENUPD7_M 0x0000C000 // MnPWM7 Enable Update Mode -#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized -#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized -#define PWM_ENUPD_ENUPD6_M 0x00003000 // MnPWM6 Enable Update Mode -#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized -#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized -#define PWM_ENUPD_ENUPD5_M 0x00000C00 // MnPWM5 Enable Update Mode -#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized -#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized -#define PWM_ENUPD_ENUPD4_M 0x00000300 // MnPWM4 Enable Update Mode -#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized -#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized -#define PWM_ENUPD_ENUPD3_M 0x000000C0 // MnPWM3 Enable Update Mode -#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized -#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized -#define PWM_ENUPD_ENUPD2_M 0x00000030 // MnPWM2 Enable Update Mode -#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized -#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized -#define PWM_ENUPD_ENUPD1_M 0x0000000C // MnPWM1 Enable Update Mode -#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized -#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized -#define PWM_ENUPD_ENUPD0_M 0x00000003 // MnPWM0 Enable Update Mode -#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized -#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CTL register. -// -//***************************************************************************** -#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_0_CTL_MODE 0x00000002 // Counter Mode -#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_INTEN register. -// -//***************************************************************************** -#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_RIS register. -// -//***************************************************************************** -#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_ISC register. -// -//***************************************************************************** -#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_LOAD register. -// -//***************************************************************************** -#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_0_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_COUNT register. -// -//***************************************************************************** -#define PWM_0_COUNT_M 0x0000FFFF // Counter Value -#define PWM_0_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CMPA register. -// -//***************************************************************************** -#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value -#define PWM_0_CMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CMPB register. -// -//***************************************************************************** -#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value -#define PWM_0_CMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_GENA register. -// -//***************************************************************************** -#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_0_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_0_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_0_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_0_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_0_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_0_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_0_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_0_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_GENB register. -// -//***************************************************************************** -#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_0_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_0_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_0_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_0_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_0_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_0_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_0_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_0_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBCTL register. -// -//***************************************************************************** -#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBRISE register. -// -//***************************************************************************** -#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay -#define PWM_0_DBRISE_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBFALL register. -// -//***************************************************************************** -#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay -#define PWM_0_DBFALL_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period -#define PWM_0_MINFLTPER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CTL register. -// -//***************************************************************************** -#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_1_CTL_MODE 0x00000002 // Counter Mode -#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_INTEN register. -// -//***************************************************************************** -#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_RIS register. -// -//***************************************************************************** -#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_ISC register. -// -//***************************************************************************** -#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_LOAD register. -// -//***************************************************************************** -#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_1_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_COUNT register. -// -//***************************************************************************** -#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_1_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CMPA register. -// -//***************************************************************************** -#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_1_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CMPB register. -// -//***************************************************************************** -#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_1_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_GENA register. -// -//***************************************************************************** -#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_1_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_1_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_1_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_1_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_1_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_1_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_1_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_1_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_GENB register. -// -//***************************************************************************** -#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_1_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_1_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_1_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_1_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_1_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_1_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_1_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_1_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBCTL register. -// -//***************************************************************************** -#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBRISE register. -// -//***************************************************************************** -#define PWM_1_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_1_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBFALL register. -// -//***************************************************************************** -#define PWM_1_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_1_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_1_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CTL register. -// -//***************************************************************************** -#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_2_CTL_MODE 0x00000002 // Counter Mode -#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_INTEN register. -// -//***************************************************************************** -#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_RIS register. -// -//***************************************************************************** -#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_ISC register. -// -//***************************************************************************** -#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_LOAD register. -// -//***************************************************************************** -#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_2_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_COUNT register. -// -//***************************************************************************** -#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_2_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CMPA register. -// -//***************************************************************************** -#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_2_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CMPB register. -// -//***************************************************************************** -#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_2_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_GENA register. -// -//***************************************************************************** -#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_2_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_2_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_2_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_2_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_2_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_2_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_2_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_2_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_GENB register. -// -//***************************************************************************** -#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_2_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_2_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_2_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_2_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_2_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_2_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_2_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_2_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBCTL register. -// -//***************************************************************************** -#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBRISE register. -// -//***************************************************************************** -#define PWM_2_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_2_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBFALL register. -// -//***************************************************************************** -#define PWM_2_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_2_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_2_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CTL register. -// -//***************************************************************************** -#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_3_CTL_MODE 0x00000002 // Counter Mode -#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_INTEN register. -// -//***************************************************************************** -#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_RIS register. -// -//***************************************************************************** -#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_ISC register. -// -//***************************************************************************** -#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_LOAD register. -// -//***************************************************************************** -#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_3_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_COUNT register. -// -//***************************************************************************** -#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_3_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CMPA register. -// -//***************************************************************************** -#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_3_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CMPB register. -// -//***************************************************************************** -#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_3_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_GENA register. -// -//***************************************************************************** -#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_3_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_3_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_3_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_3_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_3_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_3_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_3_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_3_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_GENB register. -// -//***************************************************************************** -#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_3_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_3_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_3_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_3_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_3_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_3_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_3_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_3_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBCTL register. -// -//***************************************************************************** -#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBRISE register. -// -//***************************************************************************** -#define PWM_3_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_3_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBFALL register. -// -//***************************************************************************** -#define PWM_3_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_3_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_3_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSEN register. -// -//***************************************************************************** -#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSEN register. -// -//***************************************************************************** -#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSEN register. -// -//***************************************************************************** -#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSEN register. -// -//***************************************************************************** -#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_PP register. -// -//***************************************************************************** -#define PWM_PP_ONE 0x00000400 // One-Shot Mode -#define PWM_PP_EFAULT 0x00000200 // Extended Fault -#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization -#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs (per PWM unit) -#define PWM_PP_GCNT_M 0x0000000F // Generators -#define PWM_PP_FCNT_S 4 -#define PWM_PP_GCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_CC register. -// -//***************************************************************************** -#define PWM_CC_USEPWM 0x00000100 // Use PWM Clock Divisor -#define PWM_CC_PWMDIV_M 0x00000007 // PWM Clock Divider -#define PWM_CC_PWMDIV_2 0x00000000 // /2 -#define PWM_CC_PWMDIV_4 0x00000001 // /4 -#define PWM_CC_PWMDIV_8 0x00000002 // /8 -#define PWM_CC_PWMDIV_16 0x00000003 // /16 -#define PWM_CC_PWMDIV_32 0x00000004 // /32 -#define PWM_CC_PWMDIV_64 0x00000005 // /64 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_CTL register. -// -//***************************************************************************** -#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count -#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter -#define QEI_CTL_STALLEN 0x00001000 // Stall QEI -#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse -#define QEI_CTL_INVB 0x00000400 // Invert PhB -#define QEI_CTL_INVA 0x00000200 // Invert PhA -#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity -#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 -#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 -#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 -#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 -#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 -#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 -#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 -#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 -#define QEI_CTL_VELEN 0x00000020 // Capture Velocity -#define QEI_CTL_RESMODE 0x00000010 // Reset Mode -#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode -#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode -#define QEI_CTL_SWAP 0x00000002 // Swap Signals -#define QEI_CTL_ENABLE 0x00000001 // Enable QEI -#define QEI_CTL_FILTCNT_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation -#define QEI_STAT_ERROR 0x00000001 // Error Detected - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator - // Value -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator - // Value -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Velocity -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable -#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt - // Enable -#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable -#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected -#define QEI_RIS_DIR 0x00000004 // Direction Change Detected -#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired -#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_ISC register. -// -//***************************************************************************** -#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt -#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt -#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt -#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_M 0x00000007 // GPTM Configuration -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this - // value selects the 32-bit timer - // configuration -#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this - // value selects the 32-bit - // real-time clock (RTC) counter - // configuration -#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this - // value selects the 16-bit timer - // configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMR register. -// -//***************************************************************************** -#define TIMER_TAMR_TCACT_M 0x0000E000 // Timer Compare Action Select -#define TIMER_TAMR_TCACT_NONE 0x00000000 // Disable compare operations -#define TIMER_TAMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out -#define TIMER_TAMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out -#define TIMER_TAMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out -#define TIMER_TAMR_TCACT_SETTOGTO \ - 0x00008000 // Set CCP immediately and toggle - // on Time-Out -#define TIMER_TAMR_TCACT_CLRTOGTO \ - 0x0000A000 // Clear CCP immediately and toggle - // on Time-Out -#define TIMER_TAMR_TCACT_SETCLRTO \ - 0x0000C000 // Set CCP immediately and clear on - // Time-Out -#define TIMER_TAMR_TCACT_CLRSETTO \ - 0x0000E000 // Clear CCP immediately and set on - // Time-Out -#define TIMER_TAMR_TACINTD 0x00001000 // One-shot/Periodic Interrupt - // Disable -#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy - // Operation -#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register - // Update -#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt - // Enable -#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write -#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode -#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger -#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt - // Enable -#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction -#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode - // Select -#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode -#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode -#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMR register. -// -//***************************************************************************** -#define TIMER_TBMR_TCACT_M 0x0000E000 // Timer Compare Action Select -#define TIMER_TBMR_TCACT_NONE 0x00000000 // Disable compare operations -#define TIMER_TBMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out -#define TIMER_TBMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out -#define TIMER_TBMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out -#define TIMER_TBMR_TCACT_SETTOGTO \ - 0x00008000 // Set CCP immediately and toggle - // on Time-Out -#define TIMER_TBMR_TCACT_CLRTOGTO \ - 0x0000A000 // Clear CCP immediately and toggle - // on Time-Out -#define TIMER_TBMR_TCACT_SETCLRTO \ - 0x0000C000 // Set CCP immediately and clear on - // Time-Out -#define TIMER_TBMR_TCACT_CLRSETTO \ - 0x0000E000 // Clear CCP immediately and set on - // Time-Out -#define TIMER_TBMR_TBCINTD 0x00001000 // One-Shot/Periodic Interrupt - // Disable -#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy - // Operation -#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register - // Update -#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt - // Enable -#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write -#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode -#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger -#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt - // Enable -#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction -#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode - // Select -#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode -#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode -#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level -#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger - // Enable -#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode -#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges -#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable -#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable -#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level -#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger - // Enable -#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable -#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode -#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges -#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable -#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_SYNC register. -// -//***************************************************************************** -#define TIMER_SYNC_SYNCT7_M 0x0000C000 // Synchronize GPTM Timer 7 -#define TIMER_SYNC_SYNCT7_NONE 0x00000000 // GPT7 is not affected -#define TIMER_SYNC_SYNCT7_TA 0x00004000 // A timeout event for Timer A of - // GPTM7 is triggered -#define TIMER_SYNC_SYNCT7_TB 0x00008000 // A timeout event for Timer B of - // GPTM7 is triggered -#define TIMER_SYNC_SYNCT7_TATB 0x0000C000 // A timeout event for both Timer A - // and Timer B of GPTM7 is - // triggered -#define TIMER_SYNC_SYNCT6_M 0x00003000 // Synchronize GPTM Timer 6 -#define TIMER_SYNC_SYNCT6_NONE 0x00000000 // GPTM6 is not affected -#define TIMER_SYNC_SYNCT6_TA 0x00001000 // A timeout event for Timer A of - // GPTM6 is triggered -#define TIMER_SYNC_SYNCT6_TB 0x00002000 // A timeout event for Timer B of - // GPTM6 is triggered -#define TIMER_SYNC_SYNCT6_TATB 0x00003000 // A timeout event for both Timer A - // and Timer B of GPTM6 is - // triggered -#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5 -#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected -#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of - // GPTM5 is triggered -#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of - // GPTM5 is triggered -#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A - // and Timer B of GPTM5 is - // triggered -#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4 -#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected -#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of - // GPTM4 is triggered -#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of - // GPTM4 is triggered -#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A - // and Timer B of GPTM4 is - // triggered -#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3 -#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected -#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of - // GPTM3 is triggered -#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of - // GPTM3 is triggered -#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A - // and Timer B of GPTM3 is - // triggered -#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2 -#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected -#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of - // GPTM2 is triggered -#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of - // GPTM2 is triggered -#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A - // and Timer B of GPTM2 is - // triggered -#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1 -#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected -#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of - // GPTM1 is triggered -#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of - // GPTM1 is triggered -#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A - // and Timer B of GPTM1 is - // triggered -#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0 -#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected -#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of - // GPTM0 is triggered -#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of - // GPTM0 is triggered -#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A - // and Timer B of GPTM0 is - // triggered - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_DMABIM 0x00002000 // GPTM Timer B DMA Done Interrupt - // Mask -#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt - // Mask -#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event - // Interrupt Mask -#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match - // Interrupt Mask -#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt - // Mask -#define TIMER_IMR_DMAAIM 0x00000020 // GPTM Timer A DMA Done Interrupt - // Mask -#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt - // Mask -#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask -#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event - // Interrupt Mask -#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match - // Interrupt Mask -#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_DMABRIS 0x00002000 // GPTM Timer B DMA Done Raw - // Interrupt Status -#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt -#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event - // Raw Interrupt -#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match - // Raw Interrupt -#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw - // Interrupt -#define TIMER_RIS_DMAARIS 0x00000020 // GPTM Timer A DMA Done Raw - // Interrupt Status -#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt -#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt -#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event - // Raw Interrupt -#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match - // Raw Interrupt -#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_MIS register. -// -//***************************************************************************** -#define TIMER_MIS_DMABMIS 0x00002000 // GPTM Timer B DMA Done Masked - // Interrupt -#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked - // Interrupt -#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event - // Masked Interrupt -#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match - // Masked Interrupt -#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked - // Interrupt -#define TIMER_MIS_DMAAMIS 0x00000020 // GPTM Timer A DMA Done Masked - // Interrupt -#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked - // Interrupt -#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt -#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event - // Masked Interrupt -#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match - // Masked Interrupt -#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_DMABINT 0x00002000 // GPTM Timer B DMA Done Interrupt - // Clear -#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt - // Clear -#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event - // Interrupt Clear -#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match - // Interrupt Clear -#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt - // Clear -#define TIMER_ICR_DMAAINT 0x00000020 // GPTM Timer A DMA Done Interrupt - // Clear -#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt - // Clear -#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear -#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event - // Interrupt Clear -#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match - // Interrupt Clear -#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load - // Register -#define TIMER_TAILR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load - // Register -#define TIMER_TBILR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register -#define TIMER_TAMATCHR_TAMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register -#define TIMER_TBMATCHR_TBMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPR register. -// -//***************************************************************************** -#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale -#define TIMER_TAPR_TAPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPR register. -// -//***************************************************************************** -#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale -#define TIMER_TBPR_TBPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPMR register. -// -//***************************************************************************** -#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match -#define TIMER_TAPMR_TAPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPMR register. -// -//***************************************************************************** -#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match -#define TIMER_TBPMR_TBPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register -#define TIMER_TAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register -#define TIMER_TBR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAV register. -// -//***************************************************************************** -#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value -#define TIMER_TAV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBV register. -// -//***************************************************************************** -#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value -#define TIMER_TBV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RTCPD register. -// -//***************************************************************************** -#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value -#define TIMER_RTCPD_RTCPD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPS register. -// -//***************************************************************************** -#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot -#define TIMER_TAPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPS register. -// -//***************************************************************************** -#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TBPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_DMAEV register. -// -//***************************************************************************** -#define TIMER_DMAEV_TBMDMAEN 0x00000800 // GPTM B Mode Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_CBEDMAEN 0x00000400 // GPTM B Capture Event DMA Trigger - // Enable -#define TIMER_DMAEV_CBMDMAEN 0x00000200 // GPTM B Capture Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_TBTODMAEN 0x00000100 // GPTM B Time-Out Event DMA - // Trigger Enable -#define TIMER_DMAEV_TAMDMAEN 0x00000010 // GPTM A Mode Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_RTCDMAEN 0x00000008 // GPTM A RTC Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_CAEDMAEN 0x00000004 // GPTM A Capture Event DMA Trigger - // Enable -#define TIMER_DMAEV_CAMDMAEN 0x00000002 // GPTM A Capture Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_TATODMAEN 0x00000001 // GPTM A Time-Out Event DMA - // Trigger Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ADCEV register. -// -//***************************************************************************** -#define TIMER_ADCEV_TBMADCEN 0x00000800 // GPTM B Mode Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_CBEADCEN 0x00000400 // GPTM B Capture Event ADC Trigger - // Enable -#define TIMER_ADCEV_CBMADCEN 0x00000200 // GPTM B Capture Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_TBTOADCEN 0x00000100 // GPTM B Time-Out Event ADC - // Trigger Enable -#define TIMER_ADCEV_TAMADCEN 0x00000010 // GPTM A Mode Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_RTCADCEN 0x00000008 // GPTM RTC Match Event ADC Trigger - // Enable -#define TIMER_ADCEV_CAEADCEN 0x00000004 // GPTM A Capture Event ADC Trigger - // Enable -#define TIMER_ADCEV_CAMADCEN 0x00000002 // GPTM A Capture Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_TATOADCEN 0x00000001 // GPTM A Time-Out Event ADC - // Trigger Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_PP register. -// -//***************************************************************************** -#define TIMER_PP_ALTCLK 0x00000040 // Alternate Clock Source -#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start -#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers -#define TIMER_PP_SIZE_M 0x0000000F // Count Size -#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are - // 16 bits each with an 8-bit - // prescale counter -#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are - // 32 bits each with a 16-bit - // prescale counter - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CC register. -// -//***************************************************************************** -#define TIMER_CC_ALTCLK 0x00000001 // Alternate Clock Source - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_BUSY 0x00010000 // ADC Busy -#define ADC_ACTSS_ADEN3 0x00000800 // ADC SS3 DMA Enable -#define ADC_ACTSS_ADEN2 0x00000400 // ADC SS2 DMA Enable -#define ADC_ACTSS_ADEN1 0x00000200 // ADC SS1 DMA Enable -#define ADC_ACTSS_ADEN0 0x00000100 // ADC SS1 DMA Enable -#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable -#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable -#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable -#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt - // Status -#define ADC_RIS_DMAINR3 0x00000800 // SS3 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR2 0x00000400 // SS2 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR1 0x00000200 // SS1 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR0 0x00000100 // SS0 DMA Raw Interrupt Status -#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status -#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status -#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status -#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_IM register. -// -//***************************************************************************** -#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on - // SS3 -#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on - // SS2 -#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on - // SS1 -#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on - // SS0 -#define ADC_IM_DMAMASK3 0x00000800 // SS3 DMA Interrupt Mask -#define ADC_IM_DMAMASK2 0x00000400 // SS2 DMA Interrupt Mask -#define ADC_IM_DMAMASK1 0x00000200 // SS1 DMA Interrupt Mask -#define ADC_IM_DMAMASK0 0x00000100 // SS0 DMA Interrupt Mask -#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask -#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask -#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask -#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ISC register. -// -//***************************************************************************** -#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt - // Status on SS3 -#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt - // Status on SS2 -#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt - // Status on SS1 -#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt - // Status on SS0 -#define ADC_ISC_DMAIN3 0x00000800 // SS3 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN2 0x00000400 // SS2 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN1 0x00000200 // SS1 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN0 0x00000100 // SS0 DMA Interrupt Status and - // Clear -#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear -#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear -#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear -#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow -#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow -#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow -#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2 -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO Pins) -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM generator 0 -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM generator 1 -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM generator 2 -#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM generator 3 -#define ADC_EMUX_EM3_NEVER 0x0000E000 // Never Trigger -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) -#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2 -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO Pins) -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM generator 0 -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM generator 1 -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM generator 2 -#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM generator 3 -#define ADC_EMUX_EM2_NEVER 0x00000E00 // Never Trigger -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) -#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2 -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO Pins) -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM generator 0 -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM generator 1 -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM generator 2 -#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM generator 3 -#define ADC_EMUX_EM1_NEVER 0x000000E0 // Never Trigger -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) -#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2 -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO Pins) -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM generator 0 -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM generator 1 -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM generator 2 -#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM generator 3 -#define ADC_EMUX_EM0_NEVER 0x0000000E // Never Trigger -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow -#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow -#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow -#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_TSSEL register. -// -//***************************************************************************** -#define ADC_TSSEL_PS3_M 0x30000000 // Generator 3 PWM Module Trigger - // Select -#define ADC_TSSEL_PS3_0 0x00000000 // Use Generator 3 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS2_M 0x00300000 // Generator 2 PWM Module Trigger - // Select -#define ADC_TSSEL_PS2_0 0x00000000 // Use Generator 2 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS1_M 0x00003000 // Generator 1 PWM Module Trigger - // Select -#define ADC_TSSEL_PS1_0 0x00000000 // Use Generator 1 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS0_M 0x00000030 // Generator 0 PWM Module Trigger - // Select -#define ADC_TSSEL_PS0_0 0x00000000 // Use Generator 0 (and its - // trigger) in PWM module 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority -#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority -#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority -#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SPC register. -// -//***************************************************************************** -#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference -#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 -#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 -#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 -#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 -#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 -#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 -#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 -#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 -#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 -#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 -#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 -#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 -#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 -#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 -#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 -#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize -#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait -#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate -#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate -#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate -#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCISC register. -// -//***************************************************************************** -#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt - // Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_CTL register. -// -//***************************************************************************** -#define ADC_CTL_VREF_M 0x00000001 // Voltage Reference Select -#define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage - // references -#define ADC_CTL_VREF_EXT_3V 0x00000001 // The external VREFA+ and VREFA- - // inputs are the voltage - // references - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX0 register. -// -//***************************************************************************** -#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select -#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select -#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select -#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select -#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX0_MUX7_S 28 -#define ADC_SSMUX0_MUX6_S 24 -#define ADC_SSMUX0_MUX5_S 20 -#define ADC_SSMUX0_MUX4_S 16 -#define ADC_SSMUX0_MUX3_S 12 -#define ADC_SSMUX0_MUX2_S 8 -#define ADC_SSMUX0_MUX1_S 4 -#define ADC_SSMUX0_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL0 register. -// -//***************************************************************************** -#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select -#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable -#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence -#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Differential Input - // Select -#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select -#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable -#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence -#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Differential Input - // Select -#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select -#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable -#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence -#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Differential Input - // Select -#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select -#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable -#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence -#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Differential Input - // Select -#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. -// -//***************************************************************************** -#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. -// -//***************************************************************************** -#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT0_HPTR_S 4 -#define ADC_SSFSTAT0_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP0 register. -// -//***************************************************************************** -#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator - // Operation -#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator - // Operation -#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator - // Operation -#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator - // Operation -#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC0 register. -// -//***************************************************************************** -#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator - // Select -#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator - // Select -#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator - // Select -#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator - // Select -#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC0_S6DCSEL_S 24 -#define ADC_SSDC0_S5DCSEL_S 20 -#define ADC_SSDC0_S4DCSEL_S 16 -#define ADC_SSDC0_S3DCSEL_S 12 -#define ADC_SSDC0_S2DCSEL_S 8 -#define ADC_SSDC0_S1DCSEL_S 4 -#define ADC_SSDC0_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX0 register. -// -//***************************************************************************** -#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH0 register. -// -//***************************************************************************** -#define ADC_SSTSH0_TSH7_M 0xF0000000 // 8th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH6_M 0x0F000000 // 7th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH5_M 0x00F00000 // 6th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH4_M 0x000F0000 // 5th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH7_S 28 -#define ADC_SSTSH0_TSH6_S 24 -#define ADC_SSTSH0_TSH5_S 20 -#define ADC_SSTSH0_TSH4_S 16 -#define ADC_SSTSH0_TSH3_S 12 -#define ADC_SSTSH0_TSH2_S 8 -#define ADC_SSTSH0_TSH1_S 4 -#define ADC_SSTSH0_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX1 register. -// -//***************************************************************************** -#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX1_MUX3_S 12 -#define ADC_SSMUX1_MUX2_S 8 -#define ADC_SSMUX1_MUX1_S 4 -#define ADC_SSMUX1_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL1 register. -// -//***************************************************************************** -#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. -// -//***************************************************************************** -#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. -// -//***************************************************************************** -#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT1_HPTR_S 4 -#define ADC_SSFSTAT1_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP1 register. -// -//***************************************************************************** -#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC1 register. -// -//***************************************************************************** -#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC1_S2DCSEL_S 8 -#define ADC_SSDC1_S1DCSEL_S 4 -#define ADC_SSDC1_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX1 register. -// -//***************************************************************************** -#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH1 register. -// -//***************************************************************************** -#define ADC_SSTSH1_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH3_S 12 -#define ADC_SSTSH1_TSH2_S 8 -#define ADC_SSTSH1_TSH1_S 4 -#define ADC_SSTSH1_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX2 register. -// -//***************************************************************************** -#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX2_MUX3_S 12 -#define ADC_SSMUX2_MUX2_S 8 -#define ADC_SSMUX2_MUX1_S 4 -#define ADC_SSMUX2_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL2 register. -// -//***************************************************************************** -#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. -// -//***************************************************************************** -#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. -// -//***************************************************************************** -#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT2_HPTR_S 4 -#define ADC_SSFSTAT2_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP2 register. -// -//***************************************************************************** -#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC2 register. -// -//***************************************************************************** -#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC2_S2DCSEL_S 8 -#define ADC_SSDC2_S1DCSEL_S 4 -#define ADC_SSDC2_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX2 register. -// -//***************************************************************************** -#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH2 register. -// -//***************************************************************************** -#define ADC_SSTSH2_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH3_S 12 -#define ADC_SSTSH2_TSH2_S 8 -#define ADC_SSTSH2_TSH1_S 4 -#define ADC_SSTSH2_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX3 register. -// -//***************************************************************************** -#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX3_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL3 register. -// -//***************************************************************************** -#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL3_IE0 0x00000004 // Sample Interrupt Enable -#define ADC_SSCTL3_END0 0x00000002 // End of Sequence -#define ADC_SSCTL3_D0 0x00000001 // Sample Differential Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. -// -//***************************************************************************** -#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. -// -//***************************************************************************** -#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT3_HPTR_S 4 -#define ADC_SSFSTAT3_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP3 register. -// -//***************************************************************************** -#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC3 register. -// -//***************************************************************************** -#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX3 register. -// -//***************************************************************************** -#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH3 register. -// -//***************************************************************************** -#define ADC_SSTSH3_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH3_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCRIC register. -// -//***************************************************************************** -#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 -#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 -#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 -#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 -#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 -#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 -#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 -#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 -#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 -#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 -#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 -#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 -#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 -#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 -#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 -#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL0 register. -// -//***************************************************************************** -#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL1 register. -// -//***************************************************************************** -#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL2 register. -// -//***************************************************************************** -#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL3 register. -// -//***************************************************************************** -#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL4 register. -// -//***************************************************************************** -#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL5 register. -// -//***************************************************************************** -#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL6 register. -// -//***************************************************************************** -#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL7 register. -// -//***************************************************************************** -#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP0 register. -// -//***************************************************************************** -#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP0_COMP1_S 16 -#define ADC_DCCMP0_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP1 register. -// -//***************************************************************************** -#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP1_COMP1_S 16 -#define ADC_DCCMP1_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP2 register. -// -//***************************************************************************** -#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP2_COMP1_S 16 -#define ADC_DCCMP2_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP3 register. -// -//***************************************************************************** -#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP3_COMP1_S 16 -#define ADC_DCCMP3_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP4 register. -// -//***************************************************************************** -#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP4_COMP1_S 16 -#define ADC_DCCMP4_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP5 register. -// -//***************************************************************************** -#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP5_COMP1_S 16 -#define ADC_DCCMP5_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP6 register. -// -//***************************************************************************** -#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP6_COMP1_S 16 -#define ADC_DCCMP6_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP7 register. -// -//***************************************************************************** -#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP7_COMP1_S 16 -#define ADC_DCCMP7_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PP register. -// -//***************************************************************************** -#define ADC_PP_APSHT 0x01000000 // Application-Programmable - // Sample-and-Hold Time -#define ADC_PP_TS 0x00800000 // Temperature Sensor -#define ADC_PP_RSL_M 0x007C0000 // Resolution -#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture -#define ADC_PP_TYPE_SAR 0x00000000 // SAR -#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count -#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count -#define ADC_PP_MCR_M 0x0000000F // Maximum Conversion Rate -#define ADC_PP_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as - // defined by TADC and NSH -#define ADC_PP_RSL_S 18 -#define ADC_PP_DC_S 10 -#define ADC_PP_CH_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PC register. -// -//***************************************************************************** -#define ADC_PC_MCR_M 0x0000000F // Conversion Rate -#define ADC_PC_MCR_1_8 0x00000001 // Eighth conversion rate. After a - // conversion completes, the logic - // pauses for 112 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_1_4 0x00000003 // Quarter conversion rate. After a - // conversion completes, the logic - // pauses for 48 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_1_2 0x00000005 // Half conversion rate. After a - // conversion completes, the logic - // pauses for 16 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as - // defined by TADC and NSH - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_CC register. -// -//***************************************************************************** -#define ADC_CC_CLKDIV_M 0x000003F0 // PLL VCO Clock Divisor -#define ADC_CC_CS_M 0x0000000F // ADC Clock Source -#define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV -#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC -#define ADC_CC_CS_MOSC 0x00000002 // MOSC -#define ADC_CC_CLKDIV_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACMIS register. -// -//***************************************************************************** -#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt - // Status -#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt - // Status -#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACRIS register. -// -//***************************************************************************** -#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status -#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status -#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACINTEN register. -// -//***************************************************************************** -#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable -#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable -#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACREFCTL -// register. -// -//***************************************************************************** -#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable -#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range -#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref -#define COMP_ACREFCTL_VREF_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. -// -//***************************************************************************** -#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL0 register. -// -//***************************************************************************** -#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. -// -//***************************************************************************** -#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL1 register. -// -//***************************************************************************** -#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT2 register. -// -//***************************************************************************** -#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL2 register. -// -//***************************************************************************** -#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_PP register. -// -//***************************************************************************** -#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present -#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present -#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present -#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present -#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present -#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test Mode Enable -#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable -#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission -#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable -#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable -#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus-Off Status -#define CAN_STS_EWARN 0x00000040 // Warning Status -#define CAN_STS_EPASS 0x00000020 // Error Passive -#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully -#define CAN_STS_TXOK 0x00000008 // Transmitted a Message - // Successfully -#define CAN_STS_LEC_M 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No Error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error -#define CAN_STS_LEC_FORM 0x00000002 // Format Error -#define CAN_STS_LEC_ACK 0x00000003 // ACK Error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error -#define CAN_STS_LEC_CRC 0x00000006 // CRC Error -#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Received Error Passive -#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter -#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter -#define CAN_ERR_REC_S 8 -#define CAN_ERR_TEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point -#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point -#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width -#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler -#define CAN_BIT_TSEG2_S 12 -#define CAN_BIT_TSEG1_S 8 -#define CAN_BIT_SJW_S 6 -#define CAN_BIT_BRP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // Receive Observation -#define CAN_TST_TX_M 0x00000060 // Transmit Control -#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point -#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low -#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High -#define CAN_TST_LBACK 0x00000010 // Loopback Mode -#define CAN_TST_SILENT 0x00000008 // Silent Mode -#define CAN_TST_BASIC 0x00000004 // Basic Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension -#define CAN_BRPE_BRPE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CRQ register. -// -//***************************************************************************** -#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF1CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CMSK register. -// -//***************************************************************************** -#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. -// -//***************************************************************************** -#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF1MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. -// -//***************************************************************************** -#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF1MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. -// -//***************************************************************************** -#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF1ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. -// -//***************************************************************************** -#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF1ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MCTL register. -// -//***************************************************************************** -#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF1MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA1 register. -// -//***************************************************************************** -#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA2 register. -// -//***************************************************************************** -#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB1 register. -// -//***************************************************************************** -#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB2 register. -// -//***************************************************************************** -#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CRQ register. -// -//***************************************************************************** -#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF2CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CMSK register. -// -//***************************************************************************** -#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. -// -//***************************************************************************** -#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF2MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. -// -//***************************************************************************** -#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF2MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. -// -//***************************************************************************** -#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF2ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. -// -//***************************************************************************** -#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF2ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MCTL register. -// -//***************************************************************************** -#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF2MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA1 register. -// -//***************************************************************************** -#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA2 register. -// -//***************************************************************************** -#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB1 register. -// -//***************************************************************************** -#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB2 register. -// -//***************************************************************************** -#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ1_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ2_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA1_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA2_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1INT register. -// -//***************************************************************************** -#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG1INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2INT register. -// -//***************************************************************************** -#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG2INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1VAL register. -// -//***************************************************************************** -#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG1VAL_MSGVAL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2VAL register. -// -//***************************************************************************** -#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG2VAL_MSGVAL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FADDR register. -// -//***************************************************************************** -#define USB_FADDR_M 0x0000007F // Function Address -#define USB_FADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_POWER register. -// -//***************************************************************************** -#define USB_POWER_ISOUP 0x00000080 // Isochronous Update -#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect -#define USB_POWER_HSENAB 0x00000020 // High Speed Enable -#define USB_POWER_HSMODE 0x00000010 // High Speed Enable -#define USB_POWER_RESET 0x00000008 // RESET Signaling -#define USB_POWER_RESUME 0x00000004 // RESUME Signaling -#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode -#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIS register. -// -//***************************************************************************** -#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt -#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt -#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt -#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt -#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt -#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt -#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt -#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIS register. -// -//***************************************************************************** -#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt -#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt -#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt -#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt -#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt -#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt -#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIE register. -// -//***************************************************************************** -#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable -#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable -#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable -#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable -#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable -#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable -#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable -#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIE register. -// -//***************************************************************************** -#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable -#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable -#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable -#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable -#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable -#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable -#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IS register. -// -//***************************************************************************** -#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) -#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) -#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) -#define USB_IS_CONN 0x00000010 // Session Connect -#define USB_IS_SOF 0x00000008 // Start of Frame -#define USB_IS_BABBLE 0x00000004 // Babble Detected -#define USB_IS_RESET 0x00000004 // RESET Signaling Detected -#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected -#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IE register. -// -//***************************************************************************** -#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG - // only) -#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG - // only) -#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt -#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt -#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt -#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt -#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt -#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt -#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FRAME register. -// -//***************************************************************************** -#define USB_FRAME_M 0x000007FF // Frame Number -#define USB_FRAME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPIDX register. -// -//***************************************************************************** -#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index -#define USB_EPIDX_EPIDX_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TEST register. -// -//***************************************************************************** -#define USB_TEST_FORCEH 0x00000080 // Force Host Mode -#define USB_TEST_FIFOACC 0x00000040 // FIFO Access -#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode -#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode -#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable -#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable -#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable -#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO0 register. -// -//***************************************************************************** -#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO0_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO1 register. -// -//***************************************************************************** -#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO1_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO2 register. -// -//***************************************************************************** -#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO2_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO3 register. -// -//***************************************************************************** -#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO3_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO4 register. -// -//***************************************************************************** -#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO4_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO5 register. -// -//***************************************************************************** -#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO5_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO6 register. -// -//***************************************************************************** -#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO6_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO7 register. -// -//***************************************************************************** -#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO7_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DEVCTL register. -// -//***************************************************************************** -#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) -#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected -#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected -#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) -#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd -#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid -#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid -#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid -#define USB_DEVCTL_HOST 0x00000004 // Host Mode -#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) -#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CCONF register. -// -//***************************************************************************** -#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable -#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. -// -//***************************************************************************** -#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. -// -//***************************************************************************** -#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFIFOADD -// register. -// -//***************************************************************************** -#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address -#define USB_TXFIFOADD_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFIFOADD -// register. -// -//***************************************************************************** -#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address -#define USB_RXFIFOADD_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL -// register. -// -//***************************************************************************** -#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ - 0x00000002 // Use External VBUS Indicator -#define USB_ULPIVBUSCTL_USEEXTVBUS \ - 0x00000001 // Use External VBUS - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGDATA -// register. -// -//***************************************************************************** -#define USB_ULPIREGDATA_REGDATA_M \ - 0x000000FF // Register Data -#define USB_ULPIREGDATA_REGDATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGADDR -// register. -// -//***************************************************************************** -#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address -#define USB_ULPIREGADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGCTL -// register. -// -//***************************************************************************** -#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control -#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete -#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPINFO register. -// -//***************************************************************************** -#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints -#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints -#define USB_EPINFO_RXEP_S 4 -#define USB_EPINFO_TXEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RAMINFO register. -// -//***************************************************************************** -#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels -#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width -#define USB_RAMINFO_DMACHAN_S 4 -#define USB_RAMINFO_RAMBITS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CONTIM register. -// -//***************************************************************************** -#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait -#define USB_CONTIM_WTID_M 0x0000000F // Wait ID -#define USB_CONTIM_WTCON_S 4 -#define USB_CONTIM_WTID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VPLEN register. -// -//***************************************************************************** -#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length -#define USB_VPLEN_VPLEN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HSEOF register. -// -//***************************************************************************** -#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap -#define USB_HSEOF_HSEOFG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FSEOF register. -// -//***************************************************************************** -#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap -#define USB_FSEOF_FSEOFG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LSEOF register. -// -//***************************************************************************** -#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap -#define USB_LSEOF_LSEOFG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR0 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT0 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT0_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT7_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT7_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CSRL0 register. -// -//***************************************************************************** -#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout -#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear -#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet -#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear -#define USB_CSRL0_REQPKT 0x00000020 // Request Packet -#define USB_CSRL0_STALL 0x00000020 // Send Stall -#define USB_CSRL0_SETEND 0x00000010 // Setup End -#define USB_CSRL0_ERROR 0x00000010 // Error -#define USB_CSRL0_DATAEND 0x00000008 // Data End -#define USB_CSRL0_SETUP 0x00000008 // Setup Packet -#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled -#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready -#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CSRH0 register. -// -//***************************************************************************** -#define USB_CSRH0_DISPING 0x00000008 // PING Disable -#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_CSRH0_DT 0x00000002 // Data Toggle -#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_COUNT0 register. -// -//***************************************************************************** -#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count -#define USB_COUNT0_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TYPE0 register. -// -//***************************************************************************** -#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed -#define USB_TYPE0_SPEED_HIGH 0x00000040 // High -#define USB_TYPE0_SPEED_FULL 0x00000080 // Full -#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_NAKLMT register. -// -//***************************************************************************** -#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit -#define USB_NAKLMT_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP1 register. -// -//***************************************************************************** -#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP1_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL1 register. -// -//***************************************************************************** -#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL1_STALL 0x00000010 // Send STALL -#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL1_ERROR 0x00000004 // Error -#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH1 register. -// -//***************************************************************************** -#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH1_MODE 0x00000020 // Mode -#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH1_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP1 register. -// -//***************************************************************************** -#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP1_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL1 register. -// -//***************************************************************************** -#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL1_STALL 0x00000020 // Send STALL -#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL1_OVER 0x00000004 // Overrun -#define USB_RXCSRL1_ERROR 0x00000004 // Error -#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH1 register. -// -//***************************************************************************** -#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH1_DT 0x00000002 // Data Toggle -#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. -// -//***************************************************************************** -#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT1_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE1 register. -// -//***************************************************************************** -#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE1_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL1 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL1_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL1_TXPOLL_S \ - 0 -#define USB_TXINTERVAL1_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE1 register. -// -//***************************************************************************** -#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE1_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL1 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL1_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL1_TXPOLL_S \ - 0 -#define USB_RXINTERVAL1_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP2 register. -// -//***************************************************************************** -#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL2 register. -// -//***************************************************************************** -#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL2_STALL 0x00000010 // Send STALL -#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL2_ERROR 0x00000004 // Error -#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH2 register. -// -//***************************************************************************** -#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH2_MODE 0x00000020 // Mode -#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH2_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP2 register. -// -//***************************************************************************** -#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL2 register. -// -//***************************************************************************** -#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL2_STALL 0x00000020 // Send STALL -#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL2_ERROR 0x00000004 // Error -#define USB_RXCSRL2_OVER 0x00000004 // Overrun -#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH2 register. -// -//***************************************************************************** -#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH2_DT 0x00000002 // Data Toggle -#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. -// -//***************************************************************************** -#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT2_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE2 register. -// -//***************************************************************************** -#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL2_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL2_NAKLMT_S \ - 0 -#define USB_TXINTERVAL2_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE2 register. -// -//***************************************************************************** -#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL2_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL2_TXPOLL_S \ - 0 -#define USB_RXINTERVAL2_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP3 register. -// -//***************************************************************************** -#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL3 register. -// -//***************************************************************************** -#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL3_STALL 0x00000010 // Send STALL -#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL3_ERROR 0x00000004 // Error -#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH3 register. -// -//***************************************************************************** -#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH3_MODE 0x00000020 // Mode -#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH3_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP3 register. -// -//***************************************************************************** -#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL3 register. -// -//***************************************************************************** -#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL3_STALL 0x00000020 // Send STALL -#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL3_ERROR 0x00000004 // Error -#define USB_RXCSRL3_OVER 0x00000004 // Overrun -#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH3 register. -// -//***************************************************************************** -#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH3_DT 0x00000002 // Data Toggle -#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. -// -//***************************************************************************** -#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT3_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE3 register. -// -//***************************************************************************** -#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL3_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL3_TXPOLL_S \ - 0 -#define USB_TXINTERVAL3_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE3 register. -// -//***************************************************************************** -#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL3_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL3_TXPOLL_S \ - 0 -#define USB_RXINTERVAL3_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP4 register. -// -//***************************************************************************** -#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL4 register. -// -//***************************************************************************** -#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL4_STALL 0x00000010 // Send STALL -#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL4_ERROR 0x00000004 // Error -#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH4 register. -// -//***************************************************************************** -#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH4_MODE 0x00000020 // Mode -#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH4_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP4 register. -// -//***************************************************************************** -#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL4 register. -// -//***************************************************************************** -#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL4_STALL 0x00000020 // Send STALL -#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL4_OVER 0x00000004 // Overrun -#define USB_RXCSRL4_ERROR 0x00000004 // Error -#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH4 register. -// -//***************************************************************************** -#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH4_DT 0x00000002 // Data Toggle -#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. -// -//***************************************************************************** -#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE4 register. -// -//***************************************************************************** -#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL4_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL4_NAKLMT_S \ - 0 -#define USB_TXINTERVAL4_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE4 register. -// -//***************************************************************************** -#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL4_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL4_NAKLMT_S \ - 0 -#define USB_RXINTERVAL4_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP5 register. -// -//***************************************************************************** -#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL5 register. -// -//***************************************************************************** -#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL5_STALL 0x00000010 // Send STALL -#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL5_ERROR 0x00000004 // Error -#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH5 register. -// -//***************************************************************************** -#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH5_MODE 0x00000020 // Mode -#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH5_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP5 register. -// -//***************************************************************************** -#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL5 register. -// -//***************************************************************************** -#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL5_STALL 0x00000020 // Send STALL -#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL5_ERROR 0x00000004 // Error -#define USB_RXCSRL5_OVER 0x00000004 // Overrun -#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH5 register. -// -//***************************************************************************** -#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH5_DT 0x00000002 // Data Toggle -#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. -// -//***************************************************************************** -#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT5_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE5 register. -// -//***************************************************************************** -#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE5_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL5 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL5_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL5_NAKLMT_S \ - 0 -#define USB_TXINTERVAL5_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE5 register. -// -//***************************************************************************** -#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE5_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL5 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL5_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL5_TXPOLL_S \ - 0 -#define USB_RXINTERVAL5_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP6 register. -// -//***************************************************************************** -#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL6 register. -// -//***************************************************************************** -#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL6_STALL 0x00000010 // Send STALL -#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL6_ERROR 0x00000004 // Error -#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH6 register. -// -//***************************************************************************** -#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH6_MODE 0x00000020 // Mode -#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH6_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP6 register. -// -//***************************************************************************** -#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL6 register. -// -//***************************************************************************** -#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL6_STALL 0x00000020 // Send STALL -#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL6_ERROR 0x00000004 // Error -#define USB_RXCSRL6_OVER 0x00000004 // Overrun -#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH6 register. -// -//***************************************************************************** -#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH6_DT 0x00000002 // Data Toggle -#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. -// -//***************************************************************************** -#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE6 register. -// -//***************************************************************************** -#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL6_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL6_TXPOLL_S \ - 0 -#define USB_TXINTERVAL6_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE6 register. -// -//***************************************************************************** -#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL6_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL6_NAKLMT_S \ - 0 -#define USB_RXINTERVAL6_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP7 register. -// -//***************************************************************************** -#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL7 register. -// -//***************************************************************************** -#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL7_STALL 0x00000010 // Send STALL -#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL7_ERROR 0x00000004 // Error -#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH7 register. -// -//***************************************************************************** -#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH7_MODE 0x00000020 // Mode -#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH7_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP7 register. -// -//***************************************************************************** -#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL7 register. -// -//***************************************************************************** -#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL7_STALL 0x00000020 // Send STALL -#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL7_ERROR 0x00000004 // Error -#define USB_RXCSRL7_OVER 0x00000004 // Overrun -#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH7 register. -// -//***************************************************************************** -#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH7_DT 0x00000002 // Data Toggle -#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. -// -//***************************************************************************** -#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE7 register. -// -//***************************************************************************** -#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL7_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL7_NAKLMT_S \ - 0 -#define USB_TXINTERVAL7_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE7 register. -// -//***************************************************************************** -#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL7_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL7_NAKLMT_S \ - 0 -#define USB_RXINTERVAL7_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAINTR register. -// -//***************************************************************************** -#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt -#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt -#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt -#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt -#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt -#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt -#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt -#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL0 register. -// -//***************************************************************************** -#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL0_DIR 0x00000002 // DMA Direction -#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL0_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR0 register. -// -//***************************************************************************** -#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR0_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT0 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT0_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL1 register. -// -//***************************************************************************** -#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL1_DIR 0x00000002 // DMA Direction -#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL1_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR1 register. -// -//***************************************************************************** -#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR1_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT1 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT1_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL2 register. -// -//***************************************************************************** -#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL2_DIR 0x00000002 // DMA Direction -#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL2_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR2 register. -// -//***************************************************************************** -#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR2_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT2 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT2_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL3 register. -// -//***************************************************************************** -#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL3_DIR 0x00000002 // DMA Direction -#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL3_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR3 register. -// -//***************************************************************************** -#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR3_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT3 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT3_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL4 register. -// -//***************************************************************************** -#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL4_DIR 0x00000002 // DMA Direction -#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL4_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR4 register. -// -//***************************************************************************** -#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR4_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT4 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT4_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL5 register. -// -//***************************************************************************** -#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL5_DIR 0x00000002 // DMA Direction -#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL5_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR5 register. -// -//***************************************************************************** -#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR5_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT5 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT5_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL6 register. -// -//***************************************************************************** -#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL6_DIR 0x00000002 // DMA Direction -#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL6_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR6 register. -// -//***************************************************************************** -#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR6_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT6 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT6_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL7 register. -// -//***************************************************************************** -#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL7_DIR 0x00000002 // DMA Direction -#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL7_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR7 register. -// -//***************************************************************************** -#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR7_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT7 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT7_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT1_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT2_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT3_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT5_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer - // Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer - // Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CTO register. -// -//***************************************************************************** -#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value -#define USB_CTO_CCTV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HHSRTN register. -// -//***************************************************************************** -#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating - // Delay -#define USB_HHSRTN_HHSRTN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HSBT register. -// -//***************************************************************************** -#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder -#define USB_HSBT_HSBT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMATTR register. -// -//***************************************************************************** -#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint -#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake -#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration -#define USB_LPMATTR_LS_M 0x0000000F // Link State -#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) -#define USB_LPMATTR_ENDPT_S 12 -#define USB_LPMATTR_HIRD_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMCNTRL register. -// -//***************************************************************************** -#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK -#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable -#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions - // are not supported. In this case, - // the USB does not respond to LPM - // transactions and LPM - // transactions cause a timeout -#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but - // extended transactions are - // supported. In this case, the USB - // does respond to an LPM - // transaction with a STALL -#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended - // transactions. In this case, the - // USB responds with a NYET or an - // ACK as determined by the value - // of TXLPM and other conditions -#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume -#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMIM register. -// -//***************************************************************************** -#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask -#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask -#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask -#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask -#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask -#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMRIS register. -// -//***************************************************************************** -#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status -#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status -#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status -#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status -#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status -#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMFADDR register. -// -//***************************************************************************** -#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address -#define USB_LPMFADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPC register. -// -//***************************************************************************** -#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action -#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged -#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate -#define USB_EPC_PFLTACT_LOW 0x00000200 // Low -#define USB_EPC_PFLTACT_HIGH 0x00000300 // High -#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable -#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense -#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable -#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable -#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable - // Configuration -#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low -#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High -#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low - // (OTG only) -#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High - // (OTG only) - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCRIS register. -// -//***************************************************************************** -#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCIM register. -// -//***************************************************************************** -#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCISC register. -// -//***************************************************************************** -#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRRIS register. -// -//***************************************************************************** -#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRIM register. -// -//***************************************************************************** -#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRISC register. -// -//***************************************************************************** -#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_GPCS register. -// -//***************************************************************************** -#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode -#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin -#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low -#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high -#define USB_GPCS_DEVMOD_HOSTVBUS \ - 0x00000004 // Use USB0VBUS and force USB0ID - // low -#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID - // high - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDC register. -// -//***************************************************************************** -#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCRIS register. -// -//***************************************************************************** -#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCIM register. -// -//***************************************************************************** -#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCISC register. -// -//***************************************************************************** -#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_PP register. -// -//***************************************************************************** -#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count -#define USB_PP_USB_M 0x000000C0 // USB Capability -#define USB_PP_USB_DEVICE 0x00000040 // DEVICE -#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST -#define USB_PP_USB_OTG 0x000000C0 // OTG -#define USB_PP_ULPI 0x00000020 // ULPI Present -#define USB_PP_PHY 0x00000010 // PHY Present -#define USB_PP_TYPE_M 0x0000000F // Controller Type -#define USB_PP_TYPE_0 0x00000000 // The first-generation USB - // controller -#define USB_PP_TYPE_1 0x00000001 // Second-generation USB - // controller.The controller - // implemented in post Icestorm - // devices that use the 3.0 version - // of the Mentor controller -#define USB_PP_ECNT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_PC register. -// -//***************************************************************************** -#define USB_PC_ULPIEN 0x00010000 // ULPI Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CC register. -// -//***************************************************************************** -#define USB_CC_CLKEN 0x00000200 // USB Clock Enable -#define USB_CC_CSD 0x00000100 // Clock Source/Direction -#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor -#define USB_CC_CLKDIV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EESIZE register. -// -//***************************************************************************** -#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks -#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words -#define EEPROM_EESIZE_BLKCNT_S 16 -#define EEPROM_EESIZE_WORDCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEBLOCK register. -// -//***************************************************************************** -#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block -#define EEPROM_EEBLOCK_BLOCK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEOFFSET -// register. -// -//***************************************************************************** -#define EEPROM_EEOFFSET_OFFSET_M \ - 0x0000000F // Current Address Offset -#define EEPROM_EEOFFSET_OFFSET_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EERDWR register. -// -//***************************************************************************** -#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data -#define EEPROM_EERDWR_VALUE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EERDWRINC -// register. -// -//***************************************************************************** -#define EEPROM_EERDWRINC_VALUE_M \ - 0xFFFFFFFF // EEPROM Read or Write Data with - // Increment -#define EEPROM_EERDWRINC_VALUE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEDONE register. -// -//***************************************************************************** -#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy -#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission -#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy -#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase -#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EESUPP register. -// -//***************************************************************************** -#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried -#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEUNLOCK -// register. -// -//***************************************************************************** -#define EEPROM_EEUNLOCK_UNLOCK_M \ - 0xFFFFFFFF // EEPROM Unlock - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPROT register. -// -//***************************************************************************** -#define EEPROM_EEPROT_ACC 0x00000008 // Access Control -#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control -#define EEPROM_EEPROT_PROT_RWNPW \ - 0x00000000 // This setting is the default. If - // there is no password, the block - // is not protected and is readable - // and writable -#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the - // block is readable or writable - // only when unlocked -#define EEPROM_EEPROT_PROT_RONPW \ - 0x00000002 // If there is no password, the - // block is readable, not writable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS0 register. -// -//***************************************************************************** -#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS0_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS1 register. -// -//***************************************************************************** -#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS1_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS2 register. -// -//***************************************************************************** -#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS2_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEINT register. -// -//***************************************************************************** -#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE0 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE0_HN_M 0xFFFFFFFE // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE1 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE1_HN_M 0xFFFFFFFF // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE2 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE2_HN_M 0xFFFFFFFF // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEDBGME register. -// -//***************************************************************************** -#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key -#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase -#define EEPROM_EEDBGME_KEY_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_PP register. -// -//***************************************************************************** -#define EEPROM_PP_SIZE_M 0x0000FFFF // EEPROM Size -#define EEPROM_PP_SIZE_64 0x00000000 // 64 bytes of EEPROM -#define EEPROM_PP_SIZE_128 0x00000001 // 128 bytes of EEPROM -#define EEPROM_PP_SIZE_256 0x00000003 // 256 bytes of EEPROM -#define EEPROM_PP_SIZE_512 0x00000007 // 512 bytes of EEPROM -#define EEPROM_PP_SIZE_1K 0x0000000F // 1 KB of EEPROM -#define EEPROM_PP_SIZE_2K 0x0000001F // 2 KB of EEPROM -#define EEPROM_PP_SIZE_3K 0x0000003F // 3 KB of EEPROM -#define EEPROM_PP_SIZE_4K 0x0000007F // 4 KB of EEPROM -#define EEPROM_PP_SIZE_5K 0x000000FF // 5 KB of EEPROM -#define EEPROM_PP_SIZE_6K 0x000001FF // 6 KB of EEPROM - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_CFG register. -// -//***************************************************************************** -#define EPI_CFG_INTDIV 0x00000100 // Integer Clock Divider Enable -#define EPI_CFG_BLKEN 0x00000010 // Block Enable -#define EPI_CFG_MODE_M 0x0000000F // Mode Select -#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose -#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM -#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8) -#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_BAUD register. -// -//***************************************************************************** -#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1 -#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0 -#define EPI_BAUD_COUNT1_S 16 -#define EPI_BAUD_COUNT0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_BAUD2 register. -// -//***************************************************************************** -#define EPI_BAUD2_COUNT1_M 0xFFFF0000 // CS3n Baud Rate Counter 1 -#define EPI_BAUD2_COUNT0_M 0x0000FFFF // CS2n Baud Rate Counter 0 -#define EPI_BAUD2_COUNT1_S 16 -#define EPI_BAUD2_COUNT0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG register. -// -//***************************************************************************** -#define EPI_HB16CFG_CLKGATE 0x80000000 // Clock Gated -#define EPI_HB16CFG_CLKGATEI 0x40000000 // Clock Gated Idle -#define EPI_HB16CFG_CLKINV 0x20000000 // Invert Output Clock Enable -#define EPI_HB16CFG_RDYEN 0x10000000 // Input Ready Enable -#define EPI_HB16CFG_IRDYINV 0x08000000 // Input Ready Invert -#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable -#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable -#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity -#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity -#define EPI_HB16CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity -#define EPI_HB16CFG_WRCRE 0x00040000 // PSRAM Configuration Register - // Write -#define EPI_HB16CFG_RDCRE 0x00020000 // PSRAM Configuration Register - // Read -#define EPI_HB16CFG_BURST 0x00010000 // Burst Mode -#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait -#define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States -#define EPI_HB16CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States -#define EPI_HB16CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration -#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode -#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0] -#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0] -#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0] -#define EPI_HB16CFG_MAXWAIT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_GPCFG register. -// -//***************************************************************************** -#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin -#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated -#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame -#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count -#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes -#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size -#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address -#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide -#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size - // cannot be used with 24-bit data -#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size - // cannot be used with data sizes - // other than 8 -#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus -#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7) -#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15) -#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23) -#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31) -#define EPI_GPCFG_FRMCNT_S 22 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_SDRAMCFG register. -// -//***************************************************************************** -#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range -#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz -#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz -#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz -#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter -#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode -#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM -#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB) -#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB) -#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB) -#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB) -#define EPI_SDRAMCFG_RFSH_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG register. -// -//***************************************************************************** -#define EPI_HB8CFG_CLKGATE 0x80000000 // Clock Gated -#define EPI_HB8CFG_CLKGATEI 0x40000000 // Clock Gated when Idle -#define EPI_HB8CFG_CLKINV 0x20000000 // Invert Output Clock Enable -#define EPI_HB8CFG_RDYEN 0x10000000 // Input Ready Enable -#define EPI_HB8CFG_IRDYINV 0x08000000 // Input Ready Invert -#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable -#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable -#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity -#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity -#define EPI_HB8CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity -#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait -#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States -#define EPI_HB8CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States -#define EPI_HB8CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode -#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0] -#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0] -#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0] -#define EPI_HB8CFG_MAXWAIT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG2 register. -// -//***************************************************************************** -#define EPI_HB8CFG2_CSCFGEXT 0x08000000 // Chip Select Extended - // Configuration -#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and - // Multiple Sub-Mode Configuration - // enable -#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration -#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration -#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration -#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration -#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration -#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity -#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity -#define EPI_HB8CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity -#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States -#define EPI_HB8CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States -#define EPI_HB8CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode -#define EPI_HB8CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG2_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG2 register. -// -//***************************************************************************** -#define EPI_HB16CFG2_CSCFGEXT 0x08000000 // Chip Select Extended - // Configuration -#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and - // Multiple Sub-Mode Configuration - // enable -#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration -#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration -#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration -#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration -#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration -#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity -#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity -#define EPI_HB16CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity -#define EPI_HB16CFG2_WRCRE 0x00040000 // CS1n PSRAM Configuration - // Register Write -#define EPI_HB16CFG2_RDCRE 0x00020000 // CS1n PSRAM Configuration - // Register Read -#define EPI_HB16CFG2_BURST 0x00010000 // CS1n Burst Mode -#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States -#define EPI_HB16CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States -#define EPI_HB16CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode -#define EPI_HB16CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG2_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_ADDRMAP register. -// -//***************************************************************************** -#define EPI_ADDRMAP_ECSZ_M 0x00000C00 // External Code Size -#define EPI_ADDRMAP_ECSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_ECSZ_64KB 0x00000400 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_ECSZ_16MB 0x00000800 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_ECSZ_256MB 0x00000C00 // 256MB; lower address range: - // 0x000.0000 to 0x0FFF.FFFF -#define EPI_ADDRMAP_ECADR_M 0x00000300 // External Code Address -#define EPI_ADDRMAP_ECADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_ECADR_1000 0x00000100 // At 0x1000.0000 -#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size -#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range: - // 0x000.0000 to 0xFFF.FFFF -#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address -#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000 -#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000 -#define EPI_ADDRMAP_EPADR_HBQS 0x00000030 // Only to be used with Host Bus - // quad chip select. In quad chip - // select mode, CS2n maps to - // 0xA000.0000 and CS3n maps to - // 0xC000.0000 -#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size -#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range: - // 0x000.0000 to 0xFFF.FFFF -#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address -#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000 -#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000 -#define EPI_ADDRMAP_ERADR_HBQS 0x00000003 // Only to be used with Host Bus - // quad chip select. In quad chip - // select mode, CS0n maps to - // 0x6000.0000 and CS1n maps to - // 0x8000.0000 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RSIZE0 register. -// -//***************************************************************************** -#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size -#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits) -#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits) -#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RADDR0 register. -// -//***************************************************************************** -#define EPI_RADDR0_ADDR_M 0xFFFFFFFF // Current Address -#define EPI_RADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RPSTD0 register. -// -//***************************************************************************** -#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count -#define EPI_RPSTD0_POSTCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RSIZE1 register. -// -//***************************************************************************** -#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size -#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits) -#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits) -#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RADDR1 register. -// -//***************************************************************************** -#define EPI_RADDR1_ADDR_M 0xFFFFFFFF // Current Address -#define EPI_RADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RPSTD1 register. -// -//***************************************************************************** -#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count -#define EPI_RPSTD1_POSTCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_STAT register. -// -//***************************************************************************** -#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full -#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty -#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence -#define EPI_STAT_WBUSY 0x00000020 // Write Busy -#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy -#define EPI_STAT_ACTIVE 0x00000001 // Register Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RFIFOCNT register. -// -//***************************************************************************** -#define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count -#define EPI_RFIFOCNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO0 -// register. -// -//***************************************************************************** -#define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO1 -// register. -// -//***************************************************************************** -#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO2 -// register. -// -//***************************************************************************** -#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO3 -// register. -// -//***************************************************************************** -#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO4 -// register. -// -//***************************************************************************** -#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO4_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO5 -// register. -// -//***************************************************************************** -#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO5_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO6 -// register. -// -//***************************************************************************** -#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO6_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO7 -// register. -// -//***************************************************************************** -#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO7_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_FIFOLVL register. -// -//***************************************************************************** -#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error -#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error -#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO -#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Interrupt is triggered while - // WRFIFO is empty. -#define EPI_FIFOLVL_WRFIFO_2 0x00000020 // Interrupt is triggered until - // there are only two slots - // available. Thus, trigger is - // deasserted when there are two - // WRFIFO entries present. This - // configuration is optimized for - // bursts of 2 -#define EPI_FIFOLVL_WRFIFO_1 0x00000030 // Interrupt is triggered until - // there is one WRFIFO entry - // available. This configuration - // expects only single writes -#define EPI_FIFOLVL_WRFIFO_NFULL \ - 0x00000040 // Trigger interrupt when WRFIFO is - // not full, meaning trigger will - // continue to assert until there - // are four entries in the WRFIFO -#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO -#define EPI_FIFOLVL_RDFIFO_1 0x00000001 // Trigger when there are 1 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_2 0x00000002 // Trigger when there are 2 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_4 0x00000003 // Trigger when there are 4 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_6 0x00000004 // Trigger when there are 6 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_7 0x00000005 // Trigger when there are 7 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_8 0x00000006 // Trigger when there are 8 entries - // in the NBRFIFO - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_WFIFOCNT register. -// -//***************************************************************************** -#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions -#define EPI_WFIFOCNT_WTAV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_DMATXCNT register. -// -//***************************************************************************** -#define EPI_DMATXCNT_TXCNT_M 0x0000FFFF // DMA Count -#define EPI_DMATXCNT_TXCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_IM register. -// -//***************************************************************************** -#define EPI_IM_DMAWRIM 0x00000010 // Write uDMA Interrupt Mask -#define EPI_IM_DMARDIM 0x00000008 // Read uDMA Interrupt Mask -#define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask -#define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask -#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RIS register. -// -//***************************************************************************** -#define EPI_RIS_DMAWRRIS 0x00000010 // Write uDMA Raw Interrupt Status -#define EPI_RIS_DMARDRIS 0x00000008 // Read uDMA Raw Interrupt Status -#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status -#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status -#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_MIS register. -// -//***************************************************************************** -#define EPI_MIS_DMAWRMIS 0x00000010 // Write uDMA Masked Interrupt - // Status -#define EPI_MIS_DMARDMIS 0x00000008 // Read uDMA Masked Interrupt - // Status -#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status -#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status -#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_EISC register. -// -//***************************************************************************** -#define EPI_EISC_DMAWRIC 0x00000010 // Write uDMA Interrupt Clear -#define EPI_EISC_DMARDIC 0x00000008 // Read uDMA Interrupt Clear -#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error -#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error -#define EPI_EISC_TOUT 0x00000001 // Timeout Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG3 register. -// -//***************************************************************************** -#define EPI_HB8CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity -#define EPI_HB8CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB8CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity -#define EPI_HB8CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States -#define EPI_HB8CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG3_RDWS_M 0x00000030 // CS2n Read Wait States -#define EPI_HB8CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode -#define EPI_HB8CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG3_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG3 register. -// -//***************************************************************************** -#define EPI_HB16CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity -#define EPI_HB16CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB16CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity -#define EPI_HB16CFG3_WRCRE 0x00040000 // CS2n PSRAM Configuration - // Register Write -#define EPI_HB16CFG3_RDCRE 0x00020000 // CS2n PSRAM Configuration - // Register Read -#define EPI_HB16CFG3_BURST 0x00010000 // CS2n Burst Mode -#define EPI_HB16CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States -#define EPI_HB16CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG3_RDWS_M 0x00000030 // CS2n Read Wait States -#define EPI_HB16CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode -#define EPI_HB16CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG3_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG4 register. -// -//***************************************************************************** -#define EPI_HB16CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity -#define EPI_HB16CFG4_RDHIGH 0x00100000 // CS3n READ Strobe Polarity -#define EPI_HB16CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity -#define EPI_HB16CFG4_WRCRE 0x00040000 // CS3n PSRAM Configuration - // Register Write -#define EPI_HB16CFG4_RDCRE 0x00020000 // CS3n PSRAM Configuration - // Register Read -#define EPI_HB16CFG4_BURST 0x00010000 // CS3n Burst Mode -#define EPI_HB16CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States -#define EPI_HB16CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG4_RDWS_M 0x00000030 // CS3n Read Wait States -#define EPI_HB16CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode -#define EPI_HB16CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG4_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG4 register. -// -//***************************************************************************** -#define EPI_HB8CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity -#define EPI_HB8CFG4_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB8CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity -#define EPI_HB8CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States -#define EPI_HB8CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG4_RDWS_M 0x00000030 // CS3n Read Wait States -#define EPI_HB8CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode -#define EPI_HB8CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG4_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME register. -// -//***************************************************************************** -#define EPI_HB8TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay -#define EPI_HB8TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture - // Width -#define EPI_HB8TIME_WRWSM 0x00000010 // Write Wait State Minus One -#define EPI_HB8TIME_RDWSM 0x00000001 // Read Wait State Minus One -#define EPI_HB8TIME_IRDYDLY_S 24 -#define EPI_HB8TIME_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME register. -// -//***************************************************************************** -#define EPI_HB16TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay -#define EPI_HB16TIME_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture - // Width -#define EPI_HB16TIME_WRWSM 0x00000010 // Write Wait State Minus One -#define EPI_HB16TIME_RDWSM 0x00000001 // Read Wait State Minus One -#define EPI_HB16TIME_IRDYDLY_S 24 -#define EPI_HB16TIME_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME2 register. -// -//***************************************************************************** -#define EPI_HB8TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay -#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000 // CS1n Inter-transfer Capture - // Width -#define EPI_HB8TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One -#define EPI_HB8TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One -#define EPI_HB8TIME2_IRDYDLY_S 24 -#define EPI_HB8TIME2_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME2 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay -#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME2_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME2_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME2_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME2_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME2_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME2_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME2_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME2_CAPWIDTH_M \ - 0x00003000 // CS1n Inter-transfer Capture - // Width -#define EPI_HB16TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One -#define EPI_HB16TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One -#define EPI_HB16TIME2_IRDYDLY_S 24 -#define EPI_HB16TIME2_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME3 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay -#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME3_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME3_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME3_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME3_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME3_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME3_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME3_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME3_CAPWIDTH_M \ - 0x00003000 // CS2n Inter-transfer Capture - // Width -#define EPI_HB16TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One -#define EPI_HB16TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One -#define EPI_HB16TIME3_IRDYDLY_S 24 -#define EPI_HB16TIME3_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME3 register. -// -//***************************************************************************** -#define EPI_HB8TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay -#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000 // CS2n Inter-transfer Capture - // Width -#define EPI_HB8TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One -#define EPI_HB8TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One -#define EPI_HB8TIME3_IRDYDLY_S 24 -#define EPI_HB8TIME3_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME4 register. -// -//***************************************************************************** -#define EPI_HB8TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay -#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000 // CS3n Inter-transfer Capture - // Width -#define EPI_HB8TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One -#define EPI_HB8TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One -#define EPI_HB8TIME4_IRDYDLY_S 24 -#define EPI_HB8TIME4_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME4 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay -#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME4_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME4_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME4_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME4_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME4_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME4_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME4_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME4_CAPWIDTH_M \ - 0x00003000 // CS3n Inter-transfer Capture - // Width -#define EPI_HB16TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One -#define EPI_HB16TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One -#define EPI_HB16TIME4_IRDYDLY_S 24 -#define EPI_HB16TIME4_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HBPSRAM register. -// -//***************************************************************************** -#define EPI_HBPSRAM_CR_M 0x001FFFFF // PSRAM Config Register -#define EPI_HBPSRAM_CR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_RIS register. -// -//***************************************************************************** -#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception - // Raw Interrupt Status -#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation - // Raw Interrupt Status -#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0 - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal - // Exception Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_IM register. -// -//***************************************************************************** -#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception - // Interrupt Mask -#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow - // Exception Interrupt Mask -#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow - // Exception Interrupt Mask -#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation - // Interrupt Mask -#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0 - // Exception Interrupt Mask -#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal - // Exception Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_MIS register. -// -//***************************************************************************** -#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception - // Masked Interrupt Status -#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation - // Masked Interrupt Status -#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0 - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal - // Exception Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_IC register. -// -//***************************************************************************** -#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception - // Interrupt Clear -#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow - // Exception Interrupt Clear -#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow - // Exception Interrupt Clear -#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation - // Interrupt Clear -#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0 - // Exception Interrupt Clear -#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal - // Exception Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCC register. -// -//***************************************************************************** -#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter -#define HIB_RTCC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCM0 register. -// -//***************************************************************************** -#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 -#define HIB_RTCM0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCLD register. -// -//***************************************************************************** -#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load -#define HIB_RTCLD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CTL register. -// -//***************************************************************************** -#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable -#define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear -#define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select -#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability -#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass -#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery - // Comparator -#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts -#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) -#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts -#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts -#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status -#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery -#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered -#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable -#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable -#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable -#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable -#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request -#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IM register. -// -//***************************************************************************** -#define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask -#define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Mask -#define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask -#define HIB_IM_WC 0x00000010 // External Write Complete/Capable - // Interrupt Mask -#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask -#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt - // Mask -#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RIS register. -// -//***************************************************************************** -#define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status -#define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw - // Interrupt Status -#define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt - // Status -#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw - // Interrupt Status -#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt - // Status -#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw - // Interrupt Status -#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_MIS register. -// -//***************************************************************************** -#define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask -#define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Mask -#define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask -#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked - // Interrupt Status -#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked - // Interrupt Status -#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked - // Interrupt Status -#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IC register. -// -//***************************************************************************** -#define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear -#define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Clear -#define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear -#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt - // Clear -#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear -#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt - // Clear -#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCT register. -// -//***************************************************************************** -#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value -#define HIB_RTCT_TRIM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCSS register. -// -//***************************************************************************** -#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match -#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count -#define HIB_RTCSS_RTCSSM_S 16 -#define HIB_RTCSS_RTCSSC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IO register. -// -//***************************************************************************** -#define HIB_IO_IOWRC 0x80000000 // I/O Write Complete -#define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable -#define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_DATA register. -// -//***************************************************************************** -#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data -#define HIB_DATA_RTD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALCTL register. -// -//***************************************************************************** -#define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode -#define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CAL0 register. -// -//***************************************************************************** -#define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load -#define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CAL0_HR_M 0x001F0000 // Hours -#define HIB_CAL0_MIN_M 0x00003F00 // Minutes -#define HIB_CAL0_SEC_M 0x0000003F // Seconds -#define HIB_CAL0_HR_S 16 -#define HIB_CAL0_MIN_S 8 -#define HIB_CAL0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CAL1 register. -// -//***************************************************************************** -#define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load -#define HIB_CAL1_DOW_M 0x07000000 // Day of Week -#define HIB_CAL1_YEAR_M 0x007F0000 // Year Value -#define HIB_CAL1_MON_M 0x00000F00 // Month -#define HIB_CAL1_DOM_M 0x0000001F // Day of Month -#define HIB_CAL1_DOW_S 24 -#define HIB_CAL1_YEAR_S 16 -#define HIB_CAL1_MON_S 8 -#define HIB_CAL1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALLD0 register. -// -//***************************************************************************** -#define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CALLD0_HR_M 0x001F0000 // Hours -#define HIB_CALLD0_MIN_M 0x00003F00 // Minutes -#define HIB_CALLD0_SEC_M 0x0000003F // Seconds -#define HIB_CALLD0_HR_S 16 -#define HIB_CALLD0_MIN_S 8 -#define HIB_CALLD0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALLD1 register. -// -//***************************************************************************** -#define HIB_CALLD1_DOW_M 0x07000000 // Day of Week -#define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value -#define HIB_CALLD1_MON_M 0x00000F00 // Month -#define HIB_CALLD1_DOM_M 0x0000001F // Day of Month -#define HIB_CALLD1_DOW_S 24 -#define HIB_CALLD1_YEAR_S 16 -#define HIB_CALLD1_MON_S 8 -#define HIB_CALLD1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALM0 register. -// -//***************************************************************************** -#define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CALM0_HR_M 0x001F0000 // Hours -#define HIB_CALM0_MIN_M 0x00003F00 // Minutes -#define HIB_CALM0_SEC_M 0x0000003F // Seconds -#define HIB_CALM0_HR_S 16 -#define HIB_CALM0_MIN_S 8 -#define HIB_CALM0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALM1 register. -// -//***************************************************************************** -#define HIB_CALM1_DOM_M 0x0000001F // Day of Month -#define HIB_CALM1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_LOCK register. -// -//***************************************************************************** -#define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock -#define HIB_LOCK_HIBLOCK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPCTL register. -// -//***************************************************************************** -#define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper - // Event -#define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event -#define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on - // tamper event -#define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB - // memory on tamper event -#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB - // memory on tamper event -#define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper - // event -#define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear -#define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPSTAT register. -// -//***************************************************************************** -#define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status -#define HIB_TPSTAT_STATE_DISABLED \ - 0x00000000 // Tamper disabled -#define HIB_TPSTAT_STATE_CONFIGED \ - 0x00000004 // Tamper configured -#define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred -#define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status -#define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPIO register. -// -//***************************************************************************** -#define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering -#define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level -#define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable -#define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering -#define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level -#define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable -#define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering -#define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level -#define HIB_TPIO_EN1 0x00000100 // TMPR1Enable -#define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering -#define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level -#define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG0 register. -// -//***************************************************************************** -#define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG0_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG1 register. -// -//***************************************************************************** -#define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG2 register. -// -//***************************************************************************** -#define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG2_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG3 register. -// -//***************************************************************************** -#define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG4 register. -// -//***************************************************************************** -#define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG4_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG5 register. -// -//***************************************************************************** -#define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG6 register. -// -//***************************************************************************** -#define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG6_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG7 register. -// -//***************************************************************************** -#define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_PP register. -// -//***************************************************************************** -#define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence -#define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CC register. -// -//***************************************************************************** -#define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMA register. -// -//***************************************************************************** -#define FLASH_FMA_OFFSET_M 0x000FFFFF // Address Offset -#define FLASH_FMA_OFFSET_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMD register. -// -//***************************************************************************** -#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value -#define FLASH_FMD_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit Register Value -#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory -#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory -#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw - // Interrupt Status -#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt - // Status -#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt - // Status -#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt - // Status -#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status -#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status -#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask -#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask -#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask -#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask -#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask -#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask -#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCMISC register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt - // Status and Clear -#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and - // Clear -#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt - // Status and Clear -#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMC2 register. -// -//***************************************************************************** -#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FWBVAL register. -// -//***************************************************************************** -#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FLPEKEY register. -// -//***************************************************************************** -#define FLASH_FLPEKEY_PEKEY_M 0x0000FFFF // Key Value -#define FLASH_FLPEKEY_PEKEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FWBN register. -// -//***************************************************************************** -#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_PP register. -// -//***************************************************************************** -#define FLASH_PP_PFC 0x40000000 // Prefetch Buffer Mode -#define FLASH_PP_FMM 0x20000000 // Flash Mirror Mode -#define FLASH_PP_DFA 0x10000000 // DMA Flash Access -#define FLASH_PP_EESS_M 0x00780000 // EEPROM Sector Size of the - // physical bank -#define FLASH_PP_EESS_1KB 0x00000000 // 1 KB -#define FLASH_PP_EESS_2KB 0x00080000 // 2 KB -#define FLASH_PP_EESS_4KB 0x00100000 // 4 KB -#define FLASH_PP_EESS_8KB 0x00180000 // 8 KB -#define FLASH_PP_MAINSS_M 0x00070000 // Flash Sector Size of the - // physical bank -#define FLASH_PP_MAINSS_1KB 0x00000000 // 1 KB -#define FLASH_PP_MAINSS_2KB 0x00010000 // 2 KB -#define FLASH_PP_MAINSS_4KB 0x00020000 // 4 KB -#define FLASH_PP_MAINSS_8KB 0x00030000 // 8 KB -#define FLASH_PP_MAINSS_16KB 0x00040000 // 16 KB -#define FLASH_PP_SIZE_M 0x0000FFFF // Flash Size -#define FLASH_PP_SIZE_1MB 0x000001FF // 1024 KB of Flash - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_SSIZE register. -// -//***************************************************************************** -#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size -#define FLASH_SSIZE_SIZE_256KB 0x000003FF // 256 KB of SRAM - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CONF register. -// -//***************************************************************************** -#define FLASH_CONF_FMME 0x40000000 // Flash Mirror Mode Enable -#define FLASH_CONF_SPFE 0x20000000 // Single Prefetch Mode Enable -#define FLASH_CONF_CLRTV 0x00100000 // Clear Valid Tags -#define FLASH_CONF_FPFON 0x00020000 // Force Prefetch On -#define FLASH_CONF_FPFOFF 0x00010000 // Force Prefetch Off - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_ROMSWMAP register. -// -//***************************************************************************** -#define FLASH_ROMSWMAP_SW7EN_M 0x0000C000 // ROM SW Region 7 Availability -#define FLASH_ROMSWMAP_SW7EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW7EN_CORE \ - 0x00004000 // Region available to core -#define FLASH_ROMSWMAP_SW6EN_M 0x00003000 // ROM SW Region 6 Availability -#define FLASH_ROMSWMAP_SW6EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW6EN_CORE \ - 0x00001000 // Region available to core -#define FLASH_ROMSWMAP_SW5EN_M 0x00000C00 // ROM SW Region 5 Availability -#define FLASH_ROMSWMAP_SW5EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW5EN_CORE \ - 0x00000400 // Region available to core -#define FLASH_ROMSWMAP_SW4EN_M 0x00000300 // ROM SW Region 4 Availability -#define FLASH_ROMSWMAP_SW4EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW4EN_CORE \ - 0x00000100 // Region available to core -#define FLASH_ROMSWMAP_SW3EN_M 0x000000C0 // ROM SW Region 3 Availability -#define FLASH_ROMSWMAP_SW3EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW3EN_CORE \ - 0x00000040 // Region available to core -#define FLASH_ROMSWMAP_SW2EN_M 0x00000030 // ROM SW Region 2 Availability -#define FLASH_ROMSWMAP_SW2EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW2EN_CORE \ - 0x00000010 // Region available to core -#define FLASH_ROMSWMAP_SW1EN_M 0x0000000C // ROM SW Region 1 Availability -#define FLASH_ROMSWMAP_SW1EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW1EN_CORE \ - 0x00000004 // Region available to core -#define FLASH_ROMSWMAP_SW0EN_M 0x00000003 // ROM SW Region 0 Availability -#define FLASH_ROMSWMAP_SW0EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW0EN_CORE \ - 0x00000001 // Region available to core - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_DMASZ register. -// -//***************************************************************************** -#define FLASH_DMASZ_SIZE_M 0x0003FFFF // uDMA-accessible Memory Size -#define FLASH_DMASZ_SIZE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_DMAST register. -// -//***************************************************************************** -#define FLASH_DMAST_ADDR_M 0x1FFFF800 // Contains the starting address of - // the flash region accessible by - // uDMA if the FLASHPP register DFA - // bit is set -#define FLASH_DMAST_ADDR_S 11 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_RVP register. -// -//***************************************************************************** -#define FLASH_RVP_RV_M 0xFFFFFFFF // Reset Vector Pointer Address -#define FLASH_RVP_RV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_BOOTCFG register. -// -//***************************************************************************** -#define FLASH_BOOTCFG_NW 0x80000000 // Not Written -#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port -#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A -#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B -#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C -#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D -#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E -#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F -#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G -#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H -#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin -#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0 -#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1 -#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2 -#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3 -#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4 -#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5 -#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6 -#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7 -#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity -#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable -#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select -#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1 -#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG0 register. -// -//***************************************************************************** -#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG1 register. -// -//***************************************************************************** -#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG2 register. -// -//***************************************************************************** -#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG3 register. -// -//***************************************************************************** -#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE8 register. -// -//***************************************************************************** -#define FLASH_FMPRE8_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE8_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE9 register. -// -//***************************************************************************** -#define FLASH_FMPRE9_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE9_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE10 register. -// -//***************************************************************************** -#define FLASH_FMPRE10_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE10_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE11 register. -// -//***************************************************************************** -#define FLASH_FMPRE11_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE11_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE12 register. -// -//***************************************************************************** -#define FLASH_FMPRE12_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE12_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE13 register. -// -//***************************************************************************** -#define FLASH_FMPRE13_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE13_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE14 register. -// -//***************************************************************************** -#define FLASH_FMPRE14_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE14_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE15 register. -// -//***************************************************************************** -#define FLASH_FMPRE15_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE15_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE8 register. -// -//***************************************************************************** -#define FLASH_FMPPE8_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE8_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE9 register. -// -//***************************************************************************** -#define FLASH_FMPPE9_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE9_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE10 register. -// -//***************************************************************************** -#define FLASH_FMPPE10_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE10_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE11 register. -// -//***************************************************************************** -#define FLASH_FMPPE11_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE11_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE12 register. -// -//***************************************************************************** -#define FLASH_FMPPE12_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE12_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE13 register. -// -//***************************************************************************** -#define FLASH_FMPPE13_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE13_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE14 register. -// -//***************************************************************************** -#define FLASH_FMPPE14_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE14_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE15 register. -// -//***************************************************************************** -#define FLASH_FMPPE15_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE15_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version -#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 - // register format. -#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_TM4C129 \ - 0x000A0000 // Tiva(TM) TM4C129-class - // microcontrollers -#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision -#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) -#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer - // revision) -#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer - // revision) -#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision -#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major - // revision update -#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change -#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version -#define SYSCTL_DID1_VER_1 0x10000000 // fury_ib -#define SYSCTL_DID1_FAM_M 0x0F000000 // Family -#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers -#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number -#define SYSCTL_DID1_PRTNO_TM4C1294NCPDT \ - 0x001F0000 // TM4C1294NCPDT -#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin LQFP package -#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin LQFP package -#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin LQFP package -#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin BGA package -#define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package -#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range -#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range -#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type -#define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package -#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package -#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance -#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PTBOCTL register. -// -//***************************************************************************** -#define SYSCTL_PTBOCTL_VDDA_UBOR_M \ - 0x00000300 // VDDA under BOR Event Action -#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE \ - 0x00000000 // No Action -#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT \ - 0x00000100 // System control interrupt -#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI \ - 0x00000200 // NMI -#define SYSCTL_PTBOCTL_VDDA_UBOR_RST \ - 0x00000300 // Reset -#define SYSCTL_PTBOCTL_VDD_UBOR_M \ - 0x00000003 // VDD (VDDS) under BOR Event - // Action -#define SYSCTL_PTBOCTL_VDD_UBOR_NONE \ - 0x00000000 // No Action -#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT \ - 0x00000001 // System control interrupt -#define SYSCTL_PTBOCTL_VDD_UBOR_NMI \ - 0x00000002 // NMI -#define SYSCTL_PTBOCTL_VDD_UBOR_RST \ - 0x00000003 // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RIS register. -// -//***************************************************************************** -#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt - // Status -#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status -#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw - // Interrupt Status -#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_IMC register. -// -//***************************************************************************** -#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask -#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask -#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure - // Interrupt Mask -#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MISC register. -// -//***************************************************************************** -#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt - // Status -#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status -#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked - // Interrupt Status -#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset -#define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset -#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset -#define SYSCTL_RESC_SW 0x00000010 // Software Reset -#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset -#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset -#define SYSCTL_RESC_EXT 0x00000001 // External Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PWRTC register. -// -//***************************************************************************** -#define SYSCTL_PWRTC_VDDA_UBOR 0x00000010 // VDDA Under BOR Status -#define SYSCTL_PWRTC_VDD_UBOR 0x00000001 // VDD Under BOR Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_NMIC register. -// -//***************************************************************************** -#define SYSCTL_NMIC_MOSCFAIL 0x00010000 // MOSC Failure NMI -#define SYSCTL_NMIC_TAMPER 0x00000200 // Tamper Event NMI -#define SYSCTL_NMIC_WDT1 0x00000020 // Watch Dog Timer (WDT) 1 NMI -#define SYSCTL_NMIC_WDT0 0x00000008 // Watch Dog Timer (WDT) 0 NMI -#define SYSCTL_NMIC_POWER 0x00000004 // Power/Brown Out Event NMI -#define SYSCTL_NMIC_EXTERNAL 0x00000001 // External Pin NMI - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. -// -//***************************************************************************** -#define SYSCTL_MOSCCTL_OSCRNG 0x00000010 // Oscillator Range -#define SYSCTL_MOSCCTL_PWRDN 0x00000008 // Power Down -#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected -#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action -#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RSCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000 // Memory Timing Register Update -#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000 // New PLLFREQ Accept -#define SYSCTL_RSCLKCFG_ACG 0x20000000 // Auto Clock Gating -#define SYSCTL_RSCLKCFG_USEPLL 0x10000000 // Use PLL -#define SYSCTL_RSCLKCFG_PLLSRC_M \ - 0x0F000000 // PLL Source -#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC \ - 0x00000000 // PIOSC is PLL input clock source -#define SYSCTL_RSCLKCFG_PLLSRC_MOSC \ - 0x03000000 // MOSC is the PLL input clock - // source -#define SYSCTL_RSCLKCFG_OSCSRC_M \ - 0x00F00000 // Oscillator Source -#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC \ - 0x00000000 // PIOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC \ - 0x00200000 // LFIOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_MOSC \ - 0x00300000 // MOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_RTC \ - 0x00400000 // Hibernation Module RTC - // Oscillator (RTCOSC) -#define SYSCTL_RSCLKCFG_OSYSDIV_M \ - 0x000FFC00 // Oscillator System Clock Divisor -#define SYSCTL_RSCLKCFG_PSYSDIV_M \ - 0x000003FF // PLL System Clock Divisor -#define SYSCTL_RSCLKCFG_OSYSDIV_S \ - 10 -#define SYSCTL_RSCLKCFG_PSYSDIV_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register. -// -//***************************************************************************** -#define SYSCTL_MEMTIM0_EBCHT_M 0x03C00000 // EEPROM Clock High Time -#define SYSCTL_MEMTIM0_EBCHT_0_5 \ - 0x00000000 // 1/2 system clock period -#define SYSCTL_MEMTIM0_EBCHT_1 0x00400000 // 1 system clock period -#define SYSCTL_MEMTIM0_EBCHT_1_5 \ - 0x00800000 // 1.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_2 0x00C00000 // 2 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_2_5 \ - 0x01000000 // 2.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_3 0x01400000 // 3 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_3_5 \ - 0x01800000 // 3.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_4 0x01C00000 // 4 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_4_5 \ - 0x02000000 // 4.5 system clock periods -#define SYSCTL_MEMTIM0_EBCE 0x00200000 // EEPROM Bank Clock Edge -#define SYSCTL_MEMTIM0_EWS_M 0x000F0000 // EEPROM Wait States -#define SYSCTL_MEMTIM0_FBCHT_M 0x000003C0 // Flash Bank Clock High Time -#define SYSCTL_MEMTIM0_FBCHT_0_5 \ - 0x00000000 // 1/2 system clock period -#define SYSCTL_MEMTIM0_FBCHT_1 0x00000040 // 1 system clock period -#define SYSCTL_MEMTIM0_FBCHT_1_5 \ - 0x00000080 // 1.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_2 0x000000C0 // 2 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_2_5 \ - 0x00000100 // 2.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_3 0x00000140 // 3 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_3_5 \ - 0x00000180 // 3.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_4 0x000001C0 // 4 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_4_5 \ - 0x00000200 // 4.5 system clock periods -#define SYSCTL_MEMTIM0_FBCE 0x00000020 // Flash Bank Clock Edge -#define SYSCTL_MEMTIM0_FWS_M 0x0000000F // Flash Wait State -#define SYSCTL_MEMTIM0_EWS_S 16 -#define SYSCTL_MEMTIM0_FWS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_ALTCLKCFG_ALTCLK_M \ - 0x0000000F // Alternate Clock Source -#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC \ - 0x00000000 // PIOSC -#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC \ - 0x00000003 // Hibernation Module Real-time - // clock output (RTCOSC) -#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC \ - 0x00000004 // Low-frequency internal - // oscillator (LFIOSC) - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000 // PIOSC Power Down -#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000 // MOSC Disable Power Down -#define SYSCTL_DSCLKCFG_DSOSCSRC_M \ - 0x00F00000 // Deep Sleep Oscillator Source -#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC \ - 0x00000000 // PIOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC \ - 0x00200000 // LFIOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC \ - 0x00300000 // MOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC \ - 0x00400000 // Hibernation Module RTCOSC -#define SYSCTL_DSCLKCFG_DSSYSDIV_M \ - 0x000003FF // Deep Sleep Clock Divisor -#define SYSCTL_DSCLKCFG_DSSYSDIV_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DIVSCLK register. -// -//***************************************************************************** -#define SYSCTL_DIVSCLK_EN 0x80000000 // DIVSCLK Enable -#define SYSCTL_DIVSCLK_SRC_M 0x00030000 // Clock Source -#define SYSCTL_DIVSCLK_SRC_SYSCLK \ - 0x00000000 // System Clock -#define SYSCTL_DIVSCLK_SRC_PIOSC \ - 0x00010000 // PIOSC -#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000 // MOSC -#define SYSCTL_DIVSCLK_DIV_M 0x000000FF // Divisor Value -#define SYSCTL_DIVSCLK_DIV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SYSPROP register. -// -//***************************************************************************** -#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PIOSCCAL -// register. -// -//***************************************************************************** -#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value -#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration -#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim -#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value -#define SYSCTL_PIOSCCAL_UT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT -// register. -// -//***************************************************************************** -#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value -#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result -#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been - // attempted -#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation - // completed to meet 1% accuracy -#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation - // failed to meet 1% accuracy -#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value -#define SYSCTL_PIOSCSTAT_DT_S 16 -#define SYSCTL_PIOSCSTAT_CT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 -// register. -// -//***************************************************************************** -#define SYSCTL_PLLFREQ0_PLLPWR 0x00800000 // PLL Power -#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value -#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value -#define SYSCTL_PLLFREQ0_MFRAC_S 10 -#define SYSCTL_PLLFREQ0_MINT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 -// register. -// -//***************************************************************************** -#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value -#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value -#define SYSCTL_PLLFREQ1_Q_S 8 -#define SYSCTL_PLLFREQ1_N_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. -// -//***************************************************************************** -#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG -// register. -// -//***************************************************************************** -#define SYSCTL_SLPPWRCFG_FLASHPM_M \ - 0x00000030 // Flash Power Modes -#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \ - 0x00000020 // Low Power Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_M \ - 0x00000003 // SRAM Power Modes -#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \ - 0x00000001 // Standby Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_LP \ - 0x00000003 // Low Power Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200 // LDO Sleep Mode -#define SYSCTL_DSLPPWRCFG_TSPD 0x00000100 // Temperature Sense Power Down -#define SYSCTL_DSLPPWRCFG_FLASHPM_M \ - 0x00000030 // Flash Power Modes -#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \ - 0x00000020 // Low Power Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_M \ - 0x00000003 // SRAM Power Modes -#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \ - 0x00000001 // Standby Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \ - 0x00000003 // Low Power Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. -// -//***************************************************************************** -#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer - // Available - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_LDOSPCTL -// register. -// -//***************************************************************************** -#define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable -#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage -#define SYSCTL_LDOSPCTL_VLDO_0_90V \ - 0x00000012 // 0.90 V -#define SYSCTL_LDOSPCTL_VLDO_0_95V \ - 0x00000013 // 0.95 V -#define SYSCTL_LDOSPCTL_VLDO_1_00V \ - 0x00000014 // 1.00 V -#define SYSCTL_LDOSPCTL_VLDO_1_05V \ - 0x00000015 // 1.05 V -#define SYSCTL_LDOSPCTL_VLDO_1_10V \ - 0x00000016 // 1.10 V -#define SYSCTL_LDOSPCTL_VLDO_1_15V \ - 0x00000017 // 1.15 V -#define SYSCTL_LDOSPCTL_VLDO_1_20V \ - 0x00000018 // 1.20 V - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_LDODPCTL -// register. -// -//***************************************************************************** -#define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable -#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage -#define SYSCTL_LDODPCTL_VLDO_0_90V \ - 0x00000012 // 0.90 V -#define SYSCTL_LDODPCTL_VLDO_0_95V \ - 0x00000013 // 0.95 V -#define SYSCTL_LDODPCTL_VLDO_1_00V \ - 0x00000014 // 1.00 V -#define SYSCTL_LDODPCTL_VLDO_1_05V \ - 0x00000015 // 1.05 V -#define SYSCTL_LDODPCTL_VLDO_1_10V \ - 0x00000016 // 1.10 V -#define SYSCTL_LDODPCTL_VLDO_1_15V \ - 0x00000017 // 1.15 V -#define SYSCTL_LDODPCTL_VLDO_1_20V \ - 0x00000018 // 1.20 V -#define SYSCTL_LDODPCTL_VLDO_1_25V \ - 0x00000019 // 1.25 V -#define SYSCTL_LDODPCTL_VLDO_1_30V \ - 0x0000001A // 1.30 V -#define SYSCTL_LDODPCTL_VLDO_1_35V \ - 0x0000001B // 1.35 V - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL -// register. -// -//***************************************************************************** -#define SYSCTL_RESBEHAVCTL_WDOG1_M \ - 0x000000C0 // Watchdog 1 Reset Operation -#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST \ - 0x00000080 // Watchdog 1 issues a system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_WDOG1_POR \ - 0x000000C0 // Watchdog 1 issues a simulated - // POR sequence. Application starts - // less than 500 us after - // deassertion (Default) -#define SYSCTL_RESBEHAVCTL_WDOG0_M \ - 0x00000030 // Watchdog 0 Reset Operation -#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST \ - 0x00000020 // Watchdog 0 issues a system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_WDOG0_POR \ - 0x00000030 // Watchdog 0 issues a simulated - // POR sequence. Application starts - // less than 500 us after - // deassertion (Default) -#define SYSCTL_RESBEHAVCTL_BOR_M \ - 0x0000000C // BOR Reset operation -#define SYSCTL_RESBEHAVCTL_BOR_SYSRST \ - 0x00000008 // Brown Out Reset issues system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_BOR_POR \ - 0x0000000C // Brown Out Reset issues a - // simulated POR sequence. The - // application starts less than 500 - // us after deassertion (Default) -#define SYSCTL_RESBEHAVCTL_EXTRES_M \ - 0x00000003 // External RST Pin Operation -#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST \ - 0x00000002 // External RST assertion issues a - // system reset. The application - // starts within 10 us -#define SYSCTL_RESBEHAVCTL_EXTRES_POR \ - 0x00000003 // External RST assertion issues a - // simulated POR sequence. - // Application starts less than 500 - // us after deassertion (Default) - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_HSSR register. -// -//***************************************************************************** -#define SYSCTL_HSSR_KEY_M 0xFF000000 // Write Key -#define SYSCTL_HSSR_CDOFF_M 0x00FFFFFF // Command Descriptor Pointer -#define SYSCTL_HSSR_KEY_S 24 -#define SYSCTL_HSSR_CDOFF_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_USBPDS register. -// -//***************************************************************************** -#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C // Memory Array Power Status -#define SYSCTL_USBPDS_MEMSTAT_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_USBPDS_MEMSTAT_RETAIN \ - 0x00000004 // SRAM Retention -#define SYSCTL_USBPDS_MEMSTAT_ON \ - 0x0000000C // Array On -#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003 // Power Domain Status -#define SYSCTL_USBPDS_PWRSTAT_OFF \ - 0x00000000 // OFF -#define SYSCTL_USBPDS_PWRSTAT_ON \ - 0x00000003 // ON - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_USBMPC register. -// -//***************************************************************************** -#define SYSCTL_USBMPC_PWRCTL_M 0x00000003 // Memory Array Power Control -#define SYSCTL_USBMPC_PWRCTL_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_USBMPC_PWRCTL_RETAIN \ - 0x00000001 // SRAM Retention -#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003 // Array On - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_EMACPDS register. -// -//***************************************************************************** -#define SYSCTL_EMACPDS_MEMSTAT_M \ - 0x0000000C // Memory Array Power Status -#define SYSCTL_EMACPDS_MEMSTAT_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_EMACPDS_MEMSTAT_ON \ - 0x0000000C // Array On -#define SYSCTL_EMACPDS_PWRSTAT_M \ - 0x00000003 // Power Domain Status -#define SYSCTL_EMACPDS_PWRSTAT_OFF \ - 0x00000000 // OFF -#define SYSCTL_EMACPDS_PWRSTAT_ON \ - 0x00000003 // ON - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_EMACMPC register. -// -//***************************************************************************** -#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003 // Memory Array Power Control -#define SYSCTL_EMACMPC_PWRCTL_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_EMACMPC_PWRCTL_ON \ - 0x00000003 // Array On - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPWD register. -// -//***************************************************************************** -#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present -#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPTIMER register. -// -//***************************************************************************** -#define SYSCTL_PPTIMER_P7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Present -#define SYSCTL_PPTIMER_P6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Present -#define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Present -#define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Present -#define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Present -#define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Present -#define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Present -#define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPGPIO register. -// -//***************************************************************************** -#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present -#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present -#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present -#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present -#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present -#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present -#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present -#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present -#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present -#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present -#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present -#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present -#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present -#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present -#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPDMA register. -// -//***************************************************************************** -#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEPI register. -// -//***************************************************************************** -#define SYSCTL_PPEPI_P0 0x00000001 // EPI Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPHIB register. -// -//***************************************************************************** -#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPUART register. -// -//***************************************************************************** -#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present -#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present -#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present -#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present -#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present -#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present -#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present -#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPSSI register. -// -//***************************************************************************** -#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present -#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present -#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present -#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPI2C register. -// -//***************************************************************************** -#define SYSCTL_PPI2C_P9 0x00000200 // I2C Module 9 Present -#define SYSCTL_PPI2C_P8 0x00000100 // I2C Module 8 Present -#define SYSCTL_PPI2C_P7 0x00000080 // I2C Module 7 Present -#define SYSCTL_PPI2C_P6 0x00000040 // I2C Module 6 Present -#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present -#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present -#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present -#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present -#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present -#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPUSB register. -// -//***************************************************************************** -#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEPHY register. -// -//***************************************************************************** -#define SYSCTL_PPEPHY_P0 0x00000001 // Ethernet PHY Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPCAN register. -// -//***************************************************************************** -#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present -#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPADC register. -// -//***************************************************************************** -#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present -#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPACMP register. -// -//***************************************************************************** -#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPPWM register. -// -//***************************************************************************** -#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPQEI register. -// -//***************************************************************************** -#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPLPC register. -// -//***************************************************************************** -#define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPPECI register. -// -//***************************************************************************** -#define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPFAN register. -// -//***************************************************************************** -#define SYSCTL_PPFAN_P0 0x00000001 // FAN Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_PPWTIMER_P0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPRTS register. -// -//***************************************************************************** -#define SYSCTL_PPRTS_P0 0x00000001 // RTS Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPCCM register. -// -//***************************************************************************** -#define SYSCTL_PPCCM_P0 0x00000001 // CRC and Cryptographic Modules - // Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPLCD register. -// -//***************************************************************************** -#define SYSCTL_PPLCD_P0 0x00000001 // LCD Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPOWIRE register. -// -//***************************************************************************** -#define SYSCTL_PPOWIRE_P0 0x00000001 // 1-Wire Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEMAC register. -// -//***************************************************************************** -#define SYSCTL_PPEMAC_P0 0x00000001 // Ethernet Controller Module - // Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPHIM register. -// -//***************************************************************************** -#define SYSCTL_PPHIM_P0 0x00000001 // HIM Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRWD register. -// -//***************************************************************************** -#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset -#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRTIMER register. -// -//***************************************************************************** -#define SYSCTL_SRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Software Reset -#define SYSCTL_SRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Software Reset -#define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Software Reset -#define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Software Reset -#define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Software Reset -#define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Software Reset -#define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Software Reset -#define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRGPIO register. -// -//***************************************************************************** -#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset -#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset -#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset -#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset -#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset -#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset -#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset -#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset -#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset -#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset -#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset -#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset -#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset -#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset -#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRDMA register. -// -//***************************************************************************** -#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREPI register. -// -//***************************************************************************** -#define SYSCTL_SREPI_R0 0x00000001 // EPI Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRHIB register. -// -//***************************************************************************** -#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software - // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRUART register. -// -//***************************************************************************** -#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset -#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset -#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset -#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset -#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset -#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset -#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset -#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRSSI register. -// -//***************************************************************************** -#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset -#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset -#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset -#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRI2C register. -// -//***************************************************************************** -#define SYSCTL_SRI2C_R9 0x00000200 // I2C Module 9 Software Reset -#define SYSCTL_SRI2C_R8 0x00000100 // I2C Module 8 Software Reset -#define SYSCTL_SRI2C_R7 0x00000080 // I2C Module 7 Software Reset -#define SYSCTL_SRI2C_R6 0x00000040 // I2C Module 6 Software Reset -#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset -#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset -#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset -#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset -#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset -#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRUSB register. -// -//***************************************************************************** -#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREPHY register. -// -//***************************************************************************** -#define SYSCTL_SREPHY_R0 0x00000001 // Ethernet PHY Module Software - // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCAN register. -// -//***************************************************************************** -#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset -#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRADC register. -// -//***************************************************************************** -#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset -#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRACMP register. -// -//***************************************************************************** -#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRPWM register. -// -//***************************************************************************** -#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRQEI register. -// -//***************************************************************************** -#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCCM register. -// -//***************************************************************************** -#define SYSCTL_SRCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREMAC register. -// -//***************************************************************************** -#define SYSCTL_SREMAC_R0 0x00000001 // Ethernet Controller MAC Module 0 - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCWD register. -// -//***************************************************************************** -#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Run Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_RCGCEPI_R0 0x00000001 // EPI Module Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_RCGCI2C_R9 0x00000200 // I2C Module 9 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R8 0x00000100 // I2C Module 8 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R7 0x00000080 // I2C Module 7 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R6 0x00000040 // I2C Module 6 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEPHY_R0 0x00000001 // Ethernet PHY Module Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCADC register. -// -//***************************************************************************** -#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_RCGCCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Run Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEMAC_R0 0x00000001 // Ethernet MAC Module 0 Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCWD register. -// -//***************************************************************************** -#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCTIMER_S7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_SCGCEPI_S0 0x00000001 // EPI Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_SCGCI2C_S9 0x00000200 // I2C Module 9 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S8 0x00000100 // I2C Module 8 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S7 0x00000080 // I2C Module 7 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S6 0x00000040 // I2C Module 6 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEPHY_S0 0x00000001 // PHY Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCADC register. -// -//***************************************************************************** -#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_SCGCCCM_S0 0x00000001 // CRC and Cryptographic Modules - // Sleep Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEMAC_S0 0x00000001 // Ethernet MAC Module 0 Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCWD register. -// -//***************************************************************************** -#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCTIMER_D7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_DCGCEPI_D0 0x00000001 // EPI Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_DCGCI2C_D9 0x00000200 // I2C Module 9 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D8 0x00000100 // I2C Module 8 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D7 0x00000080 // I2C Module 7 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D6 0x00000040 // I2C Module 6 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEPHY_D0 0x00000001 // PHY Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCADC register. -// -//***************************************************************************** -#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 - // Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_DCGCCCM_D0 0x00000001 // CRC and Cryptographic Modules - // Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEMAC_D0 0x00000001 // Ethernet MAC Module 0 Deep-Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCWD register. -// -//***************************************************************************** -#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control -#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCTIMER register. -// -//***************************************************************************** -#define SYSCTL_PCTIMER_P7 0x00000080 // General-Purpose Timer 7 Power - // Control -#define SYSCTL_PCTIMER_P6 0x00000040 // General-Purpose Timer 6 Power - // Control -#define SYSCTL_PCTIMER_P5 0x00000020 // General-Purpose Timer 5 Power - // Control -#define SYSCTL_PCTIMER_P4 0x00000010 // General-Purpose Timer 4 Power - // Control -#define SYSCTL_PCTIMER_P3 0x00000008 // General-Purpose Timer 3 Power - // Control -#define SYSCTL_PCTIMER_P2 0x00000004 // General-Purpose Timer 2 Power - // Control -#define SYSCTL_PCTIMER_P1 0x00000002 // General-Purpose Timer 1 Power - // Control -#define SYSCTL_PCTIMER_P0 0x00000001 // General-Purpose Timer 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCGPIO register. -// -//***************************************************************************** -#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control -#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control -#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control -#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control -#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control -#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control -#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control -#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control -#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control -#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control -#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control -#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control -#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control -#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control -#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCDMA register. -// -//***************************************************************************** -#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEPI register. -// -//***************************************************************************** -#define SYSCTL_PCEPI_P0 0x00000001 // EPI Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCHIB register. -// -//***************************************************************************** -#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCUART register. -// -//***************************************************************************** -#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control -#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control -#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control -#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control -#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control -#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control -#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control -#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCSSI register. -// -//***************************************************************************** -#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control -#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control -#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control -#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCI2C register. -// -//***************************************************************************** -#define SYSCTL_PCI2C_P9 0x00000200 // I2C Module 9 Power Control -#define SYSCTL_PCI2C_P8 0x00000100 // I2C Module 8 Power Control -#define SYSCTL_PCI2C_P7 0x00000080 // I2C Module 7 Power Control -#define SYSCTL_PCI2C_P6 0x00000040 // I2C Module 6 Power Control -#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control -#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control -#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control -#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control -#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control -#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCUSB register. -// -//***************************************************************************** -#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEPHY register. -// -//***************************************************************************** -#define SYSCTL_PCEPHY_P0 0x00000001 // Ethernet PHY Module Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCCAN register. -// -//***************************************************************************** -#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control -#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCADC register. -// -//***************************************************************************** -#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control -#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCACMP register. -// -//***************************************************************************** -#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCPWM register. -// -//***************************************************************************** -#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCQEI register. -// -//***************************************************************************** -#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCCCM register. -// -//***************************************************************************** -#define SYSCTL_PCCCM_P0 0x00000001 // CRC and Cryptographic Modules - // Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEMAC register. -// -//***************************************************************************** -#define SYSCTL_PCEMAC_P0 0x00000001 // Ethernet MAC Module 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRWD register. -// -//***************************************************************************** -#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral - // Ready -#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRTIMER register. -// -//***************************************************************************** -#define SYSCTL_PRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Peripheral Ready -#define SYSCTL_PRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Peripheral Ready -#define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Peripheral Ready -#define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Peripheral Ready -#define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Peripheral Ready -#define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Peripheral Ready -#define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Peripheral Ready -#define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRGPIO register. -// -//***************************************************************************** -#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready -#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready -#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready -#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready -#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready -#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready -#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready -#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready -#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready -#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready -#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready -#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready -#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready -#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready -#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRDMA register. -// -//***************************************************************************** -#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREPI register. -// -//***************************************************************************** -#define SYSCTL_PREPI_R0 0x00000001 // EPI Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRHIB register. -// -//***************************************************************************** -#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRUART register. -// -//***************************************************************************** -#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready -#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready -#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready -#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready -#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready -#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready -#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready -#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRSSI register. -// -//***************************************************************************** -#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready -#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready -#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready -#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRI2C register. -// -//***************************************************************************** -#define SYSCTL_PRI2C_R9 0x00000200 // I2C Module 9 Peripheral Ready -#define SYSCTL_PRI2C_R8 0x00000100 // I2C Module 8 Peripheral Ready -#define SYSCTL_PRI2C_R7 0x00000080 // I2C Module 7 Peripheral Ready -#define SYSCTL_PRI2C_R6 0x00000040 // I2C Module 6 Peripheral Ready -#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready -#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready -#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready -#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready -#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready -#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRUSB register. -// -//***************************************************************************** -#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREPHY register. -// -//***************************************************************************** -#define SYSCTL_PREPHY_R0 0x00000001 // Ethernet PHY Module Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRCAN register. -// -//***************************************************************************** -#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready -#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRADC register. -// -//***************************************************************************** -#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready -#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRACMP register. -// -//***************************************************************************** -#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 - // Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRPWM register. -// -//***************************************************************************** -#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRQEI register. -// -//***************************************************************************** -#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRCCM register. -// -//***************************************************************************** -#define SYSCTL_PRCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREMAC register. -// -//***************************************************************************** -#define SYSCTL_PREMAC_R0 0x00000001 // Ethernet MAC Module 0 Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_STAT register. -// -//***************************************************************************** -#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 -#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status -#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle -#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data -#define UDMA_STAT_STATE_RD_SRCENDP \ - 0x00000020 // Reading source end pointer -#define UDMA_STAT_STATE_RD_DSTENDP \ - 0x00000030 // Reading destination end pointer -#define UDMA_STAT_STATE_RD_SRCDAT \ - 0x00000040 // Reading source data -#define UDMA_STAT_STATE_WR_DSTDAT \ - 0x00000050 // Writing destination data -#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to - // clear -#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data -#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled -#define UDMA_STAT_STATE_DONE 0x00000090 // Done -#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined -#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status -#define UDMA_STAT_DMACHANS_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CFG register. -// -//***************************************************************************** -#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CTLBASE register. -// -//***************************************************************************** -#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address -#define UDMA_CTLBASE_ADDR_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTBASE register. -// -//***************************************************************************** -#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address - // Pointer -#define UDMA_ALTBASE_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_WAITSTAT register. -// -//***************************************************************************** -#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_SWREQ register. -// -//***************************************************************************** -#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_USEBURSTSET -// register. -// -//***************************************************************************** -#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_USEBURSTCLR -// register. -// -//***************************************************************************** -#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_REQMASKSET -// register. -// -//***************************************************************************** -#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_REQMASKCLR -// register. -// -//***************************************************************************** -#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ENASET register. -// -//***************************************************************************** -#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ENACLR register. -// -//***************************************************************************** -#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTSET register. -// -//***************************************************************************** -#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTCLR register. -// -//***************************************************************************** -#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_PRIOSET register. -// -//***************************************************************************** -#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_PRIOCLR register. -// -//***************************************************************************** -#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ERRCLR register. -// -//***************************************************************************** -#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHASGN register. -// -//***************************************************************************** -#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select -#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel - // assignment -#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel - // assignment - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP0 register. -// -//***************************************************************************** -#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select -#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select -#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select -#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select -#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select -#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select -#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select -#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select -#define UDMA_CHMAP0_CH7SEL_S 28 -#define UDMA_CHMAP0_CH6SEL_S 24 -#define UDMA_CHMAP0_CH5SEL_S 20 -#define UDMA_CHMAP0_CH4SEL_S 16 -#define UDMA_CHMAP0_CH3SEL_S 12 -#define UDMA_CHMAP0_CH2SEL_S 8 -#define UDMA_CHMAP0_CH1SEL_S 4 -#define UDMA_CHMAP0_CH0SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP1 register. -// -//***************************************************************************** -#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select -#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select -#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select -#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select -#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select -#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select -#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select -#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select -#define UDMA_CHMAP1_CH15SEL_S 28 -#define UDMA_CHMAP1_CH14SEL_S 24 -#define UDMA_CHMAP1_CH13SEL_S 20 -#define UDMA_CHMAP1_CH12SEL_S 16 -#define UDMA_CHMAP1_CH11SEL_S 12 -#define UDMA_CHMAP1_CH10SEL_S 8 -#define UDMA_CHMAP1_CH9SEL_S 4 -#define UDMA_CHMAP1_CH8SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP2 register. -// -//***************************************************************************** -#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select -#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select -#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select -#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select -#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select -#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select -#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select -#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select -#define UDMA_CHMAP2_CH23SEL_S 28 -#define UDMA_CHMAP2_CH22SEL_S 24 -#define UDMA_CHMAP2_CH21SEL_S 20 -#define UDMA_CHMAP2_CH20SEL_S 16 -#define UDMA_CHMAP2_CH19SEL_S 12 -#define UDMA_CHMAP2_CH18SEL_S 8 -#define UDMA_CHMAP2_CH17SEL_S 4 -#define UDMA_CHMAP2_CH16SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP3 register. -// -//***************************************************************************** -#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select -#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select -#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select -#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select -#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select -#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select -#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select -#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select -#define UDMA_CHMAP3_CH31SEL_S 28 -#define UDMA_CHMAP3_CH30SEL_S 24 -#define UDMA_CHMAP3_CH29SEL_S 20 -#define UDMA_CHMAP3_CH28SEL_S 16 -#define UDMA_CHMAP3_CH27SEL_S 12 -#define UDMA_CHMAP3_CH26SEL_S 8 -#define UDMA_CHMAP3_CH25SEL_S 4 -#define UDMA_CHMAP3_CH24SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_SRCENDP register. -// -//***************************************************************************** -#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer -#define UDMA_SRCENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_DSTENDP register. -// -//***************************************************************************** -#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer -#define UDMA_DSTENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHCTL register. -// -//***************************************************************************** -#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment -#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word -#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word -#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment -#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word -#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment -#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word -#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word -#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment -#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word -#define UDMA_CHCTL_DSTPROT0 0x00200000 // Destination Privilege Access -#define UDMA_CHCTL_SRCPROT0 0x00040000 // Source Privilege Access -#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers -#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst -#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_CHCTL_XFERMODE_STOP \ - 0x00000000 // Stop -#define UDMA_CHCTL_XFERMODE_BASIC \ - 0x00000001 // Basic -#define UDMA_CHCTL_XFERMODE_AUTO \ - 0x00000002 // Auto-Request -#define UDMA_CHCTL_XFERMODE_PINGPONG \ - 0x00000003 // Ping-Pong -#define UDMA_CHCTL_XFERMODE_MEM_SG \ - 0x00000004 // Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_MEM_SGA \ - 0x00000005 // Alternate Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SG \ - 0x00000006 // Peripheral Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SGA \ - 0x00000007 // Alternate Peripheral - // Scatter-Gather -#define UDMA_CHCTL_XFERSIZE_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCCTRL register. -// -//***************************************************************************** -#define CCM_CRCCTRL_INIT_M 0x00006000 // CRC Initialization -#define CCM_CRCCTRL_INIT_SEED 0x00000000 // Use the CRCSEED register context - // as the starting value -#define CCM_CRCCTRL_INIT_0 0x00004000 // Initialize to all '0s' -#define CCM_CRCCTRL_INIT_1 0x00006000 // Initialize to all '1s' -#define CCM_CRCCTRL_SIZE 0x00001000 // Input Data Size -#define CCM_CRCCTRL_RESINV 0x00000200 // Result Inverse Enable -#define CCM_CRCCTRL_OBR 0x00000100 // Output Reverse Enable -#define CCM_CRCCTRL_BR 0x00000080 // Bit reverse enable -#define CCM_CRCCTRL_ENDIAN_M 0x00000030 // Endian Control -#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000 // Configuration unchanged. (B3, - // B2, B1, B0) -#define CCM_CRCCTRL_ENDIAN_SHW 0x00000010 // Bytes are swapped in half-words - // but half-words are not swapped - // (B2, B3, B0, B1) -#define CCM_CRCCTRL_ENDIAN_SHWNB \ - 0x00000020 // Half-words are swapped but bytes - // are not swapped in half-word. - // (B1, B0, B3, B2) -#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030 // Bytes are swapped in half-words - // and half-words are swapped. (B0, - // B1, B2, B3) -#define CCM_CRCCTRL_TYPE_M 0x0000000F // Operation Type -#define CCM_CRCCTRL_TYPE_P8055 0x00000000 // Polynomial 0x8005 -#define CCM_CRCCTRL_TYPE_P1021 0x00000001 // Polynomial 0x1021 -#define CCM_CRCCTRL_TYPE_P4C11DB7 \ - 0x00000002 // Polynomial 0x4C11DB7 -#define CCM_CRCCTRL_TYPE_P1EDC6F41 \ - 0x00000003 // Polynomial 0x1EDC6F41 -#define CCM_CRCCTRL_TYPE_TCPCHKSUM \ - 0x00000008 // TCP checksum - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCSEED register. -// -//***************************************************************************** -#define CCM_CRCSEED_SEED_M 0xFFFFFFFF // SEED/Context Value -#define CCM_CRCSEED_SEED_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCDIN register. -// -//***************************************************************************** -#define CCM_CRCDIN_DATAIN_M 0xFFFFFFFF // Data Input -#define CCM_CRCDIN_DATAIN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCRSLTPP -// register. -// -//***************************************************************************** -#define CCM_CRCRSLTPP_RSLTPP_M 0xFFFFFFFF // Post Processing Result -#define CCM_CRCRSLTPP_RSLTPP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTLR register. -// -//***************************************************************************** -#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating - // Point -#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple - // Cycle Instructions - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CURRENT -// register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN2 register. -// -//***************************************************************************** -#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN3 register. -// -//***************************************************************************** -#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS2 register. -// -//***************************************************************************** -#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS3 register. -// -//***************************************************************************** -#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND2 register. -// -//***************************************************************************** -#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND3 register. -// -//***************************************************************************** -#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND2 register. -// -//***************************************************************************** -#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND3 register. -// -//***************************************************************************** -#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE2 register. -// -//***************************************************************************** -#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE3 register. -// -//***************************************************************************** -#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI11 register. -// -//***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI12 register. -// -//***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI13 register. -// -//***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI14 register. -// -//***************************************************************************** -#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask -#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask -#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask -#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask -#define NVIC_PRI14_INTD_S 29 -#define NVIC_PRI14_INTC_S 21 -#define NVIC_PRI14_INTB_S 13 -#define NVIC_PRI14_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI15 register. -// -//***************************************************************************** -#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask -#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask -#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask -#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask -#define NVIC_PRI15_INTD_S 29 -#define NVIC_PRI15_INTC_S 21 -#define NVIC_PRI15_INTB_S 13 -#define NVIC_PRI15_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI16 register. -// -//***************************************************************************** -#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask -#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask -#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask -#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask -#define NVIC_PRI16_INTD_S 29 -#define NVIC_PRI16_INTC_S 21 -#define NVIC_PRI16_INTB_S 13 -#define NVIC_PRI16_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI17 register. -// -//***************************************************************************** -#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask -#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask -#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask -#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask -#define NVIC_PRI17_INTD_S 29 -#define NVIC_PRI17_INTC_S 21 -#define NVIC_PRI17_INTB_S 13 -#define NVIC_PRI17_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI18 register. -// -//***************************************************************************** -#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask -#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask -#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask -#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask -#define NVIC_PRI18_INTD_S 29 -#define NVIC_PRI18_INTC_S 21 -#define NVIC_PRI18_INTB_S 13 -#define NVIC_PRI18_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI19 register. -// -//***************************************************************************** -#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask -#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask -#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask -#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask -#define NVIC_PRI19_INTD_S 29 -#define NVIC_PRI19_INTC_S 21 -#define NVIC_PRI19_INTB_S 13 -#define NVIC_PRI19_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI20 register. -// -//***************************************************************************** -#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask -#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask -#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask -#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask -#define NVIC_PRI20_INTD_S 29 -#define NVIC_PRI20_INTC_S 21 -#define NVIC_PRI20_INTB_S 13 -#define NVIC_PRI20_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI21 register. -// -//***************************************************************************** -#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask -#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask -#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask -#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask -#define NVIC_PRI21_INTD_S 29 -#define NVIC_PRI21_INTC_S 21 -#define NVIC_PRI21_INTB_S 13 -#define NVIC_PRI21_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI22 register. -// -//***************************************************************************** -#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask -#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask -#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask -#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask -#define NVIC_PRI22_INTD_S 29 -#define NVIC_PRI22_INTC_S 21 -#define NVIC_PRI22_INTB_S 13 -#define NVIC_PRI22_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI23 register. -// -//***************************************************************************** -#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask -#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask -#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask -#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask -#define NVIC_PRI23_INTD_S 29 -#define NVIC_PRI23_INTC_S 21 -#define NVIC_PRI23_INTB_S 13 -#define NVIC_PRI23_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI24 register. -// -//***************************************************************************** -#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask -#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask -#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask -#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask -#define NVIC_PRI24_INTD_S 29 -#define NVIC_PRI24_INTC_S 21 -#define NVIC_PRI24_INTB_S 13 -#define NVIC_PRI24_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI25 register. -// -//***************************************************************************** -#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask -#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask -#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask -#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask -#define NVIC_PRI25_INTD_S 29 -#define NVIC_PRI25_INTC_S 21 -#define NVIC_PRI25_INTB_S 13 -#define NVIC_PRI25_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI26 register. -// -//***************************************************************************** -#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask -#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask -#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask -#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask -#define NVIC_PRI26_INTD_S 29 -#define NVIC_PRI26_INTC_S 21 -#define NVIC_PRI26_INTB_S 13 -#define NVIC_PRI26_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI27 register. -// -//***************************************************************************** -#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask -#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask -#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask -#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask -#define NVIC_PRI27_INTD_S 29 -#define NVIC_PRI27_INTC_S 21 -#define NVIC_PRI27_INTB_S 13 -#define NVIC_PRI27_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI28 register. -// -//***************************************************************************** -#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask -#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask -#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask -#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask -#define NVIC_PRI28_INTD_S 29 -#define NVIC_PRI28_INTC_S 21 -#define NVIC_PRI28_INTB_S 13 -#define NVIC_PRI28_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI -#define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault -#define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault -#define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault -#define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault -#define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall -#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV -#define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset -#define NVIC_VTABLE_OFFSET_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception - // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and - // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL -// register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending -#define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage - // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy - // State Preservation -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address - // Register Valid -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on - // Floating-Point Lazy State - // Preservation -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_HFAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DEBUG_STAT -// register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_ADDR -// register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPAC register. -// -//***************************************************************************** -#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access - // Privilege -#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied -#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only -#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access -#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access - // Privilege -#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied -#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only -#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_NUMBER -// register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE_ADDR_S 5 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable -#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable -#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable -#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE1_ADDR_S 5 -#define NVIC_MPU_BASE1_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR1_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR1_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR1_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE2_ADDR_S 5 -#define NVIC_MPU_BASE2_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR2_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR2_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR2_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE3_ADDR_S 5 -#define NVIC_MPU_BASE3_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR3_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR3_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR3_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read -#define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction - // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available -#define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID -#define NVIC_SW_TRIG_INTID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPCC register. -// -//***************************************************************************** -#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation - // Enable -#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable -#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready -#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready -#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready -#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready -#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode -#define NVIC_FPCC_USER 0x00000002 // User Privilege Level -#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPCA register. -// -//***************************************************************************** -#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address -#define NVIC_FPCA_ADDRESS_S 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPDSC register. -// -//***************************************************************************** -#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default -#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default -#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default -#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default -#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode -#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) - // mode -#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity - // (RM) mode -#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode - -//***************************************************************************** -// -// The following definitions are deprecated. -// -//***************************************************************************** -#ifndef DEPRECATED -#define SYSCTL_DID0_CLASS_SNOWFLAKE \ - 0x000A0000 // Tiva(TM) C Series TM4C129-class - // microcontrollers - -//***************************************************************************** -// -// Deprecated defines for the bit fields in the SYSCTL_PWRTC register. -// -//***************************************************************************** -#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010 // VDDA Under BOR0 Status -#define SYSCTL_PWRTC_VDD_UBOR0 0x00000001 // VDD Under BOR0 Status - -#endif - -#endif // __TM4C1294NCPDT_H__ diff --git a/bsp/tm4c129x-dk/libraries/startup/startup_ewarm.c b/bsp/tm4c129x-dk/libraries/startup/startup_ewarm.c deleted file mode 100644 index a5dbd78756cabf89a7ddc7b25b0588929d9c9ed4..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/startup/startup_ewarm.c +++ /dev/null @@ -1,302 +0,0 @@ -//***************************************************************************** -// -// startup_ewarm.c - Startup code for use with IAR's Embedded Workbench, -// version 5. -// -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Texas Instruments (TI) is supplying this software for use solely and -// exclusively on TI's microcontroller products. The software is owned by -// TI and/or its suppliers, and is protected under applicable copyright -// laws. You may not combine this software with "viral" open-source -// software in order to form a larger program. -// -// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -// DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. -// -//***************************************************************************** - -#include -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" - -//***************************************************************************** -// -// Enable the IAR extensions for this source file. -// -//***************************************************************************** -#pragma language=extended - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); - -//***************************************************************************** -// -// The entry point for the application startup code. -// -//***************************************************************************** -extern void __iar_program_start(void); -extern void PendSV_Handler(void); -extern void SysTick_Handler(void); -extern void UART0_IRQHandler(void); -extern void HardFault_Handler(void); -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -static uint32_t pui32Stack[128] @ ".noinit"; - -//***************************************************************************** -// -// A union that describes the entries of the vector table. The union is needed -// since the first entry is the stack pointer and the remainder are function -// pointers. -// -//***************************************************************************** -typedef union -{ - void (*pfnHandler)(void); - uint32_t ui32Ptr; -} -uVectorEntry; - -//***************************************************************************** -// -// The vector table. Note that the proper constructs must be placed on this to -// ensure that it ends up at physical address 0x0000.0000. -// -//***************************************************************************** -__root const uVectorEntry __vector_table[] @ ".intvec" = -{ - { .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) }, - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - HardFault_Handler, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - PendSV_Handler, //IntDefaultHandler, // The PendSV handler - SysTick_Handler,//IntDefaultHandler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - IntDefaultHandler, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - UART0_IRQHandler, //IntDefaultHandler, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI0 Rx and Tx - IntDefaultHandler, // I2C0 Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - IntDefaultHandler, // Quadrature Encoder 0 - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - IntDefaultHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler, // FLASH Control - IntDefaultHandler, // GPIO Port F - IntDefaultHandler, // GPIO Port G - IntDefaultHandler, // GPIO Port H - IntDefaultHandler, // UART2 Rx and Tx - IntDefaultHandler, // SSI1 Rx and Tx - IntDefaultHandler, // Timer 3 subtimer A - IntDefaultHandler, // Timer 3 subtimer B - IntDefaultHandler, // I2C1 Master and Slave - IntDefaultHandler, // CAN0 - IntDefaultHandler, // CAN1 - IntDefaultHandler, // Ethernet - IntDefaultHandler, // Hibernate - IntDefaultHandler, // USB0 - IntDefaultHandler, // PWM Generator 3 - IntDefaultHandler, // uDMA Software Transfer - IntDefaultHandler, // uDMA Error - IntDefaultHandler, // ADC1 Sequence 0 - IntDefaultHandler, // ADC1 Sequence 1 - IntDefaultHandler, // ADC1 Sequence 2 - IntDefaultHandler, // ADC1 Sequence 3 - IntDefaultHandler, // External Bus Interface 0 - IntDefaultHandler, // GPIO Port J - IntDefaultHandler, // GPIO Port K - IntDefaultHandler, // GPIO Port L - IntDefaultHandler, // SSI2 Rx and Tx - IntDefaultHandler, // SSI3 Rx and Tx - IntDefaultHandler, // UART3 Rx and Tx - IntDefaultHandler, // UART4 Rx and Tx - IntDefaultHandler, // UART5 Rx and Tx - IntDefaultHandler, // UART6 Rx and Tx - IntDefaultHandler, // UART7 Rx and Tx - IntDefaultHandler, // I2C2 Master and Slave - IntDefaultHandler, // I2C3 Master and Slave - IntDefaultHandler, // Timer 4 subtimer A - IntDefaultHandler, // Timer 4 subtimer B - IntDefaultHandler, // Timer 5 subtimer A - IntDefaultHandler, // Timer 5 subtimer B - IntDefaultHandler, // FPU - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // I2C4 Master and Slave - IntDefaultHandler, // I2C5 Master and Slave - IntDefaultHandler, // GPIO Port M - IntDefaultHandler, // GPIO Port N - 0, // Reserved - IntDefaultHandler, // Tamper - IntDefaultHandler, // GPIO Port P (Summary or P0) - IntDefaultHandler, // GPIO Port P1 - IntDefaultHandler, // GPIO Port P2 - IntDefaultHandler, // GPIO Port P3 - IntDefaultHandler, // GPIO Port P4 - IntDefaultHandler, // GPIO Port P5 - IntDefaultHandler, // GPIO Port P6 - IntDefaultHandler, // GPIO Port P7 - IntDefaultHandler, // GPIO Port Q (Summary or Q0) - IntDefaultHandler, // GPIO Port Q1 - IntDefaultHandler, // GPIO Port Q2 - IntDefaultHandler, // GPIO Port Q3 - IntDefaultHandler, // GPIO Port Q4 - IntDefaultHandler, // GPIO Port Q5 - IntDefaultHandler, // GPIO Port Q6 - IntDefaultHandler, // GPIO Port Q7 - IntDefaultHandler, // GPIO Port R - IntDefaultHandler, // GPIO Port S - IntDefaultHandler, // SHA/MD5 0 - IntDefaultHandler, // AES 0 - IntDefaultHandler, // DES3DES 0 - IntDefaultHandler, // LCD Controller 0 - IntDefaultHandler, // Timer 6 subtimer A - IntDefaultHandler, // Timer 6 subtimer B - IntDefaultHandler, // Timer 7 subtimer A - IntDefaultHandler, // Timer 7 subtimer B - IntDefaultHandler, // I2C6 Master and Slave - IntDefaultHandler, // I2C7 Master and Slave - IntDefaultHandler, // HIM Scan Matrix Keyboard 0 - IntDefaultHandler, // One Wire 0 - IntDefaultHandler, // HIM PS/2 0 - IntDefaultHandler, // HIM LED Sequencer 0 - IntDefaultHandler, // HIM Consumer IR 0 - IntDefaultHandler, // I2C8 Master and Slave - IntDefaultHandler, // I2C9 Master and Slave - IntDefaultHandler // GPIO Port T -}; - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - // - // Enable the floating-point unit. This must be done here to handle the - // case where main() uses floating-point and the function prologue saves - // floating-point registers (which will fault if floating-point is not - // enabled). Any configuration of the floating-point unit using DriverLib - // APIs must be done here prior to the floating-point unit being enabled. - // - // Note that this does not use DriverLib since it might not be included in - // this project. - // - HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & - ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | - NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); - - // - // Call the application's entry point. - // - __iar_program_start(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/bsp/tm4c129x-dk/libraries/startup/startup_gcc.c b/bsp/tm4c129x-dk/libraries/startup/startup_gcc.c deleted file mode 100644 index 9f20837e514ebedf7559eff5b9954c0c7535bc64..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/startup/startup_gcc.c +++ /dev/null @@ -1,319 +0,0 @@ -//***************************************************************************** -// -// startup_gcc.c - Startup code for use with GNU tools. -// -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Texas Instruments (TI) is supplying this software for use solely and -// exclusively on TI's microcontroller products. The software is owned by -// TI and/or its suppliers, and is protected under applicable copyright -// laws. You may not combine this software with "viral" open-source -// software in order to form a larger program. -// -// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -// DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. -// -//***************************************************************************** - -#include -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); - -//***************************************************************************** -// -// The entry point for the application. -// -//***************************************************************************** -extern int main(void); - -extern void SysTick_Handler(void); -extern void PendSV_Handler(void); -extern void UART0_IRQHandler(void); -extern void HardFault_Handler(void); -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -static uint32_t pui32Stack[64]; - -//***************************************************************************** -// -// The vector table. Note that the proper constructs must be placed on this to -// ensure that it ends up at physical address 0x0000.0000. -// -//***************************************************************************** -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = -{ - (void (*)(void))((uint32_t)pui32Stack + sizeof(pui32Stack)), - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - HardFault_Handler, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - IntDefaultHandler, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - UART0_IRQHandler, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI0 Rx and Tx - IntDefaultHandler, // I2C0 Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - IntDefaultHandler, // Quadrature Encoder 0 - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - IntDefaultHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler, // FLASH Control - IntDefaultHandler, // GPIO Port F - IntDefaultHandler, // GPIO Port G - IntDefaultHandler, // GPIO Port H - IntDefaultHandler, // UART2 Rx and Tx - IntDefaultHandler, // SSI1 Rx and Tx - IntDefaultHandler, // Timer 3 subtimer A - IntDefaultHandler, // Timer 3 subtimer B - IntDefaultHandler, // I2C1 Master and Slave - IntDefaultHandler, // CAN0 - IntDefaultHandler, // CAN1 - IntDefaultHandler, // Ethernet - IntDefaultHandler, // Hibernate - IntDefaultHandler, // USB0 - IntDefaultHandler, // PWM Generator 3 - IntDefaultHandler, // uDMA Software Transfer - IntDefaultHandler, // uDMA Error - IntDefaultHandler, // ADC1 Sequence 0 - IntDefaultHandler, // ADC1 Sequence 1 - IntDefaultHandler, // ADC1 Sequence 2 - IntDefaultHandler, // ADC1 Sequence 3 - IntDefaultHandler, // External Bus Interface 0 - IntDefaultHandler, // GPIO Port J - IntDefaultHandler, // GPIO Port K - IntDefaultHandler, // GPIO Port L - IntDefaultHandler, // SSI2 Rx and Tx - IntDefaultHandler, // SSI3 Rx and Tx - IntDefaultHandler, // UART3 Rx and Tx - IntDefaultHandler, // UART4 Rx and Tx - IntDefaultHandler, // UART5 Rx and Tx - IntDefaultHandler, // UART6 Rx and Tx - IntDefaultHandler, // UART7 Rx and Tx - IntDefaultHandler, // I2C2 Master and Slave - IntDefaultHandler, // I2C3 Master and Slave - IntDefaultHandler, // Timer 4 subtimer A - IntDefaultHandler, // Timer 4 subtimer B - IntDefaultHandler, // Timer 5 subtimer A - IntDefaultHandler, // Timer 5 subtimer B - IntDefaultHandler, // FPU - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // I2C4 Master and Slave - IntDefaultHandler, // I2C5 Master and Slave - IntDefaultHandler, // GPIO Port M - IntDefaultHandler, // GPIO Port N - 0, // Reserved - IntDefaultHandler, // Tamper - IntDefaultHandler, // GPIO Port P (Summary or P0) - IntDefaultHandler, // GPIO Port P1 - IntDefaultHandler, // GPIO Port P2 - IntDefaultHandler, // GPIO Port P3 - IntDefaultHandler, // GPIO Port P4 - IntDefaultHandler, // GPIO Port P5 - IntDefaultHandler, // GPIO Port P6 - IntDefaultHandler, // GPIO Port P7 - IntDefaultHandler, // GPIO Port Q (Summary or Q0) - IntDefaultHandler, // GPIO Port Q1 - IntDefaultHandler, // GPIO Port Q2 - IntDefaultHandler, // GPIO Port Q3 - IntDefaultHandler, // GPIO Port Q4 - IntDefaultHandler, // GPIO Port Q5 - IntDefaultHandler, // GPIO Port Q6 - IntDefaultHandler, // GPIO Port Q7 - IntDefaultHandler, // GPIO Port R - IntDefaultHandler, // GPIO Port S - IntDefaultHandler, // SHA/MD5 0 - IntDefaultHandler, // AES 0 - IntDefaultHandler, // DES3DES 0 - IntDefaultHandler, // LCD Controller 0 - IntDefaultHandler, // Timer 6 subtimer A - IntDefaultHandler, // Timer 6 subtimer B - IntDefaultHandler, // Timer 7 subtimer A - IntDefaultHandler, // Timer 7 subtimer B - IntDefaultHandler, // I2C6 Master and Slave - IntDefaultHandler, // I2C7 Master and Slave - IntDefaultHandler, // HIM Scan Matrix Keyboard 0 - IntDefaultHandler, // One Wire 0 - IntDefaultHandler, // HIM PS/2 0 - IntDefaultHandler, // HIM LED Sequencer 0 - IntDefaultHandler, // HIM Consumer IR 0 - IntDefaultHandler, // I2C8 Master and Slave - IntDefaultHandler, // I2C9 Master and Slave - IntDefaultHandler // GPIO Port T -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -extern uint32_t _sidata; -extern uint32_t _sdata; -extern uint32_t _edata; -extern uint32_t _sbss; -extern uint32_t _ebss; - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - uint32_t *pui32Src, *pui32Dest; - - // - // Copy the data segment initializers from flash to SRAM. - // - pui32Src = &_sidata; - for(pui32Dest = &_sdata; pui32Dest < &_edata; ) - { - *pui32Dest++ = *pui32Src++; - } - - // - // Zero fill the bss segment. - // - __asm(" ldr r0, =_sbss\n" - " ldr r1, =_ebss\n" - " mov r2, #0\n" - " .thumb_func\n" - "zero_loop:\n" - " cmp r0, r1\n" - " it lt\n" - " strlt r2, [r0], #4\n" - " blt zero_loop"); - - // - // Enable the floating-point unit. This must be done here to handle the - // case where main() uses floating-point and the function prologue saves - // floating-point registers (which will fault if floating-point is not - // enabled). Any configuration of the floating-point unit using DriverLib - // APIs must be done here prior to the floating-point unit being enabled. - // - // Note that this does not use DriverLib since it might not be included in - // this project. - // - HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & - ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | - NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); - - // - // Call the application's entry point. - // - main(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/bsp/tm4c129x-dk/libraries/startup/startup_rvmdk.S b/bsp/tm4c129x-dk/libraries/startup/startup_rvmdk.S deleted file mode 100644 index 3554d001434bd5b3bf9b423538432647bb291b56..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/libraries/startup/startup_rvmdk.S +++ /dev/null @@ -1,324 +0,0 @@ -; <<< Use Configuration Wizard in Context Menu >>> -;****************************************************************************** -; -; startup_rvmdk.S - Startup code for use with Keil's uVision. -; -; Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -; Software License Agreement -; -; Texas Instruments (TI) is supplying this software for use solely and -; exclusively on TI's microcontroller products. The software is owned by -; TI and/or its suppliers, and is protected under applicable copyright -; laws. You may not combine this software with "viral" open-source -; software in order to form a larger program. -; -; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -; DAMAGES, FOR ANY REASON WHATSOEVER. -; -; This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. -; -;****************************************************************************** - -;****************************************************************************** -; -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -;****************************************************************************** -Stack EQU 0x00000200 - -;****************************************************************************** -; -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -;****************************************************************************** -Heap EQU 0x00000000 - -;****************************************************************************** -; -; Allocate space for the stack. -; -;****************************************************************************** - AREA STACK, NOINIT, READWRITE, ALIGN=3 -StackMem - SPACE Stack -__initial_sp - -;****************************************************************************** -; -; Allocate space for the heap. -; -;****************************************************************************** - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -HeapMem - SPACE Heap -__heap_limit - -;****************************************************************************** -; -; Indicate that the code in this file preserves 8-byte alignment of the stack. -; -;****************************************************************************** - PRESERVE8 - -;****************************************************************************** -; -; Place code into the reset code section. -; -;****************************************************************************** - AREA RESET, CODE, READONLY - THUMB - -;****************************************************************************** -; -; The vector table. -; -;****************************************************************************** - EXPORT __Vectors -__Vectors - DCD StackMem + Stack ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NmiSR ; NMI Handler - DCD FaultISR ; Hard Fault Handler - DCD IntDefaultHandler ; The MPU fault handler - DCD IntDefaultHandler ; The bus fault handler - DCD IntDefaultHandler ; The usage fault handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD IntDefaultHandler ; SVCall handler - DCD IntDefaultHandler ; Debug monitor handler - DCD 0 ; Reserved - DCD IntDefaultHandler ; The PendSV handler - DCD IntDefaultHandler ; The SysTick handler - DCD IntDefaultHandler ; GPIO Port A - DCD IntDefaultHandler ; GPIO Port B - DCD IntDefaultHandler ; GPIO Port C - DCD IntDefaultHandler ; GPIO Port D - DCD IntDefaultHandler ; GPIO Port E - DCD IntDefaultHandler ; UART0 Rx and Tx - DCD IntDefaultHandler ; UART1 Rx and Tx - DCD IntDefaultHandler ; SSI0 Rx and Tx - DCD IntDefaultHandler ; I2C0 Master and Slave - DCD IntDefaultHandler ; PWM Fault - DCD IntDefaultHandler ; PWM Generator 0 - DCD IntDefaultHandler ; PWM Generator 1 - DCD IntDefaultHandler ; PWM Generator 2 - DCD IntDefaultHandler ; Quadrature Encoder 0 - DCD IntDefaultHandler ; ADC Sequence 0 - DCD IntDefaultHandler ; ADC Sequence 1 - DCD IntDefaultHandler ; ADC Sequence 2 - DCD IntDefaultHandler ; ADC Sequence 3 - DCD IntDefaultHandler ; Watchdog timer - DCD IntDefaultHandler ; Timer 0 subtimer A - DCD IntDefaultHandler ; Timer 0 subtimer B - DCD IntDefaultHandler ; Timer 1 subtimer A - DCD IntDefaultHandler ; Timer 1 subtimer B - DCD IntDefaultHandler ; Timer 2 subtimer A - DCD IntDefaultHandler ; Timer 2 subtimer B - DCD IntDefaultHandler ; Analog Comparator 0 - DCD IntDefaultHandler ; Analog Comparator 1 - DCD IntDefaultHandler ; Analog Comparator 2 - DCD IntDefaultHandler ; System Control (PLL, OSC, BO) - DCD IntDefaultHandler ; FLASH Control - DCD IntDefaultHandler ; GPIO Port F - DCD IntDefaultHandler ; GPIO Port G - DCD IntDefaultHandler ; GPIO Port H - DCD IntDefaultHandler ; UART2 Rx and Tx - DCD IntDefaultHandler ; SSI1 Rx and Tx - DCD IntDefaultHandler ; Timer 3 subtimer A - DCD IntDefaultHandler ; Timer 3 subtimer B - DCD IntDefaultHandler ; I2C1 Master and Slave - DCD IntDefaultHandler ; CAN0 - DCD IntDefaultHandler ; CAN1 - DCD IntDefaultHandler ; Ethernet - DCD IntDefaultHandler ; Hibernate - DCD IntDefaultHandler ; USB0 - DCD IntDefaultHandler ; PWM Generator 3 - DCD IntDefaultHandler ; uDMA Software Transfer - DCD IntDefaultHandler ; uDMA Error - DCD IntDefaultHandler ; ADC1 Sequence 0 - DCD IntDefaultHandler ; ADC1 Sequence 1 - DCD IntDefaultHandler ; ADC1 Sequence 2 - DCD IntDefaultHandler ; ADC1 Sequence 3 - DCD IntDefaultHandler ; External Bus Interface 0 - DCD IntDefaultHandler ; GPIO Port J - DCD IntDefaultHandler ; GPIO Port K - DCD IntDefaultHandler ; GPIO Port L - DCD IntDefaultHandler ; SSI2 Rx and Tx - DCD IntDefaultHandler ; SSI3 Rx and Tx - DCD IntDefaultHandler ; UART3 Rx and Tx - DCD IntDefaultHandler ; UART4 Rx and Tx - DCD IntDefaultHandler ; UART5 Rx and Tx - DCD IntDefaultHandler ; UART6 Rx and Tx - DCD IntDefaultHandler ; UART7 Rx and Tx - DCD IntDefaultHandler ; I2C2 Master and Slave - DCD IntDefaultHandler ; I2C3 Master and Slave - DCD IntDefaultHandler ; Timer 4 subtimer A - DCD IntDefaultHandler ; Timer 4 subtimer B - DCD IntDefaultHandler ; Timer 5 subtimer A - DCD IntDefaultHandler ; Timer 5 subtimer B - DCD IntDefaultHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD IntDefaultHandler ; I2C4 Master and Slave - DCD IntDefaultHandler ; I2C5 Master and Slave - DCD IntDefaultHandler ; GPIO Port M - DCD IntDefaultHandler ; GPIO Port N - DCD 0 ; Reserved - DCD IntDefaultHandler ; Tamper - DCD IntDefaultHandler ; GPIO Port P (Summary or P0) - DCD IntDefaultHandler ; GPIO Port P1 - DCD IntDefaultHandler ; GPIO Port P2 - DCD IntDefaultHandler ; GPIO Port P3 - DCD IntDefaultHandler ; GPIO Port P4 - DCD IntDefaultHandler ; GPIO Port P5 - DCD IntDefaultHandler ; GPIO Port P6 - DCD IntDefaultHandler ; GPIO Port P7 - DCD IntDefaultHandler ; GPIO Port Q (Summary or Q0) - DCD IntDefaultHandler ; GPIO Port Q1 - DCD IntDefaultHandler ; GPIO Port Q2 - DCD IntDefaultHandler ; GPIO Port Q3 - DCD IntDefaultHandler ; GPIO Port Q4 - DCD IntDefaultHandler ; GPIO Port Q5 - DCD IntDefaultHandler ; GPIO Port Q6 - DCD IntDefaultHandler ; GPIO Port Q7 - DCD IntDefaultHandler ; GPIO Port R - DCD IntDefaultHandler ; GPIO Port S - DCD IntDefaultHandler ; SHA/MD5 0 - DCD IntDefaultHandler ; AES 0 - DCD IntDefaultHandler ; DES3DES 0 - DCD IntDefaultHandler ; LCD Controller 0 - DCD IntDefaultHandler ; Timer 6 subtimer A - DCD IntDefaultHandler ; Timer 6 subtimer B - DCD IntDefaultHandler ; Timer 7 subtimer A - DCD IntDefaultHandler ; Timer 7 subtimer B - DCD IntDefaultHandler ; I2C6 Master and Slave - DCD IntDefaultHandler ; I2C7 Master and Slave - DCD IntDefaultHandler ; HIM Scan Matrix Keyboard 0 - DCD IntDefaultHandler ; One Wire 0 - DCD IntDefaultHandler ; HIM PS/2 0 - DCD IntDefaultHandler ; HIM LED Sequencer 0 - DCD IntDefaultHandler ; HIM Consumer IR 0 - DCD IntDefaultHandler ; I2C8 Master and Slave - DCD IntDefaultHandler ; I2C9 Master and Slave - DCD IntDefaultHandler ; GPIO Port T - -;****************************************************************************** -; -; This is the code that gets called when the processor first starts execution -; following a reset event. -; -;****************************************************************************** - EXPORT Reset_Handler -Reset_Handler - ; - ; Enable the floating-point unit. This must be done here to handle the - ; case where main() uses floating-point and the function prologue saves - ; floating-point registers (which will fault if floating-point is not - ; enabled). Any configuration of the floating-point unit using - ; DriverLib APIs must be done here prior to the floating-point unit - ; being enabled. - ; - ; Note that this does not use DriverLib since it might not be included - ; in this project. - ; - MOVW R0, #0xED88 - MOVT R0, #0xE000 - LDR R1, [R0] - ORR R1, #0x00F00000 - STR R1, [R0] - - ; - ; Call the C library enty point that handles startup. This will copy - ; the .data section initializers from flash to SRAM and zero fill the - ; .bss section. - ; - IMPORT __main - B __main - -;****************************************************************************** -; -; This is the code that gets called when the processor receives a NMI. This -; simply enters an infinite loop, preserving the system state for examination -; by a debugger. -; -;****************************************************************************** -NmiSR - B NmiSR - -;****************************************************************************** -; -; This is the code that gets called when the processor receives a fault -; interrupt. This simply enters an infinite loop, preserving the system state -; for examination by a debugger. -; -;****************************************************************************** -FaultISR - B FaultISR - -;****************************************************************************** -; -; This is the code that gets called when the processor receives an unexpected -; interrupt. This simply enters an infinite loop, preserving the system state -; for examination by a debugger. -; -;****************************************************************************** -IntDefaultHandler - B IntDefaultHandler - -;****************************************************************************** -; -; Make sure the end of this section is aligned. -; -;****************************************************************************** - ALIGN - -;****************************************************************************** -; -; Some code in the normal code section for initializing the heap and stack. -; -;****************************************************************************** - AREA |.text|, CODE, READONLY - -;****************************************************************************** -; -; The function expected of the C library startup code for defining the stack -; and heap memory locations. For the C library version of the startup code, -; provide this function so that the C library initialization code can find out -; the location of the stack and heap. -; -;****************************************************************************** - IF :DEF: __MICROLIB - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - ELSE - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - LDR R0, =HeapMem - LDR R1, =(StackMem + Stack) - LDR R2, =(HeapMem + Heap) - LDR R3, =StackMem - BX LR - ENDIF - -;****************************************************************************** -; -; Make sure the end of this section is aligned. -; -;****************************************************************************** - ALIGN - -;****************************************************************************** -; -; Tell the assembler that we're done. -; -;****************************************************************************** - END diff --git a/bsp/tm4c129x-dk/project.ewp b/bsp/tm4c129x-dk/project.ewp deleted file mode 100644 index aa39574c29f3fcb7af1b26e0e137ab7e9167dd11..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/project.ewp +++ /dev/null @@ -1,2276 +0,0 @@ - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 22 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - Libraries - - $PROJ_DIR$\libraries/driverlib/adc.c - - - $PROJ_DIR$\libraries/driverlib/aes.c - - - $PROJ_DIR$\libraries/driverlib/can.c - - - $PROJ_DIR$\libraries/driverlib/comp.c - - - $PROJ_DIR$\libraries/driverlib/cpu.c - - - $PROJ_DIR$\libraries/driverlib/crc.c - - - $PROJ_DIR$\libraries/driverlib/des.c - - - $PROJ_DIR$\libraries/driverlib/eeprom.c - - - $PROJ_DIR$\libraries/driverlib/emac.c - - - $PROJ_DIR$\libraries/driverlib/epi.c - - - $PROJ_DIR$\libraries/driverlib/flash.c - - - $PROJ_DIR$\libraries/driverlib/fpu.c - - - $PROJ_DIR$\libraries/driverlib/gpio.c - - - $PROJ_DIR$\libraries/driverlib/hibernate.c - - - $PROJ_DIR$\libraries/driverlib/i2c.c - - - $PROJ_DIR$\libraries/driverlib/interrupt.c - - - $PROJ_DIR$\libraries/driverlib/lcd.c - - - $PROJ_DIR$\libraries/driverlib/mpu.c - - - $PROJ_DIR$\libraries/driverlib/pwm.c - - - $PROJ_DIR$\libraries/driverlib/qei.c - - - $PROJ_DIR$\libraries/driverlib/shamd5.c - - - $PROJ_DIR$\libraries/driverlib/ssi.c - - - $PROJ_DIR$\libraries/driverlib/sw_crc.c - - - $PROJ_DIR$\libraries/driverlib/sysctl.c - - - $PROJ_DIR$\libraries/driverlib/sysexc.c - - - $PROJ_DIR$\libraries/driverlib/systick.c - - - $PROJ_DIR$\libraries/driverlib/tiva_timer.c - - - $PROJ_DIR$\libraries/driverlib/uart.c - - - $PROJ_DIR$\libraries/driverlib/udma.c - - - $PROJ_DIR$\libraries/driverlib/usb.c - - - $PROJ_DIR$\libraries/driverlib/watchdog.c - - - $PROJ_DIR$\libraries/startup/startup_ewarm.c - - - - Drivers - - $PROJ_DIR$\drivers/drv_eth.c - - - $PROJ_DIR$\drivers/drv_uart.c - - - - Applications - - $PROJ_DIR$\applications/application.c - - - $PROJ_DIR$\applications/board.c - - - - Kernel - - $PROJ_DIR$\../../src/clock.c - - - $PROJ_DIR$\../../src/components.c - - - $PROJ_DIR$\../../src/device.c - - - $PROJ_DIR$\../../src/idle.c - - - $PROJ_DIR$\../../src/ipc.c - - - $PROJ_DIR$\../../src/irq.c - - - $PROJ_DIR$\../../src/kservice.c - - - $PROJ_DIR$\../../src/mem.c - - - $PROJ_DIR$\../../src/memheap.c - - - $PROJ_DIR$\../../src/mempool.c - - - $PROJ_DIR$\../../src/object.c - - - $PROJ_DIR$\../../src/scheduler.c - - - $PROJ_DIR$\../../src/signal.c - - - $PROJ_DIR$\../../src/thread.c - - - $PROJ_DIR$\../../src/timer.c - - - - CORTEX-M4 - - $PROJ_DIR$\../../libcpu/arm/cortex-m4/cpuport.c - - - $PROJ_DIR$\../../libcpu/arm/cortex-m4/context_iar.S - - - $PROJ_DIR$\../../libcpu/arm/common/backtrace.c - - - $PROJ_DIR$\../../libcpu/arm/common/div0.c - - - $PROJ_DIR$\../../libcpu/arm/common/showmem.c - - - - DeviceDrivers - - $PROJ_DIR$\../../components/drivers/serial/serial.c - - - $PROJ_DIR$\../../components/drivers/src/completion.c - - - $PROJ_DIR$\../../components/drivers/src/dataqueue.c - - - $PROJ_DIR$\../../components/drivers/src/pipe.c - - - $PROJ_DIR$\../../components/drivers/src/ringbuffer.c - - - $PROJ_DIR$\../../components/drivers/src/waitqueue.c - - - $PROJ_DIR$\../../components/drivers/src/workqueue.c - - - - finsh - - $PROJ_DIR$\../../components/finsh/shell.c - - - $PROJ_DIR$\../../components/finsh/symbol.c - - - $PROJ_DIR$\../../components/finsh/cmd.c - - - $PROJ_DIR$\../../components/finsh/finsh_compiler.c - - - $PROJ_DIR$\../../components/finsh/finsh_error.c - - - $PROJ_DIR$\../../components/finsh/finsh_heap.c - - - $PROJ_DIR$\../../components/finsh/finsh_init.c - - - $PROJ_DIR$\../../components/finsh/finsh_node.c - - - $PROJ_DIR$\../../components/finsh/finsh_ops.c - - - $PROJ_DIR$\../../components/finsh/finsh_parser.c - - - $PROJ_DIR$\../../components/finsh/finsh_var.c - - - $PROJ_DIR$\../../components/finsh/finsh_vm.c - - - $PROJ_DIR$\../../components/finsh/finsh_token.c - - - - LwIP - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/api_lib.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/api_msg.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/err.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/netbuf.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/netdb.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/netifapi.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/sockets.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/tcpip.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/arch/sys_arch.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/def.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/dhcp.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/dns.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/init.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/memp.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/netif.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/pbuf.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/raw.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/stats.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/sys.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/tcp.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/tcp_in.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/tcp_out.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/timers.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/udp.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/inet.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/ip.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/netif/etharp.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/netif/ethernetif.c - - - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/netif/slipif.c - - - diff --git a/bsp/tm4c129x-dk/project.eww b/bsp/tm4c129x-dk/project.eww deleted file mode 100644 index faa93f37cdf824efd53c15b77e75dc1f03727d9a..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/project.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\project.ewp - - - - - diff --git a/bsp/tm4c129x-dk/project.uvoptx b/bsp/tm4c129x-dk/project.uvoptx deleted file mode 100644 index e93d27b1516b1827203356a24c8beeadaeaf898a..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/project.uvoptx +++ /dev/null @@ -1,1570 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - RT-Thread TM4C129X - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 4 - - - 0 - Tiva C Series TM4C1294 Connected LaunchPad Web Page (EK-TM4C1294XL) - http://http://www.ti.com/tool/ek-tm4c1294xl - - - 1 - DK-TM4C129X Connected Development Kit Web Page (DK-TM4C129x) - http://www.ti.com/tool/DK-TM4C129X - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - - - - - - - BIN\UL2CM3.DLL - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0TM4C129_1024 -FL0100000 -FS00 -FP0($$Device:TM4C129XNCZAD$Flash\TM4C129_1024.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - - - 0 - - - - - Libraries - 0 - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - libraries/driverlib/adc.c - adc.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - libraries/driverlib/aes.c - aes.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - libraries/driverlib/can.c - can.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - libraries/driverlib/comp.c - comp.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - libraries/driverlib/cpu.c - cpu.c - 0 - 0 - - - 1 - 6 - 1 - 0 - 0 - 0 - libraries/driverlib/crc.c - crc.c - 0 - 0 - - - 1 - 7 - 1 - 0 - 0 - 0 - libraries/driverlib/des.c - des.c - 0 - 0 - - - 1 - 8 - 1 - 0 - 0 - 0 - libraries/driverlib/eeprom.c - eeprom.c - 0 - 0 - - - 1 - 9 - 1 - 0 - 0 - 0 - libraries/driverlib/emac.c - emac.c - 0 - 0 - - - 1 - 10 - 1 - 0 - 0 - 0 - libraries/driverlib/epi.c - epi.c - 0 - 0 - - - 1 - 11 - 1 - 0 - 0 - 0 - libraries/driverlib/flash.c - flash.c - 0 - 0 - - - 1 - 12 - 1 - 0 - 0 - 0 - libraries/driverlib/fpu.c - fpu.c - 0 - 0 - - - 1 - 13 - 1 - 0 - 0 - 0 - libraries/driverlib/gpio.c - gpio.c - 0 - 0 - - - 1 - 14 - 1 - 0 - 0 - 0 - libraries/driverlib/hibernate.c - hibernate.c - 0 - 0 - - - 1 - 15 - 1 - 0 - 0 - 0 - libraries/driverlib/i2c.c - i2c.c - 0 - 0 - - - 1 - 16 - 1 - 0 - 0 - 0 - libraries/driverlib/interrupt.c - interrupt.c - 0 - 0 - - - 1 - 17 - 1 - 0 - 0 - 0 - libraries/driverlib/lcd.c - lcd.c - 0 - 0 - - - 1 - 18 - 1 - 0 - 0 - 0 - libraries/driverlib/mpu.c - mpu.c - 0 - 0 - - - 1 - 19 - 1 - 0 - 0 - 0 - libraries/driverlib/pwm.c - pwm.c - 0 - 0 - - - 1 - 20 - 1 - 0 - 0 - 0 - libraries/driverlib/qei.c - qei.c - 0 - 0 - - - 1 - 21 - 1 - 0 - 0 - 0 - libraries/driverlib/shamd5.c - shamd5.c - 0 - 0 - - - 1 - 22 - 1 - 0 - 0 - 0 - libraries/driverlib/ssi.c - ssi.c - 0 - 0 - - - 1 - 23 - 1 - 0 - 0 - 0 - libraries/driverlib/sw_crc.c - sw_crc.c - 0 - 0 - - - 1 - 24 - 1 - 0 - 0 - 0 - libraries/driverlib/sysctl.c - sysctl.c - 0 - 0 - - - 1 - 25 - 1 - 0 - 0 - 0 - libraries/driverlib/sysexc.c - sysexc.c - 0 - 0 - - - 1 - 26 - 1 - 0 - 0 - 0 - libraries/driverlib/systick.c - systick.c - 0 - 0 - - - 1 - 27 - 1 - 0 - 0 - 0 - libraries/driverlib/tiva_timer.c - tiva_timer.c - 0 - 0 - - - 1 - 28 - 1 - 0 - 0 - 0 - libraries/driverlib/uart.c - uart.c - 0 - 0 - - - 1 - 29 - 1 - 0 - 0 - 0 - libraries/driverlib/udma.c - udma.c - 0 - 0 - - - 1 - 30 - 1 - 0 - 0 - 0 - libraries/driverlib/usb.c - usb.c - 0 - 0 - - - 1 - 31 - 1 - 0 - 0 - 0 - libraries/driverlib/watchdog.c - watchdog.c - 0 - 0 - - - 1 - 32 - 2 - 0 - 0 - 0 - libraries/startup/startup_rvmdk.S - startup_rvmdk.S - 0 - 0 - - - - - Drivers - 0 - 0 - 0 - 0 - - 2 - 33 - 1 - 0 - 0 - 0 - drivers/drv_eth.c - drv_eth.c - 0 - 0 - - - 2 - 34 - 1 - 0 - 0 - 0 - drivers/drv_uart.c - drv_uart.c - 0 - 0 - - - - - Applications - 1 - 0 - 0 - 0 - - 3 - 35 - 1 - 0 - 0 - 0 - applications/application.c - application.c - 0 - 0 - - - 3 - 36 - 1 - 0 - 0 - 0 - applications/board.c - board.c - 0 - 0 - - - - - Kernel - 0 - 0 - 0 - 0 - - 4 - 37 - 1 - 0 - 0 - 0 - ../../src/clock.c - clock.c - 0 - 0 - - - 4 - 38 - 1 - 0 - 0 - 0 - ../../src/components.c - components.c - 0 - 0 - - - 4 - 39 - 1 - 0 - 0 - 0 - ../../src/device.c - device.c - 0 - 0 - - - 4 - 40 - 1 - 0 - 0 - 0 - ../../src/idle.c - idle.c - 0 - 0 - - - 4 - 41 - 1 - 0 - 0 - 0 - ../../src/ipc.c - ipc.c - 0 - 0 - - - 4 - 42 - 1 - 0 - 0 - 0 - ../../src/irq.c - irq.c - 0 - 0 - - - 4 - 43 - 1 - 0 - 0 - 0 - ../../src/kservice.c - kservice.c - 0 - 0 - - - 4 - 44 - 1 - 0 - 0 - 0 - ../../src/mem.c - mem.c - 0 - 0 - - - 4 - 45 - 1 - 0 - 0 - 0 - ../../src/memheap.c - memheap.c - 0 - 0 - - - 4 - 46 - 1 - 0 - 0 - 0 - ../../src/mempool.c - mempool.c - 0 - 0 - - - 4 - 47 - 1 - 0 - 0 - 0 - ../../src/object.c - object.c - 0 - 0 - - - 4 - 48 - 1 - 0 - 0 - 0 - ../../src/scheduler.c - scheduler.c - 0 - 0 - - - 4 - 49 - 1 - 0 - 0 - 0 - ../../src/signal.c - signal.c - 0 - 0 - - - 4 - 50 - 1 - 0 - 0 - 0 - ../../src/thread.c - thread.c - 0 - 0 - - - 4 - 51 - 1 - 0 - 0 - 0 - ../../src/timer.c - timer.c - 0 - 0 - - - - - CORTEX-M4 - 0 - 0 - 0 - 0 - - 5 - 52 - 1 - 0 - 0 - 0 - ../../libcpu/arm/cortex-m4/cpuport.c - cpuport.c - 0 - 0 - - - 5 - 53 - 2 - 0 - 0 - 0 - ../../libcpu/arm/cortex-m4/context_rvds.S - context_rvds.S - 0 - 0 - - - 5 - 54 - 1 - 0 - 0 - 0 - ../../libcpu/arm/common/backtrace.c - backtrace.c - 0 - 0 - - - 5 - 55 - 1 - 0 - 0 - 0 - ../../libcpu/arm/common/div0.c - div0.c - 0 - 0 - - - 5 - 56 - 1 - 0 - 0 - 0 - ../../libcpu/arm/common/showmem.c - showmem.c - 0 - 0 - - - - - DeviceDrivers - 0 - 0 - 0 - 0 - - 6 - 57 - 1 - 0 - 0 - 0 - ../../components/drivers/serial/serial.c - serial.c - 0 - 0 - - - 6 - 58 - 1 - 0 - 0 - 0 - ../../components/drivers/src/completion.c - completion.c - 0 - 0 - - - 6 - 59 - 1 - 0 - 0 - 0 - ../../components/drivers/src/dataqueue.c - dataqueue.c - 0 - 0 - - - 6 - 60 - 1 - 0 - 0 - 0 - ../../components/drivers/src/pipe.c - pipe.c - 0 - 0 - - - 6 - 61 - 1 - 0 - 0 - 0 - ../../components/drivers/src/ringbuffer.c - ringbuffer.c - 0 - 0 - - - 6 - 62 - 1 - 0 - 0 - 0 - ../../components/drivers/src/waitqueue.c - waitqueue.c - 0 - 0 - - - 6 - 63 - 1 - 0 - 0 - 0 - ../../components/drivers/src/workqueue.c - workqueue.c - 0 - 0 - - - - - finsh - 0 - 0 - 0 - 0 - - 7 - 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finsh_vm.c - 0 - 0 - - - 7 - 76 - 1 - 0 - 0 - 0 - ../../components/finsh/finsh_token.c - finsh_token.c - 0 - 0 - - - - - LwIP - 0 - 0 - 0 - 0 - - 8 - 77 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/api_lib.c - api_lib.c - 0 - 0 - - - 8 - 78 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/api_msg.c - api_msg.c - 0 - 0 - - - 8 - 79 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/err.c - err.c - 0 - 0 - - - 8 - 80 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/netbuf.c - netbuf.c - 0 - 0 - - - 8 - 81 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/netdb.c - netdb.c - 0 - 0 - - - 8 - 82 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/netifapi.c - netifapi.c - 0 - 0 - - - 8 - 83 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/sockets.c - sockets.c - 0 - 0 - - - 8 - 84 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/tcpip.c - tcpip.c - 0 - 0 - - - 8 - 85 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/arch/sys_arch.c - sys_arch.c - 0 - 0 - - - 8 - 86 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/def.c - def.c - 0 - 0 - - - 8 - 87 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/dhcp.c - dhcp.c - 0 - 0 - - - 8 - 88 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/dns.c - dns.c - 0 - 0 - - - 8 - 89 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/init.c - init.c - 0 - 0 - - - 8 - 90 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/memp.c - memp.c - 0 - 0 - - - 8 - 91 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/netif.c - netif.c - 0 - 0 - - - 8 - 92 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/pbuf.c - pbuf.c - 0 - 0 - - - 8 - 93 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/raw.c - raw.c - 0 - 0 - - - 8 - 94 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/stats.c - stats.c - 0 - 0 - - - 8 - 95 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/sys.c - sys.c - 0 - 0 - - - 8 - 96 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/tcp.c - tcp.c - 0 - 0 - - - 8 - 97 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/tcp_in.c - tcp_in.c - 0 - 0 - - - 8 - 98 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/tcp_out.c - tcp_out.c - 0 - 0 - - - 8 - 99 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/timers.c - timers.c - 0 - 0 - - - 8 - 100 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/udp.c - udp.c - 0 - 0 - - - 8 - 101 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c - autoip.c - 0 - 0 - - - 8 - 102 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c - icmp.c - 0 - 0 - - - 8 - 103 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c - igmp.c - 0 - 0 - - - 8 - 104 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c - inet.c - 0 - 0 - - - 8 - 105 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c - inet_chksum.c - 0 - 0 - - - 8 - 106 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c - ip.c - 0 - 0 - - - 8 - 107 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c - ip_addr.c - 0 - 0 - - - 8 - 108 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c - ip_frag.c - 0 - 0 - - - 8 - 109 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/netif/etharp.c - etharp.c - 0 - 0 - - - 8 - 110 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/netif/ethernetif.c - ethernetif.c - 0 - 0 - - - 8 - 111 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/netif/slipif.c - slipif.c - 0 - 0 - - - - diff --git a/bsp/tm4c129x-dk/project.uvproj b/bsp/tm4c129x-dk/project.uvproj deleted file mode 100644 index ce7d9b3c95d8fadcadf08e8c9f7e03b5150be7a4..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/project.uvproj +++ /dev/null @@ -1,1210 +0,0 @@ - - - 1.1 -
### uVision Project, (C) Keil Software
- - - RT-Thread TM4C129X - 0x4 - ARM-ADS - - - TM4C1294NCPDT - Texas Instruments - Keil.TM4C_DFP.1.0.0 - http://www.keil.com/pack/ - IROM(0x00000000,0x100000) IRAM(0x20000000,0x040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(120000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C129_1024 -FS00 -FL0100000 -FP0($$Device:TM4C1294NCPDT$Flash\TM4C129_1024.FLM)) - 7088 - $$Device:TM4C1294NCPDT$Device\Include\TM4C129\TM4C129.h - - - - - - - -DTM4C1294NCPDT - - - $$Device:TM4C1294NCPDT$SVD\TM4C129\TM4C1294NCPDT.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-tm4c - 1 - 0 - 0 - 1 - 1 - .\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x40000 - - - 1 - 0x0 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x100000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x40000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - - - PART_TM4C129XNCZAD - - libraries;libraries/inc;libraries/driverlib;drivers;applications;.;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/net/lwip-1.4.1/src/include;../../components/net/lwip-1.4.1/src/include/ipv4;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/netif - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x00000000 - - tm4c_rom.sct - - - --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - - - - - - - Libraries - - - adc.c - 1 - libraries/driverlib/adc.c - - - - - aes.c - 1 - libraries/driverlib/aes.c - - - - - can.c - 1 - libraries/driverlib/can.c - - - - - comp.c - 1 - libraries/driverlib/comp.c - - - - - cpu.c - 1 - libraries/driverlib/cpu.c - - - - - crc.c - 1 - libraries/driverlib/crc.c - - - - - des.c - 1 - libraries/driverlib/des.c - - - - - eeprom.c - 1 - libraries/driverlib/eeprom.c - - - - - emac.c - 1 - libraries/driverlib/emac.c - - - - - epi.c - 1 - libraries/driverlib/epi.c - - - - - flash.c - 1 - libraries/driverlib/flash.c - - - - - fpu.c - 1 - libraries/driverlib/fpu.c - - - - - gpio.c - 1 - libraries/driverlib/gpio.c - - - - - hibernate.c - 1 - libraries/driverlib/hibernate.c - - - - - i2c.c - 1 - libraries/driverlib/i2c.c - - - - - interrupt.c - 1 - libraries/driverlib/interrupt.c - - - - - lcd.c - 1 - libraries/driverlib/lcd.c - - - - - mpu.c - 1 - libraries/driverlib/mpu.c - - - - - pwm.c - 1 - libraries/driverlib/pwm.c - - - - - qei.c - 1 - libraries/driverlib/qei.c - - - - - shamd5.c - 1 - libraries/driverlib/shamd5.c - - - - - ssi.c - 1 - libraries/driverlib/ssi.c - - - - - sw_crc.c - 1 - libraries/driverlib/sw_crc.c - - - - - sysctl.c - 1 - libraries/driverlib/sysctl.c - - - - - sysexc.c - 1 - libraries/driverlib/sysexc.c - - - - - systick.c - 1 - libraries/driverlib/systick.c - - - - - tiva_timer.c - 1 - libraries/driverlib/tiva_timer.c - - - - - uart.c - 1 - libraries/driverlib/uart.c - - - - - udma.c - 1 - libraries/driverlib/udma.c - - - - - usb.c - 1 - libraries/driverlib/usb.c - - - - - watchdog.c - 1 - libraries/driverlib/watchdog.c - - - - - startup_rvmdk.S - 2 - libraries/startup/startup_rvmdk.S - - - - - Drivers - - - drv_eth.c - 1 - drivers/drv_eth.c - - - - - drv_uart.c - 1 - drivers/drv_uart.c - - - - - Applications - - - application.c - 1 - applications/application.c - - - - - board.c - 1 - applications/board.c - - - - - Kernel - - - clock.c - 1 - ../../src/clock.c - - - - - components.c - 1 - ../../src/components.c - - - - - device.c - 1 - ../../src/device.c - - - - - idle.c - 1 - ../../src/idle.c - - - - - ipc.c - 1 - ../../src/ipc.c - - - - - irq.c - 1 - ../../src/irq.c - - - - - kservice.c - 1 - ../../src/kservice.c - - - - - mem.c - 1 - ../../src/mem.c - - - - - memheap.c - 1 - ../../src/memheap.c - - - - - mempool.c - 1 - ../../src/mempool.c - - - - - object.c - 1 - ../../src/object.c - - - - - scheduler.c - 1 - ../../src/scheduler.c - - - - - signal.c - 1 - ../../src/signal.c - - - - - thread.c - 1 - ../../src/thread.c - - - - - timer.c - 1 - ../../src/timer.c - - - - - CORTEX-M4 - - - cpuport.c - 1 - ../../libcpu/arm/cortex-m4/cpuport.c - - - - - context_rvds.S - 2 - ../../libcpu/arm/cortex-m4/context_rvds.S - - - - - backtrace.c - 1 - ../../libcpu/arm/common/backtrace.c - - - - - div0.c - 1 - ../../libcpu/arm/common/div0.c - - - - - showmem.c - 1 - ../../libcpu/arm/common/showmem.c - - - - - DeviceDrivers - - - serial.c - 1 - ../../components/drivers/serial/serial.c - - - - - completion.c - 1 - ../../components/drivers/src/completion.c - - - - - dataqueue.c - 1 - ../../components/drivers/src/dataqueue.c - - - - - pipe.c - 1 - ../../components/drivers/src/pipe.c - - - - - ringbuffer.c - 1 - ../../components/drivers/src/ringbuffer.c - - - - - waitqueue.c - 1 - ../../components/drivers/src/waitqueue.c - - - - - workqueue.c - 1 - ../../components/drivers/src/workqueue.c - - - - - finsh - - - shell.c - 1 - ../../components/finsh/shell.c - - - - - symbol.c - 1 - ../../components/finsh/symbol.c - - - - - cmd.c - 1 - ../../components/finsh/cmd.c - - - - - finsh_compiler.c - 1 - ../../components/finsh/finsh_compiler.c - - - - - finsh_error.c - 1 - ../../components/finsh/finsh_error.c - - - - - finsh_heap.c - 1 - ../../components/finsh/finsh_heap.c - - - - - finsh_init.c - 1 - ../../components/finsh/finsh_init.c - - - - - finsh_node.c - 1 - ../../components/finsh/finsh_node.c - - - - - finsh_ops.c - 1 - ../../components/finsh/finsh_ops.c - - - - - finsh_parser.c - 1 - ../../components/finsh/finsh_parser.c - - - - - finsh_var.c - 1 - ../../components/finsh/finsh_var.c - - - - - finsh_vm.c - 1 - ../../components/finsh/finsh_vm.c - - - - - finsh_token.c - 1 - ../../components/finsh/finsh_token.c - - - - - LwIP - - - api_lib.c - 1 - ../../components/net/lwip-1.4.1/src/api/api_lib.c - - - - - api_msg.c - 1 - ../../components/net/lwip-1.4.1/src/api/api_msg.c - - - - - err.c - 1 - ../../components/net/lwip-1.4.1/src/api/err.c - - - - - netbuf.c - 1 - ../../components/net/lwip-1.4.1/src/api/netbuf.c - - - - - netdb.c - 1 - ../../components/net/lwip-1.4.1/src/api/netdb.c - - - - - netifapi.c - 1 - ../../components/net/lwip-1.4.1/src/api/netifapi.c - - - - - sockets.c - 1 - ../../components/net/lwip-1.4.1/src/api/sockets.c - - - - - tcpip.c - 1 - ../../components/net/lwip-1.4.1/src/api/tcpip.c - - - - - sys_arch.c - 1 - ../../components/net/lwip-1.4.1/src/arch/sys_arch.c - - - - - def.c - 1 - ../../components/net/lwip-1.4.1/src/core/def.c - - - - - dhcp.c - 1 - ../../components/net/lwip-1.4.1/src/core/dhcp.c - - - - - dns.c - 1 - ../../components/net/lwip-1.4.1/src/core/dns.c - - - - - init.c - 1 - ../../components/net/lwip-1.4.1/src/core/init.c - - - - - memp.c - 1 - ../../components/net/lwip-1.4.1/src/core/memp.c - - - - - netif.c - 1 - ../../components/net/lwip-1.4.1/src/core/netif.c - - - - - pbuf.c - 1 - ../../components/net/lwip-1.4.1/src/core/pbuf.c - - - - - raw.c - 1 - ../../components/net/lwip-1.4.1/src/core/raw.c - - - - - stats.c - 1 - ../../components/net/lwip-1.4.1/src/core/stats.c - - - - - sys.c - 1 - ../../components/net/lwip-1.4.1/src/core/sys.c - - - - - tcp.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp.c - - - - - tcp_in.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp_in.c - - - - - tcp_out.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp_out.c - - - - - timers.c - 1 - ../../components/net/lwip-1.4.1/src/core/timers.c - - - - - udp.c - 1 - ../../components/net/lwip-1.4.1/src/core/udp.c - - - - - autoip.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c - - - - - icmp.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c - - - - - igmp.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c - - - - - inet.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c - - - - - inet_chksum.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c - - - - - ip.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c - - - - - ip_addr.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c - - - - - ip_frag.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c - - - - - etharp.c - 1 - ../../components/net/lwip-1.4.1/src/netif/etharp.c - - - - - ethernetif.c - 1 - ../../components/net/lwip-1.4.1/src/netif/ethernetif.c - - - - - slipif.c - 1 - ../../components/net/lwip-1.4.1/src/netif/slipif.c - - - - - - - diff --git a/bsp/tm4c129x-dk/project.uvprojx b/bsp/tm4c129x-dk/project.uvprojx deleted file mode 100644 index 4e3387f6be4d4df34d789c938467abd3857bfb79..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/project.uvprojx +++ /dev/null @@ -1,978 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - RT-Thread TM4C129X - 0x4 - ARM-ADS - 5060300::V5.06 update 3 (build 300)::ARMCC - - - TM4C129XNCZAD - Texas Instruments - Keil.TM4C_DFP.1.1.0 - http://www.keil.com/pack/ - IRAM(0x20000000,0x040000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C129_1024 -FS00 -FL0100000 -FP0($$Device:TM4C129XNCZAD$Flash\TM4C129_1024.FLM)) - 0 - $$Device:TM4C129XNCZAD$Device\Include\TM4C129\TM4C129.h - - - - - - - - - - $$Device:TM4C129XNCZAD$SVD\TM4C129\TM4C129XNCZAD.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-tm4c - 1 - 0 - 0 - 1 - 1 - .\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x40000 - - - 1 - 0x0 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x100000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x40000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - PART_TM4C129XNCZAD - - libraries;libraries/inc;libraries/driverlib;drivers;applications;.;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/net/lwip-1.4.1/src/include;../../components/net/lwip-1.4.1/src/include/ipv4;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/netif - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x00000000 - - tm4c_rom.sct - - - --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - - - - - - - Libraries - - - adc.c - 1 - libraries/driverlib/adc.c - - - aes.c - 1 - libraries/driverlib/aes.c - - - can.c - 1 - libraries/driverlib/can.c - - - comp.c - 1 - libraries/driverlib/comp.c - - - cpu.c - 1 - libraries/driverlib/cpu.c - - - crc.c - 1 - libraries/driverlib/crc.c - - - des.c - 1 - libraries/driverlib/des.c - - - eeprom.c - 1 - libraries/driverlib/eeprom.c - - - emac.c - 1 - libraries/driverlib/emac.c - - - epi.c - 1 - libraries/driverlib/epi.c - - - flash.c - 1 - libraries/driverlib/flash.c - - - fpu.c - 1 - libraries/driverlib/fpu.c - - - gpio.c - 1 - libraries/driverlib/gpio.c - - - hibernate.c - 1 - libraries/driverlib/hibernate.c - - - i2c.c - 1 - libraries/driverlib/i2c.c - - - interrupt.c - 1 - libraries/driverlib/interrupt.c - - - lcd.c - 1 - libraries/driverlib/lcd.c - - - mpu.c - 1 - libraries/driverlib/mpu.c - - - pwm.c - 1 - libraries/driverlib/pwm.c - - - qei.c - 1 - libraries/driverlib/qei.c - - - shamd5.c - 1 - libraries/driverlib/shamd5.c - - - ssi.c - 1 - libraries/driverlib/ssi.c - - - sw_crc.c - 1 - libraries/driverlib/sw_crc.c - - - sysctl.c - 1 - libraries/driverlib/sysctl.c - - - sysexc.c - 1 - libraries/driverlib/sysexc.c - - - systick.c - 1 - libraries/driverlib/systick.c - - - tiva_timer.c - 1 - libraries/driverlib/tiva_timer.c - - - uart.c - 1 - libraries/driverlib/uart.c - - - udma.c - 1 - libraries/driverlib/udma.c - - - usb.c - 1 - libraries/driverlib/usb.c - - - watchdog.c - 1 - libraries/driverlib/watchdog.c - - - startup_rvmdk.S - 2 - libraries/startup/startup_rvmdk.S - - - - - Drivers - - - drv_eth.c - 1 - drivers/drv_eth.c - - - drv_uart.c - 1 - drivers/drv_uart.c - - - - - Applications - - - application.c - 1 - applications/application.c - - - board.c - 1 - applications/board.c - - - - - Kernel - - - clock.c - 1 - ../../src/clock.c - - - components.c - 1 - ../../src/components.c - - - device.c - 1 - ../../src/device.c - - - idle.c - 1 - ../../src/idle.c - - - ipc.c - 1 - ../../src/ipc.c - - - irq.c - 1 - ../../src/irq.c - - - kservice.c - 1 - ../../src/kservice.c - - - mem.c - 1 - ../../src/mem.c - - - memheap.c - 1 - ../../src/memheap.c - - - mempool.c - 1 - ../../src/mempool.c - - - object.c - 1 - ../../src/object.c - - - scheduler.c - 1 - ../../src/scheduler.c - - - signal.c - 1 - ../../src/signal.c - - - thread.c - 1 - ../../src/thread.c - - - timer.c - 1 - ../../src/timer.c - - - - - CORTEX-M4 - - - cpuport.c - 1 - ../../libcpu/arm/cortex-m4/cpuport.c - - - context_rvds.S - 2 - ../../libcpu/arm/cortex-m4/context_rvds.S - - - backtrace.c - 1 - ../../libcpu/arm/common/backtrace.c - - - div0.c - 1 - ../../libcpu/arm/common/div0.c - - - showmem.c - 1 - ../../libcpu/arm/common/showmem.c - - - - - DeviceDrivers - - - serial.c - 1 - ../../components/drivers/serial/serial.c - - - completion.c - 1 - ../../components/drivers/src/completion.c - - - dataqueue.c - 1 - ../../components/drivers/src/dataqueue.c - - - pipe.c - 1 - ../../components/drivers/src/pipe.c - - - ringbuffer.c - 1 - ../../components/drivers/src/ringbuffer.c - - - waitqueue.c - 1 - ../../components/drivers/src/waitqueue.c - - - workqueue.c - 1 - ../../components/drivers/src/workqueue.c - - - - - finsh - - - shell.c - 1 - ../../components/finsh/shell.c - - - symbol.c - 1 - ../../components/finsh/symbol.c - - - cmd.c - 1 - ../../components/finsh/cmd.c - - - finsh_compiler.c - 1 - ../../components/finsh/finsh_compiler.c - - - finsh_error.c - 1 - ../../components/finsh/finsh_error.c - - - finsh_heap.c - 1 - ../../components/finsh/finsh_heap.c - - - finsh_init.c - 1 - ../../components/finsh/finsh_init.c - - - finsh_node.c - 1 - ../../components/finsh/finsh_node.c - - - finsh_ops.c - 1 - ../../components/finsh/finsh_ops.c - - - finsh_parser.c - 1 - ../../components/finsh/finsh_parser.c - - - finsh_var.c - 1 - ../../components/finsh/finsh_var.c - - - finsh_vm.c - 1 - ../../components/finsh/finsh_vm.c - - - finsh_token.c - 1 - ../../components/finsh/finsh_token.c - - - - - LwIP - - - api_lib.c - 1 - ../../components/net/lwip-1.4.1/src/api/api_lib.c - - - api_msg.c - 1 - ../../components/net/lwip-1.4.1/src/api/api_msg.c - - - err.c - 1 - ../../components/net/lwip-1.4.1/src/api/err.c - - - netbuf.c - 1 - ../../components/net/lwip-1.4.1/src/api/netbuf.c - - - netdb.c - 1 - ../../components/net/lwip-1.4.1/src/api/netdb.c - - - netifapi.c - 1 - ../../components/net/lwip-1.4.1/src/api/netifapi.c - - - sockets.c - 1 - ../../components/net/lwip-1.4.1/src/api/sockets.c - - - tcpip.c - 1 - ../../components/net/lwip-1.4.1/src/api/tcpip.c - - - sys_arch.c - 1 - ../../components/net/lwip-1.4.1/src/arch/sys_arch.c - - - def.c - 1 - ../../components/net/lwip-1.4.1/src/core/def.c - - - dhcp.c - 1 - ../../components/net/lwip-1.4.1/src/core/dhcp.c - - - dns.c - 1 - ../../components/net/lwip-1.4.1/src/core/dns.c - - - init.c - 1 - ../../components/net/lwip-1.4.1/src/core/init.c - - - memp.c - 1 - ../../components/net/lwip-1.4.1/src/core/memp.c - - - netif.c - 1 - ../../components/net/lwip-1.4.1/src/core/netif.c - - - pbuf.c - 1 - ../../components/net/lwip-1.4.1/src/core/pbuf.c - - - raw.c - 1 - ../../components/net/lwip-1.4.1/src/core/raw.c - - - stats.c - 1 - ../../components/net/lwip-1.4.1/src/core/stats.c - - - sys.c - 1 - ../../components/net/lwip-1.4.1/src/core/sys.c - - - tcp.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp.c - - - tcp_in.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp_in.c - - - tcp_out.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp_out.c - - - timers.c - 1 - ../../components/net/lwip-1.4.1/src/core/timers.c - - - udp.c - 1 - ../../components/net/lwip-1.4.1/src/core/udp.c - - - autoip.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c - - - icmp.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c - - - igmp.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c - - - inet.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c - - - inet_chksum.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c - - - ip.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c - - - ip_addr.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c - - - ip_frag.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c - - - etharp.c - 1 - ../../components/net/lwip-1.4.1/src/netif/etharp.c - - - ethernetif.c - 1 - ../../components/net/lwip-1.4.1/src/netif/ethernetif.c - - - slipif.c - 1 - ../../components/net/lwip-1.4.1/src/netif/slipif.c - - - - - - - - diff --git a/bsp/tm4c129x-dk/rtconfig.h b/bsp/tm4c129x-dk/rtconfig.h deleted file mode 100644 index d9e6e561c901169a0594b1bb6c78805cd8d0133b..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/rtconfig.h +++ /dev/null @@ -1,194 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_DEBUG -#define RT_USING_OVERFLOW_CHECK -#define RT_DEBUG_INIT 0 -/* RT_DEBUG_THREAD is not set */ -#define RT_USING_HOOK -#define IDLE_THREAD_STACK_SIZE 256 -#define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_MEMHEAP -#define RT_USING_HEAP -#define RT_USING_SMALL_MEM -/* RT_USING_SLAB is not set */ - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart0" -/* RT_USING_MODULE is not set */ - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN - -/* C++ features */ - -/* RT_USING_CPLUSPLUS is not set */ - -/* Command shell */ - -#define RT_USING_FINSH -#define FINSH_USING_HISTORY -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ -/* FINSH_USING_MSH is not set */ - -/* Device virtual file system */ - -/* RT_USING_DFS is not set */ - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_USING_SERIAL -/* RT_USING_CAN is not set */ -/* RT_USING_HWTIMER is not set */ -/* RT_USING_I2C is not set */ -/* RT_USING_PIN is not set */ -/* RT_USING_MTD_NOR is not set */ -/* RT_USING_MTD_NAND is not set */ -/* RT_USING_RTC is not set */ -/* RT_USING_SDIO is not set */ -/* RT_USING_SPI is not set */ -/* RT_USING_WDT is not set */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ - -/* POSIX layer and C standard library */ - -/* RT_USING_LIBC is not set */ -/* RT_USING_PTHREADS is not set */ - -/* Network stack */ - -/* light weight TCP/IP stack */ - -#define RT_USING_LWIP -#define RT_USING_LWIP141 -/* RT_USING_LWIP202 is not set */ -/* RT_LWIP_IGMP is not set */ -#define RT_LWIP_ICMP -/* RT_LWIP_SNMP is not set */ -#define RT_LWIP_DNS -#define RT_LWIP_DHCP -#define IP_SOF_BROADCAST 1 -#define IP_SOF_BROADCAST_RECV 1 -/* LWIP_USING_DHCPD is not set */ - -/* Static IPv4 Address */ - -#define RT_LWIP_IPADDR "192.168.1.30" -#define RT_LWIP_GWADDR "192.168.1.1" -#define RT_LWIP_MSKADDR "255.255.255.0" -#define RT_LWIP_UDP -#define RT_LWIP_TCP -/* RT_LWIP_RAW is not set */ -/* RT_LWIP_PPP is not set */ -/* RT_LWIP_PPPOE is not set */ -/* RT_LWIP_PPPOS is not set */ -#define RT_LWIP_PBUF_NUM 16 -#define RT_LWIP_RAW_PCB_NUM 4 -#define RT_LWIP_UDP_PCB_NUM 4 -#define RT_LWIP_TCP_PCB_NUM 4 -#define RT_LWIP_TCP_SEG_NUM 40 -#define RT_LWIP_TCP_SND_BUF 8196 -#define RT_LWIP_TCP_WND 8196 -#define RT_LWIP_TCPTHREAD_PRIORITY 10 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_PRIORITY 12 -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 -/* RT_LWIP_REASSEMBLY_FRAG is not set */ -#define LWIP_NETIF_STATUS_CALLBACK 1 -#define SO_REUSE 1 -#define LWIP_SO_RCVTIMEO 1 -#define LWIP_SO_SNDTIMEO 1 -#define LWIP_SO_RCVBUF 1 - -/* Modbus master and slave stack */ - -/* RT_USING_MODBUS is not set */ -/* RT_USING_NETUTILS is not set */ - -/* RT-Thread UI Engine */ - -/* PKG_USING_GUIENGINE is not set */ - -/* RT-Thread online packages */ - -/* system packages */ - -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_SQLITE is not set */ - -/* IoT - internet of things */ - -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_EZXML is not set */ - -/* Marvell WiFi */ - -/* PKG_USING_MARVELLWIFI is not set */ - -/* security packages */ - -/* PKG_USING_MBEDTLS is not set */ - -/* language packages */ - -/* PKG_USING_JERRYSCRIPT is not set */ - -/* multimedia packages */ - -/* tools packages */ - -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYLOGGER is not set */ - -/* miscellaneous packages */ - -/* PKG_USING_HELLO is not set */ - -/* BSP_SPECIAL CONFIG */ - -#define RT_USING_UART0 - -#endif diff --git a/bsp/tm4c129x-dk/rtconfig.py b/bsp/tm4c129x-dk/rtconfig.py deleted file mode 100644 index 8db01c509b8973742f1964146e2a4cd50b263fe7..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/rtconfig.py +++ /dev/null @@ -1,133 +0,0 @@ -# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad (REV D) - -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='keil' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -#device options -PART_TYPE = 'PART_TM4C129XNCZAD' -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:\ArdaArmTools\Sourcery_Lite\bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:\Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -#BUILD = 'debug' -BUILD = 'release' - -if PLATFORM == 'gcc': - # tool-chains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -std=c99 -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-tm4c129x.map,-cref,-u,Reset_Handler -T tm4c_rom.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter tm4c_rom.sct --info sizes --info totals --info unused --info veneers --list rtthread-tm4c129x.map --strict' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/LIB' - - EXEC_PATH += '/arm/armcc/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' # + ' -D' + PART_TYPE - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu VFPv4_sp' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "tm4c_rom.icf"' - LFLAGS += ' --entry __iar_program_start' - #LFLAGS += ' --silent' - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = '' \ No newline at end of file diff --git a/bsp/tm4c129x-dk/startup_rvmdk.lst b/bsp/tm4c129x-dk/startup_rvmdk.lst deleted file mode 100644 index 748d55a117899a4a4ca060363cd5f97ec0ecaaa8..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/startup_rvmdk.lst +++ /dev/null @@ -1,890 +0,0 @@ - - - -ARM Macro Assembler Page 1 - - - 1 00000000 ; <<< Use Configuration Wizard in Context Menu >>> - 2 00000000 ;******************************************************* - *********************** - 3 00000000 ; - 4 00000000 ; startup_rvmdk.S - Startup code for use with Keil's uVi - sion. - 5 00000000 ; - 6 00000000 ; Copyright (c) 2013-2017 Texas Instruments Incorporated - . All rights reserved. - 7 00000000 ; Software License Agreement - 8 00000000 ; - 9 00000000 ; Texas Instruments (TI) is supplying this software for - use solely and - 10 00000000 ; exclusively on TI's microcontroller products. The soft - ware is owned by - 11 00000000 ; TI and/or its suppliers, and is protected under applic - able copyright - 12 00000000 ; laws. You may not combine this software with "viral" o - pen-source - 13 00000000 ; software in order to form a larger program. - 14 00000000 ; - 15 00000000 ; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. - - 16 00000000 ; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - INCLUDING, BUT - 17 00000000 ; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY - AND FITNESS FOR - 18 00000000 ; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL - NOT, UNDER ANY - 19 00000000 ; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR C - ONSEQUENTIAL - 20 00000000 ; DAMAGES, FOR ANY REASON WHATSOEVER. - 21 00000000 ; - 22 00000000 ; This is part of revision 2.1.4.178 of the DK-TM4C129X - Firmware Package. - 23 00000000 ; - 24 00000000 ;******************************************************* - *********************** - 25 00000000 - 26 00000000 ;******************************************************* - *********************** - 27 00000000 ; - 28 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - 29 00000000 ; - 30 00000000 ;******************************************************* - *********************** - 31 00000000 00000200 - Stack EQU 0x00000200 - 32 00000000 - 33 00000000 ;******************************************************* - *********************** - 34 00000000 ; - 35 00000000 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - 36 00000000 ; - 37 00000000 ;******************************************************* - *********************** - 38 00000000 00000000 - Heap EQU 0x00000000 - 39 00000000 - - - -ARM Macro Assembler Page 2 - - - 40 00000000 ;******************************************************* - *********************** - 41 00000000 ; - 42 00000000 ; Allocate space for the stack. - 43 00000000 ; - 44 00000000 ;******************************************************* - *********************** - 45 00000000 AREA STACK, NOINIT, READWRITE, ALIGN -=3 - 46 00000000 StackMem - 47 00000000 SPACE Stack - 48 00000200 __initial_sp - 49 00000200 - 50 00000200 ;******************************************************* - *********************** - 51 00000200 ; - 52 00000200 ; Allocate space for the heap. - 53 00000200 ; - 54 00000200 ;******************************************************* - *********************** - 55 00000200 AREA HEAP, NOINIT, READWRITE, ALIGN= -3 - 56 00000000 __heap_base - 57 00000000 HeapMem - 58 00000000 SPACE Heap - 59 00000000 __heap_limit - 60 00000000 - 61 00000000 ;******************************************************* - *********************** - 62 00000000 ; - 63 00000000 ; Indicate that the code in this file preserves 8-byte a - lignment of the stack. - 64 00000000 ; - 65 00000000 ;******************************************************* - *********************** - 66 00000000 PRESERVE8 - 67 00000000 - 68 00000000 ;******************************************************* - *********************** - 69 00000000 ; - 70 00000000 ; Place code into the reset code section. - 71 00000000 ; - 72 00000000 ;******************************************************* - *********************** - 73 00000000 AREA RESET, CODE, READONLY - 74 00000000 THUMB - 75 00000000 - 76 00000000 ;******************************************************* - *********************** - 77 00000000 ; - 78 00000000 ; The vector table. - 79 00000000 ; - 80 00000000 ;******************************************************* - *********************** - 81 00000000 EXPORT __Vectors - 82 00000000 __Vectors - 83 00000000 00000200 DCD StackMem + Stack ; Top of Stack - - 84 00000004 00000000 DCD Reset_Handler ; Reset Handler - - - -ARM Macro Assembler Page 3 - - - 85 00000008 00000000 DCD NmiSR ; NMI Handler - 86 0000000C 00000000 DCD FaultISR ; Hard Fault Handle - r - 87 00000010 00000000 DCD IntDefaultHandler ; The MPU fau - lt handler - 88 00000014 00000000 DCD IntDefaultHandler ; The bus fau - lt handler - 89 00000018 00000000 DCD IntDefaultHandler ; The usage f - ault handler - 90 0000001C 00000000 DCD 0 ; Reserved - 91 00000020 00000000 DCD 0 ; Reserved - 92 00000024 00000000 DCD 0 ; Reserved - 93 00000028 00000000 DCD 0 ; Reserved - 94 0000002C 00000000 DCD IntDefaultHandler - ; SVCall handler - 95 00000030 00000000 DCD IntDefaultHandler ; Debug monit - or handler - 96 00000034 00000000 DCD 0 ; Reserved - 97 00000038 00000000 DCD IntDefaultHandler ; The PendSV - handler - 98 0000003C 00000000 DCD IntDefaultHandler ; The SysTick - handler - 99 00000040 00000000 DCD IntDefaultHandler ; GPIO Port A - - 100 00000044 00000000 DCD IntDefaultHandler ; GPIO Port B - - 101 00000048 00000000 DCD IntDefaultHandler ; GPIO Port C - - 102 0000004C 00000000 DCD IntDefaultHandler ; GPIO Port D - - 103 00000050 00000000 DCD IntDefaultHandler ; GPIO Port E - - 104 00000054 00000000 DCD IntDefaultHandler - ; UART0 Rx and Tx - 105 00000058 00000000 DCD IntDefaultHandler - ; UART1 Rx and Tx - 106 0000005C 00000000 DCD IntDefaultHandler - ; SSI0 Rx and Tx - 107 00000060 00000000 DCD IntDefaultHandler ; I2C0 Master - and Slave - 108 00000064 00000000 DCD IntDefaultHandler ; PWM Fault - 109 00000068 00000000 DCD IntDefaultHandler - ; PWM Generator 0 - 110 0000006C 00000000 DCD IntDefaultHandler - ; PWM Generator 1 - 111 00000070 00000000 DCD IntDefaultHandler - ; PWM Generator 2 - 112 00000074 00000000 DCD IntDefaultHandler ; Quadrature - Encoder 0 - 113 00000078 00000000 DCD IntDefaultHandler - ; ADC Sequence 0 - 114 0000007C 00000000 DCD IntDefaultHandler - ; ADC Sequence 1 - 115 00000080 00000000 DCD IntDefaultHandler - ; ADC Sequence 2 - 116 00000084 00000000 DCD IntDefaultHandler - ; ADC Sequence 3 - 117 00000088 00000000 DCD IntDefaultHandler - ; Watchdog timer - - - -ARM Macro Assembler Page 4 - - - 118 0000008C 00000000 DCD IntDefaultHandler ; Timer 0 sub - timer A - 119 00000090 00000000 DCD IntDefaultHandler ; Timer 0 sub - timer B - 120 00000094 00000000 DCD IntDefaultHandler ; Timer 1 sub - timer A - 121 00000098 00000000 DCD IntDefaultHandler ; Timer 1 sub - timer B - 122 0000009C 00000000 DCD IntDefaultHandler ; Timer 2 sub - timer A - 123 000000A0 00000000 DCD IntDefaultHandler ; Timer 2 sub - timer B - 124 000000A4 00000000 DCD IntDefaultHandler ; Analog Comp - arator 0 - 125 000000A8 00000000 DCD IntDefaultHandler ; Analog Comp - arator 1 - 126 000000AC 00000000 DCD IntDefaultHandler ; Analog Comp - arator 2 - 127 000000B0 00000000 DCD IntDefaultHandler ; System Cont - rol (PLL, OSC, BO) - 128 000000B4 00000000 DCD IntDefaultHandler - ; FLASH Control - 129 000000B8 00000000 DCD IntDefaultHandler ; GPIO Port F - - 130 000000BC 00000000 DCD IntDefaultHandler ; GPIO Port G - - 131 000000C0 00000000 DCD IntDefaultHandler ; GPIO Port H - - 132 000000C4 00000000 DCD IntDefaultHandler - ; UART2 Rx and Tx - 133 000000C8 00000000 DCD IntDefaultHandler - ; SSI1 Rx and Tx - 134 000000CC 00000000 DCD IntDefaultHandler ; Timer 3 sub - timer A - 135 000000D0 00000000 DCD IntDefaultHandler ; Timer 3 sub - timer B - 136 000000D4 00000000 DCD IntDefaultHandler ; I2C1 Master - and Slave - 137 000000D8 00000000 DCD IntDefaultHandler ; CAN0 - 138 000000DC 00000000 DCD IntDefaultHandler ; CAN1 - 139 000000E0 00000000 DCD IntDefaultHandler ; Ethernet - 140 000000E4 00000000 DCD IntDefaultHandler ; Hibernate - 141 000000E8 00000000 DCD IntDefaultHandler ; USB0 - 142 000000EC 00000000 DCD IntDefaultHandler - ; PWM Generator 3 - 143 000000F0 00000000 DCD IntDefaultHandler ; uDMA Softwa - re Transfer - 144 000000F4 00000000 DCD IntDefaultHandler ; uDMA Error - 145 000000F8 00000000 DCD IntDefaultHandler - ; ADC1 Sequence 0 - 146 000000FC 00000000 DCD IntDefaultHandler - ; ADC1 Sequence 1 - 147 00000100 00000000 DCD IntDefaultHandler - ; ADC1 Sequence 2 - 148 00000104 00000000 DCD IntDefaultHandler - ; ADC1 Sequence 3 - 149 00000108 00000000 DCD IntDefaultHandler ; External Bu - s Interface 0 - 150 0000010C 00000000 DCD IntDefaultHandler ; GPIO Port J - - - -ARM Macro Assembler Page 5 - - - - 151 00000110 00000000 DCD IntDefaultHandler ; GPIO Port K - - 152 00000114 00000000 DCD IntDefaultHandler ; GPIO Port L - - 153 00000118 00000000 DCD IntDefaultHandler - ; SSI2 Rx and Tx - 154 0000011C 00000000 DCD IntDefaultHandler - ; SSI3 Rx and Tx - 155 00000120 00000000 DCD IntDefaultHandler - ; UART3 Rx and Tx - 156 00000124 00000000 DCD IntDefaultHandler - ; UART4 Rx and Tx - 157 00000128 00000000 DCD IntDefaultHandler - ; UART5 Rx and Tx - 158 0000012C 00000000 DCD IntDefaultHandler - ; UART6 Rx and Tx - 159 00000130 00000000 DCD IntDefaultHandler - ; UART7 Rx and Tx - 160 00000134 00000000 DCD IntDefaultHandler ; I2C2 Master - and Slave - 161 00000138 00000000 DCD IntDefaultHandler ; I2C3 Master - and Slave - 162 0000013C 00000000 DCD IntDefaultHandler ; Timer 4 sub - timer A - 163 00000140 00000000 DCD IntDefaultHandler ; Timer 4 sub - timer B - 164 00000144 00000000 DCD IntDefaultHandler ; Timer 5 sub - timer A - 165 00000148 00000000 DCD IntDefaultHandler ; Timer 5 sub - timer B - 166 0000014C 00000000 DCD IntDefaultHandler ; FPU - 167 00000150 00000000 DCD 0 ; Reserved - 168 00000154 00000000 DCD 0 ; Reserved - 169 00000158 00000000 DCD IntDefaultHandler ; I2C4 Master - and Slave - 170 0000015C 00000000 DCD IntDefaultHandler ; I2C5 Master - and Slave - 171 00000160 00000000 DCD IntDefaultHandler ; GPIO Port M - - 172 00000164 00000000 DCD IntDefaultHandler ; GPIO Port N - - 173 00000168 00000000 DCD 0 ; Reserved - 174 0000016C 00000000 DCD IntDefaultHandler ; Tamper - 175 00000170 00000000 DCD IntDefaultHandler ; GPIO Port P - (Summary or P0) - 176 00000174 00000000 DCD IntDefaultHandler - ; GPIO Port P1 - 177 00000178 00000000 DCD IntDefaultHandler - ; GPIO Port P2 - 178 0000017C 00000000 DCD IntDefaultHandler - ; GPIO Port P3 - 179 00000180 00000000 DCD IntDefaultHandler - ; GPIO Port P4 - 180 00000184 00000000 DCD IntDefaultHandler - ; GPIO Port P5 - 181 00000188 00000000 DCD IntDefaultHandler - ; GPIO Port P6 - 182 0000018C 00000000 DCD IntDefaultHandler - - - -ARM Macro Assembler Page 6 - - - ; GPIO Port P7 - 183 00000190 00000000 DCD IntDefaultHandler ; GPIO Port Q - (Summary or Q0) - 184 00000194 00000000 DCD IntDefaultHandler - ; GPIO Port Q1 - 185 00000198 00000000 DCD IntDefaultHandler - ; GPIO Port Q2 - 186 0000019C 00000000 DCD IntDefaultHandler - ; GPIO Port Q3 - 187 000001A0 00000000 DCD IntDefaultHandler - ; GPIO Port Q4 - 188 000001A4 00000000 DCD IntDefaultHandler - ; GPIO Port Q5 - 189 000001A8 00000000 DCD IntDefaultHandler - ; GPIO Port Q6 - 190 000001AC 00000000 DCD IntDefaultHandler - ; GPIO Port Q7 - 191 000001B0 00000000 DCD IntDefaultHandler ; GPIO Port R - - 192 000001B4 00000000 DCD IntDefaultHandler ; GPIO Port S - - 193 000001B8 00000000 DCD IntDefaultHandler ; SHA/MD5 0 - 194 000001BC 00000000 DCD IntDefaultHandler ; AES 0 - 195 000001C0 00000000 DCD IntDefaultHandler ; DES3DES 0 - 196 000001C4 00000000 DCD IntDefaultHandler - ; LCD Controller 0 - 197 000001C8 00000000 DCD IntDefaultHandler ; Timer 6 sub - timer A - 198 000001CC 00000000 DCD IntDefaultHandler ; Timer 6 sub - timer B - 199 000001D0 00000000 DCD IntDefaultHandler ; Timer 7 sub - timer A - 200 000001D4 00000000 DCD IntDefaultHandler ; Timer 7 sub - timer B - 201 000001D8 00000000 DCD IntDefaultHandler ; I2C6 Master - and Slave - 202 000001DC 00000000 DCD IntDefaultHandler ; I2C7 Master - and Slave - 203 000001E0 00000000 DCD IntDefaultHandler ; HIM Scan Ma - trix Keyboard 0 - 204 000001E4 00000000 DCD IntDefaultHandler ; One Wire 0 - 205 000001E8 00000000 DCD IntDefaultHandler ; HIM PS/2 0 - 206 000001EC 00000000 DCD IntDefaultHandler ; HIM LED Seq - uencer 0 - 207 000001F0 00000000 DCD IntDefaultHandler - ; HIM Consumer IR 0 - - 208 000001F4 00000000 DCD IntDefaultHandler ; I2C8 Master - and Slave - 209 000001F8 00000000 DCD IntDefaultHandler ; I2C9 Master - and Slave - 210 000001FC 00000000 DCD IntDefaultHandler ; GPIO Port T - - 211 00000200 - 212 00000200 ;******************************************************* - *********************** - 213 00000200 ; - 214 00000200 ; This is the code that gets called when the processor f - irst starts execution - - - -ARM Macro Assembler Page 7 - - - 215 00000200 ; following a reset event. - 216 00000200 ; - 217 00000200 ;******************************************************* - *********************** - 218 00000200 EXPORT Reset_Handler - 219 00000200 Reset_Handler - 220 00000200 ; - 221 00000200 ; Enable the floating-point unit. This must be done her - e to handle the - 222 00000200 ; case where main() uses floating-point and the function - prologue saves - 223 00000200 ; floating-point registers (which will fault if floating - -point is not - 224 00000200 ; enabled). Any configuration of the floating-point uni - t using - 225 00000200 ; DriverLib APIs must be done here prior to the floating - -point unit - 226 00000200 ; being enabled. - 227 00000200 ; - 228 00000200 ; Note that this does not use DriverLib since it might n - ot be included - 229 00000200 ; in this project. - 230 00000200 ; - 231 00000200 F64E 5088 MOVW R0, #0xED88 - 232 00000204 F2CE 0000 MOVT R0, #0xE000 - 233 00000208 6801 LDR R1, [R0] - 234 0000020A F441 0170 ORR R1, #0x00F00000 - 235 0000020E 6001 STR R1, [R0] - 236 00000210 - 237 00000210 ; - 238 00000210 ; Call the C library enty point that handles startup. T - his will copy - 239 00000210 ; the .data section initializers from flash to SRAM and - zero fill the - 240 00000210 ; .bss section. - 241 00000210 ; - 242 00000210 IMPORT __main - 243 00000210 F7FF BFFE B __main - 244 00000214 - 245 00000214 ;******************************************************* - *********************** - 246 00000214 ; - 247 00000214 ; This is the code that gets called when the processor r - eceives a NMI. This - 248 00000214 ; simply enters an infinite loop, preserving the system - state for examination - 249 00000214 ; by a debugger. - 250 00000214 ; - 251 00000214 ;******************************************************* - *********************** - 252 00000214 NmiSR - 253 00000214 E7FE B NmiSR - 254 00000216 - 255 00000216 ;******************************************************* - *********************** - 256 00000216 ; - 257 00000216 ; This is the code that gets called when the processor r - eceives a fault - 258 00000216 ; interrupt. This simply enters an infinite loop, prese - - - -ARM Macro Assembler Page 8 - - - rving the system state - 259 00000216 ; for examination by a debugger. - 260 00000216 ; - 261 00000216 ;******************************************************* - *********************** - 262 00000216 FaultISR - 263 00000216 E7FE B FaultISR - 264 00000218 - 265 00000218 ;******************************************************* - *********************** - 266 00000218 ; - 267 00000218 ; This is the code that gets called when the processor r - eceives an unexpected - 268 00000218 ; interrupt. This simply enters an infinite loop, prese - rving the system state - 269 00000218 ; for examination by a debugger. - 270 00000218 ; - 271 00000218 ;******************************************************* - *********************** - 272 00000218 IntDefaultHandler - 273 00000218 E7FE B IntDefaultHandler - 274 0000021A - 275 0000021A ;******************************************************* - *********************** - 276 0000021A ; - 277 0000021A ; Make sure the end of this section is aligned. - 278 0000021A ; - 279 0000021A ;******************************************************* - *********************** - 280 0000021A 00 00 ALIGN - 281 0000021C - 282 0000021C ;******************************************************* - *********************** - 283 0000021C ; - 284 0000021C ; Some code in the normal code section for initializing - the heap and stack. - 285 0000021C ; - 286 0000021C ;******************************************************* - *********************** - 287 0000021C AREA |.text|, CODE, READONLY - 288 00000000 - 289 00000000 ;******************************************************* - *********************** - 290 00000000 ; - 291 00000000 ; The function expected of the C library startup code fo - r defining the stack - 292 00000000 ; and heap memory locations. For the C library version - of the startup code, - 293 00000000 ; provide this function so that the C library initializa - tion code can find out - 294 00000000 ; the location of the stack and heap. - 295 00000000 ; - 296 00000000 ;******************************************************* - *********************** - 297 00000000 IF :DEF: __MICROLIB - 302 00000000 IMPORT __use_two_region_memory - 303 00000000 EXPORT __user_initial_stackheap - 304 00000000 __user_initial_stackheap - 305 00000000 4802 LDR R0, =HeapMem - - - -ARM Macro Assembler Page 9 - - - 306 00000002 4903 LDR R1, =(StackMem + Stack) - 307 00000004 4A01 LDR R2, =(HeapMem + Heap) - 308 00000006 4B03 LDR R3, =StackMem - 309 00000008 4770 BX LR - 310 0000000A ENDIF - 311 0000000A - 312 0000000A ;******************************************************* - *********************** - 313 0000000A ; - 314 0000000A ; Make sure the end of this section is aligned. - 315 0000000A ; - 316 0000000A ;******************************************************* - *********************** - 317 0000000A 00 00 ALIGN - 318 0000000C - 319 0000000C ;******************************************************* - *********************** - 320 0000000C ; - 321 0000000C ; Tell the assembler that we're done. - 322 0000000C ; - 323 0000000C ;******************************************************* - *********************** - 324 0000000C END - 00000000 - 00000200 - 00000000 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp --apcs=int -erwork --depend=.\build\startup_rvmdk.d -o.\build\startup_rvmdk.o -IC:\Users\zy -lww\Documents\Study\CodeHub\rt-thread\bsp\tm4c129x-dk\RTE -IC:\Software\Keil\AR -M\PACK\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C129 -IC:\Software\Keil\ARM\CMSIS\ -Include --predefine="__UVISION_VERSION SETA 521" --predefine="TM4C129XNCZAD SET -A 1" --list=.\startup_rvmdk.lst libraries/startup/startup_rvmdk.S - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -STACK 00000000 - -Symbol: STACK - Definitions - At line 45 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: STACK unused -StackMem 00000000 - -Symbol: StackMem - Definitions - At line 46 in file libraries/startup/startup_rvmdk.S - Uses - At line 83 in file libraries/startup/startup_rvmdk.S - At line 306 in file libraries/startup/startup_rvmdk.S - At line 308 in file libraries/startup/startup_rvmdk.S - -__initial_sp 00000200 - -Symbol: __initial_sp - Definitions - At line 48 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: __initial_sp unused -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -HEAP 00000000 - -Symbol: HEAP - Definitions - At line 55 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: HEAP unused -HeapMem 00000000 - -Symbol: HeapMem - Definitions - At line 57 in file libraries/startup/startup_rvmdk.S - Uses - At line 305 in file libraries/startup/startup_rvmdk.S - At line 307 in file libraries/startup/startup_rvmdk.S - -__heap_base 00000000 - -Symbol: __heap_base - Definitions - At line 56 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: __heap_base unused -__heap_limit 00000000 - -Symbol: __heap_limit - Definitions - At line 59 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: __heap_limit unused -4 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -FaultISR 00000216 - -Symbol: FaultISR - Definitions - At line 262 in file libraries/startup/startup_rvmdk.S - Uses - At line 86 in file libraries/startup/startup_rvmdk.S - At line 263 in file libraries/startup/startup_rvmdk.S - -IntDefaultHandler 00000218 - -Symbol: IntDefaultHandler - Definitions - At line 272 in file libraries/startup/startup_rvmdk.S - Uses - At line 87 in file libraries/startup/startup_rvmdk.S - At line 88 in file libraries/startup/startup_rvmdk.S - At line 89 in file libraries/startup/startup_rvmdk.S - At line 94 in file libraries/startup/startup_rvmdk.S - At line 95 in file libraries/startup/startup_rvmdk.S - At line 97 in file libraries/startup/startup_rvmdk.S - At line 98 in file libraries/startup/startup_rvmdk.S - At line 99 in file libraries/startup/startup_rvmdk.S - At line 100 in file libraries/startup/startup_rvmdk.S - At line 101 in file libraries/startup/startup_rvmdk.S - At line 102 in file libraries/startup/startup_rvmdk.S - At line 103 in file libraries/startup/startup_rvmdk.S - At line 104 in file libraries/startup/startup_rvmdk.S - At line 105 in file libraries/startup/startup_rvmdk.S - At line 106 in file libraries/startup/startup_rvmdk.S - At line 107 in file libraries/startup/startup_rvmdk.S - At line 108 in file libraries/startup/startup_rvmdk.S - At line 109 in file libraries/startup/startup_rvmdk.S - At line 110 in file libraries/startup/startup_rvmdk.S - At line 111 in file libraries/startup/startup_rvmdk.S - At line 112 in file libraries/startup/startup_rvmdk.S - At line 113 in file libraries/startup/startup_rvmdk.S - At line 114 in file libraries/startup/startup_rvmdk.S - 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At line 133 in file libraries/startup/startup_rvmdk.S - At line 134 in file libraries/startup/startup_rvmdk.S - At line 135 in file libraries/startup/startup_rvmdk.S - - - -ARM Macro Assembler Page 2 Alphabetic symbol ordering -Relocatable symbols - - At line 136 in file libraries/startup/startup_rvmdk.S - At line 137 in file libraries/startup/startup_rvmdk.S - At line 138 in file libraries/startup/startup_rvmdk.S - At line 139 in file libraries/startup/startup_rvmdk.S - At line 140 in file libraries/startup/startup_rvmdk.S - At line 141 in file libraries/startup/startup_rvmdk.S - At line 142 in file libraries/startup/startup_rvmdk.S - At line 143 in file libraries/startup/startup_rvmdk.S - At line 144 in file libraries/startup/startup_rvmdk.S - At line 145 in file libraries/startup/startup_rvmdk.S - At line 146 in file libraries/startup/startup_rvmdk.S - At line 147 in file libraries/startup/startup_rvmdk.S - At line 148 in file libraries/startup/startup_rvmdk.S - At line 149 in file libraries/startup/startup_rvmdk.S - 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At line 189 in file libraries/startup/startup_rvmdk.S - At line 190 in file libraries/startup/startup_rvmdk.S - At line 191 in file libraries/startup/startup_rvmdk.S - At line 192 in file libraries/startup/startup_rvmdk.S - At line 193 in file libraries/startup/startup_rvmdk.S - At line 194 in file libraries/startup/startup_rvmdk.S - At line 195 in file libraries/startup/startup_rvmdk.S - At line 196 in file libraries/startup/startup_rvmdk.S - At line 197 in file libraries/startup/startup_rvmdk.S - - - -ARM Macro Assembler Page 3 Alphabetic symbol ordering -Relocatable symbols - - At line 198 in file libraries/startup/startup_rvmdk.S - At line 199 in file libraries/startup/startup_rvmdk.S - At line 200 in file libraries/startup/startup_rvmdk.S - At line 201 in file libraries/startup/startup_rvmdk.S - At line 202 in file libraries/startup/startup_rvmdk.S - At line 203 in file libraries/startup/startup_rvmdk.S - At line 204 in file libraries/startup/startup_rvmdk.S - At line 205 in file libraries/startup/startup_rvmdk.S - At line 206 in file libraries/startup/startup_rvmdk.S - At line 207 in file libraries/startup/startup_rvmdk.S - At line 208 in file libraries/startup/startup_rvmdk.S - At line 209 in file libraries/startup/startup_rvmdk.S - At line 210 in file libraries/startup/startup_rvmdk.S - At line 273 in file libraries/startup/startup_rvmdk.S - -NmiSR 00000214 - -Symbol: NmiSR - Definitions - At line 252 in file libraries/startup/startup_rvmdk.S - Uses - At line 85 in file libraries/startup/startup_rvmdk.S - At line 253 in file libraries/startup/startup_rvmdk.S - -RESET 00000000 - -Symbol: RESET - Definitions - At line 73 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: RESET unused -Reset_Handler 00000200 - -Symbol: Reset_Handler - Definitions - At line 219 in file libraries/startup/startup_rvmdk.S - Uses - At line 84 in file libraries/startup/startup_rvmdk.S - At line 218 in file libraries/startup/startup_rvmdk.S - -__Vectors 00000000 - -Symbol: __Vectors - Definitions - At line 82 in file libraries/startup/startup_rvmdk.S - Uses - At line 81 in file libraries/startup/startup_rvmdk.S -Comment: __Vectors used once -6 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -.text 00000000 - -Symbol: .text - Definitions - At line 287 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: .text unused -__user_initial_stackheap 00000000 - -Symbol: __user_initial_stackheap - Definitions - At line 304 in file libraries/startup/startup_rvmdk.S - Uses - At line 303 in file libraries/startup/startup_rvmdk.S -Comment: __user_initial_stackheap used once -2 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Absolute symbols - -Heap 00000000 - -Symbol: Heap - Definitions - At line 38 in file libraries/startup/startup_rvmdk.S - Uses - At line 58 in file libraries/startup/startup_rvmdk.S - At line 307 in file libraries/startup/startup_rvmdk.S - -Stack 00000200 - -Symbol: Stack - Definitions - At line 31 in file libraries/startup/startup_rvmdk.S - Uses - At line 47 in file libraries/startup/startup_rvmdk.S - At line 83 in file libraries/startup/startup_rvmdk.S - At line 306 in file libraries/startup/startup_rvmdk.S - -2 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -External symbols - -__main 00000000 - -Symbol: __main - Definitions - At line 242 in file libraries/startup/startup_rvmdk.S - Uses - At line 243 in file libraries/startup/startup_rvmdk.S -Comment: __main used once -__use_two_region_memory 00000000 - -Symbol: __use_two_region_memory - Definitions - At line 302 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: __use_two_region_memory unused -2 symbols -356 symbols in table diff --git a/bsp/tm4c129x-dk/template.ewp b/bsp/tm4c129x-dk/template.ewp deleted file mode 100644 index 97696050b618e1c9fde229b38b39125f738c0889..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/template.ewp +++ /dev/null @@ -1,1889 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 22 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - - diff --git a/bsp/tm4c129x-dk/template.eww b/bsp/tm4c129x-dk/template.eww deleted file mode 100644 index bd036bb4c98c1598f04b85f64b0dff37f6ec6028..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/template.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\template.ewp - - - - - diff --git a/bsp/tm4c129x-dk/template.uvproj b/bsp/tm4c129x-dk/template.uvproj deleted file mode 100644 index 342711d8becf303f8f6ef8f866df48bf593d4a25..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/template.uvproj +++ /dev/null @@ -1,411 +0,0 @@ - - - - 1.1 - -
### uVision Project, (C) Keil Software
- - - - RT-Thread TM4C129X - 0x4 - ARM-ADS - - - TM4C1294NCPDT - Texas Instruments - Keil.TM4C_DFP.1.0.0 - http://www.keil.com/pack/ - IROM(0x00000000,0x100000) IRAM(0x20000000,0x040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(120000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C129_1024 -FS00 -FL0100000 -FP0($$Device:TM4C1294NCPDT$Flash\TM4C129_1024.FLM)) - 7088 - $$Device:TM4C1294NCPDT$Device\Include\TM4C129\TM4C129.h - - - - - - - -DTM4C1294NCPDT - - - $$Device:TM4C1294NCPDT$SVD\TM4C129\TM4C1294NCPDT.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-tm4c - 1 - 0 - 0 - 1 - 1 - .\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x40000 - - - 1 - 0x0 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x100000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x40000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x00000000 - - tm4c_rom.sct - - - - - - - - - - - - diff --git a/bsp/tm4c129x-dk/tm4c_rom.icf b/bsp/tm4c129x-dk/tm4c_rom.icf deleted file mode 100644 index 4bda7a154a4612fa8614cdb2ab52b9943fe26eb0..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/tm4c_rom.icf +++ /dev/null @@ -1,87 +0,0 @@ -//***************************************************************************** -// -// tm4c_room.icf - Linker configuration file for RT-Thread BSP. -// -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Texas Instruments (TI) is supplying this software for use solely and -// exclusively on TI's microcontroller products. The software is owned by -// TI and/or its suppliers, and is protected under applicable copyright -// laws. You may not combine this software with "viral" open-source -// software in order to form a larger program. -// -// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -// DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. -// -//***************************************************************************** - -// -// Define a memory region that covers the entire 4 GB addressible space of the -// processor. -// -define memory mem with size = 4G; - -// -// Define a region for the on-chip flash. -// -define region FLASH = mem:[from 0x00000000 to 0x000fffff]; - -// -// Define a region for the on-chip SRAM. -// -define region SRAM = mem:[from 0x20000000 to 0x2003ffff]; - -// -// Define a block for the heap. The size should be set to something other -// than zero if things in the C library that require the heap are used. -// -define block HEAP with alignment = 8, size = 0x00000000 { }; - -// -// Define a block for RT-Thread components initialization -// -define block RTT_INIT_FUNC with fixed order { readonly section .rti_fn* }; - -// -// Indicate that the read/write values should be initialized by copying from -// flash. -// -initialize by copy { readwrite }; - -// -// Indicate that the noinit values should be left alone. This includes the -// stack, which if initialized will destroy the return address from the -// initialization code, causing the processor to branch to zero and fault. -// -do not initialize { section .noinit }; - -// -// Place the interrupt vectors at the start of flash. -// -place at start of FLASH { readonly section .intvec }; - -// -// Place the remainder of the read-only items into flash. -// -place in FLASH { readonly, block RTT_INIT_FUNC }; - -// -// Place the RAM vector table at the start of SRAM. -// -place at start of SRAM { section VTABLE }; - -// -// Place all read/write items into SRAM. -// -place in SRAM { readwrite, block HEAP }; - -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; \ No newline at end of file diff --git a/bsp/tm4c129x-dk/tm4c_rom.ld b/bsp/tm4c129x-dk/tm4c_rom.ld deleted file mode 100644 index 7b266ed519690f9f185702b458b38935496bdd18..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/tm4c_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * - * blinky.ld - Linker configuration file for blinky. - * - * Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. - * Software License Agreement - * - * Texas Instruments (TI) is supplying this software for use solely and - * exclusively on TI's microcontroller products. The software is owned by - * TI and/or its suppliers, and is protected under applicable copyright - * laws. You may not combine this software with "viral" open-source - * software in order to form a larger program. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. - * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT - * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY - * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL - * DAMAGES, FOR ANY REASON WHATSOEVER. - * - * This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. - * - *****************************************************************************/ - -MEMORY -{ - CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 - DATA (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 -} - -ENTRY(ResetISR) -_system_stack_size = 0x200; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - PROVIDE(__ctors_start__ = .); - /* old GCC version uses .ctors */ - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - /* new GCC version uses .init_array */ - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(4); - _etext = .; - } > CODE = 0 - - .ARM.extab : - { - *(.ARM.extab*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - - /* .data section which is used for initialized data */ - .data : AT (_sidata) - { - . = ALIGN(4); - PROVIDE(__dtors_start__ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(__dtors_end__ = .); - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } > DATA - - .stack : - { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >DATA - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - *(.bss.init) - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/tm4c129x-dk/tm4c_rom.sct b/bsp/tm4c129x-dk/tm4c_rom.sct deleted file mode 100644 index 9162ff8c44f7ec2a80c2f8ad2520e3bff89419b3..0000000000000000000000000000000000000000 --- a/bsp/tm4c129x-dk/tm4c_rom.sct +++ /dev/null @@ -1,47 +0,0 @@ -;****************************************************************************** -; -; blinky.sct - Linker configuration file for blinky. -; -; Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -; Software License Agreement -; -; Texas Instruments (TI) is supplying this software for use solely and -; exclusively on TI's microcontroller products. The software is owned by -; TI and/or its suppliers, and is protected under applicable copyright -; laws. You may not combine this software with "viral" open-source -; software in order to form a larger program. -; -; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -; DAMAGES, FOR ANY REASON WHATSOEVER. -; -; This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. -; -;****************************************************************************** - -LR_IROM 0x00000000 0x00100000 -{ - ; - ; Specify the Execution Address of the code and the size. - ; - ER_IROM 0x00000000 0x00100000 - { - *.o (RESET, +First) - * (InRoot$$Sections, +RO) - } - - ; - ; Specify the Execution Address of the data area. - ; - RW_IRAM 0x20000000 0x00040000 - { - ; - ; Uncomment the following line in order to use IntRegister(). - ; - ;* (vtable, +First) - * (+RW, +ZI) - } -}