diff --git a/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld b/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld
index b0178bdcdd177eb13714aaf7719d6e13fccc4820..b8c229ae3cc7681902fc706b48ec7d4a1bb8f503 100644
--- a/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld
+++ b/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld
@@ -53,8 +53,8 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
 /* Specify the memory areas */
 MEMORY
 {
-  m_boot_data           (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00000400
-  m_image_vertor_table  (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00000400
+  m_boot_data           (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
+  m_image_vertor_table  (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
 
   m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
   m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00
@@ -72,12 +72,14 @@ SECTIONS
 {
   .boot_data :
   {
-    KEEP(*(.bootdata))
+    KEEP(*(.boot_hdr.conf))
   } > m_boot_data
 
   .image_vertor_table :
   {
-    KEEP(*(.ivt))
+    KEEP(*(.boot_hdr.ivt))
+    KEEP(*(.boot_hdr.boot_data))
+    KEEP(*(.boot_hdr.dcd_data))
   } > m_image_vertor_table
 
   /* The startup code goes first into internal RAM */
diff --git a/bsp/stm32f10x-HAL/drivers/board.c b/bsp/stm32f10x-HAL/drivers/board.c
index d520411984f7c2ae9c677cae6ad7d6c3ee9cec0c..12d5b7d80f0547d289baa95812ea0339a908b878 100644
--- a/bsp/stm32f10x-HAL/drivers/board.c
+++ b/bsp/stm32f10x-HAL/drivers/board.c
@@ -49,6 +49,7 @@ void HAL_MspInit(void)
 
 void SystemClock_Config(void)
 {
+    rt_err_t result;
     RCC_OscInitTypeDef RCC_OscInitStruct;
     RCC_ClkInitTypeDef RCC_ClkInitStruct;
     /**Initializes the CPU, AHB and APB busses clocks
@@ -60,7 +61,8 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
     RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
-    RT_ASSERT(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK);
+    result = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+    RT_ASSERT(result == HAL_OK);
     /**Initializes the CPU, AHB and APB busses clocks
       */
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
@@ -68,7 +70,8 @@ void SystemClock_Config(void)
     RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-    RT_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK);
+    result = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+    RT_ASSERT(result == HAL_OK);
     /**Configure the Systick interrupt time
       */
     HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
diff --git a/bsp/stm32f10x-HAL/drivers/drv_usart.c b/bsp/stm32f10x-HAL/drivers/drv_usart.c
index 80bf5578d870ccff0fdc18b59db9e46149e407db..771f4d62a1cd6c5b3a90891c49bf41505c17ab64 100644
--- a/bsp/stm32f10x-HAL/drivers/drv_usart.c
+++ b/bsp/stm32f10x-HAL/drivers/drv_usart.c
@@ -267,6 +267,7 @@ INIT_BOARD_EXPORT(rt_hw_usart_init);
 
 static void MX_USART_UART_Init(UART_HandleTypeDef *uartHandle)
 {
+    rt_err_t result;
     uartHandle->Init.BaudRate = 115200;
     uartHandle->Init.WordLength = UART_WORDLENGTH_8B;
     uartHandle->Init.StopBits = UART_STOPBITS_1;
@@ -274,7 +275,8 @@ static void MX_USART_UART_Init(UART_HandleTypeDef *uartHandle)
     uartHandle->Init.Mode = UART_MODE_TX_RX;
     uartHandle->Init.HwFlowCtl = UART_HWCONTROL_NONE;
     uartHandle->Init.OverSampling = UART_OVERSAMPLING_16;
-    RT_ASSERT(HAL_UART_Init(uartHandle) == HAL_OK);
+    result = HAL_UART_Init(uartHandle);
+    RT_ASSERT(result == HAL_OK);
 
 }
 /* USART2 init function */